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Hardware and Edge Computing

GiZano edited this page Aug 5, 2026 · 1 revision

Hardware & Edge Computing (ESP32-C3)

The edge layer operates on resource-constrained microcontrollers, specifically the ESP32-C3 SuperMini (RISC-V architecture).

Hardware Configuration

Due to the specific physical layout, the I2C bus is software-mapped to non-standard GPIO pins:

  • SDA (Data): GPIO 7 (requires internal pull-up).
  • SCL (Clock): GPIO 8 (requires internal pull-up).
  • Power: The ADXL345 is powered strictly via the 3.3V rail.

The sensor operates at a 100Hz sampling rate (ADXL345_DATARATE_100_HZ) with a measurement range of ±16G.

Digital Signal Processing (DSP) Pipeline

  • High-Pass Filter (HPF): A digital filter (HPF_ALPHA = 0.9f) isolates dynamic vibration data by subtracting the static DC component (Earth's gravity).
  • Noise Gate: Micro-vibrations below the empirical threshold of 0.04G are clamped to zero to prevent false positives from electrical noise.
  • Dropout Protection: The firmware automatically drops frames reporting near-zero absolute acceleration (< 2.0 $m/s^2$ prior to filtering), mitigating corrupted readings from I2C disconnects.

STA/LTA Seismic Detection Algorithm

The implementation utilizes a custom, memory-efficient RingBuffer template class in C++ to maintain rolling sums for $O(1)$ average calculations:

  • Short-Term Window (STA): 100 samples (1 second).
  • Long-Term Window (LTA): 1000 samples (10 seconds).
  • Trigger Condition: An earthquake is registered when the STA/LTA ratio exceeds 1.8f, provided the STA absolute value is above the noise floor.

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