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CUDA/HIP: VALU cross-lane ops for partial-top-k shuffles (~1.06-1.10x, follow-up to #15)#16

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DeanoC merged 1 commit into
feat/hip-topk-argsortfrom
feat/topk-valu-crosslane
Jul 10, 2026
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CUDA/HIP: VALU cross-lane ops for partial-top-k shuffles (~1.06-1.10x, follow-up to #15)#16
DeanoC merged 1 commit into
feat/hip-topk-argsortfrom
feat/topk-valu-crosslane

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@DeanoC

@DeanoC DeanoC commented Jul 10, 2026

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Draft — follow-up to #15, stacked on its branch (feat/hip-topk-argsort), so the diff below is only this change. Found by our kernel optimizer on top of #15's partial-bitonic; kept separate so #15 stays a clean, self-contained win.

What

The partial-bitonic top-k's intra-wave xor shuffles were all issuing through the LDS permute crossbar (ds_swizzle_b32 / ds_bpermute_b32). Move the ones expressible as pure VALU cross-lane gathers off the crossbar onto the ALU pipe, shortening the dependent shuffle chains these latency-bound kernels sit on:

  • xor ^1 / ^2 (intra-quad) → DPP mov_dpp quad_perm (0xB1 / 0x4E)
  • xor ^16 (widest intra-wave stride, entry stage of every 32-lane chain) → v_permlanex16_b32 (identity-cross form)
  • ^4 / ^8 stay on ds_swizzle_b32; the wave64 j==32 tail falls back to __shfl_xor
  • plus a middle-cross-wave-stride group-merge fuse in the shared/2wave Phase-A/B

Comparator/merge networks are byte-identical → the produced top-k set is bit-identical.

Impact (test-backend-ops perf -o TOP_K, ne=[1000,16], vs #15's partial-bitonic)

k gfx1201 (R9700) gfx1151 (Strix Halo)
1 3.91 → 3.62 µs (1.08×) 2.53 → 2.24 µs (1.13×)
10 4.99 → 4.69 µs (1.06×) 3.70 → 3.41 µs (1.09×)
40 5.51 → 5.32 µs (1.04×) 4.28 → 4.11 µs (1.04×)
400 6.32 → 5.91 µs (1.07×) 5.21 → 4.53 µs (1.15×)

Geomean ~1.06× (gfx1201) / ~1.10× (gfx1151) on top of #15.

Validation

  • All DPP quad_perm / permlanex16 / ds_swizzle encodings verified bit-identical to __shfl_xor on gfx1201 and gfx1151 (on-device probe + the test gate).
  • test-backend-ops test -o TOP_K: 2/2 backends passed, 0 fail, on both archs.
  • Perf measured with interleaved-A/B rebuilds (per-variant libggml-hip.so swap) to cancel warm-drift.

Notes

Draft because it's incremental polish on already-diminishing returns (the optimizer plateaued for 15 iterations after this) — merge #15 first; this can follow. Same-arch dependency: nothing new (pure ISA-level shuffle lowering).

…~1.06-1.10x)

Follow-up tuning of the partial-bitonic top-k, correctness-preserving (comparator/
merge networks byte-identical -> bit-exact TOP_K set), validated with interleaved
A/B rebuilds on gfx1201 and gfx1151.

The intra-wave xor shuffles were issuing through the LDS permute crossbar
(ds_swizzle_b32 / ds_bpermute_b32). Move the ones expressible as pure VALU
cross-lane gathers off the crossbar onto the ALU pipe, shortening the dependent
shuffle chains these latency-bound kernels sit on:

  * xor ^1 / ^2 (intra-quad) -> DPP mov_dpp quad_perm (0xB1 / 0x4E).
  * xor ^16 (widest intra-wave stride, entry stage of every 32-lane chain) ->
    v_permlanex16_b32 in its identity-cross form.
  * ^4 / ^8 stay on ds_swizzle_b32; the wave64 j==32 tail falls back to __shfl_xor.
  * plus a middle-cross-wave-stride group-merge fuse in the shared/2wave Phase-A/B.

All cross-lane encodings verified bit-identical to __shfl_xor on gfx1201 and
gfx1151. test-backend-ops -o TOP_K: 0 fail on both archs. Perf (ne=[1000,16],
geomean over k=1/10/40/400 vs the prior partial-bitonic): gfx1201 ~1.06x,
gfx1151 ~1.10x (k=1 and k=400 gain most: gfx1151 1.13x / 1.15x).
@DeanoC

DeanoC commented Jul 10, 2026

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Folded into #15 — the VALU commit was fast-forwarded onto #15's branch (feat/hip-topk-argsort), so GitHub auto-marked this merged. The ~+0.5% e2e is included in #15's combined microbench + DSpark e2e numbers. No separate PR needed.

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