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Generate a key-value prop-dict printer that dispatches each field to its ODS printer while retaining attribute conversion for non-compositional default parsers. Keep operation-specific property printer hooks ahead of the generated implementation and preserve legacy input compatibility. See #155475 Assisted-by: Codex
Do not apply SplitDelinearizeSpanningLastLinearizeArg when the split would consume an entire outer-bounded basis. Rewriting that case can discard earlier linearization inputs and previously built an invalid zero-result prefix operation. Assisted-by: Codex
Enable the strict properties assembly format mode for the Math dialect. Spell the classification fast-math attribute in the declarative format so it is not parsed from attr-dict in strict mode. Assisted-by: Codex
POSIX defines confstr as returning strings for various macros (see: https://pubs.opengroup.org/onlinepubs/9799919799/functions/confstr.html) This PR adds an implementation as experimental that always returns that there's no valid string. Assisted-by: Automated tooling, human reviewed.
Represent OpenCL C and C++ for OpenCL source languages in CIR module attributes. Emit the source language from CIRGen so later lowering can distinguish OpenCL language modes without reconstructing them from target metadata. Assisted-by: Codex / GPT-5.6 Sol
…218557) * Check for valid alignment when parsing common symbols (also for data symbols) * lld: Use uint32 for size field, matching similar class in in this file * Add support for COMMON in YAML emitter for tests
…arkers" (#218804) Reverts #191909 This is causing downstream issues for Google as well as ROCm. Reverting for now. CC: @ronlieb @isoard-amd @rupprecht
### summary Part of : #185382 This is a light patch and a follow up of : #205508 All lowering logic have been implemented in this PR : #204285 , I just need to migrate these intrinsics. Migrate the 6 test_vmovl_high_{s,u}{8,16,32} tests from neon-intrinsics.c to widen.c with LLVM + CIR checks, and drop the now-stale TODO in widen.c. This PR completed with the assistance of DeepSeek
Visit inherent attributes directly from operation property storage. Allow visitors to replace values through generated property conversions. Keep populateInherentAttrs as a wrapper and migrate core IR callers. This is intended as a more efficient than populateInherentAttrs that avoids materializing the list. Assisted-by: Codex
Add handling of `llvm.dx.resource.handlefromheap` to `DXILRemoveUnusedResources` pass. In practice heap resources are usually assigned to local variables, and get cleaned up in earlier passes if unused. If that does not happen for some reason, they get removed by `DXILRemoveUnusedResources`. Related to #208053
…7991) Accurate BTF types for DW_CC_nocall functions were added in [1] and work at -O2. At -O1 the entry block keeps debug locations that -O2 optimizes away, and two of those patterns defeat the argument-register scan. Accurate signatures are worth having at -O1 too: transformations move between optimization levels over time, and some users build at -O1. collectNocallEntryArgRegs() scans the entry block for DBG_VALUEs to find which physical register each source argument arrived in. An argument may have several DBG_VALUEs there, and the map was last-write-wins, so a later location silently replaced the entry one. The registers then no longer match the optimized IR signature, canUseNocallOptimizedSignature() bails, and BTFDebug emits the unfiltered source prototype -- a FUNC_PROTO that does not describe the real ABI. The first pattern is a spilled argument. From progs/test_l4lb_noinline_dynptr.c in the kernel BPF selftests, with the stack stores elided: bb.0 (%ir-block.4): liveins: $r1, $r2, $r4, $w3 DBG_VALUE $w3, $noreg, !"is_ipv6", !DIExpression(DW_OP_LLVM_convert, 1, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_stack_value) ... STW32 $w3, $r10, -184 DBG_VALUE $r10, $noreg, !"is_ipv6", !DIExpression(DW_OP_constu, 184, DW_OP_minus, DW_OP_deref_size, 4, DW_OP_LLVM_convert, 1, DW_ATE_unsigned, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_stack_value) JEQ_ri_32 killed $w3, 0, %bb.9 "is_ipv6" arrives in $w3 and is spilled, after which the register allocator emits a second DBG_VALUE for the spill slot. It is not indirect -- the offset operand is $noreg, not an immediate -- so isIndirectDebugValue() does not reject it, and $r10 is the frame pointer, never redefined in the entry block, so the DefinedRegs check does not either. It replaced $w3 with $r10 and the DWARF register order check then failed. The second pattern is an argument reassigned from another argument: bb.0 (%ir-block.5): liveins: $r1, $r2, $r3, $r4, $r5 DBG_VALUE $r1, $noreg, !"a", !DIExpression() ... DBG_VALUE $r5, $noreg, !"e", !DIExpression() $r1 = nsw MUL_ri killed $r1(tied-def 0), 3 DBG_VALUE $r5, $noreg, !"a", !DIExpression() The last DBG_VALUE describes "a" after an assignment "a = e". Entry locations are keyed by source argument number, so it overwrote "a"'s entry location $r1 with $r5. $r5 is a live-in the entry block never redefines, so DefinedRegs does not reject it here either. Fix by recording the first eligible DBG_VALUE for each argument instead of the last: at function entry an argument still sits in its ABI-assigned register, and any later DBG_VALUE describes where it moved to. [1] #198426
…KindFunc. (#218560) We were iterating a std::map that uses a pointer for the key which isn't deterministic. To fix, dereference the pointer and use operator< from the class.
…18564) The PtrAddrSpace field was previously unused and I think it always has been. The AddrSpace field used to be vector, but was made a single value in 8350764. Replace AddrSpace with PtrAddrSpace for clarity. Remove unnecessary conversions to ValueTypeByHwMode to get the pointer address space. The conversion copies the PtrAddrSpace directly from the TypeSetByHwMode without modification.
Assisted-by: Claude
…RefPtr (#218723) Fix a bug that lambda capture checkers were checking for the exact match for "protectedThis" as opposed to any protective smart pointer.
) Add a legalizer rule for G_READCYCLECOUNTER/G_READSTEADYCOUNTER. On RV64 they are legal and select via the existing tablegen Pats (rdcycle/rdtime). On RV32 lower them to the ReadCounterWide target pseudo, which FinalizeISel expands into the re-read-the-high-half loop (emitReadCounterWidePseudo) — the same expansion SelectionDAG uses.
GlobalISel aborted on `llvm.prefetch` ("unable to legalize
`G_PREFETCH`") while SDAG lowers it to `prefetch.r/w/i`. Add a legalizer
rule marking `G_PREFETCH` legal for p0 addresses, and a custom selector
since the SDAG patterns use the `AddrRegImmLsb00000` complex pattern
that the GISel pattern importer does not auto-translate. The selector
picks `prefetch.r/w/i` from the rw/cache-type immediates and folds a
`simm12_lsb00000` offset when present, matching SDAG.
'@', '#', and '?' are assembly identifier characters, but they terminate a macro argument name.
In case it may be zero/sign-extended into an REX/REX2 register. Fixes: #218583 Assisted-by: Claude Opus 4.8
#212533) Clang currently emits command-line implicit inputs such as `-imacros`, `-include-pch`/`-include-pth`, and `-include` as part of the predefines buffer. This causes them to be processed before the main source file. For a C++20 module unit with a global module fragment: ```cpp module; export module M; ``` a force-included header containing declarations was effectively processed as: ```cpp #include "Header.h" module; export module M; ``` This places declarations before the global module fragment introducer and makes the module unit ill-formed. The same problem affects named module units without an explicit GMF, including CUDA compilations that use force-included runtime headers. [Compiler Explorer](https://godbolt.org/z/5Gzdra43c). This change records implicit command-line inputs during preprocessor initialization and determines their placement when entering the main source file: - Ordinary translation units retain the existing behavior by appending the implicit inputs to Predefines. - Module units beginning with `module;` process the inputs immediately after the GMF introducer. - Named module interface and implementation units without a GMF receive a synthesized `module;`, followed by the implicit inputs. --------- Signed-off-by: yronglin <yronglin777@gmail.com>
Related to #185382 CIR lowering for load intrinsics (`vld1_*`/`vld1q_*`) (https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#stride) Port tests: - `clang/test/CodeGen/AArch64/neon-intrinsics.c` - `clang/test/CodeGen/AArch64/neon-ldst-one.c` - `clang/test/CodeGen/AArch64/poly64.c` - `clang/test/CodeGen/arm-neon-vld.c` to `clang/test/CodeGen/AArch64/neon/load.c`
…etvlimax (#218594) The result of `llvm.riscv.vsetvli/vsetvlimax` models VLMAX (or a VL bounded by it) and is only defined for XLen, so the result type must be i32 or i64. Narrower types cannot represent the architectural VLMAX range of [1, 65536] that value analyses rely on. Also check that the VSEW and VLMUL immediate operands encode a valid SEW/LMUL pair (VSEW <= 3, VLMUL != reserved), so that consumers can assume a well-formed vtype. Assisted-by: TRAE CLI (Opus 4.8)
This follows our own CI best practices and ensures zizmor/CodeQL will not complain about this when people inevitably touch it in the future.
Now that 23.1.0 has been released, we should update the container to ensure we're using the latest released version of the tooling.
Make NumLoadsPerBlock control both equality and ordering memcmp expansions. For ordering comparisons, pack consecutive legal loads in memory order into a value no wider than the target preferred load width, then compare the packed values. This preserves lexicographic semantics while reducing conditional branches. BPF uses groups of eight byte-load pairs, so an align-1 32-byte comparison forms four i64 compare blocks instead of 32 byte compare blocks. Other targets retain their existing default ordering behavior unless grouping is explicitly requested. Assisted-by: TRAE CLI (GPT-5)
VLMAX = VLEN * LMUL / SEW is always a non-zero power of two for any valid vtype, so llvm.riscv.vsetvlimax is a power of two regardless of SEW/LMUL or whether a vscale_range is present. Report this in isKnownToBeAPowerOfTwo so that consumers such as ctpop and the x & (x - 1) idiom can fold. Assisted-by: TRAE CLI (Opus 4.8)
For now, epilogue tail-folding is restricted to innermost loops with explicitly forced main and epilogue VFs, where mainVF > epilogueVF. Reject cases requiring a scalar epilogue, cases where the main vector loop is already tail-folded, and early-exit loops.
These got reported in #96270. - Allow "0F B6 44 24 XX : movzx eax, byte ptr [esp + XX]" for x86 and x86_64. - Add "0F B6 4C 24 XX : movzx ecx, byte ptr [esp + XX]" - Add "4F 8D 0C XX : lea r9, [...]" - Add "66 83 3A XX : cmp word ptr [rdx], XX" - Add "85 D2 : test edx, edx" - Add "8D 44 24 XX : lea eax, [esp + XX]" - Add "F3 0F 1E FA : endbr64" - Add "F3 0F 1E FB : endbr32"
…le statement (#219056) In conditions with an empty init statement with attributes such as '([[]];)', the InitStmt pointer argument in the ParseCondition method will be dereferenced. However, InitStmt is set to nullptr when parsing a 'while' statement condition, causing a crash. This change fixes the issue by added a check that InitStmt is not nullptr before entering the associated logic, which is consistent with how other parts of this function handle a nullptr InitStmt. This makes sense because a nullptr InitStmt is associated with conditions that cannot have an init statement (the only case being 'while') and this block operates exclusively on init statements. Fix #218879
…AbiTagLookup (#203984) TestAbiTagLookup.py used `v1` as the inline namespace name. On macOS the dyld shared cache contains two unrelated internal data symbols named `v1` (one in dyld, one in libdyld.dylib). When evaluating `v1::withImplicitTag(...)`, `ClangExpressionDeclMap` resolves `v1` as a namespace correctly, but then still falls through to `SymbolContext::FindBestGlobalDataSymbol`, which finds the two dyld symbols and raises "Multiple internal symbols found for 'v1'", failing the test. Rename the inline namespace to `lldb_test_abi_tag_lookup_inline_ns` so the test no longer collides with anything in dyld. Add a new XFAIL test, namespace_data_symbol_collision, that reproduces the underlying bug deterministically (without depending on `dyld`) by linking two non-debug-info objects that each define a static data symbol whose name matches a real namespace in main.cpp.
Reviewers: Pull Request: #219197
…arization with them (#218980) bdver4/znver1/znver2 have notoriously bad implementations of the PDEP/PEXT scalar instructions - we're much better off keeping vector expansions
Close #218152 This was only reported in windows as MSSTL chose to implement std module by wrapping the STL into extern "C++", which is different from libstdc++ and libc++. But technically this is not specific to windows and we're able to preoduce it in linux although we won't face it in linux.
) Summary: For GPU targets trying to use these checks, it would cause some issues. the RTL function takes a flat pointer, but the global would be generated as AS(1) with no cast. This seemed to work fine, mostly because for AMDGPU the flat and global address spaces are byte identical, but it's broken heavior. It lead to the backend not being able to fully identify the call graph because it was not calling the 'right' function. Just add an address space cast, these are no-ops in the vast majority of cases.
…219153) This simplifies the implementation a bit more and avoids some includes. This is a step towards removing `__libcpp_allocate`.
As anticipated, doing this ends up introducing miscompiles, because we drop provenance captures, as reported at https://discourse.llvm.org/t/scalarevolution-parses-ptrtoint-as-ptrtoaddr-losing-provenance/91675. Now that clang uses ptrtoaddr for pointer subtraction, this workaround should be less relevant.
Attribute target testing was missing a bunch of checks -- this adds them. One test (attr-target-x86-mmx.c) is now redundant. Patch done with usage of claude code --------- Co-authored-by: Simon Pilgrim <llvm-dev@redking.me.uk>
These variables are only used in assertions but are used multiple times/do not make sense to inline, so mark them [[maybe_unused]].
## Problem DWARF permits the operand of `DW_OP_convert` to reference a floating-point base type. LLDB instead stops while resolving such a DIE and reports `unsupported encoding`. This also breaks expressions that only use the float as an intermediate value, such as converting zero to float32 and then back to the generic type. ## Change Carry the base type's DWARF encoding into the expression evaluator so it can distinguish integer and floating-point destinations. Float32, float64, and x87 float80 are mapped to their corresponding `APFloat` semantics. The conversion rules are now: - integer to float and float precision changes use nearest-ties-to-even; - float to integer uses toward-zero; - NaN, integer overflow, unsupported float widths, and impractical integer widths produce evaluation errors. The existing integer truncation and extension behavior, including conversion to the generic address-sized unsigned type, is unchanged. ## Tests Extend `DWARFExpression.DW_OP_convert` with the reported expression and cover 32-, 64-, and 80-bit float targets, precision narrowing, positive and negative toward-zero conversion, NaN and range errors, excessive integer widths, and the existing malformed-DIE paths. Fixes #202605
…214575) fixes #136941 This flag, mirroring DXC, opts into assuming row-major buffer bytes instead, for compatibility with legacy shaders. Outside of the driver change the raw buffers carry no layout metadata, so matrix values loaded/stored via ByteAddressBuffer::Load<T>/Store<T> are ambiguous (native layout is column-major). - New __builtin_hlsl_resource_load_typed/store_typed builtins for the templated ByteAddressBuffer Load<T>/Store<T> overloads - CodeGen transposes matrix values via llvm.matrix.transpose when the flag is set and the target is SPIR-V - Plumb flag from driver -> cc1 -> new LangOpts bit Assisted by Claude Sonnet 5 via CoPilot
…up (#216893) fixes #216888 In the process of testing the scalarization of HLSL long vectors I discoved that some intrinsics were crashing when used with llc but not when used with opt -scalarizer. This change makes sure that we have setup TargetTransformInfoWrapperPass so that we can call the DirectX versions of `isTargetIntrinsicWithScalarOpAtArg` and `isTargetIntrinsicWithOverloadTypeAtArg`. resolves #216191 Because we are also turning off the scalarizer if sm 6.9 Assisted by Copilot with GPT 5.6-Sol
## Summary MIMG instructions with TFE or LWE enabled are now excluded during mergeable candidate collection in `collectMergeableInsts()`, preventing them from ever entering the merge candidate list in `SILoadStoreOptimizer`. ## Problem TFE (Texture Fetch Error) and LWE (Load Word Error) add status-result semantics to image load instructions — the result register includes an additional status word alongside the texture data. The image merge path in `SILoadStoreOptimizer` does not reconstruct or represent these status lanes. The previous eligibility logic in `dmasksCanBeCombined()` only checked the leading instruction (`CI.I`) for TFE/LWE, which allowed the asymmetric ordinary→TFE/LWE ordering to enter the merge path. ## Fix - `collectMergeableInsts()` now skips MIMG instructions with enabled TFE or LWE before they are added to the mergeable candidate list. - Because TFE/LWE instructions never enter the candidate list, both orderings (ordinary→TFE/LWE and TFE/LWE→ordinary) are excluded from pair combination. - No changes were made to `dmasksCanBeCombined()` relative to upstream — its existing `CI.I`-only TFE/LWE check remains as defense-in-depth. - `AMDGPUImageIntrinsicOptimizer` is not part of this change. ## Testing Focused lit tests run with `llvm-lit -sv`: - `llvm/test/CodeGen/AMDGPU/merge-image-load.mir` - `llvm/test/CodeGen/AMDGPU/merge-image-load-gfx10.mir` - `llvm/test/CodeGen/AMDGPU/merge-image-load-gfx11.mir` - `llvm/test/CodeGen/AMDGPU/merge-image-load-gfx12.mir` Coverage matrix (in `merge-image-load.mir`): - **Newly added regressions**: - `image_load_tfe_second_not_merged` — ordinary → TFE: **not merged** (Passed) - `image_load_lwe_second_not_merged` — ordinary → LWE: **not merged** (Passed) - **Pre-existing reverse-order tests**: - `image_load_not_merged_7` — TFE → ordinary: **not merged** (Passed) - `image_load_not_merged_8` — LWE → ordinary: **not merged** (Passed) - **Pre-existing status-free positive merge tests**: - `image_load_merged_v1v3` (and others) — ordinary → ordinary: **merged** (Passed) ## AI tool disclosure AI-assisted tools were used during the investigation, implementation support, and drafting of this change. I personally reviewed and understand the final code and tests, ran the validation listed above, and remain responsible for the contribution. Fixes #187335 Signed-off-by: Yudistira Putra <85178972+Yudis-bit@users.noreply.github.com>
This patch does 2 things: 1. If `ValueObject::CastToBasicType` or `ValueObject::CastToEnumType` return an ValueObject with an error, retrieve the error message and return it as `DILDiagnosticError`. 2. Fix a minor bug in error checking logic in `ValueObject::CastToBasicType`.
…15270) Fix Level Zero memory fills that cannot use `zeCommandListAppendMemoryFill`, such as non-power-of-two patterns. The replication fallback previously submitted a temporary host vector whose lifetime could end before the asynchronous copy completed, which caused unit test failures. This PR changes the replication fallback to simply use `dataSubmit()` + `synchronize()` for the seed upload. The software fill is also moved to L0SyncQueueTy so it's only possible with a synchronous queue. Assisted-by: Codex
These data type combinations were added in arm/tosa-specification#74 --------- Signed-off-by: Ian Tayler Lessa <ian.taylerlessa@arm.com>
The variables are placed together in one entrypoint, as they will be modified together by `tzset()` (and also `ctime()`, `localtime()`, and `mktime()`). For `tzname`, this PR updates hdrgen to handle array types for objects. Assisted-by: Automated tooling, human reviewed.
Support downstream code that assumes `sigev_notify_thread_id`, even though defined for Linux is a macro that expands to use private `struct sigevent` fields.
…xtension (#217946) This is a generalization of the previously existing rule, that required one of the sides of the `setcc` to be zero. With this commit we now support comparisons between any two variables. This requires us to insert an additional instruction to compare the two. But it is still beneficial vs the unoptimized lowering as it reduces 1 instruction in the output. This fixes one of the issues identified in #179584. Namely `test_lt3`, now uses `czero.{nez,eqz}` for those cases. AI Disclosure: I have used AI to help me understand the LLVM build and test system as well as to understand the existing codebase. The new code add in this PR is authored by me.
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