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Fix unregistered transmit output #29

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Merged
cchaine merged 1 commit into from
Dec 27, 2025
Merged

Fix unregistered transmit output #29

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60 changes: 24 additions & 36 deletions config/traceability-matrix.csv
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Original file line number Diff line number Diff line change
Expand Up @@ -87,42 +87,30 @@ tb_rx_frontend.framing.03
tb_tx_frontend.idle.01
tb_tx_frontend.idle.02
tb_tx_frontend.idle.03
tb_tx_frontend.7N1.01
tb_tx_frontend.7N1.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.7N1.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.7N2.01
tb_tx_frontend.7N2.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.7N2.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.7E1.01
tb_tx_frontend.7E1.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.7E1.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.7E2.01
tb_tx_frontend.7E2.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.7E2.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.7O1.01
tb_tx_frontend.7O1.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.7O1.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.7O2.01
tb_tx_frontend.7O2.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.7O2.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.8N1.01
tb_tx_frontend.8N1.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.8N1.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.8N2.01
tb_tx_frontend.8N2.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.8N2.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.8E1.01
tb_tx_frontend.8E1.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.8E1.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.8E2.01
tb_tx_frontend.8E2.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.8E2.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.8O1.01
tb_tx_frontend.8O1.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.8O1.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.8O2.01
tb_tx_frontend.8O2.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.8O2.03;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.7N1.01;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.7N1.02;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.7N2.01;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.7N2.02;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.7E1.01;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.7E1.02;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.7E2.01;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.7E2.02;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.7O1.01;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.7O1.02;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.7O2.01;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.7O2.02;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.8N1.01;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.8N1.02;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.8N2.01;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.8N2.02;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.8E1.01;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.8E1.02;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.8E2.01;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.8E2.02;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.8O1.01;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.8O1.02;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.8O2.01;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.8O2.02;F_UART_02;F_UART_03;F_TRANSMIT_01
tb_tx_frontend.baudrate.01
tb_tx_frontend.baudrate.02;F_UART_01;F_UART_02;F_TRANSMIT_01
tb_tx_frontend.baudrate.03;F_UART_02;F_UART_03;F_TRANSMIT_01
Expand Down
8 changes: 6 additions & 2 deletions src/tx_frontend.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -69,7 +69,7 @@ logic parity_d, parity_q;
/* Output signals */
/*****************************************/

logic uart_tx_d;
logic uart_tx_d, uart_tx_q;

logic done_d, done_q;

Expand Down Expand Up @@ -212,6 +212,8 @@ always_ff @(posedge clk_i) begin
parity_q <= 0;

done_q <= 0;

uart_tx_q <= 1;
end else begin
state_q <= state_d;

Expand All @@ -229,14 +231,16 @@ always_ff @(posedge clk_i) begin

// Asserted to indicate the end of a transmission
done_q <= done_d;

uart_tx_q <= uart_tx_d;
end
end

/*****************************************/
/* Assign output signals */
/*****************************************/

assign uart_tx_o = rst_i ? 1 : uart_tx_d;
assign uart_tx_o = uart_tx_q;
assign done_o = done_q;

endmodule // tx_frontend
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