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Merged
cchaine merged 2 commits into from
Dec 6, 2025
Merged

Use verilator-cmake v1.1.0 #27

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e359a7a
Use verilator-cmake v1.1.0
cchaine Dec 6, 2025
e54ba90
Fix linting issues
cchaine Dec 6, 2025
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2 changes: 1 addition & 1 deletion CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,7 @@ add_dependency(

add_dependency(
GIT ecap5/verilator-cmake
TAG tags/v1.0.1)
TAG release/v1.1.0)

add_dependency(
GIT ecap5/ecap5-treq
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26 changes: 13 additions & 13 deletions src/ecap5_dwbuart.sv
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Expand Up @@ -21,21 +21,21 @@
*/

module ecap5_dwbuart #(
localparam UART_SR = 0,
localparam UART_CR = 1,
localparam UART_RXDR = 2,
localparam UART_TXDR = 3,
localparam logic[2:0] UART_SR = 0,
localparam logic[2:0] UART_CR = 1,
localparam logic[2:0] UART_RXDR = 2,
localparam logic[2:0] UART_TXDR = 3,

// The minimum frame size is :
// - 7 data bits
// - 1 stop bit
localparam MIN_FRAME_SIZE = 8,
localparam logic[3:0] MIN_FRAME_SIZE = 8,

// The maximum frame size is :
// - 8 data bits
// - 1 parity bit
// - 2 stop bit
localparam MAX_FRAME_SIZE = 11
localparam logic[3:0] MAX_FRAME_SIZE = 11
)(
input logic clk_i,
input logic rst_i,
Expand Down Expand Up @@ -169,7 +169,7 @@ always_comb begin : register_access

// Set the data output for read requests
mem_read_data_d = 0;
case(mem_addr[7:2])
case(mem_addr[4:2])
UART_SR: mem_read_data_d = {27'b0, sr_pe_q, sr_fe_q, sr_rxoe_q, sr_txe_q, sr_rxne_q};
UART_CR: mem_read_data_d = {cr_acc_incr_q, 12'b0, cr_ds_q, cr_s_q, cr_p_q};
UART_RXDR: mem_read_data_d = {24'b0, rxdr_rxd_q};
Expand All @@ -178,7 +178,7 @@ always_comb begin : register_access

// Set the register data for write requests
if(mem_write) begin
case(mem_addr[7:2])
case(mem_addr[4:2])
UART_CR: begin
cr_acc_incr_d = mem_write_data[31:16];
cr_ds_d = mem_write_data[3];
Expand All @@ -193,7 +193,7 @@ always_comb begin : register_access
end

// Priority to the memory request
if(mem_write && (mem_addr[7:2] == UART_TXDR)) begin
if(mem_write && (mem_addr[4:2] == UART_TXDR)) begin
sr_txe_d = 0;
end else if (tx_done) begin
sr_txe_d = 1;
Expand All @@ -214,12 +214,12 @@ always_comb begin : register_access
end
// When the memory request occurs but no data was received
// we clear the previously received data
end else if(mem_read && mem_addr[7:2] == UART_RXDR) begin
end else if(mem_read && mem_addr[4:2] == UART_RXDR) begin
rxdr_rxd_d = '0;
sr_rxne_d = 0;
// When the memory request occurs but no data was received
// we clear the errors
end else if(mem_read && mem_addr[7:2] == UART_SR) begin
end else if(mem_read && mem_addr[4:2] == UART_SR) begin
sr_pe_d = 0;
sr_fe_d = 0;
sr_rxoe_d = 0;
Expand All @@ -228,10 +228,10 @@ end

always_comb begin : frontend_interface
// Reset the frontends after either a reset or a write to UART_CR
frontend_rst = rst_i || (mem_write && mem_addr[7:2] == UART_CR);
frontend_rst = rst_i || (mem_write && mem_addr[4:2] == UART_CR);

// Transmit after a write to UART_TXDR
tx_transmit_d = mem_write && (mem_addr[7:2] == UART_TXDR);
tx_transmit_d = mem_write && (mem_addr[4:2] == UART_TXDR);
end

always_ff @(posedge clk_i) begin
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6 changes: 3 additions & 3 deletions src/rx_frontend.sv
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Expand Up @@ -21,8 +21,8 @@
*/

module rx_frontend #(
parameter MIN_FRAME_SIZE = 8,
parameter MAX_FRAME_SIZE = 11
parameter logic[3:0] MIN_FRAME_SIZE = 8,
parameter logic[3:0] MAX_FRAME_SIZE = 11
)(
input logic clk_i,
input logic rst_i,
Expand Down Expand Up @@ -54,7 +54,7 @@ state_t state_d, state_q;
logic uart_rx_q, uart_rx_qq, uart_rx_qqq;

logic[16:0] baud_acc_d, baud_acc_q;
logic baud_acc_half_overflow, baud_acc_overflow;;
logic baud_acc_half_overflow, baud_acc_overflow;

logic[MAX_FRAME_SIZE:0] frame_bit_cnt_d, frame_bit_cnt_q;

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4 changes: 2 additions & 2 deletions src/tx_frontend.sv
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Expand Up @@ -21,8 +21,8 @@
*/

module tx_frontend #(
parameter MIN_FRAME_SIZE = 8,
parameter MAX_FRAME_SIZE = 11
parameter logic[3:0] MIN_FRAME_SIZE = 8,
parameter logic[3:0] MAX_FRAME_SIZE = 11
)(
input logic clk_i,
input logic rst_i,
Expand Down
2 changes: 1 addition & 1 deletion tests/CMakeLists.txt
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Expand Up @@ -29,7 +29,7 @@ set(TESTDATA_DIR ${CMAKE_CURRENT_BINARY_DIR}/)
# Lint
add_lint_target(
TARGET lint
LIB ecap5_dwbmmsc
LIB ecap5_dwbuart
)

# Add testbenches
Expand Down