Add support for near arbitrary baud rate

config/gtkwave/config/ecap5_dwbuart.gtkw

@@ -1,15 +1,15 @@
 [*]
 [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
-[*] Wed May  8 07:33:08 2024
+[*] Thu Dec  4 18:16:15 2025
 [*]
 [dumpfile] "/Users/cchaine/Desktop/Documents/projects/.ecap5.nosync/design/wbuart/build/tests/waves/ecap5_dwbuart.vcd"
-[dumpfile_mtime] "Wed May  8 07:26:31 2024"
-[dumpfile_size] 23128
+[dumpfile_mtime] "Thu Dec  4 18:15:49 2025"
+[dumpfile_size] 67035
 [savefile] "/Users/cchaine/Desktop/Documents/projects/.ecap5.nosync/design/wbuart/config/gtkwave/config/ecap5_dwbuart.gtkw"
-[timestart] 1
-[size] 1440 783
+[timestart] 2792
+[size] 1900 935
 [pos] -1 -1
-*-6.069452 123 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+*-4.971742 2889 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 [markername] AA
 [markername] BB
 [markername] CC
@@ -39,13 +39,13 @@
 [treeopen] TOP.
 [treeopen] TOP.tb_ecap5_dwbuart.
 [treeopen] TOP.tb_ecap5_dwbuart.dut.
-[sst_width] 253
+[sst_width] 255
 [signals_width] 193
 [sst_expanded] 1
-[sst_vpaned_height] 386
+[sst_vpaned_height] 682
 @2024
 [color] 1
-^1 /Users/cchaine/Desktop/Documents/projects/.ecap5.nosync/design/wbuart/config/gtkwave/filters/ecap5_dwbuart_testcase_filter.gtkw
+^1 /Users/cchaine/Desktop/Documents/projects/.ecap5.nosync/design/wbuart/config/gtkwave/filters/ecap5_wbuart_testcase_filter.gtkw
 TOP.tb_ecap5_dwbuart.testcase[31:0]
 @28
 TOP.tb_ecap5_dwbuart.clk_i
@@ -78,30 +78,29 @@ TOP.tb_ecap5_dwbuart.wb_stall_o
 -Wishbone
 @28
 [color] 7
-TOP.tb_ecap5_dwbuart.uart_rx_i
+TOP.tb_ecap5_dwbuart.dut.uart_rx_i
 [color] 7
-TOP.tb_ecap5_dwbuart.uart_tx_o
+TOP.tb_ecap5_dwbuart.dut.uart_tx_o
 @800200
 -Registers
-@c00201
 -CR
 @22
-TOP.tb_ecap5_dwbuart.dut.cr_clk_div_q[15:0]
+TOP.tb_ecap5_dwbuart.dut.cr_acc_incr_q[15:0]
 @28
 TOP.tb_ecap5_dwbuart.dut.cr_ds_q
 TOP.tb_ecap5_dwbuart.dut.cr_p_q[1:0]
 TOP.tb_ecap5_dwbuart.dut.cr_s_q
-@1401201
+@1000200
 -CR
-@c00200
+@800200
 -SR
 @28
 TOP.tb_ecap5_dwbuart.dut.sr_fe_q
 TOP.tb_ecap5_dwbuart.dut.sr_pe_q
 TOP.tb_ecap5_dwbuart.dut.sr_rxne_q
 TOP.tb_ecap5_dwbuart.dut.sr_rxoe_q
 TOP.tb_ecap5_dwbuart.dut.sr_txe_q
-@1401200
+@1000200
 -SR
 @22
 TOP.tb_ecap5_dwbuart.dut.txdr_txd_q[7:0]
@@ -115,7 +114,7 @@ TOP.tb_ecap5_dwbuart.dut.tx_done
 TOP.tb_ecap5_dwbuart.dut.rx_valid
 @22
 TOP.tb_ecap5_dwbuart.dut.rx_frame[10:0]
-@28
-TOP.tb_ecap5_dwbuart.dut.rx_parity
+@29
+TOP.tb_ecap5_dwbuart.inj_frame_error
 [pattern_trace] 1
 [pattern_trace] 0

config/gtkwave/filters/ecap5_wbuart_testcase_filter.gtkw

@@ -5,4 +5,7 @@
 5 T_RXOE
 6 T_FE
 7 T_PE
-8 T_FULL_DUPLEX
+8 T_RACE_SR
+9 T_RACE_TXDR
+10 T_RACE_RXDR
+11 T_ERROR_RETENTION

docs/src/spec/2_overall-description.rst

@@ -42,6 +42,10 @@ Configuration
 
    The baud rate of the peripheral shall be software-configurable.
 
+.. requirement:: U_BAUD_RATE_02
+
+   The following baudrates shall be tested to be within 2% tolerance : 4800, 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600, 1000000, 2000000, 3000000.
+
 .. requirement:: U_PARITY_BIT_01
 
    The parity bit of the peripheral shall be software-configurable.

docs/src/spec/content/uart_cr.rst

@@ -14,7 +14,7 @@ UART_CR contains the control for selecting the UART baudrate, parity, size and s
             { "name": "S", "bits": 1},
             { "name": "DS", "bits": 1},
             { "name": "reserved", "bits": 12, "type": 1},
-            { "name": "CLK_DIV", "bits": 16}
+            { "name": "ACC_INCR", "bits": 16}
         ]
 
 |
@@ -28,10 +28,10 @@ UART_CR contains the control for selecting the UART baudrate, parity, size and s
     - Description
 
   * - 31-16
-    - CLK_DIV
-    - *Clock Divider/Baud Rate selector*
+    - ACC_INCR
+    - *Accumulator increment/Baudrate selector*
 
-      The specified clock divider determines the baud rate with the formula Baud Rate = Freq / CLK_DIV.
+      The specified accumulator increment determines the baud rate with the formula ACC_INCR = round(baudrate * 2^15 / freq).
   * - 15-4
     - reserved
     - *This field is reserved.*
@@ -50,7 +50,7 @@ UART_CR contains the control for selecting the UART baudrate, parity, size and s
 
       0 |tab| 1 stop bit
 
-      2 |tab| 1.5 stop bits
+      1 |tab| 2 stop bits
   * - 1-0
     - P
     - *Parity bit selector*

src/ecap5_dwbuart.sv

@@ -83,7 +83,7 @@ logic tx_transmit_d, tx_transmit_q,
 /*        Memory mapped registers        */
 /*****************************************/
 
-logic[15:0] cr_clk_div_d, cr_clk_div_q;
+logic[15:0] cr_acc_incr_d, cr_acc_incr_q;
 logic       cr_ds_d, cr_ds_q,
             cr_s_d, cr_s_q;
 logic[1:0]  cr_p_d, cr_p_q;
@@ -105,7 +105,7 @@ rx_frontend #(
 ) rx_frontend_inst (
   .clk_i (clk_i),   .rst_i (frontend_rst),
 
-  .cr_clk_div_i   (cr_clk_div_q),
+  .cr_acc_incr_i   (cr_acc_incr_q),
   .cr_ds_i        (cr_ds_q),
   .cr_s_i         (cr_s_q),
   .cr_p_i         (cr_p_q),
@@ -124,7 +124,7 @@ tx_frontend #(
 ) tx_frontend_inst (
   .clk_i (clk_i),   .rst_i (frontend_rst),
 
-  .cr_clk_div_i   (cr_clk_div_q),
+  .cr_acc_incr_i   (cr_acc_incr_q),
   .cr_ds_i        (cr_ds_q),
   .cr_s_i         (cr_s_q),
   .cr_p_i         (cr_p_q),
@@ -153,7 +153,7 @@ ecap5_dwbmmsc wb_interface_inst (
 );
 
 always_comb begin : register_access
-  cr_clk_div_d = cr_clk_div_q;
+  cr_acc_incr_d = cr_acc_incr_q;
   cr_ds_d      = cr_ds_q;
   cr_s_d       = cr_s_q;
   cr_p_d       = cr_p_q;
@@ -167,60 +167,59 @@ always_comb begin : register_access
   rxdr_rxd_d   = rxdr_rxd_q;
   txdr_txd_d   = txdr_txd_q;
 
-  // Set the data output for R and R/W registers
+  // Set the data output for read requests
   mem_read_data_d = 0;
   case(mem_addr[7:2])
     UART_SR:   mem_read_data_d = {27'b0, sr_pe_q, sr_fe_q, sr_rxoe_q, sr_txe_q, sr_rxne_q};
-    UART_CR:   mem_read_data_d = {cr_clk_div_q, 12'b0, cr_s_q, cr_p_q, cr_ds_q};
+    UART_CR:   mem_read_data_d = {cr_acc_incr_q, 12'b0, cr_ds_q, cr_s_q, cr_p_q};
     UART_RXDR: mem_read_data_d = {24'b0, rxdr_rxd_q};
     default:   mem_read_data_d = '0;
   endcase
 
-  // Set the register data for R/W and W registers
+  // Set the register data for write requests
   if(mem_write) begin
     case(mem_addr[7:2])
       UART_CR: begin
-        cr_clk_div_d = mem_write_data[31:16];
+        cr_acc_incr_d = mem_write_data[31:16];
         cr_ds_d = mem_write_data[3];
         cr_s_d = mem_write_data[2];
         cr_p_d = mem_write_data[1:0];
       end
-      UART_TXDR: txdr_txd_d = mem_write_data[7:0];
+      UART_TXDR: begin
+        txdr_txd_d = mem_write_data[7:0];
+      end
       default: begin end
     endcase 
   end
 
-  // Set the TXE field
-  if(tx_done) begin
-    sr_txe_d = 1;
-  end
-
-  // Reset the TXE field
+  // Priority to the memory request
   if(mem_write && (mem_addr[7:2] == UART_TXDR)) begin
     sr_txe_d = 0;
+  end else if (tx_done) begin
+    sr_txe_d = 1;
   end
 
-  // Set the RXDR register and RXNE field
+  // Priority to the hardware
   if(rx_valid) begin
     rxdr_rxd_d = rx_frame[7:0];
     sr_rxne_d = 1;
-  end
 
-  // Reset UART_RXDR after reading
-  if(mem_read && mem_addr[7:2] == UART_RXDR) begin
+    // Errors accumulate so they are never lost
+    sr_pe_d = sr_pe_q | rx_parity_err;
+    sr_fe_d = sr_fe_q | rx_frame_err;
+
+    // If data was read but the buffer was already full
+    if (sr_rxne_q) begin
+      sr_rxoe_d = 1;
+    end
+  // When the memory request occurs but no data was received
+  // we clear the previously received data
+  end else if(mem_read && mem_addr[7:2] == UART_RXDR) begin
     rxdr_rxd_d = '0;
     sr_rxne_d = 0;
-  end
-
-  // Receive error detection
-  if(rx_valid) begin
-    sr_pe_d = rx_parity_err;
-    sr_fe_d = rx_frame_err;
-    sr_rxoe_d = sr_rxne_q | sr_rxoe_q;
-  end
-
-  // Reset UART_SR error fields after reading UART_SR
-  if(mem_read && mem_addr[7:2] == UART_SR) begin
+  // When the memory request occurs but no data was received
+  // we clear the errors
+  end else if(mem_read && mem_addr[7:2] == UART_SR) begin
     sr_pe_d = 0;
     sr_fe_d = 0;
     sr_rxoe_d = 0;
@@ -237,7 +236,7 @@ end
 
 always_ff @(posedge clk_i) begin
   if(rst_i) begin
-    cr_clk_div_q <= '0;
+    cr_acc_incr_q <= '0;
     cr_ds_q <= 0;
     cr_s_q <= 0;
     cr_p_q <= '0;
@@ -255,7 +254,7 @@ always_ff @(posedge clk_i) begin
 
     mem_read_data_q <= '0;
   end else begin
-    cr_clk_div_q <= cr_clk_div_d;
+    cr_acc_incr_q <= cr_acc_incr_d;
     cr_ds_q <= cr_ds_d;
     cr_s_q <= cr_s_d;
     cr_p_q <= cr_p_d;