Update internal bus address

src/ecap5_dwbmmsc.sv

@@ -41,7 +41,7 @@ module ecap5_dwbmmsc
   //=================================
   //    Output interface
 
-  output  logic[7:0]   addr_o,
+  output  logic[31:0]  addr_o,
   output  logic        read_o,
   input   logic[31:0]  read_data_i,
   output  logic        write_o,
@@ -98,7 +98,7 @@ assign wb_ack_o = wb_ack_q;
 assign wb_dat_o = read_data_i;
 assign wb_stall_o = 0;
 
-assign addr_o = wb_adr_i[7:0];
+assign addr_o = wb_adr_i;
 assign read_o  = wb_stb_i && wb_cyc_i && ~wb_we_i;
 assign write_o = wb_stb_i && wb_cyc_i && wb_we_i;
 assign write_data_o = wb_dat_i;

tests/benches/ecap5_dwbmmsc/tb_ecap5_dwbmmsc.cpp

@@ -163,7 +163,7 @@ void tb_ecap5_dwbmmsc_read(TB_Ecap5_dwbmmsc * tb) {
   //      Checks 
 
   tb->check(COND_output, (core->read_o == 1) &&
-                         (core->addr_o == (addr & 0xFF)) &&
+                         (core->addr_o == addr) &&
                          (core->write_o == 0));
 
   //=================================
@@ -251,7 +251,7 @@ void tb_ecap5_dwbmmsc_write(TB_Ecap5_dwbmmsc * tb) {
   //      Checks 
 
   tb->check(COND_output, (core->read_o == 0) &&
-                         (core->addr_o == (addr & 0xFF)) &&
+                         (core->addr_o == addr) &&
                          (core->write_o == 1) &&
                          (core->write_data_o == data));
 

tests/benches/ecap5_dwbmmsc/tb_ecap5_dwbmmsc.sv

@@ -43,7 +43,7 @@ module tb_ecap5_dwbmmsc
   //=================================
   //    Output interface
 
-  output  logic[7:0]   addr_o,
+  output  logic[31:0]  addr_o,
   output  logic        read_o,
   input   logic[31:0]  read_data_i,
   output  logic        write_o,