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Merged
cchaine merged 1 commit into from
Dec 27, 2025
Merged

Add pll to the system on chip #19

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25 changes: 20 additions & 5 deletions CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -83,11 +83,10 @@ add_dependency(
GIT ecap5/ecap5-dwbspi
TAG release/v1.0.0)

# Define an interface library
# Define an interface library for the sources
add_library(ecap5_dsoc INTERFACE)
target_sources(ecap5_dsoc INTERFACE
${CMAKE_CURRENT_LIST_DIR}/src/ecap5_dsoc.sv
${CMAKE_CURRENT_LIST_DIR}/src/poweron_reset.sv
)
target_link_libraries(ecap5_dsoc INTERFACE
ecap5_dproc
Expand All @@ -113,15 +112,31 @@ if(PROJECT_IS_TOP_LEVEL)
add_subdirectory(firmware)
add_subdirectory(tests)

# Define an interface library for the bitstream generation
add_library(ecap5_dsoc_bitstream INTERFACE)
target_sources(ecap5_dsoc_bitstream INTERFACE
${CMAKE_BINARY_DIR}/generated_pll.v
)
target_link_libraries(ecap5_dsoc_bitstream INTERFACE
ecap5_dsoc
)

# Bitstream generation

set(CLOCK_FREQUENCY 60)
add_ecp5_pll_generation(
INPUT_FREQ 24
OUTPUT_FREQ ${CLOCK_FREQUENCY}
MODULE_NAME generated_pll)

add_synthesis_target(
LIB ecap5_dsoc
LIB ecap5_dsoc_bitstream
TOP_MODULE ecap5_dsoc
TARGET_FPGA ecp5
OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/synth.json
DEPENDS bootloader
DEFINES BOOTLOADER_PATH=\\\"${CMAKE_CURRENT_BINARY_DIR}/firmware/bootloader.load\\\")
DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/generated_pll.v bootloader
DEFINES BOOTLOADER_PATH=\\\"${CMAKE_CURRENT_BINARY_DIR}/firmware/bootloader.load\\\"
CLK_FREQ=${CLOCK_FREQUENCY}000000)

add_place_and_route_target(
INPUT ${CMAKE_CURRENT_BINARY_DIR}/synth.json
Expand Down
6 changes: 3 additions & 3 deletions config/pinout.lpf
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Expand Up @@ -4,10 +4,10 @@

# Oscillator input

LOCATE COMP "clk_i" SITE "P5";
LOCATE COMP "ext_clk_i" SITE "P5";

PORT "clk_i" IO_TYPE=LVCMOS33;
FREQUENCY PORT "clk_i" 24 MHZ;
PORT "ext_clk_i" IO_TYPE=LVCMOS33;
FREQUENCY PORT "ext_clk_i" 24 MHZ;

# Power monitoring - SPI

Expand Down
2 changes: 1 addition & 1 deletion firmware/bootloader/uart.S
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@
.equ UART_DS_MASK, (1 << 3)
.equ UART_TXE_MASK, (1 << 1)

.equ UART_ACC_INCR, 26
.equ UART_ACC_INCR, 10
.equ UART_DS, 1

.section .text
Expand Down
43 changes: 25 additions & 18 deletions src/ecap5_dsoc.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -20,8 +20,12 @@
* along with ECAP5-DSOC. If not, see <http://www.gnu.org/licenses/>.
*/

`ifndef CLK_FREQ
`define CLK_FREQ 24000000
`endif

module ecap5_dsoc (
input logic clk_i,
input logic ext_clk_i,

//=================================
// UART interface
Expand Down Expand Up @@ -61,8 +65,8 @@ module ecap5_dsoc (
output logic emmc_rst_n
);

// poweron-reset
logic por_rst;
// PLL signals
logic clk, rst, pll_locked;

// core master memory bus
logic[31:0] core_wb_adr_o;
Expand Down Expand Up @@ -123,16 +127,17 @@ logic flash_wb_stall_o;
logic flash_clk;
logic flash_cs;

poweron_reset por_inst (
.clk_i (clk_i),
.rst_o (por_rst)
generated_pll pll_inst (
.clkin (ext_clk_i),
.clkout0 (clk),
.locked (pll_locked)
);

ecap5_dproc #(
.BOOT_ADDRESS (32'h0)
) core_inst (
.clk_i (clk_i),
.rst_i (por_rst),
.clk_i (clk),
.rst_i (rst),

.wb_adr_o (core_wb_adr_o),
.wb_dat_i (core_wb_dat_i),
Expand All @@ -146,8 +151,8 @@ ecap5_dproc #(
);

ecap5_dwbuart uart_inst (
.clk_i (clk_i),
.rst_i (por_rst),
.clk_i (clk),
.rst_i (rst),

.wb_adr_i (uart_wb_adr_i),
.wb_dat_o (uart_wb_dat_o),
Expand All @@ -168,8 +173,8 @@ ecap5_dwbmem_bram #(
.ENABLE_PRELOADING (1),
.PRELOAD_HEX_PATH (`BOOTLOADER_PATH)
) bram_inst (
.clk_i (clk_i),
.rst_i (por_rst),
.clk_i (clk),
.rst_i (rst),

.wb_adr_i (bram_wb_adr_i),
.wb_dat_o (bram_wb_dat_o),
Expand All @@ -183,10 +188,10 @@ ecap5_dwbmem_bram #(
);

ecap5_dwbtimer #(
.CLK_FREQ (24000000)
.CLK_FREQ (`CLK_FREQ)
) timer_inst (
.clk_i (clk_i),
.rst_i (por_rst),
.clk_i (clk),
.rst_i (rst),

.wb_adr_i (timer_wb_adr_i),
.wb_dat_o (timer_wb_dat_o),
Expand All @@ -201,8 +206,8 @@ ecap5_dwbtimer #(

ecap5_dwbspi #(
) flash_inst (
.clk_i (clk_i),
.rst_i (por_rst),
.clk_i (clk),
.rst_i (rst),

.wb_adr_i (flash_wb_adr_i),
.wb_dat_o (flash_wb_dat_o),
Expand Down Expand Up @@ -298,7 +303,9 @@ always_comb begin : memory_mapping
flash_wb_stb_i = core_wb_stb_o;
end

assign flash_cs_n = ~flash_cs;
assign rst = !pll_locked;

assign flash_cs_n = !flash_cs;

assign sram_ce_n = 1;
assign sdram0_cs_n = 1;
Expand Down
42 changes: 0 additions & 42 deletions src/poweron_reset.sv
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This file was deleted.

28 changes: 27 additions & 1 deletion tests/CMakeLists.txt
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Expand Up @@ -32,10 +32,36 @@ add_lint_target(
LIB ecap5_dsoc
)

# Generate a mocked pll
file(WRITE ${CMAKE_CURRENT_BINARY_DIR}/generated_pll.v
"module generated_pll(\n"
" input clkin,\n"
" output clkout0,\n"
" output locked\n"
");\n"
"logic locked_q = 1'b0;\n"
"logic locked_qq;\n"
"always_ff @(posedge clkin) begin\n"
" locked_q <= 1;\n"
" locked_qq <= locked_q;\n"
"end\n"
"assign clkout0 = clkin;\n"
"assign locked = locked_qq;\n"
"endmodule\n"
)
# Create a test interface library
add_library(ecap5_dsoc_tests INTERFACE)
target_sources(ecap5_dsoc_tests INTERFACE
${CMAKE_CURRENT_BINARY_DIR}/generated_pll.v
)
target_link_libraries(ecap5_dsoc_tests INTERFACE
ecap5_dsoc
)

# Add testbenches
add_testbench(
MODULE ecap5_dsoc
LIBS ecap5_dsoc
LIBS ecap5_dsoc_tests
BENCH_DIR ${BENCH_DIR}
TESTDATA_DIR ${TESTDATA_DIR}
TEST_INCLUDE_DIRS ${TEST_INCLUDE_DIRS}
Expand Down
8 changes: 5 additions & 3 deletions tests/benches/ecap5_dsoc/tb_ecap5_dsoc.cpp
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Expand Up @@ -62,13 +62,15 @@ int main(int argc, char ** argv, char ** env) {
tb->init_conditions(__CondIdEnd);
tb->debug_log = true;

// 24MHz
tb->clk_period_in_ps = 41667;
// 60MHz
tb->clk_ptr = &tb->core->ext_clk_i;
tb->clk_period_in_ps = 16667;

/************************************************************/

tb->reset();
tb->n_tick(200000);
// 10ms
tb->n_tick(600000);

/************************************************************/

Expand Down
4 changes: 2 additions & 2 deletions tests/benches/ecap5_dsoc/tb_ecap5_dsoc.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@
*/

module tb_ecap5_dsoc (
input logic clk_i,
input logic ext_clk_i,

//=================================
// UART interface
Expand Down Expand Up @@ -50,7 +50,7 @@ module tb_ecap5_dsoc (
);

ecap5_dsoc dut (
.clk_i (clk_i),
.ext_clk_i (ext_clk_i),

.uart_tx_o (uart_tx_o),
.uart_rx_i (uart_rx_i),
Expand Down