Fix build on newer versions of Verilator

.gitignore

@@ -0,0 +1,7 @@
+obj_dir
+blinky_tb
+blinky.json
+
+*_out.config
+*.vcd
+*.bit

Makefile

@@ -29,15 +29,18 @@ VERILATOR_ROOT ?= $(shell bash -c '$(VERILATOR) -V|grep VERILATOR_ROOT | head -1
 ## The directory containing the verilator includes
 VINC := $(VERILATOR_ROOT)/include
 
+VSRCS = verilated verilated_threads verilated_vcd_c
+
 $(VDIRFB)/V$(TOPMOD).cpp: $(TOPMOD).v
 	$(VERILATOR) $(VFLAGS) -cc $(VLOGFIL)
 
 $(VDIRFB)/V$(TOPMOD)__ALL.a: $(VDIRFB)/V$(TOPMOD).cpp
 	make --no-print-directory -C $(VDIRFB) -f V$(TOPMOD).mk
 
 $(SIMPROG): $(SIMFILE) $(VDIRFB)/V$(TOPMOD)__ALL.a $(COSIMS)
-	$(GCC) $(CFLAGS) $(VINC)/verilated.cpp				\
-		$(VINC)/verilated_vcd_c.cpp $(SIMFILE) $(COSIMS)	\
+	$(GCC) $(CFLAGS) 				\
+		$(patsubst %, $(VINC)/%.cpp, $(VSRCS))	\
+		$(SIMFILE) $(COSIMS)			\
 		$(VDIRFB)/V$(TOPMOD)__ALL.a -o $(SIMPROG)
 
 test: $(VCDFILE)

TestPattern/.gitignore

@@ -0,0 +1,5 @@
+pattern_tb
+image.ppm
+ULX3S_45F.json
+ULX3S_45F.ys
+ulx3s_45f_ULX3S_45F.config

TestPattern/Makefile

@@ -31,15 +31,18 @@ VERILATOR_ROOT ?= $(shell bash -c '$(VERILATOR) -V|grep VERILATOR_ROOT | head -1
 ## The directory containing the verilator includes
 VINC := $(VERILATOR_ROOT)/include
 
+VSRCS = verilated verilated_threads verilated_vcd_c
+
 $(VDIRFB)/V$(TOPMOD).cpp: $(TOPMOD).v 
 	$(VERILATOR) $(VFLAGS) -cc --top-module $(TOPMOD) $(VLOGFIL)
 
 $(VDIRFB)/V$(TOPMOD)__ALL.a: $(VDIRFB)/V$(TOPMOD).cpp
 	make --no-print-directory -C $(VDIRFB) -f V$(TOPMOD).mk
 
 $(SIMPROG): $(SIMFILE) $(VDIRFB)/V$(TOPMOD)__ALL.a $(COSIMS)
-	$(GCC) $(CFLAGS) $(VINC)/verilated.cpp				\
-		$(VINC)/verilated_vcd_c.cpp $(SIMFILE) $(COSIMS)	\
+	$(GCC) $(CFLAGS) 				\
+		$(patsubst %, $(VINC)/%.cpp, $(VSRCS))	\
+		$(SIMFILE) $(COSIMS)			\
 		$(VDIRFB)/V$(TOPMOD)__ALL.a -o $(SIMPROG)
 
 test: $(VCDFILE)

TestPattern/llhdmi.v

@@ -1,32 +1,24 @@
 `default_nettype none
 //
 module llhdmi(
-  i_tmdsclk, i_pixclk,
-  i_reset, i_red, i_grn, i_blu,
-  o_rd, o_newline, o_newframe,
+  input wire i_tmdsclk,		// TMDS clock
+  input wire i_pixclk,		// Pixel clock, 10 times slower than i_tmdsclk
+  input wire i_reset,		// Reset this module when strobed high
+  input wire [7:0] i_red,	// Red green and blue colour values
+  input wire [7:0] i_grn,	// for each pixel
+  input wire [7:0] i_blu,
 `ifdef VERILATOR
-  o_TMDS_red, o_TMDS_grn, o_TMDS_blu,
-`endif
-  o_red, o_grn, o_blu);
-
-  input wire i_tmdsclk;		// TMDS clock
-  input wire i_pixclk;		// Pixel clock, 10 times slower than i_tmdsclk
-  input wire i_reset;		// Reset this module when strobed high
-  input wire [7:0] i_red;	// Red green and blue colour values
-  input wire [7:0] i_grn;	// for each pixel
-  input wire [7:0] i_blu;
-  output wire o_rd;		// True when we can accept pixel data
-  output reg o_newline;		// True on last pixel of each line
-  output reg o_newframe;	// True on last pixel of each frame
-  output wire o_red;		// Red TMDS pixel stream
-  output wire o_grn;		// Green TMDS pixel stream
-  output wire o_blu;		// Blue TMDS pixel stream
-`ifdef VERILATOR
-  output wire [9:0] o_TMDS_red, o_TMDS_grn, o_TMDS_blu;
-  assign o_TMDS_red= TMDS_red;
-  assign o_TMDS_grn= TMDS_grn;
-  assign o_TMDS_blu= TMDS_blu;
+  output wire [9:0] o_TMDS_red,
+  output wire [9:0] o_TMDS_grn,
+  output wire [9:0] o_TMDS_blu,
 `endif
+  output wire o_rd,		// True when we can accept pixel data
+  output reg o_newline,		// True on last pixel of each line
+  output reg o_newframe,	// True on last pixel of each frame
+  output wire o_red,		// Red TMDS pixel stream
+  output wire o_grn,		// Green TMDS pixel stream
+  output wire o_blu		// Blue TMDS pixel stream
+);
 
   reg [9:0] CounterX, CounterY;
   reg hSync, vSync, DrawArea;
@@ -108,4 +100,10 @@ module llhdmi(
   assign o_grn= TMDS_shift_grn[0];
   assign o_blu= TMDS_shift_blu[0];
 
+`ifdef VERILATOR
+  assign o_TMDS_red= TMDS_red;
+  assign o_TMDS_grn= TMDS_grn;
+  assign o_TMDS_blu= TMDS_blu;
+`endif
+
 endmodule

TestPattern/pattern.v

@@ -1,9 +1,13 @@
 `default_nettype none
 
-module pattern(input i_tmdsclk, i_pixclk, output red, grn, blu, o_rd,
-	o_TMDS_red, o_TMDS_grn, o_TMDS_blu);
-
-  wire [7:0] red, grn, blu;
+module pattern(
+               input wire        i_tmdsclk,
+               input wire        i_pixclk,
+               output wire [7:0] red, grn, blu,
+               output wire       o_rd,
+	       output wire [9:0] o_TMDS_red, o_TMDS_grn, o_TMDS_blu);
+
+  // wire [7:0] red, grn, blu;
   wire [23:0] pixel;
   assign red= pixel[23:16];
   assign grn= pixel[15:8];
@@ -13,9 +17,8 @@ module pattern(input i_tmdsclk, i_pixclk, output red, grn, blu, o_rd,
   wire o_red;
   wire o_grn;
   wire o_blu;
-  wire [9:0] o_TMDS_red, o_TMDS_grn, o_TMDS_blu;
 /* verilator lint_on UNUSED */
-  wire o_rd, o_newline, o_newframe;
+  wire o_newline, o_newframe;
 
   // A reset line that goes low after 16 ticks
   reg [2:0] reset_cnt = 0;

blinky.v

@@ -1,15 +1,12 @@
 `ifdef VERILATOR
 /* verilator lint_off UNUSED */		// Not all of btn gets used, sigh
-module blinky(input i_clk, input [6:0] btn, output [7:0] o_led);
+module blinky(input wire i_clk, input wire [6:0] btn, output wire [7:0] o_led);
 /* verilator lint_on UNUSED */
-    wire i_clk;
-    wire [6:0] btn;
-    wire [7:0] o_led;
 `else
-module top(input clk_25mhz,
-           input [6:0] btn,
-           output [7:0] led,
-           output wifi_gpio0);
+module top(input wire clk_25mhz,
+           input wire [6:0] btn,
+           output wire [7:0] led,
+           output wire wifi_gpio0);
 
     wire i_clk;