Extend Gatework

.github/workflows/ci.yml

@@ -100,6 +100,10 @@ jobs:
         run: cabal run gatework -- --netlist fixtures/delay.net --duration 12 --output /tmp/delay.vcd --set a=0 --at 2 a=1 --at 6 a=0
       - name: Compare the gate delay demo with the golden file
         run: diff fixtures/delay.golden.vcd /tmp/delay.vcd
+      - name: Run the asymmetric delay demo
+        run: cabal run gatework -- --netlist fixtures/asymdelay.net --duration 15 --output /tmp/asymdelay.vcd --set a=0 --at 1 a=1 --at 6 a=0 --at 11 a=1
+      - name: Compare the asymmetric delay demo with the golden file
+        run: diff fixtures/asymdelay.golden.vcd /tmp/asymdelay.vcd
       - name: Confirm a missing library file stops the run
         run: |
           if cabal run gatework -- --netlist fixtures/libadder.net --library fixtures/missing.net --duration 0 --output /tmp/none.vcd 2>/tmp/none.log; then

CHANGELOG.md

@@ -5,6 +5,25 @@ All notable changes to Gatework appear in this file.
 The format follows the Keep a Changelog convention.
 This project uses semantic versioning.
 
+## [0.14.0.0] - 2026-08-04
+
+### Added
+
+- Declare separate rise and fall delays with the `rise=N` and `fall=N` fields.
+- A rising output transition fires after the rise delay.
+- Any other transition fires after the fall delay.
+- The `delay=N` field sets both delays to the same value.
+- The `delay=N` field cannot combine with `rise=` or `fall=`.
+- Reject negative, non-integer, repeated, and unknown delay fields.
+- Add an asymmetric delay demo fixture and a golden waveform.
+- Add deterministic tests and a QuickCheck property for asymmetric delays.
+
+### Changed
+
+- The scheduler picks the delay from the new output value.
+- Bump the package version to 0.14.0.0.
+- Update the golden VCD files to the new version string.
+
 ## [0.13.0.0] - 2026-08-03
 
 ### Added

README.md

@@ -51,6 +51,9 @@ You can do these tasks:
 - Declare a gate output delay with the `delay=N` field.
 - Watch a gate transition fire after its declared delay.
 - Let gate delays accumulate through a chain of gates.
+- Declare separate rise and fall delays with the `rise=N` and `fall=N` fields.
+- Watch a rising output fire after its rise delay.
+- Watch a falling output fire after its fall delay.
 
 ## Architecture
 
@@ -84,6 +87,8 @@ The scheduler processes only changed signals.
 The scheduler tracks one committed contribution per gate driver.
 The scheduler resolves several gate drivers into one wire value.
 A delayed gate commits its new value after its delay elapses.
+A rising output uses the rise delay.
+A falling output uses the fall delay.
 A gate delay accumulates through a chain of gates.
 A rising clock edge samples attached flip-flops together.
 An asserted reset forces flip-flop outputs to their initial values.
@@ -515,6 +520,45 @@ The signal `x` rises at time 8.
 The signal `y` falls at time 11.
 The initial state settles at time zero without delay.
 
+## Asymmetric delay demo
+
+Run one inverter with different rise and fall delays.
+
+```powershell
+cabal run gatework -- --netlist fixtures/asymdelay.net --duration 15 --output asymdelay.vcd --set a=0 --at 1 a=1 --at 6 a=0 --at 11 a=1
+```
+
+The command writes this output:
+
+```text
+Wrote asymdelay.vcd
+Signals: 2
+Duration: 15 time units
+Assertions: 7 passed
+```
+
+The gate uses the `rise=4` and `fall=1` fields.
+A rising output waits four time units.
+A falling output waits one time unit.
+The input changes stay farther apart than the longest delay.
+
+| Time | a | y |
+| --- | --- | --- |
+| 0 | 0 | 1 |
+| 1 | 1 | 1 |
+| 2 | 1 | 0 |
+| 6 | 0 | 0 |
+| 10 | 0 | 1 |
+| 11 | 1 | 1 |
+| 12 | 1 | 0 |
+
+The input `a` rises at time 1.
+The output `y` falls at time 2, one unit later.
+The input `a` falls at time 6.
+The output `y` rises at time 10, four units later.
+The input `a` rises at time 11.
+The output `y` falls at time 12.
+
 ## Bus demo
 
 Run four-bit bus operations with gates and a register.
@@ -759,6 +803,35 @@ The value `b0101` means `a[3]=0`, `a[2]=1`, `a[1]=0`, and `a[0]=1`.
 The value `b1111` means every bit of `x` is high.
 The register output `q` changes together on the clock edge.
 
+The file `fixtures/asymdelay.golden.vcd` holds the asymmetric delay demo waveform.
+Its timeline shows the output fall one unit after the input rise.
+The output rise comes four units after the input fall:
+
+```text
+#0
+0!
+0"
+1"
+#1
+1!
+#2
+0"
+#6
+0!
+#10
+1"
+#11
+1!
+#12
+0"
+```
+
+Here `!` is the input `a` and `"` is the output `y`.
+The input rises at time 1 and time 11.
+The output falls one unit later at time 2 and time 12.
+The input falls at time 6.
+The output rises four units later at time 10.
+
 ## Netlist format
 
 Use one declaration per line.
@@ -814,11 +887,23 @@ A chain of gates adds the delays together.
 The example output `y` changes two units after `a`.
 The output `z` changes three units after `y`.
 
-The initial state settles at time zero without delay.
-Events at time zero ignore the gate delay.
+A gate can use separate rise and fall delays.
+The `rise=N` field delays a transition to high.
+The `fall=N` field delays every other transition.
+Omitted delays default to zero.
+
+```text
+gate NOT slow (a) -> y rise=4 fall=1
+```
+
+The `delay=N` field sets both delays to the same value.
+The `delay=` field cannot combine with `rise=` or `fall=`.
 A delay field cannot repeat on one gate.
 An unknown gate field is an error.
 
+The initial state settles at time zero without delay.
+Events at time zero ignore the gate delay.
+
 ### Multiple drivers
 
 One wire can have many gate drivers.
@@ -1041,13 +1126,15 @@ Deterministic tests also cover whole-bus input values, their bit order, their er
 Deterministic tests also cover VCD vectors, their header declarations, their grouped values, four-state vector values, and module-internal bus vectors.
 Deterministic tests also cover gate delay parsing and invalid delay fields.
 Deterministic tests also cover delayed transitions, delay accumulation, zero-delay behavior, multi-driver delays, and the initial settle.
+Deterministic tests also cover rise and fall delay parsing, conflict rules, direction-specific transitions, and the asymmetric delay demo.
 QuickCheck properties cover gate algebra, full adder correctness, scheduled input sampling, reset sampling, register width, and assertion soundness.
 QuickCheck properties also compare the hierarchical adder and counter with their flat versions.
 QuickCheck properties also cover the four-state model and the tri-state buffer truth table.
 QuickCheck properties also compare a bus circuit with a bitwise reference model.
 QuickCheck properties also compare the shared bus with a per-time resolution model.
 QuickCheck properties also compare a library adder with its flat version.
 QuickCheck properties also compare a delayed gate with a per-time reference model.
+QuickCheck properties also compare an asymmetric delayed gate with a per-time reference model.
 QuickCheck properties also compare the counter report with the simulated waveform.
 QuickCheck properties also compare whole-bus input values with per-bit reference values.
 QuickCheck properties also compare every VCD vector value with the per-bit waveform.
@@ -1071,6 +1158,7 @@ The library adder property compares a library netlist with the flat adder.
 The counter report property compares each report cell with the simulated value.
 The VCD vector property compares each vector value with the per-bit values at that time.
 The delayed-gate property compares each output sample with the reference input time.
+The asymmetric-delay property compares each output sample with the directional reference.
 
 ## Test status
 
@@ -1083,6 +1171,7 @@ CI runs the report demo and compares it with the report golden file.
 CI runs the bus demo with whole-bus input values.
 CI runs the four-state vector demo and compares it with its golden file.
 CI runs the gate delay demo and compares it with its golden file.
+CI runs the asymmetric delay demo and compares it with its golden file.
 CI confirms that a missing library file stops the run.
 CI confirms that an invalid gate delay stops the run.
 
@@ -1099,6 +1188,10 @@ A gate cannot drive a flip-flop output.
 Combinational loops stop with an event-limit error.
 A gate without a delay field uses zero delay.
 A gate delay applies to both rising and falling transitions.
+A transition to high uses the rise delay.
+Every other transition uses the fall delay.
+The `delay=` field sets both delays to one value.
+The `delay=` field cannot combine with `rise=` or `fall=`.
 The initial state settles at time zero without delay.
 Events at time zero ignore the gate delay.
 A delayed transition uses the input value at its fire time.
@@ -1134,6 +1227,7 @@ The report prints every signal in the stable signal order.
 
 ## Roadmap
 
+Release 0.14.0.0 completed separate rise and fall gate delays.
 Release 0.13.0.0 completed configurable gate delays.
 Release 0.12.0.0 completed multi-bit values in the VCD timeline.
 Release 0.11.0.0 completed whole-bus input values on the command line.
@@ -1149,9 +1243,8 @@ Release 0.2.0.0 completed scheduled input transitions.
 
 Remaining work:
 
-1. Add separate rise and fall delay fields.
-2. Add a clock-to-output delay field for flip-flops.
-3. Add a buffer gate to the gate library.
+1. Add a clock-to-output delay field for flip-flops.
+2. Add a buffer gate to the gate library.
 
 ## License
 

fixtures/adder.golden.vcd

@@ -2,7 +2,7 @@ $date
   generated deterministically by gatework
 $end
 $version
-  gatework 0.13.0.0
+  gatework 0.14.0.0
 $end
 $timescale 1ns $end
 $scope module gatework $end

fixtures/assert.golden.vcd

@@ -2,7 +2,7 @@ $date
   generated deterministically by gatework
 $end
 $version
-  gatework 0.13.0.0
+  gatework 0.14.0.0
 $end
 $comment
   assert y = 1 at 0

fixtures/asymdelay.golden.vcd

@@ -0,0 +1,37 @@
+$date
+  generated deterministically by gatework
+$end
+$version
+  gatework 0.14.0.0
+$end
+$comment
+  assert y = 1 at 0
+  assert y = 1 at 1
+  assert y = 0 at 2
+  assert y = 0 at 9
+  assert y = 1 at 10
+  assert y = 1 at 11
+  assert y = 0 at 12
+$end
+$timescale 1ns $end
+$scope module gatework $end
+$var wire 1 ! a $end
+$var wire 1 " y $end
+$upscope $end
+$enddefinitions $end
+#0
+0!
+0"
+1"
+#1
+1!
+#2
+0"
+#6
+0!
+#10
+1"
+#11
+1!
+#12
+0"

fixtures/asymdelay.net

@@ -0,0 +1,17 @@
+# Asymmetric gate delay demo.
+# A rising output transition uses the rise delay.
+# A falling output transition uses the fall delay.
+# The input changes stay farther apart than the longest delay.
+input a
+output y
+wire y
+
+gate NOT inv (a) -> y rise=4 fall=1
+
+assert y = 1 at 0
+assert y = 1 at 1
+assert y = 0 at 2
+assert y = 0 at 9
+assert y = 1 at 10
+assert y = 1 at 11
+assert y = 0 at 12

fixtures/bus.golden.vcd

@@ -2,7 +2,7 @@ $date
   generated deterministically by gatework
 $end
 $version
-  gatework 0.13.0.0
+  gatework 0.14.0.0
 $end
 $comment
   assert x[0] = 1 at 0

fixtures/counter.golden.vcd

@@ -2,7 +2,7 @@ $date
   generated deterministically by gatework
 $end
 $version
-  gatework 0.13.0.0
+  gatework 0.14.0.0
 $end
 $timescale 1ns $end
 $scope module gatework $end

fixtures/delay.golden.vcd

@@ -2,7 +2,7 @@ $date
   generated deterministically by gatework
 $end
 $version
-  gatework 0.13.0.0
+  gatework 0.14.0.0
 $end
 $comment
   assert x = 1 at 0

fixtures/gates.golden.vcd

@@ -2,7 +2,7 @@ $date
   generated deterministically by gatework
 $end
 $version
-  gatework 0.13.0.0
+  gatework 0.14.0.0
 $end
 $comment
   assert nand_out = 1 at 0

fixtures/haddader.golden.vcd

@@ -2,7 +2,7 @@ $date
   generated deterministically by gatework
 $end
 $version
-  gatework 0.13.0.0
+  gatework 0.14.0.0
 $end
 $timescale 1ns $end
 $scope module gatework $end

fixtures/hcounter.golden.vcd

@@ -2,7 +2,7 @@ $date
   generated deterministically by gatework
 $end
 $version
-  gatework 0.13.0.0
+  gatework 0.14.0.0
 $end
 $timescale 1ns $end
 $scope module gatework $end

fixtures/libadder.golden.vcd

@@ -2,7 +2,7 @@ $date
   generated deterministically by gatework
 $end
 $version
-  gatework 0.13.0.0
+  gatework 0.14.0.0
 $end
 $timescale 1ns $end
 $scope module gatework $end

fixtures/reg2.golden.vcd

@@ -2,7 +2,7 @@ $date
   generated deterministically by gatework
 $end
 $version
-  gatework 0.13.0.0
+  gatework 0.14.0.0
 $end
 $timescale 1ns $end
 $scope module gatework $end

fixtures/register.golden.vcd

@@ -2,7 +2,7 @@ $date
   generated deterministically by gatework
 $end
 $version
-  gatework 0.13.0.0
+  gatework 0.14.0.0
 $end
 $timescale 1ns $end
 $scope module gatework $end

fixtures/reset.golden.vcd

@@ -2,7 +2,7 @@ $date
   generated deterministically by gatework
 $end
 $version
-  gatework 0.13.0.0
+  gatework 0.14.0.0
 $end
 $timescale 1ns $end
 $scope module gatework $end

fixtures/shared.golden.vcd

@@ -2,7 +2,7 @@ $date
   generated deterministically by gatework
 $end
 $version
-  gatework 0.13.0.0
+  gatework 0.14.0.0
 $end
 $comment
   assert y = z at 0