ECE Student | Embedded Systems | VLSI & Digital Design | Robotics
I build practical engineering systems across VLSI and digital RTL, embedded firmware, hardware design, robotics, and software interfaces.
My work ranges from Verilog RTL and digital design to STM32 and ESP32 firmware, communication protocols, processor-oriented hardware, ROS 2 robotics, IoT systems, and hardware-focused prototypes.
I enjoy working across the boundary between software and hardware — from writing the code to understanding the system underneath it.
My VLSI and RTL work has progressed from digital logic fundamentals toward reusable hardware blocks, processor-oriented designs, and synthesis workflows.
The current Verilog portfolio contains 27 projects covering:
- Combinational and sequential RTL
- Finite State Machines
- SPI, I²C, UART and CAN
- AXI4-Lite interfaces
- SDRAM and arbitration
- DMA
- Interrupt controllers
- Pipelined ALU design
- Hazard detection
- Forwarding logic
- Branch control
- RISC-V-oriented pipeline concepts
The workflow includes RTL development, simulation, waveform analysis, and Yosys synthesis so that I can connect the HDL I write with the hardware structure produced after synthesis.
I work on microcontroller-based systems with an emphasis on firmware structure, peripheral integration, debugging, and practical validation.
Current work includes:
- STM32 firmware
- ESP32 systems
- Embedded C
- Sensor interfacing
- ADC and PWM
- Timers and interrupts
- UART communication
- Data logging
- IoT systems
- Firmware verification
I am building toward autonomous robotics through ROS 2, simulation, embedded systems, and modular software architecture.
Current areas include:
- ROS 2
- Python
- Gazebo
- Robot simulation
- Autonomous vehicle concepts
- Perception and control
- Hardware/software integration
Alongside firmware and RTL, I work on practical hardware systems and prototypes involving:
- PCB design
- Sensor systems
- IoT devices
- Embedded controllers
- STEM hardware
- Robotics platforms
- Hardware interfaces
| Area | Project | Focus |
|---|---|---|
| VLSI & Digital Design | Verilog RTL Projects | RTL design, verification and Yosys synthesis |
| Embedded Systems | STM32 Industrial Firmware | STM32 firmware and embedded verification |
| Robotics | Autonomous Robotics | ROS 2 and autonomous robotics development |
| ROS 2 | ROS 2 Fundamentals | ROS 2 learning and robotics foundations |
These repositories represent different parts of the engineering stack I am building toward, from low-level firmware and RTL to larger software and robotics systems.
CircuitJester is my engineering portfolio and project showcase.
It brings together my work across:
- VLSI and digital hardware
- Embedded systems
- Robotics
- IoT
- Hardware prototyping
- Software and interface design
The website acts as the presentation layer for the broader engineering work, while the individual GitHub repositories contain the implementation, documentation, experiments, and engineering history behind the projects.
Visit the CircuitJester portfolio →
Across different domains, I try to follow the same basic engineering loop:
Problem
↓
Requirements
↓
Architecture
↓
Implementation
↓
Simulation / Bring-up
↓
Verification
↓
Debugging
↓
Documentation
- Verilog HDL
- Icarus Verilog
- GTKWave
- Yosys
- Linux / WSL
- C
- STM32 HAL
- STM32CubeMX
- STM32CubeIDE
- ESP32
- PICSimLab
- Python
- ROS 2
- Gazebo
- Linux / WSL
- PCB Design
- EasyEDA
- Sensor interfacing
- Embedded hardware prototyping
- Git
- GitHub
- VS Code
My long-term direction is toward hardware architecture and open-source silicon development.
Embedded Systems
↓
Digital RTL
↓
FPGA Design
↓
Yosys
↓
OpenROAD
↓
Open-Source ASIC Flow
↓
RISC-V Hardware
↓
AI Hardware
I am approaching this progressively — strengthening my RTL and embedded foundations first, then moving deeper into FPGA design, synthesis, physical design, processor architecture, and larger hardware systems.
Right now I am spending most of my time improving:
- VLSI and RTL design
- RTL verification
- Embedded firmware architecture
- FPGA-oriented digital design
- Yosys synthesis
- Open-source ASIC tooling
- Processor pipeline concepts
- ROS 2 robotics
- Hardware/software system integration
The main goal behind these projects is to understand engineering systems as complete systems rather than as isolated code examples.
I am working on connecting the layers:
Software
↕
Firmware
↕
Digital Logic
↕
RTL
↕
Hardware Architecture
↕
Silicon
That connection is what interests me most — understanding how a system moves from an idea and an architecture toward something that can actually run in hardware.
Building systems, learning the layers underneath them, and documenting the process along the way.