FreeRTOS support

.github/workflows/main.yml

@@ -11,6 +11,8 @@ jobs:
           - sim_alu
           - sim_inst_immediate_decode
           - sim_load_store
+          - sim_csr
+          - sim_mtimer
           # sim_cpu is not a testbench, but a target for RISCOF testing, so it
           # is not included here
     uses: ./.github/workflows/simulate.yml
@@ -21,19 +23,29 @@ jobs:
     strategy:
       matrix:
         target:
-          - sim_memory
           - sim_top
     uses: ./.github/workflows/simulate.yml
     with:
       project: crush_example
       target: ${{ matrix.target }}
+  verilog-sim-crush-example-freertos-cpu:
+    uses: ./.github/workflows/simulate.yml
+    with:
+      project: crush_example_freertos
+      target: sim_cpu
+  verilog-sim-crush-example-freertos-top:
+    uses: ./.github/workflows/simulate.yml
+    with:
+      project: crush_example_freertos
+      target: sim_top
+      timeout-minutes: 10
   verilog-lint:
     runs-on: ubuntu-22.04
     container:
       image: barabas5532/crush-ci:5
     strategy:
       matrix:
-        project: [crush, crush_example]
+        project: [crush, crush_example, crush_example_freertos]
     steps:
       - uses: actions/checkout@v4
         with:
@@ -77,6 +89,9 @@ jobs:
     runs-on: ubuntu-22.04
     container:
       image: barabas5532/crush-ci:5
+    strategy:
+      matrix:
+        project: [crush_example, crush_example_freertos]
     steps:
       - uses: actions/checkout@v4
         with:
@@ -94,24 +109,23 @@ jobs:
         timeout-minutes: 1
         run: |
           . script/init.sh
-          fusesoc --verbose run crush_example
+          fusesoc --verbose run ${{ matrix.project }}
   firmware:
     runs-on: ubuntu-22.04
+    strategy:
+      matrix:
+        path:
+          - crush_example/fw
+          - crush_example_freertos/fw/spi_bootloader
+          - crush_example_freertos/fw/app
     container:
       image: barabas5532/crush-ci:5
     defaults:
       run:
-        working-directory: crush_example/fw
+        working-directory: ${{ matrix.path }}
     steps:
       - uses: actions/checkout@v4
       - name: Configure
         run: cmake -B build -G Ninja -DCMAKE_TOOLCHAIN_FILE=TC-crush.cmake
       - name: Build
         run: cmake --build build
-      - uses: actions/upload-artifact@v4
-        with:
-          name: firmware-elf
-          path: |
-            fw/build/crush-blinky
-            fw/build/crush-blinky.bin
-            fw/build/crush-blinky.data

.github/workflows/simulate.yml

@@ -9,6 +9,10 @@ on:
       target:
         required: true
         type: string
+      timeout-minutes:
+        default: 1
+        required: false
+        type: number
 
 jobs:
   simulate:
@@ -29,7 +33,7 @@ jobs:
           # also use the venv.
           echo PATH=$PATH >> $GITHUB_ENV
       - name: Run simulation
-        timeout-minutes: 1
+        timeout-minutes: ${{ inputs.timeout-minutes }}
         run: |
           . script/init.sh
           fusesoc run --target ${{ inputs.target }} --resolve-env-vars-early ${{ inputs.project }}

.gitignore

@@ -2,3 +2,4 @@
 build
 
 fusesoc.conf
+fusesoc_libraries

README.md

@@ -24,3 +24,64 @@ Goals:
 | [verible](https://github.com/chipsalliance/verible) | Standard LSP linter that can integrate with most text editors. |
 | [FuseSoC](https://github.com/olofk/fusesoc) | Build tool that simplifies running the testbenches and synthesis tools. |
 | [RISCOF, a RISC-V Architectural Test Framework](https://github.com/riscv-software-src/riscof) | The design passes all tests provided by RISCOF. See the `tools/compliance` folder. |
+
+## Demo SoCs
+
+### Basic Configuration (module top)
+
+#### Boot process
+
+All firmware executes directly from configurable block RAM. There is no support
+for booting from flash. The block RAM stores both the executable code and the
+system RAM.
+
+#### Vectors
+
+| Vector | Address     |
+|--------|-------------|
+| Reset  | 0x1000_0000 |
+
+
+#### Memory Map
+
+| Address     | Size (bytes) | Description |
+|-------------|--------------|-------------|
+| 0x1000_0000 | 8192         | Block RAM   |
+| 0x4000_0000 |              | GPIO        |
+
+### RTOS configuration (module top_freertos)
+
+#### Boot process
+
+The first stage bootloader stored in block RAM copies program data from flash to
+RAM, then jumps to the "Boot entry" vector at the top of RAM (0x1000_0000).
+After the bootloader completes, the application runs from SPRAM and the flash is
+not used any more.
+
+#### Vectors
+
+| Vector               | Address     |
+|----------------------|-------------|
+| Reset                | 0x0000_0000 |
+| Bootloader app entry | 0x1000_0000 |
+| Interrupt            | 0x1000_0100 |
+
+#### Memory Map
+
+| Address     | Size (bytes) | Description    |
+|-------------|--------------|----------------|
+| 0x0000_0000 | 1024         | Boot block RAM |
+| 0x1000_0000 | 65536        | SPRAM          |
+| 0x3000_0000 |              | mtimer         |
+| 0x4000_0000 |              | GPIO           |
+| 0x5000_0000 |              | SPI            |
+
+## References
+
+The SPI flash bootloader is based on the following open source libraries:
+
+https://github.com/no2fpga/no2bootloader
+
+https://github.com/chipsalliance/VeeRwolf
+
+https://github.com/olofk/simple_spi

crush/crush.core

@@ -11,6 +11,7 @@ filesets:
       - rtl/inst_decode_registers.v
       - rtl/inst_immediate_decode.v
       - rtl/memory_infer.v: {file_type: systemVerilogSource}
+      - rtl/mtimer.v
       - rtl/params.vh: {is_include_file: true}
       - rtl/program_counter.v
       - rtl/registers.v
@@ -20,26 +21,38 @@ filesets:
     files:
      - sim/inst_immediate_decode_tb.v
     file_type: systemVerilogSource
-    depend: [crush_support]
+    depend: [crush_testing]
 
   sim_alu:
     files:
      - sim/alu_tb.v
     file_type: systemVerilogSource
-    depend: [crush_support]
+    depend: [crush_testing]
 
   sim_load_store:
     files:
      - sim/load_store_tb.v
     file_type: systemVerilogSource
-    depend: [crush_support]
+    depend: [crush_testing]
 
   sim_cpu:
     files:
      - sim/control.v
      - sim/cpu_tb.v
     file_type: systemVerilogSource
 
+  sim_csr:
+    files:
+     - sim/csr_tb.v
+    file_type: systemVerilogSource
+    depend: [crush_testing]
+
+  sim_mtimer:
+    files:
+     - sim/mtimer_tb.v
+    file_type: systemVerilogSource
+    depend: [crush_testing]
+
   verilator_waiver:
     files:
       - ../data/verilator_waiver.vlt
@@ -55,6 +68,8 @@ targets:
         iverilog_options:
           - "-g2012"
           - "-gassertions"
+    parameters:
+      - MACHINE_MODE
 
   lint:
     default_tool : verilator
@@ -102,3 +117,24 @@ targets:
     toplevel: cpu_tb
     default_tool: icarus
 
+  sim_csr:
+    <<: *default
+    filesets_append:
+      - sim_csr
+    toplevel: csr_tb
+    default_tool: icarus
+    parameters:
+      - MACHINE_MODE=true
+
+  sim_mtimer:
+    <<: *default
+    filesets_append:
+      - sim_mtimer
+    toplevel: mtimer_tb
+    default_tool: icarus
+
+parameters:
+  MACHINE_MODE:
+    datatype   : bool
+    description: Enables machine privilege mode features
+    paramtype  : vlogdefine

crush/rtl/alu.v

@@ -21,14 +21,19 @@ module alu (
   wire [31:0] B_immediate;
   wire [31:0] U_immediate;
   wire [31:0] J_immediate;
+  // False positive, because only used in machine mode
+  // verilator lint_off UNUSEDSIGNAL
+  wire [31:0] CSR_immediate;
+  // verilator lint_on UNUSEDSIGNAL
 
   inst_immediate_decode immediate_decode (
       .inst(instruction),
       .I_immediate(I_immediate),
       .S_immediate(S_immediate),
       .B_immediate(B_immediate),
       .U_immediate(U_immediate),
-      .J_immediate(J_immediate)
+      .J_immediate(J_immediate),
+      .CSR_immediate(CSR_immediate)
   );
 
   wire [6:0] opcode = instruction[6:0];
@@ -78,6 +83,17 @@ module alu (
       OPCODE_STORE:  out = op_a + S_immediate;
       OPCODE_JAL:    out = pc + J_immediate;
       OPCODE_JALR:   out = (op_a + I_immediate) & ~1;
+`ifdef MACHINE_MODE
+      OPCODE_SYSTEM: case(funct3)
+            FUNCT3_CSRRW: out = op_a;
+            FUNCT3_CSRRWI: out = CSR_immediate;
+            FUNCT3_CSRRC: out = op_a & ~op_b;
+            FUNCT3_CSRRCI: out = op_a & ~CSR_immediate;
+            FUNCT3_CSRRS: out = op_a | op_b;
+            FUNCT3_CSRRSI: out = op_a | CSR_immediate;
+            default: ;
+      endcase
+`endif
       default: ;
     endcase
   end