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Angelo-EEE/README.md

Hi there 👋

I'm Angelo, an Electronic and Electrical Engineering student based in the UK.

I like designing and building anything that piques my interest.

I love being hands on and involved.

My main interest right now is using FPGAs to design and implement real-time, low level hardware solutions, although right now I am still a beginner who is learning 😅.

For my final year dissertation project, I am aiming to build a real-time single degree of freedom prosthetic elbow. I acquire EMG signals from the biceps, triceps and front deltoid and use an FPGA for quick DSP and signal conditioning to output a PWM signal to a servo motor which will control the joint🔧.

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  1. FPGA-UART-Loopback--VHDL FPGA-UART-Loopback--VHDL Public

    A complete VHDL UART transceiver and loopback interface featuring 2-stage input synchronization, mid-bit oversampling, framing error detection, and an integrated FIFO buffer.

    VHDL 1

  2. VHDL-Code-for-NAND2TETRIS-Elementary-Gates-Memory-and-ALU VHDL-Code-for-NAND2TETRIS-Elementary-Gates-Memory-and-ALU Public

    VHDL code and testbenches for the elementary gates, memory and ALU of the NAND2TETRIS course. This was a learning experience and was my first time programming in VHDL.

    VHDL