ECE @ IIIT Hyderabad. I work at the intersection of computer architecture, compiler infrastructure, and high-performance computing (HPC). My focus is on RISC-V, custom AI silicon, and building computational systems that are heavily optimized from the algorithm down to the hardware level.
LLVM Project
- #188004 — [CIR][CUDA][HIP] Stream-per-thread kernel launch support
- #184444 — [CIR] CUDA mangling tests with CIR and OG CodeGen verification
- #183998 — [CIR] Upstream basic CodeGen tests from incubator
RISC-V & Custom Silicon
- riscv-perf-model #284 — Git SHA tracking & version reproducibility in official Olympia simulator output.
- tt-metal #39781 — RT-DETR bringup on Tenstorrent Wormhole N300 (49.8 mAP on COCO val2017).
RISC-V 5-Stage Pipeline & C++17 ISS
Designed a 64-bit pipelined RV64I core in Verilog achieving a 2.69× clock improvement (286 MHz) with 75% stall reduction via data forwarding. Architected a cycle-accurate C++17 Instruction Set Simulator (ISS) as a golden reference model for RTL verification.
Recourse-ATS (Explainable AI)
Built an explainable resume screening system using GAT + MoE fusion. Implemented SHAP and Integrated Gradients attribution for fairness auditing and transparency in algorithmic hiring.
Neural Machine Translation (PyTorch)
Architected a complete Transformer model from scratch (Multi-Head Self-Attention, Positional Encoding). Achieved a BLEU score of 26.97, outperforming baseline seq2seq RNNs by 23%.
Languages: C/C++ (C++17) · Python · Verilog · SystemVerilog · RISC-V Assembly · Bash
Infrastructure & Compilers: LLVM IR · CMake · Make · Git · Vivado
Frameworks & HPC: PyTorch · RVV Intrinsics (Vector Math)