testbench.v

// ============================================================
// CPU Testbench
// Tests: arithmetic, logic, memory, branches, register ops, HLT
// ============================================================
module testbench;
    reg clk, rst;
    wire halted;
    wire [7:0]  dbg_pc;
    wire [15:0] dbg_ir, dbg_acc;
    wire [2:0]  dbg_state;

    cpu dut(
        .clk(clk), .rst(rst),
        .halted(halted),
        .dbg_pc(dbg_pc),
        .dbg_ir(dbg_ir),
        .dbg_acc(dbg_acc),
        .dbg_state(dbg_state)
    );

    // --------------------------------------------------------
    // Clock: period = 10, negedges at 5, 15, 25, ...
    // --------------------------------------------------------
    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end

    // --------------------------------------------------------
    // Memory layout:
    //   0x00-0x1D: Tests 1-6 (arithmetic, logic, branches)
    //   0x1E:      JMP 0x40
    //   0x40-0x4E: Test 7 (register ops)
    //   0x4F:      HLT
    //   0x80:      data = 10
    //   0x81:      data = 20
    // --------------------------------------------------------
    integer i;
    initial begin
        // Zero all memory
        for (i = 0; i < 256; i = i + 1)
            dut.mem.r1.mem[i] = 16'b0;

        // ==================== PROGRAM ====================

        // ---- Test 1: basic arithmetic ----
        dut.mem.r1.mem[16'h00] = 16'h1080;   // LDA  0x80     ACC = 10
        dut.mem.r1.mem[16'h01] = 16'h3081;   // ADD  0x81     ACC = 10+20 = 30
        dut.mem.r1.mem[16'h02] = 16'h2082;   // STA  0x82     mem[0x82] = 30
        dut.mem.r1.mem[16'h03] = 16'h4081;   // SUB  0x81     ACC = 30-20 = 10
        dut.mem.r1.mem[16'h04] = 16'h2083;   // STA  0x83     mem[0x83] = 10

        // ---- Test 2: logic ----
        dut.mem.r1.mem[16'h05] = 16'h5080;   // AND  0x80     ACC = 10 & 10 = 10
        dut.mem.r1.mem[16'h06] = 16'h6080;   // XOR  0x80     ACC = 10 ^ 10 = 0
        dut.mem.r1.mem[16'h07] = 16'h7081;   // OR   0x81     ACC = 0 | 20 = 20
        dut.mem.r1.mem[16'h08] = 16'h8000;   // NOT           ACC = ~20 = 0xFFEB
        dut.mem.r1.mem[16'h09] = 16'h9000;   // INC           ACC = 0xFFEC
        dut.mem.r1.mem[16'h0A] = 16'hA000;   // DEC           ACC = 0xFFEB

        // ---- Reset ACC to 10 ----
        dut.mem.r1.mem[16'h0B] = 16'h1080;   // LDA  0x80     ACC = 10

        // ---- Test 3: branch NOT taken ----
        dut.mem.r1.mem[16'h0C] = 16'hC00E;   // JEQ  0x0E     ACC=10 -> NOT taken
        dut.mem.r1.mem[16'h0D] = 16'h9000;   // INC           ACC = 11          (runs)
        dut.mem.r1.mem[16'h0E] = 16'h2084;   // STA  0x84     mem[0x84] = 11
        dut.mem.r1.mem[16'h0F] = 16'hD012;   // JLT  0x12     ACC=11 -> NOT taken
        dut.mem.r1.mem[16'h10] = 16'h1081;   // LDA  0x81     ACC = 20
        dut.mem.r1.mem[16'h11] = 16'hA000;   // DEC           ACC = 19

        // ---- Test 4: JGT taken ----
        dut.mem.r1.mem[16'h12] = 16'hE014;   // JGT  0x14     ACC=19 -> TAKEN
        dut.mem.r1.mem[16'h13] = 16'h2085;   // STA  0x85     SKIPPED
        dut.mem.r1.mem[16'h14] = 16'h2086;   // STA  0x86     mem[0x86] = 19

        // ---- Test 5: JEQ taken ----
        dut.mem.r1.mem[16'h15] = 16'h1080;   // LDA  0x80     ACC = 10
        dut.mem.r1.mem[16'h16] = 16'h4080;   // SUB  0x80     ACC = 10-10 = 0
        dut.mem.r1.mem[16'h17] = 16'hC01A;   // JEQ  0x1A     ACC=0 -> TAKEN
        dut.mem.r1.mem[16'h18] = 16'h9000;   // INC           SKIPPED
        dut.mem.r1.mem[16'h19] = 16'h9000;   // INC           SKIPPED
        dut.mem.r1.mem[16'h1A] = 16'hA000;   // DEC           ACC = -1 (0xFFFF)

        // ---- Test 6: JLT taken ----
        dut.mem.r1.mem[16'h1B] = 16'hD01D;   // JLT  0x1D     ACC<0 -> TAKEN
        dut.mem.r1.mem[16'h1C] = 16'h9000;   // INC           SKIPPED
        dut.mem.r1.mem[16'h1D] = 16'h2087;   // STA  0x87     mem[0x87] = 0xFFFF

        // ---- Jump to register test ----
        dut.mem.r1.mem[16'h1E] = 16'hB040;   // JMP  0x40

        // ==================== Test 7: register ops @ 0x40 ====================
        // Register encoding: IR[15:12]=op=0  IR[11:8]=subop  IR[7:5]=reg
        //   subop=1 = ACC_TO_REG Rd   subop=2 = REG_TO_ACC Rs
        //   ACC_TO_REG R0 = 0b_0000_0001_000_00000 = 0x0100
        //   ACC_TO_REG R1 = 0b_0000_0001_001_00000 = 0x0120
        //   REG_TO_ACC R0 = 0b_0000_0010_000_00000 = 0x0200
        dut.mem.r1.mem[16'h40] = 16'h1080;   // LDA  0x80          ACC = 10
        dut.mem.r1.mem[16'h41] = 16'h0100;   // ACC_TO_REG R0      reg[0] = 10
        dut.mem.r1.mem[16'h42] = 16'h1081;   // LDA  0x81          ACC = 20
        dut.mem.r1.mem[16'h43] = 16'h0120;   // ACC_TO_REG R1      reg[1] = 20
        dut.mem.r1.mem[16'h44] = 16'h0200;   // REG_TO_ACC R0      ACC = reg[0] = 10
        dut.mem.r1.mem[16'h45] = 16'h3081;   // ADD  0x81          ACC = 10+20 = 30
        dut.mem.r1.mem[16'h46] = 16'h2088;   // STA  0x88          mem[0x88] = 30

        // ---- Halt ----
        dut.mem.r1.mem[16'h4F] = 16'hF000;   // HLT

        // ==================== DATA ====================
        dut.mem.r1.mem[16'h80] = 16'd10;      // data[0x80] = 10
        dut.mem.r1.mem[16'h81] = 16'd20;      // data[0x81] = 20
    end

    // --------------------------------------------------------
    // Run simulation
    // --------------------------------------------------------
    initial begin
        $dumpfile("dump.vcd");
        $dumpvars(0, testbench);

        $display("========================================================");
        $display("  16-bit CPU Testbench");
        $display("  6-cycle per instruction (F1 F2 F3 E1 E2 E3)");
        $display("  negedge clock");
        $display("========================================================");

        // Reset (hold active past first negedge at t=5)
        rst = 1;
        #12;
        rst = 0;

        // Monitor
        $monitor("%4t: PC=%0d  st=%b  IR=%h  ACC=%h  halted=%b",
                  $time, dut.PC, dut.state, dut.IR, dut.ACC, halted);

        // Wait for halt
        wait (halted);
        #10;

        // ========================================================
        // Results
        // ========================================================
        $display("========================================================");
        $display("  RESULTS");
        $display("========================================================");
        $display("  ACC        = %h (%0d)", dut.ACC, dut.ACC);
        $display("  mem[0x82]  = %h  (expect 30)",    dut.mem.r1.mem[16'h82]);
        $display("  mem[0x83]  = %h  (expect 10)",    dut.mem.r1.mem[16'h83]);
        $display("  mem[0x84]  = %h  (expect 0B)",    dut.mem.r1.mem[16'h84]);
        $display("  mem[0x85]  = %h  (expect 00)",    dut.mem.r1.mem[16'h85]);
        $display("  mem[0x86]  = %h  (expect 13)",    dut.mem.r1.mem[16'h86]);
        $display("  mem[0x87]  = %h  (expect FFFF)",  dut.mem.r1.mem[16'h87]);
        $display("  mem[0x88]  = %h  (expect 30)",    dut.mem.r1.mem[16'h88]);
        $display("  reg[0]     = %h  (expect 0A)",    dut.regfile.regs[0]);
        $display("  reg[1]     = %h  (expect 14)",    dut.regfile.regs[1]);
        $display("--------------------------------------------------------");

        // Check
        if (dut.mem.r1.mem[16'h82] === 16'd30 &&
            dut.mem.r1.mem[16'h83] === 16'd10 &&
            dut.mem.r1.mem[16'h84] === 16'd11 &&
            dut.mem.r1.mem[16'h85] === 16'd0  &&
            dut.mem.r1.mem[16'h86] === 16'd19 &&
            dut.mem.r1.mem[16'h87] === 16'hFFFF &&
            dut.mem.r1.mem[16'h88] === 16'd30 &&
            dut.regfile.regs[0] === 16'd10 &&
            dut.regfile.regs[1] === 16'd20)
            $display("  *** ALL TESTS PASSED ***");
        else
            $display("  *** SOME TESTS FAILED ***");

        $display("========================================================");
        $finish;
    end
endmodule