ALU_inst.v

module ALUinst(
    input [3:0] op,
    input [3:0] subop,
    input [2:0] state,
    output reg u,
    output reg op0,
    output reg op1,
    output reg ze,
    output reg sw,
    output reg lt,
    output reg eq,
    output reg gt,
    output reg Aw,
    output reg wr,
    output reg re,
    output reg load_acc,
    output reg reg_wr_en,
    output reg sel_reg   // 1 = route reg_rd_data to ALU.in2
);

always @(*) begin
    // defaults: all off
    u = 0; op0 = 0; op1 = 0; ze = 0; sw = 0;
    lt = 0; eq = 0; gt = 0;
    Aw = 0; wr = 0; re = 0; load_acc = 0;
    reg_wr_en = 0; sel_reg = 0;

    case (state)
        // ========== FETCH1: load PC into address register ==========
        3'b000: begin
            Aw = 1;
        end

        // ========== FETCH2: read instruction from memory ==========
        3'b001: begin
            re = 1;
        end

        // ========== FETCH3: IR is latched, PC inc ==========
        3'b010: begin
            // cpu.v handles IR load and PC increment
        end

        // ========== EXEC1 ==========
        3'b011: begin
            case (op)
                // ---- memory operations: set address ----
                4'b0001, // LDA
                4'b0011, // ADD
                4'b0100, // SUB
                4'b0101, // AND
                4'b0110, // XOR
                4'b0111, // OR
                4'b0010: // STA
                    Aw = 1;

                // ---- register-only ALU ----
                4'b1000: // NOT
                begin u=0; op0=1; op1=1; ze=0; load_acc=1; end

                4'b1001: // INC
                begin u=1; op0=1; op1=0; ze=0; load_acc=1; end

                4'b1010: // DEC
                begin u=1; op0=1; op1=1; ze=0; load_acc=1; end

                // ---- branches (set condition selects) ----
                4'b1100: // JEQ
                begin lt=0; eq=1; gt=0; end

                4'b1101: // JLT
                begin lt=1; eq=0; gt=0; end

                4'b1110: // JGT
                begin lt=0; eq=0; gt=1; end

                // ---- NOP / register sub-ops ----
                4'b0000: begin
                    if (subop == 4'b0001)      // ACC_TO_REG
                        reg_wr_en = 1;
                    else if (subop == 4'b0010) // REG_TO_ACC
                    begin sel_reg=1; u=1; op0=0; op1=0; ze=1; load_acc=1; end
                end
            endcase
        end

        // ========== EXEC2: memory read/write ==========
        3'b100: begin
            case (op)
                4'b0001, // LDA
                4'b0011, // ADD
                4'b0100, // SUB
                4'b0101, // AND
                4'b0110, // XOR
                4'b0111: // OR
                    re = 1;  // read operand data

                4'b0010: // STA
                    wr = 1;  // write ACC to memory
            endcase
        end

        // ========== EXEC3: latch ALU result (for mem-based ops) ==========
        3'b101: begin
            case (op)
                4'b0001: // LDA: ACC = 0 + mem[addr]
                begin u=1; op0=0; op1=0; ze=1; load_acc=1; end

                4'b0011: // ADD
                begin u=1; op0=0; op1=0; ze=0; load_acc=1; end

                4'b0100: // SUB
                begin u=1; op0=0; op1=1; ze=0; load_acc=1; end

                4'b0101: // AND
                begin u=0; op0=0; op1=0; ze=0; load_acc=1; end

                4'b0110: // XOR
                begin u=0; op0=0; op1=1; ze=0; load_acc=1; end

                4'b0111: // OR
                begin u=0; op0=1; op1=0; ze=0; load_acc=1; end

                // HLT: handled by cpu.v (check opcode in state 101)
            endcase
        end
    endcase
end

endmodule