From 9d8f535a91faae64fb248a0fb0f2768e62a72291 Mon Sep 17 00:00:00 2001 From: Evgeny Boger Date: Fri, 10 Jul 2026 16:36:29 +0300 Subject: [PATCH] arm64: dts: allwinner: wirenboard85x: park CPU at a boot-safe OPP across suspend MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On suspend-to-off resume, U-Boot SPL's board init runs before the resume branch and programs VDD-CPU to its 0.90 V cold-boot value (CONFIG_AXP_DCDC2_VOLT=900); BL31 then re-locks PLL_CPUX to the frequency the kernel parked at. Under schedutil the suspend-entry work (fs sync, freezing) spikes the load, so the kernel routinely parks at a 1.00-1.10 V OPP (up to 1416 MHz) — leaving the cluster up to 200 mV under-volted until cpufreq's resume rewrites the regulator ~2 s later. The resulting fetch/load transients during secondary bringup were the WB8 post-resume corruption family (fetch faults on valid code words, single-bit pointer flips, bringup lockups — always within ~2 s of resume, with retained-DRAM CRC clean on every failing cycle). Mark the 480 MHz OPP as the suspend OPP: cpufreq_generic_suspend() parks there before the PSCI call. 480 MHz is rated 0.90 V and present on every speed bin (opp-supported-hw 0x1f), so the parked frequency is safe at SPL's boot voltage even if the firmware-side fix is absent or the boot voltage changes. Costs a few hundred ms of resume latency until the governor revives. The primary fix is in BL31 (restores the recorded voltage before the recorded frequency); this is the kernel-side belt so firmware and kernel cannot skew apart. Co-Authored-By: Claude Fable 5 --- .../allwinner/sun50i-h616-wirenboard85x.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-wirenboard85x.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-wirenboard85x.dtsi index c9d81df23e05..9857ba04ce53 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-wirenboard85x.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-wirenboard85x.dtsi @@ -1662,3 +1662,20 @@ &iommu { status = "okay"; }; + +/* + * Suspend-to-off contract with the boot firmware: on resume, U-Boot + * SPL's board init runs before the resume branch and programs VDD-CPU + * to its 0.90 V cold-boot value (CONFIG_AXP_DCDC2_VOLT), and BL31 then + * restores the PLL frequency the kernel parked at. The OPP the kernel + * parks at across suspend must therefore be safe at 0.90 V on every + * speed bin. 480 MHz is 0.90 V-rated and bin-universal + * (opp-supported-hw 0x1f). The primary fix lives in BL31 (it restores + * the recorded voltage before the recorded frequency); this is the + * kernel-side belt in case firmware and kernel ever skew. + */ +&cpu_opp_table { + opp-480000000 { + opp-suspend; + }; +};