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Improve per-file dependency handling #1

Description

@undernorthernsky

At this time the generated rules suffer from the problem described here: http://mad-scientist.net/make/autodep.html

Specifically:

  • deps are always created
    Especially when you don't need/want them:
    • building from a clean tree
    • calling targets (make clean) that do not require deps
    • check ifneq "$(MAKECMDGOALS)" "clean" (in makefile.ng; this kind of hackery is simply _not good enough_)
  • we likely hit the no rule to make target trouble as well
    I've seen make simply stop somewhere in the build (File does not exist. File has not been updated. -- yes, thank you) more than once, sometimes it doesn't even deign to complain about it :-(
    In short: under certain conditions the currently generated rules can break, especially for parallel builds.
  • prerequisites of .d files
    Sometimes we need/want to force certain rules to be run even before generating dependencies; right now this has to be done manually (VERBATIM) usually resulting in somewhat fragile and repetitive rules (path components; checking for touchstone files instead of complete dependency information)

Actually we only need to run so early to avoid harmless errors (that look frightening anyway):

[mkdep]  foo/bar.cpp
foo/bar.cpp:9:23: fatal error: curl/curl.h: No such file or directory
compilation terminated.
  • modern compilers (gcc & clang) support single-pass compilation & dependency creation

We really want something like this:

SRC := $(wildcard *.c)
OBJ := $(SRC:%.c=%.o)
DEP := $(SRC:%.c=%.d)

all: a.out

clean:
    $(RM) -f $(OBJ) $(DEP) a.out

%.o: %.c
    $(CC) $(CFLAGS) $(CPPFLAGS) -MMD -MF"$(@:%.o=%.d)" -c -o $@ $<

a.out: $(OBJ)
    $(CC) -o $@ $^ $(LDFLAGS)

-include $(DEP)

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