From d3a8476161017f9d3aae63f3a0c9aee329d55bf7 Mon Sep 17 00:00:00 2001 From: Tynan McAuley Date: Mon, 27 Jul 2026 14:30:52 -0700 Subject: [PATCH] Bump inclusive LLC for sbus-cbus clocking fix See chipsalliance/rocket-chip-inclusive-cache#42. --- .../main/scala/config/fragments/SubsystemFragments.scala | 7 +++++++ generators/rocket-chip-inclusive-cache | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala index 287fb2501a..a007422a4d 100644 --- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala @@ -32,6 +32,13 @@ class WithInclusiveCacheExteriorBuffer(buffer: InclusiveCachePortParameters = In case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerExterior=buffer, bufOuterExterior=buffer) }) +// Customize the control crossing of the inclusive LLC. The LLC runs on the sbus domain, and the +// two control ports are driven by the cbus. Defaults to whatever crossing is already configured +// between sbus and cbus. +class WithInclusiveCacheCtrlCrossingType(xType: Option[ClockCrossingType] = None) extends Config((site, here, up) => { + case InclusiveCacheKey => up(InclusiveCacheKey).copy(ctrlXType = xType.getOrElse(site(SbusToCbusXTypeKey))) +}) + /** Use asynchronous reset for Rocket Chip's Debug Module. */ class WithAsyncResetRocketSubsystem extends Config((_, _, _) => { case SubsystemResetSchemeKey => ResetAsynchronous diff --git a/generators/rocket-chip-inclusive-cache b/generators/rocket-chip-inclusive-cache index 85420cf26f..813c837b99 160000 --- a/generators/rocket-chip-inclusive-cache +++ b/generators/rocket-chip-inclusive-cache @@ -1 +1 @@ -Subproject commit 85420cf26f9abcebf685f0d68d14189598943c19 +Subproject commit 813c837b9951655b704dfe4e96e18eeaac112709