Order of assembly and the staged bring-up that follows it. The rule behind the whole sequence: nothing is energised until the stage before it has been verified with the power off, and the ear is the very last load to be connected.
Read SAFETY.md first. Exact holes and net names live in board-map.md.
- Soldering iron, thin solder, side cutters, tweezers.
- Multimeter — continuity buzzer, resistance, DC volts, AC volts. Battery powered.
- A magnifier or a phone camera with zoom, for inspecting joints.
- A 4.7–10 kΩ resistor as a dummy load. Keep it in the parts box; every bring-up and every later diagnosis starts by putting the output into it instead of an ear.
- Optional but useful once: a cheap USB logic analyser to confirm bridge timing.
Measure every resistor before fitting it. Bags get mixed and colour bands get misread; the meter takes two seconds.
Diode-test every MOSFET and write down which leg is which. SOT-23→DIP adapters do not share a pinout, and getting this wrong is the single most expensive mistake in this project's history — see board-map.md. Procedure:
- Meter in diode mode.
- P-channel (BSS84, marked "PD"): red probe on drain, black on source → ≈0.6 V.
- N-channel (2N7002, marked "7002"): black on drain, red on source → ≈0.6 V.
- The gate reads open against everything.
- Record the result per device by adapter hole, and wire to that record, not to a datasheet.
ESD, seriously. Until the gate pull-downs are fitted, every gate floats and static kills parts silently. One BSS84 died exactly that way here. Ground yourself, hold adapters by the edges, and keep spares in foil.
Run the five buses in bare copper on the solder side: +12 V (column C), STAR/GND (column U), SRC (column S), OUTA (row 3), OUTB (row 25). Then check with the buzzer that each bus is continuous end to end and that no two buses ring against each other.
Fit Q1–Q6 in their rows, then the gate resistors: 10 kΩ high-side pull-ups to +12 V, the four 1 kΩ series resistors, and the four 100 kΩ pull-downs. The pull-downs matter as much as anything else here: they hold every gate at a known level while the ESP32 boots.
Then the shunt: Rs 47 Ω between S9 and U9, with the bottom at the ground star, and R_flt 10 kΩ from S10 to T10.
Two sweeps with the board completely dead.
Sweep 1 — no shorts. +12 V rail against ground: must not ring. Each bridge output (OUTA, OUTB) against +12 V and against ground: must not ring. SRC against ground: only through Rs, so ≈47 Ω, not a short.
Sweep 2 — every intended net rings. Walk the tables in board-map.md and confirm each connection: source to its bus, drain to its output row, gate to its resistor network, shifter drain to the high-side gate it drives.
Diode map. Re-check all six transistors in place, as in step 0. A device that was fine in the bag and is silent now died during soldering — replace it before applying power, never after.
Probe on metal legs and bare wire, not into board holes. Holes give false readings in both directions; that has produced phantom faults here more than once.
Five wires from the ESP32 to the power board — ground first, then GPIO4→J6, GPIO5→N22, GPIO6→O6, GPIO7→T22.
Ground first is not a stylistic preference. If the common ground is missing or comes last, the gate signals have no return path: the firmware runs, the status LED behaves, the 12 V is present, and the bridge does absolutely nothing. It looks exactly like a dead microcontroller.
- Set the boost converter's output with a multimeter before it is connected to anything: 12.0 V to start. Never past 20 V.
- Connect the 12 V rail and ground; leave the transformer disconnected.
- Power up. Watch the shunt and the transistors for heat, and measure the rail under load.
- With stimulation off, there should be essentially no current through Rs. With it on, the drop across Rs should be small and stable.
Anything that gets warm — power off immediately and go back to step 3. A cooking shunt means a permanent path from rail to ground, which almost always means a transistor is in backwards.
If you have a logic analyser, this is where it earns its price: probe GPIO4–7, capture, and confirm
- the phase period matches the configured frequency (40.10 ms at 25 Hz, measured here),
- the PWM carrier period (40 µs at 25 kHz),
- the low-side windows around the phases,
- Q1&Q3 overlap = 0 µs and Q2&Q4 overlap = 0 µs — no shoot-through,
- diagonals Q1↔Q4 and Q2↔Q3 line up.
Those are the numbers measured on this build. Doing this before any high-power work turns "I hope the logic is right" into a fact, and it costs one evening.
Fit T1's primary between H3 and H25. On the secondary build the ear network point to point: R_lim → Cb → node A, second lead → node B, Rb across A–B.
Before anything else, measure T1 primary↔secondary isolation. It must read OL / megohms. This is the barrier the entire safety argument depends on.
Then hang the 4.7–10 kΩ dummy load between A and B and run the stimulation:
- AC volts across the dummy load should rise with amplitude. Reference figures measured here: 0.7 V at 25 %, 1.0 V at 50 % into a bare dummy; 0.2 V at 50 % and 0.4 V at 100 % through the full ear network.
- DC volts across the dummy load must read ≈ 0. This is the charge-balance check from SAFETY.md.
On yourself, not on anyone else. Then:
- Two electrodes on one ear, a few millimetres apart, with fresh gel and no gel bridge between them.
- Amplitude from zero, upward slowly, to a clear but comfortable tingle. Stop at the first sign of anything on the list in SAFETY.md.
- Use the panel's threshold search (see control-panel.md) if you want the level recorded rather than guessed.
Any power-carrying wire gets a screw terminal, or a proper joint with strain relief. The single wire from the boost converter's OUT− to the ground star detached twice in two days. Both times the device looked dead in a way that pointed at the microcontroller.
If a joint has to be soldered: stranded wire, tin the whole end, aim for a cone rather than a ball (a ball is a cold joint), and put a blob of hot glue a centimetre back so that any pull lands on the glue and not on the solder.