CSE-306-Computer-Architecture Offline / Assignment on ALU, Floating Point Adder and 8 bit MIPS Datapath along with pipelining
Computer Architecture Projects
explore different implementations of adders and study their characteristics.
Hardware designs modelled with verilog
Contains codes and designs of computer architecture assignments
Contains the project resources of the course CSE306. These were group projects.
verilog files
IEEE-754 compliant FPU implementing single (32-bit) and double (64-bit) precision arithmetic, including add, subtract, multiply, and divide operations
floating point adder
Assignments done in CSE306 course offered by CSE, BUET
Half Precision Floating Point Adder in Verilog
Simulated and Synthesised an adder for the shortened (16-bit) version of the 32-bit IEEE 754 single-precision floating-point format using a State Machine.
32 bit floating point adder written in VHDL
This repository contains all home and lab assignments for the CSE 306 : Computer Architecture Sessional course, part of our Term-1, Level-3 curriculum. It applies theories from CSE 305 to implement different components of computer architecture..
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