From 231e4baf4c3fd775863cec7beadabdc9fb165ce5 Mon Sep 17 00:00:00 2001 From: Vivek Date: Fri, 18 Jul 2025 15:28:19 -0700 Subject: [PATCH 01/16] Integrate HW-MGMT 7.0040.4019 Changes (#489) Co-authored-by: Guohan Lu --- patch/kconfig-inclusions | 2 ++ 1 file changed, 2 insertions(+) diff --git a/patch/kconfig-inclusions b/patch/kconfig-inclusions index 3c12c44ea..d16bf051c 100644 --- a/patch/kconfig-inclusions +++ b/patch/kconfig-inclusions @@ -43,6 +43,8 @@ CONFIG_EEPROM_AT24=m CONFIG_AMD_XGBE=m CONFIG_IGB=m CONFIG_MLXSW_CORE=m +CONFIG_MARVELL_PHY=m +CONFIG_MARVELL_10G_PHY=m CONFIG_SERIAL_8250_DW=y CONFIG_HW_RANDOM_AMD=m CONFIG_I2C_CHARDEV=m From 0f9d50390453350ac6c7aadcd2d0a925ce0768c5 Mon Sep 17 00:00:00 2001 From: Saikrishna Arcot Date: Thu, 31 Jul 2025 09:05:58 -0700 Subject: [PATCH 02/16] Fix slave container used for master branch (#502) Use the master branch tag instead of the bookworm branch tag to get the slave container. Signed-off-by: Saikrishna Arcot --- .azure-pipelines/build-template.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.azure-pipelines/build-template.yml b/.azure-pipelines/build-template.yml index 2b4ebebc0..0cc2a8bef 100644 --- a/.azure-pipelines/build-template.yml +++ b/.azure-pipelines/build-template.yml @@ -42,7 +42,7 @@ jobs: timeoutInMinutes: ${{ parameters.timeout }} container: - image: sonicdev-microsoft.azurecr.io:443/${{ parameters.sonic_slave }}:bookworm + image: sonicdev-microsoft.azurecr.io:443/${{ parameters.sonic_slave }}:master steps: - checkout: self From 1fcf7e136ef7a2e5e75a3bd37ce37b6a8e654f02 Mon Sep 17 00:00:00 2001 From: byu343 Date: Thu, 31 Jul 2025 13:08:35 -0700 Subject: [PATCH 03/16] Fix for i2c_designware shutdown (#497) * Fix for i2c_designware shutdown Designware I2C driver was failing to probe the I2C controller after we kexec to another kernel on some Arista platforms: i2c_designware AMDI0010:00: Unknown Synopsys component type: 0xffffffff * Fix the patch header --------- Co-authored-by: StormLiangMS <89824293+StormLiangMS@users.noreply.github.com> Co-authored-by: Saikrishna Arcot --- ...river-arista-i2c-designware-shutdown.patch | 54 +++++++++++++++++++ patch/series | 1 + 2 files changed, 55 insertions(+) create mode 100644 patch/driver-arista-i2c-designware-shutdown.patch diff --git a/patch/driver-arista-i2c-designware-shutdown.patch b/patch/driver-arista-i2c-designware-shutdown.patch new file mode 100644 index 000000000..268d35a30 --- /dev/null +++ b/patch/driver-arista-i2c-designware-shutdown.patch @@ -0,0 +1,54 @@ +From: Justin Oliver +Date: 2022-12-12 17:42:20 +0000 +Subject: [PATCH] i2c: designware: Fix device probe failure after kexec + +The Designware I2C driver sometimes fails to probe the I2C controller after +we boot into another kernel with kexec. Kexec will call the `shutdown` +method of each platform driver before booting the new kernel so this patch +defines a `shutdown` procedure for the Designware I2C platform driver. This +will gracefully bring down the I2C controller, allowing the driver to +successfully initialize the device with the new kernel. + +This patch addresses the following error after kexec: +i2c_designware AMDI0010:00: Unknown Synopsys component type: 0xffffffff + +Signed-off-by: Justin Oliver +Signed-off-by: Karan Jagjitkumar +--- + drivers/i2c/busses/i2c-designware-platdrv.c | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c +index 01234567..89abcdef 100644 +--- a/drivers/i2c/busses/i2c-designware-platdrv.c ++++ b/drivers/i2c/busses/i2c-designware-platdrv.c +@@ -350,6 +350,21 @@ static int dw_i2c_plat_remove(struct platform_device *pdev) + return 0; + } + ++static void dw_i2c_plat_shutdown(struct platform_device *pdev) ++{ ++ struct dw_i2c_dev *dev = platform_get_drvdata(pdev); ++ ++ pm_runtime_get_sync(&pdev->dev); ++ ++ dev->disable(dev); ++ ++ pm_runtime_dont_use_autosuspend(&pdev->dev); ++ pm_runtime_put_sync(&pdev->dev); ++ dw_i2c_plat_pm_cleanup(dev); ++ ++ reset_control_assert(dev->rst); ++} ++ + #ifdef CONFIG_PM_SLEEP + static int dw_i2c_plat_prepare(struct device *dev) + { +@@ -425,6 +440,7 @@ MODULE_ALIAS("platform:i2c_designware"); + static struct platform_driver dw_i2c_driver = { + .probe = dw_i2c_plat_probe, + .remove = dw_i2c_plat_remove, ++ .shutdown = dw_i2c_plat_shutdown, + .driver = { + .name = "i2c_designware", + .of_match_table = of_match_ptr(dw_i2c_of_match), diff --git a/patch/series b/patch/series index 65294a20a..d95cf7520 100755 --- a/patch/series +++ b/patch/series @@ -10,6 +10,7 @@ driver-arista-net-tg3-access-regs-indirectly.patch driver-arista-pci-reassign-pref-mem.patch driver-arista-mmcblk-not-working-on-AMD-platforms.patch driver-arista-restrict-eMMC-drive-to-50Mhz-from-userland.patch +driver-arista-i2c-designware-shutdown.patch driver-support-sff-8436-eeprom.patch driver-support-sff-8436-eeprom-update.patch driver-sff-8436-use-nvmem-framework.patch From 271e3a5af162e8dc7b207dbb79b4ac8cee53b0d1 Mon Sep 17 00:00:00 2001 From: Vivek Date: Thu, 31 Jul 2025 16:06:25 -0700 Subject: [PATCH 04/16] Ignore table if the EFI memory attributes are corrupt (#500) Signed-off-by: vkarri Co-authored-by: Saikrishna Arcot --- ...e-table-if-the-size-is-clearly-bogus.patch | 66 +++++++++++++++++++ patch/series | 2 + 2 files changed, 68 insertions(+) create mode 100644 patch/0001-efi-memattr-Ignore-table-if-the-size-is-clearly-bogus.patch diff --git a/patch/0001-efi-memattr-Ignore-table-if-the-size-is-clearly-bogus.patch b/patch/0001-efi-memattr-Ignore-table-if-the-size-is-clearly-bogus.patch new file mode 100644 index 000000000..1fac195ec --- /dev/null +++ b/patch/0001-efi-memattr-Ignore-table-if-the-size-is-clearly-bogus.patch @@ -0,0 +1,66 @@ +From 8fbe4c49c0ccac9a6a3cff35a45fa55d4ae35d6e Mon Sep 17 00:00:00 2001 +From: Ard Biesheuvel +Date: Thu, 31 Oct 2024 18:58:23 +0100 +Subject: [PATCH] efi/memattr: Ignore table if the size is clearly bogus + +There are reports [0] of cases where a corrupt EFI Memory Attributes +Table leads to out of memory issues at boot because the descriptor size +and entry count in the table header are still used to reserve the entire +table in memory, even though the resulting region is gigabytes in size. + +Given that the EFI Memory Attributes Table is supposed to carry up to 3 +entries for each EfiRuntimeServicesCode region in the EFI memory map, +and given that there is no reason for the descriptor size used in the +table to exceed the one used in the EFI memory map, 3x the size of the +entire EFI memory map is a reasonable upper bound for the size of this +table. This means that sizes exceeding that are highly likely to be +based on corrupted data, and the table should just be ignored instead. + +[0] https://bugzilla.suse.com/show_bug.cgi?id=1231465 + +Cc: Gregory Price +Cc: Usama Arif +Acked-by: Jiri Slaby +Acked-by: Breno Leitao +Link: https://lore.kernel.org/all/20240912155159.1951792-2-ardb+git@google.com/ +Signed-off-by: Ard Biesheuvel +--- + drivers/firmware/efi/memattr.c | 18 +++++++++++++++++- + 1 file changed, 17 insertions(+), 1 deletion(-) + +diff --git a/drivers/firmware/efi/memattr.c b/drivers/firmware/efi/memattr.c +index 164203429fa7a3..c38b1a335590d4 100644 +--- a/drivers/firmware/efi/memattr.c ++++ b/drivers/firmware/efi/memattr.c +@@ -22,6 +22,7 @@ unsigned long __ro_after_init efi_mem_attr_table = EFI_INVALID_TABLE_ADDR; + int __init efi_memattr_init(void) + { + efi_memory_attributes_table_t *tbl; ++ unsigned long size; + + if (efi_mem_attr_table == EFI_INVALID_TABLE_ADDR) + return 0; +@@ -39,7 +40,22 @@ int __init efi_memattr_init(void) + goto unmap; + } + +- tbl_size = sizeof(*tbl) + tbl->num_entries * tbl->desc_size; ++ ++ /* ++ * Sanity check: the Memory Attributes Table contains up to 3 entries ++ * for each entry of type EfiRuntimeServicesCode in the EFI memory map. ++ * So if the size of the table exceeds 3x the size of the entire EFI ++ * memory map, there is clearly something wrong, and the table should ++ * just be ignored altogether. ++ */ ++ size = tbl->num_entries * tbl->desc_size; ++ if (size > 3 * efi.memmap.nr_map * efi.memmap.desc_size) { ++ pr_warn(FW_BUG "Corrupted EFI Memory Attributes Table detected! (version == %u, desc_size == %u, num_entries == %u)\n", ++ tbl->version, tbl->desc_size, tbl->num_entries); ++ goto unmap; ++ } ++ ++ tbl_size = sizeof(*tbl) + size; + memblock_reserve(efi_mem_attr_table, tbl_size); + set_bit(EFI_MEM_ATTR, &efi.flags); + diff --git a/patch/series b/patch/series index d95cf7520..016839f75 100755 --- a/patch/series +++ b/patch/series @@ -70,6 +70,8 @@ Support-for-fullcone-nat.patch # Tbridge-per-port-multicast-broadcast-flood-flags.patch # +0001-efi-memattr-Ignore-table-if-the-size-is-clearly-bogus.patch + # Mellanox patches for 5.10 ###-> mellanox_sdk-start 0001-psample-define-the-macro-PSAMPLE_MD_EXTENDED_ATTR.patch From 7a4859dc071eb8138e6a5b2b01daa9e0fc9e147e Mon Sep 17 00:00:00 2001 From: Philo Shao <135693886+micas-net@users.noreply.github.com> Date: Sat, 9 Aug 2025 00:14:59 +0800 Subject: [PATCH 05/16] tty/8250: Deactivate the HSUART DMA for the DNV CPU (#476) Intel DNV CPU reports an error, indicating that there is a possibility of abnormal serial port functionality and the CPU may hang. The HSUART DMA will be deactivated for the DNV CPU. --------- Co-authored-by: Saikrishna Arcot --- ...SUART-DMA-be-deactivated-for-DNV-CPU.patch | 45 +++++++++++++++++++ patch/series | 1 + 2 files changed, 46 insertions(+) create mode 100644 patch/0001-tty-8250-HSUART-DMA-be-deactivated-for-DNV-CPU.patch diff --git a/patch/0001-tty-8250-HSUART-DMA-be-deactivated-for-DNV-CPU.patch b/patch/0001-tty-8250-HSUART-DMA-be-deactivated-for-DNV-CPU.patch new file mode 100644 index 000000000..d6845a6c3 --- /dev/null +++ b/patch/0001-tty-8250-HSUART-DMA-be-deactivated-for-DNV-CPU.patch @@ -0,0 +1,45 @@ +From b63977b0e1421c641495940fafab9502a2a6d659 Mon Sep 17 00:00:00 2001 +From: Philo Shao +Date: Thu, 17 Apr 2025 02:17:18 -0500 +Subject: tty/8250: Deactivate the HSUART DMA for the DNV CPU + +Intel DNV CPU reports an error, indicating that there is a possibility of abnormal serial port functionality and the CPU may hang. +The HSUART DMA will be deactivated for the DNV CPU. + +Signed-off-by: Philo Shao +--- + drivers/tty/serial/8250/8250_mid.c | 18 +++++++++++------- + 1 file changed, 11 insertions(+), 7 deletions(-) + +diff --git a/drivers/tty/serial/8250/8250_mid.c b/drivers/tty/serial/8250/8250_mid.c +index 2cc78a4bf..e4a5d6358 100644 +--- a/drivers/tty/serial/8250/8250_mid.c ++++ b/drivers/tty/serial/8250/8250_mid.c +@@ -321,13 +321,17 @@ static int mid8250_probe(struct pci_dev *pdev, const struct pci_device_id *id) + if (!uart.port.membase) + return -ENOMEM; + +- ret = mid->board->setup(mid, &uart.port); +- if (ret) +- return ret; +- +- ret = mid8250_dma_setup(mid, &uart); +- if (ret) +- goto err; ++ if (id->device != PCI_DEVICE_ID_INTEL_DNV_UART) { ++ ret = mid->board->setup(mid, &uart.port); ++ if (ret) ++ return ret; ++ ++ ret = mid8250_dma_setup(mid, &uart); ++ if (ret) ++ goto err; ++ } else { ++ uart.port.handle_irq = dnv_handle_irq; ++ } + + ret = serial8250_register_8250_port(&uart); + if (ret < 0) +-- +2.25.1 + diff --git a/patch/series b/patch/series index 016839f75..15febe5a7 100755 --- a/patch/series +++ b/patch/series @@ -229,6 +229,7 @@ cisco-npu-disable-other-bars.patch # Micas patches 0001-fix-os-crash-caused-by-optoe-when-class-switch.patch +0001-tty-8250-HSUART-DMA-be-deactivated-for-DNV-CPU.patch # Fix to avoid kernel panic on Kernel 6.1.94 # https://github.com/sonic-net/sonic-buildimage/issues/20901 From 4bfb14aa3a2415cc922209cf0739e4931c129a46 Mon Sep 17 00:00:00 2001 From: Pavan Prakash <120486223+Pavan-Nokia@users.noreply.github.com> Date: Tue, 12 Aug 2025 13:50:12 -0400 Subject: [PATCH 06/16] arm64: dts: marvell: Remove HS400 as supported eMMC mode (#486) Remove HS400 as supported eMMC mode Issues being observed with the device not booting at cold start. Rootcause: Timing violations seen when using HS400 Mode as HS400 mode is not supported by sdhci-xenon-phy driver Verification: Modify EMMC mode to HS200 and try multiple boot up test throughout the supported operating temperature range of the device. Used oscilloscope to confirm that there are no timing violations. Signed-off-by: Pavan Prakash Co-authored-by: Saikrishna Arcot --- ...011-arm64-dts-marvell-Add-Nokia-7215-IXS-A1-board.patch | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/patch/0011-arm64-dts-marvell-Add-Nokia-7215-IXS-A1-board.patch b/patch/0011-arm64-dts-marvell-Add-Nokia-7215-IXS-A1-board.patch index 905315082..b50e18f55 100644 --- a/patch/0011-arm64-dts-marvell-Add-Nokia-7215-IXS-A1-board.patch +++ b/patch/0011-arm64-dts-marvell-Add-Nokia-7215-IXS-A1-board.patch @@ -11,9 +11,9 @@ Signed-off-by: Natarajan Subbiramani Tested-by: Natarajan Subbiramani Reviewed-by: Jon Goldberg --- - arch/arm64/boot/dts/marvell/7215-ixs-a1.dts | 226 ++++++++++++++++++++ + arch/arm64/boot/dts/marvell/7215-ixs-a1.dts | 225 ++++++++++++++++++++ arch/arm64/boot/dts/marvell/Makefile | 1 + - 2 files changed, 227 insertions(+) + 2 files changed, 226 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/7215-ixs-a1.dts diff --git a/arch/arm64/boot/dts/marvell/7215-ixs-a1.dts b/arch/arm64/boot/dts/marvell/7215-ixs-a1.dts @@ -21,7 +21,7 @@ new file mode 100644 index 000000000000..e683b7ca4c9c --- /dev/null +++ b/arch/arm64/boot/dts/marvell/7215-ixs-a1.dts -@@ -0,0 +1,226 @@ +@@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Nokia @@ -140,7 +140,6 @@ index 000000000000..e683b7ca4c9c + non-removable; + mmc-ddr-1_8v; + mmc-hs200-1_8v; -+ mmc-hs400-1_8v; +}; + +/*Delete nodes that are not available*/ From 9f6cc60663e227aafa8712cf76e2549c8585c04f Mon Sep 17 00:00:00 2001 From: Hemanth Kumar Tirupati Date: Thu, 28 Aug 2025 16:16:30 -0700 Subject: [PATCH 07/16] Add upstream fix for bridge link show failure (#509) Backport torvalds/linux@e92df79 into sonic-linux-kernel On SmartSwitch we see the following error when hostside PF interfaces (for DPUs) created by mlx5_core driver are present. root@sonic:/home/admin/# bridge vlan show port vlan-id *** *** RTNETLINK answers: Operation not permitted Dump terminated Similar error is seen for bridge link show command as well. This backport is expected to fix these issues. --- ...lure-for-non-eswitch-allowed-devices.patch | 45 +++++++++++++++++++ patch/series | 2 + 2 files changed, 47 insertions(+) create mode 100644 patch/0001-prevent-bridge-link-show-failure-for-non-eswitch-allowed-devices.patch diff --git a/patch/0001-prevent-bridge-link-show-failure-for-non-eswitch-allowed-devices.patch b/patch/0001-prevent-bridge-link-show-failure-for-non-eswitch-allowed-devices.patch new file mode 100644 index 000000000..750576465 --- /dev/null +++ b/patch/0001-prevent-bridge-link-show-failure-for-non-eswitch-allowed-devices.patch @@ -0,0 +1,45 @@ +From e92df790d07a8eea873efcb84776e7b71f81c7d5 Mon Sep 17 00:00:00 2001 +From: Carolina Jubran +Date: Tue, 11 Mar 2025 00:01:44 +0200 +Subject: [PATCH] net/mlx5e: Prevent bridge link show failure for + non-eswitch-allowed devices + +mlx5_eswitch_get_vepa returns -EPERM if the device lacks +eswitch_manager capability, blocking mlx5e_bridge_getlink from +retrieving VEPA mode. Since mlx5e_bridge_getlink implements +ndo_bridge_getlink, returning -EPERM causes bridge link show to fail +instead of skipping devices without this capability. + +To avoid this, return -EOPNOTSUPP from mlx5e_bridge_getlink when +mlx5_eswitch_get_vepa fails, ensuring the command continues processing +other devices while ignoring those without the necessary capability. + +Fixes: 4b89251de024 ("net/mlx5: Support ndo bridge_setlink and getlink") +Signed-off-by: Carolina Jubran +Reviewed-by: Jianbo Liu +Signed-off-by: Tariq Toukan +Reviewed-by: Michal Swiatkowski +Link: https://patch.msgid.link/1741644104-97767-7-git-send-email-tariqt@nvidia.com +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +index a814b63ed97e57..8fcaee381b0e09 100644 +--- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c ++++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +@@ -5132,11 +5132,9 @@ static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, + struct mlx5e_priv *priv = netdev_priv(dev); + struct mlx5_core_dev *mdev = priv->mdev; + u8 mode, setting; +- int err; + +- err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting); +- if (err) +- return err; ++ if (mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting)) ++ return -EOPNOTSUPP; + mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB; + return ndo_dflt_bridge_getlink(skb, pid, seq, dev, + mode, diff --git a/patch/series b/patch/series index 15febe5a7..ebc3574e6 100755 --- a/patch/series +++ b/patch/series @@ -71,6 +71,8 @@ Support-for-fullcone-nat.patch # 0001-efi-memattr-Ignore-table-if-the-size-is-clearly-bogus.patch +# Backport from v6.14 to v6.1.132 and v6.12.20 +0001-prevent-bridge-link-show-failure-for-non-eswitch-allowed-devices.patch # Mellanox patches for 5.10 ###-> mellanox_sdk-start From 3f93a0d05cb6a67801333a3cf09d1fc6b3eea740 Mon Sep 17 00:00:00 2001 From: eladnachman <87485227+eladnachman@users.noreply.github.com> Date: Wed, 10 Sep 2025 06:12:51 +0300 Subject: [PATCH 08/16] Kdump arm64 (#501) * Fix slave container used for master branch (#502) Use the master branch tag instead of the bookworm branch tag to get the slave container. Signed-off-by: Saikrishna Arcot * Fix for i2c_designware shutdown (#497) * Fix for i2c_designware shutdown Designware I2C driver was failing to probe the I2C controller after we kexec to another kernel on some Arista platforms: i2c_designware AMDI0010:00: Unknown Synopsys component type: 0xffffffff * Fix the patch header --------- Co-authored-by: StormLiangMS <89824293+StormLiangMS@users.noreply.github.com> Co-authored-by: Saikrishna Arcot * Ignore table if the EFI memory attributes are corrupt (#500) Signed-off-by: vkarri Co-authored-by: Saikrishna Arcot * i2c: mv64xxx: prevent illegal pointer access Spurious interrupts left while i2c controller still at RX or TX state would try to access the RX or TX buffer pointer, which is NULL. Add check to verify buffer pointer is not NULL before reading or writing the buffer for additional TX or RX operations. Signed-off-by: Elad Nachman * irqchip/mvebu-gicp: clear pending irqs on init For kexec case, left interrupt might generate spurious interrupts in various A7/A8/CN913x interrupt system from the I/O SB to the NB. Clear all pending interrupts when the driver is initialized to prevent these spurious interrupts. Signed-off-by: Elad Nachman --------- Signed-off-by: Saikrishna Arcot Signed-off-by: vkarri Signed-off-by: Elad Nachman Co-authored-by: Saikrishna Arcot Co-authored-by: byu343 Co-authored-by: StormLiangMS <89824293+StormLiangMS@users.noreply.github.com> Co-authored-by: Vivek --- patch/0018-i2c-mv64xxx-kdump-sonic.patch | 44 ++++++++++++++++++ patch/0019-mrvl-gicp-clr-irqs-on-probe.patch | 47 ++++++++++++++++++++ patch/series | 2 + 3 files changed, 93 insertions(+) create mode 100644 patch/0018-i2c-mv64xxx-kdump-sonic.patch create mode 100644 patch/0019-mrvl-gicp-clr-irqs-on-probe.patch diff --git a/patch/0018-i2c-mv64xxx-kdump-sonic.patch b/patch/0018-i2c-mv64xxx-kdump-sonic.patch new file mode 100644 index 000000000..0f08411e3 --- /dev/null +++ b/patch/0018-i2c-mv64xxx-kdump-sonic.patch @@ -0,0 +1,44 @@ +From 3c04dd543d85e6e087e7ad3147b47b3d6d702bdd Mon Sep 17 00:00:00 2001 +From: Elad Nachman +Date: Tue, 29 Jul 2025 11:09:46 +0300 +Subject: [PATCH v2 1/1] i2c: mv64xxx: prevent illegal pointer access + +Spurious interrupts left while i2c controller still at RX or TX state +would try to access the RX or TX buffer pointer, which is NULL. +Add check to verify buffer pointer is not NULL before reading or writing +the buffer for additional TX or RX operations. + +Signed-off-by: Elad Nachman +--- + drivers/i2c/busses/i2c-mv64xxx.c | 10 +++++++--- + 1 file changed, 7 insertions(+), 3 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c +index 8fc26a511320..e6baa9c520b4 100644 +--- a/drivers/i2c/busses/i2c-mv64xxx.c ++++ b/drivers/i2c/busses/i2c-mv64xxx.c +@@ -390,14 +390,18 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data) + break; + + case MV64XXX_I2C_ACTION_SEND_DATA: +- writel(drv_data->msg->buf[drv_data->byte_posn++], +- drv_data->reg_base + drv_data->reg_offsets.data); ++ if (drv_data->msg && drv_data->msg->buf) ++ writel(drv_data->msg->buf[drv_data->byte_posn++], ++ drv_data->reg_base + drv_data->reg_offsets.data); + writel(drv_data->cntl_bits, + drv_data->reg_base + drv_data->reg_offsets.control); + break; + + case MV64XXX_I2C_ACTION_RCV_DATA: +- drv_data->msg->buf[drv_data->byte_posn++] = ++ if (drv_data->msg && drv_data->msg->buf) ++ drv_data->msg->buf[drv_data->byte_posn++] = ++ readl(drv_data->reg_base + drv_data->reg_offsets.data); ++ else + readl(drv_data->reg_base + drv_data->reg_offsets.data); + writel(drv_data->cntl_bits, + drv_data->reg_base + drv_data->reg_offsets.control); +-- +2.25.1 + diff --git a/patch/0019-mrvl-gicp-clr-irqs-on-probe.patch b/patch/0019-mrvl-gicp-clr-irqs-on-probe.patch new file mode 100644 index 000000000..fef1e7624 --- /dev/null +++ b/patch/0019-mrvl-gicp-clr-irqs-on-probe.patch @@ -0,0 +1,47 @@ +From 21c4ec02660984feece49f1863245d48fc9774a7 Mon Sep 17 00:00:00 2001 +From: Elad Nachman +Date: Sun, 10 Aug 2025 12:48:23 +0300 +Subject: [PATCH v2 1/1] irqchip/mvebu-gicp: clear pending irqs on init + +When a kexec'ed kernel boots up, there might be stale unhandled interrupts +pending in the interrupt controller. These are delivered as spurious +interrupts once the boot CPU enables interrupts. +Clear all pending interrupts when the driver is initialized to prevent +these spurious interrupts from locking the CPU in an endless loop. + +Signed-off-by: Elad Nachman +--- + drivers/irqchip/irq-mvebu-gicp.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/irqchip/irq-mvebu-gicp.c b/drivers/irqchip/irq-mvebu-gicp.c +index d3232d6d8dce..4b2cad09bc71 100644 +--- a/drivers/irqchip/irq-mvebu-gicp.c ++++ b/drivers/irqchip/irq-mvebu-gicp.c +@@ -172,6 +172,7 @@ + struct device_node *node = pdev->dev.of_node; + struct device_node *irq_parent_dn; + int ret, i; ++ void __iomem *base; + + gicp = devm_kzalloc(&pdev->dev, sizeof(*gicp), GFP_KERNEL); + if (!gicp) +@@ -245,6 +246,15 @@ + + platform_set_drvdata(pdev, gicp); + ++ base = ioremap(gicp->res->start, resource_size(gicp->res)); ++ if (!base) { ++ dev_err(&pdev->dev, "ioremap() failed. Unable to clear pending interrupts.\n"); ++ } else { ++ for (i = 0; i < 64; i++) ++ writel(i, base + GICP_CLRSPI_NSR_OFFSET); ++ iounmap(base); ++ } ++ + return 0; + } + +-- +2.25.1 + diff --git a/patch/series b/patch/series index ebc3574e6..6ae936323 100755 --- a/patch/series +++ b/patch/series @@ -193,6 +193,8 @@ cisco-npu-disable-other-bars.patch 0015-arm64-dts-marvell-Add-Supermicro-SSE-G3748-board.patch 0016-arm64-dts-marvell-Add-Wistron-ES-1227-54TS-board.patch 0017-Extend-driver-to-support-XMC-XM25QH256C-device.patch +0018-i2c-mv64xxx-kdump-sonic.patch +0019-mrvl-gicp-clr-irqs-on-probe.patch # amd-pensando elba support 0000-Add-support-for-the-TI-TPS53659.patch From 15e4ad9ba9f625033e237c9e30e8f2aef8750f81 Mon Sep 17 00:00:00 2001 From: Brad House - NextHop Date: Sat, 18 Oct 2025 15:21:53 -0700 Subject: [PATCH 09/16] Secureboot modifications for ephemeral key signing (#499) The current sonic secureboot implementation assumes all assets are signed with the DB Key. There are roughly 3600 kernel modules that get signed in the process. Organizations may have varying security policy requirements where any signing requests may require signoff by one or more parties, this may simply be infeasible for that many requests. Given that the DB key may be a long-lived key, and only RSA 2048 is often used or available, it is a security best-practice to sign as few assets as possible with such a key. This is backwards-compatible so it can be applied prior to the sonic-buildimage patches. Co-authored-by: Brad House Co-authored-by: Saikrishna Arcot --- Makefile | 3 ++- manage-config | 12 ++++++------ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/Makefile b/Makefile index 4de8def18..cb1a4d059 100644 --- a/Makefile +++ b/Makefile @@ -11,6 +11,7 @@ CONFIGURED_ARCH ?= amd64 CONFIGURED_PLATFORM ?= vs SECURE_UPGRADE_MODE ?= SECURE_UPGRADE_SIGNING_CERT ?= +SECURE_UPGRADE_KERNEL_CAFILE ?= $(SECURE_UPGRADE_SIGNING_CERT) LINUX_HEADER_COMMON = linux-headers-$(KVERSION_SHORT)-common_$(KERNEL_VERSION)-$(KERNEL_SUBVERSION)_all.deb LINUX_HEADER_AMD64 = linux-headers-$(KVERSION)_$(KERNEL_VERSION)-$(KERNEL_SUBVERSION)_$(CONFIGURED_ARCH).deb @@ -104,7 +105,7 @@ $(addprefix $(DEST)/, $(MAIN_TARGET)): $(DEST)/% : # Optionally add/remove kernel options if [ -f ../manage-config ]; then - ../manage-config $(CONFIGURED_ARCH) $(CONFIGURED_PLATFORM) $(SECURE_UPGRADE_MODE) $(SECURE_UPGRADE_SIGNING_CERT) + ../manage-config $(CONFIGURED_ARCH) $(CONFIGURED_PLATFORM) $(SECURE_UPGRADE_MODE) $(SECURE_UPGRADE_KERNEL_CAFILE) fi # Building a custom kernel from Debian kernel source diff --git a/manage-config b/manage-config index 8478ba067..d09326e2e 100755 --- a/manage-config +++ b/manage-config @@ -27,7 +27,7 @@ ARCH=amd64 PLATFORM= SECURE_UPGRADE_MODE="no_sign" -SECURE_UPGRADE_SIGNING_CERT= +SECURE_UPGRADE_KERNEL_CAFILE= if [ $# -ge 1 ]; then ARCH=$1 fi @@ -38,7 +38,7 @@ if [ $# -ge 3 ]; then SECURE_UPGRADE_MODE=$3 fi if [ $# -ge 4 ]; then - SECURE_UPGRADE_SIGNING_CERT=$4 + SECURE_UPGRADE_KERNEL_CAFILE=$4 fi case "$ARCH" in @@ -163,12 +163,12 @@ ret_process_inc_ex=$? # Secure Boot support if [ $ret_process_inc_ex -eq 0 ]; then - echo "Secure Boot params: SECURE_UPGRADE_MODE=${SECURE_UPGRADE_MODE}, SECURE_UPGRADE_SIGNING_CERT=${SECURE_UPGRADE_SIGNING_CERT}" + echo "Secure Boot params: SECURE_UPGRADE_MODE=${SECURE_UPGRADE_MODE}, SECURE_UPGRADE_KERNEL_CAFILE=${SECURE_UPGRADE_KERNEL_CAFILE}" if [ ${SECURE_UPGRADE_MODE} == "dev" -o ${SECURE_UPGRADE_MODE} == "prod" ]; then echo "set kconfig-secure-boot-exclusions & kconfig-secure-boot-inclusions" - if [ ! -f "${SECURE_UPGRADE_SIGNING_CERT}" ]; then - echo "ERROR: SECURE_UPGRADE_SIGNING_CERT=${SECURE_UPGRADE_SIGNING_CERT} file does not exist" + if [ ! -f "${SECURE_UPGRADE_KERNEL_CAFILE}" ]; then + echo "ERROR: SECURE_UPGRADE_KERNEL_CAFILE=${SECURE_UPGRADE_KERNEL_CAFILE} file does not exist" exit 1 fi @@ -177,7 +177,7 @@ if [ $ret_process_inc_ex -eq 0 ]; then force_inclusion_file="../patch/kconfig-force-secure-boot-inclusions" # save the new pub key in kernel - sed -i "s|^CONFIG_SYSTEM_TRUSTED_KEYS=.*|CONFIG_SYSTEM_TRUSTED_KEYS=\"$SECURE_UPGRADE_SIGNING_CERT\"|g" ${inclusion_file} + sed -i "s|^CONFIG_SYSTEM_TRUSTED_KEYS=.*|CONFIG_SYSTEM_TRUSTED_KEYS=\"$SECURE_UPGRADE_KERNEL_CAFILE\"|g" ${inclusion_file} process_inclusion_exclusion_files ret_process_inc_ex=$? From 14cd5ce71680e33f467d1d132738f0be989735a1 Mon Sep 17 00:00:00 2001 From: JunhongMao <134556118+JunhongMao@users.noreply.github.com> Date: Sun, 19 Oct 2025 19:23:56 -0400 Subject: [PATCH 10/16] Enable TMP464 I2C Temperature Sensor for Nokia H6-64O. (#511) Co-authored-by: Guohan Lu --- patch/kconfig-inclusions | 1 + 1 file changed, 1 insertion(+) diff --git a/patch/kconfig-inclusions b/patch/kconfig-inclusions index d16bf051c..d8ca57cc0 100644 --- a/patch/kconfig-inclusions +++ b/patch/kconfig-inclusions @@ -162,6 +162,7 @@ CONFIG_SPI_GPIO=m CONFIG_SENSORS_INA3221=m # For Nokia CONFIG_RTC_DRV_DS1307=m +CONFIG_SENSORS_TMP464=m # For Nexthop CONFIG_PCI_STUB=y CONFIG_SENSORS_ADM1266=m From 255dc5281288781d836ffc4e497cbad7c9cd0953 Mon Sep 17 00:00:00 2001 From: yijingyan2 Date: Tue, 18 Nov 2025 03:32:54 +1100 Subject: [PATCH 11/16] Automated agent pool migration (#515) Signed-off-by: yijingyan2 --- .azure-pipelines/build-template.yml | 8 ++++---- azure-pipelines.yml | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/.azure-pipelines/build-template.yml b/.azure-pipelines/build-template.yml index 0cc2a8bef..1edc3b046 100644 --- a/.azure-pipelines/build-template.yml +++ b/.azure-pipelines/build-template.yml @@ -16,11 +16,11 @@ parameters: - name: pool type: string values: - - sonicbld-1es + - sonicso1ES-amd64 - sonicbld_8c - - sonicbld-arm64 - - sonicbld-armhf - default: sonicbld-1es + - sonicso1ES-arm64 + - sonicso1ES-armhf + default: sonicso1ES-amd64 - name: timeout type: number diff --git a/azure-pipelines.yml b/azure-pipelines.yml index e333e460f..41abd26d6 100644 --- a/azure-pipelines.yml +++ b/azure-pipelines.yml @@ -22,7 +22,7 @@ stages: - template: .azure-pipelines/build-template.yml parameters: arch: arm64 - pool: sonicbld-arm64 + pool: sonicso1ES-arm64 sonic_slave: sonic-slave-bookworm-arm64 artifact_name: sonic-linux-kernel.arm64 linux_deb_pattern: linux-image-*-unsigned_*deb @@ -30,7 +30,7 @@ stages: - template: .azure-pipelines/build-template.yml parameters: arch: armhf - pool: sonicbld-armhf + pool: sonicso1ES-armhf sonic_slave: sonic-slave-bookworm-armhf artifact_name: sonic-linux-kernel.armhf linux_deb_pattern: linux-image-*-armmp_*deb @@ -39,7 +39,7 @@ stages: parameters: arch: arm64 platform: pensando - pool: sonicbld-arm64 + pool: sonicso1ES-arm64 sonic_slave: sonic-slave-bookworm-arm64 artifact_name: sonic-linux-kernel.pensando.arm64 linux_deb_pattern: linux-image-*-unsigned_*deb From c3a089c9373843fdb6bd92cd28d4811d72abb7da Mon Sep 17 00:00:00 2001 From: Saikrishna Arcot Date: Mon, 24 Nov 2025 19:12:21 -0800 Subject: [PATCH 12/16] Update to 6.12.41 for Debian Trixie (#488) Update the kernel to 6.12.41, part of the 6.12 series kernel used in Debian Trixie. Additionally, with this, integrate SONiC-specific configs and patches into the build infra that Debian has set up for doing builds of different flavors and architectures of the kernel. There is room in that infra for downstream distributions to add in their own configs and patches. SONiC will use that portion of the infra to set custom kernel configs and include our patches there. --------- Signed-off-by: Saikrishna Arcot Signed-off-by: Yan Markman Co-authored-by: Yan Markman <32263981+yanmarkman@users.noreply.github.com> Co-authored-by: Tharigonda Rohini Kumar Co-authored-by: Hemanth Kumar Tirupati --- .azure-pipelines/build-template.yml | 34 +- Makefile | 78 +- azure-pipelines.yml | 32 +- config.local/amd64/config.sonic | 173 + config.local/amd64/config.sonic-secureboot | 12 + config.local/amd64/defines.toml | 6 + config.local/arm64/config.sonic | 42 + config.local/arm64/config.sonic-mellanox | 2 + config.local/arm64/config.sonic-pensando | 20 + config.local/arm64/config.sonic-secureboot | 12 + config.local/arm64/defines.toml | 6 + config.local/armhf/config.sonic | 3 + .../armhf/config.sonic-marvell-prestera | 22 + config.local/armhf/defines.toml | 6 + config.local/defines.toml | 22 + config.local/featureset-sonic/config | 19 + manage-config | 182 +- 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patch/0047-dt-bindings-trivial-devices-Add-infineon-xdpe1a2g7.patch => patches-sonic/0020-dt-bindings-trivial-devices-Add-infineon-xdpe1a2g7.patch (74%) rename {patch => patches-sonic}/0020-dts-pensando-add-mnet-and-mcrypt-devices.patch (100%) rename {patch => patches-sonic}/0021-drivers-soc-pensando-sbus-driver.patch (100%) rename patch/0050-leds-mlxreg-Skip-setting-LED-color-during-initializa.patch => patches-sonic/0021-leds-mlxreg-Skip-setting-LED-color-during-initializa.patch (82%) create mode 100644 patches-sonic/0022-arm64-dts-marvell-Add-DTS-for-cn9131-db-comexpress-trixie.patch rename {patch => patches-sonic}/0022-drivers-soc-pensando-boot_count-to-sysfs-for-kdump.patch (100%) rename patch/0052-i2c-mux-Add-register-map-based-mux-driver.patch => patches-sonic/0022-i2c-mux-Add-register-map-based-mux-driver.patch (90%) rename {patch => patches-sonic}/0023-arch-arm64-boot-dts-psci-support.patch (100%) rename patch/0053-platform-mellanox-Add-support-for-dynamic-I2C-channe.patch => patches-sonic/0023-platform-mellanox-Add-support-for-dynamic-I2C-channe.patch (89%) rename {patch => patches-sonic}/0024-drivers-soc-pensando-penfw-driver.patch (100%) rename patch/0055-mellanox-Relocate-mlx-platform-driver.patch => patches-sonic/0024-mellanox-Relocate-mlx-platform-driver.patch (64%) rename {patch => patches-sonic}/0025-dts-changes-for-mtfuji-and-lipari.patch (100%) create mode 100644 patches-sonic/0025-platform-mellanox-mlx-platform-Cosmetic-changes.patch rename {patch => patches-sonic}/0026-Add-support-for-new-qspi-macronix-flash-mx66u1g45g.patch (100%) create mode 100644 patches-sonic/0026-platform-mellanox-Rename-field-to-improve-code-reada.patch rename {patch => patches-sonic}/0027-pensando-add-rtc-cpld.patch (100%) rename patch/0089-platform-mellanox-mlx-platform-Change-register-name.patch => patches-sonic/0027-platform-mellanox-mlx-platform-Change-register-name.patch (70%) rename {patch => patches-sonic}/0028-Added-current-sensors-in-dtsi.patch (100%) rename {patch => patches-sonic}/0028-Create-miniaturised-diafgw-partition-for-128MB-flash.patch (100%) rename patch/0091-platform-mellanox-mlxreg-dpu-Add-initial-support-for.patch => patches-sonic/0028-platform-mellanox-mlxreg-dpu-Add-initial-support-for.patch (92%) rename {patch => patches-sonic}/0029-pcie-if-hotplug-enabled-do-immediate-reset-on-panic.patch (100%) create mode 100644 patches-sonic/0029-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch rename patch/0085-hwmon-mlxreg-fan-Separate-methods-of-fan-setting-com.patch => patches-sonic/0030-hwmon-mlxreg-fan-Separate-methods-of-fan-setting-com.patch (93%) rename patch/0087-platform-mellanox-indicate-deferred-I2C-bus-creation.patch => patches-sonic/0031-platform-mellanox-indicate-deferred-I2C-bus-creation.patch (70%) rename patch/0087-platform_data-mlxreg-Add-capability-bit-and-mask-fie.patch => patches-sonic/0032-platform_data-mlxreg-Add-capability-bit-and-mask-fie.patch (91%) rename patch/0088-platform-mellanox-mlxreg-hotplug-Add-support-for-new.patch => patches-sonic/0033-platform-mellanox-mlxreg-hotplug-Add-support-for-new.patch (85%) create mode 100644 patches-sonic/0034-platform-mellanox-Cosmetic-changes-to-improve-code-s.patch rename patch/0097-platform-mellanox-mlx-platform-Add-support-for-new-N.patch => patches-sonic/0035-platform-mellanox-mlx-platform-Add-support-for-new-N.patch (63%) create mode 100644 patches-sonic/0036-platform-mellanox-mlxreg-dpu-Fix-smatch-warnings.patch rename patch/0100-platform-mellanox-mlxreg-io-Extend-number-of-hwmon-a.patch => patches-sonic/0037-platform-mellanox-mlxreg-io-Extend-number-of-hwmon-a.patch (81%) rename patch/0101-platform_data-mlxreg-Add-fields-for-interrupt-storm-.patch => patches-sonic/0038-platform_data-mlxreg-Add-fields-for-interrupt-storm-.patch (90%) rename patch/0102-platform-mellanox-mlxreg-hotplug-Add-support-for-han.patch => patches-sonic/0039-platform-mellanox-mlxreg-hotplug-Add-support-for-han.patch (86%) rename patch/0103-platform-mellanox-mlx-dpu-improve-interrupt-handling.patch => patches-sonic/0040-platform-mellanox-mlxreg-dpu-Introduce-completion-ca.patch (74%) create mode 100644 patches-sonic/0041-hwmon-add-MP2869-MP29608-MP29612-and-MP29816-series-.patch create mode 100644 patches-sonic/0042-hwmon-add-MP29502-driver.patch rename patch/0093-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2855-c.patch => patches-sonic/0043-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2855-c.patch (95%) create mode 100644 patches-sonic/0044-platform_data-mlxreg-Add-non-sticky-bit-indication-f.patch create mode 100644 patches-sonic/0045-platform-mellanox-mlxreg-hotplug-Add-handling-of-non.patch create mode 100644 patches-sonic/0046-platform-mellanox-nvsw-bmc-Add-system-control-and-mo.patch create mode 100644 patches-sonic/0047-hwmon-mlxreg-fan-Prevent-fans-from-getting-stuck-at-.patch rename patch/0054-platform-mellanox-Introduce-support-for-switches-equ.patch => patches-sonic/0052-platform-mellanox-Introduce-support-for-switches-equ.patch (86%) create mode 100644 patches-sonic/0053-platform-mellanox-mlx-platform-Add-support-for-new-X.patch rename patch/0094-i2c-asf-Introduce-MCTP-support-over-ASF-controller.patch => patches-sonic/0054-i2c-asf-Introduce-MCTP-support-over-ASF-controller.patch (98%) rename patch/0099-platform-mellanox-Downstream-Add-support-DGX-flavor-.patch => patches-sonic/0055-platform-mellanox-Downstream-Add-support-DGX-flavor-.patch (88%) rename {patch => patches-sonic}/0195-platform-x86-MLX_PLATFORM-select-REGMAP-instead-of-d.patch (100%) rename {patch => patches-sonic}/0201-i2c-mlxbf-incorrect-base-address-passed-during-io-wr.patch (100%) rename {patch => patches-sonic}/0202-i2c-mlxbf-prevent-stack-overflow-in-mlxbf_i2c_smbus_.patch (100%) rename {patch => patches-sonic}/0204-i2c-mlxbf-Fix-frequency-calculation.patch (100%) rename {patch => patches-sonic}/0205-i2c-mlxbf-support-lock-mechanism.patch (100%) rename {patch => patches-sonic}/0265-hwmon-mlxreg-fan-Return-zero-speed-for-broken-fan.patch (100%) rename {patch => patches-sonic}/8000-mlxsw-Use-weak-reverse-dependencies-for-firmware-fla.patch (81%) create mode 100644 patches-sonic/8001-platform-mlx-platform-Downstream-Add-SPI-path-for-ra.patch rename patch/8003-mlxsw-i2c-SONIC-ISSU-Prevent-transaction-execution-f.patch => patches-sonic/8002-mlxsw-i2c-SONIC-ISSU-Prevent-transaction-execution-f.patch (92%) rename patch/8004-mlxsw-minimal-Downstream-Ignore-error-reading-SPAD-r.patch => patches-sonic/8003-mlxsw-minimal-Downstream-Ignore-error-reading-SPAD-r.patch (80%) rename patch/8005-leds-leds-mlxreg-Downstream-Send-udev-event-from-led.patch => patches-sonic/8004-leds-leds-mlxreg-Downstream-Send-udev-event-from-led.patch (86%) rename patch/8006-i2c-mlxcpld-Downstream-WA-to-avoid-error-for-SMBUS-r.patch => patches-sonic/8005-i2c-mlxcpld-Downstream-WA-to-avoid-error-for-SMBUS-r.patch (80%) rename patch/8007-hwmon-mlxreg-fan-Downstream-Allow-fan-speed-setting-.patch => patches-sonic/8006-hwmon-mlxreg-fan-Downstream-Allow-fan-speed-setting-.patch (91%) rename patch/8008-hwmon-emc2305-Downstream-Allow-fan-speed-setting-gra.patch => patches-sonic/8007-hwmon-emc2305-Downstream-Allow-fan-speed-setting-gra.patch (78%) rename patch/8009-hwmon-mlxsw-Downstream-Allow-fan-speed-setting-granu.patch => patches-sonic/8008-hwmon-mlxsw-Downstream-Allow-fan-speed-setting-granu.patch (87%) rename patch/8010-mlxsw-i2c-Downstream-Add-retry-mechanism-for-failed-.patch => patches-sonic/8009-mlxsw-i2c-Downstream-Add-retry-mechanism-for-failed-.patch (95%) rename patch/8011-mlxsw-minimal-Downstream-Disable-ethtool-interface.patch => patches-sonic/8010-mlxsw-minimal-Downstream-Disable-ethtool-interface.patch (75%) rename patch/8012-hwmon-pmbus-Downstream-Workaround-for-psu-attributes.patch => patches-sonic/8011-hwmon-pmbus-Downstream-Workaround-for-psu-attributes.patch (77%) create mode 100644 patches-sonic/8013-hwmon-pmbus-mp2975-Clear-interrupts-at-probe.patch create mode 100644 patches-sonic/8014-platform-mellanox-mlxreg-dpu-Debug-trace-for-dpu-pro.patch rename patch/0098-platform-mellanox-Downstream-Add-support-for-new-Nvi.patch => patches-sonic/9000-platform-mellanox-Downstream-Add-support-for-new-Nvi.patch (93%) rename {patch => patches-sonic}/PCI-ASPM-Fix-link-state-exit-during-switch-upstream.patch (100%) rename {patch => patches-sonic}/Support-for-fullcone-nat.patch (100%) rename {patch => patches-sonic}/bridge-per-port-multicast-broadcast-flood-flags.patch (100%) rename {patch => patches-sonic}/cisco-Enable-static-memory-reservation-for-OIRable-PCIe-de.patch (95%) rename {patch => patches-sonic}/cisco-acpi-spi-nor.patch (96%) rename {patch => patches-sonic}/cisco-add-support-for-ltc2979-chip.patch (100%) rename {patch => patches-sonic}/cisco-ds4424-null-of-node.patch (100%) rename {patch => patches-sonic}/cisco-hwmon-pmbus_core-pec-support-check.patch (100%) rename {patch => patches-sonic}/cisco-mdio-mux-support-acpi.patch (92%) rename {patch => patches-sonic}/cisco-mtd-part.patch (100%) rename {patch => patches-sonic}/cisco-npu-disable-other-bars.patch (91%) rename {patch => patches-sonic}/cisco-x86-gpio-config.patch (100%) rename {patch => patches-sonic}/driver-arista-i2c-designware-shutdown.patch (79%) rename {patch => patches-sonic}/driver-arista-mmcblk-not-working-on-AMD-platforms.patch (100%) rename {patch => patches-sonic}/driver-arista-net-tg3-access-regs-indirectly.patch (100%) rename {patch => patches-sonic}/driver-arista-net-tg3-disallow-broadcom-default-mac.patch (100%) rename {patch => patches-sonic}/driver-arista-net-tg3-dma-mask-4g-sb800.patch (95%) rename {patch => patches-sonic}/driver-arista-pci-reassign-pref-mem.patch (99%) rename {patch => patches-sonic}/driver-arista-restrict-eMMC-drive-to-50Mhz-from-userland.patch (100%) rename {patch => patches-sonic}/driver-at24-fix-odd-length-two-byte-access.patch (100%) rename {patch => patches-sonic}/driver-hwmon-lm75b-update.patch (100%) rename {patch => patches-sonic}/driver-hwmon-max6658-fix-write-convrate.patch (100%) rename {patch => patches-sonic}/driver-hwmon-pmbus-add-dps460-support.patch (100%) rename {patch => patches-sonic}/driver-hwmon-pmbus-dni_dps460-add-status-attributes.patch (100%) rename {patch => patches-sonic}/driver-hwmon-pmbus-dni_dps460-update-pmbus-core.patch (100%) rename {patch => patches-sonic}/driver-hwmon-pmbus-dni_dps460.patch (100%) rename {patch => patches-sonic}/driver-hwmon-pmbus-dps1900.patch (100%) rename {patch => patches-sonic}/driver-hwmon-pmbus-dps200.patch (100%) rename {patch => patches-sonic}/driver-hwmon-pmbus-ucd9200-mlnx.patch (100%) rename {patch => patches-sonic}/driver-i2c-bus-intel-ismt-add-delay-param.patch (100%) rename {patch => patches-sonic}/driver-net-tg3-add-param-short-preamble-and-reset.patch (100%) rename {patch => patches-sonic}/driver-net-tg3-change-dma-mask-for-57766.patch (97%) rename {patch => patches-sonic}/driver-sff-8436-use-nvmem-framework.patch (100%) rename {patch => patches-sonic}/driver-sff-8436-use-nvmem_device_read.patch (100%) rename {patch => patches-sonic}/driver-support-optoe-EOF_fix.patch (100%) rename {patch => patches-sonic}/driver-support-optoe-QSFP_DD.patch (100%) rename {patch => patches-sonic}/driver-support-optoe-chunk-offset-fix.patch (100%) rename {patch => patches-sonic}/driver-support-optoe-dynamic-write-timeout.patch (100%) rename {patch => patches-sonic}/driver-support-optoe-oneaddr-pageable.patch (100%) rename {patch => patches-sonic}/driver-support-optoe-twoaddr-a2h-access.patch (100%) rename {patch => patches-sonic}/driver-support-optoe-update-to-linux-6.1.patch (100%) create mode 100644 patches-sonic/driver-support-optoe-update-to-linux-6.10.patch rename {patch => patches-sonic}/driver-support-optoe-write-max.patch (100%) rename {patch => patches-sonic}/driver-support-optoe-write-max_fix.patch (100%) rename {patch => patches-sonic}/driver-support-optoe.patch (100%) rename {patch => patches-sonic}/driver-support-sff-8436-eeprom-update.patch (95%) rename {patch => patches-sonic}/driver-support-sff-8436-eeprom.patch (100%) rename {patch => patches-sonic}/driver-support-sff-8436-read-write-fix.patch (100%) create mode 100644 patches-sonic/kconfig-exclusions create mode 100644 patches-sonic/kconfig-force-inclusions create mode 100644 patches-sonic/kconfig-inclusions create mode 100644 patches-sonic/kconfig-secure-boot-exclusions create mode 100644 patches-sonic/kconfig-secure-boot-inclusions rename {patch => patches-sonic}/kernel-sched-core-fix-cgroup-fork-race.patch (100%) rename {patch => patches-sonic}/rtnetlink-catch-EOPNOTSUPP-errors.patch (100%) create mode 100644 patches-sonic/series diff --git a/.azure-pipelines/build-template.yml b/.azure-pipelines/build-template.yml index 1edc3b046..4cfa93870 100644 --- a/.azure-pipelines/build-template.yml +++ b/.azure-pipelines/build-template.yml @@ -17,28 +17,37 @@ parameters: type: string values: - sonicso1ES-amd64 - - sonicbld_8c - sonicso1ES-arm64 - sonicso1ES-armhf default: sonicso1ES-amd64 - name: timeout type: number - default: 600 + default: 180 - name: sonic_slave type: string +- name: old_artifact_name + type: string + +- name: old_linux_deb_pattern + type: string + - name: artifact_name type: string - name: linux_deb_pattern type: string +- name: secure_boot + type: boolean + default: false + jobs: - job: pool: ${{ parameters.pool }} - displayName: ${{ parameters.platform }}-${{ parameters.arch }} + displayName: ${{ parameters.platform }}-${{ parameters.arch }} (Secure boot ${{ parameters.secure_boot }}) timeoutInMinutes: ${{ parameters.timeout }} container: @@ -53,20 +62,27 @@ jobs: source: specific project: build pipelineId: 499053 - artifact: ${{ parameters.artifact_name }} + artifact: ${{ parameters.old_artifact_name }} runVersion: 'specific' - itemPattern: ${{ parameters.linux_deb_pattern }} + itemPattern: ${{ parameters.old_linux_deb_pattern }} targetPath: $(Agent.TempDirectory)/ displayName: "Download the linux-image artifact from the last build with a different kernel version" - script: | - git config --global user.email "lguohan@build.com" - git config --global user.name "Guohan Lu" - export kernel_procure_method=build + openssl req -new -noenc -utf8 -sha256 -days 30 -batch -x509 -subj "/CN=Autogenerated pipeline build key" -outform PEM -out build_trusted_key.pem -keyout /dev/null + displayName: "Generate additional secure boot certificate" + condition: ${{ eq(parameters.secure_boot, true) }} + - script: | + set -x cat /proc/cpuinfo + if [[ ${{ parameters.secure_boot }} = "True" ]]; then + export SECURE_UPGRADE_MODE=dev + export SECURE_UPGRADE_SIGNING_CERT=$(System.DefaultWorkingDirectory)/build_trusted_key.pem + fi CONFIGURED_ARCH=${{ parameters.arch }} CONFIGURED_PLATFORM=${{ parameters.platform }} make displayName: "Compile sonic kernel" - script: | - dpkg-deb -x $(Agent.TempDirectory)/${{ parameters.linux_deb_pattern }} $(Agent.TempDirectory)/old + set -e + dpkg-deb -x $(Agent.TempDirectory)/${{ parameters.old_linux_deb_pattern }} $(Agent.TempDirectory)/old dpkg-deb -x $(System.DefaultWorkingDirectory)/${{ parameters.linux_deb_pattern }} $(Agent.TempDirectory)/new pip3 install tabulate python3 $(System.DefaultWorkingDirectory)/.azure-pipelines/kcfg-diff.py \ diff --git a/Makefile b/Makefile index cb1a4d059..2c4cc7609 100644 --- a/Makefile +++ b/Makefile @@ -1,28 +1,39 @@ .ONESHELL: SHELL = /bin/bash -.SHELLFLAGS += -e +.SHELLFLAGS += -ex -KERNEL_ABI_MINOR_VERSION = 2 -KVERSION_SHORT ?= 6.1.0-29-$(KERNEL_ABI_MINOR_VERSION) -KVERSION ?= $(KVERSION_SHORT)-amd64 -KERNEL_VERSION ?= 6.1.123 +KERNEL_VERSION ?= 6.12.41 +KERNEL_ABISUFFIX ?= +deb13 KERNEL_SUBVERSION ?= 1 +KERNEL_FEATURESET ?= sonic CONFIGURED_ARCH ?= amd64 CONFIGURED_PLATFORM ?= vs +CROSS_BUILD_ENVIRON ?= n +SONIC_CONFIG_MAKE_JOBS ?= $(shell nproc) +KVERSION_SHORT := $(KERNEL_VERSION)$(KERNEL_ABISUFFIX)-$(KERNEL_FEATURESET) +ifeq ($(CONFIGURED_ARCH), armhf) +# Override kernel version for ARMHF as it uses arm MP (multi-platform) for short version +KVERSION ?= $(KVERSION_SHORT)-armmp +else +KVERSION ?= $(KVERSION_SHORT)-$(CONFIGURED_ARCH) +endif SECURE_UPGRADE_MODE ?= SECURE_UPGRADE_SIGNING_CERT ?= SECURE_UPGRADE_KERNEL_CAFILE ?= $(SECURE_UPGRADE_SIGNING_CERT) -LINUX_HEADER_COMMON = linux-headers-$(KVERSION_SHORT)-common_$(KERNEL_VERSION)-$(KERNEL_SUBVERSION)_all.deb -LINUX_HEADER_AMD64 = linux-headers-$(KVERSION)_$(KERNEL_VERSION)-$(KERNEL_SUBVERSION)_$(CONFIGURED_ARCH).deb +LINUX_HEADER_COMMON = linux-headers-$(KERNEL_VERSION)$(KERNEL_ABISUFFIX)-common-$(KERNEL_FEATURESET)_$(KERNEL_VERSION)-$(KERNEL_SUBVERSION)_all.deb +LINUX_HEADER_ARCH = linux-headers-$(KVERSION)_$(KERNEL_VERSION)-$(KERNEL_SUBVERSION)_$(CONFIGURED_ARCH).deb +LINUX_KBUILD = linux-kbuild-$(KERNEL_VERSION)$(KERNEL_ABISUFFIX)_$(KERNEL_VERSION)-$(KERNEL_SUBVERSION)_$(CONFIGURED_ARCH).deb ifeq ($(CONFIGURED_ARCH), armhf) LINUX_IMAGE = linux-image-$(KVERSION)_$(KERNEL_VERSION)-$(KERNEL_SUBVERSION)_$(CONFIGURED_ARCH).deb + KERNEL_FLAVOR_ARCH=armmp else LINUX_IMAGE = linux-image-$(KVERSION)-unsigned_$(KERNEL_VERSION)-$(KERNEL_SUBVERSION)_$(CONFIGURED_ARCH).deb + KERNEL_FLAVOR_ARCH=$(CONFIGURED_ARCH) endif MAIN_TARGET = $(LINUX_HEADER_COMMON) -DERIVED_TARGETS = $(LINUX_HEADER_AMD64) $(LINUX_IMAGE) +DERIVED_TARGETS = $(LINUX_HEADER_ARCH) $(LINUX_IMAGE) $(LINUX_KBUILD) DSC_FILE = linux_$(KERNEL_VERSION)-$(KERNEL_SUBVERSION).dsc DEBIAN_FILE = linux_$(KERNEL_VERSION)-$(KERNEL_SUBVERSION).debian.tar.xz @@ -71,49 +82,26 @@ $(addprefix $(DEST)/, $(MAIN_TARGET)): $(DEST)/% : dpkg-source -x $(DSC_FILE) pushd $(BUILD_DIR) - git init - git add -f * - git commit -qm "check in all loose files and diffs" - # patching anything that could affect following configuration generation. - stg init - stg import -s ../patch/preconfig/series + cp -vr ../config.local ../patches-sonic debian/ + if [[ -f debian/config.local/$(CONFIGURED_ARCH)/config.sonic-$(CONFIGURED_PLATFORM) ]]; then + cp debian/config.local/$(CONFIGURED_ARCH)/config.sonic-$(CONFIGURED_PLATFORM) debian/config.local/$(CONFIGURED_ARCH)/config.sonic-platform-specific + fi + + patch -p1 -i ../patches-debian/disable-secureboot-config-checks.patch + + # Enable secure boot configs if needed + ../manage-config $(CONFIGURED_ARCH) $(SECURE_UPGRADE_MODE) $(SECURE_UPGRADE_KERNEL_CAFILE) - # re-generate debian/rules.gen, requires kernel-wedge + # re-generate debian packages and rules with SONiC customizations debian/bin/gencontrol.py - # generate linux build file for amd64_none_amd64 - DEB_HOST_ARCH=armhf fakeroot make -f debian/rules.gen setup_armhf_none_armmp - DEB_HOST_ARCH=arm64 fakeroot make -f debian/rules.gen setup_arm64_none_arm64 - DEB_HOST_ARCH=amd64 fakeroot make -f debian/rules.gen setup_amd64_none_amd64 - - # Applying patches and configuration changes - git add debian/build/build_armhf_none_armmp/.config -f - git add debian/build/build_arm64_none_arm64/.config -f - git add debian/build/build_amd64_none_amd64/.config -f - git add debian/config.defines.dump -f - git add debian/control -f - git add debian/rules.gen -f - git add debian/tests/control -f - git add debian/*.maintscript -f - git add debian/*.bug-presubj -f - git commit -m "unmodified debian source" - - # Learning new git repo head (above commit) by calling stg repair. - stg repair - stg import -s ../patch/series - - # Optionally add/remove kernel options - if [ -f ../manage-config ]; then - ../manage-config $(CONFIGURED_ARCH) $(CONFIGURED_PLATFORM) $(SECURE_UPGRADE_MODE) $(SECURE_UPGRADE_KERNEL_CAFILE) - fi + # TODO(trixie): Make a way to verify that our configs are being set - # Building a custom kernel from Debian kernel source - ARCH=$(CONFIGURED_ARCH) DEB_HOST_ARCH=$(CONFIGURED_ARCH) DEB_BUILD_PROFILES=nodoc fakeroot make -f debian/rules -j $(shell nproc) binary-indep -ifeq ($(CONFIGURED_ARCH), armhf) - ARCH=$(CONFIGURED_ARCH) DEB_HOST_ARCH=$(CONFIGURED_ARCH) fakeroot make -f debian/rules.gen -j $(shell nproc) binary-arch_$(CONFIGURED_ARCH)_none_armmp +ifeq ($(CROSS_BUILD_ENVIRON), y) + dpkg-buildpackage -b -us -uc -a$(CONFIGURED_ARCH) -Pcross,nocheck,nodoc -j$(SONIC_CONFIG_MAKE_JOBS) else - ARCH=$(CONFIGURED_ARCH) DEB_HOST_ARCH=$(CONFIGURED_ARCH) fakeroot make -f debian/rules.gen -j $(shell nproc) binary-arch_$(CONFIGURED_ARCH)_none_$(CONFIGURED_ARCH) + dpkg-buildpackage -b -us -uc -Pnodoc -j$(SONIC_CONFIG_MAKE_JOBS) endif popd diff --git a/azure-pipelines.yml b/azure-pipelines.yml index 41abd26d6..ea2d932ba 100644 --- a/azure-pipelines.yml +++ b/azure-pipelines.yml @@ -15,32 +15,52 @@ stages: - template: .azure-pipelines/build-template.yml parameters: arch: amd64 - sonic_slave: sonic-slave-bookworm - artifact_name: sonic-linux-kernel + pool: sonicso1ES-amd64 + sonic_slave: sonic-slave-trixie + old_artifact_name: sonic-linux-kernel + artifact_name: sonic-linux-kernel.amd64 + old_linux_deb_pattern: linux-image-*-unsigned_*deb linux_deb_pattern: linux-image-*-unsigned_*deb + - template: .azure-pipelines/build-template.yml + parameters: + arch: amd64 + pool: sonicso1ES-amd64 + sonic_slave: sonic-slave-trixie + old_artifact_name: sonic-linux-kernel + artifact_name: sonic-linux-kernel.amd64.secure + old_linux_deb_pattern: linux-image-*-unsigned_*deb + linux_deb_pattern: linux-image-*-unsigned_*deb + secure_boot: true + - template: .azure-pipelines/build-template.yml parameters: arch: arm64 pool: sonicso1ES-arm64 - sonic_slave: sonic-slave-bookworm-arm64 + sonic_slave: sonic-slave-trixie-arm64 + old_artifact_name: sonic-linux-kernel.arm64 artifact_name: sonic-linux-kernel.arm64 + old_linux_deb_pattern: linux-image-*-unsigned_*deb linux_deb_pattern: linux-image-*-unsigned_*deb - template: .azure-pipelines/build-template.yml parameters: arch: armhf pool: sonicso1ES-armhf - sonic_slave: sonic-slave-bookworm-armhf + sonic_slave: sonic-slave-trixie-armhf + old_artifact_name: sonic-linux-kernel.armhf artifact_name: sonic-linux-kernel.armhf - linux_deb_pattern: linux-image-*-armmp_*deb + old_linux_deb_pattern: linux-image-*-armmp_*deb + linux_deb_pattern: linux-image-*+deb*-*-armmp_*deb - template: .azure-pipelines/build-template.yml parameters: arch: arm64 platform: pensando pool: sonicso1ES-arm64 - sonic_slave: sonic-slave-bookworm-arm64 + sonic_slave: sonic-slave-trixie-arm64 + old_artifact_name: sonic-linux-kernel.pensando.arm64 artifact_name: sonic-linux-kernel.pensando.arm64 + old_linux_deb_pattern: linux-image-*-unsigned_*deb linux_deb_pattern: linux-image-*-unsigned_*deb diff --git a/config.local/amd64/config.sonic b/config.local/amd64/config.sonic new file mode 100644 index 000000000..23bf715f2 --- /dev/null +++ b/config.local/amd64/config.sonic @@ -0,0 +1,173 @@ + +CONFIG_SATA_MOBILE_LPM_POLICY=1 +# For Arista +CONFIG_I2C_MUX_PCA9541=m +CONFIG_SENSORS_MAX6697=m +#CONFIG_SENSORS_DPS1900=m # TODO: enable once the DPS1900 patch is re-enabled +CONFIG_PCI_REASSIGN_PREF_MEM=y +# For cig-cs6436 +CONFIG_SERIAL_8250_LPSS=m +# SFF_8436 +CONFIG_EEPROM_SFF_8436=m +# For Dell S6000 +CONFIG_SENSORS_MAX6620=m +CONFIG_PMBUS=m +CONFIG_SENSORS_PMBUS=m +#CONFIG_SENSORS_DNI_DPS460=m # TODO: enable once the DPS460 patch is re-enabled +CONFIG_I2C_MUX_GPIO=m +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_SCH=m +# For Dell Z9100 +CONFIG_I2C_MUX_PCA954x=m +# For Ingrasys S9100 +CONFIG_I2C_GPIO=m +CONFIG_GPIO_PCA953X=m +# For Inventec d7032 +CONFIG_GPIO_ICH=m +# For mitac ly1200 +CONFIG_SENSORS_MAX31790=m +# For optoe +CONFIG_EEPROM_OPTOE=m +###-> mellanox_amd64-start +CONFIG_X86_AMD_PLATFORM_DEVICE=y +CONFIG_MCTP=y +CONFIG_DMI_SYSFS=y +CONFIG_OF=y +CONFIG_EEPROM_AT24=m +CONFIG_AMD_XGBE=m +CONFIG_IGB=m +CONFIG_MLXSW_CORE=m +CONFIG_MARVELL_PHY=m +CONFIG_MARVELL_10G_PHY=m +CONFIG_SERIAL_8250_DW=y +CONFIG_HW_RANDOM_AMD=m +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MUX=m +CONFIG_I2C_SMBUS=m +CONFIG_I2C_I801=m +CONFIG_I2C_DESIGNWARE_CORE=m +CONFIG_I2C_MLXCPLD=m +CONFIG_I2C_SLAVE=y +CONFIG_PINCTRL=y +CONFIG_GPIOLIB=y +CONFIG_SENSORS_K10TEMP=m +CONFIG_SENSORS_DRIVETEMP=m +CONFIG_SENSORS_CORETEMP=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_POWR1220=m +CONFIG_SENSORS_LM75=m +CONFIG_PMBUS=m +CONFIG_SENSORS_EMC1403=m +CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_STTS751=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_TMP421=m +CONFIG_THERMAL_NETLINK=y +CONFIG_INTEL_PCH_THERMAL=m +CONFIG_WATCHDOG_SYSFS=y +CONFIG_LPC_ICH=m +CONFIG_MFD_INTEL_LPSS_PCI=y +CONFIG_LEDS_MLXREG=m +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_DW_DMAC_PCI=y +CONFIG_MELLANOX_PLATFORM=y +CONFIG_MLX_PLATFORM=m +CONFIG_NET_DEVLINK=y +CONFIG_I2C_MUX_REG=m +CONFIG_I2C_MUX_MLXCPLD=m +CONFIG_REGMAP_I2C=m +CONFIG_GPIO_SYSFS=y +CONFIG_IIO_SYSFS_TRIGGER=m +CONFIG_NVME_HWMON=y +CONFIG_MLXSW_CORE_HWMON=y +CONFIG_MLXSW_I2C=m +CONFIG_MLXSW_MINIMAL=m +CONFIG_MLXSW_CORE_THERMAL=n +CONFIG_MLXREG_HOTPLUG=m +CONFIG_MLXREG_IO=m +CONFIG_MLX_WDT=m +CONFIG_MLXREG_LC=m +CONFIG_MLXREG_DPU=m +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_SENSORS_PMBUS=m +CONFIG_SENSORS_MLXREG_FAN=m +CONFIG_GPIO_GENERIC=m +CONFIG_MAX1363=m +CONFIG_SENSORS_TPS53679=m +CONFIG_SENSORS_XDPE122=m +CONFIG_SENSORS_MP2975=m +CONFIG_SENSORS_MP2855=m +CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2891=m +CONFIG_SENSORS_MP2869=m +CONFIG_SENSORS_MP29502=m +CONFIG_GPIO_ICH=m +CONFIG_CPU_THERMAL=y +CONFIG_IGB_HWMON=y +CONFIG_MFD_CORE=y +CONFIG_MFD_INTEL_LPSS=y +CONFIG_TI_ADS1015=m +CONFIG_PINCTRL_INTEL=y +CONFIG_PINCTRL_CANNONLAKE=m +CONFIG_PINCTRL_DENVERTON=m +CONFIG_NVSW_SN2201=m +CONFIG_I2C_DESIGNWARE_PLATFORM=m +CONFIG_I2C_DESIGNWARE_BAYTRAIL=y +CONFIG_I2C_DESIGNWARE_PCI=m +CONFIG_SPI_PXA2XX=m +CONFIG_SENSORS_XDPE152=m +CONFIG_SENSORS_IIO_HWMON=m +CONFIG_SENSORS_LM25066=m +CONFIG_SENSORS_UCD9000=m +CONFIG_SENSORS_UCD9200=m +CONFIG_THERMAL_OF=y +CONFIG_MCTP_FLOWS=y +CONFIG_MCTP_TRANSPORT_I2C=m +CONFIG_I2C_SLAVE_EEPROM=m +CONFIG_I2C_ASF=m +CONFIG_SPI_AMD=m +CONFIG_PINCTRL_AMD=y +CONFIG_EDAC_AMD64=m +CONFIG_AMD_XGBE_DCB=y +CONFIG_SENSORS_ISL68137=m +###-> mellanox_amd64-end +# For Cisco 8000 +CONFIG_PHYLIB=m +CONFIG_OF_GPIO=y +CONFIG_OF_MDIO=m +CONFIG_MDIO_BUS_MUX_GPIO=m +CONFIG_MDIO_BUS_MUX=m +CONFIG_REGMAP_MMIO=y +CONFIG_TI_TLC4541=m +CONFIG_SENSORS_LTC2978=m +CONFIG_SENSORS_LTC2945=m +CONFIG_SENSORS_TPS40422=m +CONFIG_SENSORS_ADM1275=m +CONFIG_SPI_INTEL_PLATFORM=m +CONFIG_SPI_INTEL=m +# For pensando +CONFIG_IONIC=m +# For AMD Ryzen Embedded processors +CONFIG_PCI_ENDPOINT=y +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_DW_EP=y +CONFIG_PCIE_DW_PLAT=y +CONFIG_PCIE_DW_PLAT_HOST=y +CONFIG_PCIE_DW_PLAT_EP=y +# For Micas +CONFIG_MDIO_BITBANG=m +CONFIG_MDIO_GPIO=m +CONFIG_SPI_GPIO=m +CONFIG_SENSORS_INA3221=m +# For Nokia +CONFIG_RTC_DRV_DS1307=m +CONFIG_SENSORS_TMP464=m +# For Nexthop +CONFIG_PCI_STUB=y +CONFIG_SENSORS_ADM1266=m + +CONFIG_AMD_MEM_ENCRYPT=n +# Unset X86_PAT according to Broadcom's requirement +CONFIG_X86_PAT=n +CONFIG_MLXSW_PCI=n diff --git a/config.local/amd64/config.sonic-secureboot b/config.local/amd64/config.sonic-secureboot new file mode 100644 index 000000000..70697c1ed --- /dev/null +++ b/config.local/amd64/config.sonic-secureboot @@ -0,0 +1,12 @@ +CONFIG_SYSTEM_TRUSTED_KEYS="debian/certs/debian-uefi-certs.pem" +CONFIG_MODULE_SIG_HASH="sha512" +CONFIG_MODULE_SIG_SHA512=y +CONFIG_KEXEC_SIG_FORCE=y +CONFIG_MODULE_SIG_FORCE=y + +CONFIG_MODULE_SIG_SHA256=n +# For mellanox +CONFIG_SECURITY_LOCKDOWN_LSM=n +CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=n +CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=n +CONFIG_LOCK_DOWN_IN_EFI_SECURE_BOOT=n diff --git a/config.local/amd64/defines.toml b/config.local/amd64/defines.toml new file mode 100644 index 000000000..8092e5461 --- /dev/null +++ b/config.local/amd64/defines.toml @@ -0,0 +1,6 @@ +[[featureset]] +name = 'sonic' +[[featureset.flavour]] +name = 'amd64' +[featureset.flavour.build] +config = ['amd64/config.sonic'] diff --git a/config.local/arm64/config.sonic b/config.local/arm64/config.sonic new file mode 100644 index 000000000..fb7db2101 --- /dev/null +++ b/config.local/arm64/config.sonic @@ -0,0 +1,42 @@ +# For enabling SDEI +CONFIG_ARM_SDE_INTERFACE=y +# For Marvell +CONFIG_EEPROM_SFF_8436=m +CONFIG_EEPROM_OPTOE=m +CONFIG_I2C_MUX_GPIO=m +CONFIG_MTD_RAW_NAND=m +CONFIG_MTD_NAND_ECC_SW_BCH=y +CONFIG_MTD_NAND_MARVELL=m +CONFIG_SENSORS_EMC2305=m +CONFIG_PHY_MVEBU_CP110_COMPHY=y +CONFIG_SPI_ORION=m +CONFIG_ARM_SMC_WATCHDOG=m +# For pensando +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_EMBEDDED=y +CONFIG_GENERIC_IRQ_DEBUGFS=y +CONFIG_GPIO_DWAPB=m +CONFIG_IP_PNP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IRQSOFF_TRACER=y +CONFIG_KALLSYMS_ALL=y +CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y +CONFIG_SCHED_TRACER=y +CONFIG_MEMTEST=y +CONFIG_MMC_DEBUG=y +CONFIG_MMC_SDHCI_CADENCE=m +CONFIG_PMBUS=m +CONFIG_SENSORS_PMBUS=m +CONFIG_SENSORS_LTC2978=m +CONFIG_SENSORS_TPS53679=m +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_CLASS=y +CONFIG_SPI_CADENCE_QUADSPI=m +CONFIG_SPI_DESIGNWARE=m +CONFIG_SPI_DW_MMIO=m +CONFIG_SQUASHFS_DECOMP_MULTI=y +CONFIG_PREEMPTIRQ_TRACEPOINTS=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_KEXEC_FILE=y diff --git a/config.local/arm64/config.sonic-mellanox b/config.local/arm64/config.sonic-mellanox new file mode 100644 index 000000000..7155ccc94 --- /dev/null +++ b/config.local/arm64/config.sonic-mellanox @@ -0,0 +1,2 @@ +[mellanox-arm64] + diff --git a/config.local/arm64/config.sonic-pensando b/config.local/arm64/config.sonic-pensando new file mode 100644 index 000000000..bbd55bc44 --- /dev/null +++ b/config.local/arm64/config.sonic-pensando @@ -0,0 +1,20 @@ +CONFIG_ARCH_PENSANDO=y +CONFIG_ARCH_PENSANDO_ELBA_SOC=y +CONFIG_PENSANDO_SOC_PENFW=y +CONFIG_EDAC_ELBA=y +CONFIG_IRQ_PENSANDO=y +CONFIG_MFD_PENSANDO_ELBASR=y +CONFIG_RESET_ELBASR=y +CONFIG_UIO_PCIEMAC=m +CONFIG_UIO_PENMSI1=m +CONFIG_UIO_PENGIC=m +CONFIG_UIO_PENMSI=m +CONFIG_ARM64_VA_BITS_39=y +CONFIG_COMMON_CLK_CS2000_CP=y +CONFIG_I2C_RD1173=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_NO_HZ_FULL=y +CONFIG_RCU_NOCB_CPU=y +CONFIG_VIRT_CPU_ACCOUNTING=y +CONFIG_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_RTC_DRV_ELBA_CPLD=y diff --git a/config.local/arm64/config.sonic-secureboot b/config.local/arm64/config.sonic-secureboot new file mode 100644 index 000000000..4eac105b3 --- /dev/null +++ b/config.local/arm64/config.sonic-secureboot @@ -0,0 +1,12 @@ +CONFIG_SYSTEM_TRUSTED_KEYS="debian/certs/debian-uefi-certs.pem" +CONFIG_MODULE_SIG_HASH="sha512" +CONFIG_MODULE_SIG_SHA512=y +CONFIG_KEXEC_SIG=y +CONFIG_MODULE_SIG_FORCE=y + +CONFIG_MODULE_SIG_SHA256=n +# For mellanox +CONFIG_SECURITY_LOCKDOWN_LSM=n +CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=n +CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=n +CONFIG_LOCK_DOWN_IN_EFI_SECURE_BOOT=n diff --git a/config.local/arm64/defines.toml b/config.local/arm64/defines.toml new file mode 100644 index 000000000..c4c3bd185 --- /dev/null +++ b/config.local/arm64/defines.toml @@ -0,0 +1,6 @@ +[[featureset]] +name = 'sonic' +[[featureset.flavour]] +name = 'arm64' +[featureset.flavour.build] +config = ['arm64/config.sonic', 'arm64/config.sonic-platform-specific'] diff --git a/config.local/armhf/config.sonic b/config.local/armhf/config.sonic new file mode 100644 index 000000000..788a8dc0f --- /dev/null +++ b/config.local/armhf/config.sonic @@ -0,0 +1,3 @@ +CONFIG_EEPROM_SFF_8436=m +CONFIG_EEPROM_OPTOE=m +CONFIG_I2C_MUX_GPIO=m diff --git a/config.local/armhf/config.sonic-marvell-prestera b/config.local/armhf/config.sonic-marvell-prestera new file mode 100644 index 000000000..e8e09b5d2 --- /dev/null +++ b/config.local/armhf/config.sonic-marvell-prestera @@ -0,0 +1,22 @@ +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=y +CONFIG_ARCH_VIRT=n +CONFIG_ARCH_BCM=n +CONFIG_ARCH_EXYNOS=n +CONFIG_ARCH_HIGHBANK=n +CONFIG_ARCH_MXC=n +CONFIG_ARCH_MESON=n +CONFIG_ARCH_OMAP3=n +CONFIG_ARCH_OMAP4=n +CONFIG_ARCH_ROCKCHIP=n +CONFIG_ARCH_SOCFPGA=n +CONFIG_ARCH_SUNXI=n +CONFIG_ARCH_TEGRA=n +CONFIG_ARCH_VEXPRESS=n +CONFIG_ARCH_WM8850=n +CONFIG_SOC_OMAP5=n +CONFIG_SOC_AM33XX=n +CONFIG_SOC_DRA7XX=n +CONFIG_EFI=n +CONFIG_SECONDARY_TRUSTED_KEYRING=n +CONFIG_SYSTEM_BLACKLIST_KEYRING=n diff --git a/config.local/armhf/defines.toml b/config.local/armhf/defines.toml new file mode 100644 index 000000000..2cf233d0b --- /dev/null +++ b/config.local/armhf/defines.toml @@ -0,0 +1,6 @@ +[[featureset]] +name = 'sonic' +[[featureset.flavour]] +name = 'armmp' +[featureset.flavour.build] +config = ['armhf/config.sonic', 'armhf/config.sonic-platform-specific'] diff --git a/config.local/defines.toml b/config.local/defines.toml new file mode 100644 index 000000000..5e09e52b9 --- /dev/null +++ b/config.local/defines.toml @@ -0,0 +1,22 @@ +[packages] +docs = false +source = false +tools_unversioned = false + +[[featureset]] +name = 'none' +enable = false + +[[featureset]] +name = 'rt' +enable = false + +[[featureset]] +name = 'sonic' +enable = true + [featureset.description] + parts = ['sonic'] + [featureset.description.long] + sonic = 'This kernel includes patches that support SONiC.' + [featureset.description.short] + sonic = 'SONiC Kernel' diff --git a/config.local/featureset-sonic/config b/config.local/featureset-sonic/config new file mode 100644 index 000000000..d15de4e4d --- /dev/null +++ b/config.local/featureset-sonic/config @@ -0,0 +1,19 @@ +CONFIG_LOG_BUF_SHIFT=20 +CONFIG_RTC_INTF_DEV_UIE_EMUL=y + +# Unset to enable UBIFS on flash +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=n +###-> mellanox_common-start +###-> mellanox_common-end +CONFIG_DRM=n +CONFIG_VIDEO_DEV=n +CONFIG_MEDIA_SUPPORT=n +CONFIG_MEDIA_CONTROLLER=n +CONFIG_DVB_CORE=n +CONFIG_MEDIA_TUNER=n +CONFIG_MEDIA_ATTACH=n + +# Disable module compression, since squashfs will do compression anyways +CONFIG_MODULE_COMPRESS=n +# Disable strict /dev/mem access checks to allow mmap on PCI resource file +CONFIG_IO_STRICT_DEVMEM=n diff --git a/manage-config b/manage-config index d09326e2e..31fcd7f66 100755 --- a/manage-config +++ b/manage-config @@ -5,186 +5,38 @@ # # Add / Remove options in kernel configuration, # and Verify the kernel configuration afterwards. -# -# To remove options from the kernel, add the options into the flat text file -# patch/kconfig-exclusions -# -# Example: -# CONFIG_SOUND -# CONFIG_ISDN -# -# To add options into the kernel, add the options into the flat text file -# patch/kconfig-inclusions -# -# Example: -# CONFIG_AD5064=y -# -# If the option is required on all architectures, add it to the common section; -# if the option is only relevant to a specific architecture, add it to the -# section of the corresponding architecture. -# Configuration file to change ARCH=amd64 -PLATFORM= SECURE_UPGRADE_MODE="no_sign" SECURE_UPGRADE_KERNEL_CAFILE= if [ $# -ge 1 ]; then ARCH=$1 fi if [ $# -ge 2 ]; then - PLATFORM=$2 + SECURE_UPGRADE_MODE=$2 fi if [ $# -ge 3 ]; then - SECURE_UPGRADE_MODE=$3 + SECURE_UPGRADE_KERNEL_CAFILE=$3 fi -if [ $# -ge 4 ]; then - SECURE_UPGRADE_KERNEL_CAFILE=$4 -fi - -case "$ARCH" in - amd64) - CONFIG_FILE_LOC=debian/build/build_amd64_none_amd64 - ;; - arm64) - CONFIG_FILE_LOC=debian/build/build_arm64_none_arm64 - ;; - armhf) - CONFIG_FILE_LOC=debian/build/build_armhf_none_armmp - ;; - *) - CONFIG_FILE_LOC=debian/build/build_amd64_none_amd64 - ;; -esac -CONFIG_FILE=${CONFIG_FILE_LOC}/.config - -function get_section_opts(){ - file=$1 - for((i=2;i<=$#;i++));do - eval section=\$$i - opts+=$(sed -n '/^\['${section}'\]/, /^\[.*\]/p' ${file} | grep -Ev '\[.*\]|^$|[#;]') - opts+=$'\n' - done - echo "$opts" -} - -function process_inclusion_exclusion_files(){ - echo "process_inclusion_exclusion_files Start" - ret=0 - echo "debug ret=$ret 1" - if [ -e ${exclusion_file} -o -e ${inclusion_file} -o -e ${force_inclusion_file} ]; then - - # Process any exclusions in the kernel - if [ -f ${exclusion_file} ]; then - exclusion_opts=$(get_section_opts ${exclusion_file} "common" ${ARCH} ${PLATFORM} ${PLATFORM}-${ARCH}) - while read -r opt; do - if [ ! -z "$opt" ] && [[ ! "$opt" =~ ^#.* ]]; then - scripts/config --file ${CONFIG_FILE} -d $opt - fi - done <<< ${exclusion_opts}; - fi - - # Process any inclusions in the kernel - if [ -f ${inclusion_file} ]; then - inclusion_opts=$(get_section_opts ${inclusion_file} "common" ${ARCH} ${PLATFORM} ${PLATFORM}-${ARCH}) - while read -r opt; do - if [ ! -z "$opt" ] && [[ ! "$opt" =~ ^#.* ]]; then - n=${opt%=*} - v="${opt#*=}" - scripts/config --file ${CONFIG_FILE} -k --set-val "$n" "$v" - fi - done <<< ${inclusion_opts}; - fi - - # Update the .config file to be sure it's consistent - make -C ${CONFIG_FILE_LOC} olddefconfig - - # Verify that the kernel options we want to remove are not in the updated configuration - if [ -f ${exclusion_file} ]; then - echo - echo "Checking removed kernel options..." - while read -r opt; do - if [ ! -z "$opt" ] && [[ ! "$opt" =~ ^#.* ]]; then - s=$(scripts/config --file ${CONFIG_FILE} -k --state $opt) - if [ ! "$s" = "undef" -a ! "$s" = "n" ]; then - ret=1 - echo "Option $opt should not be set, but is set to [$s]" - fi - fi - done <<< ${exclusion_opts}; - if [ $ret = 0 ]; then - echo "No error" - fi - fi - - # Verify that the kernel options we want to add are now in the updated configuration - if [ -f ${inclusion_file} ]; then - echo - echo "Checking added kernel options..." - while read -r opt; do - if [ ! -z "$opt" ] && [[ ! "$opt" =~ ^#.* ]]; then - n=${opt%=*} - v="${opt#*=}" - v="${v/#\"/}" - v="${v/%\"/}" - s=$(scripts/config --file ${CONFIG_FILE} -k --state $n) - if [ ! "$s" = "$v" ]; then - ret=2 - echo "Option $n should be set to [$v] instead of [$s]" - fi - fi - done <<< ${inclusion_opts}; - if [ $ret = 0 ]; then - echo "No error" - fi - fi - - # Process any force inclusions in the kernel - if [ -f ${force_inclusion_file} ]; then - force_inclusion_opts=$(get_section_opts ${force_inclusion_file} "common" ${ARCH} ${PLATFORM}) - while read -r opt; do - if [ ! -z "$opt" ] && [[ ! "$opt" =~ ^#.* ]]; then - echo $opt >> ${CONFIG_FILE} - fi - done <<< ${force_inclusion_opts}; - fi - - echo - fi - - echo "process_inclusion_exclusion_files Done" - return $ret -} - -exclusion_file="../patch/kconfig-exclusions" -inclusion_file="../patch/kconfig-inclusions" -force_inclusion_file="../patch/kconfig-force-inclusions" -process_inclusion_exclusion_files -ret_process_inc_ex=$? # Secure Boot support -if [ $ret_process_inc_ex -eq 0 ]; then - echo "Secure Boot params: SECURE_UPGRADE_MODE=${SECURE_UPGRADE_MODE}, SECURE_UPGRADE_KERNEL_CAFILE=${SECURE_UPGRADE_KERNEL_CAFILE}" - if [ ${SECURE_UPGRADE_MODE} == "dev" -o ${SECURE_UPGRADE_MODE} == "prod" ]; then - echo "set kconfig-secure-boot-exclusions & kconfig-secure-boot-inclusions" +echo "Secure Boot params: SECURE_UPGRADE_MODE=${SECURE_UPGRADE_MODE}, SECURE_UPGRADE_KERNEL_CAFILE=${SECURE_UPGRADE_KERNEL_CAFILE}" +if [ ${SECURE_UPGRADE_MODE} == "dev" -o ${SECURE_UPGRADE_MODE} == "prod" ]; then + echo "Enable secure boot configs" - if [ ! -f "${SECURE_UPGRADE_KERNEL_CAFILE}" ]; then - echo "ERROR: SECURE_UPGRADE_KERNEL_CAFILE=${SECURE_UPGRADE_KERNEL_CAFILE} file does not exist" - exit 1 - fi + if [ ! -f "${SECURE_UPGRADE_KERNEL_CAFILE}" ]; then + echo "ERROR: SECURE_UPGRADE_KERNEL_CAFILE=${SECURE_UPGRADE_KERNEL_CAFILE} file does not exist" + exit 1 + fi - exclusion_file="../patch/kconfig-secure-boot-exclusions" - inclusion_file="../patch/kconfig-secure-boot-inclusions" - force_inclusion_file="../patch/kconfig-force-secure-boot-inclusions" + if [ -f debian/config.local/${ARCH}/config.sonic-secureboot ]; then + cat debian/config.local/${ARCH}/config.sonic-secureboot >> debian/config.local/${ARCH}/config.sonic + fi - # save the new pub key in kernel - sed -i "s|^CONFIG_SYSTEM_TRUSTED_KEYS=.*|CONFIG_SYSTEM_TRUSTED_KEYS=\"$SECURE_UPGRADE_KERNEL_CAFILE\"|g" ${inclusion_file} + # save the new pub key in kernel + sed -i "s|^CONFIG_SYSTEM_TRUSTED_KEYS=.*|CONFIG_SYSTEM_TRUSTED_KEYS=\"$SECURE_UPGRADE_KERNEL_CAFILE\"|g" debian/config.local/${ARCH}/config.sonic - process_inclusion_exclusion_files - ret_process_inc_ex=$? - echo "Secure Boot kernel configuration done." - else - echo "no Secure Boot Kernel configuration required." - fi + echo "Secure Boot kernel configuration done." +else + echo "No Secure Boot Kernel configuration required." fi - -exit $ret_process_inc_ex diff --git a/patch/0001-net-allow-user-to-set-metric-on-default-route-learne.patch b/patch/0001-net-allow-user-to-set-metric-on-default-route-learne.patch deleted file mode 100644 index 9660bf5b8..000000000 --- a/patch/0001-net-allow-user-to-set-metric-on-default-route-learne.patch +++ /dev/null @@ -1,262 +0,0 @@ -From 23d559efa7ddfccb29dfe2df772217e55402cd71 Mon Sep 17 00:00:00 2001 -From: Praveen Chaudhary -Date: Mon, 25 Jan 2021 13:44:30 -0800 -Subject: [PATCH] net: allow user to set metric on default route learned via - Router Advertisement - -For IPv4, default route is learned via DHCPv4 and user is allowed to change -metric using config etc/network/interfaces. But for IPv6, default route can -be learned via RA, for which, currently a fixed metric value 1024 is used. - -Ideally, user should be able to configure metric on default route for IPv6 -similar to IPv4. This patch adds sysctl for the same. - -Logs: - -For IPv4: - -Config in etc/network/interfaces: -auto eth0 -iface eth0 inet dhcp - metric 4261413864 - -IPv4 Kernel Route Table: -$ ip route list -default via 172.21.47.1 dev eth0 metric 4261413864 - -FRR Table, if a static route is configured: -[In real scenario, it is useful to prefer BGP learned default route over DHCPv4 default route.] -Codes: K - kernel route, C - connected, S - static, R - RIP, - O - OSPF, I - IS-IS, B - BGP, P - PIM, E - EIGRP, N - NHRP, - T - Table, v - VNC, V - VNC-Direct, A - Babel, D - SHARP, - > - selected route, * - FIB route - -S>* 0.0.0.0/0 [20/0] is directly connected, eth0, 00:00:03 -K 0.0.0.0/0 [254/1000] via 172.21.47.1, eth0, 6d08h51m - -i.e. User can prefer Default Router learned via Routing Protocol in IPv4. -Similar behavior is not possible for IPv6, without this fix. - -After fix [for IPv6]: -sudo sysctl -w net.ipv6.conf.eth0.net.ipv6.conf.eth0.ra_defrtr_metric=1996489705 - -IP monitor: [When IPv6 RA is received] -default via fe80::xx16:xxxx:feb3:ce8e dev eth0 proto ra metric 1996489705 pref high - -Kernel IPv6 routing table -$ ip -6 route list -default via fe80::be16:65ff:feb3:ce8e dev eth0 proto ra metric 1996489705 expires 21sec hoplimit 64 pref high - -FRR Table, if a static route is configured: -[In real scenario, it is useful to prefer BGP learned default route over IPv6 RA default route.] -Codes: K - kernel route, C - connected, S - static, R - RIPng, - O - OSPFv3, I - IS-IS, B - BGP, N - NHRP, T - Table, - v - VNC, V - VNC-Direct, A - Babel, D - SHARP, - > - selected route, * - FIB route - -S>* ::/0 [20/0] is directly connected, eth0, 00:00:06 -K ::/0 [119/1001] via fe80::xx16:xxxx:feb3:ce8e, eth0, 6d07h43m - -If the metric is changed later, the effect will be seen only when next IPv6 -RA is received, because the default route must be fully controlled by RA msg. -Below metric is changed from 1996489705 to 1996489704. - -$ sudo sysctl -w net.ipv6.conf.eth0.ra_defrtr_metric=1996489704 -net.ipv6.conf.eth0.ra_defrtr_metric = 1996489704 - -IP monitor: -[On next IPv6 RA msg, Kernel deletes prev route and installs new route with updated metric] - -Deleted default via fe80::xx16:xxxx:feb3:ce8e dev eth0 proto ra metric 1996489705 expires 3sec hoplimit 64 pref high -default via fe80::xx16:xxxx:feb3:ce8e dev eth0 proto ra metric 1996489704 pref high - -Signed-off-by: Praveen Chaudhary -Signed-off-by: Zhenggen Xu -Reviewed-by: David Ahern -Link: https://lore.kernel.org/r/20210125214430.24079-1-pchaudhary@linkedin.com -Signed-off-by: Jakub Kicinski ---- - Documentation/networking/ip-sysctl.rst | 10 ++++++++++ - include/linux/ipv6.h | 1 + - include/net/ip6_route.h | 3 ++- - include/uapi/linux/ipv6.h | 1 + - include/uapi/linux/sysctl.h | 1 + - net/ipv6/addrconf.c | 11 +++++++++++ - net/ipv6/ndisc.c | 12 ++++++++---- - net/ipv6/route.c | 5 +++-- - 8 files changed, 37 insertions(+), 7 deletions(-) - -diff --git a/Documentation/networking/ip-sysctl.rst b/Documentation/networking/ip-sysctl.rst -index bf1f0ec9740b..e4e1216e6a7d 100644 ---- a/Documentation/networking/ip-sysctl.rst -+++ b/Documentation/networking/ip-sysctl.rst -@@ -1876,6 +1876,16 @@ accept_ra_defrtr - BOOLEAN - - enabled if accept_ra is enabled. - - disabled if accept_ra is disabled. - -+ra_defrtr_metric - UNSIGNED INTEGER -+ Route metric for default route learned in Router Advertisement. This value -+ will be assigned as metric for the default route learned via IPv6 Router -+ Advertisement. Takes affect only if accept_ra_defrtr is enabled. -+ -+ Possible values: -+ 1 to 0xFFFFFFFF -+ -+ Default: IP6_RT_PRIO_USER i.e. 1024. -+ - accept_ra_from_local - BOOLEAN - Accept RA with source-address that is found on local machine - if the RA is otherwise proper and able to be accepted. -diff --git a/include/linux/ipv6.h b/include/linux/ipv6.h -index 7a918daa3b19..88641e3b1cc4 100644 ---- a/include/linux/ipv6.h -+++ b/include/linux/ipv6.h -@@ -31,6 +31,7 @@ struct ipv6_devconf { - __s32 max_desync_factor; - __s32 max_addresses; - __s32 accept_ra_defrtr; -+ __u32 ra_defrtr_metric; - __s32 accept_ra_min_hop_limit; - __s32 accept_ra_pinfo; - __s32 ignore_routes_with_linkdown; -diff --git a/include/net/ip6_route.h b/include/net/ip6_route.h -index 44969d03debf..0bf09a9bca4e 100644 ---- a/include/net/ip6_route.h -+++ b/include/net/ip6_route.h -@@ -174,7 +174,8 @@ struct fib6_info *rt6_get_dflt_router(struct net *net, - struct net_device *dev); - struct fib6_info *rt6_add_dflt_router(struct net *net, - const struct in6_addr *gwaddr, -- struct net_device *dev, unsigned int pref); -+ struct net_device *dev, unsigned int pref, -+ u32 defrtr_usr_metric); - - void rt6_purge_dflt_routers(struct net *net); - -diff --git a/include/uapi/linux/ipv6.h b/include/uapi/linux/ipv6.h -index 9cdbc5b04855..a5e93062315b 100644 ---- a/include/uapi/linux/ipv6.h -+++ b/include/uapi/linux/ipv6.h -@@ -190,6 +190,7 @@ enum { - DEVCONF_NDISC_TCLASS, - DEVCONF_RPL_SEG_ENABLED, - DEVCONF_ACCEPT_UNTRACKED_NA, -+ DEVCONF_RA_DEFRTR_METRIC, - DEVCONF_MAX - }; - -diff --git a/include/uapi/linux/sysctl.h b/include/uapi/linux/sysctl.h -index 09dabb76a113..6a3b194c50fe 100644 ---- a/include/uapi/linux/sysctl.h -+++ b/include/uapi/linux/sysctl.h -@@ -572,6 +572,7 @@ enum { - NET_IPV6_ACCEPT_SOURCE_ROUTE=25, - NET_IPV6_ACCEPT_RA_FROM_LOCAL=26, - NET_IPV6_ACCEPT_RA_RT_INFO_MIN_PLEN=27, -+ NET_IPV6_RA_DEFRTR_METRIC=28, - __NET_IPV6_MAX - }; - -diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c -index 038708de6ef9..cac1e63dac54 100644 ---- a/net/ipv6/addrconf.c -+++ b/net/ipv6/addrconf.c -@@ -205,6 +205,7 @@ static struct ipv6_devconf ipv6_devconf __read_mostly = { - .max_desync_factor = MAX_DESYNC_FACTOR, - .max_addresses = IPV6_MAX_ADDRESSES, - .accept_ra_defrtr = 1, -+ .ra_defrtr_metric = IP6_RT_PRIO_USER, - .accept_ra_from_local = 0, - .accept_ra_min_hop_limit= 1, - .accept_ra_pinfo = 1, -@@ -260,6 +261,7 @@ static struct ipv6_devconf ipv6_devconf_dflt __read_mostly = { - .max_desync_factor = MAX_DESYNC_FACTOR, - .max_addresses = IPV6_MAX_ADDRESSES, - .accept_ra_defrtr = 1, -+ .ra_defrtr_metric = IP6_RT_PRIO_USER, - .accept_ra_from_local = 0, - .accept_ra_min_hop_limit= 1, - .accept_ra_pinfo = 1, -@@ -5512,6 +5514,7 @@ static inline void ipv6_store_devconf(struct ipv6_devconf *cnf, - array[DEVCONF_MAX_DESYNC_FACTOR] = cnf->max_desync_factor; - array[DEVCONF_MAX_ADDRESSES] = cnf->max_addresses; - array[DEVCONF_ACCEPT_RA_DEFRTR] = cnf->accept_ra_defrtr; -+ array[DEVCONF_RA_DEFRTR_METRIC] = cnf->ra_defrtr_metric; - array[DEVCONF_ACCEPT_RA_MIN_HOP_LIMIT] = cnf->accept_ra_min_hop_limit; - array[DEVCONF_ACCEPT_RA_PINFO] = cnf->accept_ra_pinfo; - #ifdef CONFIG_IPV6_ROUTER_PREF -@@ -6705,6 +6708,14 @@ static const struct ctl_table addrconf_sysctl[] = { - .mode = 0644, - .proc_handler = proc_dointvec, - }, -+ { -+ .procname = "ra_defrtr_metric", -+ .data = &ipv6_devconf.ra_defrtr_metric, -+ .maxlen = sizeof(u32), -+ .mode = 0644, -+ .proc_handler = proc_douintvec_minmax, -+ .extra1 = (void *)SYSCTL_ONE, -+ }, - { - .procname = "accept_ra_min_hop_limit", - .data = &ipv6_devconf.accept_ra_min_hop_limit, -diff --git a/net/ipv6/ndisc.c b/net/ipv6/ndisc.c -index f236ed938efd..85cd34710a04 100644 ---- a/net/ipv6/ndisc.c -+++ b/net/ipv6/ndisc.c -@@ -1199,6 +1199,7 @@ static void ndisc_router_discovery(struct sk_buff *skb) - struct neighbour *neigh = NULL; - struct inet6_dev *in6_dev; - struct fib6_info *rt = NULL; -+ u32 defrtr_usr_metric; - struct net *net; - int lifetime; - struct ndisc_options ndopts; -@@ -1329,18 +1330,21 @@ static void ndisc_router_discovery(struct sk_buff *skb) - return; - } - } -- if (rt && lifetime == 0) { -+ /* Set default route metric as specified by user */ -+ defrtr_usr_metric = in6_dev->cnf.ra_defrtr_metric; -+ /* delete the route if lifetime is 0 or if metric needs change */ -+ if (rt && (lifetime == 0 || rt->fib6_metric != defrtr_usr_metric)) { - ip6_del_rt(net, rt, false); - rt = NULL; - } - -- ND_PRINTK(3, info, "RA: rt: %p lifetime: %d, for dev: %s\n", -- rt, lifetime, skb->dev->name); -+ ND_PRINTK(3, info, "RA: rt: %p lifetime: %d, metric: %d, for dev: %s\n", -+ rt, lifetime, defrtr_usr_metric, skb->dev->name); - if (!rt && lifetime) { - ND_PRINTK(3, info, "RA: adding default router\n"); - - rt = rt6_add_dflt_router(net, &ipv6_hdr(skb)->saddr, -- skb->dev, pref); -+ skb->dev, pref, defrtr_usr_metric); - if (!rt) { - ND_PRINTK(0, err, - "RA: %s failed to add default route\n", -diff --git a/net/ipv6/route.c b/net/ipv6/route.c -index cdf215442d37..2a32cc7db014 100644 ---- a/net/ipv6/route.c -+++ b/net/ipv6/route.c -@@ -4269,11 +4269,12 @@ struct fib6_info *rt6_get_dflt_router(struct net *net, - struct fib6_info *rt6_add_dflt_router(struct net *net, - const struct in6_addr *gwaddr, - struct net_device *dev, -- unsigned int pref) -+ unsigned int pref, -+ u32 defrtr_usr_metric) - { - struct fib6_config cfg = { - .fc_table = l3mdev_fib_table(dev) ? : RT6_TABLE_DFLT, -- .fc_metric = IP6_RT_PRIO_USER, -+ .fc_metric = defrtr_usr_metric, - .fc_ifindex = dev->ifindex, - .fc_flags = RTF_GATEWAY | RTF_ADDRCONF | RTF_DEFAULT | - RTF_UP | RTF_EXPIRES | RTF_PREF(pref), --- -2.25.1 - diff --git a/patch/0001-net-arp-introduce-arp_evict_nocarrier-sysctl-paramet.patch b/patch/0001-net-arp-introduce-arp_evict_nocarrier-sysctl-paramet.patch deleted file mode 100644 index 8c09606fe..000000000 --- a/patch/0001-net-arp-introduce-arp_evict_nocarrier-sysctl-paramet.patch +++ /dev/null @@ -1,217 +0,0 @@ -From fcdb44d08a95003c3d040aecdee286156ec6f34e Mon Sep 17 00:00:00 2001 -From: James Prestwood -Date: Mon, 1 Nov 2021 10:36:28 -0700 -Subject: [PATCH] net: arp: introduce arp_evict_nocarrier sysctl parameter - -This change introduces a new sysctl parameter, arp_evict_nocarrier. -When set (default) the ARP cache will be cleared on a NOCARRIER event. -This new option has been defaulted to '1' which maintains existing -behavior. - -Clearing the ARP cache on NOCARRIER is relatively new, introduced by: - -commit 859bd2ef1fc1110a8031b967ee656c53a6260a76 -Author: David Ahern -Date: Thu Oct 11 20:33:49 2018 -0700 - - net: Evict neighbor entries on carrier down - -The reason for this changes is to prevent the ARP cache from being -cleared when a wireless device roams. Specifically for wireless roams -the ARP cache should not be cleared because the underlying network has not -changed. Clearing the ARP cache in this case can introduce significant -delays sending out packets after a roam. - -A user reported such a situation here: - -https://lore.kernel.org/linux-wireless/CACsRnHWa47zpx3D1oDq9JYnZWniS8yBwW1h0WAVZ6vrbwL_S0w@mail.gmail.com/ - -After some investigation it was found that the kernel was holding onto -packets until ARP finished which resulted in this 1 second delay. It -was also found that the first ARP who-has was never responded to, -which is actually what caues the delay. This change is more or less -working around this behavior, but again, there is no reason to clear -the cache on a roam anyways. - -As for the unanswered who-has, we know the packet made it OTA since -it was seen while monitoring. Why it never received a response is -unknown. In any case, since this is a problem on the AP side of things -all that can be done is to work around it until it is solved. - -Some background on testing/reproducing the packet delay: - -Hardware: - - 2 access points configured for Fast BSS Transition (Though I don't - see why regular reassociation wouldn't have the same behavior) - - Wireless station running IWD as supplicant - - A device on network able to respond to pings (I used one of the APs) - -Procedure: - - Connect to first AP - - Ping once to establish an ARP entry - - Start a tcpdump - - Roam to second AP - - Wait for operstate UP event, and note the timestamp - - Start pinging - -Results: - -Below is the tcpdump after UP. It was recorded the interface went UP at -10:42:01.432875. - -10:42:01.461871 ARP, Request who-has 192.168.254.1 tell 192.168.254.71, length 28 -10:42:02.497976 ARP, Request who-has 192.168.254.1 tell 192.168.254.71, length 28 -10:42:02.507162 ARP, Reply 192.168.254.1 is-at ac:86:74:55:b0:20, length 46 -10:42:02.507185 IP 192.168.254.71 > 192.168.254.1: ICMP echo request, id 52792, seq 1, length 64 -10:42:02.507205 IP 192.168.254.71 > 192.168.254.1: ICMP echo request, id 52792, seq 2, length 64 -10:42:02.507212 IP 192.168.254.71 > 192.168.254.1: ICMP echo request, id 52792, seq 3, length 64 -10:42:02.507219 IP 192.168.254.71 > 192.168.254.1: ICMP echo request, id 52792, seq 4, length 64 -10:42:02.507225 IP 192.168.254.71 > 192.168.254.1: ICMP echo request, id 52792, seq 5, length 64 -10:42:02.507232 IP 192.168.254.71 > 192.168.254.1: ICMP echo request, id 52792, seq 6, length 64 -10:42:02.515373 IP 192.168.254.1 > 192.168.254.71: ICMP echo reply, id 52792, seq 1, length 64 -10:42:02.521399 IP 192.168.254.1 > 192.168.254.71: ICMP echo reply, id 52792, seq 2, length 64 -10:42:02.521612 IP 192.168.254.1 > 192.168.254.71: ICMP echo reply, id 52792, seq 3, length 64 -10:42:02.521941 IP 192.168.254.1 > 192.168.254.71: ICMP echo reply, id 52792, seq 4, length 64 -10:42:02.522419 IP 192.168.254.1 > 192.168.254.71: ICMP echo reply, id 52792, seq 5, length 64 -10:42:02.523085 IP 192.168.254.1 > 192.168.254.71: ICMP echo reply, id 52792, seq 6, length 64 - -You can see the first ARP who-has went out very quickly after UP, but -was never responded to. Nearly a second later the kernel retries and -gets a response. Only then do the ping packets go out. If an ARP entry -is manually added prior to UP (after the cache is cleared) it is seen -that the first ping is never responded to, so its not only an issue with -ARP but with data packets in general. - -As mentioned prior, the wireless interface was also monitored to verify -the ping/ARP packet made it OTA which was observed to be true. - -Signed-off-by: James Prestwood -Reviewed-by: David Ahern -Signed-off-by: Jakub Kicinski ---- - Documentation/networking/ip-sysctl.rst | 9 +++++++++ - include/linux/inetdevice.h | 2 ++ - include/uapi/linux/ip.h | 1 + - include/uapi/linux/sysctl.h | 1 + - net/ipv4/arp.c | 11 ++++++++++- - net/ipv4/devinet.c | 4 ++++ - 6 files changed, 27 insertions(+), 1 deletion(-) - -diff --git a/Documentation/networking/ip-sysctl.rst b/Documentation/networking/ip-sysctl.rst -index 16b8bf72feaf..18fde4ed7a5e 100644 ---- a/Documentation/networking/ip-sysctl.rst -+++ b/Documentation/networking/ip-sysctl.rst -@@ -1611,6 +1611,15 @@ arp_accept - BOOLEAN - gratuitous arp frame, the arp table will be updated regardless - if this setting is on or off. - -+arp_evict_nocarrier - BOOLEAN -+ Clears the ARP cache on NOCARRIER events. This option is important for -+ wireless devices where the ARP cache should not be cleared when roaming -+ between access points on the same network. In most cases this should -+ remain as the default (1). -+ -+ - 1 - (default): Clear the ARP cache on NOCARRIER events -+ - 0 - Do not clear ARP cache on NOCARRIER events -+ - mcast_solicit - INTEGER - The maximum number of multicast probes in INCOMPLETE state, - when the associated hardware address is unknown. Defaults -diff --git a/include/linux/inetdevice.h b/include/linux/inetdevice.h -index a038feb63f23..518b484a7f07 100644 ---- a/include/linux/inetdevice.h -+++ b/include/linux/inetdevice.h -@@ -133,6 +133,8 @@ static inline void ipv4_devconf_setall(struct in_device *in_dev) - #define IN_DEV_ARP_ANNOUNCE(in_dev) IN_DEV_MAXCONF((in_dev), ARP_ANNOUNCE) - #define IN_DEV_ARP_IGNORE(in_dev) IN_DEV_MAXCONF((in_dev), ARP_IGNORE) - #define IN_DEV_ARP_NOTIFY(in_dev) IN_DEV_MAXCONF((in_dev), ARP_NOTIFY) -+#define IN_DEV_ARP_EVICT_NOCARRIER(in_dev) IN_DEV_ANDCONF((in_dev), \ -+ ARP_EVICT_NOCARRIER) - - struct in_ifaddr { - struct hlist_node hash; -diff --git a/include/uapi/linux/ip.h b/include/uapi/linux/ip.h -index e42d13b55cf3..e00bbb9c47bb 100644 ---- a/include/uapi/linux/ip.h -+++ b/include/uapi/linux/ip.h -@@ -169,6 +169,7 @@ enum - IPV4_DEVCONF_DROP_UNICAST_IN_L2_MULTICAST, - IPV4_DEVCONF_DROP_GRATUITOUS_ARP, - IPV4_DEVCONF_BC_FORWARDING, -+ IPV4_DEVCONF_ARP_EVICT_NOCARRIER, - __IPV4_DEVCONF_MAX - }; - -diff --git a/include/uapi/linux/sysctl.h b/include/uapi/linux/sysctl.h -index 1e05d3caa712..6a3b194c50fe 100644 ---- a/include/uapi/linux/sysctl.h -+++ b/include/uapi/linux/sysctl.h -@@ -482,6 +482,7 @@ enum - NET_IPV4_CONF_PROMOTE_SECONDARIES=20, - NET_IPV4_CONF_ARP_ACCEPT=21, - NET_IPV4_CONF_ARP_NOTIFY=22, -+ NET_IPV4_CONF_ARP_EVICT_NOCARRIER=23, - }; - - /* /proc/sys/net/ipv4/netfilter */ -diff --git a/net/ipv4/arp.c b/net/ipv4/arp.c -index 922dd73e5740..857a144b1ea9 100644 ---- a/net/ipv4/arp.c -+++ b/net/ipv4/arp.c -@@ -1247,6 +1247,8 @@ static int arp_netdev_event(struct notifier_block *this, unsigned long event, - { - struct net_device *dev = netdev_notifier_info_to_dev(ptr); - struct netdev_notifier_change_info *change_info; -+ struct in_device *in_dev; -+ bool evict_nocarrier; - - switch (event) { - case NETDEV_CHANGEADDR: -@@ -1257,7 +1259,14 @@ static int arp_netdev_event(struct notifier_block *this, unsigned long event, - change_info = ptr; - if (change_info->flags_changed & IFF_NOARP) - neigh_changeaddr(&arp_tbl, dev); -- if (!netif_carrier_ok(dev)) -+ -+ in_dev = __in_dev_get_rtnl(dev); -+ if (!in_dev) -+ evict_nocarrier = true; -+ else -+ evict_nocarrier = IN_DEV_ARP_EVICT_NOCARRIER(in_dev); -+ -+ if (evict_nocarrier && !netif_carrier_ok(dev)) - neigh_carrier_down(&arp_tbl, dev); - break; - default: -diff --git a/net/ipv4/devinet.c b/net/ipv4/devinet.c -index f4468980b675..ec73a0d52d3e 100644 ---- a/net/ipv4/devinet.c -+++ b/net/ipv4/devinet.c -@@ -75,6 +75,7 @@ static struct ipv4_devconf ipv4_devconf = { - [IPV4_DEVCONF_SHARED_MEDIA - 1] = 1, - [IPV4_DEVCONF_IGMPV2_UNSOLICITED_REPORT_INTERVAL - 1] = 10000 /*ms*/, - [IPV4_DEVCONF_IGMPV3_UNSOLICITED_REPORT_INTERVAL - 1] = 1000 /*ms*/, -+ [IPV4_DEVCONF_ARP_EVICT_NOCARRIER - 1] = 1, - }, - }; - -@@ -87,6 +88,7 @@ static struct ipv4_devconf ipv4_devconf_dflt = { - [IPV4_DEVCONF_ACCEPT_SOURCE_ROUTE - 1] = 1, - [IPV4_DEVCONF_IGMPV2_UNSOLICITED_REPORT_INTERVAL - 1] = 10000 /*ms*/, - [IPV4_DEVCONF_IGMPV3_UNSOLICITED_REPORT_INTERVAL - 1] = 1000 /*ms*/, -+ [IPV4_DEVCONF_ARP_EVICT_NOCARRIER - 1] = 1, - }, - }; - -@@ -2532,6 +2534,8 @@ static struct devinet_sysctl_table { - DEVINET_SYSCTL_RW_ENTRY(ARP_IGNORE, "arp_ignore"), - DEVINET_SYSCTL_RW_ENTRY(ARP_ACCEPT, "arp_accept"), - DEVINET_SYSCTL_RW_ENTRY(ARP_NOTIFY, "arp_notify"), -+ DEVINET_SYSCTL_RW_ENTRY(ARP_EVICT_NOCARRIER, -+ "arp_evict_nocarrier"), - DEVINET_SYSCTL_RW_ENTRY(PROXY_ARP_PVLAN, "proxy_arp_pvlan"), - DEVINET_SYSCTL_RW_ENTRY(FORCE_IGMP_VERSION, - "force_igmp_version"), --- -2.17.1 - diff --git a/patch/0001-net-ipv6-Introduce-accept_unsolicited_na-knob-to-imp.patch b/patch/0001-net-ipv6-Introduce-accept_unsolicited_na-knob-to-imp.patch deleted file mode 100644 index 854a5362c..000000000 --- a/patch/0001-net-ipv6-Introduce-accept_unsolicited_na-knob-to-imp.patch +++ /dev/null @@ -1,438 +0,0 @@ -From a831dae1f2fadea0e173b5192d2a9bb70bb06e07 Mon Sep 17 00:00:00 2001 -From: Arun Ajith S -Date: Fri, 15 Apr 2022 08:34:02 +0000 -Subject: [PATCH 1/2] net/ipv6: Introduce accept_unsolicited_na knob to - implement router-side changes for RFC9131 - -Add a new neighbour cache entry in STALE state for routers on receiving -an unsolicited (gratuitous) neighbour advertisement with -target link-layer-address option specified. -This is similar to the arp_accept configuration for IPv4. -A new sysctl endpoint is created to turn on this behaviour: -/proc/sys/net/ipv6/conf/interface/accept_unsolicited_na. - -Signed-off-by: Arun Ajith S -Reviewed-by: David Ahern -Signed-off-by: David S. Miller ---- - Documentation/networking/ip-sysctl.rst | 27 ++ - include/linux/ipv6.h | 1 + - include/uapi/linux/ipv6.h | 1 + - net/ipv6/addrconf.c | 10 + - net/ipv6/ndisc.c | 20 +- - tools/testing/selftests/net/Makefile | 1 + - .../net/ndisc_unsolicited_na_test.sh | 255 ++++++++++++++++++ - 7 files changed, 314 insertions(+), 1 deletion(-) - create mode 100755 tools/testing/selftests/net/ndisc_unsolicited_na_test.sh - -diff --git a/Documentation/networking/ip-sysctl.rst b/Documentation/networking/ip-sysctl.rst -index 25e6673a085a..76c645584e93 100644 ---- a/Documentation/networking/ip-sysctl.rst -+++ b/Documentation/networking/ip-sysctl.rst -@@ -2256,6 +2256,33 @@ drop_unsolicited_na - BOOLEAN - - By default this is turned off. - -+accept_unsolicited_na - BOOLEAN -+ Add a new neighbour cache entry in STALE state for routers on receiving an -+ unsolicited neighbour advertisement with target link-layer address option -+ specified. This is as per router-side behavior documented in RFC9131. -+ This has lower precedence than drop_unsolicited_na. -+ -+ ==== ====== ====== ============================================== -+ drop accept fwding behaviour -+ ---- ------ ------ ---------------------------------------------- -+ 1 X X Drop NA packet and don't pass up the stack -+ 0 0 X Pass NA packet up the stack, don't update NC -+ 0 1 0 Pass NA packet up the stack, don't update NC -+ 0 1 1 Pass NA packet up the stack, and add a STALE -+ NC entry -+ ==== ====== ====== ============================================== -+ -+ This will optimize the return path for the initial off-link communication -+ that is initiated by a directly connected host, by ensuring that -+ the first-hop router which turns on this setting doesn't have to -+ buffer the initial return packets to do neighbour-solicitation. -+ The prerequisite is that the host is configured to send -+ unsolicited neighbour advertisements on interface bringup. -+ This setting should be used in conjunction with the ndisc_notify setting -+ on the host to satisfy this prerequisite. -+ -+ By default this is turned off. -+ - enhanced_dad - BOOLEAN - Include a nonce option in the IPv6 neighbor solicitation messages used for - duplicate address detection per RFC7527. A received DAD NS will only signal -diff --git a/include/linux/ipv6.h b/include/linux/ipv6.h -index dda61d150a13..65862d6e0d8f 100644 ---- a/include/linux/ipv6.h -+++ b/include/linux/ipv6.h -@@ -60,6 +60,7 @@ struct ipv6_devconf { - __s32 suppress_frag_ndisc; - __s32 accept_ra_mtu; - __s32 drop_unsolicited_na; -+ __s32 accept_unsolicited_na; - struct ipv6_stable_secret { - bool initialized; - struct in6_addr secret; -diff --git a/include/uapi/linux/ipv6.h b/include/uapi/linux/ipv6.h -index 13e8751bf24a..6c320b140806 100644 ---- a/include/uapi/linux/ipv6.h -+++ b/include/uapi/linux/ipv6.h -@@ -189,6 +189,7 @@ enum { - DEVCONF_ACCEPT_RA_RT_INFO_MIN_PLEN, - DEVCONF_NDISC_TCLASS, - DEVCONF_RPL_SEG_ENABLED, -+ DEVCONF_ACCEPT_UNSOLICITED_NA, - DEVCONF_MAX - }; - -diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c -index 8b6eb384bac7..a238476403a7 100644 ---- a/net/ipv6/addrconf.c -+++ b/net/ipv6/addrconf.c -@@ -5516,6 +5516,7 @@ static inline void ipv6_store_devconf(struct ipv6_devconf *cnf, - array[DEVCONF_DISABLE_POLICY] = cnf->disable_policy; - array[DEVCONF_NDISC_TCLASS] = cnf->ndisc_tclass; - array[DEVCONF_RPL_SEG_ENABLED] = cnf->rpl_seg_enabled; -+ array[DEVCONF_ACCEPT_UNSOLICITED_NA] = cnf->accept_unsolicited_na; - } - - static inline size_t inet6_ifla6_size(void) -@@ -6896,6 +6897,15 @@ static const struct ctl_table addrconf_sysctl[] = { - .mode = 0644, - .proc_handler = proc_dointvec, - }, -+ { -+ .procname = "accept_unsolicited_na", -+ .data = &ipv6_devconf.accept_unsolicited_na, -+ .maxlen = sizeof(int), -+ .mode = 0644, -+ .proc_handler = proc_dointvec, -+ .extra1 = (void *)SYSCTL_ZERO, -+ .extra2 = (void *)SYSCTL_ONE, -+ }, - { - /* sentinel */ - } -diff --git a/net/ipv6/ndisc.c b/net/ipv6/ndisc.c -index 76717478f173..fd37aae022d3 100644 ---- a/net/ipv6/ndisc.c -+++ b/net/ipv6/ndisc.c -@@ -964,6 +964,7 @@ static void ndisc_recv_na(struct sk_buff *skb) - struct inet6_dev *idev = __in6_dev_get(dev); - struct inet6_ifaddr *ifp; - struct neighbour *neigh; -+ bool create_neigh; - - if (skb->len < sizeof(struct nd_msg)) { - ND_PRINTK(2, warn, "NA: packet too short\n"); -@@ -984,6 +985,7 @@ static void ndisc_recv_na(struct sk_buff *skb) - /* For some 802.11 wireless deployments (and possibly other networks), - * there will be a NA proxy and unsolicitd packets are attacks - * and thus should not be accepted. -+ * drop_unsolicited_na takes precedence over accept_unsolicited_na - */ - if (!msg->icmph.icmp6_solicited && idev && - idev->cnf.drop_unsolicited_na) -@@ -1024,7 +1026,23 @@ static void ndisc_recv_na(struct sk_buff *skb) - in6_ifa_put(ifp); - return; - } -- neigh = neigh_lookup(&nd_tbl, &msg->target, dev); -+ /* RFC 9131 updates original Neighbour Discovery RFC 4861. -+ * An unsolicited NA can now create a neighbour cache entry -+ * on routers if it has Target LL Address option. -+ * -+ * drop accept fwding behaviour -+ * ---- ------ ------ ---------------------------------------------- -+ * 1 X X Drop NA packet and don't pass up the stack -+ * 0 0 X Pass NA packet up the stack, don't update NC -+ * 0 1 0 Pass NA packet up the stack, don't update NC -+ * 0 1 1 Pass NA packet up the stack, and add a STALE -+ * NC entry -+ * Note that we don't do a (daddr == all-routers-mcast) check. -+ */ -+ create_neigh = !msg->icmph.icmp6_solicited && lladdr && -+ idev && idev->cnf.forwarding && -+ idev->cnf.accept_unsolicited_na; -+ neigh = __neigh_lookup(&nd_tbl, &msg->target, dev, create_neigh); - - if (neigh) { - u8 old_flags = neigh->flags; -diff --git a/tools/testing/selftests/net/Makefile b/tools/testing/selftests/net/Makefile -index ef352477cac6..35d14273d61e 100644 ---- a/tools/testing/selftests/net/Makefile -+++ b/tools/testing/selftests/net/Makefile -@@ -21,6 +21,7 @@ TEST_PROGS += rxtimestamp.sh - TEST_PROGS += devlink_port_split.py - TEST_PROGS += drop_monitor_tests.sh - TEST_PROGS += vrf_route_leaking.sh -+TEST_PROGS += ndisc_unsolicited_na_test.sh - TEST_PROGS_EXTENDED := in_netns.sh - TEST_GEN_FILES = socket nettest - TEST_GEN_FILES += psock_fanout psock_tpacket msg_zerocopy reuseport_addr_any -diff --git a/tools/testing/selftests/net/ndisc_unsolicited_na_test.sh b/tools/testing/selftests/net/ndisc_unsolicited_na_test.sh -new file mode 100755 -index 000000000000..f508657ee126 ---- /dev/null -+++ b/tools/testing/selftests/net/ndisc_unsolicited_na_test.sh -@@ -0,0 +1,255 @@ -+#!/bin/bash -+# SPDX-License-Identifier: GPL-2.0 -+ -+# This test is for the accept_unsolicited_na feature to -+# enable RFC9131 behaviour. The following is the test-matrix. -+# drop accept fwding behaviour -+# ---- ------ ------ ---------------------------------------------- -+# 1 X X Drop NA packet and don't pass up the stack -+# 0 0 X Pass NA packet up the stack, don't update NC -+# 0 1 0 Pass NA packet up the stack, don't update NC -+# 0 1 1 Pass NA packet up the stack, and add a STALE -+# NC entry -+ -+ret=0 -+# Kselftest framework requirement - SKIP code is 4. -+ksft_skip=4 -+ -+PAUSE_ON_FAIL=no -+PAUSE=no -+ -+HOST_NS="ns-host" -+ROUTER_NS="ns-router" -+ -+HOST_INTF="veth-host" -+ROUTER_INTF="veth-router" -+ -+ROUTER_ADDR="2000:20::1" -+HOST_ADDR="2000:20::2" -+SUBNET_WIDTH=64 -+ROUTER_ADDR_WITH_MASK="${ROUTER_ADDR}/${SUBNET_WIDTH}" -+HOST_ADDR_WITH_MASK="${HOST_ADDR}/${SUBNET_WIDTH}" -+ -+IP_HOST="ip -6 -netns ${HOST_NS}" -+IP_HOST_EXEC="ip netns exec ${HOST_NS}" -+IP_ROUTER="ip -6 -netns ${ROUTER_NS}" -+IP_ROUTER_EXEC="ip netns exec ${ROUTER_NS}" -+ -+tcpdump_stdout= -+tcpdump_stderr= -+ -+log_test() -+{ -+ local rc=$1 -+ local expected=$2 -+ local msg="$3" -+ -+ if [ ${rc} -eq ${expected} ]; then -+ printf " TEST: %-60s [ OK ]\n" "${msg}" -+ nsuccess=$((nsuccess+1)) -+ else -+ ret=1 -+ nfail=$((nfail+1)) -+ printf " TEST: %-60s [FAIL]\n" "${msg}" -+ if [ "${PAUSE_ON_FAIL}" = "yes" ]; then -+ echo -+ echo "hit enter to continue, 'q' to quit" -+ read a -+ [ "$a" = "q" ] && exit 1 -+ fi -+ fi -+ -+ if [ "${PAUSE}" = "yes" ]; then -+ echo -+ echo "hit enter to continue, 'q' to quit" -+ read a -+ [ "$a" = "q" ] && exit 1 -+ fi -+} -+ -+setup() -+{ -+ set -e -+ -+ local drop_unsolicited_na=$1 -+ local accept_unsolicited_na=$2 -+ local forwarding=$3 -+ -+ # Setup two namespaces and a veth tunnel across them. -+ # On end of the tunnel is a router and the other end is a host. -+ ip netns add ${HOST_NS} -+ ip netns add ${ROUTER_NS} -+ ${IP_ROUTER} link add ${ROUTER_INTF} type veth \ -+ peer name ${HOST_INTF} netns ${HOST_NS} -+ -+ # Enable IPv6 on both router and host, and configure static addresses. -+ # The router here is the DUT -+ # Setup router configuration as specified by the arguments. -+ # forwarding=0 case is to check that a non-router -+ # doesn't add neighbour entries. -+ ROUTER_CONF=net.ipv6.conf.${ROUTER_INTF} -+ ${IP_ROUTER_EXEC} sysctl -qw \ -+ ${ROUTER_CONF}.forwarding=${forwarding} -+ ${IP_ROUTER_EXEC} sysctl -qw \ -+ ${ROUTER_CONF}.drop_unsolicited_na=${drop_unsolicited_na} -+ ${IP_ROUTER_EXEC} sysctl -qw \ -+ ${ROUTER_CONF}.accept_unsolicited_na=${accept_unsolicited_na} -+ ${IP_ROUTER_EXEC} sysctl -qw ${ROUTER_CONF}.disable_ipv6=0 -+ ${IP_ROUTER} addr add ${ROUTER_ADDR_WITH_MASK} dev ${ROUTER_INTF} -+ -+ # Turn on ndisc_notify on host interface so that -+ # the host sends unsolicited NAs. -+ HOST_CONF=net.ipv6.conf.${HOST_INTF} -+ ${IP_HOST_EXEC} sysctl -qw ${HOST_CONF}.ndisc_notify=1 -+ ${IP_HOST_EXEC} sysctl -qw ${HOST_CONF}.disable_ipv6=0 -+ ${IP_HOST} addr add ${HOST_ADDR_WITH_MASK} dev ${HOST_INTF} -+ -+ set +e -+} -+ -+start_tcpdump() { -+ set -e -+ tcpdump_stdout=`mktemp` -+ tcpdump_stderr=`mktemp` -+ ${IP_ROUTER_EXEC} timeout 15s \ -+ tcpdump --immediate-mode -tpni ${ROUTER_INTF} -c 1 \ -+ "icmp6 && icmp6[0] == 136 && src ${HOST_ADDR}" \ -+ > ${tcpdump_stdout} 2> /dev/null -+ set +e -+} -+ -+cleanup_tcpdump() -+{ -+ set -e -+ [[ ! -z ${tcpdump_stdout} ]] && rm -f ${tcpdump_stdout} -+ [[ ! -z ${tcpdump_stderr} ]] && rm -f ${tcpdump_stderr} -+ tcpdump_stdout= -+ tcpdump_stderr= -+ set +e -+} -+ -+cleanup() -+{ -+ cleanup_tcpdump -+ ip netns del ${HOST_NS} -+ ip netns del ${ROUTER_NS} -+} -+ -+link_up() { -+ set -e -+ ${IP_ROUTER} link set dev ${ROUTER_INTF} up -+ ${IP_HOST} link set dev ${HOST_INTF} up -+ set +e -+} -+ -+verify_ndisc() { -+ local drop_unsolicited_na=$1 -+ local accept_unsolicited_na=$2 -+ local forwarding=$3 -+ -+ neigh_show_output=$(${IP_ROUTER} neigh show \ -+ to ${HOST_ADDR} dev ${ROUTER_INTF} nud stale) -+ if [ ${drop_unsolicited_na} -eq 0 ] && \ -+ [ ${accept_unsolicited_na} -eq 1 ] && \ -+ [ ${forwarding} -eq 1 ]; then -+ # Neighbour entry expected to be present for 011 case -+ [[ ${neigh_show_output} ]] -+ else -+ # Neighbour entry expected to be absent for all other cases -+ [[ -z ${neigh_show_output} ]] -+ fi -+} -+ -+test_unsolicited_na_common() -+{ -+ # Setup the test bed, but keep links down -+ setup $1 $2 $3 -+ -+ # Bring the link up, wait for the NA, -+ # and add a delay to ensure neighbour processing is done. -+ link_up -+ start_tcpdump -+ -+ # Verify the neighbour table -+ verify_ndisc $1 $2 $3 -+ -+} -+ -+test_unsolicited_na_combination() { -+ test_unsolicited_na_common $1 $2 $3 -+ test_msg=("test_unsolicited_na: " -+ "drop_unsolicited_na=$1 " -+ "accept_unsolicited_na=$2 " -+ "forwarding=$3") -+ log_test $? 0 "${test_msg[*]}" -+ cleanup -+} -+ -+test_unsolicited_na_combinations() { -+ # Args: drop_unsolicited_na accept_unsolicited_na forwarding -+ -+ # Expect entry -+ test_unsolicited_na_combination 0 1 1 -+ -+ # Expect no entry -+ test_unsolicited_na_combination 0 0 0 -+ test_unsolicited_na_combination 0 0 1 -+ test_unsolicited_na_combination 0 1 0 -+ test_unsolicited_na_combination 1 0 0 -+ test_unsolicited_na_combination 1 0 1 -+ test_unsolicited_na_combination 1 1 0 -+ test_unsolicited_na_combination 1 1 1 -+} -+ -+############################################################################### -+# usage -+ -+usage() -+{ -+ cat < /dev/null -+ -+test_unsolicited_na_combinations -+ -+printf "\nTests passed: %3d\n" ${nsuccess} -+printf "Tests failed: %3d\n" ${nfail} -+ -+exit $ret --- -2.25.1 - diff --git a/patch/0001-platform-mellanox-Introduce-support-for-rack-manager.patch b/patch/0001-platform-mellanox-Introduce-support-for-rack-manager.patch deleted file mode 100644 index 67c4a5f6e..000000000 --- a/patch/0001-platform-mellanox-Introduce-support-for-rack-manager.patch +++ /dev/null @@ -1,426 +0,0 @@ -From e81bfa677c49da39ae72d58d96c997dbf2e085b3 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 8 Feb 2023 08:33:18 +0200 -Subject: [PATCH backport 6.1.42 01/85] platform: mellanox: Introduce support - for rack manager switch - -The rack switch is designed to provide high bandwidth, low latency -connectivity using optical fiber as the primary interconnect. - -System supports 32 OSFP ports, non-blocking switching capacity of -25.6Tbps. -System equipped with: -- 2 replaceable power supplies (AC) with 1+1 redundancy model. -- 7 replaceable fan drawers with 6+1 redundancy model. -- 2 External Root of Trust or EROT (Glacier) devices for securing - ASICs firmware. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych -Link: https://lore.kernel.org/r/20230208063331.15560-2-vadimp@nvidia.com -Signed-off-by: Hans de Goede ---- - drivers/platform/x86/mlx-platform.c | 261 ++++++++++++++++++++++++++++ - 1 file changed, 261 insertions(+) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 2fac05a17a5c..3e4adeb20a7e 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -90,6 +90,12 @@ - #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88 - #define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89 - #define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a -+#define MLXPLAT_CPLD_LPC_REG_EROT_OFFSET 0x91 -+#define MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET 0x92 -+#define MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET 0x93 -+#define MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET 0x94 -+#define MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET 0x95 -+#define MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET 0x96 - #define MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET 0x9a - #define MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET 0x9b - #define MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET 0x9c -@@ -109,6 +115,8 @@ - #define MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET 0xaa - #define MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET 0xab - #define MLXPLAT_CPLD_LPC_REG_LC_PWR_ON 0xb2 -+#define MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET 0xc2 -+#define MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT 0xc3 - #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7 - #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8 - #define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9 -@@ -214,6 +222,7 @@ - #define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0) - #define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4) - #define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0) -+#define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0) - #define MLXPLAT_CPLD_I2C_CAP_BIT 0x04 - #define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5, MLXPLAT_CPLD_I2C_CAP_BIT) - -@@ -243,6 +252,7 @@ - #define MLXPLAT_CPLD_CH2_ETH_MODULAR 3 - #define MLXPLAT_CPLD_CH3_ETH_MODULAR 43 - #define MLXPLAT_CPLD_CH4_ETH_MODULAR 51 -+#define MLXPLAT_CPLD_CH2_RACK_SWITCH 18 - - /* Number of LPC attached MUX platform devices */ - #define MLXPLAT_CPLD_LPC_MUX_DEVS 4 -@@ -280,6 +290,9 @@ - /* Minimum power required for turning on Ethernet modular system (WATT) */ - #define MLXPLAT_CPLD_ETH_MODULAR_PWR_MIN 50 - -+/* Default value for PWM control register for rack switch system */ -+#define MLXPLAT_REGMAP_NVSWITCH_PWM_DEFAULT 0xf4 -+ - /* mlxplat_priv - platform private data - * @pdev_i2c - i2c controller platform device - * @pdev_mux - array of mux platform devices -@@ -460,6 +473,36 @@ static struct i2c_mux_reg_platform_data mlxplat_modular_mux_data[] = { - }, - }; - -+/* Platform channels for rack swicth system family */ -+static const int mlxplat_rack_switch_channels[] = { -+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, -+}; -+ -+/* Platform rack switch mux data */ -+static struct i2c_mux_reg_platform_data mlxplat_rack_switch_mux_data[] = { -+ { -+ .parent = 1, -+ .base_nr = MLXPLAT_CPLD_CH1, -+ .write_only = 1, -+ .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, -+ .reg_size = 1, -+ .idle_in_use = 1, -+ .values = mlxplat_rack_switch_channels, -+ .n_values = ARRAY_SIZE(mlxplat_rack_switch_channels), -+ }, -+ { -+ .parent = 1, -+ .base_nr = MLXPLAT_CPLD_CH2_RACK_SWITCH, -+ .write_only = 1, -+ .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, -+ .reg_size = 1, -+ .idle_in_use = 1, -+ .values = mlxplat_msn21xx_channels, -+ .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), -+ }, -+ -+}; -+ - /* Platform hotplug devices */ - static struct i2c_board_info mlxplat_mlxcpld_pwr[] = { - { -@@ -2064,6 +2107,97 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_nvlink_blade_data = { - .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, - }; - -+/* Platform hotplug for switch systems family data */ -+static struct mlxreg_core_data mlxplat_mlxcpld_erot_ap_items_data[] = { -+ { -+ .label = "erot1_ap", -+ .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, -+ .mask = BIT(0), -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "erot2_ap", -+ .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, -+ .mask = BIT(1), -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+}; -+ -+static struct mlxreg_core_data mlxplat_mlxcpld_erot_error_items_data[] = { -+ { -+ .label = "erot1_error", -+ .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, -+ .mask = BIT(0), -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "erot2_error", -+ .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, -+ .mask = BIT(1), -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+}; -+ -+static struct mlxreg_core_item mlxplat_mlxcpld_rack_switch_items[] = { -+ { -+ .data = mlxplat_mlxcpld_ext_psu_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, -+ .mask = MLXPLAT_CPLD_PSU_EXT_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), -+ .inversed = 1, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_ext_pwr_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, -+ .mask = MLXPLAT_CPLD_PWR_EXT_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), -+ .inversed = 0, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_default_ng_fan_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .mask = MLXPLAT_CPLD_FAN_NG_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), -+ .inversed = 1, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_erot_ap_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, -+ .mask = MLXPLAT_CPLD_EROT_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_ap_items_data), -+ .inversed = 1, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_erot_error_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, -+ .mask = MLXPLAT_CPLD_EROT_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_error_items_data), -+ .inversed = 1, -+ .health = false, -+ }, -+}; -+ -+static -+struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_rack_switch_data = { -+ .items = mlxplat_mlxcpld_rack_switch_items, -+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_rack_switch_items), -+ .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, -+ .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, -+ .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, -+ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, -+}; -+ - /* Platform led default data */ - static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { - { -@@ -2947,6 +3081,44 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mask = GENMASK(7, 0) & ~BIT(2), - .mode = 0200, - }, -+ { -+ .label = "erot1_reset", -+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(6), -+ .mode = 0644, -+ }, -+ { -+ .label = "erot2_reset", -+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), -+ .mode = 0644, -+ }, -+ { -+ .label = "erot1_recovery", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(6), -+ .mode = 0644, -+ }, -+ { -+ .label = "erot2_recovery", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), -+ .mode = 0644, -+ }, -+ { -+ .label = "erot1_wp", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0644, -+ .secured = 1, -+ }, -+ { -+ .label = "erot2_wp", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0644, -+ .secured = 1, -+ }, - { - .label = "reset_long_pb", - .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, -@@ -3142,6 +3314,25 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mask = GENMASK(7, 0) & ~BIT(4), - .mode = 0644, - }, -+ { -+ .label = "erot1_ap_reset", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0444, -+ }, -+ { -+ .label = "erot2_ap_reset", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0444, -+ }, -+ { -+ .label = "spi_chnl_select", -+ .reg = MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT, -+ .mask = GENMASK(7, 0), -+ .bit = 1, -+ .mode = 0644, -+ }, - { - .label = "config1", - .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, -@@ -4257,6 +4448,10 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: -@@ -4274,6 +4469,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: -+ case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT: - case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: -@@ -4358,6 +4554,12 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET: -@@ -4382,6 +4584,8 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: -+ case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT: - case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: -@@ -4492,6 +4696,12 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET: -@@ -4516,6 +4726,8 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: -+ case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT: - case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: -@@ -4583,6 +4795,13 @@ static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = { - { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, - }; - -+static const struct reg_default mlxplat_mlxcpld_regmap_rack_switch[] = { -+ { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, MLXPLAT_REGMAP_NVSWITCH_PWM_DEFAULT }, -+ { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, -+ { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, -+ { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, -+}; -+ - static const struct reg_default mlxplat_mlxcpld_regmap_eth_modular[] = { - { MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 0x61 }, - { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, -@@ -4676,6 +4895,20 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng400 = { - .reg_write = mlxplat_mlxcpld_reg_write, - }; - -+static const struct regmap_config mlxplat_mlxcpld_regmap_config_rack_switch = { -+ .reg_bits = 8, -+ .val_bits = 8, -+ .max_register = 255, -+ .cache_type = REGCACHE_FLAT, -+ .writeable_reg = mlxplat_mlxcpld_writeable_reg, -+ .readable_reg = mlxplat_mlxcpld_readable_reg, -+ .volatile_reg = mlxplat_mlxcpld_volatile_reg, -+ .reg_defaults = mlxplat_mlxcpld_regmap_rack_switch, -+ .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_rack_switch), -+ .reg_read = mlxplat_mlxcpld_reg_read, -+ .reg_write = mlxplat_mlxcpld_reg_write, -+}; -+ - static const struct regmap_config mlxplat_mlxcpld_regmap_config_eth_modular = { - .reg_bits = 8, - .val_bits = 8, -@@ -4957,6 +5190,27 @@ static int __init mlxplat_dmi_nvlink_blade_matched(const struct dmi_system_id *d - return 1; - } - -+static int __init mlxplat_dmi_rack_switch_matched(const struct dmi_system_id *dmi) -+{ -+ int i; -+ -+ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; -+ mlxplat_mux_num = ARRAY_SIZE(mlxplat_rack_switch_mux_data); -+ mlxplat_mux_data = mlxplat_rack_switch_mux_data; -+ mlxplat_hotplug = &mlxplat_mlxcpld_rack_switch_data; -+ mlxplat_hotplug->deferred_nr = -+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; -+ mlxplat_led = &mlxplat_default_ng_led_data; -+ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; -+ mlxplat_fan = &mlxplat_default_fan_data; -+ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) -+ mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; -+ mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; -+ mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_rack_switch; -+ -+ return 1; -+} -+ - static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { - { - .callback = mlxplat_dmi_default_wc_matched, -@@ -5014,6 +5268,13 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { - DMI_MATCH(DMI_BOARD_NAME, "VMOD0009"), - }, - }, -+ { -+ .callback = mlxplat_dmi_rack_switch_matched, -+ .matches = { -+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"), -+ DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI142"), -+ }, -+ }, - { - .callback = mlxplat_dmi_ng400_matched, - .matches = { --- -2.20.1 - diff --git a/patch/0001-prevent-bridge-link-show-failure-for-non-eswitch-allowed-devices.patch b/patch/0001-prevent-bridge-link-show-failure-for-non-eswitch-allowed-devices.patch deleted file mode 100644 index 750576465..000000000 --- a/patch/0001-prevent-bridge-link-show-failure-for-non-eswitch-allowed-devices.patch +++ /dev/null @@ -1,45 +0,0 @@ -From e92df790d07a8eea873efcb84776e7b71f81c7d5 Mon Sep 17 00:00:00 2001 -From: Carolina Jubran -Date: Tue, 11 Mar 2025 00:01:44 +0200 -Subject: [PATCH] net/mlx5e: Prevent bridge link show failure for - non-eswitch-allowed devices - -mlx5_eswitch_get_vepa returns -EPERM if the device lacks -eswitch_manager capability, blocking mlx5e_bridge_getlink from -retrieving VEPA mode. Since mlx5e_bridge_getlink implements -ndo_bridge_getlink, returning -EPERM causes bridge link show to fail -instead of skipping devices without this capability. - -To avoid this, return -EOPNOTSUPP from mlx5e_bridge_getlink when -mlx5_eswitch_get_vepa fails, ensuring the command continues processing -other devices while ignoring those without the necessary capability. - -Fixes: 4b89251de024 ("net/mlx5: Support ndo bridge_setlink and getlink") -Signed-off-by: Carolina Jubran -Reviewed-by: Jianbo Liu -Signed-off-by: Tariq Toukan -Reviewed-by: Michal Swiatkowski -Link: https://patch.msgid.link/1741644104-97767-7-git-send-email-tariqt@nvidia.com -Signed-off-by: Paolo Abeni ---- - drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 6 ++---- - 1 file changed, 2 insertions(+), 4 deletions(-) - -diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c -index a814b63ed97e57..8fcaee381b0e09 100644 ---- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c -+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c -@@ -5132,11 +5132,9 @@ static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, - struct mlx5e_priv *priv = netdev_priv(dev); - struct mlx5_core_dev *mdev = priv->mdev; - u8 mode, setting; -- int err; - -- err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting); -- if (err) -- return err; -+ if (mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting)) -+ return -EOPNOTSUPP; - mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB; - return ndo_dflt_bridge_getlink(skb, pid, seq, dev, - mode, diff --git a/patch/0001-x86-platform-Increase-maximum-GPIO-number-for-X86_64.patch b/patch/0001-x86-platform-Increase-maximum-GPIO-number-for-X86_64.patch deleted file mode 100644 index f66c5c9b8..000000000 --- a/patch/0001-x86-platform-Increase-maximum-GPIO-number-for-X86_64.patch +++ /dev/null @@ -1,39 +0,0 @@ -From d7109fe3a0991a0f7b4ac099b78c908e3b619787 Mon Sep 17 00:00:00 2001 -From: Andy Shevchenko -Date: Thu, 26 Aug 2021 18:03:17 +0300 -Subject: [PATCH] x86/platform: Increase maximum GPIO number for X86_64 - -By default the 512 GPIOs is the maximum on any x86 platform. -With, for example, Intel Tiger Lake-H the SoC based controller -occupies up to 480 pins. This leaves only 32 available for -GPIO expanders or other drivers, like PMIC. Hence, bump the -maximum GPIO number to 1024 for X86_64 and leave 512 for X86_32. - -Signed-off-by: Andy Shevchenko -Signed-off-by: Thomas Gleixner -Reviewed-by: Linus Walleij -Reviewed-by: Rafael J. Wysocki -Link: https://lore.kernel.org/r/20210826150317.29435-1-andriy.shevchenko@linux.intel.com ---- - arch/x86/Kconfig | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig -index 421fa9e38c60..10163887c5eb 100644 ---- a/arch/x86/Kconfig -+++ b/arch/x86/Kconfig -@@ -340,6 +340,11 @@ config NEED_PER_CPU_PAGE_FIRST_CHUNK - config ARCH_HIBERNATION_POSSIBLE - def_bool y - -+config ARCH_NR_GPIO -+ int -+ default 1024 if X86_64 -+ default 512 -+ - config ARCH_SUSPEND_POSSIBLE - def_bool y - --- -2.32.0 - diff --git a/patch/0002-net-ipv6-Expand-and-rename-accept_unsolicited_na-to-.patch b/patch/0002-net-ipv6-Expand-and-rename-accept_unsolicited_na-to-.patch deleted file mode 100644 index f5777e368..000000000 --- a/patch/0002-net-ipv6-Expand-and-rename-accept_unsolicited_na-to-.patch +++ /dev/null @@ -1,273 +0,0 @@ -From babe4dd2db417d840b59743dfab4a3dbac367bb2 Mon Sep 17 00:00:00 2001 -From: Arun Ajith S -Date: Mon, 30 May 2022 10:14:14 +0000 -Subject: [PATCH 2/2] net/ipv6: Expand and rename accept_unsolicited_na to - accept_untracked_na - -RFC 9131 changes default behaviour of handling RX of NA messages when the -corresponding entry is absent in the neighbour cache. The current -implementation is limited to accept just unsolicited NAs. However, the -RFC is more generic where it also accepts solicited NAs. Both types -should result in adding a STALE entry for this case. - -Expand accept_untracked_na behaviour to also accept solicited NAs to -be compliant with the RFC and rename the sysctl knob to -accept_untracked_na. - -Fixes: f9a2fb73318e ("net/ipv6: Introduce accept_unsolicited_na knob to implement router-side changes for RFC9131") -Signed-off-by: Arun Ajith S -Reviewed-by: David Ahern -Link: https://lore.kernel.org/r/20220530101414.65439-1-aajith@arista.com -Signed-off-by: Paolo Abeni ---- - Documentation/networking/ip-sysctl.rst | 23 ++++------ - include/linux/ipv6.h | 2 +- - include/uapi/linux/ipv6.h | 2 +- - net/ipv6/addrconf.c | 6 +-- - net/ipv6/ndisc.c | 42 +++++++++++-------- - .../net/ndisc_unsolicited_na_test.sh | 23 +++++----- - 6 files changed, 50 insertions(+), 48 deletions(-) - -diff --git a/Documentation/networking/ip-sysctl.rst b/Documentation/networking/ip-sysctl.rst -index 76c645584e93..38e49fd3ee69 100644 ---- a/Documentation/networking/ip-sysctl.rst -+++ b/Documentation/networking/ip-sysctl.rst -@@ -2256,21 +2256,16 @@ drop_unsolicited_na - BOOLEAN - - By default this is turned off. - --accept_unsolicited_na - BOOLEAN -- Add a new neighbour cache entry in STALE state for routers on receiving an -- unsolicited neighbour advertisement with target link-layer address option -- specified. This is as per router-side behavior documented in RFC9131. -- This has lower precedence than drop_unsolicited_na. -+accept_untracked_na - BOOLEAN -+ Add a new neighbour cache entry in STALE state for routers on receiving a -+ neighbour advertisement (either solicited or unsolicited) with target -+ link-layer address option specified if no neighbour entry is already -+ present for the advertised IPv6 address. Without this knob, NAs received -+ for untracked addresses (absent in neighbour cache) are silently ignored. -+ -+ This is as per router-side behaviour documented in RFC9131. - -- ==== ====== ====== ============================================== -- drop accept fwding behaviour -- ---- ------ ------ ---------------------------------------------- -- 1 X X Drop NA packet and don't pass up the stack -- 0 0 X Pass NA packet up the stack, don't update NC -- 0 1 0 Pass NA packet up the stack, don't update NC -- 0 1 1 Pass NA packet up the stack, and add a STALE -- NC entry -- ==== ====== ====== ============================================== -+ This has lower precedence than drop_unsolicited_na. - - This will optimize the return path for the initial off-link communication - that is initiated by a directly connected host, by ensuring that -diff --git a/include/linux/ipv6.h b/include/linux/ipv6.h -index 65862d6e0d8f..dc2d928b979f 100644 ---- a/include/linux/ipv6.h -+++ b/include/linux/ipv6.h -@@ -60,7 +60,7 @@ struct ipv6_devconf { - __s32 suppress_frag_ndisc; - __s32 accept_ra_mtu; - __s32 drop_unsolicited_na; -- __s32 accept_unsolicited_na; -+ __s32 accept_untracked_na; - struct ipv6_stable_secret { - bool initialized; - struct in6_addr secret; -diff --git a/include/uapi/linux/ipv6.h b/include/uapi/linux/ipv6.h -index 6c320b140806..9cdbc5b04855 100644 ---- a/include/uapi/linux/ipv6.h -+++ b/include/uapi/linux/ipv6.h -@@ -189,7 +189,7 @@ enum { - DEVCONF_ACCEPT_RA_RT_INFO_MIN_PLEN, - DEVCONF_NDISC_TCLASS, - DEVCONF_RPL_SEG_ENABLED, -- DEVCONF_ACCEPT_UNSOLICITED_NA, -+ DEVCONF_ACCEPT_UNTRACKED_NA, - DEVCONF_MAX - }; - -diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c -index a238476403a7..9ac433cfbfaf 100644 ---- a/net/ipv6/addrconf.c -+++ b/net/ipv6/addrconf.c -@@ -5516,7 +5516,7 @@ static inline void ipv6_store_devconf(struct ipv6_devconf *cnf, - array[DEVCONF_DISABLE_POLICY] = cnf->disable_policy; - array[DEVCONF_NDISC_TCLASS] = cnf->ndisc_tclass; - array[DEVCONF_RPL_SEG_ENABLED] = cnf->rpl_seg_enabled; -- array[DEVCONF_ACCEPT_UNSOLICITED_NA] = cnf->accept_unsolicited_na; -+ array[DEVCONF_ACCEPT_UNTRACKED_NA] = cnf->accept_untracked_na; - } - - static inline size_t inet6_ifla6_size(void) -@@ -6898,8 +6898,8 @@ static const struct ctl_table addrconf_sysctl[] = { - .proc_handler = proc_dointvec, - }, - { -- .procname = "accept_unsolicited_na", -- .data = &ipv6_devconf.accept_unsolicited_na, -+ .procname = "accept_untracked_na", -+ .data = &ipv6_devconf.accept_untracked_na, - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec, -diff --git a/net/ipv6/ndisc.c b/net/ipv6/ndisc.c -index fd37aae022d3..f236ed938efd 100644 ---- a/net/ipv6/ndisc.c -+++ b/net/ipv6/ndisc.c -@@ -964,7 +964,7 @@ static void ndisc_recv_na(struct sk_buff *skb) - struct inet6_dev *idev = __in6_dev_get(dev); - struct inet6_ifaddr *ifp; - struct neighbour *neigh; -- bool create_neigh; -+ u8 new_state; - - if (skb->len < sizeof(struct nd_msg)) { - ND_PRINTK(2, warn, "NA: packet too short\n"); -@@ -985,7 +985,7 @@ static void ndisc_recv_na(struct sk_buff *skb) - /* For some 802.11 wireless deployments (and possibly other networks), - * there will be a NA proxy and unsolicitd packets are attacks - * and thus should not be accepted. -- * drop_unsolicited_na takes precedence over accept_unsolicited_na -+ * drop_unsolicited_na takes precedence over accept_untracked_na - */ - if (!msg->icmph.icmp6_solicited && idev && - idev->cnf.drop_unsolicited_na) -@@ -1026,25 +1026,33 @@ static void ndisc_recv_na(struct sk_buff *skb) - in6_ifa_put(ifp); - return; - } -+ -+ neigh = neigh_lookup(&nd_tbl, &msg->target, dev); -+ - /* RFC 9131 updates original Neighbour Discovery RFC 4861. -- * An unsolicited NA can now create a neighbour cache entry -- * on routers if it has Target LL Address option. -+ * NAs with Target LL Address option without a corresponding -+ * entry in the neighbour cache can now create a STALE neighbour -+ * cache entry on routers. -+ * -+ * entry accept fwding solicited behaviour -+ * ------- ------ ------ --------- ---------------------- -+ * present X X 0 Set state to STALE -+ * present X X 1 Set state to REACHABLE -+ * absent 0 X X Do nothing -+ * absent 1 0 X Do nothing -+ * absent 1 1 X Add a new STALE entry - * -- * drop accept fwding behaviour -- * ---- ------ ------ ---------------------------------------------- -- * 1 X X Drop NA packet and don't pass up the stack -- * 0 0 X Pass NA packet up the stack, don't update NC -- * 0 1 0 Pass NA packet up the stack, don't update NC -- * 0 1 1 Pass NA packet up the stack, and add a STALE -- * NC entry - * Note that we don't do a (daddr == all-routers-mcast) check. - */ -- create_neigh = !msg->icmph.icmp6_solicited && lladdr && -- idev && idev->cnf.forwarding && -- idev->cnf.accept_unsolicited_na; -- neigh = __neigh_lookup(&nd_tbl, &msg->target, dev, create_neigh); -+ new_state = msg->icmph.icmp6_solicited ? NUD_REACHABLE : NUD_STALE; -+ if (!neigh && lladdr && -+ idev && idev->cnf.forwarding && -+ idev->cnf.accept_untracked_na) { -+ neigh = neigh_create(&nd_tbl, &msg->target, dev); -+ new_state = NUD_STALE; -+ } - -- if (neigh) { -+ if (neigh && !IS_ERR(neigh)) { - u8 old_flags = neigh->flags; - struct net *net = dev_net(dev); - -@@ -1064,7 +1072,7 @@ static void ndisc_recv_na(struct sk_buff *skb) - } - - ndisc_update(dev, neigh, lladdr, -- msg->icmph.icmp6_solicited ? NUD_REACHABLE : NUD_STALE, -+ new_state, - NEIGH_UPDATE_F_WEAK_OVERRIDE| - (msg->icmph.icmp6_override ? NEIGH_UPDATE_F_OVERRIDE : 0)| - NEIGH_UPDATE_F_OVERRIDE_ISROUTER| -diff --git a/tools/testing/selftests/net/ndisc_unsolicited_na_test.sh b/tools/testing/selftests/net/ndisc_unsolicited_na_test.sh -index f508657ee126..86e621b7b9c7 100755 ---- a/tools/testing/selftests/net/ndisc_unsolicited_na_test.sh -+++ b/tools/testing/selftests/net/ndisc_unsolicited_na_test.sh -@@ -1,15 +1,14 @@ - #!/bin/bash - # SPDX-License-Identifier: GPL-2.0 - --# This test is for the accept_unsolicited_na feature to -+# This test is for the accept_untracked_na feature to - # enable RFC9131 behaviour. The following is the test-matrix. - # drop accept fwding behaviour - # ---- ------ ------ ---------------------------------------------- --# 1 X X Drop NA packet and don't pass up the stack --# 0 0 X Pass NA packet up the stack, don't update NC --# 0 1 0 Pass NA packet up the stack, don't update NC --# 0 1 1 Pass NA packet up the stack, and add a STALE --# NC entry -+# 1 X X Don't update NC -+# 0 0 X Don't update NC -+# 0 1 0 Don't update NC -+# 0 1 1 Add a STALE NC entry - - ret=0 - # Kselftest framework requirement - SKIP code is 4. -@@ -72,7 +71,7 @@ setup() - set -e - - local drop_unsolicited_na=$1 -- local accept_unsolicited_na=$2 -+ local accept_untracked_na=$2 - local forwarding=$3 - - # Setup two namespaces and a veth tunnel across them. -@@ -93,7 +92,7 @@ setup() - ${IP_ROUTER_EXEC} sysctl -qw \ - ${ROUTER_CONF}.drop_unsolicited_na=${drop_unsolicited_na} - ${IP_ROUTER_EXEC} sysctl -qw \ -- ${ROUTER_CONF}.accept_unsolicited_na=${accept_unsolicited_na} -+ ${ROUTER_CONF}.accept_untracked_na=${accept_untracked_na} - ${IP_ROUTER_EXEC} sysctl -qw ${ROUTER_CONF}.disable_ipv6=0 - ${IP_ROUTER} addr add ${ROUTER_ADDR_WITH_MASK} dev ${ROUTER_INTF} - -@@ -144,13 +143,13 @@ link_up() { - - verify_ndisc() { - local drop_unsolicited_na=$1 -- local accept_unsolicited_na=$2 -+ local accept_untracked_na=$2 - local forwarding=$3 - - neigh_show_output=$(${IP_ROUTER} neigh show \ - to ${HOST_ADDR} dev ${ROUTER_INTF} nud stale) - if [ ${drop_unsolicited_na} -eq 0 ] && \ -- [ ${accept_unsolicited_na} -eq 1 ] && \ -+ [ ${accept_untracked_na} -eq 1 ] && \ - [ ${forwarding} -eq 1 ]; then - # Neighbour entry expected to be present for 011 case - [[ ${neigh_show_output} ]] -@@ -179,14 +178,14 @@ test_unsolicited_na_combination() { - test_unsolicited_na_common $1 $2 $3 - test_msg=("test_unsolicited_na: " - "drop_unsolicited_na=$1 " -- "accept_unsolicited_na=$2 " -+ "accept_untracked_na=$2 " - "forwarding=$3") - log_test $? 0 "${test_msg[*]}" - cleanup - } - - test_unsolicited_na_combinations() { -- # Args: drop_unsolicited_na accept_unsolicited_na forwarding -+ # Args: drop_unsolicited_na accept_untracked_na forwarding - - # Expect entry - test_unsolicited_na_combination 0 1 1 --- -2.25.1 - diff --git a/patch/0002-platform-mellanox-Change-reset_pwr_converter_fail-at.patch b/patch/0002-platform-mellanox-Change-reset_pwr_converter_fail-at.patch deleted file mode 100644 index a372a0aa9..000000000 --- a/patch/0002-platform-mellanox-Change-reset_pwr_converter_fail-at.patch +++ /dev/null @@ -1,38 +0,0 @@ -From c93a5081438b02b5ec4d3fd1fde8e6bf383a2996 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 8 Feb 2023 08:33:19 +0200 -Subject: [PATCH backport 6.1.42 02/85] platform: mellanox: Change - "reset_pwr_converter_fail" attribute - -Change "reset_voltmon_upgrade_fail" attribute name to -"reset_pwr_converter_fail". - -For systems using "mlxplat_mlxcpld_default_ng_regs_io_data", relevant -CPLD 'register.bit' indicates the failure of power converter, while on -older systems same 'register.bit' indicates failure of voltage monitor -devices upgrade failure. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych -Link: https://lore.kernel.org/r/20230208063331.15560-3-vadimp@nvidia.com -Signed-off-by: Hans de Goede ---- - drivers/platform/x86/mlx-platform.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 3e4adeb20a7e..c53eca49c47f 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -3186,7 +3186,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mode = 0444, - }, - { -- .label = "reset_voltmon_upgrade_fail", -+ .label = "reset_pwr_converter_fail", - .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(0), - .mode = 0444, --- -2.20.1 - diff --git a/patch/0003-platform-mellanox-Cosmetic-changes-rename-to-more-co.patch b/patch/0003-platform-mellanox-Cosmetic-changes-rename-to-more-co.patch deleted file mode 100644 index a965cb850..000000000 --- a/patch/0003-platform-mellanox-Cosmetic-changes-rename-to-more-co.patch +++ /dev/null @@ -1,117 +0,0 @@ -From db6f384dac123c41fce3169bc9961f304086e4cd Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 8 Feb 2023 08:33:20 +0200 -Subject: [PATCH backport 6.1.42 03/85] platform: mellanox: Cosmetic changes - - rename to more common name - -Rename 'nvlink_blade' in several declaration to more common name -"chassis_blade", since these names are going to be used for different -kinds of blades. - -Fix 'swicth' to 'switch' in comment. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych -Link: https://lore.kernel.org/r/20230208063331.15560-4-vadimp@nvidia.com -Signed-off-by: Hans de Goede ---- - drivers/platform/x86/mlx-platform.c | 28 ++++++++++++++-------------- - 1 file changed, 14 insertions(+), 14 deletions(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index c53eca49c47f..e629ec8a2a2f 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -473,7 +473,7 @@ static struct i2c_mux_reg_platform_data mlxplat_modular_mux_data[] = { - }, - }; - --/* Platform channels for rack swicth system family */ -+/* Platform channels for rack switch system family */ - static const int mlxplat_rack_switch_channels[] = { - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, - }; -@@ -2085,7 +2085,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_global_wp_items_data[] = { - }, - }; - --static struct mlxreg_core_item mlxplat_mlxcpld_nvlink_blade_items[] = { -+static struct mlxreg_core_item mlxplat_mlxcpld_chassis_blade_items[] = { - { - .data = mlxplat_mlxcpld_global_wp_items_data, - .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -@@ -2098,9 +2098,9 @@ static struct mlxreg_core_item mlxplat_mlxcpld_nvlink_blade_items[] = { - }; - - static --struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_nvlink_blade_data = { -- .items = mlxplat_mlxcpld_nvlink_blade_items, -- .counter = ARRAY_SIZE(mlxplat_mlxcpld_nvlink_blade_items), -+struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_chassis_blade_data = { -+ .items = mlxplat_mlxcpld_chassis_blade_items, -+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_items), - .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, - .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX, - .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, -@@ -3848,8 +3848,8 @@ static struct mlxreg_core_platform_data mlxplat_modular_regs_io_data = { - .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_regs_io_data), - }; - --/* Platform register access for NVLink blade systems family data */ --static struct mlxreg_core_data mlxplat_mlxcpld_nvlink_blade_regs_io_data[] = { -+/* Platform register access for chassis blade systems family data */ -+static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { - { - .label = "cpld1_version", - .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, -@@ -4046,9 +4046,9 @@ static struct mlxreg_core_data mlxplat_mlxcpld_nvlink_blade_regs_io_data[] = { - }, - }; - --static struct mlxreg_core_platform_data mlxplat_nvlink_blade_regs_io_data = { -- .data = mlxplat_mlxcpld_nvlink_blade_regs_io_data, -- .counter = ARRAY_SIZE(mlxplat_mlxcpld_nvlink_blade_regs_io_data), -+static struct mlxreg_core_platform_data mlxplat_chassis_blade_regs_io_data = { -+ .data = mlxplat_mlxcpld_chassis_blade_regs_io_data, -+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_regs_io_data), - }; - - /* Platform FAN default */ -@@ -5168,14 +5168,14 @@ static int __init mlxplat_dmi_modular_matched(const struct dmi_system_id *dmi) - return 1; - } - --static int __init mlxplat_dmi_nvlink_blade_matched(const struct dmi_system_id *dmi) -+static int __init mlxplat_dmi_chassis_blade_matched(const struct dmi_system_id *dmi) - { - int i; - - mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; - mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); - mlxplat_mux_data = mlxplat_default_mux_data; -- mlxplat_hotplug = &mlxplat_mlxcpld_nvlink_blade_data; -+ mlxplat_hotplug = &mlxplat_mlxcpld_chassis_blade_data; - mlxplat_hotplug->deferred_nr = - mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; - for (i = 0; i < mlxplat_mux_num; i++) { -@@ -5183,7 +5183,7 @@ static int __init mlxplat_dmi_nvlink_blade_matched(const struct dmi_system_id *d - mlxplat_mux_data[i].n_values = - ARRAY_SIZE(mlxplat_msn21xx_channels); - } -- mlxplat_regs_io = &mlxplat_nvlink_blade_regs_io_data; -+ mlxplat_regs_io = &mlxplat_chassis_blade_regs_io_data; - mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; - mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; - -@@ -5288,7 +5288,7 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { - }, - }, - { -- .callback = mlxplat_dmi_nvlink_blade_matched, -+ .callback = mlxplat_dmi_chassis_blade_matched, - .matches = { - DMI_MATCH(DMI_BOARD_NAME, "VMOD0015"), - }, --- -2.20.1 - diff --git a/patch/0004-platform-mellanox-Introduce-support-for-next-generat.patch b/patch/0004-platform-mellanox-Introduce-support-for-next-generat.patch deleted file mode 100644 index 7e94603d2..000000000 --- a/patch/0004-platform-mellanox-Introduce-support-for-next-generat.patch +++ /dev/null @@ -1,302 +0,0 @@ -From 20c7544580b2ec58139fb9ad84fee44052c75573 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 8 Feb 2023 08:33:21 +0200 -Subject: [PATCH backport 6.1.42 04/85] platform: mellanox: Introduce support - for next-generation 800GB/s switch - -Introduce support for Nvidia next-generation 800GB/s ethernet switch -SN5600. - -SN5600 is 51.2 Tbps Ethernet switch based on Nvidia Spectrum-4 ASIC. -It can provide up to 64x800Gb/s (ETH) full bidirectional bandwidth per -port using PAM-4 modulations. The system supports 64 Belly to Belly 2x4 -OSFP cages. -The switch was designed to fit standard 2U racks. - -Features: -- 64 OSFP ports support 800GbE - 10GbE speed. -- Additional 25GbE - 1GbE service port on the front panel. -- Air-cooled with 3 + 1 redundant fan units. -- 1 + 1 redundant 3000W or 3600W PSUs. -- System management board is based on Intel Coffee-lake CPU E-2276 - with secure-boot support. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych -Link: https://lore.kernel.org/r/20230208063331.15560-5-vadimp@nvidia.com -Signed-off-by: Hans de Goede ---- - drivers/platform/x86/mlx-platform.c | 180 ++++++++++++++++++++++++++++ - 1 file changed, 180 insertions(+) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index e629ec8a2a2f..cd7f6ff11b1e 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -253,6 +253,7 @@ - #define MLXPLAT_CPLD_CH3_ETH_MODULAR 43 - #define MLXPLAT_CPLD_CH4_ETH_MODULAR 51 - #define MLXPLAT_CPLD_CH2_RACK_SWITCH 18 -+#define MLXPLAT_CPLD_CH2_NG800 34 - - /* Number of LPC attached MUX platform devices */ - #define MLXPLAT_CPLD_LPC_MUX_DEVS 4 -@@ -503,6 +504,37 @@ static struct i2c_mux_reg_platform_data mlxplat_rack_switch_mux_data[] = { - - }; - -+/* Platform channels for ng800 system family */ -+static const int mlxplat_ng800_channels[] = { -+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, -+ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 -+}; -+ -+/* Platform ng800 mux data */ -+static struct i2c_mux_reg_platform_data mlxplat_ng800_mux_data[] = { -+ { -+ .parent = 1, -+ .base_nr = MLXPLAT_CPLD_CH1, -+ .write_only = 1, -+ .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, -+ .reg_size = 1, -+ .idle_in_use = 1, -+ .values = mlxplat_ng800_channels, -+ .n_values = ARRAY_SIZE(mlxplat_ng800_channels), -+ }, -+ { -+ .parent = 1, -+ .base_nr = MLXPLAT_CPLD_CH2_NG800, -+ .write_only = 1, -+ .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, -+ .reg_size = 1, -+ .idle_in_use = 1, -+ .values = mlxplat_msn21xx_channels, -+ .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), -+ }, -+ -+}; -+ - /* Platform hotplug devices */ - static struct i2c_board_info mlxplat_mlxcpld_pwr[] = { - { -@@ -522,6 +554,15 @@ static struct i2c_board_info mlxplat_mlxcpld_ext_pwr[] = { - }, - }; - -+static struct i2c_board_info mlxplat_mlxcpld_pwr_ng800[] = { -+ { -+ I2C_BOARD_INFO("dps460", 0x59), -+ }, -+ { -+ I2C_BOARD_INFO("dps460", 0x5a), -+ }, -+}; -+ - static struct i2c_board_info mlxplat_mlxcpld_fan[] = { - { - I2C_BOARD_INFO("24c32", 0x50), -@@ -601,6 +642,23 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_wc_items_data[] = { - }, - }; - -+static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_ng800_items_data[] = { -+ { -+ .label = "pwr1", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, -+ .mask = BIT(0), -+ .hpdev.brdinfo = &mlxplat_mlxcpld_pwr_ng800[0], -+ .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, -+ }, -+ { -+ .label = "pwr2", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, -+ .mask = BIT(1), -+ .hpdev.brdinfo = &mlxplat_mlxcpld_pwr_ng800[1], -+ .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, -+ }, -+}; -+ - static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = { - { - .label = "fan1", -@@ -1224,6 +1282,47 @@ static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = { - } - }; - -+static struct mlxreg_core_item mlxplat_mlxcpld_ng800_items[] = { -+ { -+ .data = mlxplat_mlxcpld_default_ng_psu_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, -+ .mask = MLXPLAT_CPLD_PSU_EXT_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data), -+ .inversed = 1, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_default_pwr_ng800_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, -+ .mask = MLXPLAT_CPLD_PWR_EXT_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_ng800_items_data), -+ .inversed = 0, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_default_ng_fan_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .mask = MLXPLAT_CPLD_FAN_NG_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), -+ .inversed = 1, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_default_asic_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, -+ .mask = MLXPLAT_CPLD_ASIC_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), -+ .inversed = 0, -+ .health = true, -+ }, -+}; -+ - static - struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { - .items = mlxplat_mlxcpld_ext_items, -@@ -1234,6 +1333,16 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { - .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, - }; - -+static -+struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_data = { -+ .items = mlxplat_mlxcpld_ng800_items, -+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_ng800_items), -+ .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, -+ .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, -+ .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, -+ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, -+}; -+ - static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = { - { - .label = "pwr1", -@@ -3093,6 +3202,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mask = GENMASK(7, 0) & ~BIT(7), - .mode = 0644, - }, -+ { -+ .label = "clk_brd_prog_en", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0644, -+ .secured = 1, -+ }, - { - .label = "erot1_recovery", - .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, -@@ -3221,6 +3337,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mask = GENMASK(7, 0) & ~BIT(6), - .mode = 0444, - }, -+ { -+ .label = "reset_ac_ok_fail", -+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), -+ .mode = 0444, -+ }, - { - .label = "psu1_on", - .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, -@@ -3302,6 +3424,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .bit = 5, - .mode = 0444, - }, -+ { -+ .label = "pwr_converter_prog_en", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0644, -+ .secured = 1, -+ }, - { - .label = "vpd_wp", - .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, -@@ -3326,6 +3455,30 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mask = GENMASK(7, 0) & ~BIT(1), - .mode = 0444, - }, -+ { -+ .label = "clk_brd1_boot_fail", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0444, -+ }, -+ { -+ .label = "clk_brd2_boot_fail", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0444, -+ }, -+ { -+ .label = "clk_brd_fail", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(6), -+ .mode = 0444, -+ }, -+ { -+ .label = "asic_pg_fail", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), -+ .mode = 0444, -+ }, - { - .label = "spi_chnl_select", - .reg = MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT, -@@ -5211,6 +5364,27 @@ static int __init mlxplat_dmi_rack_switch_matched(const struct dmi_system_id *dm - return 1; - } - -+static int __init mlxplat_dmi_ng800_matched(const struct dmi_system_id *dmi) -+{ -+ int i; -+ -+ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; -+ mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data); -+ mlxplat_mux_data = mlxplat_ng800_mux_data; -+ mlxplat_hotplug = &mlxplat_mlxcpld_ng800_data; -+ mlxplat_hotplug->deferred_nr = -+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; -+ mlxplat_led = &mlxplat_default_ng_led_data; -+ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; -+ mlxplat_fan = &mlxplat_default_fan_data; -+ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) -+ mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; -+ mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; -+ mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; -+ -+ return 1; -+} -+ - static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { - { - .callback = mlxplat_dmi_default_wc_matched, -@@ -5287,6 +5461,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { - DMI_MATCH(DMI_BOARD_NAME, "VMOD0011"), - }, - }, -+ { -+ .callback = mlxplat_dmi_ng800_matched, -+ .matches = { -+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0013"), -+ }, -+ }, - { - .callback = mlxplat_dmi_chassis_blade_matched, - .matches = { --- -2.20.1 - diff --git a/patch/0005-platform-mellanox-Introduce-support-of-new-Nvidia-L1.patch b/patch/0005-platform-mellanox-Introduce-support-of-new-Nvidia-L1.patch deleted file mode 100644 index 207e78011..000000000 --- a/patch/0005-platform-mellanox-Introduce-support-of-new-Nvidia-L1.patch +++ /dev/null @@ -1,640 +0,0 @@ -From 8f1fd1a859300ddf496de8876e8f3e7dcb54a3dc Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 8 Feb 2023 08:33:22 +0200 -Subject: [PATCH backport 6.1.42 05/85] platform: mellanox: Introduce support - of new Nvidia L1 switch - -Add support for new L1 switch nodes providing L1 connectivity for -multi-node networking chassis. - -The purpose is to provide compute server with full management and IO -subsystems with connections to L1 switches. - -System contains the following components: -- COMe module based on Intel Coffee Lake CPU -- Switch baseboard with two ASICs, while - 24 ports of each ASICs are connected to one backplane connector - 32 ports of each ASIC are connected to 8 OSFPs -- Integrated 60mm dual-rotor FANs inside L1 node (N+2 redundancy) -- Support 48V or 54V DC input from the external power server. - -Add the structures related to the new systems to allow proper activation -of the all required platform driver. - -Add poweroff callback to support deep power cycle flow, which should -include special actions against CPLD device for performing graceful -operation. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych -Link: https://lore.kernel.org/r/20230208063331.15560-6-vadimp@nvidia.com -Signed-off-by: Hans de Goede ---- - drivers/platform/x86/mlx-platform.c | 392 +++++++++++++++++++++++++++- - 1 file changed, 391 insertions(+), 1 deletion(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index cd7f6ff11b1e..1a07a9994f05 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -15,6 +15,7 @@ - #include - #include - #include -+#include - #include - - #define MLX_PLAT_DEVICE_NAME "mlxplat" -@@ -61,12 +62,19 @@ - #define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37 - #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a - #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b -+#define MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET 0x3c -+#define MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET 0x3d -+#define MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET 0x3e -+#define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET 0x3f - #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40 - #define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41 - #define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42 - #define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0x43 - #define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0x44 - #define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0x45 -+#define MLXPLAT_CPLD_LPC_REG_BRD_OFFSET 0x47 -+#define MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET 0x48 -+#define MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET 0x49 - #define MLXPLAT_CPLD_LPC_REG_GWP_OFFSET 0x4a - #define MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET 0x4b - #define MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET 0x4c -@@ -96,6 +104,9 @@ - #define MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET 0x94 - #define MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET 0x95 - #define MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET 0x96 -+#define MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET 0x97 -+#define MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET 0x98 -+#define MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET 0x99 - #define MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET 0x9a - #define MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET 0x9b - #define MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET 0x9c -@@ -127,6 +138,7 @@ - #define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0xd1 - #define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2 - #define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3 -+#define MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET 0xd9 - #define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0xde - #define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0xdf - #define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0xe0 -@@ -210,6 +222,7 @@ - MLXPLAT_CPLD_AGGR_MASK_LC_SDWN) - #define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1 - #define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2 BIT(2) -+#define MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT BIT(4) - #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6) - #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0) - #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0) -@@ -223,6 +236,16 @@ - #define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4) - #define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0) - #define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0) -+#define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0) -+#define MLXPLAT_CPLD_LATCH_RST_MASK BIT(5) -+#define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3) -+#define MLXPLAT_CPLD_THERMAL2_PDB_MASK BIT(4) -+#define MLXPLAT_CPLD_INTRUSION_MASK BIT(6) -+#define MLXPLAT_CPLD_PWM_PG_MASK BIT(7) -+#define MLXPLAT_CPLD_L1_CHA_HEALTH_MASK (MLXPLAT_CPLD_THERMAL1_PDB_MASK | \ -+ MLXPLAT_CPLD_THERMAL2_PDB_MASK | \ -+ MLXPLAT_CPLD_INTRUSION_MASK |\ -+ MLXPLAT_CPLD_PWM_PG_MASK) - #define MLXPLAT_CPLD_I2C_CAP_BIT 0x04 - #define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5, MLXPLAT_CPLD_I2C_CAP_BIT) - -@@ -235,6 +258,8 @@ - /* Masks for aggregation for modular systems */ - #define MLXPLAT_CPLD_LPC_LC_MASK GENMASK(7, 0) - -+#define MLXPLAT_CPLD_HALT_MASK BIT(3) -+ - /* Default I2C parent bus number */ - #define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1 - -@@ -315,6 +340,8 @@ struct mlxplat_priv { - void *regmap; - }; - -+static struct platform_device *mlxplat_dev; -+ - /* Regions for LPC I2C controller and LPC base register space */ - static const struct resource mlxplat_lpc_resources[] = { - [0] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_I2C_BASE_ADRR, -@@ -2307,6 +2334,156 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_rack_switch_data = { - .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, - }; - -+/* Callback performs graceful shutdown after notification about power button event */ -+static int -+mlxplat_mlxcpld_l1_switch_pwr_events_handler(void *handle, enum mlxreg_hotplug_kind kind, -+ u8 action) -+{ -+ dev_info(&mlxplat_dev->dev, "System shutdown due to short press of power button"); -+ kernel_halt(); -+ return 0; -+} -+ -+static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_pwr_events_notifier = { -+ .user_handler = mlxplat_mlxcpld_l1_switch_pwr_events_handler, -+}; -+ -+/* Platform hotplug for l1 switch systems family data */ -+static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_pwr_events_items_data[] = { -+ { -+ .label = "power_button", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, -+ .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_pwr_events_notifier, -+ }, -+}; -+ -+/* Callback activates latch reset flow after notification about intrusion event */ -+static int -+mlxplat_mlxcpld_l1_switch_intrusion_events_handler(void *handle, enum mlxreg_hotplug_kind kind, -+ u8 action) -+{ -+ struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); -+ u32 regval; -+ int err; -+ -+ err = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ®val); -+ if (err) -+ goto fail_regmap_read; -+ -+ if (action) { -+ dev_info(&mlxplat_dev->dev, "Detected intrusion - system latch is opened"); -+ err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, -+ regval | MLXPLAT_CPLD_LATCH_RST_MASK); -+ } else { -+ dev_info(&mlxplat_dev->dev, "System latch is properly closed"); -+ err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, -+ regval & ~MLXPLAT_CPLD_LATCH_RST_MASK); -+ } -+ -+ if (err) -+ goto fail_regmap_write; -+ -+ return 0; -+ -+fail_regmap_read: -+fail_regmap_write: -+ dev_err(&mlxplat_dev->dev, "Register access failed"); -+ return err; -+} -+ -+static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_intrusion_events_notifier = { -+ .user_handler = mlxplat_mlxcpld_l1_switch_intrusion_events_handler, -+}; -+ -+static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_health_events_items_data[] = { -+ { -+ .label = "thermal1_pdb", -+ .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, -+ .mask = MLXPLAT_CPLD_THERMAL1_PDB_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "thermal2_pdb", -+ .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, -+ .mask = MLXPLAT_CPLD_THERMAL2_PDB_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "intrusion", -+ .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, -+ .mask = MLXPLAT_CPLD_INTRUSION_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_intrusion_events_notifier, -+ }, -+ { -+ .label = "pwm_pg", -+ .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, -+ .mask = MLXPLAT_CPLD_PWM_PG_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+}; -+ -+static struct mlxreg_core_item mlxplat_mlxcpld_l1_switch_events_items[] = { -+ { -+ .data = mlxplat_mlxcpld_default_ng_fan_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .mask = MLXPLAT_CPLD_FAN_NG_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), -+ .inversed = 1, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_erot_ap_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, -+ .mask = MLXPLAT_CPLD_EROT_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_ap_items_data), -+ .inversed = 1, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_erot_error_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, -+ .mask = MLXPLAT_CPLD_EROT_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_error_items_data), -+ .inversed = 1, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_l1_switch_pwr_events_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, -+ .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_pwr_events_items_data), -+ .inversed = 0, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_l1_switch_health_events_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, -+ .mask = MLXPLAT_CPLD_L1_CHA_HEALTH_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_health_events_items_data), -+ .inversed = 0, -+ .health = false, -+ .ind = 8, -+ }, -+}; -+ -+static -+struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_l1_switch_data = { -+ .items = mlxplat_mlxcpld_l1_switch_events_items, -+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_events_items), -+ .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, -+ .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, -+ .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, -+ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT, -+}; -+ - /* Platform led default data */ - static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { - { -@@ -2836,6 +3013,114 @@ static struct mlxreg_core_platform_data mlxplat_modular_led_data = { - .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_led_data), - }; - -+/* Platform led data for chassis system */ -+static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_led_data[] = { -+ { -+ .label = "status:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ }, -+ { -+ .label = "status:orange", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK -+ }, -+ { -+ .label = "fan1:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(0), -+ }, -+ { -+ .label = "fan1:orange", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(0), -+ }, -+ { -+ .label = "fan2:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(1), -+ }, -+ { -+ .label = "fan2:orange", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(1), -+ }, -+ { -+ .label = "fan3:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(2), -+ }, -+ { -+ .label = "fan3:orange", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(2), -+ }, -+ { -+ .label = "fan4:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(3), -+ }, -+ { -+ .label = "fan4:orange", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(3), -+ }, -+ { -+ .label = "fan5:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(4), -+ }, -+ { -+ .label = "fan5:orange", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(4), -+ }, -+ { -+ .label = "fan6:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(5), -+ }, -+ { -+ .label = "fan6:orange", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(5), -+ }, -+ { -+ .label = "uid:blue", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ }, -+}; -+ -+static struct mlxreg_core_platform_data mlxplat_l1_switch_led_data = { -+ .data = mlxplat_mlxcpld_l1_switch_led_data, -+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_led_data), -+}; -+ - /* Platform register access default */ - static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = { - { -@@ -3367,12 +3652,48 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mask = GENMASK(7, 0) & ~BIT(3), - .mode = 0200, - }, -+ { -+ .label = "deep_pwr_cycle", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0200, -+ }, -+ { -+ .label = "latch_reset", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0200, -+ }, - { - .label = "jtag_enable", - .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(4), - .mode = 0644, - }, -+ { -+ .label = "dbg1", -+ .reg = MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0644, -+ }, -+ { -+ .label = "dbg2", -+ .reg = MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0644, -+ }, -+ { -+ .label = "dbg3", -+ .reg = MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0644, -+ }, -+ { -+ .label = "dbg4", -+ .reg = MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0644, -+ }, - { - .label = "asic_health", - .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, -@@ -4586,11 +4907,18 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: - case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: -@@ -4605,6 +4933,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: -@@ -4633,6 +4963,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: -@@ -4683,6 +5014,10 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: -@@ -4692,6 +5027,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: -@@ -4713,6 +5051,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET: - case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET: -@@ -4749,6 +5090,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: -@@ -4825,6 +5167,10 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: -@@ -4834,6 +5180,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: -@@ -4855,6 +5204,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET: - case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET: -@@ -4885,6 +5237,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: -@@ -5080,7 +5433,6 @@ static struct resource mlxplat_mlxcpld_resources[] = { - [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug"), - }; - --static struct platform_device *mlxplat_dev; - static struct mlxreg_core_hotplug_platform_data *mlxplat_i2c; - static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug; - static struct mlxreg_core_platform_data *mlxplat_led; -@@ -5090,6 +5442,14 @@ static struct mlxreg_core_platform_data - *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS]; - static const struct regmap_config *mlxplat_regmap_config; - -+/* Platform default poweroff function */ -+static void mlxplat_poweroff(void) -+{ -+ struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); -+ -+ regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, MLXPLAT_CPLD_HALT_MASK); -+} -+ - static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi) - { - int i; -@@ -5385,6 +5745,28 @@ static int __init mlxplat_dmi_ng800_matched(const struct dmi_system_id *dmi) - return 1; - } - -+static int __init mlxplat_dmi_l1_switch_matched(const struct dmi_system_id *dmi) -+{ -+ int i; -+ -+ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; -+ mlxplat_mux_num = ARRAY_SIZE(mlxplat_rack_switch_mux_data); -+ mlxplat_mux_data = mlxplat_rack_switch_mux_data; -+ mlxplat_hotplug = &mlxplat_mlxcpld_l1_switch_data; -+ mlxplat_hotplug->deferred_nr = -+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; -+ mlxplat_led = &mlxplat_l1_switch_led_data; -+ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; -+ mlxplat_fan = &mlxplat_default_fan_data; -+ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) -+ mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; -+ mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; -+ mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_rack_switch; -+ pm_power_off = mlxplat_poweroff; -+ -+ return 1; -+} -+ - static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { - { - .callback = mlxplat_dmi_default_wc_matched, -@@ -5473,6 +5855,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { - DMI_MATCH(DMI_BOARD_NAME, "VMOD0015"), - }, - }, -+ { -+ .callback = mlxplat_dmi_l1_switch_matched, -+ .matches = { -+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0017"), -+ }, -+ }, - { - .callback = mlxplat_dmi_msn274x_matched, - .matches = { -@@ -5802,6 +6190,8 @@ static void __exit mlxplat_exit(void) - struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); - int i; - -+ if (pm_power_off) -+ pm_power_off = NULL; - for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--) - platform_device_unregister(priv->pdev_wd[i]); - if (priv->pdev_fan) --- -2.20.1 - diff --git a/patch/0006-platform-mellanox-Split-initialization-procedure.patch b/patch/0006-platform-mellanox-Split-initialization-procedure.patch deleted file mode 100644 index d4c1855d1..000000000 --- a/patch/0006-platform-mellanox-Split-initialization-procedure.patch +++ /dev/null @@ -1,171 +0,0 @@ -From 1ed767e22aef60dc8b2d1ec472438ce734e61a56 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 8 Feb 2023 08:33:23 +0200 -Subject: [PATCH backport 6.1.42 06/85] platform: mellanox: Split - initialization procedure - -Split mlxplat_init() into two by adding mlxplat_pre_init(). - -Motivation is to prepare 'mlx-platform' driver to support systems -equipped PCIe based programming logic device. - -Such systems are supposed to use different system resources, thus this -commit separates resources allocation related code. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych -Link: https://lore.kernel.org/r/20230208063331.15560-7-vadimp@nvidia.com -Signed-off-by: Hans de Goede ---- - drivers/platform/x86/mlx-platform.c | 78 ++++++++++++++++++++++------- - 1 file changed, 60 insertions(+), 18 deletions(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 1a07a9994f05..2d33d1e5d427 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -328,6 +328,8 @@ - * @pdev_fan - FAN platform devices - * @pdev_wd - array of watchdog platform devices - * @regmap: device register map -+ * @hotplug_resources: system hotplug resources -+ * @hotplug_resources_size: size of system hotplug resources - */ - struct mlxplat_priv { - struct platform_device *pdev_i2c; -@@ -338,6 +340,8 @@ struct mlxplat_priv { - struct platform_device *pdev_fan; - struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS]; - void *regmap; -+ struct resource *hotplug_resources; -+ unsigned int hotplug_resources_size; - }; - - static struct platform_device *mlxplat_dev; -@@ -6002,20 +6006,63 @@ static int mlxplat_mlxcpld_check_wd_capability(void *regmap) - return 0; - } - -+static int mlxplat_lpc_cpld_device_init(struct resource **hotplug_resources, -+ unsigned int *hotplug_resources_size) -+{ -+ int err; -+ -+ mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, PLATFORM_DEVID_NONE, -+ mlxplat_lpc_resources, -+ ARRAY_SIZE(mlxplat_lpc_resources)); -+ if (IS_ERR(mlxplat_dev)) -+ return PTR_ERR(mlxplat_dev); -+ -+ mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev, -+ mlxplat_lpc_resources[1].start, 1); -+ if (!mlxplat_mlxcpld_regmap_ctx.base) { -+ err = -ENOMEM; -+ goto fail_devm_ioport_map; -+ } -+ -+ *hotplug_resources = mlxplat_mlxcpld_resources; -+ *hotplug_resources_size = ARRAY_SIZE(mlxplat_mlxcpld_resources); -+ -+ return 0; -+ -+fail_devm_ioport_map: -+ platform_device_unregister(mlxplat_dev); -+ return err; -+} -+ -+static void mlxplat_lpc_cpld_device_exit(void) -+{ -+ platform_device_unregister(mlxplat_dev); -+} -+ -+static int -+mlxplat_pre_init(struct resource **hotplug_resources, unsigned int *hotplug_resources_size) -+{ -+ return mlxplat_lpc_cpld_device_init(hotplug_resources, hotplug_resources_size); -+} -+ -+static void mlxplat_post_exit(void) -+{ -+ mlxplat_lpc_cpld_device_exit(); -+} -+ - static int __init mlxplat_init(void) - { -+ unsigned int hotplug_resources_size; -+ struct resource *hotplug_resources; - struct mlxplat_priv *priv; - int i, j, nr, err; - - if (!dmi_check_system(mlxplat_dmi_table)) - return -ENODEV; - -- mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, PLATFORM_DEVID_NONE, -- mlxplat_lpc_resources, -- ARRAY_SIZE(mlxplat_lpc_resources)); -- -- if (IS_ERR(mlxplat_dev)) -- return PTR_ERR(mlxplat_dev); -+ err = mlxplat_pre_init(&hotplug_resources, &hotplug_resources_size); -+ if (err) -+ return err; - - priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv), - GFP_KERNEL); -@@ -6025,12 +6072,8 @@ static int __init mlxplat_init(void) - } - platform_set_drvdata(mlxplat_dev, priv); - -- mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev, -- mlxplat_lpc_resources[1].start, 1); -- if (!mlxplat_mlxcpld_regmap_ctx.base) { -- err = -ENOMEM; -- goto fail_alloc; -- } -+ priv->hotplug_resources = hotplug_resources; -+ priv->hotplug_resources_size = hotplug_resources_size; - - if (!mlxplat_regmap_config) - mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config; -@@ -6051,8 +6094,8 @@ static int __init mlxplat_init(void) - if (mlxplat_i2c) - mlxplat_i2c->regmap = priv->regmap; - priv->pdev_i2c = platform_device_register_resndata(&mlxplat_dev->dev, "i2c_mlxcpld", -- nr, mlxplat_mlxcpld_resources, -- ARRAY_SIZE(mlxplat_mlxcpld_resources), -+ nr, priv->hotplug_resources, -+ priv->hotplug_resources_size, - mlxplat_i2c, sizeof(*mlxplat_i2c)); - if (IS_ERR(priv->pdev_i2c)) { - err = PTR_ERR(priv->pdev_i2c); -@@ -6076,8 +6119,8 @@ static int __init mlxplat_init(void) - priv->pdev_hotplug = - platform_device_register_resndata(&mlxplat_dev->dev, - "mlxreg-hotplug", PLATFORM_DEVID_NONE, -- mlxplat_mlxcpld_resources, -- ARRAY_SIZE(mlxplat_mlxcpld_resources), -+ priv->hotplug_resources, -+ priv->hotplug_resources_size, - mlxplat_hotplug, sizeof(*mlxplat_hotplug)); - if (IS_ERR(priv->pdev_hotplug)) { - err = PTR_ERR(priv->pdev_hotplug); -@@ -6179,7 +6222,6 @@ static int __init mlxplat_init(void) - platform_device_unregister(priv->pdev_mux[i]); - platform_device_unregister(priv->pdev_i2c); - fail_alloc: -- platform_device_unregister(mlxplat_dev); - - return err; - } -@@ -6207,7 +6249,7 @@ static void __exit mlxplat_exit(void) - platform_device_unregister(priv->pdev_mux[i]); - - platform_device_unregister(priv->pdev_i2c); -- platform_device_unregister(mlxplat_dev); -+ mlxplat_post_exit(); - } - module_exit(mlxplat_exit); - --- -2.20.1 - diff --git a/patch/0007-platform-mellanox-Split-logic-in-init-and-exit-flow.patch b/patch/0007-platform-mellanox-Split-logic-in-init-and-exit-flow.patch deleted file mode 100644 index 825a3a6e0..000000000 --- a/patch/0007-platform-mellanox-Split-logic-in-init-and-exit-flow.patch +++ /dev/null @@ -1,458 +0,0 @@ -From c182cf6f64708b3531f38c10e43b5e8333071e19 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 8 Feb 2023 08:33:24 +0200 -Subject: [PATCH backport 6.1.42 07/85] platform: mellanox: Split logic in init - and exit flow - -Split logic in mlxplat_init()/mlxplat_exit() routines. -Separate initialization of I2C infrastructure and others platform -drivers. - -Motivation is to provide synchronization between I2C bus and mux -drivers and other drivers using this infrastructure. -I2C main bus and MUX busses are implemented in FPGA logic. On some new -systems the numbers allocated for these busses could be variable -depending on order of initialization of I2C native busses. Since bus -numbers are passed to some other platform drivers during initialization -flow, it is necessary to synchronize completion of I2C infrastructure -drivers and activation of rest of drivers. - -Thus initialization flow will be performed in synchronized order. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych -Link: https://lore.kernel.org/r/20230208063331.15560-8-vadimp@nvidia.com -Signed-off-by: Hans de Goede ---- - drivers/platform/x86/mlx-platform.c | 313 ++++++++++++++++++---------- - 1 file changed, 204 insertions(+), 109 deletions(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 2d33d1e5d427..bd94d82ecce5 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -319,6 +319,9 @@ - /* Default value for PWM control register for rack switch system */ - #define MLXPLAT_REGMAP_NVSWITCH_PWM_DEFAULT 0xf4 - -+#define MLXPLAT_I2C_MAIN_BUS_NOTIFIED 0x01 -+#define MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED 0x02 -+ - /* mlxplat_priv - platform private data - * @pdev_i2c - i2c controller platform device - * @pdev_mux - array of mux platform devices -@@ -330,6 +333,7 @@ - * @regmap: device register map - * @hotplug_resources: system hotplug resources - * @hotplug_resources_size: size of system hotplug resources -+ * @hi2c_main_init_status: init status of I2C main bus - */ - struct mlxplat_priv { - struct platform_device *pdev_i2c; -@@ -342,9 +346,11 @@ struct mlxplat_priv { - void *regmap; - struct resource *hotplug_resources; - unsigned int hotplug_resources_size; -+ u8 i2c_main_init_status; - }; - - static struct platform_device *mlxplat_dev; -+static int mlxplat_i2c_main_complition_notify(void *handle, int id); - - /* Regions for LPC I2C controller and LPC base register space */ - static const struct resource mlxplat_lpc_resources[] = { -@@ -379,6 +385,7 @@ static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_ng_data = { - .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX, - .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET, - .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_I2C, -+ .completion_notify = mlxplat_i2c_main_complition_notify, - }; - - /* Platform default channels */ -@@ -6050,68 +6057,9 @@ static void mlxplat_post_exit(void) - mlxplat_lpc_cpld_device_exit(); - } - --static int __init mlxplat_init(void) -+static int mlxplat_post_init(struct mlxplat_priv *priv) - { -- unsigned int hotplug_resources_size; -- struct resource *hotplug_resources; -- struct mlxplat_priv *priv; -- int i, j, nr, err; -- -- if (!dmi_check_system(mlxplat_dmi_table)) -- return -ENODEV; -- -- err = mlxplat_pre_init(&hotplug_resources, &hotplug_resources_size); -- if (err) -- return err; -- -- priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv), -- GFP_KERNEL); -- if (!priv) { -- err = -ENOMEM; -- goto fail_alloc; -- } -- platform_set_drvdata(mlxplat_dev, priv); -- -- priv->hotplug_resources = hotplug_resources; -- priv->hotplug_resources_size = hotplug_resources_size; -- -- if (!mlxplat_regmap_config) -- mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config; -- -- priv->regmap = devm_regmap_init(&mlxplat_dev->dev, NULL, -- &mlxplat_mlxcpld_regmap_ctx, -- mlxplat_regmap_config); -- if (IS_ERR(priv->regmap)) { -- err = PTR_ERR(priv->regmap); -- goto fail_alloc; -- } -- -- err = mlxplat_mlxcpld_verify_bus_topology(&nr); -- if (nr < 0) -- goto fail_alloc; -- -- nr = (nr == mlxplat_max_adap_num) ? -1 : nr; -- if (mlxplat_i2c) -- mlxplat_i2c->regmap = priv->regmap; -- priv->pdev_i2c = platform_device_register_resndata(&mlxplat_dev->dev, "i2c_mlxcpld", -- nr, priv->hotplug_resources, -- priv->hotplug_resources_size, -- mlxplat_i2c, sizeof(*mlxplat_i2c)); -- if (IS_ERR(priv->pdev_i2c)) { -- err = PTR_ERR(priv->pdev_i2c); -- goto fail_alloc; -- } -- -- for (i = 0; i < mlxplat_mux_num; i++) { -- priv->pdev_mux[i] = platform_device_register_resndata(&priv->pdev_i2c->dev, -- "i2c-mux-reg", i, NULL, 0, -- &mlxplat_mux_data[i], -- sizeof(mlxplat_mux_data[i])); -- if (IS_ERR(priv->pdev_mux[i])) { -- err = PTR_ERR(priv->pdev_mux[i]); -- goto fail_platform_mux_register; -- } -- } -+ int i = 0, err; - - /* Add hotplug driver */ - if (mlxplat_hotplug) { -@@ -6124,19 +6072,10 @@ static int __init mlxplat_init(void) - mlxplat_hotplug, sizeof(*mlxplat_hotplug)); - if (IS_ERR(priv->pdev_hotplug)) { - err = PTR_ERR(priv->pdev_hotplug); -- goto fail_platform_mux_register; -+ goto fail_platform_hotplug_register; - } - } - -- /* Set default registers. */ -- for (j = 0; j < mlxplat_regmap_config->num_reg_defaults; j++) { -- err = regmap_write(priv->regmap, -- mlxplat_regmap_config->reg_defaults[j].reg, -- mlxplat_regmap_config->reg_defaults[j].def); -- if (err) -- goto fail_platform_mux_register; -- } -- - /* Add LED driver. */ - if (mlxplat_led) { - mlxplat_led->regmap = priv->regmap; -@@ -6146,7 +6085,7 @@ static int __init mlxplat_init(void) - sizeof(*mlxplat_led)); - if (IS_ERR(priv->pdev_led)) { - err = PTR_ERR(priv->pdev_led); -- goto fail_platform_hotplug_register; -+ goto fail_platform_leds_register; - } - } - -@@ -6160,7 +6099,7 @@ static int __init mlxplat_init(void) - sizeof(*mlxplat_regs_io)); - if (IS_ERR(priv->pdev_io_regs)) { - err = PTR_ERR(priv->pdev_io_regs); -- goto fail_platform_led_register; -+ goto fail_platform_io_register; - } - } - -@@ -6173,7 +6112,7 @@ static int __init mlxplat_init(void) - sizeof(*mlxplat_fan)); - if (IS_ERR(priv->pdev_fan)) { - err = PTR_ERR(priv->pdev_fan); -- goto fail_platform_io_regs_register; -+ goto fail_platform_fan_register; - } - } - -@@ -6181,59 +6120,42 @@ static int __init mlxplat_init(void) - err = mlxplat_mlxcpld_check_wd_capability(priv->regmap); - if (err) - goto fail_platform_wd_register; -- for (j = 0; j < MLXPLAT_CPLD_WD_MAX_DEVS; j++) { -- if (mlxplat_wd_data[j]) { -- mlxplat_wd_data[j]->regmap = priv->regmap; -- priv->pdev_wd[j] = -- platform_device_register_resndata(&mlxplat_dev->dev, "mlx-wdt", j, -- NULL, 0, mlxplat_wd_data[j], -- sizeof(*mlxplat_wd_data[j])); -- if (IS_ERR(priv->pdev_wd[j])) { -- err = PTR_ERR(priv->pdev_wd[j]); -+ for (i = 0; i < MLXPLAT_CPLD_WD_MAX_DEVS; i++) { -+ if (mlxplat_wd_data[i]) { -+ mlxplat_wd_data[i]->regmap = priv->regmap; -+ priv->pdev_wd[i] = -+ platform_device_register_resndata(&mlxplat_dev->dev, "mlx-wdt", i, -+ NULL, 0, mlxplat_wd_data[i], -+ sizeof(*mlxplat_wd_data[i])); -+ if (IS_ERR(priv->pdev_wd[i])) { -+ err = PTR_ERR(priv->pdev_wd[i]); - goto fail_platform_wd_register; - } - } - } - -- /* Sync registers with hardware. */ -- regcache_mark_dirty(priv->regmap); -- err = regcache_sync(priv->regmap); -- if (err) -- goto fail_platform_wd_register; -- - return 0; - - fail_platform_wd_register: -- while (--j >= 0) -- platform_device_unregister(priv->pdev_wd[j]); -- if (mlxplat_fan) -- platform_device_unregister(priv->pdev_fan); --fail_platform_io_regs_register: -+ while (--i >= 0) -+ platform_device_unregister(priv->pdev_wd[i]); -+fail_platform_fan_register: - if (mlxplat_regs_io) - platform_device_unregister(priv->pdev_io_regs); --fail_platform_led_register: -+fail_platform_io_register: - if (mlxplat_led) - platform_device_unregister(priv->pdev_led); --fail_platform_hotplug_register: -+fail_platform_leds_register: - if (mlxplat_hotplug) - platform_device_unregister(priv->pdev_hotplug); --fail_platform_mux_register: -- while (--i >= 0) -- platform_device_unregister(priv->pdev_mux[i]); -- platform_device_unregister(priv->pdev_i2c); --fail_alloc: -- -+fail_platform_hotplug_register: - return err; - } --module_init(mlxplat_init); - --static void __exit mlxplat_exit(void) -+static void mlxplat_pre_exit(struct mlxplat_priv *priv) - { -- struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); - int i; - -- if (pm_power_off) -- pm_power_off = NULL; - for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--) - platform_device_unregister(priv->pdev_wd[i]); - if (priv->pdev_fan) -@@ -6244,13 +6166,186 @@ static void __exit mlxplat_exit(void) - platform_device_unregister(priv->pdev_led); - if (priv->pdev_hotplug) - platform_device_unregister(priv->pdev_hotplug); -+} -+ -+static int -+mlxplat_i2c_mux_complition_notify(void *handle, struct i2c_adapter *parent, -+ struct i2c_adapter *adapters[]) -+{ -+ struct mlxplat_priv *priv = handle; -+ -+ return mlxplat_post_init(priv); -+} - -- for (i = mlxplat_mux_num - 1; i >= 0 ; i--) -+static int mlxplat_i2c_mux_topolgy_init(struct mlxplat_priv *priv) -+{ -+ int i, err; -+ -+ if (!priv->pdev_i2c) { -+ priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_NOTIFIED; -+ return 0; -+ } -+ -+ priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED; -+ for (i = 0; i < mlxplat_mux_num; i++) { -+ priv->pdev_mux[i] = platform_device_register_resndata(&priv->pdev_i2c->dev, -+ "i2c-mux-reg", i, NULL, 0, -+ &mlxplat_mux_data[i], -+ sizeof(mlxplat_mux_data[i])); -+ if (IS_ERR(priv->pdev_mux[i])) { -+ err = PTR_ERR(priv->pdev_mux[i]); -+ goto fail_platform_mux_register; -+ } -+ } -+ -+ return mlxplat_i2c_mux_complition_notify(priv, NULL, NULL); -+ -+fail_platform_mux_register: -+ while (--i >= 0) - platform_device_unregister(priv->pdev_mux[i]); -+ return err; -+} -+ -+static void mlxplat_i2c_mux_topolgy_exit(struct mlxplat_priv *priv) -+{ -+ int i; -+ -+ for (i = mlxplat_mux_num - 1; i >= 0 ; i--) { -+ if (priv->pdev_mux[i]) -+ platform_device_unregister(priv->pdev_mux[i]); -+ } - -- platform_device_unregister(priv->pdev_i2c); - mlxplat_post_exit(); - } -+ -+static int mlxplat_i2c_main_complition_notify(void *handle, int id) -+{ -+ struct mlxplat_priv *priv = handle; -+ -+ return mlxplat_i2c_mux_topolgy_init(priv); -+} -+ -+static int mlxplat_i2c_main_init(struct mlxplat_priv *priv) -+{ -+ int nr, err; -+ -+ if (!mlxplat_i2c) -+ return 0; -+ -+ err = mlxplat_mlxcpld_verify_bus_topology(&nr); -+ if (nr < 0) -+ goto fail_mlxplat_mlxcpld_verify_bus_topology; -+ -+ nr = (nr == mlxplat_max_adap_num) ? -1 : nr; -+ mlxplat_i2c->regmap = priv->regmap; -+ mlxplat_i2c->handle = priv; -+ -+ priv->pdev_i2c = platform_device_register_resndata(&mlxplat_dev->dev, "i2c_mlxcpld", -+ nr, priv->hotplug_resources, -+ priv->hotplug_resources_size, -+ mlxplat_i2c, sizeof(*mlxplat_i2c)); -+ if (IS_ERR(priv->pdev_i2c)) { -+ err = PTR_ERR(priv->pdev_i2c); -+ goto fail_platform_i2c_register; -+ } -+ -+ if (priv->i2c_main_init_status == MLXPLAT_I2C_MAIN_BUS_NOTIFIED) { -+ err = mlxplat_i2c_mux_topolgy_init(priv); -+ if (err) -+ goto fail_mlxplat_i2c_mux_topolgy_init; -+ } -+ -+ return 0; -+ -+fail_mlxplat_i2c_mux_topolgy_init: -+fail_platform_i2c_register: -+fail_mlxplat_mlxcpld_verify_bus_topology: -+ return err; -+} -+ -+static void mlxplat_i2c_main_exit(struct mlxplat_priv *priv) -+{ -+ mlxplat_i2c_mux_topolgy_exit(priv); -+ if (priv->pdev_i2c) -+ platform_device_unregister(priv->pdev_i2c); -+} -+ -+static int __init mlxplat_init(void) -+{ -+ unsigned int hotplug_resources_size; -+ struct resource *hotplug_resources; -+ struct mlxplat_priv *priv; -+ int i, err; -+ -+ if (!dmi_check_system(mlxplat_dmi_table)) -+ return -ENODEV; -+ -+ err = mlxplat_pre_init(&hotplug_resources, &hotplug_resources_size); -+ if (err) -+ return err; -+ -+ priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv), -+ GFP_KERNEL); -+ if (!priv) { -+ err = -ENOMEM; -+ goto fail_alloc; -+ } -+ platform_set_drvdata(mlxplat_dev, priv); -+ priv->hotplug_resources = hotplug_resources; -+ priv->hotplug_resources_size = hotplug_resources_size; -+ -+ if (!mlxplat_regmap_config) -+ mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config; -+ -+ priv->regmap = devm_regmap_init(&mlxplat_dev->dev, NULL, -+ &mlxplat_mlxcpld_regmap_ctx, -+ mlxplat_regmap_config); -+ if (IS_ERR(priv->regmap)) { -+ err = PTR_ERR(priv->regmap); -+ goto fail_alloc; -+ } -+ -+ /* Set default registers. */ -+ for (i = 0; i < mlxplat_regmap_config->num_reg_defaults; i++) { -+ err = regmap_write(priv->regmap, -+ mlxplat_regmap_config->reg_defaults[i].reg, -+ mlxplat_regmap_config->reg_defaults[i].def); -+ if (err) -+ goto fail_regmap_write; -+ } -+ -+ err = mlxplat_i2c_main_init(priv); -+ if (err) -+ goto fail_mlxplat_i2c_main_init; -+ -+ /* Sync registers with hardware. */ -+ regcache_mark_dirty(priv->regmap); -+ err = regcache_sync(priv->regmap); -+ if (err) -+ goto fail_regcache_sync; -+ -+ return 0; -+ -+fail_regcache_sync: -+ mlxplat_pre_exit(priv); -+fail_mlxplat_i2c_main_init: -+fail_regmap_write: -+fail_alloc: -+ mlxplat_post_exit(); -+ -+ return err; -+} -+module_init(mlxplat_init); -+ -+static void __exit mlxplat_exit(void) -+{ -+ struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); -+ -+ if (pm_power_off) -+ pm_power_off = NULL; -+ mlxplat_pre_exit(priv); -+ mlxplat_i2c_main_exit(priv); -+} - module_exit(mlxplat_exit); - - MODULE_AUTHOR("Vadim Pasternak (vadimp@mellanox.com)"); --- -2.20.1 - diff --git a/patch/0008-platform-mellanox-Extend-all-systems-with-I2C-notifi.patch b/patch/0008-platform-mellanox-Extend-all-systems-with-I2C-notifi.patch deleted file mode 100644 index a2d87c031..000000000 --- a/patch/0008-platform-mellanox-Extend-all-systems-with-I2C-notifi.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 9c901b497e90f874d903f9cbbe8d6076e8c9956a Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 8 Feb 2023 08:33:25 +0200 -Subject: [PATCH backport 6.1.42 08/85] platform: mellanox: Extend all systems - with I2C notification callback - -Motivation is to provide synchronization between I2C main bus and other -platform drivers using this notification callback. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych -Link: https://lore.kernel.org/r/20230208063331.15560-9-vadimp@nvidia.com -Signed-off-by: Hans de Goede ---- - drivers/platform/x86/mlx-platform.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index bd94d82ecce5..e541046c9100 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -363,6 +363,11 @@ static const struct resource mlxplat_lpc_resources[] = { - IORESOURCE_IO), - }; - -+/* Platform systems default i2c data */ -+static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_default_data = { -+ .completion_notify = mlxplat_i2c_main_complition_notify, -+}; -+ - /* Platform i2c next generation systems data */ - static struct mlxreg_core_data mlxplat_mlxcpld_i2c_ng_items_data[] = { - { -@@ -5479,6 +5484,7 @@ static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi) - mlxplat_led = &mlxplat_default_led_data; - mlxplat_regs_io = &mlxplat_default_regs_io_data; - mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; -+ mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; - - return 1; - } -@@ -5501,6 +5507,7 @@ static int __init mlxplat_dmi_default_wc_matched(const struct dmi_system_id *dmi - mlxplat_led = &mlxplat_default_led_wc_data; - mlxplat_regs_io = &mlxplat_default_regs_io_data; - mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; -+ mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; - - return 1; - } -@@ -5548,6 +5555,7 @@ static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi) - mlxplat_led = &mlxplat_msn21xx_led_data; - mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; - mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; -+ mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; - - return 1; - } -@@ -5570,6 +5578,7 @@ static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi) - mlxplat_led = &mlxplat_default_led_data; - mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; - mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; -+ mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; - - return 1; - } -@@ -5592,6 +5601,7 @@ static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi) - mlxplat_led = &mlxplat_msn21xx_led_data; - mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; - mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; -+ mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; - - return 1; - } -@@ -5641,6 +5651,7 @@ static int __init mlxplat_dmi_comex_matched(const struct dmi_system_id *dmi) - mlxplat_fan = &mlxplat_default_fan_data; - for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) - mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; -+ mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; - mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_comex; - - return 1; --- -2.20.1 - diff --git a/patch/0009-platform-mellanox-mlx-platform-Add-mux-selection-reg.patch b/patch/0009-platform-mellanox-mlx-platform-Add-mux-selection-reg.patch deleted file mode 100644 index 27a182d0f..000000000 --- a/patch/0009-platform-mellanox-mlx-platform-Add-mux-selection-reg.patch +++ /dev/null @@ -1,102 +0,0 @@ -From e3494fcd4510b98a5fd816dde3fd773f7f34b340 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 8 Feb 2023 08:33:28 +0200 -Subject: [PATCH backport 6.1.42 09/85] platform: mellanox: mlx-platform: Add - mux selection register to regmap -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Extend writeable, readable, volatile registers of the 'regmap' object -with for I2C mux selector registers. - -The motivation is to pass this object extended with selector registers -to I2C mux driver working over ‘regmap’. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych -Link: https://lore.kernel.org/r/20230208063331.15560-12-vadimp@nvidia.com -Signed-off-by: Hans de Goede ---- - drivers/platform/x86/mlx-platform.c | 28 ++++++++++++++++++++-------- - 1 file changed, 20 insertions(+), 8 deletions(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index e541046c9100..60062d9f3b9b 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -139,6 +139,10 @@ - #define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2 - #define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3 - #define MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET 0xd9 -+#define MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET 0xdb -+#define MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET 0xda -+#define MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET 0xdc -+#define MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET 0xdd - #define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0xde - #define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0xdf - #define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0xe0 -@@ -172,23 +176,19 @@ - #define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc - #define MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET 0xfd - #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100 --#define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb --#define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda --#define MLXPLAT_CPLD_LPC_I2C_CH3_OFF 0xdc --#define MLXPLAT_CPLD_LPC_I2C_CH4_OFF 0xdd - - #define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL - #define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ -- MLXPLAT_CPLD_LPC_I2C_CH1_OFF) | \ -+ MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET) | \ - MLXPLAT_CPLD_LPC_PIO_OFFSET) - #define MLXPLAT_CPLD_LPC_REG2 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ -- MLXPLAT_CPLD_LPC_I2C_CH2_OFF) | \ -+ MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET) | \ - MLXPLAT_CPLD_LPC_PIO_OFFSET) - #define MLXPLAT_CPLD_LPC_REG3 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ -- MLXPLAT_CPLD_LPC_I2C_CH3_OFF) | \ -+ MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET) | \ - MLXPLAT_CPLD_LPC_PIO_OFFSET) - #define MLXPLAT_CPLD_LPC_REG4 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ -- MLXPLAT_CPLD_LPC_I2C_CH4_OFF) | \ -+ MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET) | \ - MLXPLAT_CPLD_LPC_PIO_OFFSET) - - /* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */ -@@ -4980,6 +4980,10 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: -@@ -5107,6 +5111,10 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: -@@ -5254,6 +5262,10 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: --- -2.20.1 - diff --git a/patch/0010-platform-mellanox-mlx-platform-Move-bus-shift-assign.patch b/patch/0010-platform-mellanox-mlx-platform-Move-bus-shift-assign.patch deleted file mode 100644 index aaee2599b..000000000 --- a/patch/0010-platform-mellanox-mlx-platform-Move-bus-shift-assign.patch +++ /dev/null @@ -1,38 +0,0 @@ -From efa7f35fe8d6d88cb1aa04ef6839d4de7c7ecd6c Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 8 Feb 2023 08:33:29 +0200 -Subject: [PATCH backport 6.1.42 10/85] platform: mellanox: mlx-platform: Move - bus shift assignment out of the loop - -Move assignment of bus shift setting out of the loop to avoid redundant -operation. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych -Link: https://lore.kernel.org/r/20230208063331.15560-13-vadimp@nvidia.com -Signed-off-by: Hans de Goede ---- - drivers/platform/x86/mlx-platform.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 60062d9f3b9b..7b6779cdb134 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -6008,10 +6008,11 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr) - shift = *nr - mlxplat_mux_data[i].parent; - mlxplat_mux_data[i].parent = *nr; - mlxplat_mux_data[i].base_nr += shift; -- if (shift > 0) -- mlxplat_hotplug->shift_nr = shift; - } - -+ if (shift > 0) -+ mlxplat_hotplug->shift_nr = shift; -+ - return 0; - } - --- -2.20.1 - diff --git a/patch/0011-platform-mellanox-mlx-platform-Initialize-shift-vari.patch b/patch/0011-platform-mellanox-mlx-platform-Initialize-shift-vari.patch deleted file mode 100644 index 2269275b7..000000000 --- a/patch/0011-platform-mellanox-mlx-platform-Initialize-shift-vari.patch +++ /dev/null @@ -1,37 +0,0 @@ -From cf1b6d5dd2e66e5ce675ad6466cf4af034d0ea3c Mon Sep 17 00:00:00 2001 -From: Hans de Goede -Date: Tue, 7 Mar 2023 11:58:42 +0100 -Subject: [PATCH backport 6.1.42 11/85] platform: mellanox: mlx-platform: - Initialize shift variable to 0 - -Initialize shift variable in mlxplat_mlxcpld_verify_bus_topology() -to 0 to avoid the following compile error: - -drivers/platform/x86/mlx-platform.c:6013 - mlxplat_mlxcpld_verify_bus_topology() error: uninitialized symbol 'shift'. - -Fixes: 50b823fdd357 ("platform: mellanox: mlx-platform: Move bus shift assignment out of the loop") -Cc: Vadim Pasternak -Cc: Michael Shych -Signed-off-by: Hans de Goede -Link: https://lore.kernel.org/r/20230307105842.286118-1-hdegoede@redhat.com ---- - drivers/platform/x86/mlx-platform.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 7b6779cdb134..67367f010139 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -5980,7 +5980,7 @@ MODULE_DEVICE_TABLE(dmi, mlxplat_dmi_table); - static int mlxplat_mlxcpld_verify_bus_topology(int *nr) - { - struct i2c_adapter *search_adap; -- int shift, i; -+ int i, shift = 0; - - /* Scan adapters from expected id to verify it is free. */ - *nr = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; --- -2.20.1 - diff --git a/patch/0012-platform-mellanox-Fix-order-in-exit-flow.patch b/patch/0012-platform-mellanox-Fix-order-in-exit-flow.patch deleted file mode 100644 index fd16ec8ff..000000000 --- a/patch/0012-platform-mellanox-Fix-order-in-exit-flow.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 257c3eaf7d68e1855ea9ac93298c5231db24e2e1 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 13 Aug 2023 08:37:32 +0000 -Subject: [PATH backport v6.1 12/32] platform: mellanox: Fix order in exit flow - -Fix exit flow order: call mlxplat_post_exit() after -mlxplat_i2c_main_exit() in order to unregister main i2c driver before -to "mlxplat" driver. - -Fixes: 0170f616f496 ("platform: mellanox: Split initialization procedure") -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych -Link: https://lore.kernel.org/r/20230813083735.39090-2-vadimp@nvidia.com -Signed-off-by: Hans de Goede ---- - drivers/platform/x86/mlx-platform.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 67367f010139..5fb3348023a7 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -6238,8 +6238,6 @@ static void mlxplat_i2c_mux_topolgy_exit(struct mlxplat_priv *priv) - if (priv->pdev_mux[i]) - platform_device_unregister(priv->pdev_mux[i]); - } -- -- mlxplat_post_exit(); - } - - static int mlxplat_i2c_main_complition_notify(void *handle, int id) -@@ -6369,6 +6367,7 @@ static void __exit mlxplat_exit(void) - pm_power_off = NULL; - mlxplat_pre_exit(priv); - mlxplat_i2c_main_exit(priv); -+ mlxplat_post_exit(); - } - module_exit(mlxplat_exit); - --- -2.20.1 - diff --git a/patch/0013-platform-mellanox-mlx-platform-Fix-signals-polarity-.patch b/patch/0013-platform-mellanox-mlx-platform-Fix-signals-polarity-.patch deleted file mode 100644 index 2fbabe2d1..000000000 --- a/patch/0013-platform-mellanox-mlx-platform-Fix-signals-polarity-.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 3813bfae9b78253deff0007f75d5f25e16256888 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 13 Aug 2023 08:37:33 +0000 -Subject: [PATH backport v6.1 13/32] platform: mellanox: mlx-platform: Fix - signals polarity and latch mask - -Change polarity of chassis health and power signals and fix latch reset -mask for L1 switch. - -Fixes: dd635e33b5c9 ("platform: mellanox: Introduce support of new Nvidia L1 switch") -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych -Link: https://lore.kernel.org/r/20230813083735.39090-3-vadimp@nvidia.com -Signed-off-by: Hans de Goede ---- - drivers/platform/x86/mlx-platform.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 5fb3348023a7..69256af04f05 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -237,7 +237,7 @@ - #define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0) - #define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0) - #define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0) --#define MLXPLAT_CPLD_LATCH_RST_MASK BIT(5) -+#define MLXPLAT_CPLD_LATCH_RST_MASK BIT(6) - #define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3) - #define MLXPLAT_CPLD_THERMAL2_PDB_MASK BIT(4) - #define MLXPLAT_CPLD_INTRUSION_MASK BIT(6) -@@ -2475,7 +2475,7 @@ static struct mlxreg_core_item mlxplat_mlxcpld_l1_switch_events_items[] = { - .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, - .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, - .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_pwr_events_items_data), -- .inversed = 0, -+ .inversed = 1, - .health = false, - }, - { -@@ -2484,7 +2484,7 @@ static struct mlxreg_core_item mlxplat_mlxcpld_l1_switch_events_items[] = { - .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, - .mask = MLXPLAT_CPLD_L1_CHA_HEALTH_MASK, - .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_health_events_items_data), -- .inversed = 0, -+ .inversed = 1, - .health = false, - .ind = 8, - }, -@@ -3677,7 +3677,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - { - .label = "latch_reset", - .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, -- .mask = GENMASK(7, 0) & ~BIT(5), -+ .mask = GENMASK(7, 0) & ~BIT(6), - .mode = 0200, - }, - { --- -2.20.1 - diff --git a/patch/0014-platform-mellanox-mlx-platform-Modify-graceful-shutd.patch b/patch/0014-platform-mellanox-mlx-platform-Modify-graceful-shutd.patch deleted file mode 100644 index cdcef3c16..000000000 --- a/patch/0014-platform-mellanox-mlx-platform-Modify-graceful-shutd.patch +++ /dev/null @@ -1,46 +0,0 @@ -From e36789aba49f2728284d169c67162a7075f9931c Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 13 Aug 2023 08:37:34 +0000 -Subject: [PATH backport v6.1 14/32] platform: mellanox: mlx-platform: Modify - graceful shutdown callback and power down mask - -Use kernel_power_off() instead of kernel_halt() to pass through -machine_power_off() -> pm_power_off(), otherwise axillary power does -not go off. - -Change "power down" bitmask. - -Fixes: dd635e33b5c9 ("platform: mellanox: Introduce support of new Nvidia L1 switch") -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych -Link: https://lore.kernel.org/r/20230813083735.39090-4-vadimp@nvidia.com -Signed-off-by: Hans de Goede ---- - drivers/platform/x86/mlx-platform.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 69256af04f05..240bc3174caf 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -222,7 +222,7 @@ - MLXPLAT_CPLD_AGGR_MASK_LC_SDWN) - #define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1 - #define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2 BIT(2) --#define MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT BIT(4) -+#define MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT GENMASK(5, 4) - #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6) - #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0) - #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0) -@@ -2356,7 +2356,7 @@ mlxplat_mlxcpld_l1_switch_pwr_events_handler(void *handle, enum mlxreg_hotplug_k - u8 action) - { - dev_info(&mlxplat_dev->dev, "System shutdown due to short press of power button"); -- kernel_halt(); -+ kernel_power_off(); - return 0; - } - --- -2.20.1 - diff --git a/patch/0015-platform-mellanox-Change-register-offset-addresses.patch b/patch/0015-platform-mellanox-Change-register-offset-addresses.patch deleted file mode 100644 index ac10474b0..000000000 --- a/patch/0015-platform-mellanox-Change-register-offset-addresses.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 3c3fbec3ebc2df518c0e1db05a7f14b3f39ef25f Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 13 Aug 2023 08:37:35 +0000 -Subject: [PATH backport v6.1 15/32] platform: mellanox: Change register offset - addresses - -Move debug register offsets to different location due to hardware changes. - -Fixes: dd635e33b5c9 ("platform: mellanox: Introduce support of new Nvidia L1 switch") -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych -Link: https://lore.kernel.org/r/20230813083735.39090-5-vadimp@nvidia.com -Signed-off-by: Hans de Goede ---- - drivers/platform/x86/mlx-platform.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 240bc3174caf..7d33977d9c60 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -62,10 +62,6 @@ - #define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37 - #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a - #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b --#define MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET 0x3c --#define MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET 0x3d --#define MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET 0x3e --#define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET 0x3f - #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40 - #define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41 - #define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42 -@@ -126,6 +122,10 @@ - #define MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET 0xaa - #define MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET 0xab - #define MLXPLAT_CPLD_LPC_REG_LC_PWR_ON 0xb2 -+#define MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET 0xb6 -+#define MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET 0xb7 -+#define MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET 0xb8 -+#define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET 0xb9 - #define MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET 0xc2 - #define MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT 0xc3 - #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7 --- -2.20.1 - diff --git a/patch/0016-platform-mellanox-Add-new-attributes.patch b/patch/0016-platform-mellanox-Add-new-attributes.patch deleted file mode 100644 index 79f3516f6..000000000 --- a/patch/0016-platform-mellanox-Add-new-attributes.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 65441ac095819a650d3197f750b6c04a734abdc3 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 23 Jul 2023 21:05:12 +0000 -Subject: [PATH backport v6.1 16/32] platform: mellanox: Add new attributes - -Link: https://www.spinics.net/lists/platform-driver-x86/msg39632.html - -Add new attribute: -"lid_open" - to indicate system intrusion detection. -"reset_long_pwr_pb" - to indicate that system has been reset due to -long press of power button. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/x86/mlx-platform.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 7d33977d9c60..26748c285ddc 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -3792,6 +3792,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mask = GENMASK(7, 0) & ~BIT(1), - .mode = 0444, - }, -+ { -+ .label = "lid_open", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0444, -+ }, - { - .label = "clk_brd1_boot_fail", - .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, -@@ -4431,6 +4437,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { - .mask = GENMASK(7, 0) & ~BIT(6), - .mode = 0444, - }, -+ { -+ .label = "reset_long_pwr_pb", -+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), -+ .mode = 0444, -+ }, - { - .label = "pwr_cycle", - .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, --- -2.20.1 - diff --git a/patch/0017-Extend-driver-to-support-XMC-XM25QH256C-device.patch b/patch/0017-Extend-driver-to-support-XMC-XM25QH256C-device.patch deleted file mode 100644 index 8cf63367e..000000000 --- a/patch/0017-Extend-driver-to-support-XMC-XM25QH256C-device.patch +++ /dev/null @@ -1,30 +0,0 @@ -From a3f125fa447f51491391f5683ef6ca5bce36e97a Mon Sep 17 00:00:00 2001 -From: Owen Wu -Date: Tue, 15 Oct 2024 14:02:06 +0800 -Subject: [PATCH] Extend driver to support XMC XM25QH256C device. - -Add new component for alternative support - -Signed-off-by: Owen Wu ---- - drivers/mtd/spi-nor/xmc.c | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/drivers/mtd/spi-nor/xmc.c b/drivers/mtd/spi-nor/xmc.c -index 051411e86..74fd4e284 100644 ---- a/drivers/mtd/spi-nor/xmc.c -+++ b/drivers/mtd/spi-nor/xmc.c -@@ -16,6 +16,10 @@ static const struct flash_info xmc_nor_parts[] = { - { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256) - NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | - SPI_NOR_QUAD_READ) }, -+ { "XM25QH256C", INFO(0x204019, 0, 64 * 1024, 512) -+ NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | -+ SPI_NOR_QUAD_READ) -+ FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, - }; - - const struct spi_nor_manufacturer spi_nor_xmc = { --- -2.25.1 - diff --git a/patch/0017-platform-mellanox-Add-field-upgrade-capability-regis.patch b/patch/0017-platform-mellanox-Add-field-upgrade-capability-regis.patch deleted file mode 100644 index 1c3d64150..000000000 --- a/patch/0017-platform-mellanox-Add-field-upgrade-capability-regis.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 02ec65e86e92d25eaf0280db68cc045a97e70ea5 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 23 Jul 2023 21:13:52 +0000 -Subject: [PATH backport v6.1 17/32] platform: mellanox: Add field upgrade - capability register - -Link: https://www.spinics.net/lists/platform-driver-x86/msg39635.html - -Add new register to indicate the method of FPGA/CPLD field upgrade -supported on the specific system. -Currently two masks are available: -b00 - field upgrade through LPC gateway (new method introduced to - accelerate field upgrade process). -b11 - field upgrade through CPU GPIO pins (old method). - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/x86/mlx-platform.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 26748c285ddc..647a10252c2f 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -62,6 +62,7 @@ - #define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37 - #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a - #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b -+#define MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET 0x3c - #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40 - #define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41 - #define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42 -@@ -236,6 +237,7 @@ - #define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4) - #define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0) - #define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0) -+#define MLXPLAT_CPLD_FU_CAP_MASK GENMASK(1, 0) - #define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0) - #define MLXPLAT_CPLD_LATCH_RST_MASK BIT(6) - #define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3) -@@ -3680,6 +3682,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mask = GENMASK(7, 0) & ~BIT(6), - .mode = 0200, - }, -+ { -+ .label = "jtag_cap", -+ .reg = MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET, -+ .mask = MLXPLAT_CPLD_FU_CAP_MASK, -+ .bit = 1, -+ .mode = 0444, -+ }, - { - .label = "jtag_enable", - .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, -@@ -4935,6 +4944,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: - case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: -@@ -5046,6 +5056,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: -@@ -5203,6 +5214,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: --- -2.20.1 - diff --git a/patch/0018-platform-mellanox-Modify-reset-causes-description.patch b/patch/0018-platform-mellanox-Modify-reset-causes-description.patch deleted file mode 100644 index 0cca1b552..000000000 --- a/patch/0018-platform-mellanox-Modify-reset-causes-description.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 153daa685be413192d55d015d8387becaa6b58b2 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 23 Jul 2023 21:25:49 +0000 -Subject: [PATH backport v6.1 18/32] platform: mellanox: Modify reset causes - description - -Link: https://www.spinics.net/lists/platform-driver-x86/msg39636.html - -For system of classes VMOD0005, VMOD0010: -- remove "reset_from_comex", since this cause doesn't define specific - reason. -- add more specific reason "reset_sw_reset", which is set along with - removed "reset_from_comex". - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/x86/mlx-platform.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 647a10252c2f..5b0579752afb 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -3556,12 +3556,6 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mask = GENMASK(7, 0) & ~BIT(2), - .mode = 0444, - }, -- { -- .label = "reset_from_comex", -- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, -- .mask = GENMASK(7, 0) & ~BIT(4), -- .mode = 0444, -- }, - { - .label = "reset_from_asic", - .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, -@@ -3580,6 +3574,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mask = GENMASK(7, 0) & ~BIT(7), - .mode = 0444, - }, -+ { -+ .label = "reset_sw_reset", -+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0444, -+ }, - { - .label = "reset_comex_pwr_fail", - .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, --- -2.20.1 - diff --git a/patch/0019-platform-mellanox-mlx-platform-Modify-health-and-pow.patch b/patch/0019-platform-mellanox-mlx-platform-Modify-health-and-pow.patch deleted file mode 100644 index b4a4afce8..000000000 --- a/patch/0019-platform-mellanox-mlx-platform-Modify-health-and-pow.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 05834de8484930c01d705e078e63eb44fbacd362 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 23 Jul 2023 21:42:37 +0000 -Subject: [PATH backport v6.1 19/32] platform: mellanox: mlx-platform: Modify - health and power hotplug action - -Link: https://www.spinics.net/lists/platform-driver-x86/msg39634.html - -Set explicitly hotplug event action for health and power signals for -L1 switch as "MLXREG_HOTPLUG_DEVICE_NO_ACTION" in order to allow -processing of notification callback even I2C parent bus is not -specified. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/x86/mlx-platform.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 5b0579752afb..648b27eff0b0 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -2373,6 +2373,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_pwr_events_items_data[] - .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, - .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, - .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, - .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_pwr_events_notifier, - }, - }; -@@ -2433,6 +2434,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_health_events_items_dat - .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, - .mask = MLXPLAT_CPLD_INTRUSION_MASK, - .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, - .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_intrusion_events_notifier, - }, - { --- -2.20.1 - diff --git a/patch/0020-platform-mellanox-mlx-platform-Add-reset-cause-attri.patch b/patch/0020-platform-mellanox-mlx-platform-Add-reset-cause-attri.patch deleted file mode 100644 index 744bbc21c..000000000 --- a/patch/0020-platform-mellanox-mlx-platform-Add-reset-cause-attri.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 9a981f2c8011e3840eb126404cb77a476f77e2c7 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Mon, 24 Jul 2023 05:20:15 +0000 -Subject: [PATH backport v6.1 20/32] platform: mellanox: mlx-platform: Add - reset cause attribute - -Link: https://www.spinics.net/lists/platform-driver-x86/msg39638.html - -Extend IO registers description for some system types with reset cause -attribute "reset_swb_dc_dc_pwr_fail" to indicate reset caused by switch -board DC-DC power failure. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/x86/mlx-platform.c | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 648b27eff0b0..8e07ed3dc552 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -3558,6 +3558,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mask = GENMASK(7, 0) & ~BIT(2), - .mode = 0444, - }, -+ { -+ .label = "reset_swb_dc_dc_pwr_fail", -+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0444, -+ }, - { - .label = "reset_from_asic", - .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, --- -2.20.1 - diff --git a/patch/0021-platform-mellanox-mlx-platform-add-support-for-addit.patch b/patch/0021-platform-mellanox-mlx-platform-add-support-for-addit.patch deleted file mode 100644 index 27ab1fb88..000000000 --- a/patch/0021-platform-mellanox-mlx-platform-add-support-for-addit.patch +++ /dev/null @@ -1,131 +0,0 @@ -From baa136fc6b3c26501c77070a73abd2d6f95b462a Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Mon, 24 Jul 2023 05:54:47 +0000 -Subject: [PATH backport v6.1 21/32] platform: mellanox: mlx-platform: add - support for additional CPLD - -Link: https://www.spinics.net/lists/platform-driver-x86/msg39641.html - -Extend to support 5-th CPLD version, PN and minimal version registers. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/x86/mlx-platform.c | 31 +++++++++++++++++++++++++++++ - 1 file changed, 31 insertions(+) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 8e07ed3dc552..dce35934cc37 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -95,6 +95,9 @@ - #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88 - #define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89 - #define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a -+#define MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET 0x8e -+#define MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET 0x8f -+#define MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET 0x90 - #define MLXPLAT_CPLD_LPC_REG_EROT_OFFSET 0x91 - #define MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET 0x92 - #define MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET 0x93 -@@ -129,6 +132,7 @@ - #define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET 0xb9 - #define MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET 0xc2 - #define MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT 0xc3 -+#define MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET 0xc4 - #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7 - #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8 - #define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9 -@@ -3431,6 +3435,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .bit = GENMASK(7, 0), - .mode = 0444, - }, -+ { -+ .label = "cpld5_version", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, - { - .label = "cpld1_pn", - .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, -@@ -3459,6 +3469,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mode = 0444, - .regnum = 2, - }, -+ { -+ .label = "cpld5_pn", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET, -+ .bit = GENMASK(15, 0), -+ .mode = 0444, -+ .regnum = 2, -+ }, - { - .label = "cpld1_version_min", - .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, -@@ -3483,6 +3500,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .bit = GENMASK(7, 0), - .mode = 0444, - }, -+ { -+ .label = "cpld5_version_min", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, - { - .label = "asic_reset", - .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, -@@ -5031,6 +5054,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: -@@ -5039,6 +5063,8 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: -@@ -5150,6 +5176,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: -@@ -5191,6 +5218,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: -@@ -5199,6 +5227,8 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: -@@ -5302,6 +5332,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: --- -2.20.1 - diff --git a/patch/0022-platform-mellanox-mlx-platform-Modify-power-off-call.patch b/patch/0022-platform-mellanox-mlx-platform-Modify-power-off-call.patch deleted file mode 100644 index 2b9debe07..000000000 --- a/patch/0022-platform-mellanox-mlx-platform-Modify-power-off-call.patch +++ /dev/null @@ -1,37 +0,0 @@ -From cca82c5a6efc06d8d9b5c7b8b83054ff09363bc4 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Mon, 24 Jul 2023 06:22:13 +0000 -Subject: [PATH backport v6.1 22/32] platform: mellanox: mlx-platform: Modify - power off callback - -Link: https://www.spinics.net/lists/platform-driver-x86/msg39639.html - -Extend platform power off callback with kernel_halt() call. - -When powering off, the process involves setting a halt bit in the -register space, which is then activated after a certain delay and -power off auxiliary power. By invoking `kernel_halt()` within this -timeframe, the intention is to facilitate a clean system power-off -sequence. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/x86/mlx-platform.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index dce35934cc37..a505f619f337 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -5539,6 +5539,7 @@ static void mlxplat_poweroff(void) - struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); - - regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, MLXPLAT_CPLD_HALT_MASK); -+ kernel_halt(); - } - - static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi) --- -2.20.1 - diff --git a/patch/0023-platform-mellanox-Cosmetic-changes.patch b/patch/0023-platform-mellanox-Cosmetic-changes.patch deleted file mode 100644 index 65f561901..000000000 --- a/patch/0023-platform-mellanox-Cosmetic-changes.patch +++ /dev/null @@ -1,76 +0,0 @@ -From 851d7b63b861b5f042ec40ee148c7a4503cdee0e Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 30 Jul 2023 20:35:23 +0000 -Subject: [PATH backport v6.1 23/32] platform: mellanox: Cosmetic changes - -Link: https://www.spinics.net/lists/platform-driver-x86/msg39637.html - -Fix routines and labels names by s/topolgy/topology. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/x86/mlx-platform.c | 14 +++++++------- - 1 file changed, 7 insertions(+), 7 deletions(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index a505f619f337..1010064d54e9 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -6265,7 +6265,7 @@ mlxplat_i2c_mux_complition_notify(void *handle, struct i2c_adapter *parent, - return mlxplat_post_init(priv); - } - --static int mlxplat_i2c_mux_topolgy_init(struct mlxplat_priv *priv) -+static int mlxplat_i2c_mux_topology_init(struct mlxplat_priv *priv) - { - int i, err; - -@@ -6294,7 +6294,7 @@ static int mlxplat_i2c_mux_topolgy_init(struct mlxplat_priv *priv) - return err; - } - --static void mlxplat_i2c_mux_topolgy_exit(struct mlxplat_priv *priv) -+static void mlxplat_i2c_mux_topology_exit(struct mlxplat_priv *priv) - { - int i; - -@@ -6308,7 +6308,7 @@ static int mlxplat_i2c_main_complition_notify(void *handle, int id) - { - struct mlxplat_priv *priv = handle; - -- return mlxplat_i2c_mux_topolgy_init(priv); -+ return mlxplat_i2c_mux_topology_init(priv); - } - - static int mlxplat_i2c_main_init(struct mlxplat_priv *priv) -@@ -6336,14 +6336,14 @@ static int mlxplat_i2c_main_init(struct mlxplat_priv *priv) - } - - if (priv->i2c_main_init_status == MLXPLAT_I2C_MAIN_BUS_NOTIFIED) { -- err = mlxplat_i2c_mux_topolgy_init(priv); -+ err = mlxplat_i2c_mux_topology_init(priv); - if (err) -- goto fail_mlxplat_i2c_mux_topolgy_init; -+ goto fail_mlxplat_i2c_mux_topology_init; - } - - return 0; - --fail_mlxplat_i2c_mux_topolgy_init: -+fail_mlxplat_i2c_mux_topology_init: - fail_platform_i2c_register: - fail_mlxplat_mlxcpld_verify_bus_topology: - return err; -@@ -6351,7 +6351,7 @@ static int mlxplat_i2c_main_init(struct mlxplat_priv *priv) - - static void mlxplat_i2c_main_exit(struct mlxplat_priv *priv) - { -- mlxplat_i2c_mux_topolgy_exit(priv); -+ mlxplat_i2c_mux_topology_exit(priv); - if (priv->pdev_i2c) - platform_device_unregister(priv->pdev_i2c); - } --- -2.20.1 - diff --git a/patch/0024-platform-mellanox-mlx-platform-Add-reset-callback.patch b/patch/0024-platform-mellanox-mlx-platform-Add-reset-callback.patch deleted file mode 100644 index fa0177e36..000000000 --- a/patch/0024-platform-mellanox-mlx-platform-Add-reset-callback.patch +++ /dev/null @@ -1,162 +0,0 @@ -From c581e018f6e8f1bf81b75b118a96425abf7dcc2b Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 30 Jul 2023 20:50:15 +0000 -Subject: [PATH backport v6.1 24/32] platform: mellanox: mlx-platform: Add - reset callback - -Link: https://www.spinics.net/lists/platform-driver-x86/msg39640.html - -On L1 switches reset should include special actions against CPLD device -for performing graceful operations. -For that purpose, special PLATFORM_RESET# signal should be indicated. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/x86/mlx-platform.c | 46 +++++++++++++++++++++++++++-- - 1 file changed, 44 insertions(+), 2 deletions(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 1010064d54e9..296569492a71 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -35,6 +35,7 @@ - #define MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET 0x09 - #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET 0x0a - #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET 0x0b -+#define MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET 0x17 - #define MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET 0x19 - #define MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET 0x1c - #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d -@@ -254,6 +255,7 @@ - MLXPLAT_CPLD_PWM_PG_MASK) - #define MLXPLAT_CPLD_I2C_CAP_BIT 0x04 - #define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5, MLXPLAT_CPLD_I2C_CAP_BIT) -+#define MLXPLAT_CPLD_SYS_RESET_MASK BIT(0) - - /* Masks for aggregation for comex carriers */ - #define MLXPLAT_CPLD_AGGR_MASK_CARRIER BIT(1) -@@ -265,6 +267,7 @@ - #define MLXPLAT_CPLD_LPC_LC_MASK GENMASK(7, 0) - - #define MLXPLAT_CPLD_HALT_MASK BIT(3) -+#define MLXPLAT_CPLD_RESET_MASK GENMASK(7, 1) - - /* Default I2C parent bus number */ - #define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1 -@@ -441,6 +444,7 @@ static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = { - static int mlxplat_max_adap_num; - static int mlxplat_mux_num; - static struct i2c_mux_reg_platform_data *mlxplat_mux_data; -+static struct notifier_block *mlxplat_reboot_nb; - - /* Platform extended mux data */ - static struct i2c_mux_reg_platform_data mlxplat_extended_mux_data[] = { -@@ -2361,8 +2365,11 @@ static int - mlxplat_mlxcpld_l1_switch_pwr_events_handler(void *handle, enum mlxreg_hotplug_kind kind, - u8 action) - { -- dev_info(&mlxplat_dev->dev, "System shutdown due to short press of power button"); -- kernel_power_off(); -+ if (action) { -+ dev_info(&mlxplat_dev->dev, "System shutdown due to short press of power button"); -+ kernel_power_off(); -+ } -+ - return 0; - } - -@@ -4957,6 +4964,7 @@ static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type3[] = { - static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) - { - switch (reg) { -+ case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: -@@ -5065,6 +5073,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: -@@ -5229,6 +5238,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: -@@ -5533,11 +5543,33 @@ static struct mlxreg_core_platform_data - *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS]; - static const struct regmap_config *mlxplat_regmap_config; - -+/* Platform default reset function */ -+static int mlxplat_reboot_notifier(struct notifier_block *nb, unsigned long action, void *unused) -+{ -+ struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); -+ u32 regval; -+ int ret; -+ -+ ret = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET, ®val); -+ -+ if (action == SYS_RESTART && !ret && regval & MLXPLAT_CPLD_SYS_RESET_MASK) -+ regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET, -+ MLXPLAT_CPLD_RESET_MASK); -+ -+ return NOTIFY_DONE; -+} -+ -+static struct notifier_block mlxplat_reboot_default_nb = { -+ .notifier_call = mlxplat_reboot_notifier, -+}; -+ - /* Platform default poweroff function */ - static void mlxplat_poweroff(void) - { - struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); - -+ if (mlxplat_reboot_nb) -+ unregister_reboot_notifier(mlxplat_reboot_nb); - regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, MLXPLAT_CPLD_HALT_MASK); - kernel_halt(); - } -@@ -5861,6 +5893,7 @@ static int __init mlxplat_dmi_l1_switch_matched(const struct dmi_system_id *dmi) - mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; - mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_rack_switch; - pm_power_off = mlxplat_poweroff; -+ mlxplat_reboot_nb = &mlxplat_reboot_default_nb; - - return 1; - } -@@ -6410,8 +6443,15 @@ static int __init mlxplat_init(void) - if (err) - goto fail_regcache_sync; - -+ if (mlxplat_reboot_nb) { -+ err = register_reboot_notifier(mlxplat_reboot_nb); -+ if (err) -+ goto fail_register_reboot_notifier; -+ } -+ - return 0; - -+fail_register_reboot_notifier: - fail_regcache_sync: - mlxplat_pre_exit(priv); - fail_mlxplat_i2c_main_init: -@@ -6429,6 +6469,8 @@ static void __exit mlxplat_exit(void) - - if (pm_power_off) - pm_power_off = NULL; -+ if (mlxplat_reboot_nb) -+ unregister_reboot_notifier(mlxplat_reboot_nb); - mlxplat_pre_exit(priv); - mlxplat_i2c_main_exit(priv); - mlxplat_post_exit(); --- -2.20.1 - diff --git a/patch/0025-platform-mellanox-mlx-platform-Prepare-driver-to-all.patch b/patch/0025-platform-mellanox-mlx-platform-Prepare-driver-to-all.patch deleted file mode 100644 index 743a8cf3c..000000000 --- a/patch/0025-platform-mellanox-mlx-platform-Prepare-driver-to-all.patch +++ /dev/null @@ -1,269 +0,0 @@ -From 72ca44d6df08d42b18489a68cdb7217481394149 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Mon, 24 Jul 2023 08:36:36 +0000 -Subject: [PATH backport v6.1 25/32] platform: mellanox: mlx-platform: Prepare - driver to allow probing through ACPI infrastructure - -Link: https://www.spinics.net/lists/platform-driver-x86/msg39642.html - -Currently driver is activated through DMI hooks. -Prepare driver to allow activation also through ACPI trigger. - -Modify mlxplat_init()/mlxplat_exit() routines. -Add mlxplat_probe()/mlxplat_remove() routines and "mlxplat_driver" -structure. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/x86/mlx-platform.c | 91 +++++++++++++++++++---------- - 1 file changed, 61 insertions(+), 30 deletions(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 296569492a71..73f887614e04 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -5574,6 +5574,17 @@ static void mlxplat_poweroff(void) - kernel_halt(); - } - -+static int __init mlxplat_register_platform_device(void) -+{ -+ mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, -1, -+ mlxplat_lpc_resources, -+ ARRAY_SIZE(mlxplat_lpc_resources)); -+ if (IS_ERR(mlxplat_dev)) -+ return PTR_ERR(mlxplat_dev); -+ else -+ return 1; -+} -+ - static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi) - { - int i; -@@ -5594,7 +5605,7 @@ static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi) - mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; - mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; - -- return 1; -+ return mlxplat_register_platform_device(); - } - - static int __init mlxplat_dmi_default_wc_matched(const struct dmi_system_id *dmi) -@@ -5617,7 +5628,7 @@ static int __init mlxplat_dmi_default_wc_matched(const struct dmi_system_id *dmi - mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; - mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; - -- return 1; -+ return mlxplat_register_platform_device(); - } - - static int __init mlxplat_dmi_default_eth_wc_blade_matched(const struct dmi_system_id *dmi) -@@ -5642,7 +5653,7 @@ static int __init mlxplat_dmi_default_eth_wc_blade_matched(const struct dmi_syst - mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; - mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng; - -- return 1; -+ return mlxplat_register_platform_device(); - } - - static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi) -@@ -5665,7 +5676,7 @@ static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi) - mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; - mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; - -- return 1; -+ return mlxplat_register_platform_device(); - } - - static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi) -@@ -5688,7 +5699,7 @@ static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi) - mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; - mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; - -- return 1; -+ return mlxplat_register_platform_device(); - } - - static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi) -@@ -5711,7 +5722,7 @@ static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi) - mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; - mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; - -- return 1; -+ return mlxplat_register_platform_device(); - } - - static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi) -@@ -5737,7 +5748,7 @@ static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi) - mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; - mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng; - -- return 1; -+ return mlxplat_register_platform_device(); - } - - static int __init mlxplat_dmi_comex_matched(const struct dmi_system_id *dmi) -@@ -5762,7 +5773,7 @@ static int __init mlxplat_dmi_comex_matched(const struct dmi_system_id *dmi) - mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; - mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_comex; - -- return 1; -+ return mlxplat_register_platform_device(); - } - - static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi) -@@ -5788,7 +5799,7 @@ static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi) - mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; - mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; - -- return 1; -+ return mlxplat_register_platform_device(); - } - - static int __init mlxplat_dmi_modular_matched(const struct dmi_system_id *dmi) -@@ -5808,7 +5819,7 @@ static int __init mlxplat_dmi_modular_matched(const struct dmi_system_id *dmi) - mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; - mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_eth_modular; - -- return 1; -+ return mlxplat_register_platform_device(); - } - - static int __init mlxplat_dmi_chassis_blade_matched(const struct dmi_system_id *dmi) -@@ -5830,7 +5841,7 @@ static int __init mlxplat_dmi_chassis_blade_matched(const struct dmi_system_id * - mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; - mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; - -- return 1; -+ return mlxplat_register_platform_device(); - } - - static int __init mlxplat_dmi_rack_switch_matched(const struct dmi_system_id *dmi) -@@ -5851,7 +5862,7 @@ static int __init mlxplat_dmi_rack_switch_matched(const struct dmi_system_id *dm - mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; - mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_rack_switch; - -- return 1; -+ return mlxplat_register_platform_device(); - } - - static int __init mlxplat_dmi_ng800_matched(const struct dmi_system_id *dmi) -@@ -5872,7 +5883,7 @@ static int __init mlxplat_dmi_ng800_matched(const struct dmi_system_id *dmi) - mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; - mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; - -- return 1; -+ return mlxplat_register_platform_device(); - } - - static int __init mlxplat_dmi_l1_switch_matched(const struct dmi_system_id *dmi) -@@ -5895,7 +5906,7 @@ static int __init mlxplat_dmi_l1_switch_matched(const struct dmi_system_id *dmi) - pm_power_off = mlxplat_poweroff; - mlxplat_reboot_nb = &mlxplat_reboot_default_nb; - -- return 1; -+ return mlxplat_register_platform_device(); - } - - static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { -@@ -6139,12 +6150,6 @@ static int mlxplat_lpc_cpld_device_init(struct resource **hotplug_resources, - { - int err; - -- mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, PLATFORM_DEVID_NONE, -- mlxplat_lpc_resources, -- ARRAY_SIZE(mlxplat_lpc_resources)); -- if (IS_ERR(mlxplat_dev)) -- return PTR_ERR(mlxplat_dev); -- - mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev, - mlxplat_lpc_resources[1].start, 1); - if (!mlxplat_mlxcpld_regmap_ctx.base) { -@@ -6158,13 +6163,11 @@ static int mlxplat_lpc_cpld_device_init(struct resource **hotplug_resources, - return 0; - - fail_devm_ioport_map: -- platform_device_unregister(mlxplat_dev); - return err; - } - - static void mlxplat_lpc_cpld_device_exit(void) - { -- platform_device_unregister(mlxplat_dev); - } - - static int -@@ -6389,16 +6392,13 @@ static void mlxplat_i2c_main_exit(struct mlxplat_priv *priv) - platform_device_unregister(priv->pdev_i2c); - } - --static int __init mlxplat_init(void) -+static int mlxplat_probe(struct platform_device *pdev) - { -- unsigned int hotplug_resources_size; -- struct resource *hotplug_resources; -+ unsigned int hotplug_resources_size = 0; -+ struct resource *hotplug_resources = NULL; - struct mlxplat_priv *priv; - int i, err; - -- if (!dmi_check_system(mlxplat_dmi_table)) -- return -ENODEV; -- - err = mlxplat_pre_init(&hotplug_resources, &hotplug_resources_size); - if (err) - return err; -@@ -6461,9 +6461,8 @@ static int __init mlxplat_init(void) - - return err; - } --module_init(mlxplat_init); - --static void __exit mlxplat_exit(void) -+static int mlxplat_remove(struct platform_device *pdev) - { - struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); - -@@ -6474,6 +6473,38 @@ static void __exit mlxplat_exit(void) - mlxplat_pre_exit(priv); - mlxplat_i2c_main_exit(priv); - mlxplat_post_exit(); -+ return 0; -+} -+ -+static struct platform_driver mlxplat_driver = { -+ .driver = { -+ .name = "mlxplat", -+ .probe_type = PROBE_FORCE_SYNCHRONOUS, -+ }, -+ .probe = mlxplat_probe, -+ .remove = mlxplat_remove, -+}; -+ -+static int __init mlxplat_init(void) -+{ -+ int err; -+ -+ if (!dmi_check_system(mlxplat_dmi_table)) -+ return -ENODEV; -+ -+ err = platform_driver_register(&mlxplat_driver); -+ if (err) -+ return err; -+ return 0; -+} -+module_init(mlxplat_init); -+ -+static void __exit mlxplat_exit(void) -+{ -+ if (mlxplat_dev) -+ platform_device_unregister(mlxplat_dev); -+ -+ platform_driver_unregister(&mlxplat_driver); - } - module_exit(mlxplat_exit); - --- -2.20.1 - diff --git a/patch/0026-platform-mellanox-mlx-platform-Introduce-ACPI-init-f.patch b/patch/0026-platform-mellanox-mlx-platform-Introduce-ACPI-init-f.patch deleted file mode 100644 index 3a2bae4a6..000000000 --- a/patch/0026-platform-mellanox-mlx-platform-Introduce-ACPI-init-f.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 003ecc1dc963e5bc53be9796139431e3189f31c2 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Mon, 24 Jul 2023 08:53:07 +0000 -Subject: [PATH backport v6.1 26/32] platform: mellanox: mlx-platform: - Introduce ACPI init flow - -Link: https://www.spinics.net/lists/platform-driver-x86/msg39643.html - -Introduce support for ACPI initialization flow - add ACPI match hook. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/x86/mlx-platform.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 73f887614e04..feedfba0acf3 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -6396,9 +6396,14 @@ static int mlxplat_probe(struct platform_device *pdev) - { - unsigned int hotplug_resources_size = 0; - struct resource *hotplug_resources = NULL; -+ struct acpi_device *acpi_dev; - struct mlxplat_priv *priv; - int i, err; - -+ acpi_dev = ACPI_COMPANION(&pdev->dev); -+ if (acpi_dev) -+ mlxplat_dev = pdev; -+ - err = mlxplat_pre_init(&hotplug_resources, &hotplug_resources_size); - if (err) - return err; -@@ -6476,9 +6481,16 @@ static int mlxplat_remove(struct platform_device *pdev) - return 0; - } - -+static const struct acpi_device_id mlxplat_acpi_table[] = { -+ { "MLNXBF49", 0 }, -+ {} -+}; -+MODULE_DEVICE_TABLE(acpi, mlxplat_acpi_table); -+ - static struct platform_driver mlxplat_driver = { - .driver = { - .name = "mlxplat", -+ .acpi_match_table = ACPI_PTR(mlxplat_acpi_table), - .probe_type = PROBE_FORCE_SYNCHRONOUS, - }, - .probe = mlxplat_probe, --- -2.20.1 - diff --git a/patch/0027-platform-mellanox-mlx-platform-Get-interrupt-line-th.patch b/patch/0027-platform-mellanox-mlx-platform-Get-interrupt-line-th.patch deleted file mode 100644 index d98f9a44b..000000000 --- a/patch/0027-platform-mellanox-mlx-platform-Get-interrupt-line-th.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 7f7f1a8c4df413bc1faf50d4f5cd77f3f5f19796 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Mon, 24 Jul 2023 10:10:52 +0000 -Subject: [PATH backport v6.1 27/32] platform: mellanox: mlx-platform: Get - interrupt line through ACPI - -Link: https://www.spinics.net/lists/platform-driver-x86/msg39645.html - -Add support for getting system interrupt line from ACPI table. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/x86/mlx-platform.c | 13 +++++++++++-- - 1 file changed, 11 insertions(+), 2 deletions(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index feedfba0acf3..3eccb6628ccc 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -343,6 +343,7 @@ - * @hotplug_resources: system hotplug resources - * @hotplug_resources_size: size of system hotplug resources - * @hi2c_main_init_status: init status of I2C main bus -+ * @irq_fpga: FPGA IRQ number - */ - struct mlxplat_priv { - struct platform_device *pdev_i2c; -@@ -356,6 +357,7 @@ struct mlxplat_priv { - struct resource *hotplug_resources; - unsigned int hotplug_resources_size; - u8 i2c_main_init_status; -+ int irq_fpga; - }; - - static struct platform_device *mlxplat_dev; -@@ -6188,6 +6190,8 @@ static int mlxplat_post_init(struct mlxplat_priv *priv) - /* Add hotplug driver */ - if (mlxplat_hotplug) { - mlxplat_hotplug->regmap = priv->regmap; -+ if (priv->irq_fpga) -+ mlxplat_hotplug->irq = priv->irq_fpga; - priv->pdev_hotplug = - platform_device_register_resndata(&mlxplat_dev->dev, - "mlxreg-hotplug", PLATFORM_DEVID_NONE, -@@ -6398,11 +6402,15 @@ static int mlxplat_probe(struct platform_device *pdev) - struct resource *hotplug_resources = NULL; - struct acpi_device *acpi_dev; - struct mlxplat_priv *priv; -- int i, err; -+ int irq_fpga = 0, i, err; - - acpi_dev = ACPI_COMPANION(&pdev->dev); -- if (acpi_dev) -+ if (acpi_dev) { -+ irq_fpga = acpi_dev_gpio_irq_get(acpi_dev, 0); -+ if (irq_fpga < 0) -+ return -ENODEV; - mlxplat_dev = pdev; -+ } - - err = mlxplat_pre_init(&hotplug_resources, &hotplug_resources_size); - if (err) -@@ -6417,6 +6425,7 @@ static int mlxplat_probe(struct platform_device *pdev) - platform_set_drvdata(mlxplat_dev, priv); - priv->hotplug_resources = hotplug_resources; - priv->hotplug_resources_size = hotplug_resources_size; -+ priv->irq_fpga = irq_fpga; - - if (!mlxplat_regmap_config) - mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config; --- -2.20.1 - diff --git a/patch/0028-platform-mellanox-Add-initial-support-for-PCIe-based.patch b/patch/0028-platform-mellanox-Add-initial-support-for-PCIe-based.patch deleted file mode 100644 index 1e38c81d3..000000000 --- a/patch/0028-platform-mellanox-Add-initial-support-for-PCIe-based.patch +++ /dev/null @@ -1,221 +0,0 @@ -From c3e2605f6350ab19e38352e4c8b3b78621bf8a2f Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 30 Jul 2023 21:17:07 +0000 -Subject: [PATH backport v6.1 28/32] platform: mellanox: Add initial support - for PCIe based programming logic device - -Link: https://www.spinics.net/lists/platform-driver-x86/msg39644.html - -Extend driver to support logic implemented by FPGA device connected -through PCIe bus. - -The motivation two support new generation of Nvidia COME module -equipped with Lattice LFD2NX-40 FPGA device. - -In order to support new Nvidia COME module FPGA device driver -initialization flow is modified. In case FPGA device is detected, -system resources are to be mapped to this device, otherwise system -resources are to be mapped same as it has been done before for Lattice -LPC based CPLD. - -FPGA device is associated with three PCIe devices: -- PCIe-LPC bridge for main register space access. -- PCIe-I2C bridge for I2C controller access. -- PCIe-JTAG bridge for JTAG access. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/x86/mlx-platform.c | 134 +++++++++++++++++++++++++++- - 1 file changed, 132 insertions(+), 2 deletions(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 3eccb6628ccc..44f107965832 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -331,6 +332,12 @@ - #define MLXPLAT_I2C_MAIN_BUS_NOTIFIED 0x01 - #define MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED 0x02 - -+/* Lattice FPGA PCI configuration */ -+#define PCI_VENDOR_ID_LATTICE 0x1204 -+#define PCI_DEVICE_ID_LATTICE_I2C_BRIDGE 0x9c2f -+#define PCI_DEVICE_ID_LATTICE_JTAG_BRIDGE 0x9c30 -+#define PCI_DEVICE_ID_LATTICE_LPC_BRIDGE 0x9c32 -+ - /* mlxplat_priv - platform private data - * @pdev_i2c - i2c controller platform device - * @pdev_mux - array of mux platform devices -@@ -362,6 +369,7 @@ struct mlxplat_priv { - - static struct platform_device *mlxplat_dev; - static int mlxplat_i2c_main_complition_notify(void *handle, int id); -+static void __iomem *i2c_bridge_addr, *jtag_bridge_addr; - - /* Regions for LPC I2C controller and LPC base register space */ - static const struct resource mlxplat_lpc_resources[] = { -@@ -5544,6 +5552,9 @@ static struct mlxreg_core_platform_data *mlxplat_fan; - static struct mlxreg_core_platform_data - *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS]; - static const struct regmap_config *mlxplat_regmap_config; -+static struct pci_dev *lpc_bridge; -+static struct pci_dev *i2c_bridge; -+static struct pci_dev *jtag_bridge; - - /* Platform default reset function */ - static int mlxplat_reboot_notifier(struct notifier_block *nb, unsigned long action, void *unused) -@@ -6172,15 +6183,131 @@ static void mlxplat_lpc_cpld_device_exit(void) - { - } - -+static int -+mlxplat_pci_fpga_device_init(unsigned int device, const char *res_name, struct pci_dev **pci_bridge, -+ void __iomem **pci_bridge_addr) -+{ -+ void __iomem *pci_mem_addr; -+ struct pci_dev *pci_dev; -+ int err; -+ -+ pci_dev = pci_get_device(PCI_VENDOR_ID_LATTICE, device, NULL); -+ if (!pci_dev) -+ return -ENODEV; -+ -+ err = pci_enable_device(pci_dev); -+ if (err) { -+ dev_err(&pci_dev->dev, "pci_enable_device failed with error %d\n", err); -+ goto fail_pci_enable_device; -+ } -+ -+ err = pci_request_region(pci_dev, 0, res_name); -+ if (err) { -+ dev_err(&pci_dev->dev, "pci_request_regions failed with error %d\n", err); -+ goto fail_pci_request_regions; -+ } -+ -+ err = dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(64)); -+ if (err) { -+ err = dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32)); -+ if (err) { -+ dev_err(&pci_dev->dev, "dma_set_mask failed with error %d\n", err); -+ goto fail_pci_set_dma_mask; -+ } -+ } -+ -+ pci_set_master(pci_dev); -+ -+ pci_mem_addr = devm_ioremap(&pci_dev->dev, pci_resource_start(pci_dev, 0), -+ pci_resource_len(pci_dev, 0)); -+ if (!pci_mem_addr) { -+ dev_err(&mlxplat_dev->dev, "ioremap failed\n"); -+ err = -EIO; -+ goto fail_ioremap; -+ } -+ -+ *pci_bridge = pci_dev; -+ *pci_bridge_addr = pci_mem_addr; -+ -+ return 0; -+ -+fail_ioremap: -+fail_pci_set_dma_mask: -+ pci_release_regions(pci_dev); -+fail_pci_request_regions: -+ pci_disable_device(pci_dev); -+fail_pci_enable_device: -+ return err; -+} -+ -+static void -+mlxplat_pci_fpga_device_exit(struct pci_dev *pci_bridge, -+ void __iomem *pci_bridge_addr) -+{ -+ iounmap(pci_bridge_addr); -+ pci_release_regions(pci_bridge); -+ pci_disable_device(pci_bridge); -+} -+ -+static int -+mlxplat_pci_fpga_devices_init(struct resource **hotplug_resources, -+ unsigned int *hotplug_resources_size) -+{ -+ int err; -+ -+ err = mlxplat_pci_fpga_device_init(PCI_DEVICE_ID_LATTICE_LPC_BRIDGE, -+ "mlxplat_lpc_bridge", &lpc_bridge, -+ &mlxplat_mlxcpld_regmap_ctx.base); -+ if (err) -+ goto mlxplat_pci_fpga_device_init_lpc_fail; -+ -+ err = mlxplat_pci_fpga_device_init(PCI_DEVICE_ID_LATTICE_I2C_BRIDGE, -+ "mlxplat_i2c_bridge", &i2c_bridge, -+ &i2c_bridge_addr); -+ if (err) -+ goto mlxplat_pci_fpga_device_init_i2c_fail; -+ -+ err = mlxplat_pci_fpga_device_init(PCI_DEVICE_ID_LATTICE_JTAG_BRIDGE, -+ "mlxplat_jtag_bridge", &jtag_bridge, -+ &jtag_bridge_addr); -+ if (err) -+ goto mlxplat_pci_fpga_device_init_jtag_fail; -+ -+ return 0; -+ -+mlxplat_pci_fpga_device_init_jtag_fail: -+ mlxplat_pci_fpga_device_exit(i2c_bridge, i2c_bridge_addr); -+mlxplat_pci_fpga_device_init_i2c_fail: -+ mlxplat_pci_fpga_device_exit(lpc_bridge, mlxplat_mlxcpld_regmap_ctx.base); -+mlxplat_pci_fpga_device_init_lpc_fail: -+ return err; -+} -+ -+static void mlxplat_pci_fpga_devices_exit(void) -+{ -+ mlxplat_pci_fpga_device_exit(jtag_bridge, jtag_bridge_addr); -+ mlxplat_pci_fpga_device_exit(i2c_bridge, i2c_bridge_addr); -+ mlxplat_pci_fpga_device_exit(lpc_bridge, mlxplat_mlxcpld_regmap_ctx.base); -+} -+ - static int - mlxplat_pre_init(struct resource **hotplug_resources, unsigned int *hotplug_resources_size) - { -- return mlxplat_lpc_cpld_device_init(hotplug_resources, hotplug_resources_size); -+ int err; -+ -+ err = mlxplat_pci_fpga_devices_init(hotplug_resources, hotplug_resources_size); -+ if (err == -ENODEV) -+ return mlxplat_lpc_cpld_device_init(hotplug_resources, hotplug_resources_size); -+ -+ return err; - } - - static void mlxplat_post_exit(void) - { -- mlxplat_lpc_cpld_device_exit(); -+ if (lpc_bridge) -+ mlxplat_pci_fpga_devices_exit(); -+ else -+ mlxplat_lpc_cpld_device_exit(); - } - - static int mlxplat_post_init(struct mlxplat_priv *priv) -@@ -6366,6 +6493,9 @@ static int mlxplat_i2c_main_init(struct mlxplat_priv *priv) - mlxplat_i2c->regmap = priv->regmap; - mlxplat_i2c->handle = priv; - -+ /* Set mapped base address of I2C-LPC bridge over PCIe */ -+ if (lpc_bridge) -+ mlxplat_i2c->addr = i2c_bridge_addr; - priv->pdev_i2c = platform_device_register_resndata(&mlxplat_dev->dev, "i2c_mlxcpld", - nr, priv->hotplug_resources, - priv->hotplug_resources_size, --- -2.20.1 - diff --git a/patch/0029-platform-mellanox-mlxreg-hotplug-Extend-condition-fo.patch b/patch/0029-platform-mellanox-mlxreg-hotplug-Extend-condition-fo.patch deleted file mode 100644 index cb00d56a1..000000000 --- a/patch/0029-platform-mellanox-mlxreg-hotplug-Extend-condition-fo.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 4c391b315de93194876fb0a5a3faf6b02becf776 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 19 Mar 2023 15:04:26 +0000 -Subject: [PATH backport v6.1 29/32] platform/mellanox: mlxreg-hotplug: Extend - condition for notification callback processing - -Link: https://www.spinics.net/lists/platform-driver-x86/msg39646.html - -Allow processing of notification callback in routine -mlxreg_hotplug_device_create() in case hotplug object is configured -with action "MLXREG_HOTPLUG_DEVICE_NO_ACTION" in case no I2C parent bus -is specified. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/mellanox/mlxreg-hotplug.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/platform/mellanox/mlxreg-hotplug.c b/drivers/platform/mellanox/mlxreg-hotplug.c -index 117bc3f395fd..4936cf158ac8 100644 ---- a/drivers/platform/mellanox/mlxreg-hotplug.c -+++ b/drivers/platform/mellanox/mlxreg-hotplug.c -@@ -113,7 +113,7 @@ static int mlxreg_hotplug_device_create(struct mlxreg_hotplug_priv_data *priv, - * Return if adapter number is negative. It could be in case hotplug - * event is not associated with hotplug device. - */ -- if (data->hpdev.nr < 0) -+ if (data->hpdev.nr < 0 && data->hpdev.action != MLXREG_HOTPLUG_DEVICE_NO_ACTION) - return 0; - - pdata = dev_get_platdata(&priv->pdev->dev); --- -2.20.1 - diff --git a/patch/0030-platform-mellanox-nvsw-sn2201-change-fans-i2c-busses.patch b/patch/0030-platform-mellanox-nvsw-sn2201-change-fans-i2c-busses.patch deleted file mode 100644 index 87e7ea90d..000000000 --- a/patch/0030-platform-mellanox-nvsw-sn2201-change-fans-i2c-busses.patch +++ /dev/null @@ -1,69 +0,0 @@ -From ac10df67c019b8ee1c80b46390759669cd69862f Mon Sep 17 00:00:00 2001 -From: Michael Shych -Date: Wed, 12 Jul 2023 14:26:38 +0000 -Subject: [PATCH 2/4] platform: mellanox: nvsw-sn2201: change fans i2c busses. - -Link: https://www.spinics.net/lists/platform-driver-x86/msg39647.html - -Define the exact i2c bus (adapter number) of fans on the SN2201 system. -This will cause fan's EEPROMs be connected already from nvsw-sn2201 -platform driver and not from user space after receiving udev events. - -Signed-off-by: Michael Shych -Reviewed-by: Vadim Pasternak -Signed-off-by: Vadim Pasternak ---- - drivers/platform/mellanox/nvsw-sn2201.c | 12 ++++++++---- - 1 file changed, 8 insertions(+), 4 deletions(-) - -diff --git a/drivers/platform/mellanox/nvsw-sn2201.c b/drivers/platform/mellanox/nvsw-sn2201.c -index f53baf7e7..1a7c45aa4 100644 ---- a/drivers/platform/mellanox/nvsw-sn2201.c -+++ b/drivers/platform/mellanox/nvsw-sn2201.c -@@ -84,6 +84,10 @@ - #define NVSW_SN2201_MAIN_MUX_CH5_NR (NVSW_SN2201_MAIN_MUX_CH0_NR + 5) - #define NVSW_SN2201_MAIN_MUX_CH6_NR (NVSW_SN2201_MAIN_MUX_CH0_NR + 6) - #define NVSW_SN2201_MAIN_MUX_CH7_NR (NVSW_SN2201_MAIN_MUX_CH0_NR + 7) -+#define NVSW_SN2201_2ND_MUX_CH0_NR (NVSW_SN2201_MAIN_MUX_CH7_NR + 1) -+#define NVSW_SN2201_2ND_MUX_CH1_NR (NVSW_SN2201_MAIN_MUX_CH7_NR + 2) -+#define NVSW_SN2201_2ND_MUX_CH2_NR (NVSW_SN2201_MAIN_MUX_CH7_NR + 3) -+#define NVSW_SN2201_2ND_MUX_CH3_NR (NVSW_SN2201_MAIN_MUX_CH7_NR + 4) - - #define NVSW_SN2201_CPLD_NR NVSW_SN2201_MAIN_MUX_CH0_NR - #define NVSW_SN2201_NR_NONE -1 -@@ -425,28 +429,28 @@ static struct mlxreg_core_data nvsw_sn2201_fan_items_data[] = { - .reg = NVSW_SN2201_FAN_PRSNT_STATUS_OFFSET, - .mask = BIT(0), - .hpdev.brdinfo = &nvsw_sn2201_fan_devices[0], -- .hpdev.nr = NVSW_SN2201_NR_NONE, -+ .hpdev.nr = NVSW_SN2201_2ND_MUX_CH0_NR, - }, - { - .label = "fan2", - .reg = NVSW_SN2201_FAN_PRSNT_STATUS_OFFSET, - .mask = BIT(1), - .hpdev.brdinfo = &nvsw_sn2201_fan_devices[1], -- .hpdev.nr = NVSW_SN2201_NR_NONE, -+ .hpdev.nr = NVSW_SN2201_2ND_MUX_CH1_NR, - }, - { - .label = "fan3", - .reg = NVSW_SN2201_FAN_PRSNT_STATUS_OFFSET, - .mask = BIT(2), - .hpdev.brdinfo = &nvsw_sn2201_fan_devices[2], -- .hpdev.nr = NVSW_SN2201_NR_NONE, -+ .hpdev.nr = NVSW_SN2201_2ND_MUX_CH2_NR, - }, - { - .label = "fan4", - .reg = NVSW_SN2201_FAN_PRSNT_STATUS_OFFSET, - .mask = BIT(3), - .hpdev.brdinfo = &nvsw_sn2201_fan_devices[3], -- .hpdev.nr = NVSW_SN2201_NR_NONE, -+ .hpdev.nr = NVSW_SN2201_2ND_MUX_CH3_NR, - }, - }; - --- -2.20.1 - diff --git a/patch/0032-platform_data-mlxreg-Add-field-with-mapped-resource-.patch b/patch/0032-platform_data-mlxreg-Add-field-with-mapped-resource-.patch deleted file mode 100644 index 7ca1f6265..000000000 --- a/patch/0032-platform_data-mlxreg-Add-field-with-mapped-resource-.patch +++ /dev/null @@ -1,37 +0,0 @@ -From e24134a55160359b2763e42b650bf8473683627c Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 9 Nov 2022 09:43:28 +0200 -Subject: [PATCH backport 6.1.42 29/85] platform_data/mlxreg: Add field with - mapped resource address - -Add field with PCIe remapped based address for passing it across -relevant platform drivers sharing common system resources. - -Signed-off-by: Vadim Pasternak ---- - include/linux/platform_data/mlxreg.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_data/mlxreg.h -index a6bd74e29b6b..0b9f81a6f753 100644 ---- a/include/linux/platform_data/mlxreg.h -+++ b/include/linux/platform_data/mlxreg.h -@@ -216,6 +216,7 @@ struct mlxreg_core_platform_data { - * @mask_low: low aggregation interrupt common mask; - * @deferred_nr: I2C adapter number must be exist prior probing execution; - * @shift_nr: I2C adapter numbers must be incremented by this value; -+ * @addr: mapped resource address; - * @handle: handle to be passed by callback; - * @completion_notify: callback to notify when platform driver probing is done; - */ -@@ -230,6 +231,7 @@ struct mlxreg_core_hotplug_platform_data { - u32 mask_low; - int deferred_nr; - int shift_nr; -+ void __iomem *addr; - void *handle; - int (*completion_notify)(void *handle, int id); - }; --- -2.20.1 - diff --git a/patch/0033-i2c-mlxcpld-Allow-driver-to-run-on-ARM64-architectur.patch b/patch/0033-i2c-mlxcpld-Allow-driver-to-run-on-ARM64-architectur.patch deleted file mode 100644 index 14135321b..000000000 --- a/patch/0033-i2c-mlxcpld-Allow-driver-to-run-on-ARM64-architectur.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 836d88c01519a1a004e0c6138fb26a69a95e2ee8 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Mon, 7 Nov 2022 12:00:37 +0200 -Subject: [PATCH backport 6.1.42 33/85] i2c: mlxcpld: Allow driver to run on - ARM64 architecture - -Extend driver dependency by ARM64 architecture. - -Signed-off-by: Vadim Pasternak ---- - drivers/i2c/busses/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig -index e50f9603d189..9460528c0b1b 100644 ---- a/drivers/i2c/busses/Kconfig -+++ b/drivers/i2c/busses/Kconfig -@@ -1363,7 +1363,7 @@ config I2C_ICY - - config I2C_MLXCPLD - tristate "Mellanox I2C driver" -- depends on X86_64 || COMPILE_TEST -+ depends on X86_64 || ARM64 || COMPILE_TEST - help - This exposes the Mellanox platform I2C busses to the linux I2C layer - for X86 based systems. --- -2.20.1 - diff --git a/patch/0034-i2c-mlxcpld-Add-support-for-extended-transaction-len.patch b/patch/0034-i2c-mlxcpld-Add-support-for-extended-transaction-len.patch deleted file mode 100644 index 268cf56a0..000000000 --- a/patch/0034-i2c-mlxcpld-Add-support-for-extended-transaction-len.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 4b25a65a3e3b1ad6f2773295d3d749a7ae2c71a4 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Mon, 24 Jul 2023 12:48:08 +0000 -Subject: [PATCH backport 6.1.42 34/85] i2c: mlxcpld: Add support for extended - transaction length for i2c-mlxcpld - -Add support for extended length of read and write transactions. -New FPGA logic allows to increase size of the read and write -transactions length. This feature is verified through capability -register 'CPBLTY_REG'. Two bits 5 and 6 of the register are used for -length capability detection. Value '10' indicates support of extended -transaction length - 128 bytes for read transactions and 132 for write -transactions. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/i2c/busses/i2c-mlxcpld.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/drivers/i2c/busses/i2c-mlxcpld.c b/drivers/i2c/busses/i2c-mlxcpld.c -index 081f51ef0551..14a63d5e1cdd 100644 ---- a/drivers/i2c/busses/i2c-mlxcpld.c -+++ b/drivers/i2c/busses/i2c-mlxcpld.c -@@ -22,6 +22,7 @@ - #define MLXCPLD_I2C_BUS_NUM 1 - #define MLXCPLD_I2C_DATA_REG_SZ 36 - #define MLXCPLD_I2C_DATA_SZ_BIT BIT(5) -+#define MLXCPLD_I2C_DATA_EXT2_SZ_BIT BIT(6) - #define MLXCPLD_I2C_DATA_SZ_MASK GENMASK(6, 5) - #define MLXCPLD_I2C_SMBUS_BLK_BIT BIT(7) - #define MLXCPLD_I2C_MAX_ADDR_LEN 4 -@@ -466,6 +467,13 @@ static const struct i2c_adapter_quirks mlxcpld_i2c_quirks_ext = { - .max_comb_1st_msg_len = 4, - }; - -+static const struct i2c_adapter_quirks mlxcpld_i2c_quirks_ext2 = { -+ .flags = I2C_AQ_COMB_WRITE_THEN_READ, -+ .max_read_len = (MLXCPLD_I2C_DATA_REG_SZ - 4) * 4, -+ .max_write_len = (MLXCPLD_I2C_DATA_REG_SZ - 4) * 4 + MLXCPLD_I2C_MAX_ADDR_LEN, -+ .max_comb_1st_msg_len = 4, -+}; -+ - static struct i2c_adapter mlxcpld_i2c_adapter = { - .owner = THIS_MODULE, - .name = "i2c-mlxcpld", -@@ -547,6 +555,8 @@ static int mlxcpld_i2c_probe(struct platform_device *pdev) - /* Check support for extended transaction length */ - if ((val & MLXCPLD_I2C_DATA_SZ_MASK) == MLXCPLD_I2C_DATA_SZ_BIT) - mlxcpld_i2c_adapter.quirks = &mlxcpld_i2c_quirks_ext; -+ else if ((val & MLXCPLD_I2C_DATA_SZ_MASK) == MLXCPLD_I2C_DATA_EXT2_SZ_BIT) -+ mlxcpld_i2c_adapter.quirks = &mlxcpld_i2c_quirks_ext2; - /* Check support for smbus block transaction */ - if (val & MLXCPLD_I2C_SMBUS_BLK_BIT) - priv->smbus_block = true; --- -2.20.1 - diff --git a/patch/0039-mlxsw-reg-Limit-MTBR-register-payload-to-a-single-da.patch b/patch/0039-mlxsw-reg-Limit-MTBR-register-payload-to-a-single-da.patch deleted file mode 100644 index dd5ff2ae4..000000000 --- a/patch/0039-mlxsw-reg-Limit-MTBR-register-payload-to-a-single-da.patch +++ /dev/null @@ -1,80 +0,0 @@ -From 692437ce4ead73e449b3f75688de24462665b592 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 16 Aug 2023 16:32:29 +0000 -Subject: [PATH backport v6.1 39/41] mlxsw: reg: Limit MTBR register payload to - a single data record - -Link: https://github.com/jpirko/linux_mlxsw/commit/b7dcef023af55d2385c9ab1869f937769dffdb35 - -The MTBR register is used to read temperatures from multiple sensors in -one transaction, but the driver only reads from a single sensor in each -transaction. - -Rrestrict the payload size of the MTBR register to prevent the -transmission of redundant data to the firmware. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Ido Schimmel ---- - drivers/net/ethernet/mellanox/mlxsw/core_env.c | 2 +- - drivers/net/ethernet/mellanox/mlxsw/core_hwmon.c | 2 +- - drivers/net/ethernet/mellanox/mlxsw/reg.h | 6 +++--- - 3 files changed, 5 insertions(+), 5 deletions(-) - -diff --git a/drivers/net/ethernet/mellanox/mlxsw/core_env.c b/drivers/net/ethernet/mellanox/mlxsw/core_env.c -index 0107cbc32fc7..550475a108ef 100644 ---- a/drivers/net/ethernet/mellanox/mlxsw/core_env.c -+++ b/drivers/net/ethernet/mellanox/mlxsw/core_env.c -@@ -777,7 +777,7 @@ static int mlxsw_env_module_has_temp_sensor(struct mlxsw_core *mlxsw_core, - int err; - - mlxsw_reg_mtbr_pack(mtbr_pl, slot_index, -- MLXSW_REG_MTBR_BASE_MODULE_INDEX + module, 1); -+ MLXSW_REG_MTBR_BASE_MODULE_INDEX + module); - err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mtbr), mtbr_pl); - if (err) - return err; -diff --git a/drivers/net/ethernet/mellanox/mlxsw/core_hwmon.c b/drivers/net/ethernet/mellanox/mlxsw/core_hwmon.c -index 0fd290d776ff..9c12e1feb643 100644 ---- a/drivers/net/ethernet/mellanox/mlxsw/core_hwmon.c -+++ b/drivers/net/ethernet/mellanox/mlxsw/core_hwmon.c -@@ -293,7 +293,7 @@ static ssize_t mlxsw_hwmon_module_temp_fault_show(struct device *dev, - - module = mlxsw_hwmon_attr->type_index - mlxsw_hwmon_dev->sensor_count; - mlxsw_reg_mtbr_pack(mtbr_pl, mlxsw_hwmon_dev->slot_index, -- MLXSW_REG_MTBR_BASE_MODULE_INDEX + module, 1); -+ MLXSW_REG_MTBR_BASE_MODULE_INDEX + module); - err = mlxsw_reg_query(mlxsw_hwmon->core, MLXSW_REG(mtbr), mtbr_pl); - if (err) { - dev_err(dev, "Failed to query module temperature sensor\n"); -diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h -index 0777bed5bb1a..9f8fb567b432 100644 ---- a/drivers/net/ethernet/mellanox/mlxsw/reg.h -+++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h -@@ -9453,7 +9453,7 @@ MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1); - #define MLXSW_REG_MTBR_ID 0x900F - #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ - #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ --#define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ -+#define MLXSW_REG_MTBR_REC_MAX_COUNT 1 - #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ - MLXSW_REG_MTBR_REC_LEN * \ - MLXSW_REG_MTBR_REC_MAX_COUNT) -@@ -9499,12 +9499,12 @@ MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, - MLXSW_REG_MTBR_REC_LEN, 0x00, false); - - static inline void mlxsw_reg_mtbr_pack(char *payload, u8 slot_index, -- u16 base_sensor_index, u8 num_rec) -+ u16 base_sensor_index) - { - MLXSW_REG_ZERO(mtbr, payload); - mlxsw_reg_mtbr_slot_index_set(payload, slot_index); - mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); -- mlxsw_reg_mtbr_num_rec_set(payload, num_rec); -+ mlxsw_reg_mtbr_num_rec_set(payload, 1); - } - - /* Error codes from temperatute reading */ --- -2.20.1 - diff --git a/patch/0040-mlxsw-core-Extend-allowed-list-of-external-cooling-d.patch b/patch/0040-mlxsw-core-Extend-allowed-list-of-external-cooling-d.patch deleted file mode 100644 index 8e7586ac1..000000000 --- a/patch/0040-mlxsw-core-Extend-allowed-list-of-external-cooling-d.patch +++ /dev/null @@ -1,37 +0,0 @@ -From b5df3db752ef8f40d75e14e49099c9c0be34c550 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 16 Aug 2023 16:32:30 +0000 -Subject: [PATH backport v6.1 40/41] mlxsw: core: Extend allowed list of - external cooling devices for thermal zone binding - -Link: https://github.com/jpirko/linux_mlxsw/commit/667f898094e6cf623cc5234dbda6a684321b80a4 - -Extend the list of allowed external cooling devices for thermal zone -binding to include devices of type "emc2305". - -The motivation is to provide support for the system SN2201, which is -equipped with the Spectrum-1 ASIC. -The system's airflow control is managed by the EMC2305 RPM-based PWM -Fan Speed Controller as the cooling device. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Ido Schimmel ---- - drivers/net/ethernet/mellanox/mlxsw/core_thermal.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/net/ethernet/mellanox/mlxsw/core_thermal.c b/drivers/net/ethernet/mellanox/mlxsw/core_thermal.c -index ef5e61708df3..d0620344da68 100644 ---- a/drivers/net/ethernet/mellanox/mlxsw/core_thermal.c -+++ b/drivers/net/ethernet/mellanox/mlxsw/core_thermal.c -@@ -28,6 +28,7 @@ - /* External cooling devices, allowed for binding to mlxsw thermal zones. */ - static char * const mlxsw_thermal_external_allowed_cdev[] = { - "mlxreg_fan", -+ "emc2305", - }; - - enum mlxsw_thermal_trips { --- -2.20.1 - diff --git a/patch/0041-mlxsw-i2c-Utilize-standard-macros-for-dividing-buffe.patch b/patch/0041-mlxsw-i2c-Utilize-standard-macros-for-dividing-buffe.patch deleted file mode 100644 index b5efc0b87..000000000 --- a/patch/0041-mlxsw-i2c-Utilize-standard-macros-for-dividing-buffe.patch +++ /dev/null @@ -1,35 +0,0 @@ -From a097327af0b5392d49fe9085fd041ca78b88d3d6 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 16 Aug 2023 16:32:31 +0000 -Subject: [PATH backport v6.1 41/41] mlxsw: i2c: Utilize standard macros for - dividing buffer into chunks - -Link: https://github.com/jpirko/linux_mlxsw/commit/da27e5f14b284ae5e3730df19971618725671dd7 - -Use standard macro DIV_ROUND_UP() to determine the number of chunks -required for a given buffer. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Ido Schimmel ---- - drivers/net/ethernet/mellanox/mlxsw/i2c.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - -diff --git a/drivers/net/ethernet/mellanox/mlxsw/i2c.c b/drivers/net/ethernet/mellanox/mlxsw/i2c.c -index d9a71ad9adae..8eb32152ee04 100644 ---- a/drivers/net/ethernet/mellanox/mlxsw/i2c.c -+++ b/drivers/net/ethernet/mellanox/mlxsw/i2c.c -@@ -424,9 +424,7 @@ mlxsw_i2c_cmd(struct device *dev, u16 opcode, u32 in_mod, size_t in_mbox_size, - - if (in_mbox) { - reg_size = mlxsw_i2c_get_reg_size(in_mbox); -- num = reg_size / mlxsw_i2c->block_size; -- if (reg_size % mlxsw_i2c->block_size) -- num++; -+ num = DIV_ROUND_UP(reg_size, mlxsw_i2c->block_size); - - if (mutex_lock_interruptible(&mlxsw_i2c->cmd.lock) < 0) { - dev_err(&client->dev, "Could not acquire lock"); --- -2.20.1 - diff --git a/patch/0043-hwmon-mlxreg-fan-Extend-number-of-supporetd-fans.patch b/patch/0043-hwmon-mlxreg-fan-Extend-number-of-supporetd-fans.patch deleted file mode 100644 index 115e5f406..000000000 --- a/patch/0043-hwmon-mlxreg-fan-Extend-number-of-supporetd-fans.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 8769d44cd9dab3e8e6f539956a40eb041f479fef Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 23 Jul 2023 06:49:01 +0000 -Subject: [PATCH v6.1 24/80] hwmon: (mlxreg-fan) Extend number of supporetd - fans - -Some new big modular systems can be equipped with up to 24 fans. -Extend maximum number of fans accordingly. - -Signed-off-by: Vadim Pasternak ---- - drivers/hwmon/mlxreg-fan.c | 12 +++++++++++- - 1 file changed, 11 insertions(+), 1 deletion(-) - -diff --git a/drivers/hwmon/mlxreg-fan.c b/drivers/hwmon/mlxreg-fan.c -index 342ff355e925..bddc927b207c 100644 ---- a/drivers/hwmon/mlxreg-fan.c -+++ b/drivers/hwmon/mlxreg-fan.c -@@ -12,7 +12,7 @@ - #include - #include - --#define MLXREG_FAN_MAX_TACHO 14 -+#define MLXREG_FAN_MAX_TACHO 24 - #define MLXREG_FAN_MAX_PWM 4 - #define MLXREG_FAN_PWM_NOT_CONNECTED 0xff - #define MLXREG_FAN_MAX_STATE 10 -@@ -304,6 +304,16 @@ static const struct hwmon_channel_info *mlxreg_fan_hwmon_info[] = { - HWMON_F_INPUT | HWMON_F_FAULT, - HWMON_F_INPUT | HWMON_F_FAULT, - HWMON_F_INPUT | HWMON_F_FAULT, -+ HWMON_F_INPUT | HWMON_F_FAULT, -+ HWMON_F_INPUT | HWMON_F_FAULT, -+ HWMON_F_INPUT | HWMON_F_FAULT, -+ HWMON_F_INPUT | HWMON_F_FAULT, -+ HWMON_F_INPUT | HWMON_F_FAULT, -+ HWMON_F_INPUT | HWMON_F_FAULT, -+ HWMON_F_INPUT | HWMON_F_FAULT, -+ HWMON_F_INPUT | HWMON_F_FAULT, -+ HWMON_F_INPUT | HWMON_F_FAULT, -+ HWMON_F_INPUT | HWMON_F_FAULT, - HWMON_F_INPUT | HWMON_F_FAULT), - HWMON_CHANNEL_INFO(pwm, - HWMON_PWM_INPUT, --- -2.20.1 - diff --git a/patch/0048-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2891-c.patch b/patch/0048-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2891-c.patch deleted file mode 100644 index 6cc2c505b..000000000 --- a/patch/0048-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2891-c.patch +++ /dev/null @@ -1,637 +0,0 @@ -From b45f52995f0108302bd25a143b82161d5053b74e Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Thu, 13 Jul 2023 06:16:53 +0000 -Subject: [PATCH v6.1 20/70] hwmon: (pmbus) Add support for MPS Multi-phase - mp2891 controller -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Introduce driver for dual-loop, digital, multi-phase controller MP2891 from -Monolithic Power Systems, Inc. (MPS) vendor. - -The MP2891 can work with MPS’s Intelli-PhaseTM products to complete the -multi-phase voltage regulator (VR) solution with minimal external -components. - -This device supports: -- Two power rails. -- Programmable Multi-Phase up to 16 Phases on rail 1, and a maximum of 8 - phases on rail 2. - -Signed-off-by: Vadim Pasternak ---- - Documentation/hwmon/mp2891.rst | 128 ++++++++++ - drivers/hwmon/pmbus/Kconfig | 9 + - drivers/hwmon/pmbus/Makefile | 1 + - drivers/hwmon/pmbus/mp2891.c | 431 +++++++++++++++++++++++++++++++++ - 4 files changed, 569 insertions(+) - create mode 100644 Documentation/hwmon/mp2891.rst - create mode 100644 drivers/hwmon/pmbus/mp2891.c - -diff --git a/Documentation/hwmon/mp2891.rst b/Documentation/hwmon/mp2891.rst -new file mode 100644 -index 000000000..c4bda3d7e ---- /dev/null -+++ b/Documentation/hwmon/mp2891.rst -@@ -0,0 +1,128 @@ -+.. SPDX-License-Identifier: GPL-2.0 -+ -+Kernel driver mp2891 -+==================== -+ -+Supported chips: -+ -+ * MPS MP2891 -+ -+ Prefix: 'mp2891' -+ -+Author: -+ -+ Vadim Pasternak -+ -+Description -+----------- -+ -+This driver implements support for Monolithic Power Systems, Inc. (MPS) -+vendor dual-loop, digital, multi-phase controller MP2891. -+The MP2891 can work with MPS’s Intelli-PhaseTM products to complete the -+multi-phase voltage regulator (VR) solution with minimal external components. -+ -+MP2891 is available in a QFN-56 (7mmx7mm) package. -+ -+This device supports: -+ -+- Two power rails. -+- Programmable Multi-Phase up to 16 Phases on rail 1, and a maximum of 8 phases -+ on rail 2. -+- PWM-VID Interface. -+- Two pages for telemetry. -+- Programmable pins for PMBus Address. -+- Ability to store and restore device configurations. -+- 200kHz to 3MHz Switching Frequency. -+- Automatic Loop Compensation. -+- Couple Inductor Mode. -+- Supports Multi-Configuration for 6 Different Applications. -+- Flexible Pulse-Width Modulation (PWM) Assignment for 2 Rails. -+- Automatic Phase-Shedding (APS) to Improve Overall Efficiency. -+- Phase-to-Phase Active Current Balancing with Configurable Offsets for Thermal -+ Balance. -+- Digital Load-Line Regulation. -+- Overclocking Mode by Adding Offset to VOUT. -+ -+Device complaint with: -+ -+- PMBus rev 1.3 interface. -+ -+Device supports direct format for reading output current, output voltage, -+input and output power and temperature. -+Device supports linear format for reading input voltage and input power. -+ -+The driver provides the next attributes for the current: -+ -+- for current out input and maximum alarm; -+- for phase current: input and label. -+ -+The driver exports the following attributes via the 'sysfs' files, where: -+ -+- 'n' is number of configured phases (from 1 to 10); -+- index 1 for "iout"; -+- indexes 2 ... 1 + n for phases. -+ -+**curr[1-{1+n}]_input** -+ -+**curr[1-{1+n}]_label** -+ -+**curr1_max** -+ -+**curr1_max_alarm** -+ -+The driver provides the next attributes for the voltage: -+ -+- for voltage in: input, low and high critical thresholds, low and high -+ critical alarms; -+- for voltage out: input and high alarm; -+ -+The driver exports the following attributes via the 'sysfs' files, where -+ -+**in1_crit** -+ -+**in1_crit_alarm** -+ -+**in1_input** -+ -+**in1_label** -+ -+**in1_min** -+ -+**in1_min_alarm** -+ -+**in2_alarm** -+ -+**in2_input** -+ -+**in2_label** -+ -+The driver provides the next attributes for the power: -+ -+- for power in alarm and input. -+- for power out: cap, cap alarm an input. -+ -+The driver exports the following attributes via the 'sysfs' files, where -+- indexes 1 for "pin"; -+- indexes 2 for "pout"; -+ -+**power1_alarm** -+ -+**power1_input** -+ -+**power1_label** -+ -+**power2_input** -+ -+**power2_label** -+ -+**power2_max** -+ -+**power2_max_alarm** -+ -+The driver provides the next attributes for the temperature: -+ -+**temp1_input** -+ -+**temp1_max** -+ -+**temp1_max_alarm** -diff --git a/drivers/hwmon/pmbus/Kconfig b/drivers/hwmon/pmbus/Kconfig -index 89668af67..77d67344c 100644 ---- a/drivers/hwmon/pmbus/Kconfig -+++ b/drivers/hwmon/pmbus/Kconfig -@@ -299,6 +299,15 @@ config SENSORS_MP2888 - This driver can also be built as a module. If so, the module will - be called mp2888. - -+config SENSORS_MP2891 -+ tristate "MPS MP2891" -+ help -+ If you say yes here you get hardware monitoring support for MPS -+ MP2891 Dual Loop Digital Multi-Phase Controller. -+ -+ This driver can also be built as a module. If so, the module will -+ be called mp2891. -+ - config SENSORS_MP2975 - tristate "MPS MP2975" - help -diff --git a/drivers/hwmon/pmbus/Makefile b/drivers/hwmon/pmbus/Makefile -index 0002dbe22..8e767d7b8 100644 ---- a/drivers/hwmon/pmbus/Makefile -+++ b/drivers/hwmon/pmbus/Makefile -@@ -32,6 +32,7 @@ obj-$(CONFIG_SENSORS_MAX31785) += max31785.o - obj-$(CONFIG_SENSORS_MAX34440) += max34440.o - obj-$(CONFIG_SENSORS_MAX8688) += max8688.o - obj-$(CONFIG_SENSORS_MP2888) += mp2888.o -+obj-$(CONFIG_SENSORS_MP2891) += mp2891.o - obj-$(CONFIG_SENSORS_MP2975) += mp2975.o - obj-$(CONFIG_SENSORS_MP5023) += mp5023.o - obj-$(CONFIG_SENSORS_PLI1209BC) += pli1209bc.o -diff --git a/drivers/hwmon/pmbus/mp2891.c b/drivers/hwmon/pmbus/mp2891.c -new file mode 100644 -index 000000000..522c0bb5f ---- /dev/null -+++ b/drivers/hwmon/pmbus/mp2891.c -@@ -0,0 +1,431 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers(MP2891) -+ * -+ * Copyright (C) 2023 Nvidia -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include "pmbus.h" -+ -+/* -+ * Vendor specific registers. -+ * Note: command PMBUS_READ_DUTY_CYCLE (0x94) is re-purposed for reading input power. -+ * command PMBUS_READ_FREQUENCY (0x95) is re-purposed for reading input current. -+ */ -+#define MP2891_PMBUS_VOUT_MIN 0x2b -+#define MP2891_VOUT_OV_FAULT_LIMIT_R1 0x40 -+#define MP2891_VOUT_UV_FAULT_LIMIT_R1 0x44 -+#define MP2891_MFR_IIN_RPT_EST 0x53 -+#define MP2891_MFR_IIN_TUNE_GAIN_EST 0x54 -+#define MP2891_MFR_SVI3_IOUT_PRT 0x65 -+#define MP2891_MFR_READ_PIN_EST 0x94 -+#define MP2891_MFR_READ_IIN_EST 0x95 -+#define MP2891_MFR_VOUT_LOOP_CTRL 0xbd -+ -+#define MP2891_MFR_OVUV_DIV2_R1 BIT(13) -+#define MP2891_MFR_OVP_REF_SEL_R1 BIT(12) -+#define MP2891_MFR_OVP_DELTA_R1 GENAMSK(11, 8) -+#define MP2891_MFR_OVP_ABS_LIMIT_R1 GENMASK(8, 0) -+#define MP2891_MFR_OVP_DELTA_DEFAULT 500 -+#define MP2891_MFR_UVP_REF_SEL_R1 BIT(12) -+#define MP2891_MFR_UVP_DELTA_R1 GENAMSK(11, 8) -+#define MP2891_MFR_UVP_ABS_LIMIT_R1 GENMASK(8, 0) -+#define MP2891_MFR_UVP_OFFSET_DEFAULT (-5000) -+#define MP2891_MFR_OVP_OFFSET_DEFAULT 5000 -+ -+#define MP2891_MFR_OVP_UVP_OFFSET_GET(ret, off) \ -+ (((((ret) & GENMASK(11, 8)) >> 8) + 1) * (off)) -+ -+#define MP2891_VID_STEP_POS 14 -+#define MP2891_VID_STEP_MASK GENMASK(MP2891_VID_STEP_POS + 1, MP2891_VID_STEP_POS) -+#define MP2891_DAC_2P5MV_MASK BIT(13) -+#define MP2891_IOUT_SCALE_MASK GENMASK(2, 0) -+ -+#define MP2975_IIN_OC_WARN_LIMIT_UNIT 2 -+#define MP2975_IOUT_OC_LIMIT_UNIT 4 -+#define MP2975_PIN_LIMIT_UNIT 2 -+#define MP2975_VIN_UNIT 32 -+#define MP2975_IOUT_UC_LIMIT_SCALE 124 -+#define MP2975_IOUT_UC_LIMIT_UNIT 25600 -+#define MP2975_TEMP_LIMIT_OFFSET 40 -+ -+#define MP2891_PAGE_NUM 2 -+ -+#define MP2891_RAIL1_FUNC (PMBUS_HAVE_VIN | PMBUS_HAVE_VOUT | PMBUS_HAVE_IOUT | \ -+ PMBUS_HAVE_IIN | PMBUS_HAVE_TEMP | PMBUS_HAVE_POUT | \ -+ PMBUS_HAVE_PIN) -+ -+#define MP2891_RAIL2_FUNC (PMBUS_HAVE_VOUT | PMBUS_HAVE_IOUT | PMBUS_HAVE_IIN | \ -+ PMBUS_HAVE_TEMP | PMBUS_HAVE_POUT) -+ -+struct mp2891_data { -+ struct pmbus_driver_info info; -+ int vid_step[MP2891_PAGE_NUM]; -+ int vid_ref[MP2891_PAGE_NUM]; -+ int iout_scale[MP2891_PAGE_NUM]; -+}; -+ -+#define to_mp2891_data(x) container_of(x, struct mp2891_data, info) -+ -+static int mp2891_read_vout(struct i2c_client *client, int page, int phase, int reg) -+{ -+ const struct pmbus_driver_info *info = pmbus_get_driver_info(client); -+ struct mp2891_data *data = to_mp2891_data(info); -+ int ret; -+ -+ ret = pmbus_read_word_data(client, page, phase, reg); -+ -+ return ret < 0 ? ret : ret * data->vid_step[page] / 100; -+} -+ -+static int mp2891_read_byte_data(struct i2c_client *client, int page, int reg) -+{ -+ int ret; -+ -+ switch (reg) { -+ case PMBUS_VOUT_MODE: -+ /* -+ * Enforce VOUT direct format, since device allows to set the -+ * different formats for the different rails. Conversion from -+ * VID to direct provided by driver internally, in case it is -+ * necessary. -+ */ -+ ret = PB_VOUT_MODE_DIRECT; -+ break; -+ default: -+ ret = -EINVAL; -+ break; -+ } -+ -+ return ret; -+} -+ -+static int mp2891_read_word_data(struct i2c_client *client, int page, int phase, int reg) -+{ -+ const struct pmbus_driver_info *info = pmbus_get_driver_info(client); -+ struct mp2891_data *data = to_mp2891_data(info); -+ int ret; -+ -+ switch (reg) { -+ case PMBUS_READ_VOUT: -+ return mp2891_read_vout(client, page, phase, reg); -+ case PMBUS_READ_VIN: -+ ret = pmbus_read_word_data(client, page, phase, reg); -+ if (ret <= 0) -+ return ret; -+ -+ /* -+ * READ_VIN register contains bits 15:11 set with the fixed value 11011b, bit 10 -+ * is set with 0. Bits 9:0 provides input voltage in linear11 format, scaled as -+ * 1/32V/LSB. -+ */ -+ return DIV_ROUND_CLOSEST(((ret & GENMASK(9, 0)) * 1000), MP2975_VIN_UNIT); -+ case PMBUS_OT_WARN_LIMIT: -+ case PMBUS_OT_FAULT_LIMIT: -+ return (pmbus_read_word_data(client, page, phase, reg) & GENMASK(7, 0)) - -+ MP2975_TEMP_LIMIT_OFFSET; -+ case PMBUS_VIN_OV_FAULT_LIMIT: -+ ret = pmbus_read_word_data(client, page, phase, reg); -+ if (ret <= 0) -+ return ret; -+ return DIV_ROUND_CLOSEST(ret & GENMASK(7, 0), 8) * 1000; -+ case PMBUS_VOUT_UV_FAULT_LIMIT: -+ ret = pmbus_read_word_data(client, page, phase, MP2891_PMBUS_VOUT_MIN); -+ if (ret <= 0) -+ return ret; -+ ret = (ret & GENMASK(10, 0)) * data->vid_step[page]; -+ return DIV_ROUND_CLOSEST(ret, 100); -+ case PMBUS_VOUT_OV_FAULT_LIMIT: -+ ret = pmbus_read_word_data(client, page, phase, PMBUS_VOUT_MAX); -+ if (ret <= 0) -+ return ret; -+ ret = (ret & GENMASK(10, 0)) * data->vid_step[page]; -+ return DIV_ROUND_CLOSEST(ret, 100); -+ case PMBUS_IOUT_UC_FAULT_LIMIT: -+ ret = pmbus_read_word_data(client, page, phase, reg); -+ return ret <= 0 ? ret : DIV_ROUND_CLOSEST((ret & GENMASK(7, 0)) * -+ MP2975_IOUT_UC_LIMIT_SCALE, -+ MP2975_IOUT_UC_LIMIT_UNIT); -+ return ret; -+ case PMBUS_READ_PIN: -+ /* -+ * From some unknown reason the vendor decide to re-purpose command -+ * PMBUS_READ_DUTY_CYCLE (0x94) for reading input and output power. -+ */ -+ return pmbus_read_word_data(client, page, phase, MP2891_MFR_READ_PIN_EST); -+ case PMBUS_READ_POUT: -+ return pmbus_read_word_data(client, page, phase, reg); -+ case PMBUS_READ_IIN: -+ /* -+ * From some unknown reason the vendor decide to re-purpose command -+ * PMBUS_READ_FREQUENCY (0x95) for reading input current. -+ */ -+ return pmbus_read_word_data(client, page, phase, MP2891_MFR_READ_IIN_EST); -+ case PMBUS_IIN_OC_WARN_LIMIT: -+ /* Read only from page 0. */ -+ ret = pmbus_read_word_data(client, 0, phase, reg); -+ return ret <= 0 ? ret : DIV_ROUND_CLOSEST(ret, MP2975_IIN_OC_WARN_LIMIT_UNIT); -+ case PMBUS_PIN_OP_WARN_LIMIT: -+ ret = pmbus_read_word_data(client, page, phase, reg); -+ return ret <= 0 ? ret : ret * MP2975_PIN_LIMIT_UNIT; -+ case PMBUS_IOUT_OC_WARN_LIMIT: -+ case PMBUS_IOUT_OC_FAULT_LIMIT: -+ ret = pmbus_read_word_data(client, page, phase, reg); -+ return ret <= 0 ? ret : DIV_ROUND_CLOSEST(ret * data->iout_scale[page], -+ MP2975_IOUT_OC_LIMIT_UNIT); -+ case PMBUS_UT_WARN_LIMIT: -+ case PMBUS_UT_FAULT_LIMIT: -+ case PMBUS_VIN_OV_WARN_LIMIT: -+ case PMBUS_VIN_UV_WARN_LIMIT: -+ case PMBUS_VOUT_OV_WARN_LIMIT: -+ case PMBUS_VOUT_UV_WARN_LIMIT: -+ case PMBUS_POUT_OP_WARN_LIMIT: -+ case PMBUS_IIN_OC_FAULT_LIMIT: -+ case PMBUS_POUT_MAX: -+ case PMBUS_POUT_OP_FAULT_LIMIT: -+ case PMBUS_MFR_VIN_MIN: -+ case PMBUS_MFR_VOUT_MIN: -+ case PMBUS_MFR_VIN_MAX: -+ case PMBUS_MFR_VOUT_MAX: -+ case PMBUS_MFR_IIN_MAX: -+ case PMBUS_MFR_IOUT_MAX: -+ case PMBUS_MFR_PIN_MAX: -+ case PMBUS_MFR_POUT_MAX: -+ case PMBUS_MFR_MAX_TEMP_1: -+ return -ENXIO; -+ default: -+ return -ENODATA; -+ } -+} -+ -+static int mp2891_write_word_data(struct i2c_client *client, int page, int reg, u16 word) -+{ -+ switch (reg) { -+ case PMBUS_OT_FAULT_LIMIT: -+ case PMBUS_OT_WARN_LIMIT: -+ /* Drop unused bits 15:8. */ -+ word = clamp_val(word, 0, GENMASK(7, 0)); -+ break; -+ case PMBUS_IOUT_OC_WARN_LIMIT: -+ case PMBUS_POUT_OP_WARN_LIMIT: -+ case PMBUS_IIN_OC_WARN_LIMIT: -+ /* Drop unused bits 15:10. */ -+ word = clamp_val(word, 0, GENMASK(9, 0)); -+ break; -+ default: -+ return -ENODATA; -+ } -+ return pmbus_write_word_data(client, page, reg, word); -+} -+ -+static int -+mp2891_git_vid_volt_ref(struct i2c_client *client, struct mp2891_data *data, int page) -+{ -+ int ret; -+ -+ ret = i2c_smbus_read_word_data(client, PMBUS_VOUT_COMMAND); -+ if (ret < 0) -+ return ret; -+ -+ data->vid_ref[page] = (ret & GENMASK(10, 0)) * data->vid_step[page]; -+ -+ return 0; -+} -+ -+static int mp2891_identify_vid(struct i2c_client *client, struct mp2891_data *data, u32 reg, -+ int page) -+{ -+ int ret; -+ -+ ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, page); -+ if (ret < 0) -+ return ret; -+ -+ ret = i2c_smbus_read_word_data(client, reg); -+ if (ret < 0) -+ return ret; -+ -+ /* -+ * Obtain vid_step from MP2891_MFR_VOUT_LOOP_CTRL register: -+ * bit 13 = 1, the vid_step is below 2.5mV/LSB; -+ * bit 13 = 0, the vid_step is defined by bits 15:14: -+ * 00b - 6.25mV/LSB, 01b - 5mV/LSB, 10b - 2mV/LSB, 11b - 1mV -+ */ -+ if (ret & MP2891_DAC_2P5MV_MASK) { -+ data->vid_step[page] = 250; -+ return mp2891_git_vid_volt_ref(client, data, page); -+ } -+ -+ switch ((ret & MP2891_VID_STEP_MASK) >> MP2891_VID_STEP_POS) { -+ case 1: -+ data->vid_step[page] = 500; -+ break; -+ case 2: -+ data->vid_step[page] = 200; -+ break; -+ case 3: -+ data->vid_step[page] = 100; -+ break; -+ default: -+ data->vid_step[page] = 250; -+ break; -+ } -+ -+ return mp2891_git_vid_volt_ref(client, data, page); -+} -+ -+static int mp2891_identify_rails_vid(struct i2c_client *client, struct mp2891_data *data) -+{ -+ int ret; -+ -+ /* Identify vid_step for rail 1. */ -+ ret = mp2891_identify_vid(client, data, MP2891_MFR_VOUT_LOOP_CTRL, 0); -+ if (ret < 0) -+ return ret; -+ -+ /* Identify vid_step for rail 2. */ -+ return mp2891_identify_vid(client, data, MP2891_MFR_VOUT_LOOP_CTRL, 1); -+} -+ -+static int -+mp2891_iout_scale_get(struct i2c_client *client, struct mp2891_data *data, u32 reg, int page) -+{ -+ int ret; -+ -+ ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, page); -+ if (ret < 0) -+ return ret; -+ -+ ret = i2c_smbus_read_word_data(client, reg); -+ if (ret < 0) -+ return ret; -+ -+ /* -+ * Obtain iout_scale from the register MP2891_MFR_SVI3_IOUT_PRT, bits 2-0. -+ * The value is selected as below: -+ * 000b - 1A/LSB, 001b - (1/32)A/LSB, 010b - (1/16)A/LSB, -+ * 011b - (1/8)A/LSB, 100b - (1/4)A/LSB, 101b - (1/2)A/LSB -+ * 110b - 1A/LSB, 111b - 2A/LSB -+ */ -+ switch (ret & MP2891_IOUT_SCALE_MASK) { -+ case 0: -+ case 6: -+ data->iout_scale[page] = 32; -+ return 0; -+ case 1: -+ data->iout_scale[page] = 1; -+ return 0; -+ case 2: -+ data->iout_scale[page] = 2; -+ return 0; -+ case 3: -+ data->iout_scale[page] = 4; -+ return 0; -+ case 4: -+ data->iout_scale[page] = 8; -+ return 0; -+ case 5: -+ data->iout_scale[page] = 16; -+ return 0; -+ default: -+ data->iout_scale[page] = 64; -+ return 0; -+ } -+} -+ -+static int mp2891_rails_iout_scale_get(struct i2c_client *client, struct mp2891_data *data) -+{ -+ int ret; -+ -+ /* Get iout_scale for rail 1. */ -+ ret = mp2891_iout_scale_get(client, data, MP2891_MFR_SVI3_IOUT_PRT, 0); -+ /* Get iout_scale for rail 2. */ -+ return ret < 0 ? ret : mp2891_iout_scale_get(client, data, MP2891_MFR_SVI3_IOUT_PRT, 1); -+} -+ -+static struct pmbus_driver_info mp2891_info = { -+ .pages = MP2891_PAGE_NUM, -+ .format[PSC_VOLTAGE_IN] = direct, -+ .format[PSC_VOLTAGE_OUT] = direct, -+ .format[PSC_CURRENT_OUT] = linear, -+ .format[PSC_TEMPERATURE] = direct, -+ .format[PSC_POWER] = linear, -+ .m[PSC_VOLTAGE_IN] = 1, -+ .m[PSC_VOLTAGE_OUT] = 1, -+ .m[PSC_CURRENT_OUT] = 1, -+ .m[PSC_TEMPERATURE] = 1, -+ .R[PSC_VOLTAGE_IN] = 3, -+ .R[PSC_VOLTAGE_OUT] = 3, -+ .R[PSC_CURRENT_OUT] = 1, -+ .R[PSC_TEMPERATURE] = 0, -+ .func[0] = MP2891_RAIL1_FUNC, -+ .func[1] = MP2891_RAIL2_FUNC, -+ .read_byte_data = mp2891_read_byte_data, -+ .read_word_data = mp2891_read_word_data, -+ .write_word_data = mp2891_write_word_data, -+}; -+ -+static struct pmbus_platform_data mp2891_pdata = { -+ .flags = PMBUS_SKIP_STATUS_CHECK, -+}; -+ -+static int mp2891_probe(struct i2c_client *client) -+{ -+ struct pmbus_driver_info *info; -+ struct mp2891_data *data; -+ int ret; -+ -+ data = devm_kzalloc(&client->dev, sizeof(struct mp2891_data), GFP_KERNEL); -+ -+ if (!data) -+ return -ENOMEM; -+ -+ client->dev.platform_data = &mp2891_pdata; -+ memcpy(&data->info, &mp2891_info, sizeof(*info)); -+ info = &data->info; -+ -+ /* Identify VID setting per rail - obtain the vid_step of output voltage. */ -+ ret = mp2891_identify_rails_vid(client, data); -+ if (ret < 0) -+ return ret; -+ -+ /* Get iout scale per rail - obtain current scale. */ -+ ret = mp2891_rails_iout_scale_get(client, data); -+ if (ret < 0) -+ return ret; -+ -+ return pmbus_do_probe(client, info); -+} -+ -+static const struct i2c_device_id mp2891_id[] = { -+ {"mp2891", 0}, -+ {} -+}; -+MODULE_DEVICE_TABLE(i2c, mp2891_id); -+ -+static const struct of_device_id __maybe_unused mp2891_of_match[] = { -+ {.compatible = "mps,mp2891"}, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, mp2891_of_match); -+ -+static struct i2c_driver mp2891_driver = { -+ .driver = { -+ .name = "mp2891", -+ .of_match_table = mp2891_of_match, -+ }, -+ .probe_new = mp2891_probe, -+ .id_table = mp2891_id, -+}; -+ -+module_i2c_driver(mp2891_driver); -+ -+MODULE_DESCRIPTION("PMBus driver for MPS MP2891 device"); -+MODULE_LICENSE("GPL"); -+MODULE_IMPORT_NS(PMBUS); --- -2.44.0 - diff --git a/patch/0049-dt-bindings-trivial-devices-Add-mps-mp2891.patch b/patch/0049-dt-bindings-trivial-devices-Add-mps-mp2891.patch deleted file mode 100644 index 9bf39cb2b..000000000 --- a/patch/0049-dt-bindings-trivial-devices-Add-mps-mp2891.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 98b6b44b7b190c664f41e482de4597571e700e7f Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Thu, 13 Jul 2023 06:20:05 +0000 -Subject: [PATCH backport 6.1.42 49/85] dt-bindings: trivial-devices: Add - mps,mp2891 - -Add new dual-loop, digital, multi-phase controller MP2891 fro -Monolithic Power Systems, Inc. (MPS) to trivial devices. - -Signed-off-by: Vadim Pasternak ---- - Documentation/devicetree/bindings/trivial-devices.yaml | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml -index 7637390dfe09..8e6c0bc60ee3 100644 ---- a/Documentation/devicetree/bindings/trivial-devices.yaml -+++ b/Documentation/devicetree/bindings/trivial-devices.yaml -@@ -113,6 +113,8 @@ properties: - - fsl,mpl3115 - # MPR121: Proximity Capacitive Touch Sensor Controller - - fsl,mpr121 -+ # Monolithic Power Systems Inc. multi-phase controller mp2891 -+ - mps,mp2891 - # Monolithic Power Systems Inc. multi-phase controller mp2888 - - mps,mp2888 - # Monolithic Power Systems Inc. multi-phase controller mp2975 --- -2.20.1 - diff --git a/patch/0051-platform-mellanox-mlxreg-hotplug-Allow-more-flexible.patch b/patch/0051-platform-mellanox-mlxreg-hotplug-Allow-more-flexible.patch deleted file mode 100644 index 1cbb17b71..000000000 --- a/patch/0051-platform-mellanox-mlxreg-hotplug-Allow-more-flexible.patch +++ /dev/null @@ -1,110 +0,0 @@ -From dbffde13eba258aa4bc20eba3e9fe4db4d5716b7 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Mon, 9 Jan 2023 19:35:31 +0200 -Subject: [PATCH backport 6.1.42 51/85] platform/mellanox: mlxreg-hotplug: - Allow more flexible hotplug events configuration -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -26e118eaUpstream commit [98cf5ec0b53198e643d5fa8d99b73b49] - -Currently hotplug configuration in logic device assumes that all items -are provided with no holes. -Thus, any group of hotplug events, associated with the specific -status/event/mask registers is configured in those registers -successively from bit zero to bit #n (#n < 8). - -This logic is changed int order to allow non-successive definition to -support configuration with the skipped bits – for example bits 3, 5, 7 -in status/event/mask registers can be associated with hotplug events, -while others can be skipped. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych -Link: https://lore.kernel.org/r/20230208063331.15560-10-vadimp@nvidia.com -Signed-off-by: Hans de Goede ---- - drivers/platform/mellanox/mlxreg-hotplug.c | 28 ++++++++++++++++++---- - 1 file changed, 23 insertions(+), 5 deletions(-) - -diff --git a/drivers/platform/mellanox/mlxreg-hotplug.c b/drivers/platform/mellanox/mlxreg-hotplug.c -index 4936cf158ac8..c5abedd3514d 100644 ---- a/drivers/platform/mellanox/mlxreg-hotplug.c -+++ b/drivers/platform/mellanox/mlxreg-hotplug.c -@@ -239,6 +239,17 @@ static ssize_t mlxreg_hotplug_attr_show(struct device *dev, - #define PRIV_ATTR(i) priv->mlxreg_hotplug_attr[i] - #define PRIV_DEV_ATTR(i) priv->mlxreg_hotplug_dev_attr[i] - -+static int mlxreg_hotplug_item_label_index_get(u32 mask, u32 bit) -+{ -+ int i, j; -+ -+ for (i = 0, j = -1; i <= bit; i++) { -+ if (mask & BIT(i)) -+ j++; -+ } -+ return j; -+} -+ - static int mlxreg_hotplug_attr_init(struct mlxreg_hotplug_priv_data *priv) - { - struct mlxreg_core_hotplug_platform_data *pdata; -@@ -246,7 +257,7 @@ static int mlxreg_hotplug_attr_init(struct mlxreg_hotplug_priv_data *priv) - struct mlxreg_core_data *data; - unsigned long mask; - u32 regval; -- int num_attrs = 0, id = 0, i, j, k, ret; -+ int num_attrs = 0, id = 0, i, j, k, count, ret; - - pdata = dev_get_platdata(&priv->pdev->dev); - item = pdata->items; -@@ -272,7 +283,8 @@ static int mlxreg_hotplug_attr_init(struct mlxreg_hotplug_priv_data *priv) - /* Go over all unmasked units within item. */ - mask = item->mask; - k = 0; -- for_each_set_bit(j, &mask, item->count) { -+ count = item->ind ? item->ind : item->count; -+ for_each_set_bit(j, &mask, count) { - if (data->capability) { - /* - * Read capability register and skip non -@@ -282,16 +294,17 @@ static int mlxreg_hotplug_attr_init(struct mlxreg_hotplug_priv_data *priv) - data->capability, ®val); - if (ret) - return ret; -+ - if (!(regval & data->bit)) { - data++; - continue; - } - } -+ - PRIV_ATTR(id) = &PRIV_DEV_ATTR(id).dev_attr.attr; - PRIV_ATTR(id)->name = devm_kasprintf(&priv->pdev->dev, - GFP_KERNEL, - data->label); -- - if (!PRIV_ATTR(id)->name) { - dev_err(priv->dev, "Memory allocation failed for attr %d.\n", - id); -@@ -365,9 +378,14 @@ mlxreg_hotplug_work_helper(struct mlxreg_hotplug_priv_data *priv, - regval &= item->mask; - asserted = item->cache ^ regval; - item->cache = regval; -- - for_each_set_bit(bit, &asserted, 8) { -- data = item->data + bit; -+ int pos; -+ -+ pos = mlxreg_hotplug_item_label_index_get(item->mask, bit); -+ if (pos < 0) -+ goto out; -+ -+ data = item->data + pos; - if (regval & BIT(bit)) { - if (item->inversed) - mlxreg_hotplug_device_destroy(priv, data, item->kind); --- -2.20.1 - diff --git a/patch/0056-Documentation-ABI-Add-new-attribute-for-mlxreg-io-sy.patch b/patch/0056-Documentation-ABI-Add-new-attribute-for-mlxreg-io-sy.patch deleted file mode 100644 index e2bd55916..000000000 --- a/patch/0056-Documentation-ABI-Add-new-attribute-for-mlxreg-io-sy.patch +++ /dev/null @@ -1,181 +0,0 @@ -From 181881ca73d8864810ded434c6a11217a2d5e3bb Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 8 Feb 2023 08:33:30 +0200 -Subject: [PATH backport v6.1 31/32] Documentation/ABI: Add new attribute for - mlxreg-io sysfs interfaces - -Upstream commit: [e7210563432a6c6fa65a9c5c11ece2a0adbeeda2] - -Add description for new attributes added for rack manager switch and -NG800 family systems. - -Attributes related to power converter board: -- reset_pwr_converter_fail; -- pwr_converter_prog_en; -Attributes related to External Root of Trust (EROT) devices recovery: -- erot1_ap_reset; -- erot2_ap_reset; -- erot1_recovery; -- erot2_recovery; -- erot1_reset; -- erot2_reset; -- erot1_wp; -- erot2_wp; -- spi_chnl_select; -Attributes related to clock board failures and recovery: -- clk_brd1_boot_fail; -- clk_brd2_boot_fail; -- clk_brd_fail; -- clk_brd_prog_en; -Attributes related to power failures: -- reset_ac_ok_fail; -- asic_pg_fail; - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych -Link: https://lore.kernel.org/r/20230208063331.15560-14-vadimp@nvidia.com -Signed-off-by: Hans de Goede ---- - .../ABI/stable/sysfs-driver-mlxreg-io | 122 +++++++++++++++++- - 1 file changed, 121 insertions(+), 1 deletion(-) - -diff --git a/Documentation/ABI/stable/sysfs-driver-mlxreg-io b/Documentation/ABI/stable/sysfs-driver-mlxreg-io -index af0cbf143c48..60953903d007 100644 ---- a/Documentation/ABI/stable/sysfs-driver-mlxreg-io -+++ b/Documentation/ABI/stable/sysfs-driver-mlxreg-io -@@ -522,7 +522,6 @@ Description: These files allow to each of ASICs by writing 1. - - The files are write only. - -- - What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/comm_chnl_ready - Date: July 2022 - KernelVersion: 5.20 -@@ -542,3 +541,124 @@ Description: The file indicates COME module hardware configuration. - The purpose is to expose some minor BOM changes for the same system SKU. - - The file is read only. -+ -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_pwr_converter_fail -+Date: February 2023 -+KernelVersion: 6.3 -+Contact: Vadim Pasternak -+Description: This file shows the system reset cause due to power converter -+ devices failure. -+ Value 1 in file means this is reset cause, 0 - otherwise. -+ -+ The file is read only. -+ -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot1_ap_reset -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot2_ap_reset -+Date: February 2023 -+KernelVersion: 6.3 -+Contact: Vadim Pasternak -+Description: These files aim to monitor the status of the External Root of Trust (EROT) -+ processor's RESET output to the Application Processor (AP). -+ By reading this file, could be determined if the EROT has invalidated or -+ revoked AP Firmware, at which point it will hold the AP in RESET until a -+ valid firmware is loaded. This protects the AP from running an -+ unauthorized firmware. In the normal flow, the AP reset should be released -+ after the EROT validates the integrity of the FW, and it should be done so -+ as quickly as possible so that the AP boots before the CPU starts to -+ communicate to each ASIC. -+ -+ The files are read only. -+ -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot1_recovery -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot2_recovery -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot1_reset -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot2_reset -+Date: February 2023 -+KernelVersion: 6.3 -+Contact: Vadim Pasternak -+Description: These files aim to perform External Root of Trust (EROT) recovery -+ sequence after EROT device failure. -+ These EROT devices protect ASICs from unauthorized access and in normal -+ flow their reset should be released with system power – earliest power -+ up stage, so that EROTs can begin boot and authentication process before -+ CPU starts to communicate to ASICs. -+ Issuing a reset to the EROT while asserting the recovery signal will cause -+ the EROT Application Processor to enter recovery mode so that the EROT FW -+ can be updated/recovered. -+ For reset/recovery the related file should be toggled by 1/0. -+ -+ The files are read/write. -+ -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot1_wp -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot2_wp -+Date: February 2023 -+KernelVersion: 6.3 -+Contact: Vadim Pasternak -+Description: These files allow access to External Root of Trust (EROT) for reset -+ and recovery sequence after EROT device failure. -+ Default is 0 (programming disabled). -+ If the system is in locked-down mode writing this file will not be allowed. -+ -+ The files are read/write. -+ -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/spi_chnl_select -+Date: February 2023 -+KernelVersion: 6.3 -+Contact: Vadim Pasternak -+Description: This file allows SPI chip selection for External Root of Trust (EROT) -+ device Out-of-Band recovery. -+ File can be written with 0 or with 1. It selects which EROT can be accessed -+ through SPI device. -+ -+ The file is read/write. -+ -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic_pg_fail -+Date: February 2023 -+KernelVersion: 6.3 -+Contact: Vadim Pasternak vadimp@nvidia.com -+Description: This file shows ASIC Power Good status. -+ Value 1 in file means ASIC Power Good failed, 0 - otherwise. -+ -+ The file is read only. -+ -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/clk_brd1_boot_fail -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/clk_brd2_boot_fail -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/clk_brd_fail -+Date: February 2023 -+KernelVersion: 6.3 -+Contact: Vadim Pasternak vadimp@nvidia.com -+Description: These files are related to clock boards status in system. -+ - clk_brd1_boot_fail: warning about 1-st clock board failed to boot from CI. -+ - clk_brd2_boot_fail: warning about 2-nd clock board failed to boot from CI. -+ - clk_brd_fail: error about common clock board boot failure. -+ -+ The files are read only. -+ -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/clk_brd_prog_en -+Date: February 2023 -+KernelVersion: 6.3 -+Contact: Vadim Pasternak -+Description: This file enables programming of clock boards. -+ Default is 0 (programming disabled). -+ If the system is in locked-down mode writing this file will not be allowed. -+ -+ The file is read/write. -+ -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/pwr_converter_prog_en -+Date: February 2023 -+KernelVersion: 6.3 -+Contact: Vadim Pasternak -+Description: This file enables programming of power converters. -+ Default is 0 (programming disabled). -+ If the system is in locked-down mode writing this file will not be allowed. -+ -+ The file is read/write. -+ -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_ac_ok_fail -+Date: February 2023 -+KernelVersion: 6.3 -+Contact: Vadim Pasternak -+Description: This file shows the system reset cause due to AC power failure. -+ Value 1 in file means this is reset cause, 0 - otherwise. -+ -+ The file is read only. --- -2.20.1 - diff --git a/patch/0057-Documentation-ABI-Add-new-attribute-for-mlxreg-io-sy.patch b/patch/0057-Documentation-ABI-Add-new-attribute-for-mlxreg-io-sy.patch deleted file mode 100644 index 943780109..000000000 --- a/patch/0057-Documentation-ABI-Add-new-attribute-for-mlxreg-io-sy.patch +++ /dev/null @@ -1,74 +0,0 @@ -From fe6caa3afd2525ee83f1b2ee13a1650c596f9e1c Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 13 Aug 2023 17:51:39 +0000 -Subject: [PATH backport v6.1 32/32] Documentation/ABI: Add new attribute for - mlxreg-io sysfs interfaces - -Link: https://www.spinics.net/lists/platform-driver-x86/msg39648.html - -Add documentation for the new attributes: -- CPLD versioning: "cpld5_pn", "cpld5_version", "cpld5_version_min". -- JTAG capability: "jtag_cap", indicating the available method of - CPLD/FPGA devices field update. -- System lid status: "lid_open". -- Reset caused by long press of power button: "reset_long_pwr_pb". - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - .../ABI/stable/sysfs-driver-mlxreg-io | 42 +++++++++++++++++++ - 1 file changed, 42 insertions(+) - -diff --git a/Documentation/ABI/stable/sysfs-driver-mlxreg-io b/Documentation/ABI/stable/sysfs-driver-mlxreg-io -index 60953903d007..633be2bf2cd0 100644 ---- a/Documentation/ABI/stable/sysfs-driver-mlxreg-io -+++ b/Documentation/ABI/stable/sysfs-driver-mlxreg-io -@@ -662,3 +662,45 @@ Description: This file shows the system reset cause due to AC power failure. - Value 1 in file means this is reset cause, 0 - otherwise. - - The file is read only. -+ -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld5_pn -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld5_version -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld5_version_min -+Date: August 2023 -+KernelVersion: 6.6 -+Contact: Vadim Pasternak -+Description: These files show with which CPLD part numbers, version and minor -+ versions have been burned the 5-th CPLD device equipped on a -+ system. -+ -+ The files are read only. -+ -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/jtag_cap -+Date: August 2023 -+KernelVersion: 6.6 -+Contact: Vadim Pasternak -+Description: This file indicates the available method of CPLD/FPGA devices -+ field update through the JTAG chain: -+ b00 - field update through LPC bus register memory space. -+ b01 - Reserved. -+ b10 - Reserved. -+ b11 - field update through CPU GPIOs bit-banging. -+ -+ The file is read only. -+ -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lid_open -+Date: August 2023 -+KernelVersion: 6.6 -+Contact: Vadim Pasternak -+Description: 1 - indicates that system lid is opened, otherwise 0. -+ -+ The file is read only. -+ -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_long_pwr_pb -+Date: August 2023 -+KernelVersion: 6.6 -+Contact: Vadim Pasternak -+Description: This file if set 1 indicates that system has been reset by -+ long press of power button. -+ -+ The file is read only. --- -2.20.1 - diff --git a/patch/0090-platform-mellanox-mlx-platform-Add-support-for-new-X.patch b/patch/0090-platform-mellanox-mlx-platform-Add-support-for-new-X.patch deleted file mode 100644 index 36e74128d..000000000 --- a/patch/0090-platform-mellanox-mlx-platform-Add-support-for-new-X.patch +++ /dev/null @@ -1,1402 +0,0 @@ -From 75f034c8cfba7ce9f79e72e06f328aa39103fcff Mon Sep 17 00:00:00 2001 -From: Felix Radensky -Date: Mon, 4 Sep 2023 18:28:37 +0000 -Subject: [PATCH v6.1 2/8] platform: mellanox: mlx-platform: Add support for - new XDR systems - -Add support for QM3400 and QM3000, Nvidia XDR switches. - -QM3400 is a 57.6Tbps switch based on Nvidia Quantum-3 ASIC. -It provides up-to 800Gbps full bidirectional bandwidth per port. -The system supports 36 OSFP cages and fits into standard 2U racks. - -QM3400 Features: - - 36 OSFP ports supporting 2.5Gbps - 800Gbps speeds. - - Air-cooled with 4 + 1 redundant fan units. - - 2 + 2 redundant 2000W PSUs. - - System management board based on Intel Coffee Lake CPU - with secure-boot support. - -QM3000 is a 115.2Tbps switch based on Nvidia Quantum-3 ASIC. -It provides up-to 800Gbps full bidirectional bandwidth per port. -The system supports 72 OSFP cages and fits into standard 4U racks. - -QM3000 Features: - - 72 OSFP ports or 144 aggregated XDR ports supporting 800Gbps speeds. - - Air-cooled with 9 + 1 redundant fan units. - - 4 + 4 redundant 2000W PSUs. - - System management board based on Intel Coffee Lake CPU - with secure-boot support. - -Signed-off-by: Felix Radensky -Reviewed-by: Vadim Pasternak ---- - drivers/platform/mellanox/mlx-platform.c | 1068 +++++++++++++++++++++- - 1 file changed, 1049 insertions(+), 19 deletions(-) - -diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index c1ebd4f85158..cafa4f762672 100644 ---- a/drivers/platform/mellanox/mlx-platform.c -+++ b/drivers/platform/mellanox/mlx-platform.c -@@ -50,6 +50,7 @@ - #define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24 - #define MLXPLAT_CPLD_LPC_REG_LED6_OFFSET 0x25 - #define MLXPLAT_CPLD_LPC_REG_LED7_OFFSET 0x26 -+#define MLXPLAT_CPLD_LPC_REG_LED8_OFFSET 0x27 - #define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a - #define MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET 0x2b - #define MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET 0x2d -@@ -95,9 +96,21 @@ - #define MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET 0x70 - #define MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET 0x71 - #define MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET 0x72 -+#define MLXPLAT_CPLD_LPC_REG_CPLD6_VER_OFFSET 0x7c -+#define MLXPLAT_CPLD_LPC_REG_CPLD6_PN_OFFSET 0x7d -+#define MLXPLAT_CPLD_LPC_REG_CPLD6_PN1_OFFSET 0x7e -+#define MLXPLAT_CPLD_LPC_REG_ASIC3_HEALTH_OFFSET 0x82 -+#define MLXPLAT_CPLD_LPC_REG_ASIC3_EVENT_OFFSET 0x83 -+#define MLXPLAT_CPLD_LPC_REG_ASIC3_MASK_OFFSET 0x84 -+#define MLXPLAT_CPLD_LPC_REG_ASIC4_HEALTH_OFFSET 0x85 -+#define MLXPLAT_CPLD_LPC_REG_ASIC4_EVENT_OFFSET 0x86 -+#define MLXPLAT_CPLD_LPC_REG_ASIC4_MASK_OFFSET 0x87 - #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88 - #define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89 - #define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a -+#define MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET 0x8b -+#define MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET 0x8c -+#define MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET 0x8d - #define MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET 0x8e - #define MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET 0x8f - #define MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET 0x90 -@@ -129,10 +142,15 @@ - #define MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET 0xaa - #define MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET 0xab - #define MLXPLAT_CPLD_LPC_REG_LC_PWR_ON 0xb2 -+#define MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET 0xb4 -+#define MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET 0xb5 - #define MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET 0xb6 - #define MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET 0xb7 - #define MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET 0xb8 - #define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET 0xb9 -+#define MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET 0xba -+#define MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET 0xbb -+#define MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET 0xc1 - #define MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET 0xc2 - #define MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT 0xc3 - #define MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET 0xc4 -@@ -183,6 +201,8 @@ - #define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb - #define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc - #define MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET 0xfd -+#define MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET 0xfe -+#define MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET 0xff - #define MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET 0x100 - #define MLXPLAT_CPLD_LPC_REG_EXT_MID_OFFSET 0x195 - #define MLXPLAT_CPLD_LPC_REG_EXT_MAX_OFFSET 0x1ff -@@ -235,19 +255,30 @@ - #define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2 BIT(2) - #define MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT GENMASK(5, 4) - #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6) -+#define MLXPLAT_CPLD_LOW_AGGR_MASK_MULTI_ASICS GENMASK(3, 0) -+#define MLXPLAT_CPLD_LOW_AGGR_MASK_FRU BIT(7) - #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0) - #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0) - #define MLXPLAT_CPLD_PSU_EXT_MASK GENMASK(3, 0) - #define MLXPLAT_CPLD_PWR_EXT_MASK GENMASK(3, 0) -+#define MLXPLAT_CPLD_PSU_XDR_MASK GENMASK(7, 0) -+#define MLXPLAT_CPLD_PWR_XDR_MASK GENMASK(7, 0) - #define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0) - #define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0) -+#define MLXPLAT_CPLD_ASIC_XDR_MASK GENMASK(3, 0) - #define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(6, 0) -+#define MLXPLAT_CPLD_FAN_QMB8700_MASK GENMASK(5, 0) -+#define MLXPLAT_CPLD_FAN_XDR_MASK GENMASK(7, 0) -+#define MLXPLAT_CPLD_FAN_XDR_EXT_MASK GENMASK(1, 0) - #define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4) - #define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0) - #define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4) - #define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0) - #define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0) - #define MLXPLAT_CPLD_FU_CAP_MASK GENMASK(1, 0) -+#define MLXPLAT_CPLD_PSU_CAP_MASK GENMASK(3, 0) -+#define MLXPLAT_CPLD_FAN_CAP_MASK GENMASK(7, 0) -+#define MLXPLAT_CPLD_ASIC_CAP_MASK GENMASK(7, 0) - #define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0) - #define MLXPLAT_CPLD_LATCH_RST_MASK BIT(6) - #define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3) -@@ -294,6 +325,7 @@ - #define MLXPLAT_CPLD_CH4_ETH_MODULAR 51 - #define MLXPLAT_CPLD_CH2_RACK_SWITCH 18 - #define MLXPLAT_CPLD_CH2_NG800 34 -+#define MLXPLAT_CPLD_CH2_XDR 66 - - /* Number of LPC attached MUX platform devices */ - #define MLXPLAT_CPLD_LPC_MUX_DEVS 4 -@@ -302,6 +334,7 @@ - #define MLXPLAT_CPLD_NR_NONE -1 - #define MLXPLAT_CPLD_PSU_DEFAULT_NR 10 - #define MLXPLAT_CPLD_PSU_MSNXXXX_NR 4 -+#define MLXPLAT_CPLD_PSU_XDR_NR 3 - #define MLXPLAT_CPLD_FAN1_DEFAULT_NR 11 - #define MLXPLAT_CPLD_FAN2_DEFAULT_NR 12 - #define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13 -@@ -644,6 +677,38 @@ static struct i2c_mux_reg_platform_data mlxplat_ng800_mux_data[] = { - - }; - -+/* Platform channels for XDR system family */ -+static const int mlxplat_xdr_channels[] = { -+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, -+ 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, -+ 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, -+ 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64 -+}; -+ -+/* Platform XDR mux data */ -+static struct i2c_mux_reg_platform_data mlxplat_xdr_mux_data[] = { -+ { -+ .parent = 1, -+ .base_nr = MLXPLAT_CPLD_CH1, -+ .write_only = 1, -+ .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, -+ .reg_size = 1, -+ .idle_in_use = 1, -+ .values = mlxplat_xdr_channels, -+ .n_values = ARRAY_SIZE(mlxplat_xdr_channels), -+ }, -+ { -+ .parent = 1, -+ .base_nr = MLXPLAT_CPLD_CH2_XDR, -+ .write_only = 1, -+ .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, -+ .reg_size = 1, -+ .idle_in_use = 1, -+ .values = mlxplat_msn21xx_channels, -+ .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), -+ }, -+}; -+ - /* Platform hotplug devices */ - static struct i2c_board_info mlxplat_mlxcpld_pwr[] = { - { -@@ -663,6 +728,21 @@ static struct i2c_board_info mlxplat_mlxcpld_ext_pwr[] = { - }, - }; - -+static struct i2c_board_info mlxplat_mlxcpld_xdr_pwr[] = { -+ { -+ I2C_BOARD_INFO("dps460", 0x5d), -+ }, -+ { -+ I2C_BOARD_INFO("dps460", 0x5c), -+ }, -+ { -+ I2C_BOARD_INFO("dps460", 0x5e), -+ }, -+ { -+ I2C_BOARD_INFO("dps460", 0x5f), -+ }, -+}; -+ - static struct i2c_board_info mlxplat_mlxcpld_pwr_ng800[] = { - { - I2C_BOARD_INFO("dps460", 0x59), -@@ -1432,6 +1512,441 @@ static struct mlxreg_core_item mlxplat_mlxcpld_ng800_items[] = { - }, - }; - -+/* Platform hotplug XDR system family data */ -+static struct mlxreg_core_data mlxplat_mlxcpld_xdr_psu_items_data[] = { -+ { -+ .label = "psu1", -+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, -+ .mask = BIT(0), -+ .slot = 1, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "psu2", -+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, -+ .mask = BIT(1), -+ .slot = 2, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "psu3", -+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, -+ .mask = BIT(2), -+ .slot = 3, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "psu4", -+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, -+ .mask = BIT(3), -+ .slot = 4, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "psu5", -+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, -+ .mask = BIT(4), -+ .slot = 5, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "psu6", -+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, -+ .mask = BIT(5), -+ .slot = 6, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "psu7", -+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, -+ .mask = BIT(6), -+ .slot = 7, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "psu8", -+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, -+ .mask = BIT(7), -+ .slot = 8, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+}; -+ -+static struct mlxreg_core_data mlxplat_mlxcpld_xdr_pwr_items_data[] = { -+ { -+ .label = "pwr1", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, -+ .mask = BIT(0), -+ .slot = 1, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, -+ .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], -+ .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, -+ }, -+ { -+ .label = "pwr2", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, -+ .mask = BIT(1), -+ .slot = 2, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, -+ .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], -+ .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, -+ }, -+ { -+ .label = "pwr3", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, -+ .mask = BIT(2), -+ .slot = 3, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, -+ .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], -+ .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, -+ }, -+ { -+ .label = "pwr4", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, -+ .mask = BIT(3), -+ .slot = 4, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, -+ .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], -+ .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, -+ }, -+ { -+ .label = "pwr5", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, -+ .mask = BIT(4), -+ .slot = 5, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, -+ .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[0], -+ .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, -+ }, -+ { -+ .label = "pwr6", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, -+ .mask = BIT(5), -+ .slot = 6, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, -+ .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[1], -+ .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, -+ }, -+ { -+ .label = "pwr7", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, -+ .mask = BIT(6), -+ .slot = 7, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, -+ .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[2], -+ .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, -+ }, -+ { -+ .label = "pwr8", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, -+ .mask = BIT(7), -+ .slot = 8, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, -+ .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[3], -+ .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, -+ }, -+}; -+ -+static int mlxplat_mlxcpld_xdr_pwr_nr_fixup[] = { -+ MLXPLAT_CPLD_PSU_MSNXXXX_NR, -+ MLXPLAT_CPLD_PSU_MSNXXXX_NR, -+ MLXPLAT_CPLD_PSU_XDR_NR, -+ MLXPLAT_CPLD_PSU_XDR_NR, -+ MLXPLAT_CPLD_PSU_MSNXXXX_NR, -+ MLXPLAT_CPLD_PSU_MSNXXXX_NR, -+ MLXPLAT_CPLD_PSU_XDR_NR, -+ MLXPLAT_CPLD_PSU_XDR_NR, -+}; -+ -+static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_items_data[] = { -+ { -+ .label = "fan1", -+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .mask = BIT(0), -+ .slot = 1, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, -+ .bit = BIT(0), -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "fan2", -+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .mask = BIT(1), -+ .slot = 2, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, -+ .bit = BIT(1), -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "fan3", -+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .mask = BIT(2), -+ .slot = 3, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, -+ .bit = BIT(2), -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "fan4", -+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .mask = BIT(3), -+ .slot = 4, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, -+ .bit = BIT(3), -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "fan5", -+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .mask = BIT(4), -+ .slot = 5, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, -+ .bit = BIT(4), -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "fan6", -+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .mask = BIT(5), -+ .slot = 6, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, -+ .bit = BIT(5), -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "fan7", -+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .mask = BIT(6), -+ .slot = 7, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, -+ .bit = BIT(6), -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "fan8", -+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .mask = BIT(7), -+ .slot = 8, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, -+ .bit = BIT(7), -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+}; -+ -+static struct mlxreg_core_data mlxplat_mlxcpld_xdr_ext_fan_items_data[] = { -+ { -+ .label = "fan9", -+ .reg = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, -+ .mask = BIT(0), -+ .slot = 9, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, -+ .bit = BIT(0), -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "fan10", -+ .reg = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, -+ .mask = BIT(1), -+ .slot = 10, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, -+ .bit = BIT(1), -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "fan11", -+ .reg = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, -+ .mask = BIT(2), -+ .slot = 11, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, -+ .bit = BIT(2), -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "fan12", -+ .reg = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, -+ .mask = BIT(3), -+ .slot = 12, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, -+ .bit = BIT(3), -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+}; -+ -+static struct mlxreg_core_data mlxplat_mlxcpld_xdr_asic1_items_data[] = { -+ { -+ .label = "asic1", -+ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, -+ .mask = MLXPLAT_CPLD_ASIC_MASK, -+ .slot = 1, -+ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ } -+}; -+ -+static struct mlxreg_core_data mlxplat_mlxcpld_xdr_asic2_items_data[] = { -+ { -+ .label = "asic2", -+ .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, -+ .mask = MLXPLAT_CPLD_ASIC_MASK, -+ .slot = 2, -+ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ } -+}; -+ -+static struct mlxreg_core_data mlxplat_mlxcpld_xdr_asic3_items_data[] = { -+ { -+ .label = "asic3", -+ .reg = MLXPLAT_CPLD_LPC_REG_ASIC3_HEALTH_OFFSET, -+ .mask = MLXPLAT_CPLD_ASIC_MASK, -+ .slot = 3, -+ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ } -+}; -+ -+static struct mlxreg_core_data mlxplat_mlxcpld_xdr_asic4_items_data[] = { -+ { -+ .label = "asic4", -+ .reg = MLXPLAT_CPLD_LPC_REG_ASIC4_HEALTH_OFFSET, -+ .mask = MLXPLAT_CPLD_ASIC_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, -+ .slot = 4, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ } -+}; -+ -+static struct mlxreg_core_item mlxplat_mlxcpld_xdr_items[] = { -+ { -+ .data = mlxplat_mlxcpld_xdr_psu_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, -+ .mask = MLXPLAT_CPLD_PSU_XDR_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_psu_items_data), -+ .inversed = 1, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_xdr_pwr_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, -+ .mask = MLXPLAT_CPLD_PWR_XDR_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_pwr_items_data), -+ .inversed = 0, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_xdr_fan_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .mask = MLXPLAT_CPLD_FAN_XDR_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_FAN_CAP_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_items_data), -+ .inversed = 1, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_xdr_ext_fan_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, -+ .mask = MLXPLAT_CPLD_FAN_XDR_EXT_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_FAN_CAP_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_ext_fan_items_data), -+ .inversed = 1, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_xdr_asic1_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, -+ .mask = MLXPLAT_CPLD_ASIC_XDR_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_asic1_items_data), -+ .inversed = 0, -+ .health = true, -+ }, -+ { -+ .data = mlxplat_mlxcpld_xdr_asic2_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, -+ .mask = MLXPLAT_CPLD_ASIC_XDR_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_asic2_items_data), -+ .inversed = 0, -+ .health = true, -+ }, -+ { -+ .data = mlxplat_mlxcpld_xdr_asic3_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_ASIC3_HEALTH_OFFSET, -+ .mask = MLXPLAT_CPLD_ASIC_XDR_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_asic3_items_data), -+ .inversed = 0, -+ .health = true, -+ }, -+ { -+ .data = mlxplat_mlxcpld_xdr_asic4_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_ASIC4_HEALTH_OFFSET, -+ .mask = MLXPLAT_CPLD_ASIC_XDR_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_asic4_items_data), -+ .inversed = 0, -+ .health = true, -+ }, -+}; -+ - static - struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { - .items = mlxplat_mlxcpld_ext_items, -@@ -1452,6 +1967,16 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_data = { - .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, - }; - -+static -+struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_xdr_data = { -+ .items = mlxplat_mlxcpld_xdr_items, -+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_xdr_items), -+ .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, -+ .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, -+ .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, -+ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_FRU | MLXPLAT_CPLD_LOW_AGGR_MASK_MULTI_ASICS, -+}; -+ - static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = { - { - .label = "pwr1", -@@ -3159,42 +3684,216 @@ static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_led_data[] = { - .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, - .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -- .bit = BIT(3), -+ .bit = BIT(3), -+ }, -+ { -+ .label = "fan4:orange", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(3), -+ }, -+ { -+ .label = "fan5:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(4), -+ }, -+ { -+ .label = "fan5:orange", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(4), -+ }, -+ { -+ .label = "fan6:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(5), -+ }, -+ { -+ .label = "fan6:orange", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(5), -+ }, -+ { -+ .label = "uid:blue", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ }, -+}; -+ -+static struct mlxreg_core_platform_data mlxplat_l1_switch_led_data = { -+ .data = mlxplat_mlxcpld_l1_switch_led_data, -+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_led_data), -+}; -+ -+/* Platform led data for XDR systems */ -+static struct mlxreg_core_data mlxplat_mlxcpld_xdr_led_data[] = { -+ { -+ .label = "status:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ }, -+ { -+ .label = "status:amber", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK -+ }, -+ { -+ .label = "psu:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ }, -+ { -+ .label = "psu:amber", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ }, -+ { -+ .label = "fan1:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .slot = 1, -+ }, -+ { -+ .label = "fan1:amber", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .slot = 1, -+ }, -+ { -+ .label = "fan2:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .slot = 2, -+ }, -+ { -+ .label = "fan2:amber", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .slot = 2, -+ }, -+ { -+ .label = "fan3:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .slot = 3, -+ }, -+ { -+ .label = "fan3:amber", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .slot = 3, -+ }, -+ { -+ .label = "fan4:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .slot = 4, -+ }, -+ { -+ .label = "fan4:amber", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .slot = 4, -+ }, -+ { -+ .label = "fan5:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .slot = 5, -+ }, -+ { -+ .label = "fan5:amber", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .slot = 5, -+ }, -+ { -+ .label = "fan6:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .slot = 6, -+ }, -+ { -+ .label = "fan6:amber", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .slot = 6, -+ }, -+ { -+ .label = "fan7:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .slot = 7, - }, - { -- .label = "fan4:orange", -- .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, -+ .label = "fan7:amber", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, - .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -- .bit = BIT(3), -+ .slot = 7, - }, - { -- .label = "fan5:green", -- .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, -+ .label = "fan8:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, - .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -- .bit = BIT(4), -+ .slot = 8, - }, - { -- .label = "fan5:orange", -- .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, -+ .label = "fan8:amber", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, - .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, - .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -- .bit = BIT(4), -+ .slot = 8, - }, - { -- .label = "fan6:green", -- .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, -+ .label = "fan9:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, - .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -- .bit = BIT(5), -+ .slot = 9, - }, - { -- .label = "fan6:orange", -- .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, -+ .label = "fan9:amber", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, - .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, - .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -- .bit = BIT(5), -+ .slot = 9, -+ }, -+ { -+ .label = "fan10:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED8_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .slot = 10, -+ }, -+ { -+ .label = "fan10:amber", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED8_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .slot = 10, - }, - { - .label = "uid:blue", -@@ -3203,9 +3902,9 @@ static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_led_data[] = { - }, - }; - --static struct mlxreg_core_platform_data mlxplat_l1_switch_led_data = { -- .data = mlxplat_mlxcpld_l1_switch_led_data, -- .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_led_data), -+static struct mlxreg_core_platform_data mlxplat_xdr_led_data = { -+ .data = mlxplat_mlxcpld_xdr_led_data, -+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_xdr_led_data), - }; - - /* Platform register access default */ -@@ -3504,6 +4203,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .bit = GENMASK(7, 0), - .mode = 0444, - }, -+ { -+ .label = "cpld6_version", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD6_VER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, - { - .label = "cpld1_pn", - .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, -@@ -3539,6 +4244,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mode = 0444, - .regnum = 2, - }, -+ { -+ .label = "cpld6_pn", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD6_PN_OFFSET, -+ .bit = GENMASK(15, 0), -+ .mode = 0444, -+ .regnum = 2, -+ }, - { - .label = "cpld1_version_min", - .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, -@@ -3569,6 +4281,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .bit = GENMASK(7, 0), - .mode = 0444, - }, -+ { -+ .label = "cpld6_version_min", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD6_MVER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, - { - .label = "asic_reset", - .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, -@@ -3758,6 +4476,43 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mask = GENMASK(7, 0) & ~BIT(1), - .mode = 0200, - }, -+ { -+ .label = "psu3_on", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0200, -+ }, -+ { -+ .label = "psu4_on", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), -+ .mode = 0200, -+ }, -+ { -+ .label = "psu5_on", -+ .reg = MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0200, -+ }, -+ -+ { -+ .label = "psu6_on", -+ .reg = MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0200, -+ }, -+ { -+ .label = "psu7_on", -+ .reg = MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0200, -+ }, -+ { -+ .label = "psu8_on", -+ .reg = MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0200, -+ }, - { - .label = "pwr_cycle", - .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, -@@ -3833,6 +4588,20 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .bit = 1, - .mode = 0444, - }, -+ { -+ .label = "asic3_health", -+ .reg = MLXPLAT_CPLD_LPC_REG_ASIC3_HEALTH_OFFSET, -+ .mask = MLXPLAT_CPLD_ASIC_MASK, -+ .bit = 1, -+ .mode = 0444, -+ }, -+ { -+ .label = "asic4_health", -+ .reg = MLXPLAT_CPLD_LPC_REG_ASIC4_HEALTH_OFFSET, -+ .mask = MLXPLAT_CPLD_ASIC_MASK, -+ .bit = 1, -+ .mode = 0444, -+ }, - { - .label = "fan_dir", - .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, -@@ -4803,6 +5572,185 @@ static struct mlxreg_core_platform_data mlxplat_default_fan_data = { - .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, - }; - -+/* XDR platform fan data */ -+static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_data[] = { -+ { -+ .label = "pwm1", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, -+ }, -+ { -+ .label = "tacho1", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .slot = 1, -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho2", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .slot = 2, -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho3", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .slot = 3, -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho4", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .slot = 4, -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho5", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .slot = 5, -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho6", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .slot = 6, -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho7", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .slot = 7, -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho8", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .slot = 8, -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho9", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .slot = 9, -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho10", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .slot = 10, -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho11", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .slot = 11, -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho12", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .slot = 12, -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho13", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .slot = 13, -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho14", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .slot = 14, -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho15", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .slot = 15, -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho16", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .slot = 16, -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho17", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .slot = 17, -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, -+ }, -+ { -+ .label = "tacho18", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .slot = 18, -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, -+ }, -+ { -+ .label = "tacho19", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .slot = 19, -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, -+ }, -+ { -+ .label = "tacho20", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .slot = 20, -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, -+ }, -+ { -+ .label = "conf", -+ .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET, -+ }, -+}; -+ -+static struct mlxreg_core_platform_data mlxplat_xdr_fan_data = { -+ .data = mlxplat_mlxcpld_xdr_fan_data, -+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_data), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .version = 1, -+}; -+ - /* Watchdog type1: hardware implementation version1 - * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems). - */ -@@ -5035,6 +5983,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: -@@ -5062,12 +6011,18 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_ASIC3_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_ASIC3_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_ASIC4_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_ASIC4_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: -@@ -5125,6 +6080,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD6_VER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: -@@ -5135,6 +6091,8 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD6_PN_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD6_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: -@@ -5147,6 +6105,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: - case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: -@@ -5184,6 +6143,12 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_ASIC3_HEALTH_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_ASIC3_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_ASIC3_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_ASIC4_HEALTH_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_ASIC4_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_ASIC4_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: -@@ -5193,6 +6158,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: -@@ -5266,6 +6234,13 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: - case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET: - case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: -@@ -5291,6 +6266,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD6_VER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: -@@ -5301,6 +6277,8 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD6_PN_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD6_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: -@@ -5313,6 +6291,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: - case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: -@@ -5348,6 +6327,12 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_ASIC3_HEALTH_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_ASIC3_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_ASIC3_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_ASIC4_HEALTH_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_ASIC4_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_ASIC4_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: -@@ -5357,6 +6342,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: -@@ -5424,6 +6412,13 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: - case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET: - case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: -@@ -6116,6 +7111,35 @@ static int __init mlxplat_dmi_bf3_comex_default_matched(const struct dmi_system_ - return 1; - } - -+static int __init mlxplat_dmi_xdr_matched(const struct dmi_system_id *dmi) -+{ -+ int i; -+ const char *sku; -+ -+ sku = dmi_get_system_info(DMI_PRODUCT_SKU); -+ if (!strcmp(sku, "HI158")) { -+ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_xdr_pwr_items_data); i++) -+ mlxplat_mlxcpld_xdr_pwr_items_data[i].hpdev.nr = -+ mlxplat_mlxcpld_xdr_pwr_nr_fixup[i]; -+ } -+ -+ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; -+ mlxplat_mux_num = ARRAY_SIZE(mlxplat_xdr_mux_data); -+ mlxplat_mux_data = mlxplat_xdr_mux_data; -+ mlxplat_hotplug = &mlxplat_mlxcpld_xdr_data; -+ mlxplat_hotplug->deferred_nr = -+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; -+ mlxplat_led = &mlxplat_xdr_led_data; -+ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; -+ mlxplat_fan = &mlxplat_xdr_fan_data; -+ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) -+ mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; -+ mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; -+ mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; -+ -+ return mlxplat_register_platform_device(); -+} -+ - static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { - { - .callback = mlxplat_dmi_default_wc_matched, -@@ -6216,6 +7240,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { - DMI_MATCH(DMI_BOARD_NAME, "VMOD0017"), - }, - }, -+ { -+ .callback = mlxplat_dmi_xdr_matched, -+ .matches = { -+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0018"), -+ }, -+ }, - { - .callback = mlxplat_dmi_msn274x_matched, - .matches = { --- -2.20.1 - diff --git a/patch/0092-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch b/patch/0092-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch deleted file mode 100644 index 98b911881..000000000 --- a/patch/0092-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch +++ /dev/null @@ -1,1248 +0,0 @@ -From 1ffb1c6f0a5d71f35e727ff228dc08b065c084c1 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Thu, 7 Dec 2023 20:43:29 +0000 -Subject: [PATCH v6.1 02/16] platform: mellanox: Introduce support of Nvidia - smart switch -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Provide platform support for Nvidia Smart Switch SN4280. - -The Smart Switch equipped with: -- Nvidia COME module based on AMD EPYC™ Embedded 3451 CPU. -- Nvidia Spectrum-3 ASIC. -- Four DPUs, each equipped with Nvidia BF3 ARM based processor and - with Lattice LFD2NX-40 FPGA device. -- 28xQSFP-DD external ports. -- Two power supplies. -- Four cooling drawers. - -Introduce configuration structures for the new systems to allow proper -activation of the required platform drivers. - -Signed-off-by: Vadim Pasternak ---- - drivers/platform/mellanox/mlx-platform.c | 927 +++++++++++++++++++++-- - 1 file changed, 860 insertions(+), 67 deletions(-) - -diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index cafa4f762..0949f32ad 100644 ---- a/drivers/platform/mellanox/mlx-platform.c -+++ b/drivers/platform/mellanox/mlx-platform.c -@@ -39,6 +39,7 @@ - #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET 0x0b - #define MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET 0x17 - #define MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET 0x19 -+#define MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET 0x1b - #define MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET 0x1c - #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d - #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e -@@ -54,6 +55,7 @@ - #define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a - #define MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET 0x2b - #define MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET 0x2d -+#define MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET 0x2c - #define MLXPLAT_CPLD_LPC_REG_GP0_OFFSET 0x2e - #define MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET 0x2f - #define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30 -@@ -73,12 +75,14 @@ - #define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0x43 - #define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0x44 - #define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0x45 -+#define MLXPLAT_CPLD_LPC_REG_GP3_OFFSET 0x46 - #define MLXPLAT_CPLD_LPC_REG_BRD_OFFSET 0x47 - #define MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET 0x48 - #define MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET 0x49 - #define MLXPLAT_CPLD_LPC_REG_GWP_OFFSET 0x4a - #define MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET 0x4b - #define MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET 0x4c -+#define MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET 0x4e - #define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50 - #define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51 - #define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52 -@@ -90,9 +94,11 @@ - #define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58 - #define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59 - #define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a -+#define MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET 0x5e - #define MLXPLAT_CPLD_LPC_REG_PWR_OFFSET 0x64 - #define MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET 0x65 - #define MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET 0x66 -+#define MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET 0x6a - #define MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET 0x70 - #define MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET 0x71 - #define MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET 0x72 -@@ -234,9 +240,15 @@ - #define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04 - #define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0) - #define MLXPLAT_CPLD_AGGR_MASK_LC BIT(3) -+#define MLXPLAT_CPLD_AGGR_MASK_DPU_BRD BIT(4) -+#define MLXPLAT_CPLD_AGGR_MASK_DPU_CORE BIT(5) - #define MLXPLAT_CPLD_AGGR_MASK_MODULAR (MLXPLAT_CPLD_AGGR_MASK_NG_DEF | \ - MLXPLAT_CPLD_AGGR_MASK_COMEX | \ - MLXPLAT_CPLD_AGGR_MASK_LC) -+#define MLXPLAT_CPLD_AGGR_MASK_SMART_SW (MLXPLAT_CPLD_AGGR_MASK_COMEX | \ -+ MLXPLAT_CPLD_AGGR_MASK_NG_DEF | \ -+ MLXPLAT_CPLD_AGGR_MASK_DPU_BRD | \ -+ MLXPLAT_CPLD_AGGR_MASK_DPU_CORE) - #define MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT BIT(0) - #define MLXPLAT_CPLD_AGGR_MASK_LC_RDY BIT(1) - #define MLXPLAT_CPLD_AGGR_MASK_LC_PG BIT(2) -@@ -279,6 +291,8 @@ - #define MLXPLAT_CPLD_PSU_CAP_MASK GENMASK(3, 0) - #define MLXPLAT_CPLD_FAN_CAP_MASK GENMASK(7, 0) - #define MLXPLAT_CPLD_ASIC_CAP_MASK GENMASK(7, 0) -+#define MLXPLAT_CPLD_BIOS_STATUS_MASK GENMASK(3, 1) -+#define MLXPLAT_CPLD_DPU_MASK GENMASK(3, 0) - #define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0) - #define MLXPLAT_CPLD_LATCH_RST_MASK BIT(6) - #define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3) -@@ -302,6 +316,9 @@ - /* Masks for aggregation for modular systems */ - #define MLXPLAT_CPLD_LPC_LC_MASK GENMASK(7, 0) - -+/* Masks for aggregation for smart switch systems */ -+#define MLXPLAT_CPLD_LPC_SM_SW_MASK GENMASK(7, 0) -+ - #define MLXPLAT_CPLD_HALT_MASK BIT(3) - #define MLXPLAT_CPLD_RESET_MASK GENMASK(7, 1) - -@@ -341,9 +358,11 @@ - #define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14 - #define MLXPLAT_CPLD_NR_ASIC 3 - #define MLXPLAT_CPLD_NR_LC_BASE 34 -+#define MLXPLAT_CPLD_NR_DPU_BASE 18 - - #define MLXPLAT_CPLD_NR_LC_SET(nr) (MLXPLAT_CPLD_NR_LC_BASE + (nr)) - #define MLXPLAT_CPLD_LC_ADDR 0x32 -+#define MLXPLAT_CPLD_DPU_ADDR 0x68 - - /* Masks and default values for watchdogs */ - #define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1) -@@ -358,6 +377,7 @@ - #define MLXPLAT_CPLD_WD_DFLT_TIMEOUT 30 - #define MLXPLAT_CPLD_WD3_DFLT_TIMEOUT 600 - #define MLXPLAT_CPLD_WD_MAX_DEVS 2 -+#define MLXPLAT_CPLD_DPU_MAX_DEVS 4 - - #define MLXPLAT_CPLD_LPC_SYSIRQ 17 - -@@ -399,6 +419,7 @@ - * @pdev_io_regs - register access platform devices - * @pdev_fan - FAN platform devices - * @pdev_wd - array of watchdog platform devices -+ * pdev_dpu - array of Data Processor Unit platform devices - * @regmap: device register map - * @hotplug_resources: system hotplug resources - * @hotplug_resources_size: size of system hotplug resources -@@ -414,6 +435,7 @@ struct mlxplat_priv { - struct platform_device *pdev_io_regs; - struct platform_device *pdev_fan; - struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS]; -+ struct platform_device *pdev_dpu[MLXPLAT_CPLD_DPU_MAX_DEVS]; - void *regmap; - struct resource *hotplug_resources; - unsigned int hotplug_resources_size; -@@ -2941,6 +2963,212 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_rack_switch_data = { - .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, - }; - -+/* Platform hotplug for smart switch systems families data */ -+static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_dpu_ready_data[] = { -+ { -+ .label = "dpu1_ready", -+ .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, -+ .mask = BIT(0), -+ .slot = 1, -+ .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_DPU_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "dpu2_ready", -+ .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, -+ .mask = BIT(1), -+ .slot = 2, -+ .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_DPU_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "dpu3_ready", -+ .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, -+ .mask = BIT(2), -+ .slot = 3, -+ .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_DPU_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "dpu4_ready", -+ .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, -+ .mask = BIT(3), -+ .slot = 4, -+ .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_DPU_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+}; -+ -+static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_dpu_shtdn_ready_data[] = { -+ { -+ .label = "dpu1_shtdn_ready", -+ .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, -+ .mask = BIT(0), -+ .slot = 1, -+ .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_DPU_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "dpu2_shtdn_ready", -+ .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, -+ .mask = BIT(1), -+ .slot = 2, -+ .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_DPU_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "dpu3_shtdn_ready", -+ .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, -+ .mask = BIT(2), -+ .slot = 3, -+ .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_DPU_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "dpu4_shtdn_ready", -+ .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, -+ .mask = BIT(3), -+ .slot = 4, -+ .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_DPU_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+}; -+ -+static struct mlxreg_core_item mlxplat_mlxcpld_smart_switch_items[] = { -+ { -+ .data = mlxplat_mlxcpld_xdr_psu_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, -+ .mask = MLXPLAT_CPLD_PSU_XDR_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_psu_items_data), -+ .inversed = 1, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_xdr_pwr_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, -+ .mask = MLXPLAT_CPLD_PWR_XDR_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_pwr_items_data), -+ .inversed = 0, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_xdr_fan_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .mask = MLXPLAT_CPLD_FAN_XDR_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_FAN_CAP_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_items_data), -+ .inversed = 1, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_xdr_asic1_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, -+ .mask = MLXPLAT_CPLD_ASIC_XDR_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_asic1_items_data), -+ .inversed = 0, -+ .health = true, -+ }, -+ { -+ .data = mlxplat_mlxcpld_smart_switch_dpu_ready_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_DPU_CORE, -+ .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, -+ .mask = MLXPLAT_CPLD_DPU_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_DPU_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_dpu_ready_data), -+ .inversed = 1, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_smart_switch_dpu_shtdn_ready_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_DPU_CORE, -+ .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, -+ .mask = MLXPLAT_CPLD_DPU_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_DPU_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_dpu_shtdn_ready_data), -+ .inversed = 1, -+ .health = false, -+ }, -+}; -+ -+static -+struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_smart_switch_data = { -+ .items = mlxplat_mlxcpld_smart_switch_items, -+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_items), -+ .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, -+ .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX | -+ MLXPLAT_CPLD_AGGR_MASK_DPU_BRD | MLXPLAT_CPLD_AGGR_MASK_DPU_CORE, -+ .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, -+ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, -+}; -+ -+/* Smart switch data processor units data */ -+static struct i2c_board_info mlxplat_mlxcpld_smart_switch_dpu_devs[] = { -+ { -+ I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR), -+ .irq = MLXPLAT_CPLD_LPC_SYSIRQ, -+ }, -+ { -+ I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR), -+ .irq = MLXPLAT_CPLD_LPC_SYSIRQ, -+ }, -+ { -+ I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR), -+ .irq = MLXPLAT_CPLD_LPC_SYSIRQ, -+ }, -+ { -+ I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR), -+ .irq = MLXPLAT_CPLD_LPC_SYSIRQ, -+ }, -+}; -+ -+static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_dpu_data[] = { -+ { -+ .label = "dpu1", -+ .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[0], -+ .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE, -+ .slot = 1, -+ }, -+ { -+ .label = "dpu2", -+ .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[1], -+ .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE + 1, -+ .slot = 2, -+ }, -+ { -+ .label = "dpu3", -+ .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[2], -+ .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE + 2, -+ .slot = 3, -+ }, -+ { -+ .label = "dpu4", -+ .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[2], -+ .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE + 3, -+ .slot = 4, -+ }, -+}; -+ - /* Callback performs graceful shutdown after notification about power button event */ - static int - mlxplat_mlxcpld_l1_switch_pwr_events_handler(void *handle, enum mlxreg_hotplug_kind kind, -@@ -5431,99 +5659,573 @@ static struct mlxreg_core_platform_data mlxplat_chassis_blade_regs_io_data = { - .counter = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_regs_io_data), - }; - --/* Platform FAN default */ --static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = { -+/* Platform register access for smart switch systems families data */ -+static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_regs_io_data[] = { - { -- .label = "pwm1", -- .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, -+ .label = "cpld1_version", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, - }, - { -- .label = "pwm2", -- .reg = MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET, -+ .label = "cpld2_version", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, - }, - { -- .label = "pwm3", -- .reg = MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET, -+ .label = "cpld3_version", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, - }, - { -- .label = "pwm4", -- .reg = MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET, -+ .label = "cpld1_pn", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, -+ .bit = GENMASK(15, 0), -+ .mode = 0444, -+ .regnum = 2, - }, - { -- .label = "tacho1", -- .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET, -- .mask = GENMASK(7, 0), -- .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -- .bit = BIT(0), -- .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -- -+ .label = "cpld2_pn", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, -+ .bit = GENMASK(15, 0), -+ .mode = 0444, -+ .regnum = 2, - }, - { -- .label = "tacho2", -- .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET, -- .mask = GENMASK(7, 0), -- .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -- .bit = BIT(1), -- .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .label = "cpld3_pn", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, -+ .bit = GENMASK(15, 0), -+ .mode = 0444, -+ .regnum = 2, - }, - { -- .label = "tacho3", -- .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET, -- .mask = GENMASK(7, 0), -- .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -- .bit = BIT(2), -- .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .label = "cpld1_version_min", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, - }, - { -- .label = "tacho4", -- .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET, -- .mask = GENMASK(7, 0), -- .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -- .bit = BIT(3), -- .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .label = "cpld2_version_min", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, - }, - { -- .label = "tacho5", -- .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET, -- .mask = GENMASK(7, 0), -- .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -- .bit = BIT(4), -- .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .label = "cpld3_version_min", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, - }, - { -- .label = "tacho6", -- .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET, -- .mask = GENMASK(7, 0), -- .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -- .bit = BIT(5), -- .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .label = "kexec_activated", -+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0644, - }, - { -- .label = "tacho7", -- .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET, -- .mask = GENMASK(7, 0), -- .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -- .bit = BIT(6), -- .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .label = "asic_reset", -+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0644, - }, - { -- .label = "tacho8", -- .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET, -- .mask = GENMASK(7, 0), -- .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -- .bit = BIT(7), -- .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .label = "eth_switch_reset", -+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0644, - }, - { -- .label = "tacho9", -- .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET, -- .mask = GENMASK(7, 0), -- .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, -- .bit = BIT(0), -- .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .label = "dpu1_rst", -+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0644, - }, - { -- .label = "tacho10", -+ .label = "dpu2_rst", -+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0644, -+ }, -+ { -+ .label = "dpu3_rst", -+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0644, -+ }, -+ { -+ .label = "dpu4_rst", -+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0644, -+ }, -+ { -+ .label = "dpu1_pwr", -+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0644, -+ }, -+ { -+ .label = "dpu2_pwr", -+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0644, -+ }, -+ { -+ .label = "dpu3_pwr", -+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0644, -+ }, -+ { -+ .label = "dpu4_pwr", -+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0644, -+ }, -+ { -+ .label = "reset_long_pb", -+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0444, -+ }, -+ { -+ .label = "reset_short_pb", -+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0444, -+ }, -+ { -+ .label = "reset_aux_pwr_or_ref", -+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0444, -+ }, -+ { -+ .label = "reset_swb_dc_dc_pwr_fail", -+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0444, -+ }, -+ { -+ .label = "reset_swb_wd", -+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(6), -+ .mode = 0444, -+ }, -+ { -+ .label = "reset_asic_thermal", -+ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), -+ .mode = 0444, -+ }, -+ { -+ .label = "reset_sw_reset", -+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0444, -+ }, -+ { -+ .label = "reset_aux_pwr_or_reload", -+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0444, -+ }, -+ { -+ .label = "reset_comex_pwr_fail", -+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0444, -+ }, -+ { -+ .label = "reset_platform", -+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0444, -+ }, -+ { -+ .label = "reset_soc", -+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0444, -+ }, -+ { -+ .label = "reset_pwr", -+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), -+ .mode = 0444, -+ }, -+ { -+ .label = "reset_pwr_converter_fail", -+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0444, -+ }, -+ { -+ .label = "reset_system", -+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0444, -+ }, -+ { -+ .label = "reset_sw_pwr_off", -+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0444, -+ }, -+ { -+ .label = "reset_comex_thermal", -+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0444, -+ }, -+ { -+ .label = "reset_ac_pwr_fail", -+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(6), -+ .mode = 0444, -+ }, -+ { -+ .label = "voltreg_update_status", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, -+ .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, -+ .bit = 5, -+ .mode = 0444, -+ }, -+ { -+ .label = "port80", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, -+ { -+ .label = "bios_status", -+ .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, -+ .mask = MLXPLAT_CPLD_BIOS_STATUS_MASK, -+ .bit = 2, -+ .mode = 0444, -+ }, -+ { -+ .label = "bios_start_retry", -+ .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0444, -+ }, -+ { -+ .label = "bios_active_image", -+ .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0444, -+ }, -+ { -+ .label = "vpd_wp", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0644, -+ }, -+ { -+ .label = "pcie_asic_reset_dis", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0644, -+ }, -+ { -+ .label = "shutdown_unlock", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0644, -+ }, -+ { -+ .label = "fan_dir", -+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, -+ { -+ .label = "dpu1_rst_en", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0200, -+ }, -+ { -+ .label = "dpu2_rst_en", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0200, -+ }, -+ { -+ .label = "dpu3_rst_en", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0200, -+ }, -+ { -+ .label = "dpu4_rst_en", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0200, -+ }, -+ { -+ .label = "psu1_on", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0200, -+ }, -+ { -+ .label = "psu2_on", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0200, -+ }, -+ { -+ .label = "pwr_cycle", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0200, -+ }, -+ { -+ .label = "pwr_down", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0200, -+ }, -+ { -+ .label = "jtag_cap", -+ .reg = MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET, -+ .mask = MLXPLAT_CPLD_FU_CAP_MASK, -+ .bit = 1, -+ .mode = 0444, -+ }, -+ { -+ .label = "jtag_enable", -+ .reg = MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE, -+ .mask = GENMASK(1, 0), -+ .bit = 1, -+ .mode = 0644, -+ }, -+ { -+ .label = "non_active_bios_select", -+ .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0644, -+ }, -+ { -+ .label = "bios_upgrade_fail", -+ .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0444, -+ }, -+ { -+ .label = "bios_image_invert", -+ .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(6), -+ .mode = 0644, -+ }, -+ { -+ .label = "me_reboot", -+ .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), -+ .mode = 0644, -+ }, -+ { -+ .label = "dpu1_pwr_force", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0644, -+ }, -+ { -+ .label = "dpu2_pwr_force", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0644, -+ }, -+ { -+ .label = "dpu3_pwr_force", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0644, -+ }, -+ { -+ .label = "dpu4_pwr_force", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), -+ .mode = 0644, -+ }, -+ { -+ .label = "ufm_done", -+ .reg = MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, -+ { -+ .label = "asic_health", -+ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, -+ .mask = MLXPLAT_CPLD_ASIC_MASK, -+ .bit = 1, -+ .mode = 0444, -+ }, -+ { -+ .label = "psu1_ac_ok", -+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0644, -+ }, -+ { -+ .label = "psu2_ac_ok", -+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0644, -+ }, -+ { -+ .label = "psu1_no_alert", -+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0644, -+ }, -+ { -+ .label = "psu2_no_alert", -+ .reg = MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0644, -+ }, -+ { -+ .label = "asic_pg_fail", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), -+ .mode = 0444, -+ }, -+ { -+ .label = "spi_chnl_select", -+ .reg = MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT, -+ .mask = GENMASK(7, 0), -+ .bit = 1, -+ .mode = 0644, -+ }, -+ { -+ .label = "config1", -+ .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, -+ { -+ .label = "config2", -+ .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, -+ { -+ .label = "config3", -+ .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, -+ { -+ .label = "ufm_version", -+ .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, -+}; -+ -+static struct mlxreg_core_platform_data mlxplat_smart_switch_regs_io_data = { -+ .data = mlxplat_mlxcpld_smart_switch_regs_io_data, -+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_regs_io_data), -+}; -+ -+/* Platform FAN default */ -+static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = { -+ { -+ .label = "pwm1", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, -+ }, -+ { -+ .label = "pwm2", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET, -+ }, -+ { -+ .label = "pwm3", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET, -+ }, -+ { -+ .label = "pwm4", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET, -+ }, -+ { -+ .label = "tacho1", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .bit = BIT(0), -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ -+ }, -+ { -+ .label = "tacho2", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .bit = BIT(1), -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho3", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .bit = BIT(2), -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho4", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .bit = BIT(3), -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho5", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .bit = BIT(4), -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho6", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .bit = BIT(5), -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho7", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .bit = BIT(6), -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho8", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, -+ .bit = BIT(7), -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho9", -+ .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET, -+ .mask = GENMASK(7, 0), -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, -+ .bit = BIT(0), -+ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ }, -+ { -+ .label = "tacho10", - .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET, - .mask = GENMASK(7, 0), - .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, -@@ -5975,6 +6677,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) - { - switch (reg) { - case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: -@@ -5990,6 +6694,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_GP3_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: - case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: - case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: -@@ -6017,8 +6722,10 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_ASIC4_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET: -@@ -6094,6 +6801,8 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_CPLD6_PN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD6_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: -@@ -6109,12 +6818,14 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: - case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_GP3_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: - case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: - case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: -@@ -6134,6 +6845,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: - case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: -@@ -6152,9 +6864,11 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: -@@ -6280,6 +6994,8 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_CPLD6_PN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD6_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: -@@ -6295,10 +7011,12 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: - case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_GP3_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: - case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: - case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: -@@ -6318,6 +7036,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: - case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: -@@ -6336,9 +7055,11 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: -@@ -6489,6 +7210,15 @@ static const struct reg_default mlxplat_mlxcpld_regmap_eth_modular[] = { - MLXPLAT_CPLD_AGGR_MASK_LC_LOW }, - }; - -+static const struct reg_default mlxplat_mlxcpld_regmap_smart_switch[] = { -+ { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, -+ { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, -+ { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, -+ { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, -+ { MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET, -+ MLXPLAT_CPLD_LPC_SM_SW_MASK }, -+}; -+ - struct mlxplat_mlxcpld_regmap_context { - void __iomem *base; - }; -@@ -6597,6 +7327,20 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config_eth_modular = { - .reg_write = mlxplat_mlxcpld_reg_write, - }; - -+static const struct regmap_config mlxplat_mlxcpld_regmap_config_smart_switch = { -+ .reg_bits = 8, -+ .val_bits = 8, -+ .max_register = 255, -+ .cache_type = REGCACHE_FLAT, -+ .writeable_reg = mlxplat_mlxcpld_writeable_reg, -+ .readable_reg = mlxplat_mlxcpld_readable_reg, -+ .volatile_reg = mlxplat_mlxcpld_volatile_reg, -+ .reg_defaults = mlxplat_mlxcpld_regmap_smart_switch, -+ .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_smart_switch), -+ .reg_read = mlxplat_mlxcpld_reg_read, -+ .reg_write = mlxplat_mlxcpld_reg_write, -+}; -+ - /* Wait completion routine for indirect access for register map */ - static int mlxplat_fpga_completion_wait(struct mlxplat_mlxcpld_regmap_context *ctx) - { -@@ -6716,6 +7460,7 @@ static struct mlxreg_core_platform_data *mlxplat_regs_io; - static struct mlxreg_core_platform_data *mlxplat_fan; - static struct mlxreg_core_platform_data - *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS]; -+static struct mlxreg_core_data *mlxplat_dpu_data[MLXPLAT_CPLD_DPU_MAX_DEVS]; - static const struct regmap_config *mlxplat_regmap_config; - static struct pci_dev *lpc_bridge; - static struct pci_dev *i2c_bridge; -@@ -7140,6 +7885,29 @@ static int __init mlxplat_dmi_xdr_matched(const struct dmi_system_id *dmi) - return mlxplat_register_platform_device(); - } - -+static int __init mlxplat_dmi_smart_switch_matched(const struct dmi_system_id *dmi) -+{ -+ int i; -+ -+ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; -+ mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data); -+ mlxplat_mux_data = mlxplat_ng800_mux_data; -+ mlxplat_hotplug = &mlxplat_mlxcpld_smart_switch_data; -+ mlxplat_hotplug->deferred_nr = -+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; -+ mlxplat_led = &mlxplat_xdr_led_data; -+ mlxplat_regs_io = &mlxplat_smart_switch_regs_io_data; -+ mlxplat_fan = &mlxplat_xdr_fan_data; -+ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) -+ mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; -+ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_dpu_data); i++) -+ mlxplat_dpu_data[i] = &mlxplat_mlxcpld_smart_switch_dpu_data[i]; -+ mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; -+ mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_smart_switch; -+ -+ return mlxplat_register_platform_device(); -+} -+ - static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { - { - .callback = mlxplat_dmi_default_wc_matched, -@@ -7246,6 +8014,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { - DMI_MATCH(DMI_BOARD_NAME, "VMOD0018"), - }, - }, -+ { -+ .callback = mlxplat_dmi_smart_switch_matched, -+ .matches = { -+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0019"), -+ }, -+ }, - { - .callback = mlxplat_dmi_msn274x_matched, - .matches = { -@@ -7547,7 +8321,7 @@ static void mlxplat_post_exit(void) - - static int mlxplat_post_init(struct mlxplat_priv *priv) - { -- int i = 0, err; -+ int i, j, err; - - /* Add hotplug driver */ - if (mlxplat_hotplug) { -@@ -7624,8 +8398,25 @@ static int mlxplat_post_init(struct mlxplat_priv *priv) - } - } - -+ /* Add DPU drivers. */ -+ for (j = 0; j < MLXPLAT_CPLD_DPU_MAX_DEVS; j++) { -+ if (mlxplat_dpu_data[j]) { -+ priv->pdev_dpu[j] = -+ platform_device_register_resndata(&mlxplat_dev->dev, "mlxreg-dpu", -+ j, NULL, 0, mlxplat_dpu_data[j], -+ sizeof(*mlxplat_dpu_data[j])); -+ if (IS_ERR(priv->pdev_dpu[j])) { -+ err = PTR_ERR(priv->pdev_dpu[j]); -+ goto fail_platform_dpu_register; -+ } -+ } -+ } -+ - return 0; - -+fail_platform_dpu_register: -+ while (--j >= 0) -+ platform_device_unregister(priv->pdev_dpu[j]); - fail_platform_wd_register: - while (--i >= 0) - platform_device_unregister(priv->pdev_wd[i]); -@@ -7646,6 +8437,8 @@ static void mlxplat_pre_exit(struct mlxplat_priv *priv) - { - int i; - -+ for (i = MLXPLAT_CPLD_DPU_MAX_DEVS - 1; i >= 0 ; i--) -+ platform_device_unregister(priv->pdev_dpu[i]); - for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--) - platform_device_unregister(priv->pdev_wd[i]); - if (priv->pdev_fan) --- -2.44.0 - diff --git a/patch/driver-ixgbe-external-phy.patch b/patch/driver-ixgbe-external-phy.patch deleted file mode 100644 index c5a866b6c..000000000 --- a/patch/driver-ixgbe-external-phy.patch +++ /dev/null @@ -1,37 +0,0 @@ -Signed-off-by: Jostar Yang - -From: Jostar Yang - - ---- - drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c | 3 +++ - drivers/net/ethernet/intel/ixgbe/ixgbe_type.h | 2 ++ - 2 files changed, 5 insertions(+) - -diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c -index fc389eecd..cb685e917 100644 ---- a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c -+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c -@@ -380,6 +380,9 @@ static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) - case X557_PHY_ID2: - phy_type = ixgbe_phy_x550em_ext_t; - break; -+ case BCM54616S_E_PHY_ID: -+ phy_type = ixgbe_phy_ext_1g_t; -+ break; - default: - phy_type = ixgbe_phy_unknown; - break; -diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h -index 2be1c4c72..fad8b436c 100644 ---- a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h -+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h -@@ -1408,6 +1408,8 @@ struct ixgbe_nvm_version { - #define ATH_PHY_ID 0x03429050 - #define AQ_FW_REV 0x20 - -+#define BCM54616S_E_PHY_ID 0x03625D10 -+ - /* Special PHY Init Routine */ - #define IXGBE_PHY_INIT_OFFSET_NL 0x002B - #define IXGBE_PHY_INIT_END_NL 0xFFFF diff --git a/patch/hwmon-Add-Maxim-MAX6620-hardware-monitoring-driver.patch b/patch/hwmon-Add-Maxim-MAX6620-hardware-monitoring-driver.patch deleted file mode 100644 index ff2b3d5d9..000000000 --- a/patch/hwmon-Add-Maxim-MAX6620-hardware-monitoring-driver.patch +++ /dev/null @@ -1,644 +0,0 @@ -From e8ac01e5db329cf4ac2b36ef66b9d877330a990c Mon Sep 17 00:00:00 2001 -From: Arun Saravanan Balachandran -Date: Mon, 13 Sep 2021 13:40:15 +0000 -Subject: hwmon: Add Maxim MAX6620 hardware monitoring driver - -commit https://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git/commit/?h=hwmon-next&id=e8ac01e5db329cf4ac2b36ef66b9d877330a990c upstream - -Add hardware monitoring driver for Maxim MAX6620 Fan controller - -Originally-from: L. Grunenberg -Originally-from: Cumulus Networks -Originally-from: Shuotian Cheng -Signed-off-by: Arun Saravanan Balachandran -Signed-off-by: Guenter Roeck ---- - Documentation/hwmon/index.rst | 1 + - Documentation/hwmon/max6620.rst | 46 ++++ - drivers/hwmon/Kconfig | 10 + - drivers/hwmon/Makefile | 1 + - drivers/hwmon/max6620.c | 514 ++++++++++++++++++++++++++++++++++++++++ - 5 files changed, 572 insertions(+) - create mode 100644 Documentation/hwmon/max6620.rst - create mode 100644 drivers/hwmon/max6620.c - -diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst -index f790f1260c33a..7046bf1870d96 100644 ---- a/Documentation/hwmon/index.rst -+++ b/Documentation/hwmon/index.rst -@@ -130,6 +130,7 @@ Hardware Monitoring Kernel Drivers - max31785 - max31790 - max34440 -+ max6620 - max6639 - max6642 - max6650 -diff --git a/Documentation/hwmon/max6620.rst b/Documentation/hwmon/max6620.rst -new file mode 100644 -index 0000000000000..84c1c44d3de4d ---- /dev/null -+++ b/Documentation/hwmon/max6620.rst -@@ -0,0 +1,46 @@ -+.. SPDX-License-Identifier: GPL-2.0-or-later -+ -+Kernel driver max6620 -+===================== -+ -+Supported chips: -+ -+ Maxim MAX6620 -+ -+ Prefix: 'max6620' -+ -+ Addresses scanned: none -+ -+ Datasheet: http://pdfserv.maxim-ic.com/en/ds/MAX6620.pdf -+ -+Authors: -+ - L\. Grunenberg -+ - Cumulus Networks -+ - Shuotian Cheng -+ - Arun Saravanan Balachandran -+ -+Description -+----------- -+ -+This driver implements support for Maxim MAX6620 fan controller. -+ -+The driver configures the fan controller in RPM mode. To give the readings more -+range or accuracy, the desired value can be set by a programmable register -+(1, 2, 4, 8, 16 or 32). Set higher values for larger speeds. -+ -+The driver provides the following sensor access in sysfs: -+ -+================ ======= ===================================================== -+fan[1-4]_alarm ro Fan alarm. -+fan[1-4]_div rw Sets the nominal RPM range of the fan. Valid values -+ are 1, 2, 4, 8, 16 and 32. -+fan[1-4]_input ro Fan speed in RPM. -+fan[1-4]_target rw Desired fan speed in RPM. -+================ ======= ===================================================== -+ -+Usage notes -+----------- -+ -+This driver does not auto-detect devices. You will have to instantiate the -+devices explicitly. Please see Documentation/i2c/instantiating-devices.rst for -+details. -diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig -index c4578e8f34bb5..91ec36aac059e 100644 ---- a/drivers/hwmon/Kconfig -+++ b/drivers/hwmon/Kconfig -@@ -1032,6 +1032,16 @@ config SENSORS_MAX31730 - This driver can also be built as a module. If so, the module - will be called max31730. - -+config SENSORS_MAX6620 -+ tristate "Maxim MAX6620 fan controller" -+ depends on I2C -+ help -+ If you say yes here you get support for the MAX6620 -+ fan controller. -+ -+ This driver can also be built as a module. If so, the module -+ will be called max6620. -+ - config SENSORS_MAX6621 - tristate "Maxim MAX6621 sensor chip" - depends on I2C -diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile -index 1629402706616..baee6a8d4dd12 100644 ---- a/drivers/hwmon/Makefile -+++ b/drivers/hwmon/Makefile -@@ -135,6 +135,7 @@ obj-$(CONFIG_SENSORS_MAX1668) += max1668.o - obj-$(CONFIG_SENSORS_MAX197) += max197.o - obj-$(CONFIG_SENSORS_MAX31722) += max31722.o - obj-$(CONFIG_SENSORS_MAX31730) += max31730.o -+obj-$(CONFIG_SENSORS_MAX6620) += max6620.o - obj-$(CONFIG_SENSORS_MAX6621) += max6621.o - obj-$(CONFIG_SENSORS_MAX6639) += max6639.o - obj-$(CONFIG_SENSORS_MAX6642) += max6642.o -diff --git a/drivers/hwmon/max6620.c b/drivers/hwmon/max6620.c -new file mode 100644 -index 0000000000000..202b6438179d1 ---- /dev/null -+++ b/drivers/hwmon/max6620.c -@@ -0,0 +1,514 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Hardware monitoring driver for Maxim MAX6620 -+ * -+ * Originally from L. Grunenberg. -+ * (C) 2012 by L. Grunenberg -+ * -+ * Copyright (c) 2021 Dell Inc. or its subsidiaries. All Rights Reserved. -+ * -+ * based on code written by : -+ * 2007 by Hans J. Koch -+ * John Morris -+ * Copyright (c) 2003 Spirent Communications -+ * and Claus Gindhart -+ * -+ * This module has only been tested with the MAX6620 chip. -+ * -+ * The datasheet was last seen at: -+ * -+ * http://pdfserv.maxim-ic.com/en/ds/MAX6620.pdf -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * MAX 6620 registers -+ */ -+ -+#define MAX6620_REG_CONFIG 0x00 -+#define MAX6620_REG_FAULT 0x01 -+#define MAX6620_REG_CONF_FAN0 0x02 -+#define MAX6620_REG_CONF_FAN1 0x03 -+#define MAX6620_REG_CONF_FAN2 0x04 -+#define MAX6620_REG_CONF_FAN3 0x05 -+#define MAX6620_REG_DYN_FAN0 0x06 -+#define MAX6620_REG_DYN_FAN1 0x07 -+#define MAX6620_REG_DYN_FAN2 0x08 -+#define MAX6620_REG_DYN_FAN3 0x09 -+#define MAX6620_REG_TACH0 0x10 -+#define MAX6620_REG_TACH1 0x12 -+#define MAX6620_REG_TACH2 0x14 -+#define MAX6620_REG_TACH3 0x16 -+#define MAX6620_REG_VOLT0 0x18 -+#define MAX6620_REG_VOLT1 0x1A -+#define MAX6620_REG_VOLT2 0x1C -+#define MAX6620_REG_VOLT3 0x1E -+#define MAX6620_REG_TAR0 0x20 -+#define MAX6620_REG_TAR1 0x22 -+#define MAX6620_REG_TAR2 0x24 -+#define MAX6620_REG_TAR3 0x26 -+#define MAX6620_REG_DAC0 0x28 -+#define MAX6620_REG_DAC1 0x2A -+#define MAX6620_REG_DAC2 0x2C -+#define MAX6620_REG_DAC3 0x2E -+ -+/* -+ * Config register bits -+ */ -+ -+#define MAX6620_CFG_RUN BIT(7) -+#define MAX6620_CFG_POR BIT(6) -+#define MAX6620_CFG_TIMEOUT BIT(5) -+#define MAX6620_CFG_FULLFAN BIT(4) -+#define MAX6620_CFG_OSC BIT(3) -+#define MAX6620_CFG_WD_MASK (BIT(2) | BIT(1)) -+#define MAX6620_CFG_WD_2 BIT(1) -+#define MAX6620_CFG_WD_6 BIT(2) -+#define MAX6620_CFG_WD10 (BIT(2) | BIT(1)) -+#define MAX6620_CFG_WD BIT(0) -+ -+/* -+ * Failure status register bits -+ */ -+ -+#define MAX6620_FAIL_TACH0 BIT(4) -+#define MAX6620_FAIL_TACH1 BIT(5) -+#define MAX6620_FAIL_TACH2 BIT(6) -+#define MAX6620_FAIL_TACH3 BIT(7) -+#define MAX6620_FAIL_MASK0 BIT(0) -+#define MAX6620_FAIL_MASK1 BIT(1) -+#define MAX6620_FAIL_MASK2 BIT(2) -+#define MAX6620_FAIL_MASK3 BIT(3) -+ -+#define MAX6620_CLOCK_FREQ 8192 /* Clock frequency in Hz */ -+#define MAX6620_PULSE_PER_REV 2 /* Tachometer pulses per revolution */ -+ -+/* Minimum and maximum values of the FAN-RPM */ -+#define FAN_RPM_MIN 240 -+#define FAN_RPM_MAX 30000 -+ -+static const u8 config_reg[] = { -+ MAX6620_REG_CONF_FAN0, -+ MAX6620_REG_CONF_FAN1, -+ MAX6620_REG_CONF_FAN2, -+ MAX6620_REG_CONF_FAN3, -+}; -+ -+static const u8 dyn_reg[] = { -+ MAX6620_REG_DYN_FAN0, -+ MAX6620_REG_DYN_FAN1, -+ MAX6620_REG_DYN_FAN2, -+ MAX6620_REG_DYN_FAN3, -+}; -+ -+static const u8 tach_reg[] = { -+ MAX6620_REG_TACH0, -+ MAX6620_REG_TACH1, -+ MAX6620_REG_TACH2, -+ MAX6620_REG_TACH3, -+}; -+ -+static const u8 target_reg[] = { -+ MAX6620_REG_TAR0, -+ MAX6620_REG_TAR1, -+ MAX6620_REG_TAR2, -+ MAX6620_REG_TAR3, -+}; -+ -+/* -+ * Client data (each client gets its own) -+ */ -+ -+struct max6620_data { -+ struct i2c_client *client; -+ struct mutex update_lock; -+ bool valid; /* false until following fields are valid */ -+ unsigned long last_updated; /* in jiffies */ -+ -+ /* register values */ -+ u8 fancfg[4]; -+ u8 fandyn[4]; -+ u8 fault; -+ u16 tach[4]; -+ u16 target[4]; -+}; -+ -+static u8 max6620_fan_div_from_reg(u8 val) -+{ -+ return BIT((val & 0xE0) >> 5); -+} -+ -+static u16 max6620_fan_rpm_to_tach(u8 div, int rpm) -+{ -+ return (60 * div * MAX6620_CLOCK_FREQ) / (rpm * MAX6620_PULSE_PER_REV); -+} -+ -+static int max6620_fan_tach_to_rpm(u8 div, u16 tach) -+{ -+ return (60 * div * MAX6620_CLOCK_FREQ) / (tach * MAX6620_PULSE_PER_REV); -+} -+ -+static int max6620_update_device(struct device *dev) -+{ -+ struct max6620_data *data = dev_get_drvdata(dev); -+ struct i2c_client *client = data->client; -+ int i; -+ int ret = 0; -+ -+ mutex_lock(&data->update_lock); -+ -+ if (time_after(jiffies, data->last_updated + HZ) || !data->valid) { -+ for (i = 0; i < 4; i++) { -+ ret = i2c_smbus_read_byte_data(client, config_reg[i]); -+ if (ret < 0) -+ goto error; -+ data->fancfg[i] = ret; -+ -+ ret = i2c_smbus_read_byte_data(client, dyn_reg[i]); -+ if (ret < 0) -+ goto error; -+ data->fandyn[i] = ret; -+ -+ ret = i2c_smbus_read_byte_data(client, tach_reg[i]); -+ if (ret < 0) -+ goto error; -+ data->tach[i] = (ret << 3) & 0x7f8; -+ ret = i2c_smbus_read_byte_data(client, tach_reg[i] + 1); -+ if (ret < 0) -+ goto error; -+ data->tach[i] |= (ret >> 5) & 0x7; -+ -+ ret = i2c_smbus_read_byte_data(client, target_reg[i]); -+ if (ret < 0) -+ goto error; -+ data->target[i] = (ret << 3) & 0x7f8; -+ ret = i2c_smbus_read_byte_data(client, target_reg[i] + 1); -+ if (ret < 0) -+ goto error; -+ data->target[i] |= (ret >> 5) & 0x7; -+ } -+ -+ /* -+ * Alarms are cleared on read in case the condition that -+ * caused the alarm is removed. Keep the value latched here -+ * for providing the register through different alarm files. -+ */ -+ ret = i2c_smbus_read_byte_data(client, MAX6620_REG_FAULT); -+ if (ret < 0) -+ goto error; -+ data->fault |= (ret >> 4) & (ret & 0x0F); -+ -+ data->last_updated = jiffies; -+ data->valid = true; -+ } -+ -+error: -+ mutex_unlock(&data->update_lock); -+ return ret; -+} -+ -+static umode_t -+max6620_is_visible(const void *data, enum hwmon_sensor_types type, u32 attr, -+ int channel) -+{ -+ switch (type) { -+ case hwmon_fan: -+ switch (attr) { -+ case hwmon_fan_alarm: -+ case hwmon_fan_input: -+ return 0444; -+ case hwmon_fan_div: -+ case hwmon_fan_target: -+ return 0644; -+ default: -+ break; -+ } -+ break; -+ default: -+ break; -+ } -+ -+ return 0; -+} -+ -+static int -+max6620_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, -+ int channel, long *val) -+{ -+ struct max6620_data *data; -+ struct i2c_client *client; -+ int ret; -+ u8 div; -+ u8 val1; -+ u8 val2; -+ -+ ret = max6620_update_device(dev); -+ if (ret < 0) -+ return ret; -+ data = dev_get_drvdata(dev); -+ client = data->client; -+ -+ switch (type) { -+ case hwmon_fan: -+ switch (attr) { -+ case hwmon_fan_alarm: -+ mutex_lock(&data->update_lock); -+ *val = !!(data->fault & BIT(channel)); -+ -+ /* Setting TACH count to re-enable fan fault detection */ -+ if (*val == 1) { -+ val1 = (data->target[channel] >> 3) & 0xff; -+ val2 = (data->target[channel] << 5) & 0xe0; -+ ret = i2c_smbus_write_byte_data(client, -+ target_reg[channel], val1); -+ if (ret < 0) { -+ mutex_unlock(&data->update_lock); -+ return ret; -+ } -+ ret = i2c_smbus_write_byte_data(client, -+ target_reg[channel] + 1, val2); -+ if (ret < 0) { -+ mutex_unlock(&data->update_lock); -+ return ret; -+ } -+ -+ data->fault &= ~BIT(channel); -+ } -+ mutex_unlock(&data->update_lock); -+ -+ break; -+ case hwmon_fan_div: -+ *val = max6620_fan_div_from_reg(data->fandyn[channel]); -+ break; -+ case hwmon_fan_input: -+ if (data->tach[channel] == 0) { -+ *val = 0; -+ } else { -+ div = max6620_fan_div_from_reg(data->fandyn[channel]); -+ *val = max6620_fan_tach_to_rpm(div, data->tach[channel]); -+ } -+ break; -+ case hwmon_fan_target: -+ if (data->target[channel] == 0) { -+ *val = 0; -+ } else { -+ div = max6620_fan_div_from_reg(data->fandyn[channel]); -+ *val = max6620_fan_tach_to_rpm(div, data->target[channel]); -+ } -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ break; -+ -+ default: -+ return -EOPNOTSUPP; -+ } -+ -+ return 0; -+} -+ -+static int -+max6620_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, -+ int channel, long val) -+{ -+ struct max6620_data *data; -+ struct i2c_client *client; -+ int ret; -+ u8 div; -+ u16 tach; -+ u8 val1; -+ u8 val2; -+ -+ ret = max6620_update_device(dev); -+ if (ret < 0) -+ return ret; -+ data = dev_get_drvdata(dev); -+ client = data->client; -+ mutex_lock(&data->update_lock); -+ -+ switch (type) { -+ case hwmon_fan: -+ switch (attr) { -+ case hwmon_fan_div: -+ switch (val) { -+ case 1: -+ div = 0; -+ break; -+ case 2: -+ div = 1; -+ break; -+ case 4: -+ div = 2; -+ break; -+ case 8: -+ div = 3; -+ break; -+ case 16: -+ div = 4; -+ break; -+ case 32: -+ div = 5; -+ break; -+ default: -+ ret = -EINVAL; -+ goto error; -+ } -+ data->fandyn[channel] &= 0x1F; -+ data->fandyn[channel] |= div << 5; -+ ret = i2c_smbus_write_byte_data(client, dyn_reg[channel], -+ data->fandyn[channel]); -+ break; -+ case hwmon_fan_target: -+ val = clamp_val(val, FAN_RPM_MIN, FAN_RPM_MAX); -+ div = max6620_fan_div_from_reg(data->fandyn[channel]); -+ tach = max6620_fan_rpm_to_tach(div, val); -+ val1 = (tach >> 3) & 0xff; -+ val2 = (tach << 5) & 0xe0; -+ ret = i2c_smbus_write_byte_data(client, target_reg[channel], val1); -+ if (ret < 0) -+ break; -+ ret = i2c_smbus_write_byte_data(client, target_reg[channel] + 1, val2); -+ if (ret < 0) -+ break; -+ -+ /* Setting TACH count re-enables fan fault detection */ -+ data->fault &= ~BIT(channel); -+ -+ break; -+ default: -+ ret = -EOPNOTSUPP; -+ break; -+ } -+ break; -+ -+ default: -+ ret = -EOPNOTSUPP; -+ break; -+ } -+ -+error: -+ mutex_unlock(&data->update_lock); -+ return ret; -+} -+ -+static const struct hwmon_channel_info *max6620_info[] = { -+ HWMON_CHANNEL_INFO(fan, -+ HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_TARGET | HWMON_F_ALARM, -+ HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_TARGET | HWMON_F_ALARM, -+ HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_TARGET | HWMON_F_ALARM, -+ HWMON_F_INPUT | HWMON_F_DIV | HWMON_F_TARGET | HWMON_F_ALARM), -+ NULL -+}; -+ -+static const struct hwmon_ops max6620_hwmon_ops = { -+ .read = max6620_read, -+ .write = max6620_write, -+ .is_visible = max6620_is_visible, -+}; -+ -+static const struct hwmon_chip_info max6620_chip_info = { -+ .ops = &max6620_hwmon_ops, -+ .info = max6620_info, -+}; -+ -+static int max6620_init_client(struct max6620_data *data) -+{ -+ struct i2c_client *client = data->client; -+ int config; -+ int err; -+ int i; -+ int reg; -+ -+ config = i2c_smbus_read_byte_data(client, MAX6620_REG_CONFIG); -+ if (config < 0) { -+ dev_err(&client->dev, "Error reading config, aborting.\n"); -+ return config; -+ } -+ -+ /* -+ * Set bit 4, disable other fans from going full speed on a fail -+ * failure. -+ */ -+ err = i2c_smbus_write_byte_data(client, MAX6620_REG_CONFIG, config | 0x10); -+ if (err < 0) { -+ dev_err(&client->dev, "Config write error, aborting.\n"); -+ return err; -+ } -+ -+ for (i = 0; i < 4; i++) { -+ reg = i2c_smbus_read_byte_data(client, config_reg[i]); -+ if (reg < 0) -+ return reg; -+ data->fancfg[i] = reg; -+ -+ /* Enable RPM mode */ -+ data->fancfg[i] |= 0xa8; -+ err = i2c_smbus_write_byte_data(client, config_reg[i], data->fancfg[i]); -+ if (err < 0) -+ return err; -+ -+ /* 2 counts (001) and Rate change 100 (0.125 secs) */ -+ data->fandyn[i] = 0x30; -+ err = i2c_smbus_write_byte_data(client, dyn_reg[i], data->fandyn[i]); -+ if (err < 0) -+ return err; -+ } -+ return 0; -+} -+ -+static int max6620_probe(struct i2c_client *client) -+{ -+ struct device *dev = &client->dev; -+ struct max6620_data *data; -+ struct device *hwmon_dev; -+ int err; -+ -+ data = devm_kzalloc(dev, sizeof(struct max6620_data), GFP_KERNEL); -+ if (!data) -+ return -ENOMEM; -+ -+ data->client = client; -+ mutex_init(&data->update_lock); -+ -+ err = max6620_init_client(data); -+ if (err) -+ return err; -+ -+ hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, -+ data, -+ &max6620_chip_info, -+ NULL); -+ -+ return PTR_ERR_OR_ZERO(hwmon_dev); -+} -+ -+static const struct i2c_device_id max6620_id[] = { -+ { "max6620", 0 }, -+ { } -+}; -+MODULE_DEVICE_TABLE(i2c, max6620_id); -+ -+static struct i2c_driver max6620_driver = { -+ .class = I2C_CLASS_HWMON, -+ .driver = { -+ .name = "max6620", -+ }, -+ .probe_new = max6620_probe, -+ .id_table = max6620_id, -+}; -+ -+module_i2c_driver(max6620_driver); -+ -+MODULE_AUTHOR("Lucas Grunenberg"); -+MODULE_DESCRIPTION("MAX6620 sensor driver"); -+MODULE_LICENSE("GPL"); --- -cgit 1.2.3-1.el7 - diff --git a/patch/kconfig-force-inclusions b/patch/kconfig-force-inclusions index 400796d6f..e14876637 100644 --- a/patch/kconfig-force-inclusions +++ b/patch/kconfig-force-inclusions @@ -1,6 +1,3 @@ [arm64] CONFIG_COMPAT_VDSO=y CONFIG_THUMB2_COMPAT_VDSO=y - -[marvell-prestera-armhf] -CONFIG_ARCH_NR_GPIO=0 diff --git a/patch/kconfig-inclusions b/patch/kconfig-inclusions index d8ca57cc0..a95b85950 100644 --- a/patch/kconfig-inclusions +++ b/patch/kconfig-inclusions @@ -91,14 +91,14 @@ CONFIG_MLXREG_HOTPLUG=m CONFIG_MLXREG_IO=m CONFIG_MLX_WDT=m CONFIG_MLXREG_LC=m -CONFIG_MLXREG_DPU=m +#CONFIG_MLXREG_DPU=m CONFIG_SENSORS_MLXREG_FAN=m CONFIG_GPIO_GENERIC=m CONFIG_MAX1363=m CONFIG_SENSORS_TPS53679=m CONFIG_SENSORS_XDPE122=m CONFIG_SENSORS_MP2975=m -CONFIG_SENSORS_MP2855=m +#CONFIG_SENSORS_MP2855=m CONFIG_SENSORS_MP2888=m CONFIG_SENSORS_MP2891=m CONFIG_CPU_THERMAL=y @@ -123,7 +123,7 @@ CONFIG_THERMAL_OF=y CONFIG_MCTP_FLOWS=y CONFIG_MCTP_TRANSPORT_I2C=m CONFIG_I2C_SLAVE_EEPROM=m -CONFIG_I2C_ASF=m +#CONFIG_I2C_ASF=m CONFIG_SPI_AMD=m CONFIG_PINCTRL_AMD=y CONFIG_EDAC_AMD64=m @@ -137,7 +137,6 @@ CONFIG_OF_MDIO=m CONFIG_MDIO_BUS_MUX_GPIO=m CONFIG_MDIO_BUS_MUX=m CONFIG_REGMAP_MMIO=y -CONFIG_ARCH_NR_GPIO=10240 CONFIG_TI_TLC4541=m CONFIG_SENSORS_LTC2978=m CONFIG_SENSORS_LTC2945=m diff --git a/patch/kernel-add-kexec-reboot-string.patch b/patch/kernel-add-kexec-reboot-string.patch deleted file mode 100644 index 80dd5dfe6..000000000 --- a/patch/kernel-add-kexec-reboot-string.patch +++ /dev/null @@ -1,22 +0,0 @@ -From cc1ab16f0e641a8b3cd90c802c2e48a4c89c238b Mon Sep 17 00:00:00 2001 - -From: Joe LeVeque - -Subject: [PATCH] Add kexec reboot string ---- - kernel/kexec_core.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/kernel/kexec_core.c b/kernel/kexec_core.c -index c589c7a95..0595252d7 100644 ---- a/kernel/kexec_core.c -+++ b/kernel/kexec_core.c -@@ -1166,7 +1166,7 @@ int kernel_kexec(void) - #endif - { - kexec_in_progress = true; -- kernel_restart_prepare(NULL); -+ kernel_restart_prepare("kexec reboot"); - migrate_to_reboot_cpu(); - - /* diff --git a/patch/kernel-compat-always-include-linux-compat.h-from-net-compat.patch b/patch/kernel-compat-always-include-linux-compat.h-from-net-compat.patch deleted file mode 100644 index 9d82ee267..000000000 --- a/patch/kernel-compat-always-include-linux-compat.h-from-net-compat.patch +++ /dev/null @@ -1,63 +0,0 @@ -From fc0d3b24bdb7a523e973e49648c45d240320ee95 Mon Sep 17 00:00:00 2001 -From: Jakub Kicinski -Date: Sat, 21 Nov 2020 13:48:44 -0800 -Subject: [PATCH] compat: always include linux/compat.h from net/compat.h -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -We're about to do reshuffling in networking headers and -eliminate some implicit includes. This results in: - -In file included from ../net/ipv4/netfilter/arp_tables.c:26: -include/net/compat.h:60:40: error: unknown type name ‘compat_uptr_t’; did you mean ‘compat_ptr_ioctl’? - struct sockaddr __user **save_addr, compat_uptr_t *ptr, - ^~~~~~~~~~~~~ - compat_ptr_ioctl -include/net/compat.h:61:4: error: unknown type name ‘compat_size_t’; did you mean ‘compat_sigset_t’? - compat_size_t *len); - ^~~~~~~~~~~~~ - compat_sigset_t - -Currently net/compat.h depends on linux/compat.h being included -first. After the upcoming changes this would break the 32bit build. - -Reviewed-by: Arnd Bergmann -Reviewed-by: Christoph Hellwig -Link: https://lore.kernel.org/r/20201121214844.1488283-1-kuba@kernel.org -Signed-off-by: Jakub Kicinski ---- - include/net/compat.h | 10 ---------- - 1 file changed, 10 deletions(-) - -diff --git a/include/net/compat.h b/include/net/compat.h -index 745db0d605b6..84805bdc4435 100644 ---- a/include/net/compat.h -+++ b/include/net/compat.h -@@ -5,8 +5,6 @@ - - struct sock; - --#if defined(CONFIG_COMPAT) -- - #include - - struct compat_msghdr { -@@ -48,14 +46,6 @@ struct compat_rtentry { - unsigned short rt_irtt; /* Initial RTT */ - }; - --#else /* defined(CONFIG_COMPAT) */ --/* -- * To avoid compiler warnings: -- */ --#define compat_msghdr msghdr --#define compat_mmsghdr mmsghdr --#endif /* defined(CONFIG_COMPAT) */ -- - int __get_compat_msghdr(struct msghdr *kmsg, struct compat_msghdr __user *umsg, - struct sockaddr __user **save_addr, compat_uptr_t *ptr, - compat_size_t *len); --- -2.25.1 - diff --git a/patch/net-sch_generic-fix-the-missing-new-qdisc-assignment.patch b/patch/net-sch_generic-fix-the-missing-new-qdisc-assignment.patch deleted file mode 100644 index 91af5dfba..000000000 --- a/patch/net-sch_generic-fix-the-missing-new-qdisc-assignment.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 81504d1952d712c8bb9c3966896efee8a37ea966 Mon Sep 17 00:00:00 2001 -From: Yunsheng Lin -Date: Tue, 3 Nov 2020 11:25:38 +0800 -Subject: net: sch_generic: fix the missing new qdisc assignment bug - -When commit 2fb541c862c9 ("net: sch_generic: aviod concurrent reset and -enqueue op for lockless qdisc") is backported to stable kernel, one -assignment is missing, which causes two problems reported by Joakim and -Vishwanath, see [1] and [2]. - -So add the assignment back to fix it. - -1. https://www.spinics.net/lists/netdev/msg693916.html -2. https://www.spinics.net/lists/netdev/msg695131.html - -Fixes: 749cc0b0c7f3 ("net: sch_generic: aviod concurrent reset and enqueue op for lockless qdisc") -Signed-off-by: Yunsheng Lin -Acked-by: Jakub Kicinski -Tested-by: Brian Norris -Signed-off-by: Greg Kroah-Hartman ---- - net/sched/sch_generic.c | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/net/sched/sch_generic.c b/net/sched/sch_generic.c -index bd96fd261dba3..4e15913e7519e 100644 ---- a/net/sched/sch_generic.c -+++ b/net/sched/sch_generic.c -@@ -1116,10 +1116,13 @@ static void dev_deactivate_queue(struct net_device *dev, - void *_qdisc_default) - { - struct Qdisc *qdisc = rtnl_dereference(dev_queue->qdisc); -+ struct Qdisc *qdisc_default = _qdisc_default; - - if (qdisc) { - if (!(qdisc->flags & TCQ_F_BUILTIN)) - set_bit(__QDISC_STATE_DEACTIVATED, &qdisc->state); -+ -+ rcu_assign_pointer(dev_queue->qdisc, qdisc_default); - } - } - --- -cgit 1.2.3-1.el7 - diff --git a/patch/preconfig/changelog.patch b/patch/preconfig/changelog.patch deleted file mode 100644 index 9096b5dec..000000000 --- a/patch/preconfig/changelog.patch +++ /dev/null @@ -1,34 +0,0 @@ -From a96e033ed01d4a68a0825c187bebe45a527fb868 Mon Sep 17 00:00:00 2001 - -From: Qi Luo - -Subject: [PATCH] Update changelog - -Signed-off-by: Qi Luo ---- - debian/changelog | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/debian/changelog b/debian/changelog -index 026b840..88c8a43 100644 ---- a/debian/changelog -+++ b/debian/changelog -@@ -1248,6 +1248,18 @@ - - -- Salvatore Bonaccorso Fri, 19 Jul 2019 13:41:00 +0200 - -+linux (4.9.168-1+deb9u3) sonic; urgency=high -+ -+ * add driver patches for MLNX SN2700 -+ -+ -- Guohan Lu Sun, 19 Dec 2015 01:50:04 +0100 -+ -+linux (4.9.168-1+deb9u3) sonic; urgency=high -+ -+ * add support for S6000 -+ -+ -- Shuotian Cheng Sun, 19 Dec 2015 01:50:04 +0100 -+ - linux (4.9.168-1+deb9u3) stretch-security; urgency=high - - [ Salvatore Bonaccorso ] diff --git a/patch/preconfig/disable-building-linux-source-deb-package.patch b/patch/preconfig/disable-building-linux-source-deb-package.patch deleted file mode 100644 index f8b886dcf..000000000 --- a/patch/preconfig/disable-building-linux-source-deb-package.patch +++ /dev/null @@ -1,26 +0,0 @@ -Don't build the linux source package. We don't use it. - -diff --git a/debian/config/defines b/debian/config/defines -index 55d7e51a7..d0bd92833 100644 ---- a/debian/config/defines -+++ b/debian/config/defines -@@ -171,3 +171,6 @@ gcc-12: gcc-12 , gcc-12-@gnu-type-package@ < - # initramfs-generators - initramfs-fallback: linux-initramfs-tool - initramfs-tools: initramfs-tools (>= 0.120+deb8u2) -+ -+[packages] -+source: false -diff --git a/debian/control.md5sum b/debian/control.md5sum -index 7d4eabf04..30b3c66a3 100644 ---- a/debian/control.md5sum -+++ b/debian/control.md5sum -@@ -38,7 +38,7 @@ afb508873a44a1f196c2a525fec4b415 debian/templates/image.prerm.in - a20d83421667bad21739041d4e743ed1 debian/templates/sourcebin.meta.maintscript.in - cbc5b0a81441c4c98b329ebe10827812 debian/templates/tools-unversioned.control.in - 568f629072d584e9a0eb1dc9d3a94749 debian/templates/tools-versioned.control.in --26c0dd754fd9fd1ffd676fe8a91d40c2 debian/config/defines -+f2176df3239edfc784a274054247ec8b debian/config/defines - 59a811890d2e7129bec940075850f11f debian/config/alpha/defines - 60569b1b4c618e2fe7b135f687d0f0d2 debian/config/amd64/defines - bc35d767074baf305423437d049be85d debian/config/arm64/defines diff --git a/patch/preconfig/packaging-update-abiname-to-11-2.patch b/patch/preconfig/packaging-update-abiname-to-11-2.patch deleted file mode 100644 index 0224c3e32..000000000 --- a/patch/preconfig/packaging-update-abiname-to-11-2.patch +++ /dev/null @@ -1,20 +0,0 @@ -Update debian abiname to 9-2 - -From: Guohan Lu - - ---- - debian/config/defines | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/debian/config/defines b/debian/config/defines -index cfc4409..fae58f7 100644 ---- a/debian/config/defines -+++ b/debian/config/defines -@@ -1,5 +1,5 @@ - [abi] --abiname: 11 -+abiname: 11-2 - ignore-changes: - __cpuhp_* - bpf_analyzer diff --git a/patch/preconfig/packaging-update-abiname.patch b/patch/preconfig/packaging-update-abiname.patch deleted file mode 100644 index b7c1dd02e..000000000 --- a/patch/preconfig/packaging-update-abiname.patch +++ /dev/null @@ -1,34 +0,0 @@ -Update debian abiname to 9-2 - -From: Olivier Singla - - ---- - debian/config/defines | 2 +- - debian/control.md5sum | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/debian/config/defines b/debian/config/defines -index 983625720..55d7e51a7 100644 ---- a/debian/config/defines -+++ b/debian/config/defines -@@ -1,5 +1,5 @@ - [abi] --abiname: 29 -+abiname: 29-2 - ignore-changes: - __cpuhp_* - __udp_gso_segment -diff --git a/debian/control.md5sum b/debian/control.md5sum -index b3ce4f58d..7d4eabf04 100644 ---- a/debian/control.md5sum -+++ b/debian/control.md5sum -@@ -38,7 +38,7 @@ afb508873a44a1f196c2a525fec4b415 debian/templates/image.prerm.in - a20d83421667bad21739041d4e743ed1 debian/templates/sourcebin.meta.maintscript.in - cbc5b0a81441c4c98b329ebe10827812 debian/templates/tools-unversioned.control.in - 568f629072d584e9a0eb1dc9d3a94749 debian/templates/tools-versioned.control.in --f3ba608063c55ec489dcdf9397ec8082 debian/config/defines -+26c0dd754fd9fd1ffd676fe8a91d40c2 debian/config/defines - 59a811890d2e7129bec940075850f11f debian/config/alpha/defines - 60569b1b4c618e2fe7b135f687d0f0d2 debian/config/amd64/defines - bc35d767074baf305423437d049be85d debian/config/arm64/defines diff --git a/patch/preconfig/series b/patch/preconfig/series deleted file mode 100644 index db0990286..000000000 --- a/patch/preconfig/series +++ /dev/null @@ -1,2 +0,0 @@ -packaging-update-abiname.patch -disable-building-linux-source-deb-package.patch diff --git a/patch/series b/patch/series deleted file mode 100755 index 6ae936323..000000000 --- a/patch/series +++ /dev/null @@ -1,249 +0,0 @@ -# This series applies on GIT commit 18c5597832fcf6988111b05a9a1607ae148723c -# Note: Markers should start with "###->". -# Header should end with .*-start eg: any_description-start -# Footer must end with .*-end eg: any_description-end -# Markers should not be nested - -driver-arista-net-tg3-dma-mask-4g-sb800.patch -driver-arista-net-tg3-disallow-broadcom-default-mac.patch -driver-arista-net-tg3-access-regs-indirectly.patch -driver-arista-pci-reassign-pref-mem.patch -driver-arista-mmcblk-not-working-on-AMD-platforms.patch -driver-arista-restrict-eMMC-drive-to-50Mhz-from-userland.patch -driver-arista-i2c-designware-shutdown.patch -driver-support-sff-8436-eeprom.patch -driver-support-sff-8436-eeprom-update.patch -driver-sff-8436-use-nvmem-framework.patch -driver-sff-8436-use-nvmem_device_read.patch -driver-support-sff-8436-read-write-fix.patch -driver-i2c-bus-intel-ismt-add-delay-param.patch -#kernel-add-kexec-reboot-string.patch # Upstreamed -#hwmon-Add-Maxim-MAX6620-hardware-monitoring-driver.patch # Upstreamed -#driver-hwmon-max6658-fix-write-convrate.patch # TODO: update for current version -#driver-hwmon-pmbus-dni_dps460.patch # TODO: build failure -#driver-hwmon-pmbus-dni_dps460-update-pmbus-core.patch # TODO: disabling for dependency -#driver-hwmon-pmbus-dni_dps460-add-status-attributes.patch # TODO: disabling for depedency -#driver-hwmon-pmbus-dps1900.patch # TODO: build failure -#driver-hwmon-pmbus-dps200.patch # TODO: disabling for dependency -driver-support-optoe.patch -driver-support-optoe-EOF_fix.patch -driver-support-optoe-chunk-offset-fix.patch -driver-support-optoe-QSFP_DD.patch -driver-support-optoe-write-max.patch -driver-support-optoe-write-max_fix.patch -driver-support-optoe-twoaddr-a2h-access.patch -driver-support-optoe-oneaddr-pageable.patch -driver-support-optoe-update-to-linux-6.1.patch -driver-support-optoe-dynamic-write-timeout.patch -driver-net-tg3-add-param-short-preamble-and-reset.patch -driver-net-tg3-change-dma-mask-for-57766.patch -0004-dt-bindings-hwmon-Add-missing-documentation-for-lm75.patch -0005-dt-bindings-hwmon-Add-tmp75b-to-lm75.txt.patch -0006-device-tree-bindinds-add-NXP-PCT2075-as-compatible-d.patch -Support-for-fullcone-nat.patch -#driver-ixgbe-external-phy.patch # Upstreamed -#kernel-compat-always-include-linux-compat.h-from-net-compat.patch # Upstreamed -#net-sch_generic-fix-the-missing-new-qdisc-assignment.patch # Functionality is present - -# Backport from 5.15 -#0001-x86-platform-Increase-maximum-GPIO-number-for-X86_64.patch - -# Backport from 5.16 -#0001-net-arp-introduce-arp_evict_nocarrier-sysctl-paramet.patch - -# Backport from 5.19 -#0001-net-ipv6-Introduce-accept_unsolicited_na-knob-to-imp.patch -#0002-net-ipv6-Expand-and-rename-accept_unsolicited_na-to-.patch - -# Backport from 5.12 -#0001-net-allow-user-to-set-metric-on-default-route-learne.patch - -# -# This series applies on GIT commit 1451b36b2b0d62178e42f648d8a18131af18f7d8 -# Tkernel-sched-core-fix-cgroup-fork-race.patch -# Tconfig-mlnx-sn2700.patch -# Tdriver-at24-fix-odd-length-two-byte-access.patch -# Tdriver-hwmon-lm75b-update.patch -# Tdriver-hwmon-pmbus-add-dps460-support.patch -# Tdriver-hwmon-pmbus-ucd9200-mlnx.patch -# Trtnetlink-catch-EOPNOTSUPP-errors.patch -# Tbridge-per-port-multicast-broadcast-flood-flags.patch -# - -0001-efi-memattr-Ignore-table-if-the-size-is-clearly-bogus.patch -# Backport from v6.14 to v6.1.132 and v6.12.20 -0001-prevent-bridge-link-show-failure-for-non-eswitch-allowed-devices.patch - -# Mellanox patches for 5.10 -###-> mellanox_sdk-start -0001-psample-define-the-macro-PSAMPLE_MD_EXTENDED_ATTR.patch -0002-drop_monitor-Extend-WJH-buffer-linux-channel.patch -###-> mellanox_sdk-end - -###-> mellanox_hw_mgmt-start -0001-platform-mellanox-Introduce-support-for-rack-manager.patch -0002-platform-mellanox-Change-reset_pwr_converter_fail-at.patch -0003-platform-mellanox-Cosmetic-changes-rename-to-more-co.patch -0004-platform-mellanox-Introduce-support-for-next-generat.patch -0005-platform-mellanox-Introduce-support-of-new-Nvidia-L1.patch -0006-platform-mellanox-Split-initialization-procedure.patch -0007-platform-mellanox-Split-logic-in-init-and-exit-flow.patch -0008-platform-mellanox-Extend-all-systems-with-I2C-notifi.patch -0009-platform-mellanox-mlx-platform-Add-mux-selection-reg.patch -0010-platform-mellanox-mlx-platform-Move-bus-shift-assign.patch -0011-platform-mellanox-mlx-platform-Initialize-shift-vari.patch -0012-platform-mellanox-Fix-order-in-exit-flow.patch -0013-platform-mellanox-mlx-platform-Fix-signals-polarity-.patch -0014-platform-mellanox-mlx-platform-Modify-graceful-shutd.patch -0015-platform-mellanox-Change-register-offset-addresses.patch -0016-platform-mellanox-Add-new-attributes.patch -0017-platform-mellanox-Add-field-upgrade-capability-regis.patch -0018-platform-mellanox-Modify-reset-causes-description.patch -0019-platform-mellanox-mlx-platform-Modify-health-and-pow.patch -0020-platform-mellanox-mlx-platform-Add-reset-cause-attri.patch -0021-platform-mellanox-mlx-platform-add-support-for-addit.patch -0022-platform-mellanox-mlx-platform-Modify-power-off-call.patch -0023-platform-mellanox-Cosmetic-changes.patch -0024-platform-mellanox-mlx-platform-Add-reset-callback.patch -0025-platform-mellanox-mlx-platform-Prepare-driver-to-all.patch -0026-platform-mellanox-mlx-platform-Introduce-ACPI-init-f.patch -0027-platform-mellanox-mlx-platform-Get-interrupt-line-th.patch -0028-platform-mellanox-Add-initial-support-for-PCIe-based.patch -0029-platform-mellanox-mlxreg-hotplug-Extend-condition-fo.patch -0030-platform-mellanox-nvsw-sn2201-change-fans-i2c-busses.patch -0032-platform_data-mlxreg-Add-field-with-mapped-resource-.patch -0033-i2c-mlxcpld-Allow-driver-to-run-on-ARM64-architectur.patch -0034-i2c-mlxcpld-Add-support-for-extended-transaction-len.patch -0035-i2c-mlxcpld-Support-PCIe-mapped-register-space.patch -0039-mlxsw-reg-Limit-MTBR-register-payload-to-a-single-da.patch -0040-mlxsw-core-Extend-allowed-list-of-external-cooling-d.patch -0041-mlxsw-i2c-Utilize-standard-macros-for-dividing-buffe.patch -0042-hwmon-mlxreg-fan-Add-support-for-new-flavour-of-capa.patch -0043-hwmon-mlxreg-fan-Extend-number-of-supporetd-fans.patch -0044-leds-mlxreg-Add-support-for-new-flavour-of-capabilit.patch -0045-leds-mlxreg-Remove-code-for-amber-LED-colour.patch -0046-Extend-driver-to-support-Infineon-Digital-Multi-phas.patch -0047-dt-bindings-trivial-devices-Add-infineon-xdpe1a2g7.patch -0048-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2891-c.patch -0049-dt-bindings-trivial-devices-Add-mps-mp2891.patch -0050-leds-mlxreg-Skip-setting-LED-color-during-initializa.patch -0051-platform-mellanox-mlxreg-hotplug-Allow-more-flexible.patch -0052-i2c-mux-Add-register-map-based-mux-driver.patch -0053-platform-mellanox-Add-support-for-dynamic-I2C-channe.patch -0054-platform-mellanox-Introduce-support-for-switches-equ.patch -0055-mellanox-Relocate-mlx-platform-driver.patch -0056-Documentation-ABI-Add-new-attribute-for-mlxreg-io-sy.patch -0057-Documentation-ABI-Add-new-attribute-for-mlxreg-io-sy.patch -0085-hwmon-mlxreg-fan-Separate-methods-of-fan-setting-com.patch -0087-platform-mellanox-indicate-deferred-I2C-bus-creation.patch -0087-platform_data-mlxreg-Add-capability-bit-and-mask-fie.patch -0088-platform-mellanox-mlxreg-hotplug-Add-support-for-new.patch -0089-platform-mellanox-mlx-platform-Change-register-name.patch -0090-platform-mellanox-mlx-platform-Add-support-for-new-X.patch -0091-platform-mellanox-mlxreg-dpu-Add-initial-support-for.patch -0092-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch -0093-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2855-c.patch -0094-i2c-asf-Introduce-MCTP-support-over-ASF-controller.patch -0095-platform-mellanox-nvsw-sn2201-Add-support-for-new-sy.patch -0097-platform-mellanox-mlx-platform-Add-support-for-new-N.patch -0098-platform-mellanox-Downstream-Add-support-for-new-Nvi.patch -0099-platform-mellanox-Downstream-Add-support-DGX-flavor-.patch -0100-platform-mellanox-mlxreg-io-Extend-number-of-hwmon-a.patch -0101-platform_data-mlxreg-Add-fields-for-interrupt-storm-.patch -0102-platform-mellanox-mlxreg-hotplug-Add-support-for-han.patch -0103-platform-mellanox-mlx-dpu-improve-interrupt-handling.patch -8000-mlxsw-Use-weak-reverse-dependencies-for-firmware-fla.patch -8003-mlxsw-i2c-SONIC-ISSU-Prevent-transaction-execution-f.patch -8004-mlxsw-minimal-Downstream-Ignore-error-reading-SPAD-r.patch -8005-leds-leds-mlxreg-Downstream-Send-udev-event-from-led.patch -8006-i2c-mlxcpld-Downstream-WA-to-avoid-error-for-SMBUS-r.patch -8007-hwmon-mlxreg-fan-Downstream-Allow-fan-speed-setting-.patch -8008-hwmon-emc2305-Downstream-Allow-fan-speed-setting-gra.patch -8009-hwmon-mlxsw-Downstream-Allow-fan-speed-setting-granu.patch -8010-mlxsw-i2c-Downstream-Add-retry-mechanism-for-failed-.patch -8011-mlxsw-minimal-Downstream-Disable-ethtool-interface.patch -8012-hwmon-pmbus-Downstream-Workaround-for-psu-attributes.patch -###-> mellanox_hw_mgmt-end - -# Cisco patches for 5.10 kernel -cisco-mtd-part.patch -cisco-mdio-mux-support-acpi.patch -cisco-x86-gpio-config.patch -cisco-acpi-spi-nor.patch -cisco-Enable-static-memory-reservation-for-OIRable-PCIe-de.patch -cisco-npu-disable-other-bars.patch -#cisco-hwmon-pmbus_core-pec-support-check.patch # Upstreamed - -# Nokia patches for 5.10 kernel -#0001-hwmon-emc2305-Fix-unable-to-probe-emc2301-2-3.patch # Upstreamed - -# -# Marvell platform patches for 6.1 kernel -0001-armhf_secondary_boot_online.patch -0002-arm64-dts-Update-cache-properties-for-marvell.patch -0003-arm64-dts-marvell-Add-NAND-flash-controller-to-AC5.patch -0004-arm64-dts-ac5-add-mmc-node-and-clock.patch -0005-dts-ac5-marvell-Add-switching-watchdog-node.patch -0006-mmc-xenon-Add-ac5-support-via-bounce-buffer.patch -0007-usb-ehci-Add-support-for-ac5.patch -0008-mv6xxx-Fix-i2c-lock-due-to-arb-loss.patch -0009-dt-bindings-marvell-Add-ARMADA-7K-properties.patch -0010-dts-marvell-Add-support-for-7020-comexpress.patch -0011-arm64-dts-marvell-Add-Nokia-7215-IXS-A1-board.patch -0015-arm64-dts-marvell-Add-Supermicro-SSE-G3748-board.patch -0016-arm64-dts-marvell-Add-Wistron-ES-1227-54TS-board.patch -0017-Extend-driver-to-support-XMC-XM25QH256C-device.patch -0018-i2c-mv64xxx-kdump-sonic.patch -0019-mrvl-gicp-clr-irqs-on-probe.patch - -# amd-pensando elba support -0000-Add-support-for-the-TI-TPS53659.patch -0001-Adding-support-LTC3888.patch -0002-i2c-designware-Support-stuck-SDA-line-recovery.patch -0003-i2c-Add-Lattice-RD1173-I2C-controller-driver.patch -0004-arm64-traps-Call-platform-handler-for-do_serror.patch -0005-add-quirks-for-the-Pensando-controller.patch -0006-Pensando-Elba-support-in-the-Cadence-EMMC-host-contr.patch -0007-spi-dw-Support-Pensando-Elba-custom-chip-select.patch -0008-Initial-support-for-the-Pensando-Elba-SoC.patch -0009-drivers-reset-Add-emmc-hardware-reset.patch -0010-dts-pensnado-Elba-flash-partitions.patch -0011-drivers-edac-Add-Elba-EDAC-support.patch -0012-drivers-soc-pensando-dev-capmem-driver.patch -0013-Interrupt-domain-controllers-for-Elba-ASIC.patch -0014-drivers-uio-UIO-drivers-for-Elba.patch -0015-drivers-pensando-soc-Boot-State-Machine-integrtion.patch -0016-drivers-soc-pensando-crash-dump-driver.patch -0017-drivers-soc-pensando-Add-the-Reset-Cause-driver.patch -0018-soc-pensando-pcie-driver.patch -0019-drivers-soc-pensando-kpcimgr-driver.patch -0020-dts-pensando-add-mnet-and-mcrypt-devices.patch -0021-drivers-soc-pensando-sbus-driver.patch -0022-drivers-soc-pensando-boot_count-to-sysfs-for-kdump.patch -0023-arch-arm64-boot-dts-psci-support.patch -0024-drivers-soc-pensando-penfw-driver.patch -0025-dts-changes-for-mtfuji-and-lipari.patch -0026-Add-support-for-new-qspi-macronix-flash-mx66u1g45g.patch -0027-pensando-add-rtc-cpld.patch -0028-Create-miniaturised-diafgw-partition-for-128MB-flash.patch -0029-pcie-if-hotplug-enabled-do-immediate-reset-on-panic.patch - -# Security patch -0001-Change-the-system.map-file-permission-only-readable-.patch - -# Micas patches -0001-fix-os-crash-caused-by-optoe-when-class-switch.patch -0001-tty-8250-HSUART-DMA-be-deactivated-for-DNV-CPU.patch - -# Fix to avoid kernel panic on Kernel 6.1.94 -# https://github.com/sonic-net/sonic-buildimage/issues/20901 -PCI-ASPM-Fix-link-state-exit-during-switch-upstream.patch - -# -# -############################################################ -# -# Internal patches will be added below (placeholder) -# Do not add any public patch below this marker -# -############################################################ diff --git a/patches-debian/disable-secureboot-config-checks.patch b/patches-debian/disable-secureboot-config-checks.patch new file mode 100644 index 000000000..213cbfd65 --- /dev/null +++ b/patches-debian/disable-secureboot-config-checks.patch @@ -0,0 +1,15 @@ +Index: linux-6.12.41/debian/bin/buildcheck.py +=================================================================== +--- linux-6.12.41.orig/debian/bin/buildcheck.py ++++ linux-6.12.41/debian/bin/buildcheck.py +@@ -23,9 +23,7 @@ class CheckSecureBootConfig: + with (self.dir / '.config').open() as fh: + kconfig.read(fh) + +- for name, value in [('EFI_STUB', True), +- ('LOCK_DOWN_IN_EFI_SECURE_BOOT', True), +- ('SYSTEM_TRUSTED_KEYS', '""')]: ++ for name, value in [('EFI_STUB', True),]: + if name not in kconfig: + out.write(f'Secure Boot: CONFIG_{name} is not defined\n') + fail = 1 diff --git a/patch/0000-Add-support-for-the-TI-TPS53659.patch b/patches-sonic/0000-Add-support-for-the-TI-TPS53659.patch similarity index 100% rename from patch/0000-Add-support-for-the-TI-TPS53659.patch rename to patches-sonic/0000-Add-support-for-the-TI-TPS53659.patch diff --git a/patch/0001-Adding-support-LTC3888.patch b/patches-sonic/0001-Adding-support-LTC3888.patch similarity index 100% rename from patch/0001-Adding-support-LTC3888.patch rename to patches-sonic/0001-Adding-support-LTC3888.patch diff --git a/patch/0001-Change-the-system.map-file-permission-only-readable-.patch b/patches-sonic/0001-Change-the-system.map-file-permission-only-readable-.patch similarity index 74% rename from patch/0001-Change-the-system.map-file-permission-only-readable-.patch rename to patches-sonic/0001-Change-the-system.map-file-permission-only-readable-.patch index 7151c716e..aa439ae78 100644 --- a/patch/0001-Change-the-system.map-file-permission-only-readable-.patch +++ b/patches-sonic/0001-Change-the-system.map-file-permission-only-readable-.patch @@ -12,31 +12,31 @@ index 98ee4ac7a..5f1d8a665 100644 --- a/debian/rules.real +++ b/debian/rules.real @@ -191,7 +191,7 @@ endif - dh_bugfiles - dh_lintian + dh_icons + dh_link dh_compress - dh_fixperms + dh_fixperms -XSystem.map-* - dh_installdeb - dh_gencontrol -- $(GENCONTROL_ARGS) - dh_md5sums + dh_missing + dh_strip $(DH_STRIP_ARGS) -Xvmlinux -Xvmlinuz + dh_makeshlibs -Xvdso -Xvmlinux -Xvmlinuz @@ -383,6 +383,7 @@ endif sed '/CONFIG_\(MODULE_SIG_\(ALL\|KEY\)\|SYSTEM_TRUSTED_KEYS\|BUILD_SALT\)[ =]/d' $(DIR)/.config > $(DESTDIR)/boot/config-$(REAL_VERSION) echo "ffffffffffffffff B The real System.map is in the linux-image--dbg package" \ > $(DESTDIR)/boot/System.map-$(REAL_VERSION) + chmod 600 $(DESTDIR)/boot/System.map-$(REAL_VERSION) - rm -f $(DESTDIR)/lib/modules/$(REAL_VERSION)/build - rm -f $(DESTDIR)/lib/modules/$(REAL_VERSION)/source rm $(DESTDIR)/lib/firmware -rf + + dh_installdirs usr/share/bug/$(PACKAGE_NAME) @@ -435,7 +436,7 @@ binary_image-dbg: $(STAMPS_DIR)/build_$(ARCH)_$(FEATURESET)_$(FLAVOUR) - dh_prep + $(dh_binary_pre) dh_installdirs usr/lib/debug usr/lib/debug/boot usr/share/lintian/overrides/ install -m644 $(DIR)/vmlinux $(DEBUG_DIR)/boot/vmlinux-$(REAL_VERSION) - install -m644 $(DIR)/System.map $(DEBUG_DIR)/boot/System.map-$(REAL_VERSION) + install -m600 $(DIR)/System.map $(DEBUG_DIR)/boot/System.map-$(REAL_VERSION) - +$(MAKE_CLEAN) -C $(DIR) modules_install DEPMOD='$(CURDIR)/debian/bin/no-depmod' INSTALL_MOD_PATH=$(DEBUG_DIR) - find $(DEBUG_DIR)/lib/modules/$(REAL_VERSION)/ -mindepth 1 -maxdepth 1 \! -name kernel -exec rm {} \+ - rm $(DEBUG_DIR)/lib/firmware -rf + + # cmd_sign=: Don't sign modules + # suffix-y=: Don't compress modules -- 2.25.1 diff --git a/patch/0001-armhf_secondary_boot_online.patch b/patches-sonic/0001-armhf_secondary_boot_online.patch similarity index 100% rename from patch/0001-armhf_secondary_boot_online.patch rename to patches-sonic/0001-armhf_secondary_boot_online.patch diff --git a/patch/0001-efi-memattr-Ignore-table-if-the-size-is-clearly-bogus.patch b/patches-sonic/0001-efi-memattr-Ignore-table-if-the-size-is-clearly-bogus.patch similarity index 100% rename from patch/0001-efi-memattr-Ignore-table-if-the-size-is-clearly-bogus.patch rename to patches-sonic/0001-efi-memattr-Ignore-table-if-the-size-is-clearly-bogus.patch diff --git a/patch/0001-fix-os-crash-caused-by-optoe-when-class-switch.patch b/patches-sonic/0001-fix-os-crash-caused-by-optoe-when-class-switch.patch similarity index 100% rename from patch/0001-fix-os-crash-caused-by-optoe-when-class-switch.patch rename to patches-sonic/0001-fix-os-crash-caused-by-optoe-when-class-switch.patch diff --git a/patch/0001-hwmon-emc2305-Fix-unable-to-probe-emc2301-2-3.patch b/patches-sonic/0001-hwmon-emc2305-Fix-unable-to-probe-emc2301-2-3.patch similarity index 100% rename from patch/0001-hwmon-emc2305-Fix-unable-to-probe-emc2301-2-3.patch rename to patches-sonic/0001-hwmon-emc2305-Fix-unable-to-probe-emc2301-2-3.patch diff --git a/patches-sonic/0001-mlxbf-bootctl-Constify-struct-bin_attribute.patch b/patches-sonic/0001-mlxbf-bootctl-Constify-struct-bin_attribute.patch new file mode 100644 index 000000000..cd30de111 --- /dev/null +++ b/patches-sonic/0001-mlxbf-bootctl-Constify-struct-bin_attribute.patch @@ -0,0 +1,48 @@ +From cad481488093e440217f6a93e45fe4fa03a77000 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= +Date: Sun, 15 Dec 2024 14:25:40 +0100 +Subject: [PATCH 01/78] mlxbf-bootctl: Constify 'struct bin_attribute' +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The sysfs core now allows instances of 'struct bin_attribute' to be +moved into read-only memory. Make use of that to protect them against +accidental or malicious modifications. + +Signed-off-by: Thomas Weißschuh +Link: https://lore.kernel.org/r/20241215-sysfs-const-bin_attr-mellanox-v1-1-b6fe4f68e2ca@weissschuh.net +Reviewed-by: Ilpo Järvinen +Signed-off-by: Ilpo Järvinen +--- + drivers/platform/mellanox/mlxbf-bootctl.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/platform/mellanox/mlxbf-bootctl.c b/drivers/platform/mellanox/mlxbf-bootctl.c +index dd5f370..7e246dd 100644 +--- a/drivers/platform/mellanox/mlxbf-bootctl.c ++++ b/drivers/platform/mellanox/mlxbf-bootctl.c +@@ -939,7 +939,7 @@ MODULE_DEVICE_TABLE(acpi, mlxbf_bootctl_acpi_ids); + + static ssize_t mlxbf_bootctl_bootfifo_read(struct file *filp, + struct kobject *kobj, +- struct bin_attribute *bin_attr, ++ const struct bin_attribute *bin_attr, + char *buf, loff_t pos, + size_t count) + { +@@ -971,9 +971,9 @@ static ssize_t mlxbf_bootctl_bootfifo_read(struct file *filp, + return p - buf; + } + +-static struct bin_attribute mlxbf_bootctl_bootfifo_sysfs_attr = { ++static const struct bin_attribute mlxbf_bootctl_bootfifo_sysfs_attr = { + .attr = { .name = "bootfifo", .mode = 0400 }, +- .read = mlxbf_bootctl_bootfifo_read, ++ .read_new = mlxbf_bootctl_bootfifo_read, + }; + + static bool mlxbf_bootctl_guid_match(const guid_t *guid, +-- +2.8.4 + diff --git a/patch/0001-psample-define-the-macro-PSAMPLE_MD_EXTENDED_ATTR.patch b/patches-sonic/0001-psample-define-the-macro-PSAMPLE_MD_EXTENDED_ATTR.patch similarity index 100% rename from patch/0001-psample-define-the-macro-PSAMPLE_MD_EXTENDED_ATTR.patch rename to patches-sonic/0001-psample-define-the-macro-PSAMPLE_MD_EXTENDED_ATTR.patch diff --git a/patch/0001-tty-8250-HSUART-DMA-be-deactivated-for-DNV-CPU.patch b/patches-sonic/0001-tty-8250-HSUART-DMA-be-deactivated-for-DNV-CPU.patch similarity index 100% rename from patch/0001-tty-8250-HSUART-DMA-be-deactivated-for-DNV-CPU.patch rename to patches-sonic/0001-tty-8250-HSUART-DMA-be-deactivated-for-DNV-CPU.patch diff --git a/patch/0002-arm64-dts-Update-cache-properties-for-marvell.patch b/patches-sonic/0002-arm64-dts-Update-cache-properties-for-marvell.patch similarity index 100% rename from patch/0002-arm64-dts-Update-cache-properties-for-marvell.patch rename to patches-sonic/0002-arm64-dts-Update-cache-properties-for-marvell.patch diff --git a/patch/0002-drop_monitor-Extend-WJH-buffer-linux-channel.patch b/patches-sonic/0002-drop_monitor-Extend-WJH-buffer-linux-channel.patch similarity index 90% rename from patch/0002-drop_monitor-Extend-WJH-buffer-linux-channel.patch rename to patches-sonic/0002-drop_monitor-Extend-WJH-buffer-linux-channel.patch index 66ab39752..81d3c85f3 100644 --- a/patch/0002-drop_monitor-Extend-WJH-buffer-linux-channel.patch +++ b/patches-sonic/0002-drop_monitor-Extend-WJH-buffer-linux-channel.patch @@ -14,13 +14,13 @@ SDK WJH-Libs is using following information for shared buffer drops: The above metadata is missing when using linux channel (drop monitor). This patch is to add the extended information also for linux channel. --- - include/net/devlink.h | 18 +++++ - include/uapi/linux/net_dropmon.h | 5 ++ - net/core/drop_monitor.c | 111 +++++++++++++++++++++++++++++++ - 3 files changed, 134 insertions(+) + include/net/devlink.h | 18 ++++++++++++++++++ + include/uapi/linux/net_dropmon.h | 5 +++++ + net/core/drop_monitor.c | 112 +++++++++++++++++++++++++++ + 3 files changed, 135 insertions(+) diff --git a/include/net/devlink.h b/include/net/devlink.h -index ba6b8b0..214edcc 100644 +index db5eff6..6024ce6 100644 --- a/include/net/devlink.h +++ b/include/net/devlink.h @@ -21,6 +21,10 @@ @@ -34,7 +34,7 @@ index ba6b8b0..214edcc 100644 struct devlink; struct devlink_linecard; -@@ -711,6 +715,11 @@ struct devlink_health_reporter_ops { +@@ -753,6 +757,11 @@ struct devlink_health_reporter_ops { * @dev_tracker: refcount tracker for @input_dev. * @fa_cookie: Flow action user cookie. * @trap_type: Trap type. @@ -46,7 +46,7 @@ index ba6b8b0..214edcc 100644 */ struct devlink_trap_metadata { const char *trap_name; -@@ -721,6 +730,15 @@ struct devlink_trap_metadata { +@@ -763,6 +772,15 @@ struct devlink_trap_metadata { const struct flow_action_cookie *fa_cookie; enum devlink_trap_type trap_type; @@ -79,10 +79,10 @@ index 84f622a..d6f6399 100644 __NET_DM_ATTR_MAX, NET_DM_ATTR_MAX = __NET_DM_ATTR_MAX - 1 diff --git a/net/core/drop_monitor.c b/net/core/drop_monitor.c -index f084a4a..0405e10 100644 +index 2e0ae33..b5d8ea3 100644 --- a/net/core/drop_monitor.c +++ b/net/core/drop_monitor.c -@@ -606,6 +606,36 @@ nla_put_failure: +@@ -609,6 +609,36 @@ nla_put_failure: return -EMSGSIZE; } @@ -119,7 +119,7 @@ index f084a4a..0405e10 100644 static int net_dm_packet_report_fill(struct sk_buff *msg, struct sk_buff *skb, size_t payload_len) { -@@ -731,6 +761,16 @@ net_dm_flow_action_cookie_size(const struct devlink_trap_metadata *hw_metadata) +@@ -749,6 +779,16 @@ net_dm_flow_action_cookie_size(const struct devlink_trap_metadata *hw_metadata) nla_total_size(hw_metadata->fa_cookie->cookie_len) : 0; } @@ -136,7 +136,7 @@ index f084a4a..0405e10 100644 static size_t net_dm_hw_packet_report_size(size_t payload_len, const struct devlink_trap_metadata *hw_metadata) -@@ -756,6 +796,16 @@ net_dm_hw_packet_report_size(size_t payload_len, +@@ -774,6 +814,16 @@ net_dm_hw_packet_report_size(size_t payload_len, nla_total_size(sizeof(u32)) + /* NET_DM_ATTR_PROTO */ nla_total_size(sizeof(u16)) + @@ -153,7 +153,7 @@ index f084a4a..0405e10 100644 /* NET_DM_ATTR_PAYLOAD */ nla_total_size(payload_len); } -@@ -801,6 +851,43 @@ static int net_dm_hw_packet_report_fill(struct sk_buff *msg, +@@ -819,6 +869,43 @@ static int net_dm_hw_packet_report_fill(struct sk_buff *msg, hw_metadata->fa_cookie->cookie)) goto nla_put_failure; @@ -197,7 +197,7 @@ index f084a4a..0405e10 100644 if (nla_put_u64_64bit(msg, NET_DM_ATTR_TIMESTAMP, ktime_to_ns(skb->tstamp), NET_DM_ATTR_PAD)) goto nla_put_failure; -@@ -867,6 +954,27 @@ net_dm_hw_metadata_copy(const struct devlink_trap_metadata *metadata) +@@ -885,6 +972,27 @@ net_dm_hw_metadata_copy(const struct devlink_trap_metadata *metadata) netdev_hold(hw_metadata->input_dev, &hw_metadata->dev_tracker, GFP_ATOMIC); @@ -225,7 +225,7 @@ index f084a4a..0405e10 100644 return hw_metadata; free_trap_name: -@@ -882,6 +990,10 @@ static void +@@ -900,6 +1008,10 @@ static void net_dm_hw_metadata_free(struct devlink_trap_metadata *hw_metadata) { netdev_put(hw_metadata->input_dev, &hw_metadata->dev_tracker); diff --git a/patch/0002-i2c-designware-Support-stuck-SDA-line-recovery.patch b/patches-sonic/0002-i2c-designware-Support-stuck-SDA-line-recovery.patch similarity index 100% rename from patch/0002-i2c-designware-Support-stuck-SDA-line-recovery.patch rename to patches-sonic/0002-i2c-designware-Support-stuck-SDA-line-recovery.patch diff --git a/patches-sonic/0002-platform-mellanox-mlxbf-pmc-Add-support-for-monitori.patch b/patches-sonic/0002-platform-mellanox-mlxbf-pmc-Add-support-for-monitori.patch new file mode 100644 index 000000000..88354f80e --- /dev/null +++ b/patches-sonic/0002-platform-mellanox-mlxbf-pmc-Add-support-for-monitori.patch @@ -0,0 +1,126 @@ +From f9a8958b29d408941ad18087f3f2c19f06c820fb Mon Sep 17 00:00:00 2001 +From: Shravan Kumar Ramani +Date: Thu, 9 Jan 2025 09:39:21 -0500 +Subject: [PATCH 02/78] platform/mellanox: mlxbf-pmc: Add support for + monitoring cycle count +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add support for programming any counter to monitor the cycle count. +This will allow the user to repurpose and dedicate any of the counters +in the block to counting cycles. + +Signed-off-by: Shravan Kumar Ramani +Reviewed-by: David Thompson +Reviewed-by: Vadim Pasternak +Link: https://lore.kernel.org/r/bd7747897cf1ce77e2e39e271cac21684830f7e7.1736413033.git.shravankr@nvidia.com +Reviewed-by: Ilpo Järvinen +Signed-off-by: Ilpo Järvinen +--- + drivers/platform/mellanox/mlxbf-pmc.c | 61 +++++++++++++++++++++++++++++++++++ + 1 file changed, 61 insertions(+) + +diff --git a/drivers/platform/mellanox/mlxbf-pmc.c b/drivers/platform/mellanox/mlxbf-pmc.c +index fbb8128..197a98e 100644 +--- a/drivers/platform/mellanox/mlxbf-pmc.c ++++ b/drivers/platform/mellanox/mlxbf-pmc.c +@@ -88,6 +88,7 @@ + #define MLXBF_PMC_CRSPACE_PERFMON_CTL(n) (n * MLXBF_PMC_CRSPACE_PERFMON_REG0_SZ) + #define MLXBF_PMC_CRSPACE_PERFMON_EN BIT(30) + #define MLXBF_PMC_CRSPACE_PERFMON_CLR BIT(28) ++#define MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(n) (MLXBF_PMC_CRSPACE_PERFMON_CTL(n) + 0x4) + #define MLXBF_PMC_CRSPACE_PERFMON_VAL0(n) (MLXBF_PMC_CRSPACE_PERFMON_CTL(n) + 0xc) + + /** +@@ -114,6 +115,7 @@ struct mlxbf_pmc_attribute { + * @attr_event: Attributes for "event" sysfs files + * @attr_event_list: Attributes for "event_list" sysfs files + * @attr_enable: Attributes for "enable" sysfs files ++ * @attr_count_clock: Attributes for "count_clock" sysfs files + * @block_attr: All attributes needed for the block + * @block_attr_grp: Attribute group for the block + */ +@@ -126,6 +128,7 @@ struct mlxbf_pmc_block_info { + struct mlxbf_pmc_attribute *attr_event; + struct mlxbf_pmc_attribute attr_event_list; + struct mlxbf_pmc_attribute attr_enable; ++ struct mlxbf_pmc_attribute attr_count_clock; + struct attribute *block_attr[MLXBF_PMC_MAX_ATTRS]; + struct attribute_group block_attr_grp; + }; +@@ -1763,6 +1766,49 @@ static ssize_t mlxbf_pmc_enable_store(struct device *dev, + return count; + } + ++/* Show function for "count_clock" sysfs files - only for crspace */ ++static ssize_t mlxbf_pmc_count_clock_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ struct mlxbf_pmc_attribute *attr_count_clock = container_of( ++ attr, struct mlxbf_pmc_attribute, dev_attr); ++ unsigned int blk_num; ++ u32 reg; ++ ++ blk_num = attr_count_clock->nr; ++ ++ if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + ++ MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(pmc->block[blk_num].counters), ++ ®)) ++ return -EINVAL; ++ ++ return sysfs_emit(buf, "%u\n", reg); ++} ++ ++/* Store function for "count_clock" sysfs files - only for crspace */ ++static ssize_t mlxbf_pmc_count_clock_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct mlxbf_pmc_attribute *attr_count_clock = container_of( ++ attr, struct mlxbf_pmc_attribute, dev_attr); ++ unsigned int blk_num; ++ u32 reg; ++ int err; ++ ++ blk_num = attr_count_clock->nr; ++ ++ err = kstrtouint(buf, 0, ®); ++ if (err < 0) ++ return err; ++ ++ mlxbf_pmc_write(pmc->block[blk_num].mmio_base + ++ MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(pmc->block[blk_num].counters), ++ MLXBF_PMC_WRITE_REG_32, reg); ++ ++ return count; ++} ++ + /* Populate attributes for blocks with counters to monitor performance */ + static int mlxbf_pmc_init_perftype_counter(struct device *dev, unsigned int blk_num) + { +@@ -1801,6 +1847,21 @@ static int mlxbf_pmc_init_perftype_counter(struct device *dev, unsigned int blk_ + attr = NULL; + } + ++ if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_CRSPACE) { ++ /* Program crspace counters to count clock cycles using "count_clock" sysfs */ ++ attr = &pmc->block[blk_num].attr_count_clock; ++ attr->dev_attr.attr.mode = 0644; ++ attr->dev_attr.show = mlxbf_pmc_count_clock_show; ++ attr->dev_attr.store = mlxbf_pmc_count_clock_store; ++ attr->nr = blk_num; ++ attr->dev_attr.attr.name = devm_kasprintf(dev, GFP_KERNEL, ++ "count_clock"); ++ if (!attr->dev_attr.attr.name) ++ return -ENOMEM; ++ pmc->block[blk_num].block_attr[++i] = &attr->dev_attr.attr; ++ attr = NULL; ++ } ++ + pmc->block[blk_num].attr_counter = devm_kcalloc( + dev, pmc->block[blk_num].counters, + sizeof(struct mlxbf_pmc_attribute), GFP_KERNEL); +-- +2.8.4 + diff --git a/patch/0003-arm64-dts-marvell-Add-NAND-flash-controller-to-AC5.patch b/patches-sonic/0003-arm64-dts-marvell-Add-NAND-flash-controller-to-AC5.patch similarity index 100% rename from patch/0003-arm64-dts-marvell-Add-NAND-flash-controller-to-AC5.patch rename to patches-sonic/0003-arm64-dts-marvell-Add-NAND-flash-controller-to-AC5.patch diff --git a/patch/0003-i2c-Add-Lattice-RD1173-I2C-controller-driver.patch b/patches-sonic/0003-i2c-Add-Lattice-RD1173-I2C-controller-driver.patch similarity index 100% rename from patch/0003-i2c-Add-Lattice-RD1173-I2C-controller-driver.patch rename to patches-sonic/0003-i2c-Add-Lattice-RD1173-I2C-controller-driver.patch diff --git a/patches-sonic/0003-platform-mellanox-mlxbf-pmc-Add-support-for-clock_me.patch b/patches-sonic/0003-platform-mellanox-mlxbf-pmc-Add-support-for-clock_me.patch new file mode 100644 index 000000000..fa5b393c7 --- /dev/null +++ b/patches-sonic/0003-platform-mellanox-mlxbf-pmc-Add-support-for-clock_me.patch @@ -0,0 +1,108 @@ +From 8dfc0be5792d269fd8203e02e7c224a355bf792c Mon Sep 17 00:00:00 2001 +From: Shravan Kumar Ramani +Date: Thu, 9 Jan 2025 09:39:22 -0500 +Subject: [PATCH 03/78] platform/mellanox: mlxbf-pmc: Add support for + clock_measure performance block +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The HW clock_measure counter info is passed to the driver from ACPI. +Create a new sub-directory for clock_measure events and provide +read access to the user. Writes are blocked since the fields are RO. + +Signed-off-by: Shravan Kumar Ramani +Reviewed-by: David Thompson +Reviewed-by: Vadim Pasternak +Link: https://lore.kernel.org/r/6ea0699497479dfde0a52fcb28aef55aee1bbc0b.1736413033.git.shravankr@nvidia.com +Reviewed-by: Ilpo Järvinen +Signed-off-by: Ilpo Järvinen +--- + drivers/platform/mellanox/mlxbf-pmc.c | 46 ++++++++++++++++++++++++++++++++--- + 1 file changed, 42 insertions(+), 4 deletions(-) + +diff --git a/drivers/platform/mellanox/mlxbf-pmc.c b/drivers/platform/mellanox/mlxbf-pmc.c +index 197a98e..771a24c 100644 +--- a/drivers/platform/mellanox/mlxbf-pmc.c ++++ b/drivers/platform/mellanox/mlxbf-pmc.c +@@ -862,6 +862,37 @@ static const struct mlxbf_pmc_events mlxbf_pmc_llt_miss_events[] = { + {75, "HISTOGRAM_HISTOGRAM_BIN9"}, + }; + ++static const struct mlxbf_pmc_events mlxbf_pmc_clock_events[] = { ++ { 0x0, "FMON_CLK_LAST_COUNT_PLL_D1_INST0" }, ++ { 0x4, "REFERENCE_WINDOW_WIDTH_PLL_D1_INST0" }, ++ { 0x8, "FMON_CLK_LAST_COUNT_PLL_D1_INST1" }, ++ { 0xc, "REFERENCE_WINDOW_WIDTH_PLL_D1_INST1" }, ++ { 0x10, "FMON_CLK_LAST_COUNT_PLL_G1" }, ++ { 0x14, "REFERENCE_WINDOW_WIDTH_PLL_G1" }, ++ { 0x18, "FMON_CLK_LAST_COUNT_PLL_W1" }, ++ { 0x1c, "REFERENCE_WINDOW_WIDTH_PLL_W1" }, ++ { 0x20, "FMON_CLK_LAST_COUNT_PLL_T1" }, ++ { 0x24, "REFERENCE_WINDOW_WIDTH_PLL_T1" }, ++ { 0x28, "FMON_CLK_LAST_COUNT_PLL_A0" }, ++ { 0x2c, "REFERENCE_WINDOW_WIDTH_PLL_A0" }, ++ { 0x30, "FMON_CLK_LAST_COUNT_PLL_C0" }, ++ { 0x34, "REFERENCE_WINDOW_WIDTH_PLL_C0" }, ++ { 0x38, "FMON_CLK_LAST_COUNT_PLL_N1" }, ++ { 0x3c, "REFERENCE_WINDOW_WIDTH_PLL_N1" }, ++ { 0x40, "FMON_CLK_LAST_COUNT_PLL_I1" }, ++ { 0x44, "REFERENCE_WINDOW_WIDTH_PLL_I1" }, ++ { 0x48, "FMON_CLK_LAST_COUNT_PLL_R1" }, ++ { 0x4c, "REFERENCE_WINDOW_WIDTH_PLL_R1" }, ++ { 0x50, "FMON_CLK_LAST_COUNT_PLL_P1" }, ++ { 0x54, "REFERENCE_WINDOW_WIDTH_PLL_P1" }, ++ { 0x58, "FMON_CLK_LAST_COUNT_REF_100_INST0" }, ++ { 0x5c, "REFERENCE_WINDOW_WIDTH_REF_100_INST0" }, ++ { 0x60, "FMON_CLK_LAST_COUNT_REF_100_INST1" }, ++ { 0x64, "REFERENCE_WINDOW_WIDTH_REF_100_INST1" }, ++ { 0x68, "FMON_CLK_LAST_COUNT_REF_156" }, ++ { 0x6c, "REFERENCE_WINDOW_WIDTH_REF_156" }, ++}; ++ + static struct mlxbf_pmc_context *pmc; + + /* UUID used to probe ATF service. */ +@@ -1035,6 +1066,9 @@ static const struct mlxbf_pmc_events *mlxbf_pmc_event_list(const char *blk, size + } else if (strstr(blk, "llt")) { + events = mlxbf_pmc_llt_events; + size = ARRAY_SIZE(mlxbf_pmc_llt_events); ++ } else if (strstr(blk, "clock_measure")) { ++ events = mlxbf_pmc_clock_events; ++ size = ARRAY_SIZE(mlxbf_pmc_clock_events); + } else { + events = NULL; + size = 0; +@@ -1469,14 +1503,15 @@ static int mlxbf_pmc_read_event(unsigned int blk_num, u32 cnt_num, bool is_l3, u + /* Method to read a register */ + static int mlxbf_pmc_read_reg(unsigned int blk_num, u32 offset, u64 *result) + { +- u32 ecc_out; ++ u32 reg; + +- if (strstr(pmc->block_name[blk_num], "ecc")) { ++ if ((strstr(pmc->block_name[blk_num], "ecc")) || ++ (strstr(pmc->block_name[blk_num], "clock_measure"))) { + if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + offset, +- &ecc_out)) ++ ®)) + return -EFAULT; + +- *result = ecc_out; ++ *result = reg; + return 0; + } + +@@ -1490,6 +1525,9 @@ static int mlxbf_pmc_read_reg(unsigned int blk_num, u32 offset, u64 *result) + /* Method to write to a register */ + static int mlxbf_pmc_write_reg(unsigned int blk_num, u32 offset, u64 data) + { ++ if (strstr(pmc->block_name[blk_num], "clock_measure")) ++ return -EINVAL; ++ + if (strstr(pmc->block_name[blk_num], "ecc")) { + return mlxbf_pmc_write(pmc->block[blk_num].mmio_base + offset, + MLXBF_PMC_WRITE_REG_32, data); +-- +2.8.4 + diff --git a/patch/0004-arm64-dts-ac5-add-mmc-node-and-clock.patch b/patches-sonic/0004-arm64-dts-ac5-add-mmc-node-and-clock.patch similarity index 100% rename from patch/0004-arm64-dts-ac5-add-mmc-node-and-clock.patch rename to patches-sonic/0004-arm64-dts-ac5-add-mmc-node-and-clock.patch diff --git a/patch/0004-arm64-traps-Call-platform-handler-for-do_serror.patch b/patches-sonic/0004-arm64-traps-Call-platform-handler-for-do_serror.patch similarity index 100% rename from patch/0004-arm64-traps-Call-platform-handler-for-do_serror.patch rename to patches-sonic/0004-arm64-traps-Call-platform-handler-for-do_serror.patch diff --git a/patch/0004-dt-bindings-hwmon-Add-missing-documentation-for-lm75.patch b/patches-sonic/0004-dt-bindings-hwmon-Add-missing-documentation-for-lm75.patch similarity index 100% rename from patch/0004-dt-bindings-hwmon-Add-missing-documentation-for-lm75.patch rename to patches-sonic/0004-dt-bindings-hwmon-Add-missing-documentation-for-lm75.patch diff --git a/patches-sonic/0004-platform-mellanox-mlxbf-bootctl-use-sysfs_emit-inste.patch b/patches-sonic/0004-platform-mellanox-mlxbf-bootctl-use-sysfs_emit-inste.patch new file mode 100644 index 000000000..2b8bd68f0 --- /dev/null +++ b/patches-sonic/0004-platform-mellanox-mlxbf-bootctl-use-sysfs_emit-inste.patch @@ -0,0 +1,77 @@ +From 6e425aad9eb78283afa517ef648d7539596bc41b Mon Sep 17 00:00:00 2001 +From: Ai Chao +Date: Thu, 16 Jan 2025 16:08:35 +0800 +Subject: [PATCH 04/78] platform/mellanox: mlxbf-bootctl: use sysfs_emit() + instead of sprintf() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Follow the advice in Documentation/filesystems/sysfs.rst: +show() should only use sysfs_emit() or sysfs_emit_at() when formatting +the value to be returned to user space. + +Signed-off-by: Ai Chao +Acked-by: Vadim Pasternak +Link: https://lore.kernel.org/r/20250116080836.2890442-1-aichao@kylinos.cn +Reviewed-by: Ilpo Järvinen +Signed-off-by: Ilpo Järvinen +--- + drivers/platform/mellanox/mlxbf-bootctl.c | 14 +++++++------- + 1 file changed, 7 insertions(+), 7 deletions(-) + +diff --git a/drivers/platform/mellanox/mlxbf-bootctl.c b/drivers/platform/mellanox/mlxbf-bootctl.c +index 7e246dd..e8530ef 100644 +--- a/drivers/platform/mellanox/mlxbf-bootctl.c ++++ b/drivers/platform/mellanox/mlxbf-bootctl.c +@@ -177,7 +177,7 @@ static ssize_t post_reset_wdog_show(struct device *dev, + if (ret < 0) + return ret; + +- return sprintf(buf, "%d\n", ret); ++ return sysfs_emit(buf, "%d\n", ret); + } + + static ssize_t post_reset_wdog_store(struct device *dev, +@@ -206,7 +206,7 @@ static ssize_t mlxbf_bootctl_show(int smc_op, char *buf) + if (action < 0) + return action; + +- return sprintf(buf, "%s\n", mlxbf_bootctl_action_to_string(action)); ++ return sysfs_emit(buf, "%s\n", mlxbf_bootctl_action_to_string(action)); + } + + static int mlxbf_bootctl_store(int smc_op, const char *buf, size_t count) +@@ -274,14 +274,14 @@ static ssize_t lifecycle_state_show(struct device *dev, + * due to using the test bits. + */ + if (test_state) { +- return sprintf(buf, "%s(test)\n", ++ return sysfs_emit(buf, "%s(test)\n", + mlxbf_bootctl_lifecycle_states[lc_state]); + } else if (use_dev_key && + (lc_state == MLXBF_BOOTCTL_SB_LIFECYCLE_GA_SECURE)) { +- return sprintf(buf, "Secured (development)\n"); ++ return sysfs_emit(buf, "Secured (development)\n"); + } + +- return sprintf(buf, "%s\n", mlxbf_bootctl_lifecycle_states[lc_state]); ++ return sysfs_emit(buf, "%s\n", mlxbf_bootctl_lifecycle_states[lc_state]); + } + + static ssize_t secure_boot_fuse_state_show(struct device *dev, +@@ -332,9 +332,9 @@ static ssize_t secure_boot_fuse_state_show(struct device *dev, + else + status = valid ? "Invalid" : "Free"; + } +- buf_len += sprintf(buf + buf_len, "%d:%s ", key, status); ++ buf_len += sysfs_emit(buf + buf_len, "%d:%s ", key, status); + } +- buf_len += sprintf(buf + buf_len, "\n"); ++ buf_len += sysfs_emit(buf + buf_len, "\n"); + + return buf_len; + } +-- +2.8.4 + diff --git a/patch/0005-add-quirks-for-the-Pensando-controller.patch b/patches-sonic/0005-add-quirks-for-the-Pensando-controller.patch similarity index 100% rename from patch/0005-add-quirks-for-the-Pensando-controller.patch rename to patches-sonic/0005-add-quirks-for-the-Pensando-controller.patch diff --git a/patch/0005-dt-bindings-hwmon-Add-tmp75b-to-lm75.txt.patch b/patches-sonic/0005-dt-bindings-hwmon-Add-tmp75b-to-lm75.txt.patch similarity index 100% rename from patch/0005-dt-bindings-hwmon-Add-tmp75b-to-lm75.txt.patch rename to patches-sonic/0005-dt-bindings-hwmon-Add-tmp75b-to-lm75.txt.patch diff --git a/patch/0005-dts-ac5-marvell-Add-switching-watchdog-node.patch b/patches-sonic/0005-dts-ac5-marvell-Add-switching-watchdog-node.patch similarity index 100% rename from patch/0005-dts-ac5-marvell-Add-switching-watchdog-node.patch rename to patches-sonic/0005-dts-ac5-marvell-Add-switching-watchdog-node.patch diff --git a/patches-sonic/0005-platform-mellanox-mlxreg-hotplug-use-sysfs_emit-inst.patch b/patches-sonic/0005-platform-mellanox-mlxreg-hotplug-use-sysfs_emit-inst.patch new file mode 100644 index 000000000..813a66ca8 --- /dev/null +++ b/patches-sonic/0005-platform-mellanox-mlxreg-hotplug-use-sysfs_emit-inst.patch @@ -0,0 +1,38 @@ +From 9d23974f2c561e438fdf48266b327e1424884ff3 Mon Sep 17 00:00:00 2001 +From: Ai Chao +Date: Thu, 16 Jan 2025 16:10:00 +0800 +Subject: [PATCH 05/78] platform/mellanox: mlxreg-hotplug: use sysfs_emit() + instead of sprintf() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Follow the advice in Documentation/filesystems/sysfs.rst: +show() should only use sysfs_emit() or sysfs_emit_at() when formatting +the value to be returned to user space. + +Signed-off-by: Ai Chao +Acked-by: Vadim Pasternak +Link: https://lore.kernel.org/r/20250116081000.2900435-1-aichao@kylinos.cn +Reviewed-by: Ilpo Järvinen +Signed-off-by: Ilpo Järvinen +--- + drivers/platform/mellanox/mlxreg-hotplug.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/platform/mellanox/mlxreg-hotplug.c b/drivers/platform/mellanox/mlxreg-hotplug.c +index 0ce9fff..40d5b99 100644 +--- a/drivers/platform/mellanox/mlxreg-hotplug.c ++++ b/drivers/platform/mellanox/mlxreg-hotplug.c +@@ -232,7 +232,7 @@ static ssize_t mlxreg_hotplug_attr_show(struct device *dev, + regval = !!(regval & data->mask); + } + +- return sprintf(buf, "%u\n", regval); ++ return sysfs_emit(buf, "%u\n", regval); + } + + #define PRIV_ATTR(i) priv->mlxreg_hotplug_attr[i] +-- +2.8.4 + diff --git a/patch/0006-Pensando-Elba-support-in-the-Cadence-EMMC-host-contr.patch b/patches-sonic/0006-Pensando-Elba-support-in-the-Cadence-EMMC-host-contr.patch similarity index 100% rename from patch/0006-Pensando-Elba-support-in-the-Cadence-EMMC-host-contr.patch rename to patches-sonic/0006-Pensando-Elba-support-in-the-Cadence-EMMC-host-contr.patch diff --git a/patch/0006-device-tree-bindinds-add-NXP-PCT2075-as-compatible-d.patch b/patches-sonic/0006-device-tree-bindinds-add-NXP-PCT2075-as-compatible-d.patch similarity index 100% rename from patch/0006-device-tree-bindinds-add-NXP-PCT2075-as-compatible-d.patch rename to patches-sonic/0006-device-tree-bindinds-add-NXP-PCT2075-as-compatible-d.patch diff --git a/patch/0006-mmc-xenon-Add-ac5-support-via-bounce-buffer.patch b/patches-sonic/0006-mmc-xenon-Add-ac5-support-via-bounce-buffer.patch similarity index 100% rename from patch/0006-mmc-xenon-Add-ac5-support-via-bounce-buffer.patch rename to patches-sonic/0006-mmc-xenon-Add-ac5-support-via-bounce-buffer.patch diff --git a/patches-sonic/0006-platform-mellanox-mlxreg-io-use-sysfs_emit-instead-o.patch b/patches-sonic/0006-platform-mellanox-mlxreg-io-use-sysfs_emit-instead-o.patch new file mode 100644 index 000000000..ec8b073c5 --- /dev/null +++ b/patches-sonic/0006-platform-mellanox-mlxreg-io-use-sysfs_emit-instead-o.patch @@ -0,0 +1,38 @@ +From 2f6b30b57d84721ea1f31a22686b57106037a964 Mon Sep 17 00:00:00 2001 +From: Ai Chao +Date: Thu, 16 Jan 2025 16:11:29 +0800 +Subject: [PATCH 06/78] platform/mellanox: mlxreg-io: use sysfs_emit() instead + of sprintf() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Follow the advice in Documentation/filesystems/sysfs.rst: +show() should only use sysfs_emit() or sysfs_emit_at() when formatting +the value to be returned to user space. + +Signed-off-by: Ai Chao +Acked-by: Vadim Pasternak +Link: https://lore.kernel.org/r/20250116081129.2902274-1-aichao@kylinos.cn +Reviewed-by: Ilpo Järvinen +Signed-off-by: Ilpo Järvinen +--- + drivers/platform/mellanox/mlxreg-io.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/platform/mellanox/mlxreg-io.c b/drivers/platform/mellanox/mlxreg-io.c +index ee7bd62..c502f2b 100644 +--- a/drivers/platform/mellanox/mlxreg-io.c ++++ b/drivers/platform/mellanox/mlxreg-io.c +@@ -126,7 +126,7 @@ mlxreg_io_attr_show(struct device *dev, struct device_attribute *attr, + + mutex_unlock(&priv->io_lock); + +- return sprintf(buf, "%u\n", regval); ++ return sysfs_emit(buf, "%u\n", regval); + + access_error: + mutex_unlock(&priv->io_lock); +-- +2.8.4 + diff --git a/patches-sonic/0007-mlxbf-bootctl-Support-sysfs-entries-for-RTC-battery-.patch b/patches-sonic/0007-mlxbf-bootctl-Support-sysfs-entries-for-RTC-battery-.patch new file mode 100644 index 000000000..399d696d8 --- /dev/null +++ b/patches-sonic/0007-mlxbf-bootctl-Support-sysfs-entries-for-RTC-battery-.patch @@ -0,0 +1,115 @@ +From 224f54a149e3fb3ef5125823ee6847750e05c4b9 Mon Sep 17 00:00:00 2001 +From: Xiangrong Li +Date: Fri, 24 Jan 2025 14:46:55 +0000 +Subject: [PATCH 07/78] mlxbf-bootctl: Support sysfs entries for RTC battery + status +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This patch extends the mlxbf-bootctl driver's sysfs entries +to support read access for the board's RTC battery status. +A successful read from this attribute returns the status of +the board's RTC battery. The RTC battery status register is +also cleared upon successful read operation. + +Signed-off-by: Xiangrong Li +Reviewed-by: David Thompson +Reviewed-by: Ilpo Järvinen +Link: https://lore.kernel.org/r/20250124144655.48564-1-xiangrongl@nvidia.com +Signed-off-by: Ilpo Järvinen +--- + .../ABI/testing/sysfs-platform-mellanox-bootctl | 10 ++++++++++ + drivers/platform/mellanox/mlxbf-bootctl.c | 20 ++++++++++++++++++++ + drivers/platform/mellanox/mlxbf-bootctl.h | 5 +++++ + 3 files changed, 35 insertions(+) + +diff --git a/Documentation/ABI/testing/sysfs-platform-mellanox-bootctl b/Documentation/ABI/testing/sysfs-platform-mellanox-bootctl +index 65ed386..09f783f 100644 +--- a/Documentation/ABI/testing/sysfs-platform-mellanox-bootctl ++++ b/Documentation/ABI/testing/sysfs-platform-mellanox-bootctl +@@ -150,3 +150,13 @@ Description: + The "mfg_lock" sysfs attribute is write-only. + A successful write to this attribute will latch the + board-level attributes into EEPROM, making them read-only. ++ ++What: /sys/bus/platform/devices/MLNXBF04:00/rtc_battery ++Date: June 2025 ++KernelVersion: 6.15 ++Contact: "Xiangrong Li " ++Description: ++ The "rtc_battery" sysfs attribute is read-only. ++ A successful read from this attribute returns the status of ++ the board's RTC battery. The RTC battery status register is ++ also cleared upon successful read operation. +diff --git a/drivers/platform/mellanox/mlxbf-bootctl.c b/drivers/platform/mellanox/mlxbf-bootctl.c +index e8530ef..25ffae1 100644 +--- a/drivers/platform/mellanox/mlxbf-bootctl.c ++++ b/drivers/platform/mellanox/mlxbf-bootctl.c +@@ -91,6 +91,7 @@ static const char * const mlxbf_rsh_log_level[] = { + static DEFINE_MUTEX(icm_ops_lock); + static DEFINE_MUTEX(os_up_lock); + static DEFINE_MUTEX(mfg_ops_lock); ++static DEFINE_MUTEX(rtc_ops_lock); + + /* + * Objects are stored within the MFG partition per type. +@@ -489,6 +490,23 @@ static ssize_t large_icm_store(struct device *dev, + return res.a0 ? -EPERM : count; + } + ++static ssize_t rtc_battery_show(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct arm_smccc_res res; ++ ++ mutex_lock(&rtc_ops_lock); ++ arm_smccc_smc(MLNX_HANDLE_GET_RTC_LOW_BATT, 0, 0, 0, 0, ++ 0, 0, 0, &res); ++ mutex_unlock(&rtc_ops_lock); ++ ++ if (res.a0) ++ return -EPERM; ++ ++ return sysfs_emit(buf, "0x%lx\n", res.a1); ++} ++ + static ssize_t os_up_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +@@ -906,6 +924,7 @@ static DEVICE_ATTR_RW(sn); + static DEVICE_ATTR_RW(uuid); + static DEVICE_ATTR_RW(rev); + static DEVICE_ATTR_WO(mfg_lock); ++static DEVICE_ATTR_RO(rtc_battery); + + static struct attribute *mlxbf_bootctl_attrs[] = { + &dev_attr_post_reset_wdog.attr, +@@ -925,6 +944,7 @@ static struct attribute *mlxbf_bootctl_attrs[] = { + &dev_attr_uuid.attr, + &dev_attr_rev.attr, + &dev_attr_mfg_lock.attr, ++ &dev_attr_rtc_battery.attr, + NULL + }; + +diff --git a/drivers/platform/mellanox/mlxbf-bootctl.h b/drivers/platform/mellanox/mlxbf-bootctl.h +index 1299750..90bbbdc 100644 +--- a/drivers/platform/mellanox/mlxbf-bootctl.h ++++ b/drivers/platform/mellanox/mlxbf-bootctl.h +@@ -103,6 +103,11 @@ + */ + #define MLNX_HANDLE_OS_UP 0x82000014 + ++/* ++ * SMC function ID to get and clear the RTC low voltage bit ++ */ ++#define MLNX_HANDLE_GET_RTC_LOW_BATT 0x82000023 ++ + /* SMC function IDs for SiP Service queries */ + #define MLXBF_BOOTCTL_SIP_SVC_CALL_COUNT 0x8200ff00 + #define MLXBF_BOOTCTL_SIP_SVC_UID 0x8200ff01 +-- +2.8.4 + diff --git a/patch/0007-spi-dw-Support-Pensando-Elba-custom-chip-select.patch b/patches-sonic/0007-spi-dw-Support-Pensando-Elba-custom-chip-select.patch similarity index 100% rename from patch/0007-spi-dw-Support-Pensando-Elba-custom-chip-select.patch rename to patches-sonic/0007-spi-dw-Support-Pensando-Elba-custom-chip-select.patch diff --git a/patches-sonic/0007-usb-ehci-Add-support-for-ac5-with-DMA-mask-64-bit.patch b/patches-sonic/0007-usb-ehci-Add-support-for-ac5-with-DMA-mask-64-bit.patch new file mode 100644 index 000000000..1c50c49ab --- /dev/null +++ b/patches-sonic/0007-usb-ehci-Add-support-for-ac5-with-DMA-mask-64-bit.patch @@ -0,0 +1,37 @@ +From ec02d4b124ea5dea90ce76fa3e1030f22c5f9e22 Mon Sep 17 00:00:00 2001 +From: Pavan Naregundi +Date: Mon, 13 Mar 2023 10:01:51 +0000 +Subject: [PATCH] usb:ehci: Add support for ac5 with DMA mask 64-bit + +Change DMA bit mask to 64-bit addressing like it is done in K-6.1 +for "ac5-ehci" 98DX25xx already present and supported by Kernel-6.12 + +Signed-off-by: Yuval Shaia +Tested-by: Raz Adashi +Reviewed-by: Raz Adashi +Signed-off-by: Yan Markman +--- + drivers/usb/host/ehci-orion.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/usb/host/ehci-orion.c b/drivers/usb/host/ehci-orion.c +index ad145a54c..03f04a3da 100644 +--- a/drivers/usb/host/ehci-orion.c ++++ b/drivers/usb/host/ehci-orion.c +@@ -68,11 +68,11 @@ static struct hc_driver __read_mostly ehci_orion_hc_driver; + /* + * Legacy DMA mask is 32 bit. + * AC5 has the DDR starting at 8GB, hence it requires +- * a larger (34-bit) DMA mask, in order for DMA allocations ++ * a larger (34-bit or even 64-bit) DMA mask, in order for DMA allocations + * to succeed: + */ + static const u64 dma_mask_orion = DMA_BIT_MASK(32); +-static const u64 dma_mask_ac5 = DMA_BIT_MASK(34); ++static const u64 dma_mask_ac5 = DMA_BIT_MASK(64); + + /* + * Implement Orion USB controller specification guidelines +-- +2.34.1 + diff --git a/patch/0007-usb-ehci-Add-support-for-ac5.patch b/patches-sonic/0007-usb-ehci-Add-support-for-ac5.patch similarity index 100% rename from patch/0007-usb-ehci-Add-support-for-ac5.patch rename to patches-sonic/0007-usb-ehci-Add-support-for-ac5.patch diff --git a/patch/0008-Initial-support-for-the-Pensando-Elba-SoC.patch b/patches-sonic/0008-Initial-support-for-the-Pensando-Elba-SoC.patch similarity index 100% rename from patch/0008-Initial-support-for-the-Pensando-Elba-SoC.patch rename to patches-sonic/0008-Initial-support-for-the-Pensando-Elba-SoC.patch diff --git a/patches-sonic/0008-mlxbf-bootctl-use-sysfs_emit_at-in-secure_boot_fuse_.patch b/patches-sonic/0008-mlxbf-bootctl-use-sysfs_emit_at-in-secure_boot_fuse_.patch new file mode 100644 index 000000000..8afc38aa6 --- /dev/null +++ b/patches-sonic/0008-mlxbf-bootctl-use-sysfs_emit_at-in-secure_boot_fuse_.patch @@ -0,0 +1,47 @@ +From 23b2eeacd3bfb7365002f623cbce2fadda8175ac Mon Sep 17 00:00:00 2001 +From: David Thompson +Date: Mon, 7 Apr 2025 13:25:58 +0000 +Subject: [PATCH 08/78] mlxbf-bootctl: use sysfs_emit_at() in + secure_boot_fuse_state_show() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +A warning is seen when running the latest kernel on a BlueField SOC: +[251.512704] ------------[ cut here ]------------ +[251.512711] invalid sysfs_emit: buf:0000000003aa32ae +[251.512720] WARNING: CPU: 1 PID: 705264 at fs/sysfs/file.c:767 sysfs_emit+0xac/0xc8 + +The warning is triggered because the mlxbf-bootctl driver invokes +"sysfs_emit()" with a buffer pointer that is not aligned to the +start of the page. The driver should instead use "sysfs_emit_at()" +to support non-zero offsets into the destination buffer. + +Fixes: 9886f575de5a ("platform/mellanox: mlxbf-bootctl: use sysfs_emit() instead of sprintf()") +Signed-off-by: David Thompson +Link: https://lore.kernel.org/r/20250407132558.2418719-1-davthompson@nvidia.com +Reviewed-by: Ilpo Järvinen +Signed-off-by: Ilpo Järvinen +--- + drivers/platform/mellanox/mlxbf-bootctl.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/platform/mellanox/mlxbf-bootctl.c b/drivers/platform/mellanox/mlxbf-bootctl.c +index 25ffae1..fd7fb42 100644 +--- a/drivers/platform/mellanox/mlxbf-bootctl.c ++++ b/drivers/platform/mellanox/mlxbf-bootctl.c +@@ -333,9 +333,9 @@ static ssize_t secure_boot_fuse_state_show(struct device *dev, + else + status = valid ? "Invalid" : "Free"; + } +- buf_len += sysfs_emit(buf + buf_len, "%d:%s ", key, status); ++ buf_len += sysfs_emit_at(buf, buf_len, "%d:%s ", key, status); + } +- buf_len += sysfs_emit(buf + buf_len, "\n"); ++ buf_len += sysfs_emit_at(buf, buf_len, "\n"); + + return buf_len; + } +-- +2.8.4 + diff --git a/patch/0008-mv6xxx-Fix-i2c-lock-due-to-arb-loss.patch b/patches-sonic/0008-mv6xxx-Fix-i2c-lock-due-to-arb-loss.patch similarity index 79% rename from patch/0008-mv6xxx-Fix-i2c-lock-due-to-arb-loss.patch rename to patches-sonic/0008-mv6xxx-Fix-i2c-lock-due-to-arb-loss.patch index 393c73a76..df5cdb015 100644 --- a/patch/0008-mv6xxx-Fix-i2c-lock-due-to-arb-loss.patch +++ b/patches-sonic/0008-mv6xxx-Fix-i2c-lock-due-to-arb-loss.patch @@ -1,4 +1,4 @@ -From 1c7573db2c31e4b30662554d230325ffcbb884e1 Mon Sep 17 00:00:00 2001 +From f8044a555a9994bbf401ce028450d285942d9dde Mon Sep 17 00:00:00 2001 From: Keshav Gupta Date: Mon, 16 Oct 2023 15:14:03 +0000 Subject: [PATCH] mv6xxx: Fix i2c lock due to arb-loss @@ -12,12 +12,13 @@ gpio to emulate bus toggling, so slave will finish its transimission. Tested-by: Raz Adashi Reviewed-by: Raz Adashi Signed-off-by: Noam Liron +Signed-off-by: Yan Markman --- - drivers/i2c/busses/i2c-mv64xxx.c | 81 ++++++++++++++++++++++++++++++++ - 1 file changed, 81 insertions(+) + drivers/i2c/busses/i2c-mv64xxx.c | 85 ++++++++++++++++++++++++++++++++ + 1 file changed, 85 insertions(+) diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c -index 878c076eb..180c32cf9 100644 +index 29f94efed..13e9bdeb4 100644 --- a/drivers/i2c/busses/i2c-mv64xxx.c +++ b/drivers/i2c/busses/i2c-mv64xxx.c @@ -9,6 +9,8 @@ @@ -29,7 +30,7 @@ index 878c076eb..180c32cf9 100644 #include #include #include -@@ -27,6 +29,7 @@ +@@ -26,6 +28,7 @@ #include #include #include @@ -37,7 +38,7 @@ index 878c076eb..180c32cf9 100644 #define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1) #define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7) -@@ -105,6 +108,7 @@ enum { +@@ -104,6 +107,7 @@ enum { MV64XXX_I2C_ACTION_RCV_DATA, MV64XXX_I2C_ACTION_RCV_DATA_STOP, MV64XXX_I2C_ACTION_SEND_STOP, @@ -45,7 +46,7 @@ index 878c076eb..180c32cf9 100644 }; struct mv64xxx_i2c_regs { -@@ -151,6 +155,11 @@ struct mv64xxx_i2c_data { +@@ -150,6 +154,11 @@ struct mv64xxx_i2c_data { bool clk_n_base_0; struct i2c_bus_recovery_info rinfo; bool atomic; @@ -57,7 +58,7 @@ index 878c076eb..180c32cf9 100644 }; static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = { -@@ -319,6 +328,11 @@ mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status) +@@ -318,6 +327,11 @@ mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status) drv_data->state = MV64XXX_I2C_STATE_IDLE; break; @@ -69,17 +70,17 @@ index 878c076eb..180c32cf9 100644 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */ case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */ case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */ -@@ -357,6 +371,9 @@ static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data) +@@ -356,6 +370,9 @@ static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data) static void mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data) { + struct pinctrl *pc; -+ int i, ret; ++ int i, ret, ret2; + switch(drv_data->action) { case MV64XXX_I2C_ACTION_SEND_RESTART: /* We should only get here if we have further messages */ -@@ -410,6 +427,46 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data) +@@ -409,6 +426,50 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data) drv_data->reg_base + drv_data->reg_offsets.control); break; @@ -94,11 +95,12 @@ index 878c076eb..180c32cf9 100644 + + /* Move i2c MPPs to GPIOs */ + if (pinctrl_select_state(pc, drv_data->i2c_gpio_state) >= 0) { ++ /* Get GPIO for temporary usage */ + ret = devm_gpio_request_one(drv_data->adapter.dev.parent, -+ drv_data->scl_gpio, GPIOF_DIR_OUT, NULL); -+ ret |= devm_gpio_request_one(drv_data->adapter.dev.parent, -+ drv_data->sda_gpio, GPIOF_DIR_OUT, NULL); -+ if (!ret) { ++ drv_data->scl_gpio, GPIOF_OUT_INIT_LOW, NULL); ++ ret2 = devm_gpio_request_one(drv_data->adapter.dev.parent, ++ drv_data->sda_gpio, GPIOF_OUT_INIT_LOW, NULL); ++ if (!ret && !ret2) { + /* toggle i2c scl 10 times, for the slave that occupies + * the bus Tx its remaining data, and release the bus + */ @@ -107,11 +109,14 @@ index 878c076eb..180c32cf9 100644 + mdelay(1); + gpio_set_value(drv_data->scl_gpio, 0); + }; -+ -+ devm_gpiod_put(drv_data->adapter.dev.parent, -+ drv_data->scl_gpio); -+ devm_gpiod_put(drv_data->adapter.dev.parent, -+ drv_data->sda_gpio); ++ /* Free temporary GPIO */ ++ gpio_free(drv_data->scl_gpio); ++ gpio_free(drv_data->sda_gpio); ++ } else { ++ if (!ret) ++ gpio_free(drv_data->scl_gpio); ++ if (!ret2) ++ gpio_free(drv_data->sda_gpio); + } + + /* restore i2c MPPs */ @@ -126,7 +131,7 @@ index 878c076eb..180c32cf9 100644 case MV64XXX_I2C_ACTION_RCV_DATA_STOP: drv_data->msg->buf[drv_data->byte_posn++] = readl(drv_data->reg_base + drv_data->reg_offsets.data); -@@ -986,6 +1043,7 @@ mv64xxx_i2c_probe(struct platform_device *pd) +@@ -985,6 +1046,7 @@ mv64xxx_i2c_probe(struct platform_device *pd) { struct mv64xxx_i2c_data *drv_data; struct mv64xxx_i2c_pdata *pdata = dev_get_platdata(&pd->dev); @@ -134,7 +139,7 @@ index 878c076eb..180c32cf9 100644 int rc; if ((!pdata && !pd->dev.of_node)) -@@ -1041,6 +1099,29 @@ mv64xxx_i2c_probe(struct platform_device *pd) +@@ -1040,6 +1102,29 @@ mv64xxx_i2c_probe(struct platform_device *pd) if (rc == -EPROBE_DEFER) return rc; @@ -165,5 +170,5 @@ index 878c076eb..180c32cf9 100644 drv_data->adapter.algo = &mv64xxx_i2c_algo; drv_data->adapter.owner = THIS_MODULE; -- -2.25.1 +2.34.1 diff --git a/patch/0009-drivers-reset-Add-emmc-hardware-reset.patch b/patches-sonic/0009-drivers-reset-Add-emmc-hardware-reset.patch similarity index 100% rename from patch/0009-drivers-reset-Add-emmc-hardware-reset.patch rename to patches-sonic/0009-drivers-reset-Add-emmc-hardware-reset.patch diff --git a/patch/0009-dt-bindings-marvell-Add-ARMADA-7K-properties.patch b/patches-sonic/0009-dt-bindings-marvell-Add-ARMADA-7K-properties.patch similarity index 100% rename from patch/0009-dt-bindings-marvell-Add-ARMADA-7K-properties.patch rename to patches-sonic/0009-dt-bindings-marvell-Add-ARMADA-7K-properties.patch diff --git a/patches-sonic/0009-platform-mellanox-mlxbf-pmc-Support-additional-PMC-b.patch b/patches-sonic/0009-platform-mellanox-mlxbf-pmc-Support-additional-PMC-b.patch new file mode 100644 index 000000000..a2011cdd4 --- /dev/null +++ b/patches-sonic/0009-platform-mellanox-mlxbf-pmc-Support-additional-PMC-b.patch @@ -0,0 +1,246 @@ +From b8a5dec9929fa888061292fb066e0566181cd3f6 Mon Sep 17 00:00:00 2001 +From: Shravan Kumar Ramani +Date: Wed, 23 Apr 2025 04:31:03 -0400 +Subject: [PATCH 09/78] platform/mellanox: mlxbf-pmc: Support additional PMC + blocks +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add list of events and counters from the following blocks: APT (ARM Processor +Tile), GGA (Global Generic Accelerator), MSN (Memory Stasher and Navigator), +EMI (External Memory Interface) and PRNF (PCIe Request Node). +If any of the fields populated from the ACPI table (like apt_num) cannot be +read, assign the corresponding block count to be 0 instead of failing probe +to maintain compatibility with older firmware. + +Signed-off-by: Shravan Kumar Ramani +Reviewed-by: David Thompson +Link: https://lore.kernel.org/r/20250423083103.5240-1-shravankr@nvidia.com +Reviewed-by: Ilpo Järvinen +Signed-off-by: Ilpo Järvinen +--- + drivers/platform/mellanox/mlxbf-pmc.c | 155 ++++++++++++++++++++++++++++++++-- + 1 file changed, 150 insertions(+), 5 deletions(-) + +diff --git a/drivers/platform/mellanox/mlxbf-pmc.c b/drivers/platform/mellanox/mlxbf-pmc.c +index 771a24c..a1c529f 100644 +--- a/drivers/platform/mellanox/mlxbf-pmc.c ++++ b/drivers/platform/mellanox/mlxbf-pmc.c +@@ -33,7 +33,7 @@ + #define MLXBF_PMC_EVENT_SET_BF3 2 + #define MLXBF_PMC_EVENT_INFO_LEN 100 + +-#define MLXBF_PMC_MAX_BLOCKS 30 ++#define MLXBF_PMC_MAX_BLOCKS 40 + #define MLXBF_PMC_MAX_ATTRS 70 + #define MLXBF_PMC_INFO_SZ 4 + #define MLXBF_PMC_REG_SIZE 8 +@@ -139,6 +139,7 @@ struct mlxbf_pmc_block_info { + * @pdev: The kernel structure representing the device + * @total_blocks: Total number of blocks + * @tile_count: Number of tiles in the system ++ * @apt_enable: Info on enabled APTs + * @llt_enable: Info on enabled LLTs + * @mss_enable: Info on enabled MSSs + * @group_num: Group number assigned to each valid block +@@ -154,6 +155,7 @@ struct mlxbf_pmc_context { + struct platform_device *pdev; + u32 total_blocks; + u32 tile_count; ++ u8 apt_enable; + u8 llt_enable; + u8 mss_enable; + u32 group_num; +@@ -893,6 +895,107 @@ static const struct mlxbf_pmc_events mlxbf_pmc_clock_events[] = { + { 0x6c, "REFERENCE_WINDOW_WIDTH_REF_156" }, + }; + ++static const struct mlxbf_pmc_events mlxbf_pmc_gga_events[] = { ++ { 0, "GGA_PERF_DESC_WQE_STRB" }, ++ { 5, "GGA_PERF_DESC_CQE_STRB" }, ++ { 8, "GGA_PERF_DESC_TPT_REQUEST_STRB" }, ++ { 17, "GGA_PERF_DESC_TPT_RESPONSESTRB" }, ++ { 120, "GGA_PERF_DESC_ENGINE0_IN_DATA_STRB" }, ++ { 121, "GGA_PERF_DESC_ENGINE1_IN_DATA_STRB" }, ++ { 122, "GGA_PERF_DESC_ENGINE2_IN_DATA_STRB" }, ++ { 123, "GGA_PERF_DESC_ENGINE3_IN_DATA_STRB" }, ++ { 124, "GGA_PERF_DESC_ENGINE4_IN_DATA_STRB" }, ++ { 125, "GGA_PERF_DESC_ENGINE5_IN_DATA_STRB" }, ++ { 126, "GGA_PERF_DESC_ENGINE6_IN_DATA_STRB" }, ++ { 127, "GGA_PERF_DESC_ENGINE7_IN_DATA_STRB" }, ++ { 128, "GGA_PERF_DESC_ENGINE8_IN_DATA_STRB" }, ++ { 129, "GGA_PERF_DESC_ENGINE9_IN_DATA_STRB" }, ++ { 130, "GGA_PERF_DESC_ENGINE10_IN_DATA_STRB" }, ++ { 131, "GGA_PERF_DESC_ENGINE11_IN_DATA_STRB" }, ++ { 132, "GGA_PERF_DESC_ENGINE12_IN_DATA_STRB" }, ++ { 133, "GGA_PERF_DESC_ENGINE13_IN_DATA_STRB" }, ++ { 134, "GGA_PERF_DESC_ENGINE14_IN_DATA_STRB" }, ++ { 195, "GGA_PERF_DESC_ENGINE0_OUT_DATA_STRB" }, ++ { 196, "GGA_PERF_DESC_ENGINE1_OUT_DATA_STRB" }, ++ { 197, "GGA_PERF_DESC_ENGINE2_OUT_DATA_STRB" }, ++ { 198, "GGA_PERF_DESC_ENGINE3_OUT_DATA_STRB" }, ++ { 199, "GGA_PERF_DESC_ENGINE4_OUT_DATA_STRB" }, ++ { 200, "GGA_PERF_DESC_ENGINE5_OUT_DATA_STRB" }, ++ { 201, "GGA_PERF_DESC_ENGINE6_OUT_DATA_STRB" }, ++ { 202, "GGA_PERF_DESC_ENGINE7_OUT_DATA_STRB" }, ++ { 203, "GGA_PERF_DESC_ENGINE8_OUT_DATA_STRB" }, ++ { 204, "GGA_PERF_DESC_ENGINE9_OUT_DATA_STRB" }, ++ { 205, "GGA_PERF_DESC_ENGINE10_OUT_DATA_STRB" }, ++ { 206, "GGA_PERF_DESC_ENGINE11_OUT_DATA_STRB" }, ++ { 207, "GGA_PERF_DESC_ENGINE12_OUT_DATA_STRB" }, ++ { 208, "GGA_PERF_DESC_ENGINE13_OUT_DATA_STRB" }, ++ { 209, "GGA_PERF_DESC_ENGINE14_OUT_DATA_STRB" }, ++}; ++ ++static const struct mlxbf_pmc_events mlxbf_pmc_apt_events[] = { ++ { 0, "APT_DATA_0" }, ++ { 1, "APT_DATA_1" }, ++ { 2, "APT_DATA_2" }, ++ { 3, "APT_DATA_3" }, ++ { 4, "APT_DATA_4" }, ++ { 5, "APT_DATA_5" }, ++ { 6, "APT_DATA_6" }, ++ { 7, "APT_DATA_7" }, ++ { 8, "APT_DATA_8" }, ++ { 9, "APT_DATA_9" }, ++ { 10, "APT_DATA_10" }, ++ { 11, "APT_DATA_11" }, ++ { 12, "APT_DATA_12" }, ++ { 13, "APT_DATA_13" }, ++ { 14, "APT_DATA_14" }, ++ { 15, "APT_DATA_15" }, ++ { 16, "APT_DATA_16" }, ++ { 17, "APT_DATA_17" }, ++ { 18, "APT_DATA_18" }, ++ { 19, "APT_DATA_19" }, ++ { 20, "APT_DATA_20" }, ++ { 21, "APT_DATA_21" }, ++}; ++ ++static const struct mlxbf_pmc_events mlxbf_pmc_emi_events[] = { ++ { 0, "MCH_WR_IN_MCH_REQ_IN_STRB" }, ++ { 10, "MCH_RD_IN_MCH_REQ_IN_STRB" }, ++ { 20, "MCH_RD_RESP_DATA_MCH_RESP_OUT_STRB" }, ++ { 98, "EMI_ARBITER_EARB2CTRL_STRB" }, ++ { 99, "EMI_ARBITER_EARB2CTRL_RAS_STRB" }, ++ { 100, "EMI_ARBITER_EARB2CTRL_CAS_STRB" }, ++}; ++ ++static const struct mlxbf_pmc_events mlxbf_pmc_prnf_events[] = { ++ { 0, "PRNF_DMA_RD_TLP_REQ" }, ++ { 1, "PRNF_DMA_RD_ICMC_BYPASS_REQ" }, ++ { 8, "PRNF_DMA_RD_TLP_SENT_TO_CHI" }, ++ { 11, "PRNF_DMA_RD_CHI_RES" }, ++ { 17, "PRNF_DMA_RD_TLP_RES_SENT" }, ++ { 18, "PRNF_DMA_WR_WR0_SLICE_ALLOC_RO" }, ++ { 19, "PRNF_DMA_WR_WR0_SLICE_ALLOC_NRO" }, ++ { 24, "PRNF_DMA_WR_WR1_SLICE_ALLOC_RO" }, ++ { 25, "PRNF_DMA_WR_WR1_SLICE_ALLOC_NRO" }, ++ { 30, "PRNF_PIO_POSTED_REQ_PUSH" }, ++ { 31, "PRNF_PIO_POSTED_REQ_POP" }, ++ { 32, "PRNF_PIO_NP_REQ_PUSH" }, ++ { 33, "PRNF_PIO_NP_REQ_POP" }, ++ { 34, "PRNF_PIO_COMP_RO_PUSH" }, ++ { 35, "PRNF_PIO_COMP_RO_POP" }, ++ { 36, "PRNF_PIO_COMP_NRO_PUSH" }, ++ { 37, "PRNF_PIO_COMP_NRO_POP" }, ++}; ++ ++static const struct mlxbf_pmc_events mlxbf_pmc_msn_events[] = { ++ { 46, "MSN_CORE_MMA_WQE_DONE_PUSH_STRB" }, ++ { 116, "MSN_CORE_MSN2MMA_WQE_STRB" }, ++ { 164, "MSN_CORE_WQE_TOP_TILE_WQE_STRB" }, ++ { 168, "MSN_CORE_TPT_TOP_GGA_REQ_STRB" }, ++ { 171, "MSN_CORE_TPT_TOP_MMA_REQ_STRB" }, ++ { 174, "MSN_CORE_TPT_TOP_GGA_RES_STRB" }, ++ { 177, "MSN_CORE_TPT_TOP_MMA_RES_STRB" }, ++}; ++ + static struct mlxbf_pmc_context *pmc; + + /* UUID used to probe ATF service. */ +@@ -1069,6 +1172,21 @@ static const struct mlxbf_pmc_events *mlxbf_pmc_event_list(const char *blk, size + } else if (strstr(blk, "clock_measure")) { + events = mlxbf_pmc_clock_events; + size = ARRAY_SIZE(mlxbf_pmc_clock_events); ++ } else if (strstr(blk, "gga")) { ++ events = mlxbf_pmc_gga_events; ++ size = ARRAY_SIZE(mlxbf_pmc_gga_events); ++ } else if (strstr(blk, "apt")) { ++ events = mlxbf_pmc_apt_events; ++ size = ARRAY_SIZE(mlxbf_pmc_apt_events); ++ } else if (strstr(blk, "emi")) { ++ events = mlxbf_pmc_emi_events; ++ size = ARRAY_SIZE(mlxbf_pmc_emi_events); ++ } else if (strstr(blk, "prnf")) { ++ events = mlxbf_pmc_prnf_events; ++ size = ARRAY_SIZE(mlxbf_pmc_prnf_events); ++ } else if (strstr(blk, "msn")) { ++ events = mlxbf_pmc_msn_events; ++ size = ARRAY_SIZE(mlxbf_pmc_msn_events); + } else { + events = NULL; + size = 0; +@@ -2056,6 +2174,18 @@ static int mlxbf_pmc_map_counters(struct device *dev) + continue; + } + ++ /* Create sysfs only for enabled EMI blocks */ ++ if (strstr(pmc->block_name[i], "emi") && ++ pmc->event_set == MLXBF_PMC_EVENT_SET_BF3) { ++ unsigned int emi_num; ++ ++ if (sscanf(pmc->block_name[i], "emi%u", &emi_num) != 1) ++ continue; ++ ++ if (!((pmc->mss_enable >> (emi_num / 2)) & 0x1)) ++ continue; ++ } ++ + /* Create sysfs only for enabled LLT blocks */ + if (strstr(pmc->block_name[i], "llt_miss")) { + unsigned int llt_num; +@@ -2075,6 +2205,17 @@ static int mlxbf_pmc_map_counters(struct device *dev) + continue; + } + ++ /* Create sysfs only for enabled APT blocks */ ++ if (strstr(pmc->block_name[i], "apt")) { ++ unsigned int apt_num; ++ ++ if (sscanf(pmc->block_name[i], "apt%u", &apt_num) != 1) ++ continue; ++ ++ if (!((pmc->apt_enable >> apt_num) & 0x1)) ++ continue; ++ } ++ + ret = device_property_read_u64_array(dev, pmc->block_name[i], + info, MLXBF_PMC_INFO_SZ); + if (ret) +@@ -2171,13 +2312,17 @@ static int mlxbf_pmc_probe(struct platform_device *pdev) + return -EFAULT; + + if (device_property_read_u32(dev, "tile_num", &pmc->tile_count)) { ++ if (device_property_read_u8(dev, "apt_enable", &pmc->apt_enable)) { ++ dev_warn(dev, "Number of APTs undefined, ignoring blocks\n"); ++ pmc->apt_enable = 0; ++ } + if (device_property_read_u8(dev, "llt_enable", &pmc->llt_enable)) { +- dev_err(dev, "Number of tiles/LLTs undefined\n"); +- return -EINVAL; ++ dev_warn(dev, "Number of LLTs undefined, ignoring blocks\n"); ++ pmc->llt_enable = 0; + } + if (device_property_read_u8(dev, "mss_enable", &pmc->mss_enable)) { +- dev_err(dev, "Number of tiles/MSSs undefined\n"); +- return -EINVAL; ++ dev_warn(dev, "Number of MSSs undefined, ignoring blocks\n"); ++ pmc->mss_enable = 0; + } + } + +-- +2.8.4 + diff --git a/patch/0010-dts-marvell-Add-support-for-7020-comexpress.patch b/patches-sonic/0010-dts-marvell-Add-support-for-7020-comexpress.patch similarity index 90% rename from patch/0010-dts-marvell-Add-support-for-7020-comexpress.patch rename to patches-sonic/0010-dts-marvell-Add-support-for-7020-comexpress.patch index 22c427f63..c3f28075e 100644 --- a/patch/0010-dts-marvell-Add-support-for-7020-comexpress.patch +++ b/patches-sonic/0010-dts-marvell-Add-support-for-7020-comexpress.patch @@ -1,3 +1,4 @@ +From 392cb3d2894af3eca861b74318aa719f2218158e Mon Sep 17 00:00:00 2001 From: Keshav Gupta Date: Wed, 4 Oct 2023 06:46:29 +0000 Subject: [PATCH] dts: marvell: Add support for 7020 comexpress @@ -18,6 +19,7 @@ Also added SDIO mode pin control configuration for CP0. Signed-off-by: Eyal Oron Tested-by: Raz Adashi Reviewed-by: Raz Adashi +Signed-off-by: Yan Markman --- arch/arm64/boot/dts/marvell/Makefile | 1 + .../dts/marvell/armada-7020-comexpress.dts | 134 ++++++++++++++++++ @@ -26,17 +28,17 @@ Reviewed-by: Raz Adashi create mode 100644 arch/arm64/boot/dts/marvell/armada-7020-comexpress.dts diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile -index 058237681..49f274add 100644 +index ce751b502..062317759 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile -@@ -26,3 +26,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb - dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb - dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb - dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb +@@ -32,3 +32,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-base.dtb + dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-pro.dtb + dtb-$(CONFIG_ARCH_MVEBU) += cn9131-cf-solidwan.dtb + dtb-$(CONFIG_ARCH_MVEBU) += cn9132-clearfog.dtb +dtb-$(CONFIG_ARCH_MVEBU) += armada-7020-comexpress.dtb diff --git a/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dts b/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dts new file mode 100644 -index 000000000..4f2020427 +index 000000000..782ac4539 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dts @@ -0,0 +1,134 @@ @@ -47,7 +49,7 @@ index 000000000..4f2020427 + * Device Tree file for Marvell Armada 7020 COMEXPRESS board. + */ + -+#include "armada-7020.dtsi" ++#include "armada-7040.dtsi" + +/ { + model = "Marvell Armada-7020 COMEXPRESS board setup"; @@ -192,5 +194,5 @@ index 293403a1a..95199cd99 100644 marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18", -- -2.25.1 +2.34.1 diff --git a/patch/0010-dts-pensnado-Elba-flash-partitions.patch b/patches-sonic/0010-dts-pensnado-Elba-flash-partitions.patch similarity index 100% rename from patch/0010-dts-pensnado-Elba-flash-partitions.patch rename to patches-sonic/0010-dts-pensnado-Elba-flash-partitions.patch diff --git a/patch/0095-platform-mellanox-nvsw-sn2201-Add-support-for-new-sy.patch b/patches-sonic/0010-platform-mellanox-nvsw-sn2200-Fix-.items-in-nvsw_sn2.patch similarity index 65% rename from patch/0095-platform-mellanox-nvsw-sn2201-Add-support-for-new-sy.patch rename to patches-sonic/0010-platform-mellanox-nvsw-sn2200-Fix-.items-in-nvsw_sn2.patch index d553f76e6..eec14acfd 100644 --- a/patch/0095-platform-mellanox-nvsw-sn2201-Add-support-for-new-sy.patch +++ b/patches-sonic/0010-platform-mellanox-nvsw-sn2200-Fix-.items-in-nvsw_sn2.patch @@ -1,25 +1,35 @@ -From 13e4e0e5b566a116e2107a0a959d2b294b388b42 Mon Sep 17 00:00:00 2001 -From: Oleksandr Shamray -Date: Wed, 11 Dec 2024 17:49:45 +0200 -Subject: [PATCH 4/4] platform: mellanox: nvsw-sn2200: Add support for new - system flavour +From 0eb3b624267260f95f0d126fe3a031af591c3d70 Mon Sep 17 00:00:00 2001 +From: Nathan Chancellor +Date: Fri, 9 May 2025 11:58:01 +0100 +Subject: [PATCH 10/78] platform: mellanox: nvsw-sn2200: Fix .items in + nvsw_sn2201_busbar_hotplug +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit -Add support for SN2201 system flavour, which is fitting OCP rack -form-factor and feeded from external power source through the rack -standard busbar interface. +Clang warns (or errors with CONFIG_WERROR=y): -Validate system type through DMI decode. -For new system flavour: -- Skip internal power supply configuration. -- Attach power hotswap device. + drivers/platform/mellanox/nvsw-sn2201.c:531:32: error: variable 'nvsw_sn2201_busbar_items' is not needed and will not be emitted [-Werror,-Wunneeded-internal-declaration] + 531 | static struct mlxreg_core_item nvsw_sn2201_busbar_items[] = { + | ^~~~~~~~~~~~~~~~~~~~~~~~ -Signed-off-by: Vadim Pasternak +nvsw_sn2201_busbar_items is only used in ARRAY_SIZE(), which uses +sizeof(), so this variable is only used at compile time. It appears that +this may be a copy and paste issue, so use nvsw_sn2201_busbar_items as +the .items member in nvsw_sn2201_busbar_hotplug, clearing up the +warning. + +Fixes: 56b0bb7f9069 ("platform: mellanox: nvsw-sn2200: Add support for new system flavour") +Signed-off-by: Nathan Chancellor +Link: https://lore.kernel.org/r/20250509-nvsw-sn2200-fix-items-busbar-hotplug-v1-1-8844fff38dc8@kernel.org +Reviewed-by: Ilpo Järvinen +Signed-off-by: Ilpo Järvinen --- - drivers/platform/mellanox/nvsw-sn2201.c | 112 +++++++++++++++++++++++- - 1 file changed, 109 insertions(+), 3 deletions(-) + drivers/platform/mellanox/nvsw-sn2201.c | 114 ++++++++++++++++++++++++++++++-- + 1 file changed, 109 insertions(+), 5 deletions(-) diff --git a/drivers/platform/mellanox/nvsw-sn2201.c b/drivers/platform/mellanox/nvsw-sn2201.c -index a3e2bc6d6..64c705f3b 100644 +index e708521..beb3f82 100644 --- a/drivers/platform/mellanox/nvsw-sn2201.c +++ b/drivers/platform/mellanox/nvsw-sn2201.c @@ -6,6 +6,7 @@ @@ -44,7 +54,7 @@ index a3e2bc6d6..64c705f3b 100644 * @cpld_devs: I2C devices for cpld; * @cpld_devs_num: number of I2C devices for cpld; * @main_mux_deferred_nr: I2C adapter number must be exist prior creating devices execution; -+ * @ext_pwr_source: 1 if system powered by external power supply; 0 - by internal; ++ * @ext_pwr_source: true if system powered by external power supply; false - by internal; */ struct nvsw_sn2201 { struct device *dev; @@ -52,12 +62,12 @@ index a3e2bc6d6..64c705f3b 100644 struct mlxreg_hotplug_device *cpld_devs; int cpld_devs_num; int main_mux_deferred_nr; -+ u8 ext_pwr_source; ++ bool ext_pwr_source; }; static bool nvsw_sn2201_writeable_reg(struct device *dev, unsigned int reg) -@@ -523,6 +529,36 @@ struct mlxreg_core_hotplug_platform_data nvsw_sn2201_hotplug = { - .deferred_nr = NVSW_SN2201_2ND_MUX_CH3_NR, +@@ -522,6 +528,35 @@ struct mlxreg_core_hotplug_platform_data nvsw_sn2201_hotplug = { + .mask = NVSW_SN2201_CPLD_AGGR_MASK_DEF, }; +static struct mlxreg_core_item nvsw_sn2201_busbar_items[] = { @@ -87,13 +97,12 @@ index a3e2bc6d6..64c705f3b 100644 + .counter = ARRAY_SIZE(nvsw_sn2201_busbar_items), + .cell = NVSW_SN2201_SYS_INT_STATUS_OFFSET, + .mask = NVSW_SN2201_CPLD_AGGR_BUSBAR_MASK_DEF, -+ .deferred_nr = NVSW_SN2201_2ND_MUX_CH3_NR, +}; + /* SN2201 static devices. */ static struct i2c_board_info nvsw_sn2201_static_devices[] = { { -@@ -558,6 +594,9 @@ static struct i2c_board_info nvsw_sn2201_static_devices[] = { +@@ -557,6 +592,9 @@ static struct i2c_board_info nvsw_sn2201_static_devices[] = { { I2C_BOARD_INFO("pmbus", 0x40), }, @@ -103,7 +112,7 @@ index a3e2bc6d6..64c705f3b 100644 }; /* SN2201 default static board info. */ -@@ -608,6 +647,59 @@ static struct mlxreg_hotplug_device nvsw_sn2201_static_brdinfo[] = { +@@ -607,6 +645,58 @@ static struct mlxreg_hotplug_device nvsw_sn2201_static_brdinfo[] = { }, }; @@ -158,12 +167,11 @@ index a3e2bc6d6..64c705f3b 100644 + .nr = NVSW_SN2201_MAIN_MUX_CH1_NR, + }, +}; -+ + /* LED default data. */ static struct mlxreg_core_data nvsw_sn2201_led_data[] = { { -@@ -982,7 +1074,10 @@ static int nvsw_sn2201_config_init(struct nvsw_sn2201 *nvsw_sn2201, void *regmap +@@ -981,7 +1071,10 @@ static int nvsw_sn2201_config_init(struct nvsw_sn2201 *nvsw_sn2201, void *regmap nvsw_sn2201->io_data = &nvsw_sn2201_regs_io; nvsw_sn2201->led_data = &nvsw_sn2201_led; nvsw_sn2201->wd_data = &nvsw_sn2201_wd; @@ -175,7 +183,16 @@ index a3e2bc6d6..64c705f3b 100644 /* Register IO access driver. */ if (nvsw_sn2201->io_data) { -@@ -1199,12 +1294,18 @@ static int nvsw_sn2201_config_pre_init(struct nvsw_sn2201 *nvsw_sn2201) +@@ -1088,7 +1181,7 @@ static int nvsw_sn2201_i2c_completion_notify(void *handle, int id) + if (!nvsw_sn2201->main_mux_devs->adapter) { + err = -ENODEV; + dev_err(nvsw_sn2201->dev, "Failed to get adapter for bus %d\n", +- nvsw_sn2201->main_mux_devs->nr); ++ nvsw_sn2201->cpld_devs->nr); + goto i2c_get_adapter_main_fail; + } + +@@ -1198,12 +1291,18 @@ static int nvsw_sn2201_config_pre_init(struct nvsw_sn2201 *nvsw_sn2201) static int nvsw_sn2201_probe(struct platform_device *pdev) { struct nvsw_sn2201 *nvsw_sn2201; @@ -186,15 +203,15 @@ index a3e2bc6d6..64c705f3b 100644 if (!nvsw_sn2201) return -ENOMEM; -+ /* Validate system powering type. */ ++ /* Validate system powering type - only HI168 SKU supports external power. */ + sku = dmi_get_system_info(DMI_PRODUCT_SKU); -+ if (!strcmp(sku, "HI168")) -+ nvsw_sn2201->ext_pwr_source = 1; ++ if (sku && !strcmp(sku, "HI168")) ++ nvsw_sn2201->ext_pwr_source = true; + nvsw_sn2201->dev = &pdev->dev; platform_set_drvdata(pdev, nvsw_sn2201); ret = platform_device_add_resources(pdev, nvsw_sn2201_lpc_io_resources, -@@ -1215,8 +1316,13 @@ static int nvsw_sn2201_probe(struct platform_device *pdev) +@@ -1214,8 +1313,13 @@ static int nvsw_sn2201_probe(struct platform_device *pdev) nvsw_sn2201->main_mux_deferred_nr = NVSW_SN2201_MAIN_MUX_DEFER_NR; nvsw_sn2201->main_mux_devs = nvsw_sn2201_main_mux_brdinfo; nvsw_sn2201->cpld_devs = nvsw_sn2201_cpld_brdinfo; @@ -210,6 +227,15 @@ index a3e2bc6d6..64c705f3b 100644 return nvsw_sn2201_config_pre_init(nvsw_sn2201); } +@@ -1253,7 +1357,7 @@ MODULE_DEVICE_TABLE(acpi, nvsw_sn2201_acpi_ids); + + static struct platform_driver nvsw_sn2201_driver = { + .probe = nvsw_sn2201_probe, +- .remove_new = nvsw_sn2201_remove, ++ .remove = nvsw_sn2201_remove, + .driver = { + .name = "nvsw-sn2201", + .acpi_match_table = nvsw_sn2201_acpi_ids, -- -2.20.1 +2.8.4 diff --git a/patch/0011-arm64-dts-marvell-Add-Nokia-7215-IXS-A1-board.patch b/patches-sonic/0011-arm64-dts-marvell-Add-Nokia-7215-IXS-A1-board.patch similarity index 88% rename from patch/0011-arm64-dts-marvell-Add-Nokia-7215-IXS-A1-board.patch rename to patches-sonic/0011-arm64-dts-marvell-Add-Nokia-7215-IXS-A1-board.patch index b50e18f55..0c29f16ac 100644 --- a/patch/0011-arm64-dts-marvell-Add-Nokia-7215-IXS-A1-board.patch +++ b/patches-sonic/0011-arm64-dts-marvell-Add-Nokia-7215-IXS-A1-board.patch @@ -1,6 +1,6 @@ -From d1cbdb3b1894c81f0762f3d7242c7f97a429de75 Mon Sep 17 00:00:00 2001 +From d0144bfbcbf78c7577f5e1330aba16f1e5bb4ebe Mon Sep 17 00:00:00 2001 From: Natarajan Subbiramani -Date: Mon, 4 Mar 2024 14:22:19 -0500 +Date: Sun, 16 Nov 2025 12:55:20 +0200 Subject: [PATCH] arm64: dts: marvell: Add DTS for 7215-IXS-A1 board 7215-IXS-A1 is an aggregation switch based on Marvell AlleyCat5X. @@ -8,20 +8,21 @@ This dts is extracted from Marvell cn9130-crb and removed unused nodes along with platform specific changes. Signed-off-by: Natarajan Subbiramani +Signed-off-by: Yan Markman Tested-by: Natarajan Subbiramani Reviewed-by: Jon Goldberg --- - arch/arm64/boot/dts/marvell/7215-ixs-a1.dts | 225 ++++++++++++++++++++ + arch/arm64/boot/dts/marvell/7215-ixs-a1.dts | 221 ++++++++++++++++++++ arch/arm64/boot/dts/marvell/Makefile | 1 + 2 files changed, 226 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/7215-ixs-a1.dts diff --git a/arch/arm64/boot/dts/marvell/7215-ixs-a1.dts b/arch/arm64/boot/dts/marvell/7215-ixs-a1.dts new file mode 100644 -index 000000000000..e683b7ca4c9c +index 000000000..fd0e6b395 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/7215-ixs-a1.dts -@@ -0,0 +1,225 @@ +@@ -0,0 +1,221 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Nokia @@ -57,15 +58,11 @@ index 000000000000..e683b7ca4c9c + #size-cells = <0x02>; + ranges; + -+ /delete-node/ psci-area@4000000; -+ -+ buf1: buffer@4000000 { ++ /* keep psci-area: 04000000 size 0x00200000 */ ++ /* keep tee: 04400000 size 0x01000000 */ ++ buf1: buffer@6000000 { + compatible = "shared-dma-pool"; -+ reg = <0x0 0x04000000 0x0 0x02000000>; -+ no-map; -+ }; -+ psci-area@6000000 { -+ reg = <0x0 0x06000000 0x0 0x00200000>; ++ reg = <0x0 0x06000000 0x0 0x02000000>; + no-map; + }; + }; @@ -248,16 +245,14 @@ index 000000000000..e683b7ca4c9c + phy-mode = "sgmii"; +}; diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile -index 49f274add..310b57e47 100644 +index 062317759..c9d4e7836 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile -@@ -27,3 +27,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb - dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb - dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb +@@ -33,3 +33,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-pro.dtb + dtb-$(CONFIG_ARCH_MVEBU) += cn9131-cf-solidwan.dtb + dtb-$(CONFIG_ARCH_MVEBU) += cn9132-clearfog.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-7020-comexpress.dtb +dtb-$(CONFIG_ARCH_MVEBU) += 7215-ixs-a1.dtb - -base-commit: 6b6f1082cb46d72823b7ea99c058c601668ba1d3 -- 2.34.1 diff --git a/patch/0011-drivers-edac-Add-Elba-EDAC-support.patch b/patches-sonic/0011-drivers-edac-Add-Elba-EDAC-support.patch similarity index 100% rename from patch/0011-drivers-edac-Add-Elba-EDAC-support.patch rename to patches-sonic/0011-drivers-edac-Add-Elba-EDAC-support.patch diff --git a/patches-sonic/0011-platform-mellanox-Fix-spelling-and-comment-clarity-i.patch b/patches-sonic/0011-platform-mellanox-Fix-spelling-and-comment-clarity-i.patch new file mode 100644 index 000000000..1aef17843 --- /dev/null +++ b/patches-sonic/0011-platform-mellanox-Fix-spelling-and-comment-clarity-i.patch @@ -0,0 +1,86 @@ +From 941fba51fff1bfeb77ad69dba08209de16e375c4 Mon Sep 17 00:00:00 2001 +From: Alok Tiwari +Date: Sun, 22 Jun 2025 00:29:11 -0700 +Subject: [PATCH 11/78] platform/mellanox: Fix spelling and comment clarity in + Mellanox drivers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This commit corrects several minor typographical errors in comments +and error messages across multiple Mellanox platform driver. +Fixed spelling of "thresholds", "region", "platform", "default", +and removed redundant spaces in comment strings and error logs. + +These changes are cosmetic and do not affect runtime behavior. + +Signed-off-by: Alok Tiwari +Reviewed-by: Vadim Pasternak +Reviewed-by: David Thompson +Link: https://lore.kernel.org/r/20250622072921.4111552-1-alok.a.tiwari@oracle.com +Reviewed-by: Ilpo Järvinen +Signed-off-by: Ilpo Järvinen +--- + drivers/platform/mellanox/mlxbf-tmfifo.c | 2 +- + drivers/platform/mellanox/mlxreg-lc.c | 10 +++++----- + 2 files changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/platform/mellanox/mlxbf-tmfifo.c b/drivers/platform/mellanox/mlxbf-tmfifo.c +index d2c27cc..c05cd93 100644 +--- a/drivers/platform/mellanox/mlxbf-tmfifo.c ++++ b/drivers/platform/mellanox/mlxbf-tmfifo.c +@@ -1288,7 +1288,7 @@ static void mlxbf_tmfifo_get_cfg_mac(u8 *mac) + ether_addr_copy(mac, mlxbf_tmfifo_net_default_mac); + } + +-/* Set TmFifo thresolds which is used to trigger interrupts. */ ++/* Set TmFifo thresholds which is used to trigger interrupts. */ + static void mlxbf_tmfifo_set_threshold(struct mlxbf_tmfifo *fifo) + { + u64 ctl; +diff --git a/drivers/platform/mellanox/mlxreg-lc.c b/drivers/platform/mellanox/mlxreg-lc.c +index 9915267..08d37ef 100644 +--- a/drivers/platform/mellanox/mlxreg-lc.c ++++ b/drivers/platform/mellanox/mlxreg-lc.c +@@ -57,9 +57,9 @@ enum mlxreg_lc_state { + * @dev: platform device; + * @lock: line card lock; + * @par_regmap: parent device regmap handle; +- * @data: pltaform core data; ++ * @data: platform core data; + * @io_data: register access platform data; +- * @led_data: LED platform data ; ++ * @led_data: LED platform data; + * @mux_data: MUX platform data; + * @led: LED device; + * @io_regs: register access device; +@@ -171,7 +171,7 @@ static int mlxreg_lc_chan[] = { + 0x4e, 0x4f + }; + +-/* Defaul mux configuration. */ ++/* Default mux configuration. */ + static struct mlxcpld_mux_plat_data mlxreg_lc_mux_data[] = { + { + .chan_ids = mlxreg_lc_chan, +@@ -181,7 +181,7 @@ static struct mlxcpld_mux_plat_data mlxreg_lc_mux_data[] = { + }, + }; + +-/* Defaul mux board info. */ ++/* Default mux board info. */ + static struct i2c_board_info mlxreg_lc_mux_brdinfo = { + I2C_BOARD_INFO("i2c-mux-mlxcpld", 0x32), + }; +@@ -758,7 +758,7 @@ mlxreg_lc_config_init(struct mlxreg_lc *mlxreg_lc, void *regmap, + platform_device_register_resndata(dev, "mlxreg-io", data->hpdev.nr, NULL, 0, + mlxreg_lc->io_data, sizeof(*mlxreg_lc->io_data)); + if (IS_ERR(mlxreg_lc->io_regs)) { +- dev_err(dev, "Failed to create regio for client %s at bus %d at addr 0x%02x\n", ++ dev_err(dev, "Failed to create region for client %s at bus %d at addr 0x%02x\n", + data->hpdev.brdinfo->type, data->hpdev.nr, + data->hpdev.brdinfo->addr); + err = PTR_ERR(mlxreg_lc->io_regs); +-- +2.8.4 + diff --git a/patch/0012-drivers-soc-pensando-dev-capmem-driver.patch b/patches-sonic/0012-drivers-soc-pensando-dev-capmem-driver.patch similarity index 100% rename from patch/0012-drivers-soc-pensando-dev-capmem-driver.patch rename to patches-sonic/0012-drivers-soc-pensando-dev-capmem-driver.patch diff --git a/patch/0013-Interrupt-domain-controllers-for-Elba-ASIC.patch b/patches-sonic/0013-Interrupt-domain-controllers-for-Elba-ASIC.patch similarity index 100% rename from patch/0013-Interrupt-domain-controllers-for-Elba-ASIC.patch rename to patches-sonic/0013-Interrupt-domain-controllers-for-Elba-ASIC.patch diff --git a/patch/0014-drivers-uio-UIO-drivers-for-Elba.patch b/patches-sonic/0014-drivers-uio-UIO-drivers-for-Elba.patch similarity index 100% rename from patch/0014-drivers-uio-UIO-drivers-for-Elba.patch rename to patches-sonic/0014-drivers-uio-UIO-drivers-for-Elba.patch diff --git a/patch/0015-arm64-dts-marvell-Add-Supermicro-SSE-G3748-board.patch b/patches-sonic/0015-arm64-dts-marvell-Add-Supermicro-SSE-G3748-board.patch similarity index 94% rename from patch/0015-arm64-dts-marvell-Add-Supermicro-SSE-G3748-board.patch rename to patches-sonic/0015-arm64-dts-marvell-Add-Supermicro-SSE-G3748-board.patch index 9d0c7791f..19ee8dabc 100644 --- a/patch/0015-arm64-dts-marvell-Add-Supermicro-SSE-G3748-board.patch +++ b/patches-sonic/0015-arm64-dts-marvell-Add-Supermicro-SSE-G3748-board.patch @@ -1,4 +1,4 @@ -From d1a0b114b178ff3949afc23f69053618dfaf581a Mon Sep 17 00:00:00 2001 +From fc880f237cbfba658a147f797b363ab61f3577d0 Mon Sep 17 00:00:00 2001 From: Erich Yen Date: Tue, 21 May 2024 20:41:37 +0000 Subject: [PATCH] arm64: dts: marvell: Add Supermicro SSE-G3748 board @@ -13,11 +13,11 @@ SPI flash partitions and i2c1 configurations are modified to match with SSE-G374 create mode 100644 arch/arm64/boot/dts/marvell/smc_sse-g3748.dts diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile -index 310b57e47..88cef592e 100644 +index c9d4e7836..10adf28c9 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile -@@ -28,3 +28,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb - dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb +@@ -34,3 +34,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9131-cf-solidwan.dtb + dtb-$(CONFIG_ARCH_MVEBU) += cn9132-clearfog.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-7020-comexpress.dtb dtb-$(CONFIG_ARCH_MVEBU) += 7215-ixs-a1.dtb +dtb-$(CONFIG_ARCH_MVEBU) += smc_sse-g3748.dtb @@ -146,5 +146,5 @@ index 000000000..00fc581d7 + }; +}; -- -2.25.1 +2.34.1 diff --git a/patch/0015-drivers-pensando-soc-Boot-State-Machine-integrtion.patch b/patches-sonic/0015-drivers-pensando-soc-Boot-State-Machine-integrtion.patch similarity index 100% rename from patch/0015-drivers-pensando-soc-Boot-State-Machine-integrtion.patch rename to patches-sonic/0015-drivers-pensando-soc-Boot-State-Machine-integrtion.patch diff --git a/patch/0035-i2c-mlxcpld-Support-PCIe-mapped-register-space.patch b/patches-sonic/0015-i2c-mlxcpld-Support-PCIe-mapped-register-space.patch similarity index 96% rename from patch/0035-i2c-mlxcpld-Support-PCIe-mapped-register-space.patch rename to patches-sonic/0015-i2c-mlxcpld-Support-PCIe-mapped-register-space.patch index f173bbc60..c680fb78e 100644 --- a/patch/0035-i2c-mlxcpld-Support-PCIe-mapped-register-space.patch +++ b/patches-sonic/0015-i2c-mlxcpld-Support-PCIe-mapped-register-space.patch @@ -1,8 +1,7 @@ -From 94ecef5305797c5461b39715900b2d99048e6bb3 Mon Sep 17 00:00:00 2001 +From 53d028fcb527a4b8cf4c9d99b55799da872390fe Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Mon, 24 Jul 2023 12:39:33 +0000 -Subject: [PATCH backport 6.1.42 35/85] i2c: mlxcpld: Support PCIe mapped - register space +Subject: [PATCH 15/78] i2c: mlxcpld: Support PCIe mapped register space Currently driver uses constant base address of register space. On new systems this base address and access to it are different. @@ -21,11 +20,11 @@ two bytes of transaction size. Signed-off-by: Vadim Pasternak Reviewed-by: Michael Shych --- - drivers/i2c/busses/i2c-mlxcpld.c | 94 +++++++++++++++++++++++++++++--- + drivers/i2c/busses/i2c-mlxcpld.c | 94 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 86 insertions(+), 8 deletions(-) diff --git a/drivers/i2c/busses/i2c-mlxcpld.c b/drivers/i2c/busses/i2c-mlxcpld.c -index 14a63d5e1cdd..2ce2c324ea4f 100644 +index 8223f6d..ecae755 100644 --- a/drivers/i2c/busses/i2c-mlxcpld.c +++ b/drivers/i2c/busses/i2c-mlxcpld.c @@ -70,6 +70,7 @@ struct mlxcpld_i2c_curr_xfer { @@ -180,5 +179,5 @@ index 14a63d5e1cdd..2ce2c324ea4f 100644 if (err) goto mlxcpld_i2_probe_failed; -- -2.20.1 +2.8.4 diff --git a/patches-sonic/0016-arm64-dts-marvell-Add-DTS-for-Wistron-ES-1227-54TS-b.patch b/patches-sonic/0016-arm64-dts-marvell-Add-DTS-for-Wistron-ES-1227-54TS-b.patch new file mode 100644 index 000000000..b9621a2ad --- /dev/null +++ b/patches-sonic/0016-arm64-dts-marvell-Add-DTS-for-Wistron-ES-1227-54TS-b.patch @@ -0,0 +1,438 @@ +From 6ef6ef01c5ecc0da55683114b10b050ab5bced95 Mon Sep 17 00:00:00 2001 +From: Owen Wu +Date: Tue, 15 Oct 2024 15:24:11 +0800 +Subject: [PATCH] arm64: dts: marvell: Add DTS for Wistron ES-1227-54TS + board + +This change adds device tree file for Wistron ES-1227-54TS +and ES-2227-54TS boards. + +This dts is extracted from Marvell cn9130-crb and removed unused +nodes along with platform specific changes. + +Signed-off-by: Owen Wu +Signed-off-by: Yan Markman +--- + arch/arm64/boot/dts/marvell/Makefile | 1 + + arch/arm64/boot/dts/marvell/es1227-54ts.dts | 74 +++++ + arch/arm64/boot/dts/marvell/es1227-54ts.dtsi | 318 +++++++++++++++++++ + 3 files changed, 393 insertions(+) + create mode 100644 arch/arm64/boot/dts/marvell/es1227-54ts.dts + create mode 100644 arch/arm64/boot/dts/marvell/es1227-54ts.dtsi + +diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile +index 10adf28c9..02cbba99b 100644 +--- a/arch/arm64/boot/dts/marvell/Makefile ++++ b/arch/arm64/boot/dts/marvell/Makefile +@@ -35,3 +35,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-clearfog.dtb + dtb-$(CONFIG_ARCH_MVEBU) += armada-7020-comexpress.dtb + dtb-$(CONFIG_ARCH_MVEBU) += 7215-ixs-a1.dtb + dtb-$(CONFIG_ARCH_MVEBU) += smc_sse-g3748.dtb ++dtb-$(CONFIG_ARCH_MVEBU) += es1227-54ts.dtb +diff --git a/arch/arm64/boot/dts/marvell/es1227-54ts.dts b/arch/arm64/boot/dts/marvell/es1227-54ts.dts +new file mode 100644 +index 000000000..c77c7d4b6 +--- /dev/null ++++ b/arch/arm64/boot/dts/marvell/es1227-54ts.dts +@@ -0,0 +1,74 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) 2021 Marvell International Ltd. ++ * ++ * Device tree for the CN9130-CRB-A board. ++ */ ++ ++#include "es1227-54ts.dtsi" ++/ { ++ model = "Wistron ES1227 board"; ++}; ++ ++&cp0_pcie2 { ++ status = "okay"; ++ num-lanes = <1>; ++ num-viewport = <8>; ++ ++ /* Generic PHY, providing serdes lanes */ ++ phys = <&cp0_comphy5 2>; ++ iommu-map = <0x0 &smmu 0x480 0x20>, ++ <0x100 &smmu 0x4a0 0x20>, ++ <0x200 &smmu 0x4c0 0x20>; ++ iommu-map-mask = <0x031f>; ++}; ++ ++&cp0_mdio { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cp0_ge_mdio_pins>; ++ ++ phy0: ethernet-phy@0 { ++ reg = <0>; ++ marvell,reg-init = <0x2 0x1A 0x7FFF 0x8000>, ++ <0x2 0x0 0x7FFF 0x8000>, ++ <0x1 0x10 0xFDFF 0x200>; ++ }; ++}; ++ ++&cp0_xmdio { ++ status = "disabled"; ++}; ++ ++&cp0_uart0 { ++ pinctrl-names = "default"; ++ status = "okay"; ++ pinctrl-0 = <&cp0_uart0_pins>; ++}; ++ ++&cp0_usb3_0 { ++ status = "okay"; ++ usb-phy = <&cp0_usb3_0_phy0>; ++ phys = <&cp0_comphy1 0>; ++ phy-names = "usb3"; ++}; ++ ++&cp0_eth0 { ++ status = "disabled"; ++}; ++ ++/* CON56 */ ++&cp0_eth1 { ++ status = "okay"; ++ phys = <&cp0_comphy3 1>; ++ phy-handle = <&phy0>; ++ phy-mode = "sgmii"; ++}; ++ ++&cp0_eth2 { ++ status = "disabled"; ++}; ++ ++&cp0_rtc { ++ status = "disabled"; ++}; +diff --git a/arch/arm64/boot/dts/marvell/es1227-54ts.dtsi b/arch/arm64/boot/dts/marvell/es1227-54ts.dtsi +new file mode 100644 +index 000000000..142232bba +--- /dev/null ++++ b/arch/arm64/boot/dts/marvell/es1227-54ts.dtsi +@@ -0,0 +1,318 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) 2021 Marvell International Ltd. ++ * ++ * Device tree for the CN9130-CRB boards. ++ */ ++ ++#include "cn9130.dtsi" ++ ++#include ++ ++/ { ++ model = "Wistron ES1227"; ++ compatible = "marvell,cn9130", "marvell,armada-ap807-quad", ++ "marvell,armada-ap807"; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ aliases { ++ gpio1 = &cp0_gpio1; ++ gpio2 = &cp0_gpio2; ++ i2c0 = &cp0_i2c0; ++ i2c1 = &cp0_i2c1; ++ ethernet0 = &cp0_eth0; ++ ethernet1 = &cp0_eth1; ++ spi1 = &cp0_spi0; ++ spi2 = &cp0_spi1; ++ }; ++ ++ /*16G */ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x4 0x00000000>; ++ }; ++ ++ cp0_usb3_0_phy0: cp0_usb3_phy@0 { ++ compatible = "usb-nop-xceiv"; ++ }; ++ ++ cp0_usb3_0_phy1: cp0_usb3_phy@1 { ++ compatible = "usb-nop-xceiv"; ++ }; ++ ++ cp0_reg_sd_vccq: cp0_sd_vccq@0 { ++ compatible = "regulator-gpio"; ++ regulator-name = "cp0_sd_vccq"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ gpios = <&cp0_gpio2 18 GPIO_ACTIVE_HIGH>; ++ states = <1800000 0x1 ++ 3300000 0x0>; ++ }; ++ ++ cp0_reg_sd_vcc: cp0_sd_vcc@0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "cp0_sd_vcc"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&ap_sdhci0 { ++ pinctrl-names = "default"; ++ bus-width = <8>; ++ status = "okay"; ++}; ++ ++&cp0_crypto { ++ status = "okay"; ++}; ++ ++&cp0_ethernet { ++ status = "okay"; ++}; ++ ++&cp0_eth1 { ++ status = "okay"; ++ phy = <&phy0>; ++ phy-mode = "rgmii-id"; ++}; ++ ++&cp0_gpio1 { ++ status = "okay"; ++}; ++ ++&cp0_gpio2 { ++ status = "okay"; ++}; ++ ++&cp0_i2c0 { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cp0_i2c0_pins>; ++ clock-frequency = <100000>; ++ ++ i2c-switch1@77 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x77>; ++ i2c-mux-idle-disconnect; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ ++ tmp75@49 { ++ compatible = "ti,tmp75"; ++ reg = <0x49>; ++ }; ++ tmp75@4a { ++ compatible = "ti,tmp75"; ++ reg = <0x4a>; ++ }; ++ tmp75@4b { ++ compatible = "ti,tmp75"; ++ reg = <0x4b>; ++ }; ++ expander0: pca953x@20 { ++ compatible = "nxp,pca9555"; ++ pinctrl-names = "default"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ reg = <0x20>; ++ status = "okay"; ++ }; ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ }; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ }; ++ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ }; ++ ++ i2c@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ ++ rtc0:rtc-ds1388@68 { ++ compatible = "dallas,ds1388"; ++ /* PDF P13 : 1101 000 R/nW , 0x68+ R/nW */ ++ reg = <0x68>; ++ }; ++ }; ++ ++ i2c@5 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <5>; ++ }; ++ ++ i2c@6 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <6>; ++ }; ++ ++ i2c@7 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <7>; ++ }; ++ }; ++ ++ eeprom@55 { ++ compatible = "atmel,24c02"; ++ reg = <0x55>; ++ }; ++}; ++ ++&cp0_i2c1 { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cp0_i2c1_pins>; ++ clock-frequency = <100000>; ++}; ++ ++ ++/* U55 */ ++&cp0_spi1 { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cp0_spi0_pins>; ++ reg = <0x700680 0x50>; ++ ++ spi-flash@0 { ++ #address-cells = <0x1>; ++ #size-cells = <0x1>; ++ compatible = "jedec,spi-nor"; ++ reg = <0x0>; ++ spi-max-frequency = <50000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "U-Boot-0"; ++ reg = <0x0 0x200000>; ++ }; ++ ++ partition@3f0000 { ++ label = "uboot-env"; ++ reg = <0x3f0000 0x10000>; ++ env_size = <0x10000>; ++ }; ++ ++ partition@400000 { ++ label = "Filesystem-0"; ++ reg = <0x400000 0xc00000>; ++ }; ++ ++ partition@1000000 { ++ label = "onie"; ++ reg = <0x1000000 0x1000000>; ++ }; ++ }; ++ }; ++}; ++ ++&cp0_syscon0 { ++ cp0_pinctrl: pinctrl { ++ compatible = "marvell,cp115-standalone-pinctrl"; ++ ++ cp0_uart0_pins: cp0-uart0-pins-0 { ++ marvell,pins = "mpp0", "mpp1"; ++ marvell,function = "uart0"; ++ }; ++ ++ cp0_ge_mdio_pins: ge-mdio-pins { ++ marvell,pins = "mpp40", "mpp41"; ++ marvell,function = "ge"; ++ }; ++ ++ cp0_i2c0_pins: cp0-i2c-pins-0 { ++ marvell,pins = "mpp37", "mpp38"; ++ marvell,function = "i2c0"; ++ }; ++ ++ cp0_i2c1_pins: cp0-i2c-pins-1 { ++ marvell,pins = "mpp35", "mpp36"; ++ marvell,function = "i2c1"; ++ }; ++ ++ cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 { ++ marvell,pins = "mpp0", "mpp1", "mpp2", ++ "mpp3", "mpp4", "mpp5", ++ "mpp6", "mpp7", "mpp8", ++ "mpp9", "mpp10", "mpp11"; ++ marvell,function = "ge0"; ++ }; ++ ++ cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 { ++ marvell,pins = "mpp44", "mpp45", "mpp46", ++ "mpp47", "mpp48", "mpp49", ++ "mpp50", "mpp51", "mpp52", ++ "mpp53", "mpp54", "mpp55"; ++ marvell,function = "ge1"; ++ }; ++ ++ cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 { ++ marvell,pins = "mpp43"; ++ marvell,function = "gpio"; ++ }; ++ ++ cp0_sdhci_pins: cp0-sdhi-pins-0 { ++ marvell,pins = "mpp56", "mpp57", "mpp58", ++ "mpp59", "mpp60", "mpp61"; ++ marvell,function = "sdio"; ++ }; ++ ++ cp0_spi0_pins: cp0-spi-pins-0 { ++ marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; ++ marvell,function = "spi1"; ++ }; ++ ++ cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb { ++ marvell,pins = "mpp55"; ++ marvell,function = "gpio"; ++ }; ++ }; ++}; ++ ++&cp0_usb3_0 { ++ status = "okay"; ++ usb-phy = <&cp0_usb3_0_phy0>; ++ phy-names = "usb"; ++}; ++ ++&cp0_usb3_1 { ++ status = "okay"; ++ usb-phy = <&cp0_usb3_0_phy1>; ++ phy-names = "usb"; ++}; +-- +2.34.1 + diff --git a/patch/0016-arm64-dts-marvell-Add-Wistron-ES-1227-54TS-board.patch b/patches-sonic/0016-arm64-dts-marvell-Add-Wistron-ES-1227-54TS-board.patch similarity index 100% rename from patch/0016-arm64-dts-marvell-Add-Wistron-ES-1227-54TS-board.patch rename to patches-sonic/0016-arm64-dts-marvell-Add-Wistron-ES-1227-54TS-board.patch diff --git a/patch/0016-drivers-soc-pensando-crash-dump-driver.patch b/patches-sonic/0016-drivers-soc-pensando-crash-dump-driver.patch similarity index 100% rename from patch/0016-drivers-soc-pensando-crash-dump-driver.patch rename to patches-sonic/0016-drivers-soc-pensando-crash-dump-driver.patch diff --git a/patch/0042-hwmon-mlxreg-fan-Add-support-for-new-flavour-of-capa.patch b/patches-sonic/0016-hwmon-mlxreg-fan-Add-support-for-new-flavour-of-capa.patch similarity index 89% rename from patch/0042-hwmon-mlxreg-fan-Add-support-for-new-flavour-of-capa.patch rename to patches-sonic/0016-hwmon-mlxreg-fan-Add-support-for-new-flavour-of-capa.patch index cced17761..031009197 100644 --- a/patch/0042-hwmon-mlxreg-fan-Add-support-for-new-flavour-of-capa.patch +++ b/patches-sonic/0016-hwmon-mlxreg-fan-Add-support-for-new-flavour-of-capa.patch @@ -1,7 +1,7 @@ -From c729c7228762db53a6219d3ef126226b50b54dfc Mon Sep 17 00:00:00 2001 +From dc8d6f8639f241ebce6589d6c9507e9a0bfca096 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Sun, 23 Jul 2023 06:26:09 +0000 -Subject: [PATCH v6.1 23/80] hwmon: (mlxreg-fan) Add support for new flavour of +Subject: [PATCH 16/78] hwmon: (mlxreg-fan) Add support for new flavour of capability register FAN platform data is common across the various systems, while fan @@ -31,7 +31,7 @@ Signed-off-by: Vadim Pasternak 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/hwmon/mlxreg-fan.c b/drivers/hwmon/mlxreg-fan.c -index 96017cc8da7e..342ff355e925 100644 +index a5f89aa..e54a438 100644 --- a/drivers/hwmon/mlxreg-fan.c +++ b/drivers/hwmon/mlxreg-fan.c @@ -63,12 +63,14 @@ struct mlxreg_fan; @@ -61,7 +61,7 @@ index 96017cc8da7e..342ff355e925 100644 /* FAN is not connected - return zero for FAN speed. */ *val = 0; return 0; -@@ -390,7 +394,7 @@ static int mlxreg_fan_connect_verify(struct mlxreg_fan *fan, +@@ -400,7 +404,7 @@ static int mlxreg_fan_connect_verify(struct mlxreg_fan *fan, return err; } @@ -70,7 +70,7 @@ index 96017cc8da7e..342ff355e925 100644 } static int mlxreg_pwm_connect_verify(struct mlxreg_fan *fan, -@@ -527,7 +531,15 @@ static int mlxreg_fan_config(struct mlxreg_fan *fan, +@@ -537,7 +541,15 @@ static int mlxreg_fan_config(struct mlxreg_fan *fan, return err; } @@ -88,5 +88,5 @@ index 96017cc8da7e..342ff355e925 100644 dev_err(fan->dev, "Configuration is invalid: drawers num %d tachos num %d\n", drwr_avail, tacho_avail); -- -2.20.1 +2.8.4 diff --git a/patches-sonic/0017-Extend-driver-to-support-XMC-XM25QH256C-device.patch b/patches-sonic/0017-Extend-driver-to-support-XMC-XM25QH256C-device.patch new file mode 100644 index 000000000..59abd5c46 --- /dev/null +++ b/patches-sonic/0017-Extend-driver-to-support-XMC-XM25QH256C-device.patch @@ -0,0 +1,33 @@ +From b7c35b19dd2e5548534b21404397d53c7d772cfa Mon Sep 17 00:00:00 2001 +From: Owen Wu +Date: Tue, 15 Oct 2024 14:02:06 +0800 +Subject: [PATCH] Extend driver to support XMC XM25QH256C device. + +Add new component for alternative support + +Signed-off-by: Owen Wu +Signed-off-by: Yan Markman +--- + drivers/mtd/spi-nor/xmc.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/mtd/spi-nor/xmc.c b/drivers/mtd/spi-nor/xmc.c +index d5a06054b..941016cad 100644 +--- a/drivers/mtd/spi-nor/xmc.c ++++ b/drivers/mtd/spi-nor/xmc.c +@@ -19,6 +19,12 @@ static const struct flash_info xmc_nor_parts[] = { + .name = "XM25QH128A", + .size = SZ_16M, + .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, ++ }, { ++ .id = SNOR_ID(0x20, 0x40, 0x19), ++ .name = "XM25QH256C", ++ .size = SZ_32M, ++ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, ++ .fixup_flags = SPI_NOR_4B_OPCODES, + }, + }; + +-- +2.34.1 + diff --git a/patch/0017-drivers-soc-pensando-Add-the-Reset-Cause-driver.patch b/patches-sonic/0017-drivers-soc-pensando-Add-the-Reset-Cause-driver.patch similarity index 100% rename from patch/0017-drivers-soc-pensando-Add-the-Reset-Cause-driver.patch rename to patches-sonic/0017-drivers-soc-pensando-Add-the-Reset-Cause-driver.patch diff --git a/patch/0044-leds-mlxreg-Add-support-for-new-flavour-of-capabilit.patch b/patches-sonic/0017-leds-mlxreg-Add-support-for-new-flavour-of-capabilit.patch similarity index 87% rename from patch/0044-leds-mlxreg-Add-support-for-new-flavour-of-capabilit.patch rename to patches-sonic/0017-leds-mlxreg-Add-support-for-new-flavour-of-capabilit.patch index bb7a89978..d61644802 100644 --- a/patch/0044-leds-mlxreg-Add-support-for-new-flavour-of-capabilit.patch +++ b/patches-sonic/0017-leds-mlxreg-Add-support-for-new-flavour-of-capabilit.patch @@ -1,8 +1,8 @@ -From 242233be3adcd06398d728b2e793d9e40e6fbc3d Mon Sep 17 00:00:00 2001 +From 5dc4e5b4c1244e5d974dc87b2b8caf898d7d721c Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Thu, 20 Jul 2023 11:01:56 +0000 -Subject: [PATCH v6.1 25/81] leds: mlxreg: Add support for new flavour of - capability register +Subject: [PATCH 17/78] leds: mlxreg: Add support for new flavour of capability + register LED platform data is common across the various systems, while LED driver should be able to apply only the LED instances relevant @@ -28,10 +28,10 @@ Signed-off-by: Vadim Pasternak 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/leds/leds-mlxreg.c b/drivers/leds/leds-mlxreg.c -index b7855c93bd72..161195de78ba 100644 +index 1b70de7..5b73cc4 100644 --- a/drivers/leds/leds-mlxreg.c +++ b/drivers/leds/leds-mlxreg.c -@@ -206,16 +206,22 @@ static int mlxreg_led_config(struct mlxreg_led_priv_data *priv) +@@ -204,16 +204,22 @@ static int mlxreg_led_config(struct mlxreg_led_priv_data *priv) dev_err(&priv->pdev->dev, "Failed to query capability register\n"); return err; } @@ -58,5 +58,5 @@ index b7855c93bd72..161195de78ba 100644 led_data->data_parent = priv; if (strstr(data->label, "red") || -- -2.20.1 +2.8.4 diff --git a/patches-sonic/0018-drivers-i2c-fix-after-kdump-crash.patch b/patches-sonic/0018-drivers-i2c-fix-after-kdump-crash.patch new file mode 100644 index 000000000..07c84ab02 --- /dev/null +++ b/patches-sonic/0018-drivers-i2c-fix-after-kdump-crash.patch @@ -0,0 +1,46 @@ +From da0d305f60d9686048033d0765c20c763ad5a986 Mon Sep 17 00:00:00 2001 +From: Elad Nachman +Date: Sun, 18 May 2025 14:02:58 +0000 +Subject: [PATCH 1/2] drivers: i2c: fix after kdump crash + +Spurious interrupts left while i2c controller still +at RX or TX state would try to access the RX or TX +buffer pointer, which is NULL. +Add check to verify buffer pointer is not NULL before +reading or writing the buffer for additional TX or RX +operations. + +Signed-off-by: Elad Nachman +--- + drivers/i2c/busses/i2c-mv64xxx.c | 10 +++++++--- + 1 file changed, 7 insertions(+), 3 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c +index 13e9bdeb4..36fdd9b19 100644 +--- a/drivers/i2c/busses/i2c-mv64xxx.c ++++ b/drivers/i2c/busses/i2c-mv64xxx.c +@@ -413,14 +413,18 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data) + break; + + case MV64XXX_I2C_ACTION_SEND_DATA: +- writel(drv_data->msg->buf[drv_data->byte_posn++], +- drv_data->reg_base + drv_data->reg_offsets.data); ++ if (drv_data->msg && drv_data->msg->buf) ++ writel(drv_data->msg->buf[drv_data->byte_posn++], ++ drv_data->reg_base + drv_data->reg_offsets.data); + writel(drv_data->cntl_bits, + drv_data->reg_base + drv_data->reg_offsets.control); + break; + + case MV64XXX_I2C_ACTION_RCV_DATA: +- drv_data->msg->buf[drv_data->byte_posn++] = ++ if (drv_data->msg && drv_data->msg->buf) ++ drv_data->msg->buf[drv_data->byte_posn++] = ++ readl(drv_data->reg_base + drv_data->reg_offsets.data); ++ else + readl(drv_data->reg_base + drv_data->reg_offsets.data); + writel(drv_data->cntl_bits, + drv_data->reg_base + drv_data->reg_offsets.control); +-- +2.34.1 + diff --git a/patch/0018-i2c-mv64xxx-kdump-sonic.patch b/patches-sonic/0018-i2c-mv64xxx-kdump-sonic.patch similarity index 100% rename from patch/0018-i2c-mv64xxx-kdump-sonic.patch rename to patches-sonic/0018-i2c-mv64xxx-kdump-sonic.patch diff --git a/patch/0045-leds-mlxreg-Remove-code-for-amber-LED-colour.patch b/patches-sonic/0018-leds-mlxreg-Remove-code-for-amber-LED-colour.patch similarity index 84% rename from patch/0045-leds-mlxreg-Remove-code-for-amber-LED-colour.patch rename to patches-sonic/0018-leds-mlxreg-Remove-code-for-amber-LED-colour.patch index b418d5dfa..d7e616952 100644 --- a/patch/0045-leds-mlxreg-Remove-code-for-amber-LED-colour.patch +++ b/patches-sonic/0018-leds-mlxreg-Remove-code-for-amber-LED-colour.patch @@ -1,7 +1,7 @@ -From 9fc276007cac2ab2efc9f55f66c11816f4e2da6b Mon Sep 17 00:00:00 2001 +From 5feddc9d395ceb20792619e506d93bdbcc9b5cbf Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Thu, 20 Jul 2023 11:17:31 +0000 -Subject: [PATCH v6.1 26/81] leds: mlxreg: Remove code for amber LED colour +Subject: [PATCH 18/78] leds: mlxreg: Remove code for amber LED colour Remove unused code for amber LED colour. @@ -14,10 +14,10 @@ Signed-off-by: Vadim Pasternak 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/leds/leds-mlxreg.c b/drivers/leds/leds-mlxreg.c -index 161195de78ba..23de154ade61 100644 +index 5b73cc4..a7057b0 100644 --- a/drivers/leds/leds-mlxreg.c +++ b/drivers/leds/leds-mlxreg.c -@@ -19,7 +19,6 @@ +@@ -18,7 +18,6 @@ #define MLXREG_LED_IS_OFF 0x00 /* Off */ #define MLXREG_LED_RED_SOLID 0x05 /* Solid red */ #define MLXREG_LED_GREEN_SOLID 0x0D /* Solid green */ @@ -25,7 +25,7 @@ index 161195de78ba..23de154ade61 100644 #define MLXREG_LED_BLINK_3HZ 167 /* ~167 msec off/on - HW support */ #define MLXREG_LED_BLINK_6HZ 83 /* ~83 msec off/on - HW support */ #define MLXREG_LED_CAPABILITY_CLEAR GENMASK(31, 8) /* Clear mask */ -@@ -224,13 +223,10 @@ static int mlxreg_led_config(struct mlxreg_led_priv_data *priv) +@@ -222,13 +221,10 @@ static int mlxreg_led_config(struct mlxreg_led_priv_data *priv) } led_cdev = &led_data->led_cdev; led_data->data_parent = priv; @@ -42,5 +42,5 @@ index 161195de78ba..23de154ade61 100644 brightness = LED_OFF; led_data->base_color = MLXREG_LED_GREEN_SOLID; -- -2.20.1 +2.8.4 diff --git a/patch/0018-soc-pensando-pcie-driver.patch b/patches-sonic/0018-soc-pensando-pcie-driver.patch similarity index 100% rename from patch/0018-soc-pensando-pcie-driver.patch rename to patches-sonic/0018-soc-pensando-pcie-driver.patch diff --git a/patch/0046-Extend-driver-to-support-Infineon-Digital-Multi-phas.patch b/patches-sonic/0019-Extend-driver-to-support-Infineon-Digital-Multi-phas.patch similarity index 77% rename from patch/0046-Extend-driver-to-support-Infineon-Digital-Multi-phas.patch rename to patches-sonic/0019-Extend-driver-to-support-Infineon-Digital-Multi-phas.patch index 7d242bac5..0e83590f0 100644 --- a/patch/0046-Extend-driver-to-support-Infineon-Digital-Multi-phas.patch +++ b/patches-sonic/0019-Extend-driver-to-support-Infineon-Digital-Multi-phas.patch @@ -1,8 +1,8 @@ -From 276c9eae3cf83bb65c575b423c785d0ff37b6da0 Mon Sep 17 00:00:00 2001 +From 92de6069e75d9981c2f9ab0f7cbd2970236d51e3 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Mon, 17 Jul 2023 15:40:08 +0000 -Subject: [PATCH backport 6.1.42 46/85] Extend driver to support Infineon - Digital Multi-phase XDPE1A2G7 device. +Subject: [PATCH 19/78] Extend driver to support Infineon Digital Multi-phase + XDPE1A2G7 device. From telemetry perspective device is almost the same as XDPE15284, but does not support READ_EIN (86h) and READ_EOUT (87h) commands. @@ -13,16 +13,16 @@ Signed-off-by: Vadim Pasternak 1 file changed, 2 insertions(+) diff --git a/drivers/hwmon/pmbus/xdpe152c4.c b/drivers/hwmon/pmbus/xdpe152c4.c -index b8a36ef73e45..1ef1141ba537 100644 +index 7f3b31d..089f268 100644 --- a/drivers/hwmon/pmbus/xdpe152c4.c +++ b/drivers/hwmon/pmbus/xdpe152c4.c @@ -44,6 +44,7 @@ static int xdpe152_probe(struct i2c_client *client) } static const struct i2c_device_id xdpe152_id[] = { -+ {"xdpe1a2g7", 0}, - {"xdpe152c4", 0}, - {"xdpe15284", 0}, ++ {"xdpe1a2g7"}, + {"xdpe152c4"}, + {"xdpe15284"}, {} @@ -52,6 +53,7 @@ static const struct i2c_device_id xdpe152_id[] = { MODULE_DEVICE_TABLE(i2c, xdpe152_id); @@ -33,5 +33,5 @@ index b8a36ef73e45..1ef1141ba537 100644 {.compatible = "infineon,xdpe15284"}, {} -- -2.20.1 +2.8.4 diff --git a/patch/0019-drivers-soc-pensando-kpcimgr-driver.patch b/patches-sonic/0019-drivers-soc-pensando-kpcimgr-driver.patch similarity index 100% rename from patch/0019-drivers-soc-pensando-kpcimgr-driver.patch rename to patches-sonic/0019-drivers-soc-pensando-kpcimgr-driver.patch diff --git a/patches-sonic/0019-irqchip-mvebu-gicp-Clear-pending-interrupts-on-init.patch b/patches-sonic/0019-irqchip-mvebu-gicp-Clear-pending-interrupts-on-init.patch new file mode 100644 index 000000000..7da1254d2 --- /dev/null +++ b/patches-sonic/0019-irqchip-mvebu-gicp-Clear-pending-interrupts-on-init.patch @@ -0,0 +1,51 @@ +From e7ca85e98fd395437c2633d8ccbf93ee20db93ca Mon Sep 17 00:00:00 2001 +From: Elad Nachman +Date: Sun, 3 Aug 2025 13:25:48 +0300 +Subject: [PATCH 2/2] irqchip/mvebu-gicp: Clear pending interrupts on init + +When a kexec'ed kernel boots up, there might be stale unhandled interrupts +pending in the interrupt controller. These are delivered as spurious +interrupts once the boot CPU enables interrupts. + +Clear all pending interrupts when the driver is initialized to prevent +these spurious interrupts from locking the CPU in an endless loop. + +Signed-off-by: Elad Nachman +Signed-off-by: Thomas Gleixner +Link: https://lore.kernel.org/all/20250803102548.669682-2-enachman@marvell.com +Signed-off-by: Yan Markman +--- + drivers/irqchip/irq-mvebu-gicp.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/irqchip/irq-mvebu-gicp.c b/drivers/irqchip/irq-mvebu-gicp.c +index 2b6183919..a582b6a2f 100644 +--- a/drivers/irqchip/irq-mvebu-gicp.c ++++ b/drivers/irqchip/irq-mvebu-gicp.c +@@ -173,6 +173,7 @@ static int mvebu_gicp_probe(struct platform_device *pdev) + struct device_node *node = pdev->dev.of_node; + struct device_node *irq_parent_dn; + struct mvebu_gicp *gicp; ++ void __iomem *base; + int ret, i; + + gicp = devm_kzalloc(&pdev->dev, sizeof(*gicp), GFP_KERNEL); +@@ -229,6 +230,15 @@ static int mvebu_gicp_probe(struct platform_device *pdev) + return -ENODEV; + } + ++ base = ioremap(gicp->res->start, gicp->res->end - gicp->res->start); ++ if (IS_ERR(base)) { ++ dev_err(&pdev->dev, "ioremap() failed. Unable to clear pending interrupts.\n"); ++ } else { ++ for (i = 0; i < 64; i++) ++ writel(i, base + GICP_CLRSPI_NSR_OFFSET); ++ iounmap(base); ++ } ++ + inner_domain = irq_domain_create_hierarchy(parent_domain, 0, + gicp->spi_cnt, + of_node_to_fwnode(node), +-- +2.34.1 + diff --git a/patch/0019-mrvl-gicp-clr-irqs-on-probe.patch b/patches-sonic/0019-mrvl-gicp-clr-irqs-on-probe.patch similarity index 85% rename from patch/0019-mrvl-gicp-clr-irqs-on-probe.patch rename to patches-sonic/0019-mrvl-gicp-clr-irqs-on-probe.patch index fef1e7624..fe8467b6f 100644 --- a/patch/0019-mrvl-gicp-clr-irqs-on-probe.patch +++ b/patches-sonic/0019-mrvl-gicp-clr-irqs-on-probe.patch @@ -19,17 +19,18 @@ index d3232d6d8dce..4b2cad09bc71 100644 --- a/drivers/irqchip/irq-mvebu-gicp.c +++ b/drivers/irqchip/irq-mvebu-gicp.c @@ -172,6 +172,7 @@ - struct device_node *node = pdev->dev.of_node; struct device_node *irq_parent_dn; + struct mvebu_gicp *gicp; int ret, i; + void __iomem *base; gicp = devm_kzalloc(&pdev->dev, sizeof(*gicp), GFP_KERNEL); if (!gicp) -@@ -245,6 +246,15 @@ - - platform_set_drvdata(pdev, gicp); - +@@ -245,6 +246,16 @@ + irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_GENERIC_MSI); + inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT; + inner_domain->msi_parent_ops = &gicp_msi_parent_ops; ++ + base = ioremap(gicp->res->start, resource_size(gicp->res)); + if (!base) { + dev_err(&pdev->dev, "ioremap() failed. Unable to clear pending interrupts.\n"); diff --git a/patch/0047-dt-bindings-trivial-devices-Add-infineon-xdpe1a2g7.patch b/patches-sonic/0020-dt-bindings-trivial-devices-Add-infineon-xdpe1a2g7.patch similarity index 74% rename from patch/0047-dt-bindings-trivial-devices-Add-infineon-xdpe1a2g7.patch rename to patches-sonic/0020-dt-bindings-trivial-devices-Add-infineon-xdpe1a2g7.patch index cafc9b58d..73a7e6ab2 100644 --- a/patch/0047-dt-bindings-trivial-devices-Add-infineon-xdpe1a2g7.patch +++ b/patches-sonic/0020-dt-bindings-trivial-devices-Add-infineon-xdpe1a2g7.patch @@ -1,8 +1,7 @@ -From 62520e9d0ab641b36fb770477792073e6aad4d54 Mon Sep 17 00:00:00 2001 +From a2f7a59cc93759e1e7cde05831afa049e7413c43 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Mon, 17 Jul 2023 16:24:58 +0000 -Subject: [PATCH backport 6.1.42 47/85] dt-bindings: trivial-devices: Add - infineon,xdpe1a2g7 +Subject: [PATCH 20/78] dt-bindings: trivial-devices: Add infineon,xdpe1a2g7 Add new Infineon Multi-phase Digital VR Controller xdpe1a2g7 @@ -12,18 +11,18 @@ Signed-off-by: Vadim Pasternak 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml -index 61746755c107..7637390dfe09 100644 +index 9bf0fb1..a190c56 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml -@@ -145,6 +145,8 @@ properties: - - infineon,tlv493d-a1b6 +@@ -131,6 +131,8 @@ properties: + - infineon,xdp710 # Infineon Multi-phase Digital VR Controller xdpe11280 - infineon,xdpe11280 + # Infineon Multi-phase Digital VR Controller xdpe1a2g7 -+ - infineon,xdpe1a2g7 ++ - infineon,xdpe1a2g7 # Infineon Multi-phase Digital VR Controller xdpe12254 - infineon,xdpe12254 # Infineon Multi-phase Digital VR Controller xdpe12284 -- -2.20.1 +2.8.4 diff --git a/patch/0020-dts-pensando-add-mnet-and-mcrypt-devices.patch b/patches-sonic/0020-dts-pensando-add-mnet-and-mcrypt-devices.patch similarity index 100% rename from patch/0020-dts-pensando-add-mnet-and-mcrypt-devices.patch rename to patches-sonic/0020-dts-pensando-add-mnet-and-mcrypt-devices.patch diff --git a/patch/0021-drivers-soc-pensando-sbus-driver.patch b/patches-sonic/0021-drivers-soc-pensando-sbus-driver.patch similarity index 100% rename from patch/0021-drivers-soc-pensando-sbus-driver.patch rename to patches-sonic/0021-drivers-soc-pensando-sbus-driver.patch diff --git a/patch/0050-leds-mlxreg-Skip-setting-LED-color-during-initializa.patch b/patches-sonic/0021-leds-mlxreg-Skip-setting-LED-color-during-initializa.patch similarity index 82% rename from patch/0050-leds-mlxreg-Skip-setting-LED-color-during-initializa.patch rename to patches-sonic/0021-leds-mlxreg-Skip-setting-LED-color-during-initializa.patch index aa3ac65e4..57c60ba4b 100644 --- a/patch/0050-leds-mlxreg-Skip-setting-LED-color-during-initializa.patch +++ b/patches-sonic/0021-leds-mlxreg-Skip-setting-LED-color-during-initializa.patch @@ -1,7 +1,7 @@ -From 7d6423a976efbdc18b6df9b38169837a68ef46aa Mon Sep 17 00:00:00 2001 +From cbf289ab3a923985e9939ee35814644a3def9f1c Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Wed, 7 Jul 2021 10:18:14 +0000 -Subject: [PATCH v6.1 31/81] leds: mlxreg: Skip setting LED color during +Subject: [PATCH 21/78] leds: mlxreg: Skip setting LED color during initialization Hardware controls LED through CPLD device and LED control ownership @@ -21,10 +21,10 @@ Reviewed-by: Michael Shych 1 file changed, 3 deletions(-) diff --git a/drivers/leds/leds-mlxreg.c b/drivers/leds/leds-mlxreg.c -index 23de154ade61..6ddbfceaceec 100644 +index a7057b0..26add3e 100644 --- a/drivers/leds/leds-mlxreg.c +++ b/drivers/leds/leds-mlxreg.c -@@ -246,9 +246,6 @@ static int mlxreg_led_config(struct mlxreg_led_priv_data *priv) +@@ -244,9 +244,6 @@ static int mlxreg_led_config(struct mlxreg_led_priv_data *priv) if (err) return err; @@ -35,5 +35,5 @@ index 23de154ade61..6ddbfceaceec 100644 data->label, data->mask, data->reg); } -- -2.20.1 +2.8.4 diff --git a/patches-sonic/0022-arm64-dts-marvell-Add-DTS-for-cn9131-db-comexpress-trixie.patch b/patches-sonic/0022-arm64-dts-marvell-Add-DTS-for-cn9131-db-comexpress-trixie.patch new file mode 100644 index 000000000..2e046b7ca --- /dev/null +++ b/patches-sonic/0022-arm64-dts-marvell-Add-DTS-for-cn9131-db-comexpress-trixie.patch @@ -0,0 +1,570 @@ +From 75b9a7225192327f5d0fd3962227b4e1b68e095c Mon Sep 17 00:00:00 2001 +From: Yan Markman +Date: Mon, 3 Nov 2025 14:46:29 +0200 +Subject: [PATCH 1/1] arm64: dts: marvell: Add DTS for cn9131-db-comexpress + trixie + +Signed-off-by: Yan Markman +--- + arch/arm64/boot/dts/marvell/Makefile | 1 + + .../boot/dts/marvell/cn9130-db-comexpress.dts | 316 ++++++++++++++++++ + .../boot/dts/marvell/cn9131-db-comexpress.dts | 212 ++++++++++++ + 3 files changed, 529 insertions(+) + create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dts + create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dts + +diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile +index 02cbba99b..78fe5e532 100644 +--- a/arch/arm64/boot/dts/marvell/Makefile ++++ b/arch/arm64/boot/dts/marvell/Makefile +@@ -33,6 +33,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-pro.dtb + dtb-$(CONFIG_ARCH_MVEBU) += cn9131-cf-solidwan.dtb + dtb-$(CONFIG_ARCH_MVEBU) += cn9132-clearfog.dtb + dtb-$(CONFIG_ARCH_MVEBU) += armada-7020-comexpress.dtb ++dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-comexpress.dtb + dtb-$(CONFIG_ARCH_MVEBU) += 7215-ixs-a1.dtb + dtb-$(CONFIG_ARCH_MVEBU) += smc_sse-g3748.dtb + dtb-$(CONFIG_ARCH_MVEBU) += es1227-54ts.dtb +diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dts b/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dts +new file mode 100644 +index 000000000..d738a214d +--- /dev/null ++++ b/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dts +@@ -0,0 +1,316 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2025 Marvell International Ltd. ++ */ ++ ++/* This DB board is an extension for "ac5x-rd-carrier-cn9131" */ ++ ++#include "cn9130.dtsi" ++ ++#include ++ ++/ { ++ model = "Marvell Armada CN9130-DB-Comexpress type 7 CPU module (TRIXIE)"; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ aliases { ++ gpio1 = &cp0_gpio1; ++ gpio2 = &cp0_gpio2; ++ i2c0 = &cp0_i2c0; ++ i2c1 = &cp0_i2c1; ++ ethernet0 = &cp0_eth0; ++ ethernet1 = &cp0_eth1; ++ ethernet2 = &cp0_eth2; ++ spi1 = &cp0_spi0; ++ spi2 = &cp0_spi1; ++ }; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x0 0x2 0x00000000>; ++ }; ++ ++ ap0_reg_sd_vccq: regulator-1 { /*OLD: ap0_sd_vccq@0 */ ++ /* Don't set ++ * gpios = <&expander0 8 GPIO_ACTIVE_HIGH>; ++ * expander0: pca9555@21 { compatible = "nxp,pca9555"; ++ */ ++ compatible = "regulator-fixed"; /* regulator-gpio not on board */ ++ regulator-name = "ap0_sd_vccq"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ states = <1800000 0x1 1800000 0x0>; ++ gpios-states = <0>; ++ }; ++ ++ cp0_reg_usb3_vbus0: regulator-2 { /*OLD: cp0_usb3_vbus@0 */ ++ compatible = "regulator-fixed"; ++ regulator-name = "cp0-xhci0-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ gpios-states = <0>; ++ }; ++ ++ cp0_usb3_0_phy0: usb-phy-1 { /*OLD: cp0_usb3_phy@0 */ ++ compatible = "usb-nop-xceiv"; ++ vcc-supply = <&cp0_reg_usb3_vbus0>; ++ }; ++ ++ cp0_reg_usb3_vbus1: regulator-3 { /*OLD: cp0_usb3_vbus@1 */ ++ compatible = "regulator-fixed"; ++ regulator-name = "cp0-xhci1-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ }; ++ ++ cp0_usb3_0_phy1: usb-phy-2 { /*OLD: cp0_usb3_phy@1 */ ++ compatible = "usb-nop-xceiv"; ++ vcc-supply = <&cp0_reg_usb3_vbus1>; ++ }; ++ ++ cp0_reg_sd_vccq: regulator-4 { /*OLD: cp0_sd_vccq@0 */ ++ compatible = "regulator-gpio"; ++ regulator-name = "cp0_sd_vccq"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ states = <1800000 0x1 ++ 3300000 0x0>; ++ }; ++ ++ cp0_reg_sd_vcc: regulator-5 { /*OLD: cp0_sd_vcc@0 */ ++ compatible = "regulator-fixed"; ++ regulator-name = "cp0_sd_vcc"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ enable-active-high; ++ regulator-always-on; ++ }; ++ ++ cp0_sfp_eth0: sfp-eth-1 { /*OLD: sfp-eth@0 */ ++ compatible = "sff,sfp"; ++ /* ++ * SFP cages are unconnected on early PCBs because of an the I2C ++ * lanes not being connected. Prevent the port for being ++ * unusable by disabling the SFP node. ++ */ ++ status = "disabled"; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cp0_uart2_pins>; ++ status = "okay"; ++}; ++ ++/* on-board eMMC - U9 */ ++&ap_sdhci0 { ++ pinctrl-names = "default"; ++ bus-width = <8>; ++ vqmmc-supply = <&ap0_reg_sd_vccq>; ++ status = "okay"; ++ non-removable; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++}; ++ ++&cp0_crypto { ++ status = "disabled"; ++}; ++ ++&cp0_ethernet { ++ status = "okay"; ++}; ++ ++/* SLM-1521-V2, CON9 */ ++&cp0_eth0 { ++ status = "disabled"; ++ phy-mode = "10gbase-kr"; ++ /* Generic PHY, providing serdes lanes */ ++ phys = <&cp0_comphy4 0>; ++ managed = "in-band-status"; ++ sfp = <&cp0_sfp_eth0>; ++}; ++ ++/* CON56 */ ++&cp0_eth1 { ++ status = "okay"; ++ phy = <&phy0>; ++ phy-mode = "rgmii-id"; ++}; ++ ++/* CON57 */ ++&cp0_eth2 { ++ status = "disabled"; ++ phy-mode = "rgmii-id"; ++}; ++ ++&cp0_gpio1 { ++ status = "okay"; ++}; ++ ++&cp0_gpio2 { ++ status = "okay"; ++}; ++ ++&cp0_i2c0 { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cp0_i2c0_pins>; ++ clock-frequency = <100000>; ++ ++ /* U42 */ ++ eeprom0: eeprom@50 { ++ compatible = "atmel,24c64"; ++ reg = <0x50>; ++ pagesize = <0x20>; ++ }; ++}; ++ ++&cp0_i2c1 { ++ status = "okay"; ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cp0_i2c1_pins>; ++}; ++ ++&cp0_mdio { ++ status = "okay"; ++ pinctrl-0 = <&cp0_ge_mdio_pins>; ++ phy0: ethernet-phy@0 { ++ marvell,reg-init = <3 16 0 0x1a4a>; ++ reg = <0>; ++ }; ++}; ++ ++/* PCIE X4 Slot */ ++&cp0_pcie0 { ++ status = "okay"; ++ num-lanes = <4>; ++ num-viewport = <8>; ++ /* Generic PHY, providing serdes lanes */ ++ phys = <&cp0_comphy0 0 ++ &cp0_comphy1 0 ++ &cp0_comphy2 0 ++ &cp0_comphy3 0>; ++}; ++ ++/* PCIE X1 Slot */ ++&cp0_pcie2 { ++ status = "okay"; ++ num-lanes = <1>; ++ num-viewport = <8>; ++ phys = <&cp0_comphy5 2>; ++}; ++ ++/* ++ * &cp0_sdhci0 { ++ * status = "disabled"; ++ * pinctrl-names = "default"; ++ * pinctrl-0 = <&cp0_sdhci_pins ++ * &cp0_sdhci_cd_pins>; ++ * bus-width = <4>; ++ * cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>; ++ * no-1-8-v; ++ * vqmmc-supply = <&cp0_reg_sd_vccq>; ++ * vmmc-supply = <&cp0_reg_sd_vcc>; ++ * }; ++ */ ++ ++/* U55 */ ++&cp0_spi1 { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cp0_spi0_pins>; ++ reg = <0x700680 0x50>; ++ ++ spi-flash@0 { ++ #address-cells = <0x1>; ++ #size-cells = <0x1>; ++ compatible = "jedec,spi-nor"; ++ reg = <0x0>; ++ /* On-board MUX does not allow higher frequencies */ ++ spi-max-frequency = <40000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "U-Boot-0"; ++ reg = <0x0 0x200000>; ++ }; ++ ++ partition@400000 { ++ label = "Filesystem-0"; ++ reg = <0x200000 0xe00000>; ++ }; ++ }; ++ }; ++}; ++ ++&cp0_syscon0 { ++ cp0_pinctrl: pinctrl { ++ compatible = "marvell,cp115-standalone-pinctrl"; ++ ++ cp0_ge_mdio_pins: ge-mdio-pins { ++ marvell,pins = "mpp40", "mpp41"; ++ marvell,function = "ge"; ++ }; ++ cp0_i2c0_pins: cp0-i2c-pins-0 { ++ marvell,pins = "mpp37", "mpp38"; ++ marvell,function = "i2c0"; ++ }; ++ cp0_i2c1_pins: cp0-i2c-pins-1 { ++ marvell,pins = "mpp35", "mpp36"; ++ marvell,function = "i2c1"; ++ }; ++ cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 { ++ marvell,pins = "mpp0", "mpp1", "mpp2", ++ "mpp3", "mpp4", "mpp5", ++ "mpp6", "mpp7", "mpp8", ++ "mpp9", "mpp10", "mpp11"; ++ marvell,function = "ge0"; ++ }; ++ cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 { ++ marvell,pins = "mpp55"; ++ marvell,function = "sdio"; ++ }; ++ cp0_sdhci_pins: cp0-sdhi-pins-0 { ++ marvell,pins = "mpp56", "mpp57", "mpp58", ++ "mpp59", "mpp60", "mpp61"; ++ marvell,function = "sdio"; ++ }; ++ cp0_spi0_pins: cp0-spi-pins-0 { ++ marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; ++ marvell,function = "spi1"; ++ }; ++ cp0_uart2_pins: uart22-pins { ++ marvell,pins = "mpp50", "mpp51"; ++ marvell,function = "uart2"; ++ }; ++ cp0_jtag_upgrade_pins: cp0-jtag-pins-0 { ++ marvell,pins = "mpp54", "mpp56", "mpp57", "mpp61"; ++ marvell,function = "gpio"; ++ }; ++ }; ++}; ++ ++&cp0_usb3_0 { ++ status = "okay"; ++ usb-phy = <&cp0_usb3_0_phy0>; ++ phy-names = "usb"; ++}; ++ ++&cp0_usb3_1 { ++ status = "okay"; ++ usb-phy = <&cp0_usb3_0_phy1>; ++ phy-names = "usb"; ++}; +diff --git a/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dts b/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dts +new file mode 100644 +index 000000000..46adda40a +--- /dev/null ++++ b/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dts +@@ -0,0 +1,212 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2025 Marvell International Ltd. ++ */ ++ ++/* This DB board is an extension for "ac5x-rd-carrier-cn9131" */ ++ ++/dts-v1/; ++ ++#include "cn9130-db-comexpress.dts" ++ ++/ { ++ model = "Marvell Armada CN9131-DB-Comexpress type 7 CPU module (TRIXIE)"; ++ compatible = "marvell,cn9131", "marvell,cn9130", ++ "marvell,armada-ap807-quad", "marvell,armada-ap807"; ++ ++ aliases { ++ /** From "cn9130-db-comexpress.dts": ++ gpio1 = &cp0_gpio1; ++ gpio2 = &cp0_gpio2; ++ i2c0 = &cp0_i2c0; ++ i2c1 = &cp0_i2c1; ++ ethernet0 = &cp0_eth0; ++ ethernet1 = &cp0_eth1; ++ ethernet2 = &cp0_eth2; ++ spi1 = &cp0_spi0; ++ spi2 = &cp0_spi1; ++ **/ ++ i2c2 = &cp1_i2c0; ++ i2c3 = &cp1_i2c1; ++ gpio3 = &cp1_gpio1; ++ gpio4 = &cp1_gpio2; ++ ethernet3 = &cp1_eth0; ++ ethernet4 = &cp1_eth1; ++ }; ++ ++ cp1_reg_usb3_vbus0: regulator-6 { /*OLD: cp1_usb3_vbus@0 */ ++ compatible = "regulator-fixed"; ++ regulator-name = "cp1-xhci0-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ }; ++ ++ cp1_usb3_0_phy0: usb-phy-3 { /*OLD: cp1_usb3_phy0 */ ++ compatible = "usb-nop-xceiv"; ++ vcc-supply = <&cp1_reg_usb3_vbus0>; ++ }; ++ ++ cp1_reg_usb3_vbus1: cp1_usb3_vbus@1 { ++ compatible = "regulator-fixed"; ++ regulator-name = "cp1-xhci1-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ }; ++ ++ cp1_usb3_0_phy1: cp1_usb3_phy@1 { ++ compatible = "usb-nop-xceiv"; ++ vcc-supply = <&cp1_reg_usb3_vbus1>; ++ }; ++ ++ cp1_sfp_eth0: sfp-eth0 { ++ compatible = "sff,sfp"; ++ /*i2c-bus = <&cp1_i2c1>;*/ ++ mod-def0-gpio = <&cp1_gpio2 10 GPIO_ACTIVE_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cp1_sfp_present_pins>; ++ }; ++}; ++ ++/* ++ * Instantiate the first slave CP115 ++ */ ++ ++#define CP11X_NAME cp1 ++#define CP11X_BASE f4000000 ++#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000)) ++#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 ++#define CP11X_PCIE0_BASE f4600000 ++#define CP11X_PCIE1_BASE f4620000 ++#define CP11X_PCIE2_BASE f4640000 ++ ++#include "armada-cp115.dtsi" ++ ++#undef CP11X_NAME ++#undef CP11X_BASE ++#undef CP11X_PCIEx_MEM_BASE ++#undef CP11X_PCIEx_MEM_SIZE ++#undef CP11X_PCIE0_BASE ++#undef CP11X_PCIE1_BASE ++#undef CP11X_PCIE2_BASE ++ ++&cp1_crypto { ++ status = "disabled"; ++}; ++ ++&cp1_ethernet { ++ status = "disabled"; ++}; ++ ++/* CON50 */ ++&cp1_eth0 { ++ status = "okay"; ++ phy-mode = "10gbase-kr"; ++ /* Generic PHY, providing serdes lanes */ ++ phys = <&cp1_comphy2 0>; ++ managed = "in-band-status"; ++ sfp = <&cp1_sfp_eth0>; ++}; ++ ++&cp1_eth1 { ++ status = "disabled"; ++}; ++ ++&cp1_eth2 { ++ status = "disabled"; ++}; ++ ++&cp1_gpio1 { ++ status = "okay"; ++}; ++ ++&cp1_gpio2 { ++ status = "okay"; ++}; ++ ++/* ++ * CP1_I2C1 MPP[02:03] ++ * or ++ * CP1_I2C1 MPP[35:36] ++ * ++ * CP1_MSSI2C? MPP[00:01] ++ * or ++ * CP1_MSSI2C? MPP[50:51] ++ */ ++&cp1_i2c0 { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cp1_mss_i2c0_pins>; ++ clock-frequency = <100000>; ++}; ++ ++&cp1_i2c1 { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cp1_i2c1_pins>; ++ clock-frequency = <100000>; ++}; ++ ++/* ++ * Comphy chip #1: ++ * Comphy-0: PEX0 ++ * Comphy-1: PEX0 ++ * Comphy-2: SFI0 10.3125 Gbps ++ * Comphy-3: SATA1 ++ * Comphy-4: PEX1 ++ * Comphy-5: PEX2 ++ */ ++ ++/* PCIE X2 NVME */ ++&cp1_pcie0 { ++ num-lanes = <2>; ++ num-viewport = <8>; ++ marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ /* Generic PHY, providing serdes lanes */ ++ phys = <&cp1_comphy0 0 ++ &cp1_comphy1 0>; ++}; ++ ++&cp1_sata0 { ++ status = "okay"; ++ ++ /* CON32 */ ++ sata-port@1 { ++ /* Generic PHY, providing serdes lanes */ ++ phys = <&cp1_comphy3 1>; ++ }; ++}; ++ ++&cp1_syscon0 { ++ cp1_pinctrl: pinctrl { ++ compatible = "marvell,cp115-standalone-pinctrl"; ++ ++ cp1_i2c1_pins: cp1-i2c-pins-1 { ++ marvell,pins = "mpp3", "mpp2"; ++ marvell,function = "i2c1"; ++ }; ++ cp1_mss_i2c0_pins: cp1-mss-i2c-pins-1 { ++ marvell,pins = "mpp0", "mpp1"; ++ marvell,function = "mss_i2c"; ++ }; ++ cp1_xmdio_pins: cp1_xmdio_pins-0 { ++ marvell,pins = "mpp37", "mpp38"; ++ marvell,function = "xg"; ++ }; ++ cp1_sfp_present_pins: cp1_sfp_present_pins-0 { ++ marvell,pins = "mpp50"; ++ marvell,function = "gpio"; ++ }; ++ }; ++}; ++ ++/* CON58 */ ++&cp1_usb3_1 { ++ status = "okay"; ++ usb-phy = <&cp1_usb3_0_phy0>; ++ /* Generic PHY, providing serdes lanes */ ++ phys = <&cp1_comphy3 1>; ++ phy-names = "usb"; ++}; +-- +2.25.1 + diff --git a/patch/0022-drivers-soc-pensando-boot_count-to-sysfs-for-kdump.patch b/patches-sonic/0022-drivers-soc-pensando-boot_count-to-sysfs-for-kdump.patch similarity index 100% rename from patch/0022-drivers-soc-pensando-boot_count-to-sysfs-for-kdump.patch rename to patches-sonic/0022-drivers-soc-pensando-boot_count-to-sysfs-for-kdump.patch diff --git a/patch/0052-i2c-mux-Add-register-map-based-mux-driver.patch b/patches-sonic/0022-i2c-mux-Add-register-map-based-mux-driver.patch similarity index 90% rename from patch/0052-i2c-mux-Add-register-map-based-mux-driver.patch rename to patches-sonic/0022-i2c-mux-Add-register-map-based-mux-driver.patch index b625f42a4..e08a1d32b 100644 --- a/patch/0052-i2c-mux-Add-register-map-based-mux-driver.patch +++ b/patches-sonic/0022-i2c-mux-Add-register-map-based-mux-driver.patch @@ -1,8 +1,7 @@ -From 020e153595d6d9e4494aa930af0af13dddfc4962 Mon Sep 17 00:00:00 2001 +From a377f235d8b753c65239ba6865354cd465f75010 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Wed, 9 Nov 2022 12:22:12 +0200 -Subject: [PATCH backport 6.1.42 31/85] i2c: mux: Add register map based mux - driver +Subject: [PATCH 22/78] i2c: mux: Add register map based mux driver Add 'regmap' mux driver to allow virtual bus switching by setting a single selector register. @@ -32,16 +31,16 @@ access. Signed-off-by: Vadim Pasternak --- - drivers/i2c/muxes/Kconfig | 12 ++ + drivers/i2c/muxes/Kconfig | 12 +++ drivers/i2c/muxes/Makefile | 1 + - drivers/i2c/muxes/i2c-mux-regmap.c | 121 +++++++++++++++++++ - include/linux/platform_data/i2c-mux-regmap.h | 34 ++++++ - 4 files changed, 168 insertions(+) + drivers/i2c/muxes/i2c-mux-regmap.c | 120 +++++++++++++++++++++++++++ + include/linux/platform_data/i2c-mux-regmap.h | 34 ++++++++ + 4 files changed, 167 insertions(+) create mode 100644 drivers/i2c/muxes/i2c-mux-regmap.c create mode 100644 include/linux/platform_data/i2c-mux-regmap.h diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig -index ea838dbae32e..a509b75bd545 100644 +index 6d2f668..9b5e525 100644 --- a/drivers/i2c/muxes/Kconfig +++ b/drivers/i2c/muxes/Kconfig @@ -99,6 +99,18 @@ config I2C_MUX_REG @@ -64,10 +63,10 @@ index ea838dbae32e..a509b75bd545 100644 tristate "pinctrl-based I2C demultiplexer" depends on PINCTRL && OF diff --git a/drivers/i2c/muxes/Makefile b/drivers/i2c/muxes/Makefile -index 6d9d865e8518..092dca428a75 100644 +index 4b24f49..edecfc5 100644 --- a/drivers/i2c/muxes/Makefile +++ b/drivers/i2c/muxes/Makefile -@@ -14,5 +14,6 @@ obj-$(CONFIG_I2C_MUX_PCA9541) += i2c-mux-pca9541.o +@@ -15,5 +15,6 @@ obj-$(CONFIG_I2C_MUX_PCA9541) += i2c-mux-pca9541.o obj-$(CONFIG_I2C_MUX_PCA954x) += i2c-mux-pca954x.o obj-$(CONFIG_I2C_MUX_PINCTRL) += i2c-mux-pinctrl.o obj-$(CONFIG_I2C_MUX_REG) += i2c-mux-reg.o @@ -76,10 +75,10 @@ index 6d9d865e8518..092dca428a75 100644 ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG diff --git a/drivers/i2c/muxes/i2c-mux-regmap.c b/drivers/i2c/muxes/i2c-mux-regmap.c new file mode 100644 -index 000000000000..1ab5f94af8a5 +index 00000000..fb5e89c --- /dev/null +++ b/drivers/i2c/muxes/i2c-mux-regmap.c -@@ -0,0 +1,121 @@ +@@ -0,0 +1,120 @@ +// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 +/* + * Regmap i2c mux driver @@ -163,7 +162,7 @@ index 000000000000..1ab5f94af8a5 + + /* Create an adapter for each channel. */ + for (num = 0; num < pdata->num_adaps; num++) { -+ err = i2c_mux_add_adapter(muxc, 0, pdata->chan_ids[num], 0); ++ err = i2c_mux_add_adapter(muxc, 0, pdata->chan_ids[num]); + if (err) + goto err_i2c_mux_add_adapter; + } @@ -179,12 +178,11 @@ index 000000000000..1ab5f94af8a5 + return err; +} + -+static int i2c_mux_regmap_remove(struct platform_device *pdev) ++static void i2c_mux_regmap_remove(struct platform_device *pdev) +{ + struct i2c_mux_core *muxc = platform_get_drvdata(pdev); + + i2c_mux_del_adapters(muxc); -+ return 0; +} + +static struct platform_driver i2c_mux_regmap_driver = { @@ -203,7 +201,7 @@ index 000000000000..1ab5f94af8a5 +MODULE_ALIAS("platform:i2c-mux-regmap"); diff --git a/include/linux/platform_data/i2c-mux-regmap.h b/include/linux/platform_data/i2c-mux-regmap.h new file mode 100644 -index 000000000000..a06614e5edd2 +index 00000000..a06614e --- /dev/null +++ b/include/linux/platform_data/i2c-mux-regmap.h @@ -0,0 +1,34 @@ @@ -242,5 +240,5 @@ index 000000000000..a06614e5edd2 + +#endif /* __LINUX_PLATFORM_DATA_I2C_MUX_REGMAP_H */ -- -2.20.1 +2.8.4 diff --git a/patch/0023-arch-arm64-boot-dts-psci-support.patch b/patches-sonic/0023-arch-arm64-boot-dts-psci-support.patch similarity index 100% rename from patch/0023-arch-arm64-boot-dts-psci-support.patch rename to patches-sonic/0023-arch-arm64-boot-dts-psci-support.patch diff --git a/patch/0053-platform-mellanox-Add-support-for-dynamic-I2C-channe.patch b/patches-sonic/0023-platform-mellanox-Add-support-for-dynamic-I2C-channe.patch similarity index 89% rename from patch/0053-platform-mellanox-Add-support-for-dynamic-I2C-channe.patch rename to patches-sonic/0023-platform-mellanox-Add-support-for-dynamic-I2C-channe.patch index f396cf234..4e1be9282 100644 --- a/patch/0053-platform-mellanox-Add-support-for-dynamic-I2C-channe.patch +++ b/patches-sonic/0023-platform-mellanox-Add-support-for-dynamic-I2C-channe.patch @@ -1,8 +1,8 @@ -From 7831c5d10460c08cb5837827784677e0286d14e7 Mon Sep 17 00:00:00 2001 +From cf91635805c4971219492c93ca299d472067c68b Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Sun, 30 Jul 2023 21:31:54 +0000 -Subject: [PATH backport v6.1 53/54] platform/mellanox: Add support for dynamic - I2C channels infrastructure +Subject: [PATCH 23/78] platform/mellanox: Add support for dynamic I2C channels + infrastructure Allow to support platform configuration for dynamically allocated I2C channels. @@ -19,11 +19,11 @@ adapters data. Signed-off-by: Vadim Pasternak Reviewed-by: Michael Shych --- - drivers/platform/x86/mlx-platform.c | 69 ++++++++++++++++++++++++----- - 1 file changed, 59 insertions(+), 10 deletions(-) + drivers/platform/x86/mlx-platform.c | 70 +++++++++++++++++++++++++++++++------ + 1 file changed, 60 insertions(+), 10 deletions(-) diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 44f107965832..9021597b5446 100644 +index 1a09f2d..cbd5634 100644 --- a/drivers/platform/x86/mlx-platform.c +++ b/drivers/platform/x86/mlx-platform.c @@ -15,6 +15,7 @@ @@ -82,7 +82,7 @@ index 44f107965832..9021597b5446 100644 mlxplat_hotplug->shift_nr = shift; return 0; -@@ -6428,8 +6438,31 @@ mlxplat_i2c_mux_complition_notify(void *handle, struct i2c_adapter *parent, +@@ -6430,8 +6440,32 @@ mlxplat_i2c_mux_complition_notify(void *handle, struct i2c_adapter *parent, struct i2c_adapter *adapters[]) { struct mlxplat_priv *priv = handle; @@ -106,16 +106,17 @@ index 44f107965832..9021597b5446 100644 + } + } -- return mlxplat_post_init(priv); +- return mlxplat_platdevs_init(priv); ++ + /* Start post initialization only after last nux segment is added */ + if (++priv->mux_added == mlxplat_mux_num) -+ return mlxplat_post_init(priv); ++ return mlxplat_platdevs_init(priv); + + return 0; } static int mlxplat_i2c_mux_topology_init(struct mlxplat_priv *priv) -@@ -6443,17 +6476,33 @@ static int mlxplat_i2c_mux_topology_init(struct mlxplat_priv *priv) +@@ -6445,17 +6479,33 @@ static int mlxplat_i2c_mux_topology_init(struct mlxplat_priv *priv) priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED; for (i = 0; i < mlxplat_mux_num; i++) { @@ -150,10 +151,10 @@ index 44f107965832..9021597b5446 100644 + if (mlxplat_mux_regmap_data && mlxplat_mux_regmap_data->completion_notify) + return 0; + -+ return mlxplat_post_init(priv); ++ return mlxplat_platdevs_init(priv); fail_platform_mux_register: while (--i >= 0) -- -2.20.1 +2.8.4 diff --git a/patch/0024-drivers-soc-pensando-penfw-driver.patch b/patches-sonic/0024-drivers-soc-pensando-penfw-driver.patch similarity index 100% rename from patch/0024-drivers-soc-pensando-penfw-driver.patch rename to patches-sonic/0024-drivers-soc-pensando-penfw-driver.patch diff --git a/patch/0055-mellanox-Relocate-mlx-platform-driver.patch b/patches-sonic/0024-mellanox-Relocate-mlx-platform-driver.patch similarity index 64% rename from patch/0055-mellanox-Relocate-mlx-platform-driver.patch rename to patches-sonic/0024-mellanox-Relocate-mlx-platform-driver.patch index 3b5f6b940..44f42f022 100644 --- a/patch/0055-mellanox-Relocate-mlx-platform-driver.patch +++ b/patches-sonic/0024-mellanox-Relocate-mlx-platform-driver.patch @@ -1,34 +1,64 @@ -From a4eca7c60f361575fb15bcab6fdcd39c795c8244 Mon Sep 17 00:00:00 2001 +From 001d29f7f17201ff584f160814408fef22cad10d Mon Sep 17 00:00:00 2001 From: Vadim Pasternak -Date: Mon, 24 Jul 2023 11:52:56 +0000 -Subject: [PATCH backport 6.1.42 58/85] mellanox: Relocate mlx-platform driver +Date: Fri, 24 Jan 2025 19:26:19 +0200 +Subject: [PATCH 26/80] mellanox: Relocate mlx-platform driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit Move 'mlx-platform' driver 'x86' to 'mellanox' folder. Motivation to allow running it on systems with ARM architecture. -Signed-off-by: Vadim Pasternak +Since drivers/platform/x86/mlx-platform.c is rellocated to folder +drivers/platform/x86/, remove "MELLANOX PLATFORM DRIVER" item. +This driver will be located under "MELLANOX HARDWARE PLATFORM SUPPORT" +item. + Reviewed-by: Michael Shych +Signed-off-by: Vadim Pasternak +Link: https://lore.kernel.org/r/20250124172632.22437-2-vadimp@nvidia.com +Reviewed-by: Ilpo Järvinen +Signed-off-by: Ilpo Järvinen --- - drivers/platform/mellanox/Kconfig | 12 ++++++++++++ + MAINTAINERS | 6 ------ + drivers/platform/mellanox/Kconfig | 13 +++++++++++++ drivers/platform/mellanox/Makefile | 1 + drivers/platform/{x86 => mellanox}/mlx-platform.c | 0 drivers/platform/x86/Kconfig | 13 ------------- drivers/platform/x86/Makefile | 1 - - 5 files changed, 13 insertions(+), 14 deletions(-) + 6 files changed, 14 insertions(+), 20 deletions(-) rename drivers/platform/{x86 => mellanox}/mlx-platform.c (100%) +diff --git a/MAINTAINERS b/MAINTAINERS +index d0f18fdba068..81730c72c960 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -14775,12 +14775,6 @@ F: Documentation/leds/leds-mlxcpld.rst + F: drivers/leds/leds-mlxcpld.c + F: drivers/leds/leds-mlxreg.c + +-MELLANOX PLATFORM DRIVER +-M: Vadim Pasternak +-L: platform-driver-x86@vger.kernel.org +-S: Supported +-F: drivers/platform/x86/mlx-platform.c +- + MEMBARRIER SUPPORT + M: Mathieu Desnoyers + M: "Paul E. McKenney" diff --git a/drivers/platform/mellanox/Kconfig b/drivers/platform/mellanox/Kconfig -index 382793e73a60..70b628834b4f 100644 +index f7dfa0e785fd..aa760f064a17 100644 --- a/drivers/platform/mellanox/Kconfig +++ b/drivers/platform/mellanox/Kconfig -@@ -14,6 +14,18 @@ menuconfig MELLANOX_PLATFORM +@@ -14,6 +14,19 @@ menuconfig MELLANOX_PLATFORM if MELLANOX_PLATFORM +config MLX_PLATFORM + tristate "Mellanox Technologies platform support" -+ depends on I2C && REGMAP ++ depends on ACPI && I2C && PCI ++ select REGMAP + help + This option enables system support for the Mellanox Technologies + platform. The Mellanox systems provide data center networking @@ -58,16 +88,16 @@ similarity index 100% rename from drivers/platform/x86/mlx-platform.c rename to drivers/platform/mellanox/mlx-platform.c diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig -index 1396a839dd8a..f11136bbf88d 100644 +index 3875abba5a79..92a3d5be0e36 100644 --- a/drivers/platform/x86/Kconfig +++ b/drivers/platform/x86/Kconfig -@@ -954,19 +954,6 @@ config SERIAL_MULTI_INSTANTIATE +@@ -1010,19 +1010,6 @@ config SERIAL_MULTI_INSTANTIATE To compile this driver as a module, choose M here: the module will be called serial-multi-instantiate. -config MLX_PLATFORM - tristate "Mellanox Technologies platform support" -- depends on I2C +- depends on ACPI && I2C && PCI - select REGMAP - help - This option enables system support for the Mellanox Technologies @@ -82,17 +112,17 @@ index 1396a839dd8a..f11136bbf88d 100644 bool "DMI based touchscreen configuration info" depends on ACPI && DMI && I2C=y && TOUCHSCREEN_SILEAD diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile -index 1d3d1b02541b..aee1bc4b0a80 100644 +index 4631c7bb22cd..776401fb9f04 100644 --- a/drivers/platform/x86/Makefile +++ b/drivers/platform/x86/Makefile -@@ -109,7 +109,6 @@ obj-$(CONFIG_TOPSTAR_LAPTOP) += topstar-laptop.o +@@ -123,7 +123,6 @@ obj-$(CONFIG_TOPSTAR_LAPTOP) += topstar-laptop.o + # Platform drivers - obj-$(CONFIG_FW_ATTR_CLASS) += firmware_attributes_class.o obj-$(CONFIG_SERIAL_MULTI_INSTANTIATE) += serial-multi-instantiate.o -obj-$(CONFIG_MLX_PLATFORM) += mlx-platform.o obj-$(CONFIG_TOUCHSCREEN_DMI) += touchscreen_dmi.o obj-$(CONFIG_WIRELESS_HOTKEY) += wireless-hotkey.o - obj-$(CONFIG_X86_ANDROID_TABLETS) += x86-android-tablets.o + obj-$(CONFIG_X86_ANDROID_TABLETS) += x86-android-tablets/ -- -2.20.1 +2.47.2 diff --git a/patch/0025-dts-changes-for-mtfuji-and-lipari.patch b/patches-sonic/0025-dts-changes-for-mtfuji-and-lipari.patch similarity index 100% rename from patch/0025-dts-changes-for-mtfuji-and-lipari.patch rename to patches-sonic/0025-dts-changes-for-mtfuji-and-lipari.patch diff --git a/patches-sonic/0025-platform-mellanox-mlx-platform-Cosmetic-changes.patch b/patches-sonic/0025-platform-mellanox-mlx-platform-Cosmetic-changes.patch new file mode 100644 index 000000000..4b691ada5 --- /dev/null +++ b/patches-sonic/0025-platform-mellanox-mlx-platform-Cosmetic-changes.patch @@ -0,0 +1,71 @@ +From 21cb84ee58d84c50143bb6abcf8648777f6134c7 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Fri, 24 Jan 2025 19:26:20 +0200 +Subject: [PATCH 25/78] platform: mellanox: mlx-platform: Cosmetic changes +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Remove redundant spaces. + +Reviewed-by: Felix Radensky +Signed-off-by: Vadim Pasternak +Link: https://lore.kernel.org/r/20250124172632.22437-3-vadimp@nvidia.com +Reviewed-by: Ilpo Järvinen +Signed-off-by: Ilpo Järvinen +--- + drivers/platform/mellanox/mlx-platform.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c +index cbd5634..cc61f8e 100644 +--- a/drivers/platform/mellanox/mlx-platform.c ++++ b/drivers/platform/mellanox/mlx-platform.c +@@ -2252,7 +2252,7 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_modular_data = { + .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, + }; + +-/* Platform hotplug for NVLink blade systems family data */ ++/* Platform hotplug for NVLink blade systems family data */ + static struct mlxreg_core_data mlxplat_mlxcpld_global_wp_items_data[] = { + { + .label = "global_wp_grant", +@@ -2284,7 +2284,7 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_chassis_blade_data = { + .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, + }; + +-/* Platform hotplug for switch systems family data */ ++/* Platform hotplug for switch systems family data */ + static struct mlxreg_core_data mlxplat_mlxcpld_erot_ap_items_data[] = { + { + .label = "erot1_ap", +@@ -2392,7 +2392,7 @@ static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_pwr_events_ + .user_handler = mlxplat_mlxcpld_l1_switch_pwr_events_handler, + }; + +-/* Platform hotplug for l1 switch systems family data */ ++/* Platform hotplug for l1 switch systems family data */ + static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_pwr_events_items_data[] = { + { + .label = "power_button", +@@ -4406,7 +4406,7 @@ static struct mlxreg_core_platform_data mlxplat_modular_regs_io_data = { + .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_regs_io_data), + }; + +-/* Platform register access for chassis blade systems family data */ ++/* Platform register access for chassis blade systems family data */ + static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { + { + .label = "cpld1_version", +@@ -6623,7 +6623,7 @@ static int mlxplat_probe(struct platform_device *pdev) + } + + /* Set default registers. */ +- for (i = 0; i < mlxplat_regmap_config->num_reg_defaults; i++) { ++ for (i = 0; i < mlxplat_regmap_config->num_reg_defaults; i++) { + err = regmap_write(priv->regmap, + mlxplat_regmap_config->reg_defaults[i].reg, + mlxplat_regmap_config->reg_defaults[i].def); +-- +2.8.4 + diff --git a/patch/0026-Add-support-for-new-qspi-macronix-flash-mx66u1g45g.patch b/patches-sonic/0026-Add-support-for-new-qspi-macronix-flash-mx66u1g45g.patch similarity index 100% rename from patch/0026-Add-support-for-new-qspi-macronix-flash-mx66u1g45g.patch rename to patches-sonic/0026-Add-support-for-new-qspi-macronix-flash-mx66u1g45g.patch diff --git a/patches-sonic/0026-platform-mellanox-Rename-field-to-improve-code-reada.patch b/patches-sonic/0026-platform-mellanox-Rename-field-to-improve-code-reada.patch new file mode 100644 index 000000000..814a0142a --- /dev/null +++ b/patches-sonic/0026-platform-mellanox-Rename-field-to-improve-code-reada.patch @@ -0,0 +1,239 @@ +From 66134d289e9ca0d1c9a3225e9e82f4ef41788290 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Sat, 12 Apr 2025 12:18:37 +0300 +Subject: [PATCH 26/78] platform/mellanox: Rename field to improve code + readability +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Rename field 'counter' in 'mlxreg_core_hotplug_platform_data' to count. + +Signed-off-by: Vadim Pasternak +Link: https://lore.kernel.org/r/20250412091843.33943-2-vadimp@nvidia.com +Reviewed-by: Ilpo Järvinen +Signed-off-by: Ilpo Järvinen +--- + drivers/platform/mellanox/mlx-platform.c | 28 ++++++++++++++-------------- + drivers/platform/mellanox/mlxreg-hotplug.c | 8 ++++---- + drivers/platform/mellanox/nvsw-sn2201.c | 4 ++-- + include/linux/platform_data/mlxreg.h | 4 ++-- + 4 files changed, 22 insertions(+), 22 deletions(-) + +diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c +index cc61f8e..a7a4c7f 100644 +--- a/drivers/platform/mellanox/mlx-platform.c ++++ b/drivers/platform/mellanox/mlx-platform.c +@@ -857,7 +857,7 @@ static struct mlxreg_core_item mlxplat_mlxcpld_comex_items[] = { + static + struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_data = { + .items = mlxplat_mlxcpld_default_items, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_items), ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_items), + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, + .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, +@@ -897,7 +897,7 @@ static struct mlxreg_core_item mlxplat_mlxcpld_default_wc_items[] = { + static + struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_wc_data = { + .items = mlxplat_mlxcpld_default_wc_items, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_wc_items), ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_wc_items), + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, + .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, +@@ -907,7 +907,7 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_wc_data = { + static + struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_comex_data = { + .items = mlxplat_mlxcpld_comex_items, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_items), ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_comex_items), + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, + .mask = MLXPLAT_CPLD_AGGR_MASK_CARR_DEF, + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET, +@@ -954,7 +954,7 @@ static struct mlxreg_core_item mlxplat_mlxcpld_msn21xx_items[] = { + static + struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn21xx_data = { + .items = mlxplat_mlxcpld_msn21xx_items, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_items), ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_items), + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, + .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, +@@ -1063,7 +1063,7 @@ static struct mlxreg_core_item mlxplat_mlxcpld_msn274x_items[] = { + static + struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn274x_data = { + .items = mlxplat_mlxcpld_msn274x_items, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_items), ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_items), + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, + .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, +@@ -1110,7 +1110,7 @@ static struct mlxreg_core_item mlxplat_mlxcpld_msn201x_items[] = { + static + struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn201x_data = { + .items = mlxplat_mlxcpld_msn201x_items, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_items), ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_items), + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, + .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, +@@ -1234,7 +1234,7 @@ static struct mlxreg_core_item mlxplat_mlxcpld_default_ng_items[] = { + static + struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_ng_data = { + .items = mlxplat_mlxcpld_default_ng_items, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_items), ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_items), + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, + .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, +@@ -1394,7 +1394,7 @@ static struct mlxreg_core_item mlxplat_mlxcpld_ng800_items[] = { + static + struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { + .items = mlxplat_mlxcpld_ext_items, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_ext_items), ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_items), + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, + .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, +@@ -1404,7 +1404,7 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { + static + struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_data = { + .items = mlxplat_mlxcpld_ng800_items, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_ng800_items), ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_ng800_items), + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, + .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, +@@ -2245,7 +2245,7 @@ static struct mlxreg_core_item mlxplat_mlxcpld_modular_items[] = { + static + struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_modular_data = { + .items = mlxplat_mlxcpld_modular_items, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_items), ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_items), + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, + .mask = MLXPLAT_CPLD_AGGR_MASK_MODULAR, + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, +@@ -2277,7 +2277,7 @@ static struct mlxreg_core_item mlxplat_mlxcpld_chassis_blade_items[] = { + static + struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_chassis_blade_data = { + .items = mlxplat_mlxcpld_chassis_blade_items, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_items), ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_items), + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, + .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX, + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, +@@ -2368,7 +2368,7 @@ static struct mlxreg_core_item mlxplat_mlxcpld_rack_switch_items[] = { + static + struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_rack_switch_data = { + .items = mlxplat_mlxcpld_rack_switch_items, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_rack_switch_items), ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_rack_switch_items), + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, + .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, +@@ -2523,7 +2523,7 @@ static struct mlxreg_core_item mlxplat_mlxcpld_l1_switch_events_items[] = { + static + struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_l1_switch_data = { + .items = mlxplat_mlxcpld_l1_switch_events_items, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_events_items), ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_events_items), + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, + .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, +@@ -6450,7 +6450,7 @@ mlxplat_i2c_mux_complition_notify(void *handle, struct i2c_adapter *parent, + */ + if (priv->mux_added == mlxplat_mux_hotplug_num) { + item = mlxplat_hotplug->items; +- for (i = 0; i < mlxplat_hotplug->counter; i++, item++) { ++ for (i = 0; i < mlxplat_hotplug->count; i++, item++) { + struct mlxreg_core_data *data = item->data; + + for (j = 0; j < item->count; j++, data++) { +diff --git a/drivers/platform/mellanox/mlxreg-hotplug.c b/drivers/platform/mellanox/mlxreg-hotplug.c +index 40d5b99..23fdbcb 100644 +--- a/drivers/platform/mellanox/mlxreg-hotplug.c ++++ b/drivers/platform/mellanox/mlxreg-hotplug.c +@@ -262,7 +262,7 @@ static int mlxreg_hotplug_attr_init(struct mlxreg_hotplug_priv_data *priv) + item = pdata->items; + + /* Go over all kinds of items - psu, pwr, fan. */ +- for (i = 0; i < pdata->counter; i++, item++) { ++ for (i = 0; i < pdata->count; i++, item++) { + if (item->capability) { + /* + * Read group capability register to get actual number +@@ -541,7 +541,7 @@ static void mlxreg_hotplug_work_handler(struct work_struct *work) + goto unmask_event; + + /* Handle topology and health configuration changes. */ +- for (i = 0; i < pdata->counter; i++, item++) { ++ for (i = 0; i < pdata->count; i++, item++) { + if (aggr_asserted & item->aggr_mask) { + if (item->health) + mlxreg_hotplug_health_work_helper(priv, item); +@@ -590,7 +590,7 @@ static int mlxreg_hotplug_set_irq(struct mlxreg_hotplug_priv_data *priv) + pdata = dev_get_platdata(&priv->pdev->dev); + item = pdata->items; + +- for (i = 0; i < pdata->counter; i++, item++) { ++ for (i = 0; i < pdata->count; i++, item++) { + /* Clear group presense event. */ + ret = regmap_write(priv->regmap, item->reg + + MLXREG_HOTPLUG_EVENT_OFF, 0); +@@ -674,7 +674,7 @@ static void mlxreg_hotplug_unset_irq(struct mlxreg_hotplug_priv_data *priv) + 0); + + /* Clear topology configurations. */ +- for (i = 0; i < pdata->counter; i++, item++) { ++ for (i = 0; i < pdata->count; i++, item++) { + data = item->data; + /* Mask group presense event. */ + regmap_write(priv->regmap, data->reg + MLXREG_HOTPLUG_MASK_OFF, +diff --git a/drivers/platform/mellanox/nvsw-sn2201.c b/drivers/platform/mellanox/nvsw-sn2201.c +index beb3f82..db31c8b 100644 +--- a/drivers/platform/mellanox/nvsw-sn2201.c ++++ b/drivers/platform/mellanox/nvsw-sn2201.c +@@ -523,7 +523,7 @@ static struct mlxreg_core_item nvsw_sn2201_items[] = { + static + struct mlxreg_core_hotplug_platform_data nvsw_sn2201_hotplug = { + .items = nvsw_sn2201_items, +- .counter = ARRAY_SIZE(nvsw_sn2201_items), ++ .count = ARRAY_SIZE(nvsw_sn2201_items), + .cell = NVSW_SN2201_SYS_INT_STATUS_OFFSET, + .mask = NVSW_SN2201_CPLD_AGGR_MASK_DEF, + }; +@@ -552,7 +552,7 @@ static struct mlxreg_core_item nvsw_sn2201_busbar_items[] = { + static + struct mlxreg_core_hotplug_platform_data nvsw_sn2201_busbar_hotplug = { + .items = nvsw_sn2201_busbar_items, +- .counter = ARRAY_SIZE(nvsw_sn2201_busbar_items), ++ .count = ARRAY_SIZE(nvsw_sn2201_busbar_items), + .cell = NVSW_SN2201_SYS_INT_STATUS_OFFSET, + .mask = NVSW_SN2201_CPLD_AGGR_BUSBAR_MASK_DEF, + }; +diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_data/mlxreg.h +index 0b9f81a..f6cca7a 100644 +--- a/include/linux/platform_data/mlxreg.h ++++ b/include/linux/platform_data/mlxreg.h +@@ -209,7 +209,7 @@ struct mlxreg_core_platform_data { + * @items: same type components with the hotplug capability; + * @irq: platform interrupt number; + * @regmap: register map of parent device; +- * @counter: number of the components with the hotplug capability; ++ * @count: number of the components with the hotplug capability; + * @cell: location of top aggregation interrupt register; + * @mask: top aggregation interrupt common mask; + * @cell_low: location of low aggregation interrupt register; +@@ -224,7 +224,7 @@ struct mlxreg_core_hotplug_platform_data { + struct mlxreg_core_item *items; + int irq; + void *regmap; +- int counter; ++ int count; + u32 cell; + u32 mask; + u32 cell_low; +-- +2.8.4 + diff --git a/patch/0027-pensando-add-rtc-cpld.patch b/patches-sonic/0027-pensando-add-rtc-cpld.patch similarity index 100% rename from patch/0027-pensando-add-rtc-cpld.patch rename to patches-sonic/0027-pensando-add-rtc-cpld.patch diff --git a/patch/0089-platform-mellanox-mlx-platform-Change-register-name.patch b/patches-sonic/0027-platform-mellanox-mlx-platform-Change-register-name.patch similarity index 70% rename from patch/0089-platform-mellanox-mlx-platform-Change-register-name.patch rename to patches-sonic/0027-platform-mellanox-mlx-platform-Change-register-name.patch index 77ae17d7f..205ce004f 100644 --- a/patch/0089-platform-mellanox-mlx-platform-Change-register-name.patch +++ b/patches-sonic/0027-platform-mellanox-mlx-platform-Change-register-name.patch @@ -1,20 +1,25 @@ -From deff38f0bc8aa9518a78474b2b1ab28f85f75f58 Mon Sep 17 00:00:00 2001 -From: Felix Radensky -Date: Thu, 21 Sep 2023 05:53:11 +0000 -Subject: [PATCH v6.1 1/8] platform: mellanox: mlx-platform: Change register - name +From f6d1e88b0f6809f755fae05b74bafb187db36f64 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Fri, 24 Jan 2025 19:26:21 +0200 +Subject: [PATCH 27/78] platform: mellanox: mlx-platform: Change register name +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit Register 0xd9 was repurposed on new systems. Change its name to correctly reflect the new functionality. -Signed-off-by: Felix Radensky -Reviewed-by: Vadim Pasternak +Reviewed-by: Felix Radensky +Signed-off-by: Vadim Pasternak +Link: https://lore.kernel.org/r/20250124172632.22437-4-vadimp@nvidia.com +Reviewed-by: Ilpo Järvinen +Signed-off-by: Ilpo Järvinen --- drivers/platform/mellanox/mlx-platform.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index 46958810e972..c1ebd4f85158 100644 +index a7a4c7f..6f24de1 100644 --- a/drivers/platform/mellanox/mlx-platform.c +++ b/drivers/platform/mellanox/mlx-platform.c @@ -146,7 +146,7 @@ @@ -26,7 +31,7 @@ index 46958810e972..c1ebd4f85158 100644 #define MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET 0xdb #define MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET 0xda #define MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET 0xdc -@@ -5102,7 +5102,6 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) +@@ -5055,7 +5055,6 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: @@ -34,7 +39,7 @@ index 46958810e972..c1ebd4f85158 100644 case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: -@@ -5239,7 +5238,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) +@@ -5191,7 +5190,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: @@ -43,7 +48,7 @@ index 46958810e972..c1ebd4f85158 100644 case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: -@@ -5397,7 +5396,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) +@@ -5348,7 +5347,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: @@ -53,5 +58,5 @@ index 46958810e972..c1ebd4f85158 100644 case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: -- -2.20.1 +2.8.4 diff --git a/patch/0028-Added-current-sensors-in-dtsi.patch b/patches-sonic/0028-Added-current-sensors-in-dtsi.patch similarity index 100% rename from patch/0028-Added-current-sensors-in-dtsi.patch rename to patches-sonic/0028-Added-current-sensors-in-dtsi.patch diff --git a/patch/0028-Create-miniaturised-diafgw-partition-for-128MB-flash.patch b/patches-sonic/0028-Create-miniaturised-diafgw-partition-for-128MB-flash.patch similarity index 100% rename from patch/0028-Create-miniaturised-diafgw-partition-for-128MB-flash.patch rename to patches-sonic/0028-Create-miniaturised-diafgw-partition-for-128MB-flash.patch diff --git a/patch/0091-platform-mellanox-mlxreg-dpu-Add-initial-support-for.patch b/patches-sonic/0028-platform-mellanox-mlxreg-dpu-Add-initial-support-for.patch similarity index 92% rename from patch/0091-platform-mellanox-mlxreg-dpu-Add-initial-support-for.patch rename to patches-sonic/0028-platform-mellanox-mlxreg-dpu-Add-initial-support-for.patch index fb43e1480..a8c1dc775 100644 --- a/patch/0091-platform-mellanox-mlxreg-dpu-Add-initial-support-for.patch +++ b/patches-sonic/0028-platform-mellanox-mlxreg-dpu-Add-initial-support-for.patch @@ -1,8 +1,8 @@ -From 2f247a7eaf25a3de00d6319f2b6314d0c3bf36f6 Mon Sep 17 00:00:00 2001 +From 10505bcbd54c4e7fc5194384f5bb0aea5230b296 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak -Date: Mon, 17 Jun 2024 00:52:00 +0300 -Subject: [PATCH backport v6.1 1/2] platform/mellanox: mlxreg-dpu: Add initial - support for Nvidia DPU +Date: Mon, 21 Apr 2025 12:20:46 +0300 +Subject: [PATCH 28/78] platform/mellanox: mlxreg-dpu: Add initial support for + Nvidia DPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -19,29 +19,34 @@ The Smart Switch equipped with: - Two power supplies. - Four cooling drawers. -Drivers provides support for the platform management and monitoring -of DPU components. -It includes support for health events, resets and boot progress -indications logic, implemented by FPGA device. +Driver provides support for the platform management and monitoring +of DPU components. It includes support for: health events, resets and +boot progress indications logic, implemented by FPGA device. +Reviewed-by: Ciju Rajan K Signed-off-by: Vadim Pasternak +[ij: added depends on I2C] +Reviewed-by: Ilpo Järvinen +Link: https://lore.kernel.org/r/20250421092051.7687-2-vadimp@nvidia.com +Signed-off-by: Ilpo Järvinen --- - drivers/platform/mellanox/Kconfig | 12 + + drivers/platform/mellanox/Kconfig | 13 + drivers/platform/mellanox/Makefile | 1 + - drivers/platform/mellanox/mlxreg-dpu.c | 625 +++++++++++++++++++++++++ - 3 files changed, 638 insertions(+) + drivers/platform/mellanox/mlxreg-dpu.c | 611 +++++++++++++++++++++++++++++++++ + 3 files changed, 625 insertions(+) create mode 100644 drivers/platform/mellanox/mlxreg-dpu.c diff --git a/drivers/platform/mellanox/Kconfig b/drivers/platform/mellanox/Kconfig -index 6f9cb3a88d68..750c4c0905d7 100644 +index aa760f0..e3afbe6 100644 --- a/drivers/platform/mellanox/Kconfig +++ b/drivers/platform/mellanox/Kconfig -@@ -26,6 +26,18 @@ config MLX_PLATFORM +@@ -27,6 +27,19 @@ config MLX_PLATFORM If you have a Mellanox system, say Y or M here. +config MLXREG_DPU + tristate "Nvidia Data Processor Unit platform driver support" ++ depends on I2C + select REGMAP_I2C + help + This driver provides support for the Nvidia BF3 Data Processor Units, @@ -50,13 +55,13 @@ index 6f9cb3a88d68..750c4c0905d7 100644 + Centers (EDC) for building Ethernet based clusters, High-Performance + Computing (HPC) and embedded environments. + -+ If you have a Nvidia smart swicth system, say Y or M here. ++ If you have a Nvidia smart switch system, say Y or M here. + config MLXREG_HOTPLUG tristate "Mellanox platform hotplug driver support" depends on HWMON diff --git a/drivers/platform/mellanox/Makefile b/drivers/platform/mellanox/Makefile -index ba56485cbe8c..e86723b44c2e 100644 +index ba56485..e86723b 100644 --- a/drivers/platform/mellanox/Makefile +++ b/drivers/platform/mellanox/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_MLX_PLATFORM) += mlx-platform.o @@ -69,10 +74,10 @@ index ba56485cbe8c..e86723b44c2e 100644 obj-$(CONFIG_MLXREG_LC) += mlxreg-lc.o diff --git a/drivers/platform/mellanox/mlxreg-dpu.c b/drivers/platform/mellanox/mlxreg-dpu.c new file mode 100644 -index 000000000..c6cfbee55 +index 00000000..277e4b8 --- /dev/null +++ b/drivers/platform/mellanox/mlxreg-dpu.c -@@ -0,0 +1,626 @@ +@@ -0,0 +1,611 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Nvidia Data Processor Unit platform driver @@ -385,7 +390,7 @@ index 000000000..c6cfbee55 +static +struct mlxreg_core_hotplug_platform_data mlxreg_dpu_default_hotplug_data = { + .items = mlxreg_dpu_hotplug_items, -+ .counter = ARRAY_SIZE(mlxreg_dpu_hotplug_items), ++ .count = ARRAY_SIZE(mlxreg_dpu_hotplug_items), + .cell = MLXREG_DPU_REG_AGGRCO_OFFSET, + .mask = MLXREG_DPU_AGGR_MASK, +}; @@ -480,11 +485,6 @@ index 000000000..c6cfbee55 + return false; +} + -+static const struct reg_default mlxreg_dpu_regmap_default[] = { -+ { MLXREG_DPU_REG_PG_EVENT_OFFSET, 0x00 }, -+ { MLXREG_DPU_REG_HEALTH_EVENT_OFFSET, 0x00 }, -+}; -+ +/* Configuration for the register map of a device with 2 bytes address space. */ +static const struct regmap_config mlxreg_dpu_regmap_conf = { + .reg_bits = 16, @@ -494,8 +494,6 @@ index 000000000..c6cfbee55 + .writeable_reg = mlxreg_dpu_writeable_reg, + .readable_reg = mlxreg_dpu_readable_reg, + .volatile_reg = mlxreg_dpu_volatile_reg, -+ .reg_defaults = mlxreg_dpu_regmap_default, -+ .num_reg_defaults = ARRAY_SIZE(mlxreg_dpu_regmap_default), +}; + +static int @@ -511,14 +509,14 @@ index 000000000..c6cfbee55 + return -ENOMEM; + + mlxreg_dpu->hotplug_data->items = devm_kmemdup(dev, hotplug_data->items, -+ mlxreg_dpu->hotplug_data->counter * ++ mlxreg_dpu->hotplug_data->count * + sizeof(*mlxreg_dpu->hotplug_data->items), + GFP_KERNEL); + if (!mlxreg_dpu->hotplug_data->items) + return -ENOMEM; + + item = mlxreg_dpu->hotplug_data->items; -+ for (i = 0; i < hotplug_data->counter; i++, item++) { ++ for (i = 0; i < hotplug_data->count; i++, item++) { + item->data = devm_kmemdup(dev, hotplug_data->items[i].data, + hotplug_data->items[i].count * sizeof(*item->data), + GFP_KERNEL); @@ -620,7 +618,7 @@ index 000000000..c6cfbee55 + if (!mlxreg_dpu) + return -ENOMEM; + -+ /* Create device at the top of DPU I2C tree.*/ ++ /* Create device at the top of DPU I2C tree. */ + data->hpdev.client = i2c_new_client_device(data->hpdev.adapter, + data->hpdev.brdinfo); + if (IS_ERR(data->hpdev.client)) { @@ -656,33 +654,25 @@ index 000000000..c6cfbee55 + if (err) + goto mlxreg_dpu_config_init_fail; + ++ return err; ++ +mlxreg_dpu_config_init_fail: +regcache_sync_fail: +devm_regmap_init_i2c_fail: -+ if (data->hpdev.client) { -+ i2c_unregister_device(data->hpdev.client); -+ data->hpdev.client = NULL; -+ } ++ i2c_unregister_device(data->hpdev.client); +i2c_new_device_fail: + i2c_put_adapter(data->hpdev.adapter); -+ data->hpdev.adapter = NULL; + return err; +} + -+static int mlxreg_dpu_remove(struct platform_device *pdev) ++static void mlxreg_dpu_remove(struct platform_device *pdev) +{ + struct mlxreg_core_data *data = dev_get_platdata(&pdev->dev); + struct mlxreg_dpu *mlxreg_dpu = platform_get_drvdata(pdev); + + mlxreg_dpu_config_exit(mlxreg_dpu); -+ if (data->hpdev.client) { -+ i2c_unregister_device(data->hpdev.client); -+ data->hpdev.client = NULL; -+ i2c_put_adapter(data->hpdev.adapter); -+ data->hpdev.adapter = NULL; -+ } -+ -+ return 0; ++ i2c_unregister_device(data->hpdev.client); ++ i2c_put_adapter(data->hpdev.adapter); +} + +static struct platform_driver mlxreg_dpu_driver = { @@ -700,5 +690,5 @@ index 000000000..c6cfbee55 +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_ALIAS("platform:mlxreg-dpu"); -- -2.44.0 +2.8.4 diff --git a/patch/0029-pcie-if-hotplug-enabled-do-immediate-reset-on-panic.patch b/patches-sonic/0029-pcie-if-hotplug-enabled-do-immediate-reset-on-panic.patch similarity index 100% rename from patch/0029-pcie-if-hotplug-enabled-do-immediate-reset-on-panic.patch rename to patches-sonic/0029-pcie-if-hotplug-enabled-do-immediate-reset-on-panic.patch diff --git a/patches-sonic/0029-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch b/patches-sonic/0029-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch new file mode 100644 index 000000000..d4120dd54 --- /dev/null +++ b/patches-sonic/0029-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch @@ -0,0 +1,4665 @@ +From 1cc8a8a867f1a15602e1188c3a03be10b68b198e Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Mon, 21 Apr 2025 12:20:47 +0300 +Subject: [PATCH 21/70] platform: mellanox: Introduce support of Nvidia smart + switch +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Provide platform support for Nvidia Smart Switch SN4280. + +The Smart Switch equipped with: +- Nvidia COME module based on AMD EPYC™ Embedded 3451 CPU. +- Nvidia Spectrum-3 ASIC. +- Four DPUs, each equipped with Nvidia BF3 ARM based processor and + with Lattice LFD2NX-40 FPGA device. +- 28xQSFP-DD external ports. +- Two power supplies. +- Four cooling drawers. + +Reviewed-by: Ciju Rajan K +Signed-off-by: Vadim Pasternak +Reviewed-by: Ilpo Järvinen +Link: https://lore.kernel.org/r/20250421092051.7687-3-vadimp@nvidia.com +Signed-off-by: Ilpo Järvinen +--- + drivers/platform/mellanox/mlx-platform.c | 3554 +++++++++++++++------- + 1 file changed, 2485 insertions(+), 1069 deletions(-) + +diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c +index 6f24de172b90..f563a4456ce6 100644 +--- a/drivers/platform/mellanox/mlx-platform.c ++++ b/drivers/platform/mellanox/mlx-platform.c +@@ -39,6 +39,7 @@ + #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET 0x0b + #define MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET 0x17 + #define MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET 0x19 ++#define MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET 0x1b + #define MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET 0x1c + #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d + #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e +@@ -50,9 +51,11 @@ + #define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24 + #define MLXPLAT_CPLD_LPC_REG_LED6_OFFSET 0x25 + #define MLXPLAT_CPLD_LPC_REG_LED7_OFFSET 0x26 ++#define MLXPLAT_CPLD_LPC_REG_LED8_OFFSET 0x27 + #define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a + #define MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET 0x2b + #define MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET 0x2d ++#define MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET 0x2c + #define MLXPLAT_CPLD_LPC_REG_GP0_OFFSET 0x2e + #define MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET 0x2f + #define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30 +@@ -72,12 +75,14 @@ + #define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0x43 + #define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0x44 + #define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0x45 ++#define MLXPLAT_CPLD_LPC_REG_GP3_OFFSET 0x46 + #define MLXPLAT_CPLD_LPC_REG_BRD_OFFSET 0x47 + #define MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET 0x48 + #define MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET 0x49 + #define MLXPLAT_CPLD_LPC_REG_GWP_OFFSET 0x4a + #define MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET 0x4b + #define MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET 0x4c ++#define MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET 0x4e + #define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50 + #define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51 + #define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52 +@@ -89,15 +94,20 @@ + #define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58 + #define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59 + #define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a ++#define MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET 0x5e + #define MLXPLAT_CPLD_LPC_REG_PWR_OFFSET 0x64 + #define MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET 0x65 + #define MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET 0x66 ++#define MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET 0x6a + #define MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET 0x70 + #define MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET 0x71 + #define MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET 0x72 + #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88 + #define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89 + #define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a ++#define MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET 0x8b ++#define MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET 0x8c ++#define MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET 0x8d + #define MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET 0x8e + #define MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET 0x8f + #define MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET 0x90 +@@ -129,10 +139,15 @@ + #define MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET 0xaa + #define MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET 0xab + #define MLXPLAT_CPLD_LPC_REG_LC_PWR_ON 0xb2 ++#define MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET 0xb4 ++#define MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET 0xb5 + #define MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET 0xb6 + #define MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET 0xb7 + #define MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET 0xb8 + #define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET 0xb9 ++#define MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET 0xba ++#define MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET 0xbb ++#define MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET 0xc1 + #define MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET 0xc2 + #define MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT 0xc3 + #define MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET 0xc4 +@@ -183,6 +198,9 @@ + #define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb + #define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc + #define MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET 0xfd ++#define MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET 0xfe ++#define MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET 0xff ++ + #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100 + + #define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL +@@ -211,9 +229,15 @@ + #define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04 + #define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0) + #define MLXPLAT_CPLD_AGGR_MASK_LC BIT(3) ++#define MLXPLAT_CPLD_AGGR_MASK_DPU_BRD BIT(4) ++#define MLXPLAT_CPLD_AGGR_MASK_DPU_CORE BIT(5) + #define MLXPLAT_CPLD_AGGR_MASK_MODULAR (MLXPLAT_CPLD_AGGR_MASK_NG_DEF | \ + MLXPLAT_CPLD_AGGR_MASK_COMEX | \ + MLXPLAT_CPLD_AGGR_MASK_LC) ++#define MLXPLAT_CPLD_AGGR_MASK_SMART_SW (MLXPLAT_CPLD_AGGR_MASK_COMEX | \ ++ MLXPLAT_CPLD_AGGR_MASK_NG_DEF | \ ++ MLXPLAT_CPLD_AGGR_MASK_DPU_BRD | \ ++ MLXPLAT_CPLD_AGGR_MASK_DPU_CORE) + #define MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT BIT(0) + #define MLXPLAT_CPLD_AGGR_MASK_LC_RDY BIT(1) + #define MLXPLAT_CPLD_AGGR_MASK_LC_PG BIT(2) +@@ -236,15 +260,21 @@ + #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0) + #define MLXPLAT_CPLD_PSU_EXT_MASK GENMASK(3, 0) + #define MLXPLAT_CPLD_PWR_EXT_MASK GENMASK(3, 0) ++#define MLXPLAT_CPLD_PSU_XDR_MASK GENMASK(7, 0) ++#define MLXPLAT_CPLD_PWR_XDR_MASK GENMASK(7, 0) + #define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0) + #define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0) ++#define MLXPLAT_CPLD_ASIC_XDR_MASK GENMASK(3, 0) + #define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(6, 0) ++#define MLXPLAT_CPLD_FAN_XDR_MASK GENMASK(7, 0) + #define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4) + #define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0) + #define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4) + #define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0) + #define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0) + #define MLXPLAT_CPLD_FU_CAP_MASK GENMASK(1, 0) ++#define MLXPLAT_CPLD_BIOS_STATUS_MASK GENMASK(3, 1) ++#define MLXPLAT_CPLD_DPU_MASK GENMASK(3, 0) + #define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0) + #define MLXPLAT_CPLD_LATCH_RST_MASK BIT(6) + #define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3) +@@ -268,6 +298,9 @@ + /* Masks for aggregation for modular systems */ + #define MLXPLAT_CPLD_LPC_LC_MASK GENMASK(7, 0) + ++/* Masks for aggregation for smart switch systems */ ++#define MLXPLAT_CPLD_LPC_SM_SW_MASK GENMASK(7, 0) ++ + #define MLXPLAT_CPLD_HALT_MASK BIT(3) + #define MLXPLAT_CPLD_RESET_MASK GENMASK(7, 1) + +@@ -298,15 +331,18 @@ + #define MLXPLAT_CPLD_NR_NONE -1 + #define MLXPLAT_CPLD_PSU_DEFAULT_NR 10 + #define MLXPLAT_CPLD_PSU_MSNXXXX_NR 4 ++#define MLXPLAT_CPLD_PSU_XDR_NR 3 + #define MLXPLAT_CPLD_FAN1_DEFAULT_NR 11 + #define MLXPLAT_CPLD_FAN2_DEFAULT_NR 12 + #define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13 + #define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14 + #define MLXPLAT_CPLD_NR_ASIC 3 + #define MLXPLAT_CPLD_NR_LC_BASE 34 ++#define MLXPLAT_CPLD_NR_DPU_BASE 18 + + #define MLXPLAT_CPLD_NR_LC_SET(nr) (MLXPLAT_CPLD_NR_LC_BASE + (nr)) + #define MLXPLAT_CPLD_LC_ADDR 0x32 ++#define MLXPLAT_CPLD_DPU_ADDR 0x68 + + /* Masks and default values for watchdogs */ + #define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1) +@@ -321,6 +357,7 @@ + #define MLXPLAT_CPLD_WD_DFLT_TIMEOUT 30 + #define MLXPLAT_CPLD_WD3_DFLT_TIMEOUT 600 + #define MLXPLAT_CPLD_WD_MAX_DEVS 2 ++#define MLXPLAT_CPLD_DPU_MAX_DEVS 4 + + #define MLXPLAT_CPLD_LPC_SYSIRQ 17 + +@@ -347,6 +384,7 @@ + * @pdev_io_regs - register access platform devices + * @pdev_fan - FAN platform devices + * @pdev_wd - array of watchdog platform devices ++ * pdev_dpu - array of Data Processor Unit platform devices + * @regmap: device register map + * @hotplug_resources: system hotplug resources + * @hotplug_resources_size: size of system hotplug resources +@@ -362,6 +400,7 @@ struct mlxplat_priv { + struct platform_device *pdev_io_regs; + struct platform_device *pdev_fan; + struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS]; ++ struct platform_device *pdev_dpu[MLXPLAT_CPLD_DPU_MAX_DEVS]; + void *regmap; + struct resource *hotplug_resources; + unsigned int hotplug_resources_size; +@@ -631,6 +670,21 @@ static struct i2c_board_info mlxplat_mlxcpld_pwr_ng800[] = { + }, + }; + ++static struct i2c_board_info mlxplat_mlxcpld_xdr_pwr[] = { ++ { ++ I2C_BOARD_INFO("dps460", 0x5d), ++ }, ++ { ++ I2C_BOARD_INFO("dps460", 0x5c), ++ }, ++ { ++ I2C_BOARD_INFO("dps460", 0x5e), ++ }, ++ { ++ I2C_BOARD_INFO("dps460", 0x5f), ++ }, ++}; ++ + static struct i2c_board_info mlxplat_mlxcpld_fan[] = { + { + I2C_BOARD_INFO("24c32", 0x50), +@@ -2375,466 +2429,584 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_rack_switch_data = { + .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, + }; + +-/* Callback performs graceful shutdown after notification about power button event */ +-static int +-mlxplat_mlxcpld_l1_switch_pwr_events_handler(void *handle, enum mlxreg_hotplug_kind kind, +- u8 action) +-{ +- if (action) { +- dev_info(&mlxplat_dev->dev, "System shutdown due to short press of power button"); +- kernel_power_off(); +- } +- +- return 0; +-} +- +-static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_pwr_events_notifier = { +- .user_handler = mlxplat_mlxcpld_l1_switch_pwr_events_handler, +-}; +- +-/* Platform hotplug for l1 switch systems family data */ +-static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_pwr_events_items_data[] = { ++/* Platform hotplug XDR and smart switch system family data */ ++static struct mlxreg_core_data mlxplat_mlxcpld_xdr_psu_items_data[] = { + { +- .label = "power_button", +- .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, +- .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, ++ .label = "psu1", ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, ++ .mask = BIT(0), ++ .slot = 1, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, +- .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, +- .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_pwr_events_notifier, + }, +-}; +- +-/* Callback activates latch reset flow after notification about intrusion event */ +-static int +-mlxplat_mlxcpld_l1_switch_intrusion_events_handler(void *handle, enum mlxreg_hotplug_kind kind, +- u8 action) +-{ +- struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); +- u32 regval; +- int err; +- +- err = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ®val); +- if (err) +- goto fail_regmap_read; +- +- if (action) { +- dev_info(&mlxplat_dev->dev, "Detected intrusion - system latch is opened"); +- err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, +- regval | MLXPLAT_CPLD_LATCH_RST_MASK); +- } else { +- dev_info(&mlxplat_dev->dev, "System latch is properly closed"); +- err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, +- regval & ~MLXPLAT_CPLD_LATCH_RST_MASK); +- } +- +- if (err) +- goto fail_regmap_write; +- +- return 0; +- +-fail_regmap_read: +-fail_regmap_write: +- dev_err(&mlxplat_dev->dev, "Register access failed"); +- return err; +-} +- +-static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_intrusion_events_notifier = { +- .user_handler = mlxplat_mlxcpld_l1_switch_intrusion_events_handler, +-}; +- +-static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_health_events_items_data[] = { + { +- .label = "thermal1_pdb", +- .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, +- .mask = MLXPLAT_CPLD_THERMAL1_PDB_MASK, ++ .label = "psu2", ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, ++ .mask = BIT(1), ++ .slot = 2, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +- .label = "thermal2_pdb", +- .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, +- .mask = MLXPLAT_CPLD_THERMAL2_PDB_MASK, ++ .label = "psu3", ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, ++ .mask = BIT(2), ++ .slot = 3, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +- .label = "intrusion", +- .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, +- .mask = MLXPLAT_CPLD_INTRUSION_MASK, ++ .label = "psu4", ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, ++ .mask = BIT(3), ++ .slot = 4, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, +- .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, +- .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_intrusion_events_notifier, + }, + { +- .label = "pwm_pg", +- .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, +- .mask = MLXPLAT_CPLD_PWM_PG_MASK, ++ .label = "psu5", ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, ++ .mask = BIT(4), ++ .slot = 5, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, +-}; +- +-static struct mlxreg_core_item mlxplat_mlxcpld_l1_switch_events_items[] = { +- { +- .data = mlxplat_mlxcpld_default_ng_fan_items_data, +- .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, +- .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, +- .mask = MLXPLAT_CPLD_FAN_NG_MASK, +- .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), +- .inversed = 1, +- .health = false, +- }, +- { +- .data = mlxplat_mlxcpld_erot_ap_items_data, +- .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, +- .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, +- .mask = MLXPLAT_CPLD_EROT_MASK, +- .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_ap_items_data), +- .inversed = 1, +- .health = false, +- }, + { +- .data = mlxplat_mlxcpld_erot_error_items_data, +- .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, +- .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, +- .mask = MLXPLAT_CPLD_EROT_MASK, +- .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_error_items_data), +- .inversed = 1, +- .health = false, ++ .label = "psu6", ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, ++ .mask = BIT(5), ++ .slot = 6, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +- .data = mlxplat_mlxcpld_l1_switch_pwr_events_items_data, +- .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, +- .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, +- .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, +- .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_pwr_events_items_data), +- .inversed = 1, +- .health = false, ++ .label = "psu7", ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, ++ .mask = BIT(6), ++ .slot = 7, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +- .data = mlxplat_mlxcpld_l1_switch_health_events_items_data, +- .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, +- .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, +- .mask = MLXPLAT_CPLD_L1_CHA_HEALTH_MASK, +- .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_health_events_items_data), +- .inversed = 1, +- .health = false, +- .ind = 8, ++ .label = "psu8", ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, ++ .mask = BIT(7), ++ .slot = 8, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + }; + +-static +-struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_l1_switch_data = { +- .items = mlxplat_mlxcpld_l1_switch_events_items, +- .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_events_items), +- .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, +- .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, +- .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, +- .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT, +-}; +- +-/* Platform led default data */ +-static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { ++static struct mlxreg_core_data mlxplat_mlxcpld_xdr_pwr_items_data[] = { + { +- .label = "status:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .label = "pwr1", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, ++ .mask = BIT(0), ++ .slot = 1, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], ++ .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, + }, + { +- .label = "status:red", +- .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK ++ .label = "pwr2", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, ++ .mask = BIT(1), ++ .slot = 2, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], ++ .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, + }, + { +- .label = "psu:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .label = "pwr3", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, ++ .mask = BIT(2), ++ .slot = 3, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], ++ .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, + }, + { +- .label = "psu:red", +- .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .label = "pwr4", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, ++ .mask = BIT(3), ++ .slot = 4, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], ++ .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, + }, + { +- .label = "fan1:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .label = "pwr5", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, ++ .mask = BIT(4), ++ .slot = 5, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[0], ++ .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, + }, + { +- .label = "fan1:red", +- .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .label = "pwr6", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, ++ .mask = BIT(5), ++ .slot = 6, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[1], ++ .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, + }, + { +- .label = "fan2:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .label = "pwr7", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, ++ .mask = BIT(6), ++ .slot = 7, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[2], ++ .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, + }, + { +- .label = "fan2:red", +- .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .label = "pwr8", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, ++ .mask = BIT(7), ++ .slot = 8, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[3], ++ .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, + }, ++}; ++ ++static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_items_data[] = { + { +- .label = "fan3:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .label = "fan1", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ .mask = BIT(0), ++ .slot = 1, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(0), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +- .label = "fan3:red", +- .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .label = "fan2", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ .mask = BIT(1), ++ .slot = 2, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(1), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +- .label = "fan4:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .label = "fan3", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ .mask = BIT(2), ++ .slot = 3, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(2), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +- .label = "fan4:red", +- .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .label = "fan4", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ .mask = BIT(3), ++ .slot = 4, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(3), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, +-}; +- +-static struct mlxreg_core_platform_data mlxplat_default_led_data = { +- .data = mlxplat_mlxcpld_default_led_data, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_data), +-}; +- +-/* Platform led default data for water cooling */ +-static struct mlxreg_core_data mlxplat_mlxcpld_default_led_wc_data[] = { + { +- .label = "status:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .label = "fan5", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ .mask = BIT(4), ++ .slot = 5, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(4), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +- .label = "status:red", +- .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK ++ .label = "fan6", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ .mask = BIT(5), ++ .slot = 6, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(5), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +- .label = "psu:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .label = "fan7", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ .mask = BIT(6), ++ .slot = 7, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(6), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +- .label = "psu:red", +- .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .label = "fan8", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ .mask = BIT(7), ++ .slot = 8, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(7), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + }; + +-static struct mlxreg_core_platform_data mlxplat_default_led_wc_data = { +- .data = mlxplat_mlxcpld_default_led_wc_data, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_wc_data), ++static struct mlxreg_core_data mlxplat_mlxcpld_xdr_asic1_items_data[] = { ++ { ++ .label = "asic1", ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_MASK, ++ .slot = 1, ++ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ } + }; + +-/* Platform led default data for water cooling Ethernet switch blade */ +-static struct mlxreg_core_data mlxplat_mlxcpld_default_led_eth_wc_blade_data[] = { ++/* Platform hotplug for smart switch systems families data */ ++static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_dpu_ready_data[] = { + { +- .label = "status:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .label = "dpu1_ready", ++ .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, ++ .mask = BIT(0), ++ .slot = 1, ++ .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +- .label = "status:red", +- .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK ++ .label = "dpu2_ready", ++ .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, ++ .mask = BIT(1), ++ .slot = 2, ++ .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "dpu3_ready", ++ .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, ++ .mask = BIT(2), ++ .slot = 3, ++ .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "dpu4_ready", ++ .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, ++ .mask = BIT(3), ++ .slot = 4, ++ .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + }; + +-static struct mlxreg_core_platform_data mlxplat_default_led_eth_wc_blade_data = { +- .data = mlxplat_mlxcpld_default_led_eth_wc_blade_data, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_eth_wc_blade_data), +-}; +- +-/* Platform led MSN21xx system family data */ +-static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_led_data[] = { ++static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_dpu_shtdn_ready_data[] = { + { +- .label = "status:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .label = "dpu1_shtdn_ready", ++ .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, ++ .mask = BIT(0), ++ .slot = 1, ++ .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +- .label = "status:red", +- .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK ++ .label = "dpu2_shtdn_ready", ++ .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, ++ .mask = BIT(1), ++ .slot = 2, ++ .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +- .label = "fan:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .label = "dpu3_shtdn_ready", ++ .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, ++ .mask = BIT(2), ++ .slot = 3, ++ .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +- .label = "fan:red", +- .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .label = "dpu4_shtdn_ready", ++ .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, ++ .mask = BIT(3), ++ .slot = 4, ++ .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, ++}; ++ ++static struct mlxreg_core_item mlxplat_mlxcpld_smart_switch_items[] = { + { +- .label = "psu1:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .data = mlxplat_mlxcpld_xdr_psu_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, ++ .mask = MLXPLAT_CPLD_PSU_XDR_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_psu_items_data), ++ .inversed = 1, ++ .health = false, + }, + { +- .label = "psu1:red", +- .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .data = mlxplat_mlxcpld_xdr_pwr_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, ++ .mask = MLXPLAT_CPLD_PWR_XDR_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_pwr_items_data), ++ .inversed = 0, ++ .health = false, + }, + { +- .label = "psu2:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .data = mlxplat_mlxcpld_xdr_fan_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ .mask = MLXPLAT_CPLD_FAN_XDR_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_items_data), ++ .inversed = 1, ++ .health = false, + }, + { +- .label = "psu2:red", +- .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .data = mlxplat_mlxcpld_xdr_asic1_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_XDR_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_asic1_items_data), ++ .inversed = 0, ++ .health = true, + }, + { +- .label = "uid:blue", +- .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .data = mlxplat_mlxcpld_smart_switch_dpu_ready_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_DPU_CORE, ++ .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, ++ .mask = MLXPLAT_CPLD_DPU_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_dpu_ready_data), ++ .inversed = 1, ++ .health = false, ++ }, ++ { ++ .data = mlxplat_mlxcpld_smart_switch_dpu_shtdn_ready_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_DPU_CORE, ++ .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, ++ .mask = MLXPLAT_CPLD_DPU_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_dpu_shtdn_ready_data), ++ .inversed = 1, ++ .health = false, + }, + }; + +-static struct mlxreg_core_platform_data mlxplat_msn21xx_led_data = { +- .data = mlxplat_mlxcpld_msn21xx_led_data, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_led_data), ++static ++struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_smart_switch_data = { ++ .items = mlxplat_mlxcpld_smart_switch_items, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_items), ++ .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, ++ .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX | ++ MLXPLAT_CPLD_AGGR_MASK_DPU_BRD | MLXPLAT_CPLD_AGGR_MASK_DPU_CORE, ++ .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, ++ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, + }; + +-/* Platform led for default data for 200GbE systems */ +-static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = { ++/* Smart switch data processor units data */ ++static struct i2c_board_info mlxplat_mlxcpld_smart_switch_dpu_devs[] = { + { +- .label = "status:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR), ++ .irq = MLXPLAT_CPLD_LPC_SYSIRQ, + }, + { +- .label = "status:orange", +- .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK ++ I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR), ++ .irq = MLXPLAT_CPLD_LPC_SYSIRQ, + }, + { +- .label = "psu:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR), ++ .irq = MLXPLAT_CPLD_LPC_SYSIRQ, + }, + { +- .label = "psu:orange", +- .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR), ++ .irq = MLXPLAT_CPLD_LPC_SYSIRQ, + }, ++}; ++ ++static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_dpu_data[] = { + { +- .label = "fan1:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, +- .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(0), ++ .label = "dpu1", ++ .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[0], ++ .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE, ++ .slot = 1, + }, + { +- .label = "fan1:orange", +- .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, +- .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(0), ++ .label = "dpu2", ++ .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[1], ++ .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE + 1, ++ .slot = 2, + }, + { +- .label = "fan2:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, +- .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(1), ++ .label = "dpu3", ++ .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[2], ++ .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE + 2, ++ .slot = 3, + }, + { +- .label = "fan2:orange", +- .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, +- .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(1), +- }, +- { +- .label = "fan3:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, +- .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(2), ++ .label = "dpu4", ++ .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[3], ++ .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE + 3, ++ .slot = 4, + }, ++}; ++ ++/* Callback performs graceful shutdown after notification about power button event */ ++static int ++mlxplat_mlxcpld_l1_switch_pwr_events_handler(void *handle, enum mlxreg_hotplug_kind kind, ++ u8 action) ++{ ++ if (action) { ++ dev_info(&mlxplat_dev->dev, "System shutdown due to short press of power button"); ++ kernel_power_off(); ++ } ++ ++ return 0; ++} ++ ++static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_pwr_events_notifier = { ++ .user_handler = mlxplat_mlxcpld_l1_switch_pwr_events_handler, ++}; ++ ++/* Platform hotplug for l1 switch systems family data */ ++static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_pwr_events_items_data[] = { + { +- .label = "fan3:orange", +- .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, +- .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(2), ++ .label = "power_button", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, ++ .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, ++ .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_pwr_events_notifier, + }, ++}; ++ ++/* Callback activates latch reset flow after notification about intrusion event */ ++static int ++mlxplat_mlxcpld_l1_switch_intrusion_events_handler(void *handle, enum mlxreg_hotplug_kind kind, ++ u8 action) ++{ ++ struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); ++ u32 regval; ++ int err; ++ ++ err = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ®val); ++ if (err) ++ goto fail_regmap_read; ++ ++ if (action) { ++ dev_info(&mlxplat_dev->dev, "Detected intrusion - system latch is opened"); ++ err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ regval | MLXPLAT_CPLD_LATCH_RST_MASK); ++ } else { ++ dev_info(&mlxplat_dev->dev, "System latch is properly closed"); ++ err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ regval & ~MLXPLAT_CPLD_LATCH_RST_MASK); ++ } ++ ++ if (err) ++ goto fail_regmap_write; ++ ++ return 0; ++ ++fail_regmap_read: ++fail_regmap_write: ++ dev_err(&mlxplat_dev->dev, "Register access failed"); ++ return err; ++} ++ ++static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_intrusion_events_notifier = { ++ .user_handler = mlxplat_mlxcpld_l1_switch_intrusion_events_handler, ++}; ++ ++static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_health_events_items_data[] = { + { +- .label = "fan4:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, +- .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(3), ++ .label = "thermal1_pdb", ++ .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, ++ .mask = MLXPLAT_CPLD_THERMAL1_PDB_MASK, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +- .label = "fan4:orange", +- .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, +- .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(3), ++ .label = "thermal2_pdb", ++ .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, ++ .mask = MLXPLAT_CPLD_THERMAL2_PDB_MASK, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +- .label = "fan5:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, +- .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(4), ++ .label = "intrusion", ++ .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, ++ .mask = MLXPLAT_CPLD_INTRUSION_MASK, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, ++ .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_intrusion_events_notifier, + }, + { +- .label = "fan5:orange", +- .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, +- .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(4), ++ .label = "pwm_pg", ++ .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, ++ .mask = MLXPLAT_CPLD_PWM_PG_MASK, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, ++}; ++ ++static struct mlxreg_core_item mlxplat_mlxcpld_l1_switch_events_items[] = { + { +- .label = "fan6:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, +- .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(5), ++ .data = mlxplat_mlxcpld_default_ng_fan_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ .mask = MLXPLAT_CPLD_FAN_NG_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), ++ .inversed = 1, ++ .health = false, + }, + { +- .label = "fan6:orange", +- .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, +- .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(5), ++ .data = mlxplat_mlxcpld_erot_ap_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, ++ .mask = MLXPLAT_CPLD_EROT_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_ap_items_data), ++ .inversed = 1, ++ .health = false, + }, + { +- .label = "fan7:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, +- .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(6), ++ .data = mlxplat_mlxcpld_erot_error_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, ++ .mask = MLXPLAT_CPLD_EROT_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_error_items_data), ++ .inversed = 1, ++ .health = false, + }, + { +- .label = "fan7:orange", +- .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, +- .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(6), ++ .data = mlxplat_mlxcpld_l1_switch_pwr_events_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, ++ .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_pwr_events_items_data), ++ .inversed = 1, ++ .health = false, + }, + { +- .label = "uid:blue", +- .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .data = mlxplat_mlxcpld_l1_switch_health_events_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, ++ .mask = MLXPLAT_CPLD_L1_CHA_HEALTH_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_health_events_items_data), ++ .inversed = 1, ++ .health = false, ++ .ind = 8, + }, + }; + +-static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = { +- .data = mlxplat_mlxcpld_default_ng_led_data, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data), ++static ++struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_l1_switch_data = { ++ .items = mlxplat_mlxcpld_l1_switch_events_items, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_events_items), ++ .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, ++ .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, ++ .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, ++ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT, + }; + +-/* Platform led for Comex based 100GbE systems */ +-static struct mlxreg_core_data mlxplat_mlxcpld_comex_100G_led_data[] = { ++/* Platform led default data */ ++static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { + { + .label = "status:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, +@@ -2895,27 +3067,22 @@ static struct mlxreg_core_data mlxplat_mlxcpld_comex_100G_led_data[] = { + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, +- { +- .label = "uid:blue", +- .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, +- }, + }; + +-static struct mlxreg_core_platform_data mlxplat_comex_100G_led_data = { +- .data = mlxplat_mlxcpld_comex_100G_led_data, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_100G_led_data), ++static struct mlxreg_core_platform_data mlxplat_default_led_data = { ++ .data = mlxplat_mlxcpld_default_led_data, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_data), + }; + +-/* Platform led for data for modular systems */ +-static struct mlxreg_core_data mlxplat_mlxcpld_modular_led_data[] = { ++/* Platform led default data for water cooling */ ++static struct mlxreg_core_data mlxplat_mlxcpld_default_led_wc_data[] = { + { + .label = "status:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { +- .label = "status:orange", ++ .label = "status:red", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK + }, +@@ -2925,36 +3092,138 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_led_data[] = { + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { +- .label = "psu:orange", ++ .label = "psu:red", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, ++}; ++ ++static struct mlxreg_core_platform_data mlxplat_default_led_wc_data = { ++ .data = mlxplat_mlxcpld_default_led_wc_data, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_wc_data), ++}; ++ ++/* Platform led default data for water cooling Ethernet switch blade */ ++static struct mlxreg_core_data mlxplat_mlxcpld_default_led_eth_wc_blade_data[] = { + { +- .label = "fan1:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, ++ .label = "status:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, +- .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(0), + }, + { +- .label = "fan1:orange", +- .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, ++ .label = "status:red", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK ++ }, ++}; ++ ++static struct mlxreg_core_platform_data mlxplat_default_led_eth_wc_blade_data = { ++ .data = mlxplat_mlxcpld_default_led_eth_wc_blade_data, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_eth_wc_blade_data), ++}; ++ ++/* Platform led MSN21xx system family data */ ++static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_led_data[] = { ++ { ++ .label = "status:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, +- .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(0), + }, + { +- .label = "fan2:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, +- .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(1), ++ .label = "status:red", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK + }, + { +- .label = "fan2:orange", ++ .label = "fan:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, +- .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, +- .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "fan:red", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "psu1:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "psu1:red", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "psu2:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "psu2:red", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "uid:blue", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data mlxplat_msn21xx_led_data = { ++ .data = mlxplat_mlxcpld_msn21xx_led_data, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_led_data), ++}; ++ ++/* Platform led for default data for 200GbE systems */ ++static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = { ++ { ++ .label = "status:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "status:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK ++ }, ++ { ++ .label = "psu:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "psu:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "fan1:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(0), ++ }, ++ { ++ .label = "fan1:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(0), ++ }, ++ { ++ .label = "fan2:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(1), ++ }, ++ { ++ .label = "fan2:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(1), + }, + { +@@ -3016,14 +3285,14 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_led_data[] = { + { + .label = "fan7:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(6), + }, + { + .label = "fan7:orange", + .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + .bit = BIT(6), + }, +@@ -3032,35 +3301,89 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_led_data[] = { + .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, ++}; ++ ++static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = { ++ .data = mlxplat_mlxcpld_default_ng_led_data, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data), ++}; ++ ++/* Platform led for Comex based 100GbE systems */ ++static struct mlxreg_core_data mlxplat_mlxcpld_comex_100G_led_data[] = { + { +- .label = "fan_front:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, ++ .label = "status:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { +- .label = "fan_front:orange", +- .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, ++ .label = "status:red", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK ++ }, ++ { ++ .label = "psu:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "psu:red", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "fan1:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { +- .label = "mgmt:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, ++ .label = "fan1:red", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { +- .label = "mgmt:orange", +- .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, ++ .label = "fan2:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "fan2:red", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "fan3:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "fan3:red", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "fan4:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "fan4:red", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "uid:blue", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + }; + +-static struct mlxreg_core_platform_data mlxplat_modular_led_data = { +- .data = mlxplat_mlxcpld_modular_led_data, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_led_data), ++static struct mlxreg_core_platform_data mlxplat_comex_100G_led_data = { ++ .data = mlxplat_mlxcpld_comex_100G_led_data, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_100G_led_data), + }; + +-/* Platform led data for chassis system */ +-static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_led_data[] = { ++/* Platform led for data for modular systems */ ++static struct mlxreg_core_data mlxplat_mlxcpld_modular_led_data[] = { + { + .label = "status:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, +@@ -3071,6 +3394,16 @@ static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_led_data[] = { + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK + }, ++ { ++ .label = "psu:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "psu:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ }, + { + .label = "fan1:green", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, +@@ -3156,102 +3489,862 @@ static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_led_data[] = { + .bit = BIT(5), + }, + { +- .label = "uid:blue", +- .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .label = "fan7:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(6), ++ }, ++ { ++ .label = "fan7:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(6), ++ }, ++ { ++ .label = "uid:blue", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "fan_front:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "fan_front:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "mgmt:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "mgmt:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data mlxplat_modular_led_data = { ++ .data = mlxplat_mlxcpld_modular_led_data, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_led_data), ++}; ++ ++/* Platform led data for chassis system */ ++static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_led_data[] = { ++ { ++ .label = "status:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "status:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK ++ }, ++ { ++ .label = "fan1:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(0), ++ }, ++ { ++ .label = "fan1:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(0), ++ }, ++ { ++ .label = "fan2:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(1), ++ }, ++ { ++ .label = "fan2:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(1), ++ }, ++ { ++ .label = "fan3:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(2), ++ }, ++ { ++ .label = "fan3:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(2), ++ }, ++ { ++ .label = "fan4:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(3), ++ }, ++ { ++ .label = "fan4:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(3), ++ }, ++ { ++ .label = "fan5:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(4), ++ }, ++ { ++ .label = "fan5:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(4), ++ }, ++ { ++ .label = "fan6:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(5), ++ }, ++ { ++ .label = "fan6:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(5), ++ }, ++ { ++ .label = "uid:blue", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data mlxplat_l1_switch_led_data = { ++ .data = mlxplat_mlxcpld_l1_switch_led_data, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_led_data), ++}; ++ ++/* Platform led data for XDR and smart switch systems */ ++static struct mlxreg_core_data mlxplat_mlxcpld_xdr_led_data[] = { ++ { ++ .label = "status:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "status:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "psu:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "psu:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "fan1:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 1, ++ }, ++ { ++ .label = "fan1:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 1, ++ }, ++ { ++ .label = "fan2:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 2, ++ }, ++ { ++ .label = "fan2:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 2, ++ }, ++ { ++ .label = "fan3:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 3, ++ }, ++ { ++ .label = "fan3:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 3, ++ }, ++ { ++ .label = "fan4:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 4, ++ }, ++ { ++ .label = "fan4:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 4, ++ }, ++ { ++ .label = "fan5:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 5, ++ }, ++ { ++ .label = "fan5:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 5, ++ }, ++ { ++ .label = "fan6:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 6, ++ }, ++ { ++ .label = "fan6:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 6, ++ }, ++ { ++ .label = "fan7:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 7, ++ }, ++ { ++ .label = "fan7:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 7, ++ }, ++ { ++ .label = "fan8:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 8, ++ }, ++ { ++ .label = "fan8:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 8, ++ }, ++ { ++ .label = "fan9:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 9, ++ }, ++ { ++ .label = "fan9:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 9, ++ }, ++ { ++ .label = "fan10:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED8_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 10, ++ }, ++ { ++ .label = "fan10:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED8_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 10, ++ }, ++ { ++ .label = "uid:blue", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data mlxplat_xdr_led_data = { ++ .data = mlxplat_mlxcpld_xdr_led_data, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_xdr_led_data), ++}; ++ ++/* Platform register access default */ ++static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = { ++ { ++ .label = "cpld1_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld2_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld1_pn", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld2_pn", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld1_version_min", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld2_version_min", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_long_pb", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_short_pb", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_aux_pwr_or_ref", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_main_pwr_fail", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_sw_reset", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_fw_reset", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_hotswap_or_wd", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_asic_thermal", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "psu1_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0200, ++ }, ++ { ++ .label = "psu2_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0200, ++ }, ++ { ++ .label = "pwr_cycle", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0200, ++ }, ++ { ++ .label = "pwr_down", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0200, ++ }, ++ { ++ .label = "select_iio", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "asic_health", ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data mlxplat_default_regs_io_data = { ++ .data = mlxplat_mlxcpld_default_regs_io_data, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data), ++}; ++ ++/* Platform register access MSN21xx, MSN201x, MSN274x systems families data */ ++static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = { ++ { ++ .label = "cpld1_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld2_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld1_pn", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld2_pn", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld1_version_min", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld2_version_min", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_long_pb", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_short_pb", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_aux_pwr_or_ref", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_sw_reset", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_main_pwr_fail", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_asic_thermal", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_hotswap_or_halt", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_sff_wd", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, ++ }, ++ { ++ .label = "psu1_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0200, ++ }, ++ { ++ .label = "psu2_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0200, ++ }, ++ { ++ .label = "pwr_cycle", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0200, ++ }, ++ { ++ .label = "pwr_down", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0200, ++ }, ++ { ++ .label = "select_iio", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "asic_health", ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data mlxplat_msn21xx_regs_io_data = { ++ .data = mlxplat_mlxcpld_msn21xx_regs_io_data, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data), ++}; ++ ++/* Platform register access for next generation systems families data */ ++static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { ++ { ++ .label = "cpld1_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld2_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld3_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld4_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld5_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld1_pn", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld2_pn", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld3_pn", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld4_pn", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld5_pn", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld1_version_min", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld2_version_min", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld3_version_min", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld4_version_min", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld5_version_min", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "asic_reset", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0200, ++ }, ++ { ++ .label = "asic2_reset", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0200, ++ }, ++ { ++ .label = "erot1_reset", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "erot2_reset", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0644, ++ }, ++ { ++ .label = "clk_brd_prog_en", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0644, ++ .secured = 1, ++ }, ++ { ++ .label = "erot1_recovery", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "erot2_recovery", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0644, ++ }, ++ { ++ .label = "erot1_wp", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, ++ .secured = 1, ++ }, ++ { ++ .label = "erot2_wp", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, ++ .secured = 1, ++ }, ++ { ++ .label = "reset_long_pb", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_short_pb", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_aux_pwr_or_ref", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_swb_dc_dc_pwr_fail", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_from_asic", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_swb_wd", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, + }, +-}; +- +-static struct mlxreg_core_platform_data mlxplat_l1_switch_led_data = { +- .data = mlxplat_mlxcpld_l1_switch_led_data, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_led_data), +-}; +- +-/* Platform register access default */ +-static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = { + { +- .label = "cpld1_version", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, +- .bit = GENMASK(7, 0), ++ .label = "reset_asic_thermal", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, + }, + { +- .label = "cpld2_version", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, +- .bit = GENMASK(7, 0), ++ .label = "reset_sw_reset", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0444, + }, + { +- .label = "cpld1_pn", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, +- .bit = GENMASK(15, 0), ++ .label = "reset_comex_pwr_fail", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0444, +- .regnum = 2, + }, + { +- .label = "cpld2_pn", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, +- .bit = GENMASK(15, 0), ++ .label = "reset_platform", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0444, +- .regnum = 2, + }, + { +- .label = "cpld1_version_min", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, +- .bit = GENMASK(7, 0), ++ .label = "reset_soc", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, + }, + { +- .label = "cpld2_version_min", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, +- .bit = GENMASK(7, 0), ++ .label = "reset_comex_wd", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0444, + }, + { +- .label = "reset_long_pb", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .label = "reset_pwr_converter_fail", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0444, + }, + { +- .label = "reset_short_pb", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .label = "reset_system", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0444, + }, + { +- .label = "reset_aux_pwr_or_ref", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .label = "reset_sw_pwr_off", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0444, + }, + { +- .label = "reset_main_pwr_fail", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .label = "reset_comex_thermal", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0444, + }, + { +- .label = "reset_sw_reset", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(4), +- .mode = 0444, +- }, +- { +- .label = "reset_fw_reset", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .label = "reset_reload_bios", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, + }, + { +- .label = "reset_hotswap_or_wd", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .label = "reset_ac_pwr_fail", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0444, + }, + { +- .label = "reset_asic_thermal", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .label = "reset_ac_ok_fail", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, + }, +@@ -3280,9 +4373,52 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = { + .mode = 0200, + }, + { +- .label = "select_iio", +- .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, ++ .label = "deep_pwr_cycle", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0200, ++ }, ++ { ++ .label = "latch_reset", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0200, ++ }, ++ { ++ .label = "jtag_cap", ++ .reg = MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET, ++ .mask = MLXPLAT_CPLD_FU_CAP_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "jtag_enable", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, ++ }, ++ { ++ .label = "dbg1", ++ .reg = MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0644, ++ }, ++ { ++ .label = "dbg2", ++ .reg = MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0644, ++ }, ++ { ++ .label = "dbg3", ++ .reg = MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0644, ++ }, ++ { ++ .label = "dbg4", ++ .reg = MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET, ++ .bit = GENMASK(7, 0), + .mode = 0644, + }, + { +@@ -3292,147 +4428,151 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = { + .bit = 1, + .mode = 0444, + }, +-}; +- +-static struct mlxreg_core_platform_data mlxplat_default_regs_io_data = { +- .data = mlxplat_mlxcpld_default_regs_io_data, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data), +-}; +- +-/* Platform register access MSN21xx, MSN201x, MSN274x systems families data */ +-static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = { + { +- .label = "cpld1_version", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, +- .bit = GENMASK(7, 0), ++ .label = "asic2_health", ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_MASK, ++ .bit = 1, + .mode = 0444, + }, + { +- .label = "cpld2_version", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, ++ .label = "fan_dir", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { +- .label = "cpld1_pn", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, +- .bit = GENMASK(15, 0), ++ .label = "bios_safe_mode", ++ .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0444, +- .regnum = 2, + }, + { +- .label = "cpld2_pn", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, +- .bit = GENMASK(15, 0), ++ .label = "bios_active_image", ++ .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, +- .regnum = 2, + }, + { +- .label = "cpld1_version_min", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, +- .bit = GENMASK(7, 0), ++ .label = "bios_auth_fail", ++ .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0444, + }, + { +- .label = "cpld2_version_min", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, +- .bit = GENMASK(7, 0), ++ .label = "bios_upgrade_fail", ++ .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, + }, + { +- .label = "reset_long_pb", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(0), ++ .label = "voltreg_update_status", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, ++ .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, ++ .bit = 5, + .mode = 0444, + }, + { +- .label = "reset_short_pb", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(1), ++ .label = "pwr_converter_prog_en", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0644, ++ .secured = 1, ++ }, ++ { ++ .label = "vpd_wp", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ }, ++ { ++ .label = "pcie_asic_reset_dis", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, ++ }, ++ { ++ .label = "erot1_ap_reset", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0444, + }, + { +- .label = "reset_aux_pwr_or_ref", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(2), ++ .label = "erot2_ap_reset", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0444, + }, + { +- .label = "reset_sw_reset", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(3), ++ .label = "lid_open", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0444, + }, + { +- .label = "reset_main_pwr_fail", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .label = "clk_brd1_boot_fail", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0444, + }, + { +- .label = "reset_asic_thermal", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .label = "clk_brd2_boot_fail", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, + }, + { +- .label = "reset_hotswap_or_halt", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .label = "clk_brd_fail", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0444, + }, + { +- .label = "reset_sff_wd", +- .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(6), ++ .label = "asic_pg_fail", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, + }, + { +- .label = "psu1_on", +- .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(0), +- .mode = 0200, +- }, +- { +- .label = "psu2_on", +- .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(1), +- .mode = 0200, ++ .label = "spi_chnl_select", ++ .reg = MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT, ++ .mask = GENMASK(7, 0), ++ .bit = 1, ++ .mode = 0644, + }, + { +- .label = "pwr_cycle", +- .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(2), +- .mode = 0200, ++ .label = "config1", ++ .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { +- .label = "pwr_down", +- .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(3), +- .mode = 0200, ++ .label = "config2", ++ .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { +- .label = "select_iio", +- .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(6), +- .mode = 0644, ++ .label = "config3", ++ .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { +- .label = "asic_health", +- .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, +- .mask = MLXPLAT_CPLD_ASIC_MASK, +- .bit = 1, ++ .label = "ufm_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, ++ .bit = GENMASK(7, 0), + .mode = 0444, + }, + }; + +-static struct mlxreg_core_platform_data mlxplat_msn21xx_regs_io_data = { +- .data = mlxplat_mlxcpld_msn21xx_regs_io_data, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data), ++static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = { ++ .data = mlxplat_mlxcpld_default_ng_regs_io_data, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data), + }; + +-/* Platform register access for next generation systems families data */ +-static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { ++/* Platform register access for modular systems families data */ ++static struct mlxreg_core_data mlxplat_mlxcpld_modular_regs_io_data[] = { + { + .label = "cpld1_version", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, +@@ -3457,12 +4597,6 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .bit = GENMASK(7, 0), + .mode = 0444, + }, +- { +- .label = "cpld5_version", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET, +- .bit = GENMASK(7, 0), +- .mode = 0444, +- }, + { + .label = "cpld1_pn", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, +@@ -3491,13 +4625,6 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .mode = 0444, + .regnum = 2, + }, +- { +- .label = "cpld5_pn", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET, +- .bit = GENMASK(15, 0), +- .mode = 0444, +- .regnum = 2, +- }, + { + .label = "cpld1_version_min", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, +@@ -3523,68 +4650,53 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .mode = 0444, + }, + { +- .label = "cpld5_version_min", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET, +- .bit = GENMASK(7, 0), +- .mode = 0444, ++ .label = "lc1_enable", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0644, + }, + { +- .label = "asic_reset", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(3), +- .mode = 0200, ++ .label = "lc2_enable", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0644, + }, + { +- .label = "asic2_reset", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, ++ .label = "lc3_enable", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), +- .mode = 0200, ++ .mode = 0644, + }, + { +- .label = "erot1_reset", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(6), ++ .label = "lc4_enable", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0644, + }, + { +- .label = "erot2_reset", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(7), ++ .label = "lc5_enable", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0644, + }, + { +- .label = "clk_brd_prog_en", +- .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(1), ++ .label = "lc6_enable", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0644, +- .secured = 1, + }, + { +- .label = "erot1_recovery", +- .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, ++ .label = "lc7_enable", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0644, + }, + { +- .label = "erot2_recovery", +- .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, ++ .label = "lc8_enable", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0644, + }, +- { +- .label = "erot1_wp", +- .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(4), +- .mode = 0644, +- .secured = 1, +- }, +- { +- .label = "erot2_wp", +- .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(5), +- .mode = 0644, +- .secured = 1, +- }, + { + .label = "reset_long_pb", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, +@@ -3598,39 +4710,33 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .mode = 0444, + }, + { +- .label = "reset_aux_pwr_or_ref", ++ .label = "reset_aux_pwr_or_fu", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0444, + }, + { +- .label = "reset_swb_dc_dc_pwr_fail", ++ .label = "reset_mgmt_dc_dc_pwr_fail", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0444, + }, + { +- .label = "reset_from_asic", ++ .label = "reset_sys_comex_bios", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, + }, + { +- .label = "reset_swb_wd", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(6), +- .mode = 0444, +- }, +- { +- .label = "reset_asic_thermal", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(7), ++ .label = "reset_sw_reset", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0444, + }, + { +- .label = "reset_sw_reset", ++ .label = "reset_aux_pwr_or_reload", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(0), ++ .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0444, + }, + { +@@ -3652,144 +4758,45 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .mode = 0444, + }, + { +- .label = "reset_comex_wd", ++ .label = "reset_pwr_off_from_carrier", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(6), ++ .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, + }, + { +- .label = "reset_pwr_converter_fail", ++ .label = "reset_swb_wd", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0444, + }, + { +- .label = "reset_system", +- .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(1), +- .mode = 0444, +- }, +- { +- .label = "reset_sw_pwr_off", +- .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, ++ .label = "reset_swb_aux_pwr_or_fu", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0444, + }, + { +- .label = "reset_comex_thermal", +- .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(3), +- .mode = 0444, +- }, +- { +- .label = "reset_reload_bios", +- .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(5), +- .mode = 0444, +- }, +- { +- .label = "reset_ac_pwr_fail", +- .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(6), +- .mode = 0444, +- }, +- { +- .label = "reset_ac_ok_fail", ++ .label = "reset_swb_dc_dc_pwr_fail", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(7), +- .mode = 0444, +- }, +- { +- .label = "psu1_on", +- .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(0), +- .mode = 0200, +- }, +- { +- .label = "psu2_on", +- .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(1), +- .mode = 0200, +- }, +- { +- .label = "pwr_cycle", +- .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(2), +- .mode = 0200, +- }, +- { +- .label = "pwr_down", +- .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), +- .mode = 0200, +- }, +- { +- .label = "deep_pwr_cycle", +- .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(5), +- .mode = 0200, +- }, +- { +- .label = "latch_reset", +- .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(6), +- .mode = 0200, +- }, +- { +- .label = "jtag_cap", +- .reg = MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET, +- .mask = MLXPLAT_CPLD_FU_CAP_MASK, +- .bit = 1, + .mode = 0444, + }, + { +- .label = "jtag_enable", +- .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(4), +- .mode = 0644, +- }, +- { +- .label = "dbg1", +- .reg = MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET, +- .bit = GENMASK(7, 0), +- .mode = 0644, +- }, +- { +- .label = "dbg2", +- .reg = MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET, +- .bit = GENMASK(7, 0), +- .mode = 0644, +- }, +- { +- .label = "dbg3", +- .reg = MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET, +- .bit = GENMASK(7, 0), +- .mode = 0644, +- }, +- { +- .label = "dbg4", +- .reg = MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET, +- .bit = GENMASK(7, 0), +- .mode = 0644, +- }, +- { +- .label = "asic_health", +- .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, +- .mask = MLXPLAT_CPLD_ASIC_MASK, +- .bit = 1, ++ .label = "reset_swb_12v_fail", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0444, + }, + { +- .label = "asic2_health", +- .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, +- .mask = MLXPLAT_CPLD_ASIC_MASK, +- .bit = 1, ++ .label = "reset_system", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, + }, + { +- .label = "fan_dir", +- .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, +- .bit = GENMASK(7, 0), ++ .label = "reset_thermal_spc_or_pciesw", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, + }, + { +@@ -3823,13 +4830,6 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .bit = 5, + .mode = 0444, + }, +- { +- .label = "pwr_converter_prog_en", +- .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(0), +- .mode = 0644, +- .secured = 1, +- }, + { + .label = "vpd_wp", + .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, +@@ -3843,251 +4843,249 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .mode = 0644, + }, + { +- .label = "erot1_ap_reset", +- .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, ++ .label = "shutdown_unlock", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, ++ }, ++ { ++ .label = "lc1_rst_mask", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), +- .mode = 0444, ++ .mode = 0200, + }, + { +- .label = "erot2_ap_reset", +- .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, ++ .label = "lc2_rst_mask", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), +- .mode = 0444, ++ .mode = 0200, + }, + { +- .label = "lid_open", +- .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, ++ .label = "lc3_rst_mask", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), +- .mode = 0444, ++ .mode = 0200, + }, + { +- .label = "clk_brd1_boot_fail", +- .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, ++ .label = "lc4_rst_mask", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0200, ++ }, ++ { ++ .label = "lc5_rst_mask", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(4), +- .mode = 0444, ++ .mode = 0200, + }, + { +- .label = "clk_brd2_boot_fail", +- .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, ++ .label = "lc6_rst_mask", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), +- .mode = 0444, ++ .mode = 0200, + }, + { +- .label = "clk_brd_fail", +- .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, ++ .label = "lc7_rst_mask", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(6), +- .mode = 0444, ++ .mode = 0200, + }, + { +- .label = "asic_pg_fail", +- .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, ++ .label = "lc8_rst_mask", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), +- .mode = 0444, +- }, +- { +- .label = "spi_chnl_select", +- .reg = MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT, +- .mask = GENMASK(7, 0), +- .bit = 1, +- .mode = 0644, +- }, +- { +- .label = "config1", +- .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, +- .bit = GENMASK(7, 0), +- .mode = 0444, +- }, +- { +- .label = "config2", +- .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, +- .bit = GENMASK(7, 0), +- .mode = 0444, +- }, +- { +- .label = "config3", +- .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, +- .bit = GENMASK(7, 0), +- .mode = 0444, ++ .mode = 0200, + }, + { +- .label = "ufm_version", +- .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, +- .bit = GENMASK(7, 0), +- .mode = 0444, ++ .label = "psu1_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0200, + }, +-}; +- +-static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = { +- .data = mlxplat_mlxcpld_default_ng_regs_io_data, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data), +-}; +- +-/* Platform register access for modular systems families data */ +-static struct mlxreg_core_data mlxplat_mlxcpld_modular_regs_io_data[] = { + { +- .label = "cpld1_version", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, +- .bit = GENMASK(7, 0), +- .mode = 0444, ++ .label = "psu2_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0200, + }, + { +- .label = "cpld2_version", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, +- .bit = GENMASK(7, 0), +- .mode = 0444, ++ .label = "pwr_cycle", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0200, + }, + { +- .label = "cpld3_version", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, +- .bit = GENMASK(7, 0), +- .mode = 0444, ++ .label = "pwr_down", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0200, + }, + { +- .label = "cpld4_version", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, +- .bit = GENMASK(7, 0), +- .mode = 0444, ++ .label = "psu3_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0200, + }, + { +- .label = "cpld1_pn", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, +- .bit = GENMASK(15, 0), +- .mode = 0444, +- .regnum = 2, ++ .label = "psu4_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0200, + }, + { +- .label = "cpld2_pn", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, +- .bit = GENMASK(15, 0), +- .mode = 0444, +- .regnum = 2, ++ .label = "auto_power_mode", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, + }, + { +- .label = "cpld3_pn", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, +- .bit = GENMASK(15, 0), +- .mode = 0444, +- .regnum = 2, ++ .label = "pm_mgmt_en", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0644, + }, + { +- .label = "cpld4_pn", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET, +- .bit = GENMASK(15, 0), +- .mode = 0444, +- .regnum = 2, ++ .label = "jtag_enable", ++ .reg = MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE, ++ .mask = GENMASK(3, 0), ++ .bit = 1, ++ .mode = 0644, + }, + { +- .label = "cpld1_version_min", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, +- .bit = GENMASK(7, 0), +- .mode = 0444, ++ .label = "safe_bios_dis", ++ .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, + }, + { +- .label = "cpld2_version_min", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, +- .bit = GENMASK(7, 0), +- .mode = 0444, ++ .label = "safe_bios_dis_wp", ++ .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, + }, + { +- .label = "cpld3_version_min", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, +- .bit = GENMASK(7, 0), ++ .label = "asic_health", ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_MASK, ++ .bit = 1, + .mode = 0444, + }, + { +- .label = "cpld4_version_min", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET, ++ .label = "fan_dir", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, + .bit = GENMASK(7, 0), + .mode = 0444, + }, + { +- .label = "lc1_enable", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, ++ .label = "lc1_pwr", ++ .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0644, + }, + { +- .label = "lc2_enable", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, ++ .label = "lc2_pwr", ++ .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0644, + }, + { +- .label = "lc3_enable", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, ++ .label = "lc3_pwr", ++ .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0644, + }, + { +- .label = "lc4_enable", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, ++ .label = "lc4_pwr", ++ .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0644, + }, + { +- .label = "lc5_enable", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, ++ .label = "lc5_pwr", ++ .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0644, + }, + { +- .label = "lc6_enable", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, ++ .label = "lc6_pwr", ++ .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0644, + }, + { +- .label = "lc7_enable", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, ++ .label = "lc7_pwr", ++ .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0644, + }, + { +- .label = "lc8_enable", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, ++ .label = "lc8_pwr", ++ .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, + .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0644, + }, + { +- .label = "reset_long_pb", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(0), ++ .label = "config1", ++ .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "config2", ++ .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "config3", ++ .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, ++ .bit = GENMASK(7, 0), + .mode = 0444, + }, + { +- .label = "reset_short_pb", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(1), ++ .label = "ufm_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, ++ .bit = GENMASK(7, 0), + .mode = 0444, + }, ++}; ++ ++static struct mlxreg_core_platform_data mlxplat_modular_regs_io_data = { ++ .data = mlxplat_mlxcpld_modular_regs_io_data, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_regs_io_data), ++}; ++ ++/* Platform register access for chassis blade systems family data */ ++static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { + { +- .label = "reset_aux_pwr_or_fu", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(2), ++ .label = "cpld1_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, ++ .bit = GENMASK(7, 0), + .mode = 0444, + }, + { +- .label = "reset_mgmt_dc_dc_pwr_fail", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(3), ++ .label = "cpld1_pn", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, ++ .bit = GENMASK(15, 0), + .mode = 0444, ++ .regnum = 2, + }, + { +- .label = "reset_sys_comex_bios", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(5), ++ .label = "cpld1_version_min", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, ++ .bit = GENMASK(7, 0), + .mode = 0444, + }, + { +- .label = "reset_sw_reset", +- .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(0), ++ .label = "reset_aux_pwr_or_ref", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0444, + }, + { +- .label = "reset_aux_pwr_or_reload", +- .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(2), ++ .label = "reset_from_comex", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), + .mode = 0444, + }, + { +@@ -4109,47 +5107,83 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_regs_io_data[] = { + .mode = 0444, + }, + { +- .label = "reset_pwr_off_from_carrier", ++ .label = "reset_comex_wd", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(7), ++ .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0444, + }, + { +- .label = "reset_swb_wd", ++ .label = "reset_voltmon_upgrade_fail", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0444, + }, + { +- .label = "reset_swb_aux_pwr_or_fu", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .label = "reset_system", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_sw_pwr_off", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0444, + }, + { +- .label = "reset_swb_dc_dc_pwr_fail", ++ .label = "reset_comex_thermal", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0444, + }, + { +- .label = "reset_swb_12v_fail", ++ .label = "reset_reload_bios", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(4), ++ .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, + }, + { +- .label = "reset_system", ++ .label = "reset_ac_pwr_fail", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(5), ++ .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0444, + }, + { +- .label = "reset_thermal_spc_or_pciesw", ++ .label = "reset_long_pwr_pb", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, + }, ++ { ++ .label = "pwr_cycle", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0200, ++ }, ++ { ++ .label = "pwr_down", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0200, ++ }, ++ { ++ .label = "global_wp_request", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0644, ++ }, ++ { ++ .label = "jtag_enable", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, ++ }, ++ { ++ .label = "comm_chnl_ready", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0200, ++ }, + { + .label = "bios_safe_mode", + .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, +@@ -4194,251 +5228,215 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_regs_io_data[] = { + .mode = 0644, + }, + { +- .label = "shutdown_unlock", +- .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(5), +- .mode = 0644, +- }, +- { +- .label = "lc1_rst_mask", +- .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, ++ .label = "global_wp_response", ++ .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), +- .mode = 0200, +- }, +- { +- .label = "lc2_rst_mask", +- .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(1), +- .mode = 0200, +- }, +- { +- .label = "lc3_rst_mask", +- .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(2), +- .mode = 0200, +- }, +- { +- .label = "lc4_rst_mask", +- .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(3), +- .mode = 0200, +- }, +- { +- .label = "lc5_rst_mask", +- .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(4), +- .mode = 0200, ++ .mode = 0444, + }, + { +- .label = "lc6_rst_mask", +- .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(5), +- .mode = 0200, ++ .label = "config1", ++ .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { +- .label = "lc7_rst_mask", +- .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(6), +- .mode = 0200, ++ .label = "config2", ++ .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { +- .label = "lc8_rst_mask", +- .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(7), +- .mode = 0200, ++ .label = "config3", ++ .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { +- .label = "psu1_on", +- .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(0), +- .mode = 0200, ++ .label = "ufm_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, ++}; ++ ++static struct mlxreg_core_platform_data mlxplat_chassis_blade_regs_io_data = { ++ .data = mlxplat_mlxcpld_chassis_blade_regs_io_data, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_regs_io_data), ++}; ++ ++/* Platform register access for smart switch systems families data */ ++static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_regs_io_data[] = { + { +- .label = "psu2_on", +- .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(1), +- .mode = 0200, ++ .label = "cpld1_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { +- .label = "pwr_cycle", +- .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(2), +- .mode = 0200, ++ .label = "cpld2_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { +- .label = "pwr_down", +- .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(3), +- .mode = 0200, ++ .label = "cpld3_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { +- .label = "psu3_on", +- .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(4), +- .mode = 0200, ++ .label = "cpld1_pn", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, + }, + { +- .label = "psu4_on", +- .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(5), +- .mode = 0200, ++ .label = "cpld2_pn", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, + }, + { +- .label = "auto_power_mode", +- .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(6), +- .mode = 0644, ++ .label = "cpld3_pn", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, + }, + { +- .label = "pm_mgmt_en", +- .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(7), +- .mode = 0644, ++ .label = "cpld1_version_min", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { +- .label = "jtag_enable", +- .reg = MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE, +- .mask = GENMASK(3, 0), +- .bit = 1, +- .mode = 0644, ++ .label = "cpld2_version_min", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { +- .label = "safe_bios_dis", +- .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(5), +- .mode = 0644, ++ .label = "cpld3_version_min", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, + }, + { +- .label = "safe_bios_dis_wp", +- .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(5), ++ .label = "kexec_activated", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0644, + }, + { +- .label = "asic_health", +- .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, +- .mask = MLXPLAT_CPLD_ASIC_MASK, +- .bit = 1, +- .mode = 0444, ++ .label = "asic_reset", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, + }, + { +- .label = "fan_dir", +- .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, +- .bit = GENMASK(7, 0), +- .mode = 0444, ++ .label = "eth_switch_reset", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, + }, + { +- .label = "lc1_pwr", +- .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, ++ .label = "dpu1_rst", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), +- .mode = 0644, ++ .mode = 0200, + }, + { +- .label = "lc2_pwr", +- .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, ++ .label = "dpu2_rst", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), +- .mode = 0644, ++ .mode = 0200, + }, + { +- .label = "lc3_pwr", +- .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, ++ .label = "dpu3_rst", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), +- .mode = 0644, ++ .mode = 0200, + }, + { +- .label = "lc4_pwr", +- .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, ++ .label = "dpu4_rst", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), +- .mode = 0644, ++ .mode = 0200, + }, + { +- .label = "lc5_pwr", +- .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, +- .mask = GENMASK(7, 0) & ~BIT(4), +- .mode = 0644, ++ .label = "dpu1_pwr", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0200, + }, + { +- .label = "lc6_pwr", +- .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, +- .mask = GENMASK(7, 0) & ~BIT(5), +- .mode = 0644, ++ .label = "dpu2_pwr", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0200, + }, + { +- .label = "lc7_pwr", +- .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, +- .mask = GENMASK(7, 0) & ~BIT(6), +- .mode = 0644, ++ .label = "dpu3_pwr", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0200, + }, + { +- .label = "lc8_pwr", +- .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, +- .mask = GENMASK(7, 0) & ~BIT(7), +- .mode = 0644, ++ .label = "dpu4_pwr", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0200, + }, + { +- .label = "config1", +- .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, +- .bit = GENMASK(7, 0), ++ .label = "reset_long_pb", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0444, + }, + { +- .label = "config2", +- .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, +- .bit = GENMASK(7, 0), ++ .label = "reset_short_pb", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0444, + }, + { +- .label = "config3", +- .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, +- .bit = GENMASK(7, 0), ++ .label = "reset_aux_pwr_or_ref", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0444, + }, + { +- .label = "ufm_version", +- .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, +- .bit = GENMASK(7, 0), ++ .label = "reset_swb_dc_dc_pwr_fail", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0444, + }, +-}; +- +-static struct mlxreg_core_platform_data mlxplat_modular_regs_io_data = { +- .data = mlxplat_mlxcpld_modular_regs_io_data, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_regs_io_data), +-}; +- +-/* Platform register access for chassis blade systems family data */ +-static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { + { +- .label = "cpld1_version", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, +- .bit = GENMASK(7, 0), ++ .label = "reset_swb_wd", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0444, + }, + { +- .label = "cpld1_pn", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, +- .bit = GENMASK(15, 0), ++ .label = "reset_asic_thermal", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, +- .regnum = 2, + }, + { +- .label = "cpld1_version_min", +- .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, +- .bit = GENMASK(7, 0), ++ .label = "reset_sw_reset", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0444, + }, + { +- .label = "reset_aux_pwr_or_ref", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, ++ .label = "reset_aux_pwr_or_reload", ++ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0444, + }, +- { +- .label = "reset_from_comex", +- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(4), +- .mode = 0444, +- }, + { + .label = "reset_comex_pwr_fail", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, +@@ -4458,13 +5456,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { + .mode = 0444, + }, + { +- .label = "reset_comex_wd", ++ .label = "reset_pwr", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(6), ++ .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, + }, + { +- .label = "reset_voltmon_upgrade_fail", ++ .label = "reset_pwr_converter_fail", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0444, +@@ -4488,23 +5486,103 @@ static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { + .mode = 0444, + }, + { +- .label = "reset_reload_bios", ++ .label = "reset_ac_pwr_fail", + .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(5), ++ .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0444, + }, + { +- .label = "reset_ac_pwr_fail", +- .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(6), ++ .label = "voltreg_update_status", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, ++ .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, ++ .bit = 5, + .mode = 0444, + }, + { +- .label = "reset_long_pwr_pb", +- .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(7), ++ .label = "port80", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_status", ++ .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, ++ .mask = MLXPLAT_CPLD_BIOS_STATUS_MASK, ++ .bit = 2, ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_start_retry", ++ .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_active_image", ++ .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "vpd_wp", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ }, ++ { ++ .label = "pcie_asic_reset_dis", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, ++ }, ++ { ++ .label = "shutdown_unlock", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, ++ }, ++ { ++ .label = "fan_dir", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, ++ .bit = GENMASK(7, 0), + .mode = 0444, + }, ++ { ++ .label = "dpu1_rst_en", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0200, ++ }, ++ { ++ .label = "dpu2_rst_en", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0200, ++ }, ++ { ++ .label = "dpu3_rst_en", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0200, ++ }, ++ { ++ .label = "dpu4_rst_en", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0200, ++ }, ++ { ++ .label = "psu1_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0200, ++ }, ++ { ++ .label = "psu2_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0200, ++ }, + { + .label = "pwr_cycle", + .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, +@@ -4518,72 +5596,117 @@ static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { + .mode = 0200, + }, + { +- .label = "global_wp_request", +- .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, ++ .label = "jtag_cap", ++ .reg = MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET, ++ .mask = MLXPLAT_CPLD_FU_CAP_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "jtag_enable", ++ .reg = MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE, ++ .mask = GENMASK(1, 0), ++ .bit = 1, ++ .mode = 0644, ++ }, ++ { ++ .label = "non_active_bios_select", ++ .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, ++ }, ++ { ++ .label = "bios_upgrade_fail", ++ .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_image_invert", ++ .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "me_reboot", ++ .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0644, ++ }, ++ { ++ .label = "dpu1_pwr_force", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0644, + }, + { +- .label = "jtag_enable", +- .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(4), ++ .label = "dpu2_pwr_force", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0644, + }, + { +- .label = "comm_chnl_ready", +- .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(6), +- .mode = 0200, ++ .label = "dpu3_pwr_force", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0644, + }, + { +- .label = "bios_safe_mode", +- .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(4), +- .mode = 0444, ++ .label = "dpu4_pwr_force", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP3_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, + }, + { +- .label = "bios_active_image", +- .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(5), ++ .label = "ufm_done", ++ .reg = MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET, ++ .bit = GENMASK(7, 0), + .mode = 0444, + }, + { +- .label = "bios_auth_fail", +- .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(6), ++ .label = "asic_health", ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_MASK, ++ .bit = 1, + .mode = 0444, + }, + { +- .label = "bios_upgrade_fail", +- .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(7), +- .mode = 0444, ++ .label = "psu1_ac_ok", ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0644, + }, + { +- .label = "voltreg_update_status", +- .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, +- .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, +- .bit = 5, +- .mode = 0444, ++ .label = "psu2_ac_ok", ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0644, + }, + { +- .label = "vpd_wp", +- .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(3), ++ .label = "psu1_no_alert", ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), + .mode = 0644, + }, + { +- .label = "pcie_asic_reset_dis", +- .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(4), ++ .label = "psu2_no_alert", ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0644, + }, + { +- .label = "global_wp_response", +- .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(0), ++ .label = "asic_pg_fail", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, + }, ++ { ++ .label = "spi_chnl_select", ++ .reg = MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT, ++ .mask = GENMASK(7, 0), ++ .bit = 1, ++ .mode = 0644, ++ }, + { + .label = "config1", + .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, +@@ -4610,9 +5733,9 @@ static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { + }, + }; + +-static struct mlxreg_core_platform_data mlxplat_chassis_blade_regs_io_data = { +- .data = mlxplat_mlxcpld_chassis_blade_regs_io_data, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_regs_io_data), ++static struct mlxreg_core_platform_data mlxplat_smart_switch_regs_io_data = { ++ .data = mlxplat_mlxcpld_smart_switch_regs_io_data, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_regs_io_data), + }; + + /* Platform FAN default */ +@@ -4756,6 +5879,185 @@ static struct mlxreg_core_platform_data mlxplat_default_fan_data = { + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, + }; + ++/* XDR and smart switch platform fan data */ ++static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_data[] = { ++ { ++ .label = "pwm1", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, ++ }, ++ { ++ .label = "tacho1", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 1, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho2", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 2, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho3", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 3, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho4", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 4, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho5", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 5, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho6", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 6, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho7", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 7, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho8", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 8, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho9", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 9, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho10", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 10, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho11", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 11, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho12", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 12, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho13", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 13, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho14", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 14, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho15", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 15, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho16", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 16, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho17", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 17, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, ++ }, ++ { ++ .label = "tacho18", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 18, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, ++ }, ++ { ++ .label = "tacho19", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 19, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, ++ }, ++ { ++ .label = "tacho20", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 20, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, ++ }, ++ { ++ .label = "conf", ++ .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data mlxplat_xdr_fan_data = { ++ .data = mlxplat_mlxcpld_xdr_fan_data, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_data), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .version = 1, ++}; ++ + /* Watchdog type1: hardware implementation version1 + * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems). + */ +@@ -4980,6 +6282,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) + { + switch (reg) { + case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: +@@ -4988,12 +6292,14 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_GP3_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: + case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: + case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: +@@ -5017,10 +6323,14 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: +@@ -5088,6 +6398,8 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: +@@ -5099,15 +6411,18 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: + case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_GP3_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: + case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: + case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: +@@ -5127,6 +6442,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: + case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: +@@ -5139,12 +6455,17 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: +@@ -5218,6 +6539,13 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: + case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET: + case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: +@@ -5253,6 +6581,8 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: +@@ -5264,13 +6594,16 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: + case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_GP3_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: + case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: + case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: +@@ -5290,6 +6623,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: + case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: +@@ -5302,9 +6636,11 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: +@@ -5375,6 +6711,13 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: + case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET: + case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: +@@ -5436,6 +6779,14 @@ static const struct reg_default mlxplat_mlxcpld_regmap_eth_modular[] = { + MLXPLAT_CPLD_AGGR_MASK_LC_LOW }, + }; + ++static const struct reg_default mlxplat_mlxcpld_regmap_smart_switch[] = { ++ { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, ++ { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, ++ { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, ++ { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, ++ { MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET, MLXPLAT_CPLD_LPC_SM_SW_MASK }, ++}; ++ + struct mlxplat_mlxcpld_regmap_context { + void __iomem *base; + }; +@@ -5544,6 +6895,20 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config_eth_modular = { + .reg_write = mlxplat_mlxcpld_reg_write, + }; + ++static const struct regmap_config mlxplat_mlxcpld_regmap_config_smart_switch = { ++ .reg_bits = 8, ++ .val_bits = 8, ++ .max_register = 255, ++ .cache_type = REGCACHE_FLAT, ++ .writeable_reg = mlxplat_mlxcpld_writeable_reg, ++ .readable_reg = mlxplat_mlxcpld_readable_reg, ++ .volatile_reg = mlxplat_mlxcpld_volatile_reg, ++ .reg_defaults = mlxplat_mlxcpld_regmap_smart_switch, ++ .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_smart_switch), ++ .reg_read = mlxplat_mlxcpld_reg_read, ++ .reg_write = mlxplat_mlxcpld_reg_write, ++}; ++ + static struct resource mlxplat_mlxcpld_resources[] = { + [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug"), + }; +@@ -5555,6 +6920,7 @@ static struct mlxreg_core_platform_data *mlxplat_regs_io; + static struct mlxreg_core_platform_data *mlxplat_fan; + static struct mlxreg_core_platform_data + *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS]; ++static struct mlxreg_core_data *mlxplat_dpu_data[MLXPLAT_CPLD_DPU_MAX_DEVS]; + static const struct regmap_config *mlxplat_regmap_config; + static struct pci_dev *lpc_bridge; + static struct pci_dev *i2c_bridge; +@@ -5926,6 +7292,31 @@ static int __init mlxplat_dmi_l1_switch_matched(const struct dmi_system_id *dmi) + return mlxplat_register_platform_device(); + } + ++static int __init mlxplat_dmi_smart_switch_matched(const struct dmi_system_id *dmi) ++{ ++ int i; ++ ++ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; ++ mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data); ++ mlxplat_mux_data = mlxplat_ng800_mux_data; ++ mlxplat_hotplug = &mlxplat_mlxcpld_smart_switch_data; ++ mlxplat_hotplug->deferred_nr = ++ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; ++ mlxplat_led = &mlxplat_xdr_led_data; ++ mlxplat_regs_io = &mlxplat_smart_switch_regs_io_data; ++ mlxplat_fan = &mlxplat_xdr_fan_data; ++ ++ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) ++ mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; ++ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_dpu_data); i++) ++ mlxplat_dpu_data[i] = &mlxplat_mlxcpld_smart_switch_dpu_data[i]; ++ ++ mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; ++ mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_smart_switch; ++ ++ return mlxplat_register_platform_device(); ++} ++ + static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { + { + .callback = mlxplat_dmi_default_wc_matched, +@@ -6020,6 +7411,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { + DMI_MATCH(DMI_BOARD_NAME, "VMOD0017"), + }, + }, ++ { ++ .callback = mlxplat_dmi_smart_switch_matched, ++ .matches = { ++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0019"), ++ }, ++ }, + { + .callback = mlxplat_dmi_msn274x_matched, + .matches = { +@@ -6400,8 +7797,25 @@ static int mlxplat_platdevs_init(struct mlxplat_priv *priv) + } + } + ++ /* Add DPU drivers. */ ++ for (i = 0; i < MLXPLAT_CPLD_DPU_MAX_DEVS; i++) { ++ if (!mlxplat_dpu_data[i]) ++ continue; ++ priv->pdev_dpu[i] = ++ platform_device_register_resndata(&mlxplat_dev->dev, "mlxreg-dpu", ++ i, NULL, 0, mlxplat_dpu_data[i], ++ sizeof(*mlxplat_dpu_data[i])); ++ if (IS_ERR(priv->pdev_dpu[i])) { ++ err = PTR_ERR(priv->pdev_dpu[i]); ++ goto fail_platform_dpu_register; ++ } ++ } ++ + return 0; + ++fail_platform_dpu_register: ++ while (i--) ++ platform_device_unregister(priv->pdev_dpu[i]); + fail_platform_wd_register: + while (--i >= 0) + platform_device_unregister(priv->pdev_wd[i]); +@@ -6422,6 +7836,8 @@ static void mlxplat_platdevs_exit(struct mlxplat_priv *priv) + { + int i; + ++ for (i = MLXPLAT_CPLD_DPU_MAX_DEVS - 1; i >= 0; i--) ++ platform_device_unregister(priv->pdev_dpu[i]); + for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--) + platform_device_unregister(priv->pdev_wd[i]); + if (priv->pdev_fan) +-- +2.47.2 + diff --git a/patch/0085-hwmon-mlxreg-fan-Separate-methods-of-fan-setting-com.patch b/patches-sonic/0030-hwmon-mlxreg-fan-Separate-methods-of-fan-setting-com.patch similarity index 93% rename from patch/0085-hwmon-mlxreg-fan-Separate-methods-of-fan-setting-com.patch rename to patches-sonic/0030-hwmon-mlxreg-fan-Separate-methods-of-fan-setting-com.patch index 88853ea87..188054c39 100644 --- a/patch/0085-hwmon-mlxreg-fan-Separate-methods-of-fan-setting-com.patch +++ b/patches-sonic/0030-hwmon-mlxreg-fan-Separate-methods-of-fan-setting-com.patch @@ -1,8 +1,8 @@ -From 66c36c502d56010fa726af98ff63c9e895791c4d Mon Sep 17 00:00:00 2001 +From 453623c4adece1b0d146f88836b4e718956c265d Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Fri, 1 Sep 2023 07:16:20 +0000 -Subject: [PATCH v6.1 68/80] hwmon: (mlxreg-fan) Separate methods of fan - setting coming from different subsystems +Subject: [PATCH 30/78] hwmon: (mlxreg-fan) Separate methods of fan setting + coming from different subsystems Distinct between fan speed setting request coming for hwmon and thermal subsystems. @@ -28,7 +28,7 @@ Signed-off-by: Vadim Pasternak 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/hwmon/mlxreg-fan.c b/drivers/hwmon/mlxreg-fan.c -index bddc927b207c..102a517940f3 100644 +index e54a438..0e9ce70 100644 --- a/drivers/hwmon/mlxreg-fan.c +++ b/drivers/hwmon/mlxreg-fan.c @@ -115,8 +115,8 @@ struct mlxreg_fan { @@ -91,5 +91,5 @@ index bddc927b207c..102a517940f3 100644 .get_max_state = mlxreg_fan_get_max_state, .get_cur_state = mlxreg_fan_get_cur_state, -- -2.20.1 +2.8.4 diff --git a/patch/0087-platform-mellanox-indicate-deferred-I2C-bus-creation.patch b/patches-sonic/0031-platform-mellanox-indicate-deferred-I2C-bus-creation.patch similarity index 70% rename from patch/0087-platform-mellanox-indicate-deferred-I2C-bus-creation.patch rename to patches-sonic/0031-platform-mellanox-indicate-deferred-I2C-bus-creation.patch index fac297021..4562391bb 100644 --- a/patch/0087-platform-mellanox-indicate-deferred-I2C-bus-creation.patch +++ b/patches-sonic/0031-platform-mellanox-indicate-deferred-I2C-bus-creation.patch @@ -1,7 +1,7 @@ -From 1c43cf584d3fd62823dd3b28018481f15a8836c7 Mon Sep 17 00:00:00 2001 +From 86f67641e8d4052f801b54362abb88c2b9eda242 Mon Sep 17 00:00:00 2001 From: Michael Shych Date: Wed, 29 Nov 2023 13:12:38 +0000 -Subject: [PATCH 3/4] platform: mellanox: indicate deferred I2C bus creation +Subject: [PATCH 31/78] platform: mellanox: indicate deferred I2C bus creation for a hot-plug driver It fixes timing issue when during initialization hot-plug driver @@ -15,17 +15,17 @@ Signed-off-by: Michael Shych 1 file changed, 1 insertion(+) diff --git a/drivers/platform/mellanox/nvsw-sn2201.c b/drivers/platform/mellanox/nvsw-sn2201.c -index 1a7c45aa4..a3e2bc6d6 100644 +index db31c8b..924ad48 100644 --- a/drivers/platform/mellanox/nvsw-sn2201.c +++ b/drivers/platform/mellanox/nvsw-sn2201.c -@@ -520,6 +520,7 @@ struct mlxreg_core_hotplug_platform_data nvsw_sn2201_hotplug = { - .counter = ARRAY_SIZE(nvsw_sn2201_items), +@@ -526,6 +526,7 @@ struct mlxreg_core_hotplug_platform_data nvsw_sn2201_hotplug = { + .count = ARRAY_SIZE(nvsw_sn2201_items), .cell = NVSW_SN2201_SYS_INT_STATUS_OFFSET, .mask = NVSW_SN2201_CPLD_AGGR_MASK_DEF, + .deferred_nr = NVSW_SN2201_2ND_MUX_CH3_NR, }; - /* SN2201 static devices. */ + static struct mlxreg_core_item nvsw_sn2201_busbar_items[] = { -- -2.20.1 +2.8.4 diff --git a/patch/0087-platform_data-mlxreg-Add-capability-bit-and-mask-fie.patch b/patches-sonic/0032-platform_data-mlxreg-Add-capability-bit-and-mask-fie.patch similarity index 91% rename from patch/0087-platform_data-mlxreg-Add-capability-bit-and-mask-fie.patch rename to patches-sonic/0032-platform_data-mlxreg-Add-capability-bit-and-mask-fie.patch index 0b5d4a713..c23d6c3e8 100644 --- a/patch/0087-platform_data-mlxreg-Add-capability-bit-and-mask-fie.patch +++ b/patches-sonic/0032-platform_data-mlxreg-Add-capability-bit-and-mask-fie.patch @@ -1,7 +1,7 @@ -From 923c91d57aa35fc063001fea28ba884a1b6ba224 Mon Sep 17 00:00:00 2001 +From aa424ad19acfa09047c184ae619963d51e027a82 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Thu, 24 Aug 2023 13:20:54 +0000 -Subject: [PATCH v6.1 31/50] platform_data/mlxreg: Add capability bit and mask +Subject: [PATCH 32/78] platform_data/mlxreg: Add capability bit and mask fields Some 'capability' registers can be shared between different resources. @@ -16,7 +16,7 @@ Reviewed-by: Felix Radensky 1 file changed, 8 insertions(+) diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_data/mlxreg.h -index 0b9f81a6f753..d9f679752226 100644 +index f6cca7a..20f84cf 100644 --- a/include/linux/platform_data/mlxreg.h +++ b/include/linux/platform_data/mlxreg.h @@ -118,6 +118,8 @@ struct mlxreg_hotplug_device { @@ -56,5 +56,5 @@ index 0b9f81a6f753..d9f679752226 100644 u8 count; u8 ind; -- -2.20.1 +2.8.4 diff --git a/patch/0088-platform-mellanox-mlxreg-hotplug-Add-support-for-new.patch b/patches-sonic/0033-platform-mellanox-mlxreg-hotplug-Add-support-for-new.patch similarity index 85% rename from patch/0088-platform-mellanox-mlxreg-hotplug-Add-support-for-new.patch rename to patches-sonic/0033-platform-mellanox-mlxreg-hotplug-Add-support-for-new.patch index 33dbe7426..c928dfd5d 100644 --- a/patch/0088-platform-mellanox-mlxreg-hotplug-Add-support-for-new.patch +++ b/patches-sonic/0033-platform-mellanox-mlxreg-hotplug-Add-support-for-new.patch @@ -1,8 +1,8 @@ -From 8ef21e6d6273636a4bb6f9c4f704c3aaa5d4f736 Mon Sep 17 00:00:00 2001 +From 2b021913a38a7e6821c4ce989742e34d8bf743c8 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Thu, 24 Aug 2023 11:47:54 +0000 -Subject: [PATCH v6.1 2/9] platform/mellanox: mlxreg-hotplug: Add support for - new flavor of capability registers +Subject: [PATCH 33/78] platform/mellanox: mlxreg-hotplug: Add support for new + flavor of capability registers Hotplug platform data is common across the various systems, while hotplug driver should be able to configure only the instances relevant @@ -31,14 +31,14 @@ relevant capability bits. Signed-off-by: Vadim Pasternak Reviewed-by: Felix Radensky --- - drivers/platform/mellanox/mlxreg-hotplug.c | 23 ++++++++++++++++++++-- + drivers/platform/mellanox/mlxreg-hotplug.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/platform/mellanox/mlxreg-hotplug.c b/drivers/platform/mellanox/mlxreg-hotplug.c -index c5abedd3514d..3737af0d3e43 100644 +index 23fdbcb..51dac7e 100644 --- a/drivers/platform/mellanox/mlxreg-hotplug.c +++ b/drivers/platform/mellanox/mlxreg-hotplug.c -@@ -275,6 +275,13 @@ static int mlxreg_hotplug_attr_init(struct mlxreg_hotplug_priv_data *priv) +@@ -274,6 +274,13 @@ static int mlxreg_hotplug_attr_init(struct mlxreg_hotplug_priv_data *priv) if (ret) return ret; @@ -52,7 +52,7 @@ index c5abedd3514d..3737af0d3e43 100644 item->mask = GENMASK((regval & item->mask) - 1, 0); } -@@ -295,7 +302,19 @@ static int mlxreg_hotplug_attr_init(struct mlxreg_hotplug_priv_data *priv) +@@ -294,7 +301,19 @@ static int mlxreg_hotplug_attr_init(struct mlxreg_hotplug_priv_data *priv) if (ret) return ret; @@ -73,7 +73,7 @@ index c5abedd3514d..3737af0d3e43 100644 data++; continue; } -@@ -626,7 +645,7 @@ static int mlxreg_hotplug_set_irq(struct mlxreg_hotplug_priv_data *priv) +@@ -611,7 +630,7 @@ static int mlxreg_hotplug_set_irq(struct mlxreg_hotplug_priv_data *priv) if (ret) goto out; @@ -83,5 +83,5 @@ index c5abedd3514d..3737af0d3e43 100644 } } -- -2.20.1 +2.8.4 diff --git a/patches-sonic/0034-platform-mellanox-Cosmetic-changes-to-improve-code-s.patch b/patches-sonic/0034-platform-mellanox-Cosmetic-changes-to-improve-code-s.patch new file mode 100644 index 000000000..d3d0caed1 --- /dev/null +++ b/patches-sonic/0034-platform-mellanox-Cosmetic-changes-to-improve-code-s.patch @@ -0,0 +1,63 @@ +From c15263c31b19f0dd2cea9e09b9951613ec459afa Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Mon, 21 Apr 2025 12:20:48 +0300 +Subject: [PATCH 34/78] platform: mellanox: Cosmetic changes to improve code + style +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Replace in 'for' loop - /i >= 0 ; i--/i >= 0 ;i--/. +Replace in 'while' loop - /(--i >= 0)/(--i)/. + +Signed-off-by: Vadim Pasternak +Reviewed-by: Ilpo Järvinen +Link: https://lore.kernel.org/r/20250421092051.7687-4-vadimp@nvidia.com +Signed-off-by: Ilpo Järvinen +--- + drivers/platform/mellanox/mlx-platform.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c +index 053c8a0..fca8883 100644 +--- a/drivers/platform/mellanox/mlx-platform.c ++++ b/drivers/platform/mellanox/mlx-platform.c +@@ -7817,7 +7817,7 @@ static int mlxplat_platdevs_init(struct mlxplat_priv *priv) + while (i--) + platform_device_unregister(priv->pdev_dpu[i]); + fail_platform_wd_register: +- while (--i >= 0) ++ while (i--) + platform_device_unregister(priv->pdev_wd[i]); + fail_platform_fan_register: + if (mlxplat_regs_io) +@@ -7838,7 +7838,7 @@ static void mlxplat_platdevs_exit(struct mlxplat_priv *priv) + + for (i = MLXPLAT_CPLD_DPU_MAX_DEVS - 1; i >= 0; i--) + platform_device_unregister(priv->pdev_dpu[i]); +- for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--) ++ for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0; i--) + platform_device_unregister(priv->pdev_wd[i]); + if (priv->pdev_fan) + platform_device_unregister(priv->pdev_fan); +@@ -7923,7 +7923,7 @@ static int mlxplat_i2c_mux_topology_init(struct mlxplat_priv *priv) + return mlxplat_platdevs_init(priv); + + fail_platform_mux_register: +- while (--i >= 0) ++ while (i--) + platform_device_unregister(priv->pdev_mux[i]); + return err; + } +@@ -7932,7 +7932,7 @@ static void mlxplat_i2c_mux_topology_exit(struct mlxplat_priv *priv) + { + int i; + +- for (i = mlxplat_mux_num - 1; i >= 0 ; i--) { ++ for (i = mlxplat_mux_num - 1; i >= 0; i--) { + if (priv->pdev_mux[i]) + platform_device_unregister(priv->pdev_mux[i]); + } +-- +2.8.4 + diff --git a/patch/0097-platform-mellanox-mlx-platform-Add-support-for-new-N.patch b/patches-sonic/0035-platform-mellanox-mlx-platform-Add-support-for-new-N.patch similarity index 63% rename from patch/0097-platform-mellanox-mlx-platform-Add-support-for-new-N.patch rename to patches-sonic/0035-platform-mellanox-mlx-platform-Add-support-for-new-N.patch index 076dee691..23e43ee5f 100644 --- a/patch/0097-platform-mellanox-mlx-platform-Add-support-for-new-N.patch +++ b/patches-sonic/0035-platform-mellanox-mlx-platform-Add-support-for-new-N.patch @@ -1,53 +1,41 @@ -From 60e5f8cfdf6bd3a18ffef73764e59ccd53bba9ff Mon Sep 17 00:00:00 2001 -From: Oleksandr Shamray -Date: Fri, 11 Oct 2024 11:09:32 +0300 -Subject: [PATCH 1/3] platform: mellanox: mlx-platform: Add support for new +From 7f87ccbae3163ac9b1289abb452eeae74df01eda Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Mon, 21 Apr 2025 12:20:49 +0300 +Subject: [PATCH 35/78] platform: mellanox: mlx-platform: Add support for new Nvidia system +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit -Add support for SN5640 and SN5610 Nvidia switches. +Add support for SN5640 and SN5610 Nvidia switches: +- SN5610 is a 51.2Tbps switch based on Nvidia SPC-4 ASIC equipped with 64 + OSFP ports supporting 2.5Gbps - 400Gbps speeds. +- SN5640 is a 51.2Tbps switch based on Nvidia SPC-5 ASIC equipped with 64 + OSFP ports supporting 10Gbps - 800Gbps speeds. -SN5640 is a 51.2Tbps switch based on Nvidia SPC-5 ASIC. -It provides up-to 400Gbps full bidirectional bandwidth per port. -The system supports 64 OSFP cages and fits into standard 2U racks. +Both equipped with: +- Air-cooled with 4 + 1 redundant fan units. +- 2 + 2 redundant 2000W PSUs. +- System management board based on AMD CPU with secure-boot support. -SN5640 Features: - - 64 OSFP ports supporting 2.5Gbps - 400Gbps speeds. - - Air-cooled with 4 + 1 redundant fan units. - - 2 + 2 redundant 2000W PSUs. - - System management board based on AMD CPU with secure-boot support. - -SN5610 is a 51.2Tbps switch based on Nvidia SPC-4 ASIC. -It provides up-to 800Gbps full bidirectional bandwidth per port. -The system supports 64 OSFP cages and fits into standard 2U racks. - -SN5610 Features: - - 64 OSFP ports supporting 10Gbps - 800Gbps speeds. - - Air-cooled with 4 + 1 redundant fan units. - - 2 + 2 redundant 2000W PSUs. - - System management board based on AMD CPU with secure-boot support. - -Signed-off-by: Oleksandr Shamray -Reviewed-by: Vadim Pasternak +Reviewed-by: Oleksandr Shamray +Signed-off-by: Vadim Pasternak +Link: https://lore.kernel.org/r/20250421092051.7687-5-vadimp@nvidia.com +Reviewed-by: Ilpo Järvinen +Signed-off-by: Ilpo Järvinen --- - drivers/platform/mellanox/mlx-platform.c | 96 ++++++++++++++++++++++++ + drivers/platform/mellanox/mlx-platform.c | 96 ++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index f94e2f2f6776..5796e4695a2a 100644 +index fca8883..a607fd6 100644 --- a/drivers/platform/mellanox/mlx-platform.c +++ b/drivers/platform/mellanox/mlx-platform.c -@@ -2131,6 +2131,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = { - }, - }; - -+ - static - struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_lc_act = { - .irq = MLXPLAT_CPLD_LPC_SYSIRQ, -@@ -2941,6 +2942,60 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_modular_data = { - .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, +@@ -3005,6 +3005,59 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_l1_switch_data = { + .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT, }; ++/* Platform hotplug for 800G systems family data */ +static struct mlxreg_core_item mlxplat_mlxcpld_ng800_hi171_items[] = { + { + .data = mlxplat_mlxcpld_ext_psu_items_data, @@ -75,7 +63,6 @@ index f94e2f2f6776..5796e4695a2a 100644 + .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, + .mask = MLXPLAT_CPLD_FAN_XDR_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .capability_mask = MLXPLAT_CPLD_FAN_CAP_MASK, + .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_items_data), + .inversed = 1, + .health = false, @@ -94,37 +81,36 @@ index f94e2f2f6776..5796e4695a2a 100644 +static +struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_hi171_data = { + .items = mlxplat_mlxcpld_ng800_hi171_items, -+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_ng800_hi171_items), ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_ng800_hi171_items), + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, + .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, + .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, +}; + -+ - /* Platform hotplug for NVLink blade systems family data */ - static struct mlxreg_core_data mlxplat_mlxcpld_global_wp_items_data[] = { + /* Platform led default data */ + static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { { -@@ -5115,6 +5170,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mask = GENMASK(7, 0) & ~BIT(4), +@@ -4492,6 +4545,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { .mode = 0644, }, -+ { + { + .label = "shutdown_unlock", + .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0644, + }, - { ++ { .label = "erot1_ap_reset", .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, -@@ -8267,6 +8328,27 @@ static int __init mlxplat_dmi_smart_switch_matched(const struct dmi_system_id *d + .mask = GENMASK(7, 0) & ~BIT(0), +@@ -7317,6 +7376,29 @@ static int __init mlxplat_dmi_smart_switch_matched(const struct dmi_system_id *d return mlxplat_register_platform_device(); } +static int __init mlxplat_dmi_ng400_hi171_matched(const struct dmi_system_id *dmi) +{ -+ int i; ++ unsigned int i; + + mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; + mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data); @@ -132,11 +118,13 @@ index f94e2f2f6776..5796e4695a2a 100644 + mlxplat_hotplug = &mlxplat_mlxcpld_ng800_hi171_data; + mlxplat_hotplug->deferred_nr = + mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; -+ mlxplat_led = &mlxplat_xdr_led_data; ++ mlxplat_led = &mlxplat_default_ng_led_data; + mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; + mlxplat_fan = &mlxplat_xdr_fan_data; ++ + for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++) + mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type3[i]; ++ + mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; + mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; + @@ -146,11 +134,10 @@ index f94e2f2f6776..5796e4695a2a 100644 static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { { .callback = mlxplat_dmi_default_wc_matched, -@@ -8386,6 +8468,20 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { - DMI_MATCH(DMI_BOARD_NAME, "VMOD0019"), +@@ -7418,6 +7500,20 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { }, }, -+ { + { + .callback = mlxplat_dmi_ng400_hi171_matched, + .matches = { + DMI_MATCH(DMI_BOARD_NAME, "VMOD0022"), @@ -164,9 +151,10 @@ index f94e2f2f6776..5796e4695a2a 100644 + DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI172"), + }, + }, - { ++ { .callback = mlxplat_dmi_msn274x_matched, .matches = { + DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), -- -2.20.1 +2.8.4 diff --git a/patches-sonic/0036-platform-mellanox-mlxreg-dpu-Fix-smatch-warnings.patch b/patches-sonic/0036-platform-mellanox-mlxreg-dpu-Fix-smatch-warnings.patch new file mode 100644 index 000000000..63274fbe0 --- /dev/null +++ b/patches-sonic/0036-platform-mellanox-mlxreg-dpu-Fix-smatch-warnings.patch @@ -0,0 +1,56 @@ +From e905a420ecf5b9e2fc526ad6c20150c5c0219c14 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Thu, 8 May 2025 23:31:39 +0300 +Subject: [PATCH 36/78] platform/mellanox: mlxreg-dpu: Fix smatch warnings +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add missed call to release adapter. +Remove wrong error pointer conversion. + +Fixes: 3e75f2954116 ("platform/mellanox: mlxreg-dpu: Add initial support for Nvidia DPU") +Signed-off-by: Vadim Pasternak +Link: https://lore.kernel.org/r/20250508203139.55171-1-vadimp@nvidia.com +Reviewed-by: Ilpo Järvinen +Signed-off-by: Ilpo Järvinen +--- + drivers/platform/mellanox/mlxreg-dpu.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/drivers/platform/mellanox/mlxreg-dpu.c b/drivers/platform/mellanox/mlxreg-dpu.c +index 277e4b8..5226010 100644 +--- a/drivers/platform/mellanox/mlxreg-dpu.c ++++ b/drivers/platform/mellanox/mlxreg-dpu.c +@@ -535,8 +535,10 @@ static int mlxreg_dpu_probe(struct platform_device *pdev) + return -EPROBE_DEFER; + + mlxreg_dpu = devm_kzalloc(&pdev->dev, sizeof(*mlxreg_dpu), GFP_KERNEL); +- if (!mlxreg_dpu) +- return -ENOMEM; ++ if (!mlxreg_dpu) { ++ err = -ENOMEM; ++ goto alloc_fail; ++ } + + /* Create device at the top of DPU I2C tree. */ + data->hpdev.client = i2c_new_client_device(data->hpdev.adapter, +@@ -562,7 +564,6 @@ static int mlxreg_dpu_probe(struct platform_device *pdev) + if (err) { + dev_err(&pdev->dev, "Failed to sync regmap for client %s at bus %d at addr 0x%02x\n", + data->hpdev.brdinfo->type, data->hpdev.nr, data->hpdev.brdinfo->addr); +- err = PTR_ERR(regmap); + goto regcache_sync_fail; + } + +@@ -581,6 +582,7 @@ static int mlxreg_dpu_probe(struct platform_device *pdev) + devm_regmap_init_i2c_fail: + i2c_unregister_device(data->hpdev.client); + i2c_new_device_fail: ++alloc_fail: + i2c_put_adapter(data->hpdev.adapter); + return err; + } +-- +2.8.4 + diff --git a/patch/0100-platform-mellanox-mlxreg-io-Extend-number-of-hwmon-a.patch b/patches-sonic/0037-platform-mellanox-mlxreg-io-Extend-number-of-hwmon-a.patch similarity index 81% rename from patch/0100-platform-mellanox-mlxreg-io-Extend-number-of-hwmon-a.patch rename to patches-sonic/0037-platform-mellanox-mlxreg-io-Extend-number-of-hwmon-a.patch index 6de92dc6d..9e271a324 100644 --- a/patch/0100-platform-mellanox-mlxreg-io-Extend-number-of-hwmon-a.patch +++ b/patches-sonic/0037-platform-mellanox-mlxreg-io-Extend-number-of-hwmon-a.patch @@ -1,7 +1,7 @@ -From 41b6df4fb187cd6a4bbf501017090821825d3bef Mon Sep 17 00:00:00 2001 +From bcca6b75be5436c0f99dee143b72ec799a7e7ea0 Mon Sep 17 00:00:00 2001 From: Oleksandr Shamray Date: Wed, 5 Feb 2025 14:45:21 +0200 -Subject: [PATCH] platform/mellanox: mlxreg-io: Extend number of hwmon +Subject: [PATCH 37/78] platform/mellanox: mlxreg-io: Extend number of hwmon attributes Extend maximum number of the attributes, exposed to 'sysfs' to support @@ -16,10 +16,10 @@ Signed-off-by: Oleksandr Shamray 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/platform/mellanox/mlxreg-io.c b/drivers/platform/mellanox/mlxreg-io.c -index ddc08ab..881182c 100644 +index c502f2b..2f28fa7 100644 --- a/drivers/platform/mellanox/mlxreg-io.c +++ b/drivers/platform/mellanox/mlxreg-io.c -@@ -18,7 +18,7 @@ +@@ -17,7 +17,7 @@ /* Attribute parameters. */ #define MLXREG_IO_ATT_SIZE 10 diff --git a/patch/0101-platform_data-mlxreg-Add-fields-for-interrupt-storm-.patch b/patches-sonic/0038-platform_data-mlxreg-Add-fields-for-interrupt-storm-.patch similarity index 90% rename from patch/0101-platform_data-mlxreg-Add-fields-for-interrupt-storm-.patch rename to patches-sonic/0038-platform_data-mlxreg-Add-fields-for-interrupt-storm-.patch index 7888fbaa7..79031302b 100644 --- a/patch/0101-platform_data-mlxreg-Add-fields-for-interrupt-storm-.patch +++ b/patches-sonic/0038-platform_data-mlxreg-Add-fields-for-interrupt-storm-.patch @@ -1,8 +1,8 @@ -From 67a686455cf959f8736b86d42aed06b446efb001 Mon Sep 17 00:00:00 2001 +From 0f24213b7eb71538c48c3df74bc6fb74b08d1842 Mon Sep 17 00:00:00 2001 From: Roy Cohen Date: Mon, 13 Jan 2025 10:47:27 +0200 -Subject: [PATCH platform-next 1/2] platform_data/mlxreg: Add fields for - interrupt storm handling +Subject: [PATCH 38/78] platform_data/mlxreg: Add fields for interrupt storm + handling Add fields for interrupt storm handling. Extend structure mlxreg_core_data with the following fields: @@ -19,7 +19,7 @@ Signed-off-by: Roy Cohen 1 file changed, 8 insertions(+) diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_data/mlxreg.h -index d9f679752226..67dddacfa8fa 100644 +index 20f84cf..97042f6 100644 --- a/include/linux/platform_data/mlxreg.h +++ b/include/linux/platform_data/mlxreg.h @@ -133,6 +133,9 @@ struct mlxreg_hotplug_device { @@ -59,5 +59,5 @@ index d9f679752226..67dddacfa8fa 100644 /** -- -2.44.0 +2.8.4 diff --git a/patch/0102-platform-mellanox-mlxreg-hotplug-Add-support-for-han.patch b/patches-sonic/0039-platform-mellanox-mlxreg-hotplug-Add-support-for-han.patch similarity index 86% rename from patch/0102-platform-mellanox-mlxreg-hotplug-Add-support-for-han.patch rename to patches-sonic/0039-platform-mellanox-mlxreg-hotplug-Add-support-for-han.patch index 73cf24f9e..7ffede213 100644 --- a/patch/0102-platform-mellanox-mlxreg-hotplug-Add-support-for-han.patch +++ b/patches-sonic/0039-platform-mellanox-mlxreg-hotplug-Add-support-for-han.patch @@ -1,8 +1,8 @@ -From 4a7d1fd44e3394961878761ba0c53f516f31d618 Mon Sep 17 00:00:00 2001 +From daa051d1b20b132d7dd8f5b3d1312084f25f392d Mon Sep 17 00:00:00 2001 From: Roy Cohen Date: Mon, 13 Jan 2025 10:50:25 +0200 -Subject: [PATCH platform-next 2/2] platform/mellanox: mlxreg-hotplug: Add - support for handling interrupt storm +Subject: [PATCH 39/78] platform/mellanox: mlxreg-hotplug: Add support for + handling interrupt storm In case of broken hardware, it is possible that broken device will flood interrupt handler with false events. @@ -27,11 +27,11 @@ replace broken device. Signed-off-by: Roy Cohen --- - drivers/platform/mellanox/mlxreg-hotplug.c | 36 ++++++++++++++++++++-- + drivers/platform/mellanox/mlxreg-hotplug.c | 36 +++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/drivers/platform/mellanox/mlxreg-hotplug.c b/drivers/platform/mellanox/mlxreg-hotplug.c -index 3737af0d3e43..37d4c02c128a 100644 +index 51dac7e..2b52610 100644 --- a/drivers/platform/mellanox/mlxreg-hotplug.c +++ b/drivers/platform/mellanox/mlxreg-hotplug.c @@ -11,6 +11,7 @@ @@ -40,9 +40,9 @@ index 3737af0d3e43..37d4c02c128a 100644 #include +#include #include - #include #include -@@ -31,6 +32,11 @@ + #include +@@ -30,6 +31,11 @@ #define MLXREG_HOTPLUG_ATTRS_MAX 128 #define MLXREG_HOTPLUG_NOT_ASSERT 3 @@ -54,7 +54,7 @@ index 3737af0d3e43..37d4c02c128a 100644 /** * struct mlxreg_hotplug_priv_data - platform private data: * @irq: platform device interrupt number; -@@ -364,7 +370,7 @@ mlxreg_hotplug_work_helper(struct mlxreg_hotplug_priv_data *priv, +@@ -363,7 +369,7 @@ mlxreg_hotplug_work_helper(struct mlxreg_hotplug_priv_data *priv, struct mlxreg_core_item *item) { struct mlxreg_core_data *data; @@ -63,7 +63,7 @@ index 3737af0d3e43..37d4c02c128a 100644 u32 regval, bit; int ret; -@@ -400,11 +406,35 @@ mlxreg_hotplug_work_helper(struct mlxreg_hotplug_priv_data *priv, +@@ -385,11 +391,35 @@ mlxreg_hotplug_work_helper(struct mlxreg_hotplug_priv_data *priv, for_each_set_bit(bit, &asserted, 8) { int pos; @@ -99,7 +99,7 @@ index 3737af0d3e43..37d4c02c128a 100644 if (regval & BIT(bit)) { if (item->inversed) mlxreg_hotplug_device_destroy(priv, data, item->kind); -@@ -424,9 +454,9 @@ mlxreg_hotplug_work_helper(struct mlxreg_hotplug_priv_data *priv, +@@ -409,9 +439,9 @@ mlxreg_hotplug_work_helper(struct mlxreg_hotplug_priv_data *priv, if (ret) goto out; @@ -107,10 +107,10 @@ index 3737af0d3e43..37d4c02c128a 100644 + /* Unmask event, exclude storming bits. */ ret = regmap_write(priv->regmap, item->reg + MLXREG_HOTPLUG_MASK_OFF, - item->mask); -+ item->mask & ~item->storming_bits); +++ item->mask & ~item->storming_bits); out: if (ret) -- -2.44.0 +2.8.4 diff --git a/patch/0103-platform-mellanox-mlx-dpu-improve-interrupt-handling.patch b/patches-sonic/0040-platform-mellanox-mlxreg-dpu-Introduce-completion-ca.patch similarity index 74% rename from patch/0103-platform-mellanox-mlx-dpu-improve-interrupt-handling.patch rename to patches-sonic/0040-platform-mellanox-mlxreg-dpu-Introduce-completion-ca.patch index 6bf10290e..f71f3b92a 100644 --- a/patch/0103-platform-mellanox-mlx-dpu-improve-interrupt-handling.patch +++ b/patches-sonic/0040-platform-mellanox-mlxreg-dpu-Introduce-completion-ca.patch @@ -1,10 +1,8 @@ -From edf1951c7f5e87a9b6c2ad82bd97866012f552a6 Mon Sep 17 00:00:00 2001 +From e3a655f23fa819710390f2ff27573d47449246c4 Mon Sep 17 00:00:00 2001 From: Ciju Rajan K Date: Tue, 25 Mar 2025 11:20:04 +0200 -Subject: [PATCH 01/22] From 4b17e10a22771fcd2dbb4754c43200af2fc69425 Mon Sep - 17 00:00:00 2001 From: Ciju Rajan K Date: Tue, 18 Mar - 2025 21:15:00 +0200 Subject: platform/mellanox: mlxreg-dpu: Introduce - completion callback +Subject: [PATCH 40/78] platform/mellanox: mlxreg-dpu: Introduce completion + callback DPU auxiliary powering can cause interrupt flooding because DPU interrupt handlers are not configured yet, while middle @@ -20,25 +18,25 @@ registers. Signed-off-by: Vadim Pasternak Signed-off-by: Ciju Rajan K --- - drivers/platform/mellanox/mlx-platform.c | 28 +++++++++++++++++++++--- - drivers/platform/mellanox/mlxreg-dpu.c | 8 +++++++ + drivers/platform/mellanox/mlx-platform.c | 25 ++++++++++++++++++++++++- + drivers/platform/mellanox/mlxreg-dpu.c | 6 ++++++ include/linux/platform_data/mlxreg.h | 4 ++++ - 3 files changed, 37 insertions(+), 3 deletions(-) + 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index b1713d805..d2dfdac34 100644 +index a607fd6..4242b13 100644 --- a/drivers/platform/mellanox/mlx-platform.c +++ b/drivers/platform/mellanox/mlx-platform.c -@@ -2198,6 +2198,8 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = { +@@ -1496,6 +1496,8 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = { }, }; +#define MLXPLAT_SMART_SWITCH_SLOT_TO_MASK(s) (GENMASK((s) * 2 - 1, (s) * 2 - 2)) + - static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_lc_act = { -@@ -3334,6 +3336,23 @@ static struct mlxreg_core_item mlxplat_mlxcpld_smart_switch_items[] = { + .irq = MLXPLAT_CPLD_LPC_SYSIRQ, +@@ -2792,6 +2794,23 @@ static struct mlxreg_core_item mlxplat_mlxcpld_smart_switch_items[] = { }, }; @@ -62,7 +60,7 @@ index b1713d805..d2dfdac34 100644 static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_smart_switch_data = { .items = mlxplat_mlxcpld_smart_switch_items, -@@ -3371,24 +3390,28 @@ static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_dpu_data[] = { +@@ -2829,24 +2848,28 @@ static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_dpu_data[] = { .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[0], .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE, .slot = 1, @@ -84,36 +82,34 @@ index b1713d805..d2dfdac34 100644 }, { .label = "dpu4", -- .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[2], -+ .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[3], + .hpdev.brdinfo = &mlxplat_mlxcpld_smart_switch_dpu_devs[3], .hpdev.nr = MLXPLAT_CPLD_NR_DPU_BASE + 3, .slot = 4, + .completion_notify = mlxplat_dpu_completion_notify, }, }; -@@ -8018,8 +8041,6 @@ static const struct reg_default mlxplat_mlxcpld_regmap_smart_switch[] = { +@@ -6843,7 +6866,6 @@ static const struct reg_default mlxplat_mlxcpld_regmap_smart_switch[] = { { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, -- { MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET, -- MLXPLAT_CPLD_LPC_SM_SW_MASK }, +- { MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET, MLXPLAT_CPLD_LPC_SM_SW_MASK }, }; struct mlxplat_mlxcpld_regmap_context { -@@ -9333,6 +9354,7 @@ static int mlxplat_post_init(struct mlxplat_priv *priv) - /* Add DPU drivers. */ - for (j = 0; j < MLXPLAT_CPLD_DPU_MAX_DEVS; j++) { - if (mlxplat_dpu_data[j]) { -+ mlxplat_dpu_data[j]->handle = priv->regmap; - priv->pdev_dpu[j] = +@@ -7897,6 +7919,7 @@ static int mlxplat_platdevs_init(struct mlxplat_priv *priv) + for (i = 0; i < MLXPLAT_CPLD_DPU_MAX_DEVS; i++) { + if (!mlxplat_dpu_data[i]) + continue; ++ mlxplat_dpu_data[i]->handle = priv->regmap; + priv->pdev_dpu[i] = platform_device_register_resndata(&mlxplat_dev->dev, "mlxreg-dpu", - j, NULL, 0, mlxplat_dpu_data[j], + i, NULL, 0, mlxplat_dpu_data[i], diff --git a/drivers/platform/mellanox/mlxreg-dpu.c b/drivers/platform/mellanox/mlxreg-dpu.c -index b7685012d..aa8923c49 100644 +index 5226010..314385c 100644 --- a/drivers/platform/mellanox/mlxreg-dpu.c +++ b/drivers/platform/mellanox/mlxreg-dpu.c -@@ -581,6 +581,14 @@ static int mlxreg_dpu_probe(struct platform_device *pdev) +@@ -575,8 +575,14 @@ static int mlxreg_dpu_probe(struct platform_device *pdev) if (err) goto mlxreg_dpu_config_init_fail; @@ -121,15 +117,15 @@ index b7685012d..aa8923c49 100644 + if (err) + goto mlxreg_dpu_completion_notify_fail; + -+ return err; -+ + return err; + +mlxreg_dpu_completion_notify_fail: + mlxreg_dpu_config_exit(mlxreg_dpu); mlxreg_dpu_config_init_fail: regcache_sync_fail: devm_regmap_init_i2c_fail: diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_data/mlxreg.h -index 67dddacfa..e8f2032b3 100644 +index 97042f6..84c94b3 100644 --- a/include/linux/platform_data/mlxreg.h +++ b/include/linux/platform_data/mlxreg.h @@ -136,6 +136,8 @@ struct mlxreg_hotplug_device { @@ -151,5 +147,5 @@ index 67dddacfa..e8f2032b3 100644 /** -- -2.44.0 +2.8.4 diff --git a/patches-sonic/0041-hwmon-add-MP2869-MP29608-MP29612-and-MP29816-series-.patch b/patches-sonic/0041-hwmon-add-MP2869-MP29608-MP29612-and-MP29816-series-.patch new file mode 100644 index 000000000..2db37ff02 --- /dev/null +++ b/patches-sonic/0041-hwmon-add-MP2869-MP29608-MP29612-and-MP29816-series-.patch @@ -0,0 +1,993 @@ +From 293cfacacafbb7e9c088d47676c4ac2eee7fe4a8 Mon Sep 17 00:00:00 2001 +From: Wensheng Wang +Date: Thu, 24 Jul 2025 17:13:04 +0800 +Subject: [PATCH 41/78] hwmon: add MP2869,MP29608,MP29612 and MP29816 series + driver + +Add support for MPS VR mp2869/mp2869a,mp29608/mp29608a,mp29612/mp29612a +and mp29816/mp29816a/mp29816b/mp29816c controller. This driver exposes +telemetry and limit value readings and writtings. + +Signed-off-by: Wensheng Wang +--- + Documentation/hwmon/index.rst | 1 + + Documentation/hwmon/mp2869.rst | 175 ++++++++++ + MAINTAINERS | 7 + + drivers/hwmon/pmbus/Kconfig | 9 + + drivers/hwmon/pmbus/Makefile | 1 + + drivers/hwmon/pmbus/mp2869.c | 719 +++++++++++++++++++++++++++++++++++++++++ + 6 files changed, 912 insertions(+) + create mode 100644 Documentation/hwmon/mp2869.rst + create mode 100644 drivers/hwmon/pmbus/mp2869.c + +diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst +index ea3b5be..1c91bbf 100644 +--- a/Documentation/hwmon/index.rst ++++ b/Documentation/hwmon/index.rst +@@ -163,6 +163,7 @@ Hardware Monitoring Kernel Drivers + menf21bmc + mlxreg-fan + mp2856 ++ mp2869 + mp2888 + mp2891 + mp2975 +diff --git a/Documentation/hwmon/mp2869.rst b/Documentation/hwmon/mp2869.rst +new file mode 100644 +index 00000000..2d9d65fc +--- /dev/null ++++ b/Documentation/hwmon/mp2869.rst +@@ -0,0 +1,175 @@ ++.. SPDX-License-Identifier: GPL-2.0 ++ ++Kernel driver mp2869 ++==================== ++ ++Supported chips: ++ ++ * MPS mp2869 ++ ++ Prefix: 'mp2869' ++ ++ * MPS mp29608 ++ ++ Prefix: 'mp29608' ++ ++ * MPS mp29612 ++ ++ Prefix: 'mp29612' ++ ++ * MPS mp29816 ++ ++ Prefix: 'mp29816' ++ ++Author: ++ ++ Wensheng Wang ++ ++Description ++----------- ++ ++This driver implements support for Monolithic Power Systems, Inc. (MPS) ++MP2869 Dual Loop Digital Multi-phase Controller. ++ ++Device compliant with: ++ ++- PMBus rev 1.3 interface. ++ ++The driver exports the following attributes via the 'sysfs' files ++for input voltage: ++ ++**in1_input** ++ ++**in1_label** ++ ++**in1_crit** ++ ++**in1_crit_alarm** ++ ++**in1_lcrit** ++ ++**in1_lcrit_alarm** ++ ++**in1_min** ++ ++**in1_min_alarm** ++ ++The driver provides the following attributes for output voltage: ++ ++**in2_input** ++ ++**in2_label** ++ ++**in2_crit** ++ ++**in2_crit_alarm** ++ ++**in2_lcrit** ++ ++**in2_lcrit_alarm** ++ ++**in3_input** ++ ++**in3_label** ++ ++**in3_crit** ++ ++**in3_crit_alarm** ++ ++**in3_lcrit** ++ ++**in3_lcrit_alarm** ++ ++The driver provides the following attributes for input current: ++ ++**curr1_input** ++ ++**curr1_label** ++ ++**curr2_input** ++ ++**curr2_label** ++ ++The driver provides the following attributes for output current: ++ ++**curr3_input** ++ ++**curr3_label** ++ ++**curr3_crit** ++ ++**curr3_crit_alarm** ++ ++**curr3_max** ++ ++**curr3_max_alarm** ++ ++**curr4_input** ++ ++**curr4_label** ++ ++**curr4_crit** ++ ++**curr4_crit_alarm** ++ ++**curr4_max** ++ ++**curr4_max_alarm** ++ ++The driver provides the following attributes for input power: ++ ++**power1_input** ++ ++**power1_label** ++ ++**power2_input** ++ ++**power2_label** ++ ++The driver provides the following attributes for output power: ++ ++**power3_input** ++ ++**power3_label** ++ ++**power3_input** ++ ++**power3_label** ++ ++**power3_max** ++ ++**power3_max_alarm** ++ ++**power4_input** ++ ++**power4_label** ++ ++**power4_input** ++ ++**power4_label** ++ ++**power4_max** ++ ++**power4_max_alarm** ++ ++The driver provides the following attributes for temperature: ++ ++**temp1_input** ++ ++**temp1_crit** ++ ++**temp1_crit_alarm** ++ ++**temp1_max** ++ ++**temp1_max_alarm** ++ ++**temp2_input** ++ ++**temp2_crit** ++ ++**temp2_crit_alarm** ++ ++**temp2_max** ++ ++**temp2_max_alarm** +diff --git a/MAINTAINERS b/MAINTAINERS +index 81730c7..c120a8e 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -15678,6 +15678,13 @@ S: Maintained + F: Documentation/devicetree/bindings/leds/backlight/mps,mp3309c.yaml + F: drivers/video/backlight/mp3309c.c + ++MPS MP2869 DRIVER ++M: Wensheng Wang ++L: linux-hwmon@vger.kernel.org ++S: Maintained ++F: Documentation/hwmon/mp2869.rst ++F: drivers/hwmon/pmbus/mp2869.c ++ + MPS MP2891 DRIVER + M: Noah Wang + L: linux-hwmon@vger.kernel.org +diff --git a/drivers/hwmon/pmbus/Kconfig b/drivers/hwmon/pmbus/Kconfig +index a4f02cad..e9a4f84 100644 +--- a/drivers/hwmon/pmbus/Kconfig ++++ b/drivers/hwmon/pmbus/Kconfig +@@ -328,6 +328,15 @@ config SENSORS_MP2856 + This driver can also be built as a module. If so, the module will + be called mp2856. + ++config SENSORS_MP2869 ++ tristate "MPS MP2869" ++ help ++ If you say yes here you get hardware monitoring support for MPS ++ MP2869 Dual Loop Digital Multi-Phase Controller. ++ ++ This driver can also be built as a module. If so, the module will ++ be called mp2869. ++ + config SENSORS_MP2888 + tristate "MPS MP2888" + help +diff --git a/drivers/hwmon/pmbus/Makefile b/drivers/hwmon/pmbus/Makefile +index d00bcc7..179e2b2 100644 +--- a/drivers/hwmon/pmbus/Makefile ++++ b/drivers/hwmon/pmbus/Makefile +@@ -35,6 +35,7 @@ obj-$(CONFIG_SENSORS_MAX31785) += max31785.o + obj-$(CONFIG_SENSORS_MAX34440) += max34440.o + obj-$(CONFIG_SENSORS_MAX8688) += max8688.o + obj-$(CONFIG_SENSORS_MP2856) += mp2856.o ++obj-$(CONFIG_SENSORS_MP2869) += mp2869.o + obj-$(CONFIG_SENSORS_MP2888) += mp2888.o + obj-$(CONFIG_SENSORS_MP2891) += mp2891.o + obj-$(CONFIG_SENSORS_MP2975) += mp2975.o +diff --git a/drivers/hwmon/pmbus/mp2869.c b/drivers/hwmon/pmbus/mp2869.c +new file mode 100644 +index 00000000..04502e5 +--- /dev/null ++++ b/drivers/hwmon/pmbus/mp2869.c +@@ -0,0 +1,719 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers(MP2869) ++ */ ++ ++#include ++#include ++#include ++#include ++#include "pmbus.h" ++ ++/* ++ * Vender specific registers, the register MFR_VOUT_SCALE_LOOP(0x29), ++ * MFR_SVI3_IOUT_PRT(0x67), READ_PIN_EST(0x94)and READ_IIN_EST(0x95) ++ * redefine the standard PMBUS register. The MFR_VOUT_LOOP_CTRL(0x29) ++ * is used to identify the vout scale and the MFR_SVI3_IOUT_PRT(0x67) ++ * is used to identify the iout scale. The READ_PIN_EST(0x94) is used ++ * to read input power per rail. The MP2891 does not have standard ++ * READ_IIN register(0x89), the iin telemetry can be obtained through ++ * the vendor redefined register READ_IIN_EST(0x95). ++ */ ++#define MFR_VOUT_SCALE_LOOP 0x29 ++#define MFR_SVI3_IOUT_PRT 0x67 ++#define MFR_READ_PIN_EST 0x94 ++#define MFR_READ_IIN_EST 0x95 ++#define MFR_TSNS_FLT_SET 0xBB ++ ++#define MP2869_VIN_OV_FAULT_GAIN 4 ++#define MP2869_READ_VOUT_DIV 1024 ++#define MP2869_READ_IOUT_DIV 32 ++#define MP2869_OVUV_LIMIT_SCALE 10 ++#define MP2869_OVUV_DELTA_SCALE 50 ++#define MP2869_TEMP_LIMIT_OFFSET 40 ++#define MP2869_IOUT_LIMIT_UINT 8 ++#define MP2869_POUT_OP_GAIN 2 ++ ++#define MP2869_PAGE_NUM 2 ++ ++#define MP2869_RAIL1_FUNC (PMBUS_HAVE_VIN | PMBUS_HAVE_VOUT | \ ++ PMBUS_HAVE_IOUT | PMBUS_HAVE_POUT | \ ++ PMBUS_HAVE_TEMP | PMBUS_HAVE_PIN | \ ++ PMBUS_HAVE_IIN | \ ++ PMBUS_HAVE_STATUS_VOUT | \ ++ PMBUS_HAVE_STATUS_IOUT | \ ++ PMBUS_HAVE_STATUS_TEMP | \ ++ PMBUS_HAVE_STATUS_INPUT) ++ ++#define MP2869_RAIL2_FUNC (PMBUS_HAVE_VOUT | PMBUS_HAVE_IOUT | \ ++ PMBUS_HAVE_POUT | PMBUS_HAVE_TEMP | \ ++ PMBUS_HAVE_PIN | PMBUS_HAVE_IIN | \ ++ PMBUS_HAVE_STATUS_VOUT | \ ++ PMBUS_HAVE_STATUS_IOUT | \ ++ PMBUS_HAVE_STATUS_TEMP | \ ++ PMBUS_HAVE_STATUS_INPUT) ++ ++enum chips {mp2869, mp29608, mp29612, mp29816}; ++ ++struct mp2869_data { ++ struct pmbus_driver_info info; ++ bool mfr_thwn_flt_en; ++ int vout_scale[MP2869_PAGE_NUM]; ++ int iout_scale[MP2869_PAGE_NUM]; ++}; ++ ++#define to_mp2869_data(x) container_of(x, struct mp2869_data, info) ++ ++static u16 mp2869_reg2data_linear11(u16 word) ++{ ++ s16 exponent; ++ s32 mantissa; ++ s64 val; ++ ++ exponent = ((s16)word) >> 11; ++ mantissa = ((s16)((word & 0x7ff) << 5)) >> 5; ++ val = mantissa; ++ ++ if (exponent >= 0) ++ val <<= exponent; ++ else ++ val >>= -exponent; ++ ++ return val; ++} ++ ++static int ++mp2869_identify_thwn_flt(struct i2c_client *client, struct pmbus_driver_info *info, ++ int page) ++{ ++ struct mp2869_data *data = to_mp2869_data(info); ++ int ret; ++ ++ ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, page); ++ if (ret < 0) ++ return ret; ++ ++ ret = i2c_smbus_read_word_data(client, MFR_TSNS_FLT_SET); ++ if (ret < 0) ++ return ret; ++ ++ if (FIELD_GET(GENMASK(13, 13), ret)) ++ data->mfr_thwn_flt_en = true; ++ else ++ data->mfr_thwn_flt_en = false; ++ ++ return 0; ++} ++ ++static int ++mp2869_identify_vout_scale(struct i2c_client *client, struct pmbus_driver_info *info, ++ int page) ++{ ++ struct mp2869_data *data = to_mp2869_data(info); ++ int ret; ++ ++ ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, page); ++ if (ret < 0) ++ return ret; ++ ++ ret = i2c_smbus_read_word_data(client, MFR_VOUT_SCALE_LOOP); ++ if (ret < 0) ++ return ret; ++ ++ /* ++ * The output voltage is equal to the READ_VOUT(0x8B) register value multiply ++ * by vout_scale. ++ * Obtain vout scale from the register MFR_VOUT_SCALE_LOOP, bits 12-10 ++ * MFR_VOUT_SCALE_LOOP[12:10]: ++ * 000b - 6.25mV/LSB, 001b - 5mV/LSB, 010b - 2.5mV/LSB, 011b - 2mV/LSB ++ * 100b - 1mV/Lsb, 101b - (1/256)mV/LSB, 110b - (1/512)mV/LSB, ++ * 111b - (1/1024)mV/LSB ++ */ ++ switch (FIELD_GET(GENMASK(12, 10), ret)) { ++ case 0: ++ data->vout_scale[page] = 6400; ++ break; ++ case 1: ++ data->vout_scale[page] = 5120; ++ break; ++ case 2: ++ data->vout_scale[page] = 2560; ++ break; ++ case 3: ++ data->vout_scale[page] = 2048; ++ break; ++ case 4: ++ data->vout_scale[page] = 1024; ++ break; ++ case 5: ++ data->vout_scale[page] = 4; ++ break; ++ case 6: ++ data->vout_scale[page] = 2; ++ break; ++ case 7: ++ data->vout_scale[page] = 1; ++ break; ++ default: ++ data->vout_scale[page] = 1; ++ break; ++ } ++ ++ return 0; ++} ++ ++static int ++mp2869_identify_iout_scale(struct i2c_client *client, struct pmbus_driver_info *info, ++ int page) ++{ ++ struct mp2869_data *data = to_mp2869_data(info); ++ int ret; ++ ++ ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, page); ++ if (ret < 0) ++ return ret; ++ ++ ret = i2c_smbus_read_word_data(client, MFR_SVI3_IOUT_PRT); ++ if (ret < 0) ++ return ret; ++ ++ /* ++ * The output current is equal to the READ_IOUT(0x8C) register value ++ * multiply by iout_scale. ++ * Obtain iout_scale from the register MFR_SVI3_IOUT_PRT[2:0]. ++ * The value is selected as below: ++ * 000b - 1A/LSB, 001b - (1/32)A/LSB, 010b - (1/16)A/LSB, ++ * 011b - (1/8)A/LSB, 100b - (1/4)A/LSB, 101b - (1/2)A/LSB ++ * 110b - 1A/LSB, 111b - 2A/LSB ++ */ ++ switch (ret & GENMASK(2, 0)) { ++ case 0: ++ case 6: ++ data->iout_scale[page] = 32; ++ break; ++ case 1: ++ data->iout_scale[page] = 1; ++ break; ++ case 2: ++ data->iout_scale[page] = 2; ++ break; ++ case 3: ++ data->iout_scale[page] = 4; ++ break; ++ case 4: ++ data->iout_scale[page] = 8; ++ break; ++ case 5: ++ data->iout_scale[page] = 16; ++ break; ++ default: ++ data->iout_scale[page] = 64; ++ break; ++ } ++ ++ return 0; ++} ++ ++static int mp2869_read_byte_data(struct i2c_client *client, int page, int reg) ++{ ++ const struct pmbus_driver_info *info = pmbus_get_driver_info(client); ++ struct mp2869_data *data = to_mp2869_data(info); ++ int ret; ++ ++ switch (reg) { ++ case PMBUS_VOUT_MODE: ++ /* ++ * The calculation of vout in this driver is based on direct format. ++ * As a result, the format of vout is enforced to direct. ++ */ ++ ret = PB_VOUT_MODE_DIRECT; ++ break; ++ case PMBUS_STATUS_BYTE: ++ /* ++ * If the tsns digital fault is enabled, the TEMPERATURE flag ++ * of PMBUS_STATUS_BYTE should come from STATUS_MFR_SPECIFIC ++ * register bit1. ++ */ ++ if (data->mfr_thwn_flt_en) { ++ ret = pmbus_read_byte_data(client, page, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = (ret & ~GENMASK(2, 2)) | ++ FIELD_PREP(GENMASK(2, 2), ++ FIELD_GET(GENMASK(1, 1), ++ pmbus_read_byte_data(client, page, ++ PMBUS_STATUS_MFR_SPECIFIC))); ++ } else { ++ ret = -ENODATA; ++ } ++ break; ++ case PMBUS_STATUS_TEMPERATURE: ++ /* ++ * If the tsns digital fault is enabled, the OT Fault and OT Warning ++ * flag of PMBUS_STATUS_TEMPERATURE should come from STATUS_MFR_SPECIFIC ++ * register bit1. ++ */ ++ if (data->mfr_thwn_flt_en) { ++ ret = pmbus_read_byte_data(client, page, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = (ret & ~GENMASK(7, 6)) | ++ FIELD_PREP(GENMASK(6, 6), ++ FIELD_GET(GENMASK(1, 1), ++ pmbus_read_byte_data(client, page, ++ PMBUS_STATUS_MFR_SPECIFIC))) | ++ FIELD_PREP(GENMASK(7, 7), ++ FIELD_GET(GENMASK(1, 1), ++ pmbus_read_byte_data(client, page, ++ PMBUS_STATUS_MFR_SPECIFIC))); ++ } else { ++ ret = -ENODATA; ++ } ++ break; ++ default: ++ ret = -ENODATA; ++ break; ++ } ++ ++ return ret; ++} ++ ++static int mp2869_read_word_data(struct i2c_client *client, int page, int phase, ++ int reg) ++{ ++ const struct pmbus_driver_info *info = pmbus_get_driver_info(client); ++ struct mp2869_data *data = to_mp2869_data(info); ++ int ret; ++ ++ switch (reg) { ++ case PMBUS_STATUS_WORD: ++ /* ++ * If the tsns digital fault is enabled, the OT Fault flag ++ * of PMBUS_STATUS_WORD should come from STATUS_MFR_SPECIFIC ++ * register bit1. ++ */ ++ if (data->mfr_thwn_flt_en) { ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = (ret & ~GENMASK(2, 2)) | ++ FIELD_PREP(GENMASK(2, 2), ++ FIELD_GET(GENMASK(1, 1), ++ pmbus_read_byte_data(client, page, ++ PMBUS_STATUS_MFR_SPECIFIC))); ++ } else { ++ ret = -ENODATA; ++ } ++ break; ++ case PMBUS_READ_VIN: ++ /* ++ * The MP2869 PMBUS_READ_VIN[10:0] is the vin value, the vin scale is ++ * 31.25mV/LSB. And the vin scale is set to 31.25mV/Lsb(using r/m/b scale) ++ * in MP2869 pmbus_driver_info struct, so the word data bit0-bit10 can be ++ * returned to pmbus core directly. ++ */ ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = FIELD_GET(GENMASK(10, 0), ret); ++ break; ++ case PMBUS_READ_IIN: ++ /* ++ * The MP2869 redefine the standard 0x95 register as iin telemetry ++ * per rail. ++ */ ++ ret = pmbus_read_word_data(client, page, phase, MFR_READ_IIN_EST); ++ if (ret < 0) ++ return ret; ++ ++ break; ++ case PMBUS_READ_PIN: ++ /* ++ * The MP2869 redefine the standard 0x94 register as pin telemetry ++ * per rail. The MP2869 MFR_READ_PIN_EST register is linear11 format, ++ * but the pin scale is set to 1W/Lsb(using r/m/b scale). As a result, ++ * the pin read from MP2869 should be converted to W, then return ++ * the result to pmbus core. ++ */ ++ ret = pmbus_read_word_data(client, page, phase, MFR_READ_PIN_EST); ++ if (ret < 0) ++ return ret; ++ ++ ret = mp2869_reg2data_linear11(ret); ++ break; ++ case PMBUS_READ_VOUT: ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = DIV_ROUND_CLOSEST((ret & GENMASK(11, 0)) * data->vout_scale[page], ++ MP2869_READ_VOUT_DIV); ++ break; ++ case PMBUS_READ_IOUT: ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = DIV_ROUND_CLOSEST((ret & GENMASK(10, 0)) * data->iout_scale[page], ++ MP2869_READ_IOUT_DIV); ++ break; ++ case PMBUS_READ_POUT: ++ /* ++ * The MP2869 PMBUS_READ_POUT register is linear11 format, but the pout ++ * scale is set to 1W/Lsb(using r/m/b scale). As a result, the pout read ++ * from MP2869 should be converted to W, then return the result to pmbus ++ * core. ++ */ ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = mp2869_reg2data_linear11(ret); ++ break; ++ case PMBUS_READ_TEMPERATURE_1: ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = FIELD_GET(GENMASK(10, 0), ret); ++ break; ++ case PMBUS_VOUT_OV_FAULT_LIMIT: ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ if (FIELD_GET(GENMASK(12, 9), ret)) ++ ret = FIELD_GET(GENMASK(8, 0), ret) * MP2869_OVUV_LIMIT_SCALE + ++ (FIELD_GET(GENMASK(12, 9), ret) + 1) * MP2869_OVUV_DELTA_SCALE; ++ else ++ ret = FIELD_GET(GENMASK(8, 0), ret) * MP2869_OVUV_LIMIT_SCALE; ++ break; ++ case PMBUS_VOUT_UV_FAULT_LIMIT: ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ if (FIELD_GET(GENMASK(12, 9), ret)) ++ ret = FIELD_GET(GENMASK(8, 0), ret) * MP2869_OVUV_LIMIT_SCALE - ++ (FIELD_GET(GENMASK(12, 9), ret) + 1) * MP2869_OVUV_DELTA_SCALE; ++ else ++ ret = FIELD_GET(GENMASK(8, 0), ret) * MP2869_OVUV_LIMIT_SCALE; ++ ++ ret = ret < 0 ? 0 : ret; ++ break; ++ case PMBUS_OT_FAULT_LIMIT: ++ case PMBUS_OT_WARN_LIMIT: ++ /* ++ * The scale of MP2869 PMBUS_OT_FAULT_LIMIT and PMBUS_OT_WARN_LIMIT ++ * is 1°C/LSB and they have 40°C offset. ++ */ ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = (ret & GENMASK(7, 0)) - MP2869_TEMP_LIMIT_OFFSET; ++ break; ++ case PMBUS_VIN_OV_FAULT_LIMIT: ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = (ret & GENMASK(7, 0)) * MP2869_VIN_OV_FAULT_GAIN; ++ break; ++ case PMBUS_VIN_UV_WARN_LIMIT: ++ case PMBUS_VIN_UV_FAULT_LIMIT: ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = FIELD_GET(GENMASK(9, 0), ret); ++ break; ++ case PMBUS_IOUT_OC_FAULT_LIMIT: ++ case PMBUS_IOUT_OC_WARN_LIMIT: ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = DIV_ROUND_CLOSEST((ret & GENMASK(7, 0)) * data->iout_scale[page] * ++ MP2869_IOUT_LIMIT_UINT, MP2869_READ_IOUT_DIV); ++ break; ++ case PMBUS_POUT_OP_WARN_LIMIT: ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = (ret & GENMASK(7, 0)) * MP2869_POUT_OP_GAIN; ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ return ret; ++} ++ ++static int mp2869_write_word_data(struct i2c_client *client, int page, int reg, ++ u16 word) ++{ ++ const struct pmbus_driver_info *info = pmbus_get_driver_info(client); ++ struct mp2869_data *data = to_mp2869_data(info); ++ int ret; ++ ++ switch (reg) { ++ case PMBUS_VOUT_UV_FAULT_LIMIT: ++ /* ++ * The MP2869 PMBUS_VOUT_UV_FAULT_LIMIT[8:0] is the limit value, ++ * and bit9-bit15 should not be changed. ++ */ ++ ret = pmbus_read_word_data(client, page, 0xff, reg); ++ if (ret < 0) ++ return ret; ++ ++ if (FIELD_GET(GENMASK(12, 9), ret)) ++ ret = pmbus_write_word_data(client, page, reg, ++ (ret & ~GENMASK(8, 0)) | ++ FIELD_PREP(GENMASK(8, 0), ++ DIV_ROUND_CLOSEST(word + ++ (FIELD_GET(GENMASK(12, 9), ++ ret) + 1) * ++ MP2869_OVUV_DELTA_SCALE, ++ MP2869_OVUV_LIMIT_SCALE))); ++ else ++ ret = pmbus_write_word_data(client, page, reg, ++ (ret & ~GENMASK(8, 0)) | ++ FIELD_PREP(GENMASK(8, 0), ++ DIV_ROUND_CLOSEST(word, ++ MP2869_OVUV_LIMIT_SCALE))); ++ break; ++ case PMBUS_VOUT_OV_FAULT_LIMIT: ++ /* ++ * The MP2869 PMBUS_VOUT_OV_FAULT_LIMIT[8:0] is the limit value, ++ * and bit9-bit15 should not be changed. ++ */ ++ ret = pmbus_read_word_data(client, page, 0xff, reg); ++ if (ret < 0) ++ return ret; ++ ++ if (FIELD_GET(GENMASK(12, 9), ret)) ++ ret = pmbus_write_word_data(client, page, reg, ++ (ret & ~GENMASK(8, 0)) | ++ FIELD_PREP(GENMASK(8, 0), ++ DIV_ROUND_CLOSEST(word - ++ (FIELD_GET(GENMASK(12, 9), ++ ret) + 1) * ++ MP2869_OVUV_DELTA_SCALE, ++ MP2869_OVUV_LIMIT_SCALE))); ++ else ++ ret = pmbus_write_word_data(client, page, reg, ++ (ret & ~GENMASK(8, 0)) | ++ FIELD_PREP(GENMASK(8, 0), ++ DIV_ROUND_CLOSEST(word, ++ MP2869_OVUV_LIMIT_SCALE))); ++ break; ++ case PMBUS_OT_FAULT_LIMIT: ++ case PMBUS_OT_WARN_LIMIT: ++ /* ++ * If the tsns digital fault is enabled, the PMBUS_OT_FAULT_LIMIT and ++ * PMBUS_OT_WARN_LIMIT can not be written. ++ */ ++ if (data->mfr_thwn_flt_en) { ++ ret = -EINVAL; ++ } else { ++ /* ++ * The MP2869 scale of MP2869 PMBUS_OT_FAULT_LIMIT and PMBUS_OT_WARN_LIMIT ++ * have 40°C offset. The bit0-bit7 is the limit value, and bit8-bit15 ++ * should not be changed. ++ */ ++ ret = pmbus_read_word_data(client, page, 0xff, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = pmbus_write_word_data(client, page, reg, ++ (ret & ~GENMASK(7, 0)) | ++ FIELD_PREP(GENMASK(7, 0), ++ word + MP2869_TEMP_LIMIT_OFFSET)); ++ } ++ break; ++ case PMBUS_VIN_OV_FAULT_LIMIT: ++ /* ++ * The MP2869 PMBUS_VIN_OV_FAULT_LIMIT[7:0] is the limit value, and bit8-bit15 ++ * should not be changed. The scale of PMBUS_VIN_OV_FAULT_LIMIT is 125mV/Lsb, ++ * but the vin scale is set to 31.25mV/Lsb(using r/m/b scale), so the word data ++ * should divide by MP2869_VIN_OV_FAULT_GAIN(4) ++ */ ++ ret = pmbus_read_word_data(client, page, 0xff, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = pmbus_write_word_data(client, page, reg, ++ (ret & ~GENMASK(7, 0)) | ++ FIELD_PREP(GENMASK(7, 0), ++ DIV_ROUND_CLOSEST(word, ++ MP2869_VIN_OV_FAULT_GAIN))); ++ break; ++ case PMBUS_VIN_UV_WARN_LIMIT: ++ case PMBUS_VIN_UV_FAULT_LIMIT: ++ /* ++ * The PMBUS_VIN_UV_LIMIT[9:0] is the limit value, and bit10-bit15 should ++ * not be changed. The scale of PMBUS_VIN_UV_LIMIT is 31.25mV/Lsb, and the ++ * vin scale is set to 31.25mV/Lsb(using r/m/b scale), so the word data can ++ * be written directly. ++ */ ++ ret = pmbus_read_word_data(client, page, 0xff, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = pmbus_write_word_data(client, page, reg, ++ (ret & ~GENMASK(9, 0)) | ++ FIELD_PREP(GENMASK(9, 0), ++ word)); ++ break; ++ case PMBUS_IOUT_OC_FAULT_LIMIT: ++ case PMBUS_IOUT_OC_WARN_LIMIT: ++ ret = pmbus_write_word_data(client, page, reg, ++ DIV_ROUND_CLOSEST(word * ++ MP2869_READ_IOUT_DIV, ++ MP2869_IOUT_LIMIT_UINT * ++ data->iout_scale[page])); ++ break; ++ case PMBUS_POUT_OP_WARN_LIMIT: ++ /* ++ * The POUT_OP_WARN_LIMIT[11:0] is the limit value, and bit12-bit15 should ++ * not be changed. The scale of POUT_OP_WARN_LIMIT is 2W/Lsb. ++ */ ++ ret = pmbus_read_word_data(client, page, 0xff, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = pmbus_write_word_data(client, page, reg, ++ (ret & ~GENMASK(11, 0)) | ++ FIELD_PREP(GENMASK(11, 0), ++ DIV_ROUND_CLOSEST(word, ++ MP2869_POUT_OP_GAIN))); ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ return ret; ++} ++ ++static int mp2869_identify(struct i2c_client *client, struct pmbus_driver_info *info) ++{ ++ int ret; ++ ++ /* Identify whether tsns digital fault is enable */ ++ ret = mp2869_identify_thwn_flt(client, info, 1); ++ if (ret < 0) ++ return 0; ++ ++ /* Identify vout scale for rail1. */ ++ ret = mp2869_identify_vout_scale(client, info, 0); ++ if (ret < 0) ++ return ret; ++ ++ /* Identify vout scale for rail2. */ ++ ret = mp2869_identify_vout_scale(client, info, 1); ++ if (ret < 0) ++ return ret; ++ ++ /* Identify iout scale for rail 1. */ ++ ret = mp2869_identify_iout_scale(client, info, 0); ++ if (ret < 0) ++ return ret; ++ ++ /* Identify iout scale for rail 2. */ ++ return mp2869_identify_iout_scale(client, info, 1); ++} ++ ++static const struct pmbus_driver_info mp2869_info = { ++ .pages = MP2869_PAGE_NUM, ++ .format[PSC_VOLTAGE_IN] = direct, ++ .format[PSC_CURRENT_IN] = linear, ++ .format[PSC_CURRENT_OUT] = direct, ++ .format[PSC_TEMPERATURE] = direct, ++ .format[PSC_POWER] = direct, ++ .format[PSC_VOLTAGE_OUT] = direct, ++ ++ .m[PSC_VOLTAGE_IN] = 32, ++ .R[PSC_VOLTAGE_IN] = 0, ++ .b[PSC_VOLTAGE_IN] = 0, ++ ++ .m[PSC_VOLTAGE_OUT] = 1, ++ .R[PSC_VOLTAGE_OUT] = 3, ++ .b[PSC_VOLTAGE_OUT] = 0, ++ ++ .m[PSC_CURRENT_OUT] = 1, ++ .R[PSC_CURRENT_OUT] = 0, ++ .b[PSC_CURRENT_OUT] = 0, ++ ++ .m[PSC_TEMPERATURE] = 1, ++ .R[PSC_TEMPERATURE] = 0, ++ .b[PSC_TEMPERATURE] = 0, ++ ++ .m[PSC_POWER] = 1, ++ .R[PSC_POWER] = 0, ++ .b[PSC_POWER] = 0, ++ ++ .func[0] = MP2869_RAIL1_FUNC, ++ .func[1] = MP2869_RAIL2_FUNC, ++ .read_word_data = mp2869_read_word_data, ++ .write_word_data = mp2869_write_word_data, ++ .read_byte_data = mp2869_read_byte_data, ++ .identify = mp2869_identify, ++}; ++ ++static int mp2869_probe(struct i2c_client *client) ++{ ++ struct pmbus_driver_info *info; ++ struct mp2869_data *data; ++ ++ data = devm_kzalloc(&client->dev, sizeof(struct mp2869_data), ++ GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ memcpy(&data->info, &mp2869_info, sizeof(*info)); ++ info = &data->info; ++ ++ return pmbus_do_probe(client, info); ++} ++ ++static const struct i2c_device_id mp2869_id[] = { ++ {"mp2869", mp2869}, ++ {"mp29608", mp29608}, ++ {"mp29612", mp29612}, ++ {"mp29816", mp29816}, ++ {} ++}; ++MODULE_DEVICE_TABLE(i2c, mp2869_id); ++ ++static const struct of_device_id __maybe_unused mp2869_of_match[] = { ++ {.compatible = "mps,mp2869", .data = (void *)mp2869}, ++ {.compatible = "mps,mp29608", .data = (void *)mp29608}, ++ {.compatible = "mps,mp29612", .data = (void *)mp29612}, ++ {.compatible = "mps,mp29816", .data = (void *)mp29816}, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, mp2869_of_match); ++ ++static struct i2c_driver mp2869_driver = { ++ .driver = { ++ .name = "mp2869", ++ .of_match_table = mp2869_of_match, ++ }, ++ .probe = mp2869_probe, ++ .id_table = mp2869_id, ++}; ++ ++module_i2c_driver(mp2869_driver); ++ ++MODULE_AUTHOR("Wensheng Wang "); ++MODULE_DESCRIPTION("PMBus driver for MPS MP2869"); ++MODULE_LICENSE("GPL"); ++MODULE_IMPORT_NS(PMBUS); +-- +2.8.4 + diff --git a/patches-sonic/0042-hwmon-add-MP29502-driver.patch b/patches-sonic/0042-hwmon-add-MP29502-driver.patch new file mode 100644 index 000000000..8a9392478 --- /dev/null +++ b/patches-sonic/0042-hwmon-add-MP29502-driver.patch @@ -0,0 +1,860 @@ +From 69e303de3d931aecff0e41c9689a1da675766176 Mon Sep 17 00:00:00 2001 +From: Wensheng Wang +Date: Thu, 24 Jul 2025 17:13:06 +0800 +Subject: [PATCH 42/78] hwmon: add MP29502 driver + +Add support for MPS VR controller mp29502. This driver exposes +telemetry and limits value readings and writtings. + +Signed-off-by: Wensheng Wang +--- + Documentation/hwmon/index.rst | 1 + + Documentation/hwmon/mp29502.rst | 93 ++++++ + MAINTAINERS | 7 + + drivers/hwmon/pmbus/Kconfig | 9 + + drivers/hwmon/pmbus/Makefile | 1 + + drivers/hwmon/pmbus/mp29502.c | 670 ++++++++++++++++++++++++++++++++++++++++ + 6 files changed, 781 insertions(+) + create mode 100644 Documentation/hwmon/mp29502.rst + create mode 100644 drivers/hwmon/pmbus/mp29502.c + +diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst +index 1c91bbf..fe0a5ef 100644 +--- a/Documentation/hwmon/index.rst ++++ b/Documentation/hwmon/index.rst +@@ -166,6 +166,7 @@ Hardware Monitoring Kernel Drivers + mp2869 + mp2888 + mp2891 ++ mp29502 + mp2975 + mp2993 + mp5023 +diff --git a/Documentation/hwmon/mp29502.rst b/Documentation/hwmon/mp29502.rst +new file mode 100644 +index 00000000..7743056 +--- /dev/null ++++ b/Documentation/hwmon/mp29502.rst +@@ -0,0 +1,93 @@ ++.. SPDX-License-Identifier: GPL-2.0 ++ ++Kernel driver mp29502 ++==================== ++ ++Supported chips: ++ ++ * MPS mp29502 ++ ++ Prefix: 'mp29502' ++ ++Author: ++ ++ Wensheng Wang ++ ++Description ++----------- ++ ++This driver implements support for Monolithic Power Systems, Inc. (MPS) ++MP29502 Digital Multi-phase Controller. ++ ++Device compliant with: ++ ++- PMBus rev 1.3 interface. ++ ++The driver exports the following attributes via the 'sysfs' files ++for input voltage: ++ ++**in1_input** ++ ++**in1_label** ++ ++**in1_crit** ++ ++**in1_crit_alarm** ++ ++The driver provides the following attributes for output voltage: ++ ++**in2_input** ++ ++**in2_label** ++ ++**in2_crit** ++ ++**in2_crit_alarm** ++ ++**in2_lcrit** ++ ++**in2_lcrit_alarm** ++ ++The driver provides the following attributes for input current: ++ ++**curr1_input** ++ ++**curr1_label** ++ ++The driver provides the following attributes for output current: ++ ++**curr2_input** ++ ++**curr2_label** ++ ++**curr2_crit** ++ ++**curr2_crit_alarm** ++ ++**curr2_max** ++ ++**curr2_max_alarm** ++ ++The driver provides the following attributes for input power: ++ ++**power1_input** ++ ++**power1_label** ++ ++The driver provides the following attributes for output power: ++ ++**power2_input** ++ ++**power2_label** ++ ++The driver provides the following attributes for temperature: ++ ++**temp1_input** ++ ++**temp1_crit** ++ ++**temp1_crit_alarm** ++ ++**temp1_max** ++ ++**temp1_max_alarm** +diff --git a/MAINTAINERS b/MAINTAINERS +index c120a8e..6b06d73 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -15692,6 +15692,13 @@ S: Maintained + F: Documentation/hwmon/mp2891.rst + F: drivers/hwmon/pmbus/mp2891.c + ++MPS MP29502 DRIVER ++M: Wensheng Wang ++L: linux-hwmon@vger.kernel.org ++S: Maintained ++F: Documentation/hwmon/mp29502.rst ++F: drivers/hwmon/pmbus/mp29502.c ++ + MPS MP2993 DRIVER + M: Noah Wang + L: linux-hwmon@vger.kernel.org +diff --git a/drivers/hwmon/pmbus/Kconfig b/drivers/hwmon/pmbus/Kconfig +index e9a4f84..60eabf9 100644 +--- a/drivers/hwmon/pmbus/Kconfig ++++ b/drivers/hwmon/pmbus/Kconfig +@@ -355,6 +355,15 @@ config SENSORS_MP2891 + This driver can also be built as a module. If so, the module will + be called mp2891. + ++config SENSORS_MP29502 ++ tristate "MPS MP29502" ++ help ++ If you say yes here you get hardware monitoring support for MPS ++ MP29502 Dual Loop Digital Multi-Phase Controller. ++ ++ This driver can also be built as a module. If so, the module will ++ be called mp29502. ++ + config SENSORS_MP2975 + tristate "MPS MP2975" + help +diff --git a/drivers/hwmon/pmbus/Makefile b/drivers/hwmon/pmbus/Makefile +index 179e2b2..55b0784 100644 +--- a/drivers/hwmon/pmbus/Makefile ++++ b/drivers/hwmon/pmbus/Makefile +@@ -38,6 +38,7 @@ obj-$(CONFIG_SENSORS_MP2856) += mp2856.o + obj-$(CONFIG_SENSORS_MP2869) += mp2869.o + obj-$(CONFIG_SENSORS_MP2888) += mp2888.o + obj-$(CONFIG_SENSORS_MP2891) += mp2891.o ++obj-$(CONFIG_SENSORS_MP29502) += mp29502.o + obj-$(CONFIG_SENSORS_MP2975) += mp2975.o + obj-$(CONFIG_SENSORS_MP2993) += mp2993.o + obj-$(CONFIG_SENSORS_MP5023) += mp5023.o +diff --git a/drivers/hwmon/pmbus/mp29502.c b/drivers/hwmon/pmbus/mp29502.c +new file mode 100644 +index 00000000..bee2028 +--- /dev/null ++++ b/drivers/hwmon/pmbus/mp29502.c +@@ -0,0 +1,670 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers(MP29502) ++ */ ++ ++#include ++#include ++#include ++#include ++#include "pmbus.h" ++ ++#define MFR_VOUT_SCALE_LOOP 0x29 ++#define MFR_SVI3_IOUT_PRT 0x67 ++#define MFR_READ_PIN_EST 0x94 ++#define MFR_READ_IIN_EST 0x95 ++#define MFR_VOUT_PROT1 0x3D ++#define MFR_VOUT_PROT2 0x51 ++#define MFR_SLOPE_CNT_SET 0xA8 ++#define MFR_TSNS_FLT_SET 0xBB ++ ++#define MP29502_VIN_OV_GAIN 4 ++#define MP29502_TEMP_LIMIT_OFFSET 40 ++#define MP29502_READ_VOUT_DIV 1024 ++#define MP29502_READ_IOUT_DIV 32 ++#define MP29502_IOUT_LIMIT_UINT 8 ++#define MP29502_OVUV_LIMIT_SCALE 10 ++#define MP28502_VOUT_OV_GAIN 512 ++#define MP28502_VOUT_OV_SCALE 40 ++#define MP29502_VOUT_UV_OFFSET 36 ++#define MP29502_PIN_GAIN 2 ++#define MP29502_IIN_DIV 2 ++ ++#define MP29502_PAGE_NUM 1 ++ ++#define MP29502_RAIL_FUNC (PMBUS_HAVE_VIN | PMBUS_HAVE_VOUT | \ ++ PMBUS_HAVE_IOUT | PMBUS_HAVE_POUT | \ ++ PMBUS_HAVE_TEMP | PMBUS_HAVE_PIN | \ ++ PMBUS_HAVE_IIN | \ ++ PMBUS_HAVE_STATUS_VOUT | \ ++ PMBUS_HAVE_STATUS_IOUT | \ ++ PMBUS_HAVE_STATUS_TEMP | \ ++ PMBUS_HAVE_STATUS_INPUT) ++ ++struct mp29502_data { ++ struct pmbus_driver_info info; ++ int vout_scale; ++ int vout_bottom_div; ++ int vout_top_div; ++ int ovp_div; ++ int iout_scale; ++}; ++ ++#define to_mp29502_data(x) container_of(x, struct mp29502_data, info) ++ ++static u16 mp29502_reg2data_linear11(u16 word) ++{ ++ s16 exponent; ++ s32 mantissa; ++ s64 val; ++ ++ exponent = ((s16)word) >> 11; ++ mantissa = ((s16)((word & 0x7ff) << 5)) >> 5; ++ val = mantissa; ++ ++ if (exponent >= 0) ++ val <<= exponent; ++ else ++ val >>= -exponent; ++ ++ return val; ++} ++ ++static int ++mp29502_identify_vout_scale(struct i2c_client *client, struct pmbus_driver_info *info, ++ int page) ++{ ++ struct mp29502_data *data = to_mp29502_data(info); ++ int ret; ++ ++ ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, page); ++ if (ret < 0) ++ return ret; ++ ++ ret = i2c_smbus_read_word_data(client, MFR_VOUT_SCALE_LOOP); ++ if (ret < 0) ++ return ret; ++ ++ switch (FIELD_GET(GENMASK(12, 10), ret)) { ++ case 0: ++ data->vout_scale = 6400; ++ break; ++ case 1: ++ data->vout_scale = 5120; ++ break; ++ case 2: ++ data->vout_scale = 2560; ++ break; ++ case 3: ++ data->vout_scale = 2048; ++ break; ++ case 4: ++ data->vout_scale = 1024; ++ break; ++ case 5: ++ data->vout_scale = 4; ++ break; ++ case 6: ++ data->vout_scale = 2; ++ break; ++ case 7: ++ data->vout_scale = 1; ++ break; ++ default: ++ data->vout_scale = 1; ++ break; ++ } ++ ++ return 0; ++} ++ ++static int ++mp29502_identify_vout_divider(struct i2c_client *client, struct pmbus_driver_info *info, ++ int page) ++{ ++ struct mp29502_data *data = to_mp29502_data(info); ++ int ret; ++ ++ ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, page); ++ if (ret < 0) ++ return ret; ++ ++ ret = i2c_smbus_read_word_data(client, MFR_VOUT_PROT1); ++ if (ret < 0) ++ return ret; ++ ++ data->vout_bottom_div = FIELD_GET(GENMASK(11, 0), ret); ++ ++ ret = i2c_smbus_read_word_data(client, MFR_VOUT_PROT2); ++ if (ret < 0) ++ return ret; ++ ++ data->vout_top_div = FIELD_GET(GENMASK(14, 0), ret); ++ ++ return 0; ++} ++ ++static int ++mp29502_identify_ovp_divider(struct i2c_client *client, struct pmbus_driver_info *info, ++ int page) ++{ ++ struct mp29502_data *data = to_mp29502_data(info); ++ int ret; ++ ++ ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, page); ++ if (ret < 0) ++ return ret; ++ ++ ret = i2c_smbus_read_word_data(client, MFR_SLOPE_CNT_SET); ++ if (ret < 0) ++ return ret; ++ ++ data->ovp_div = FIELD_GET(GENMASK(9, 0), ret); ++ ++ return 0; ++} ++ ++static int ++mp29502_identify_iout_scale(struct i2c_client *client, struct pmbus_driver_info *info, ++ int page) ++{ ++ struct mp29502_data *data = to_mp29502_data(info); ++ int ret; ++ ++ ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, page); ++ if (ret < 0) ++ return ret; ++ ++ ret = i2c_smbus_read_word_data(client, MFR_SVI3_IOUT_PRT); ++ if (ret < 0) ++ return ret; ++ ++ switch (ret & GENMASK(2, 0)) { ++ case 0: ++ case 6: ++ data->iout_scale = 32; ++ break; ++ case 1: ++ data->iout_scale = 1; ++ break; ++ case 2: ++ data->iout_scale = 2; ++ break; ++ case 3: ++ data->iout_scale = 4; ++ break; ++ case 4: ++ data->iout_scale = 8; ++ break; ++ case 5: ++ data->iout_scale = 16; ++ break; ++ default: ++ data->iout_scale = 64; ++ break; ++ } ++ ++ return 0; ++} ++ ++static int mp29502_read_vout_ov_limit(struct i2c_client *client, struct mp29502_data *data) ++{ ++ int ret; ++ int ov_value; ++ ++ /* ++ * This is because the vout ov fault limit value comes from ++ * page1 MFR_TSNS_FLT_SET reg, and other telemetry and limit ++ * value comes from page0 reg. So the page should be set to ++ * 0 after the reading of vout ov limit. ++ */ ++ ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, 1); ++ if (ret < 0) ++ return ret; ++ ++ ret = i2c_smbus_read_word_data(client, MFR_TSNS_FLT_SET); ++ if (ret < 0) ++ return ret; ++ ++ ov_value = DIV_ROUND_CLOSEST(FIELD_GET(GENMASK(12, 7), ret) * ++ MP28502_VOUT_OV_GAIN * MP28502_VOUT_OV_SCALE, ++ data->ovp_div); ++ ++ ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, 0); ++ if (ret < 0) ++ return ret; ++ ++ return ov_value; ++} ++ ++static int mp29502_write_vout_ov_limit(struct i2c_client *client, u16 word, ++ struct mp29502_data *data) ++{ ++ int ret; ++ ++ /* ++ * This is because the vout ov fault limit value comes from ++ * page1 MFR_TSNS_FLT_SET reg, and other telemetry and limit ++ * value comes from page0 reg. So the page should be set to ++ * 0 after the writing of vout ov limit. ++ */ ++ ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, 1); ++ if (ret < 0) ++ return ret; ++ ++ ret = i2c_smbus_read_word_data(client, MFR_TSNS_FLT_SET); ++ if (ret < 0) ++ return ret; ++ ++ ret = i2c_smbus_write_word_data(client, MFR_TSNS_FLT_SET, ++ (ret & ~GENMASK(12, 7)) | ++ FIELD_PREP(GENMASK(12, 7), ++ DIV_ROUND_CLOSEST(word * data->ovp_div, ++ MP28502_VOUT_OV_GAIN * MP28502_VOUT_OV_SCALE))); ++ ++ return i2c_smbus_write_byte_data(client, PMBUS_PAGE, 0); ++} ++ ++static int mp29502_read_byte_data(struct i2c_client *client, int page, int reg) ++{ ++ int ret; ++ ++ ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, 0); ++ if (ret < 0) ++ return ret; ++ ++ switch (reg) { ++ case PMBUS_VOUT_MODE: ++ ret = PB_VOUT_MODE_DIRECT; ++ break; ++ default: ++ ret = -ENODATA; ++ break; ++ } ++ ++ return ret; ++} ++ ++static int mp29502_read_word_data(struct i2c_client *client, int page, ++ int phase, int reg) ++{ ++ const struct pmbus_driver_info *info = pmbus_get_driver_info(client); ++ struct mp29502_data *data = to_mp29502_data(info); ++ int ret; ++ ++ switch (reg) { ++ case PMBUS_STATUS_WORD: ++ ret = -ENODATA; ++ break; ++ case PMBUS_READ_VIN: ++ /* ++ * The MP29502 PMBUS_READ_VIN[10:0] is the vin value, the vin scale is ++ * 125mV/LSB. And the vin scale is set to 125mV/Lsb(using r/m/b scale) ++ * in MP29502 pmbus_driver_info struct, so the word data bit0-bit10 can ++ * be returned to pmbus core directly. ++ */ ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = FIELD_GET(GENMASK(10, 0), ret); ++ break; ++ case PMBUS_READ_VOUT: ++ /* ++ * The MP29502 PMBUS_READ_VOUT[11:0] is the vout value, and vout ++ * value is calculated based on vout scale and vout divider. ++ */ ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = DIV_ROUND_CLOSEST((ret & GENMASK(11, 0)) * ++ data->vout_scale * ++ (data->vout_bottom_div + ++ 4 * data->vout_top_div), ++ MP29502_READ_VOUT_DIV * ++ data->vout_bottom_div); ++ break; ++ case PMBUS_READ_IIN: ++ /* ++ * The MP29502 MFR_READ_IIN_EST register is linear11 format, and the ++ * exponent is not a constant value. But the iin scale is set to ++ * 1A/Lsb(using r/m/b scale). As a result, the iin read from MP29502 ++ * should be calculated to A, then return the result to pmbus core. ++ */ ++ ret = pmbus_read_word_data(client, page, phase, MFR_READ_IIN_EST); ++ if (ret < 0) ++ return ret; ++ ++ ret = DIV_ROUND_CLOSEST(mp29502_reg2data_linear11(ret), ++ MP29502_IIN_DIV); ++ break; ++ case PMBUS_READ_PIN: ++ /* ++ * The MP29502 MFR_READ_PIN_EST register is linear11 format, and the ++ * exponent is not a constant value. But the pin scale is set to ++ * 1W/Lsb(using r/m/b scale). As a result, the pout read from MP29502 ++ * should be calculated to W, then return the result to pmbus core. ++ */ ++ ret = pmbus_read_word_data(client, page, phase, MFR_READ_PIN_EST); ++ if (ret < 0) ++ return ret; ++ ++ ret = mp29502_reg2data_linear11(ret) * MP29502_PIN_GAIN; ++ break; ++ case PMBUS_READ_POUT: ++ /* ++ * The MP29502 PMBUS_READ_POUT register is linear11 format, and the ++ * exponent is not a constant value. But the pout scale is set to ++ * 1W/Lsb(using r/m/b scale). As a result, the pout read from MP29502 ++ * should be calculated to W, then return the result to pmbus core. ++ * And the pout is calculated based on vout divider. ++ */ ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = DIV_ROUND_CLOSEST(mp29502_reg2data_linear11(ret) * ++ (data->vout_bottom_div + ++ 4 * data->vout_top_div), ++ data->vout_bottom_div); ++ break; ++ case PMBUS_READ_IOUT: ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = DIV_ROUND_CLOSEST((ret & GENMASK(10, 0)) * data->iout_scale, ++ MP29502_READ_IOUT_DIV); ++ break; ++ case PMBUS_READ_TEMPERATURE_1: ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = FIELD_GET(GENMASK(10, 0), ret); ++ break; ++ case PMBUS_VIN_OV_FAULT_LIMIT: ++ /* ++ * The MP29502 PMBUS_VIN_OV_FAULT_LIMIT is 500mV/Lsb, but ++ * the vin scale is set to 125mV/Lsb(using r/m/b scale), ++ * so the word data should multiply by 4. ++ */ ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = FIELD_GET(GENMASK(7, 0), ret) * MP29502_VIN_OV_GAIN; ++ break; ++ case PMBUS_VIN_UV_WARN_LIMIT: ++ case PMBUS_VIN_UV_FAULT_LIMIT: ++ /* ++ * The MP29502 PMBUS_VIN_UV_WARN_LIMIT and PMBUS_VIN_UV_FAULT_LIMIT ++ * scale is 125mV/Lsb, but the vin scale is set to 125mV/Lsb(using ++ * r/m/b scale), so the word data bit0-bit9 can be returned to pmbus ++ * core directly. ++ */ ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = FIELD_GET(GENMASK(9, 0), ret); ++ break; ++ case PMBUS_VOUT_OV_FAULT_LIMIT: ++ /* ++ * The MP29502 vout ov fault limit value comes from ++ * page1 MFR_TSNS_FLT_SET[12:7]. ++ */ ++ ret = mp29502_read_vout_ov_limit(client, data); ++ if (ret < 0) ++ return ret; ++ ++ break; ++ case PMBUS_VOUT_UV_FAULT_LIMIT: ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = DIV_ROUND_CLOSEST((FIELD_GET(GENMASK(8, 0), ret) * ++ MP29502_OVUV_LIMIT_SCALE - ++ MP29502_VOUT_UV_OFFSET) * ++ (data->vout_bottom_div + ++ 4 * data->vout_top_div), ++ data->vout_bottom_div); ++ break; ++ case PMBUS_IOUT_OC_FAULT_LIMIT: ++ case PMBUS_IOUT_OC_WARN_LIMIT: ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = DIV_ROUND_CLOSEST((ret & GENMASK(7, 0)) * ++ data->iout_scale * ++ MP29502_IOUT_LIMIT_UINT, ++ MP29502_READ_IOUT_DIV); ++ break; ++ case PMBUS_OT_FAULT_LIMIT: ++ case PMBUS_OT_WARN_LIMIT: ++ /* ++ * The scale of MP29502 PMBUS_OT_FAULT_LIMIT and PMBUS_OT_WARN_LIMIT ++ * is 1°C/LSB and they have 40°C offset. ++ */ ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = (ret & GENMASK(7, 0)) - MP29502_TEMP_LIMIT_OFFSET; ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ return ret; ++} ++ ++static int mp29502_write_word_data(struct i2c_client *client, int page, int reg, ++ u16 word) ++{ ++ const struct pmbus_driver_info *info = pmbus_get_driver_info(client); ++ struct mp29502_data *data = to_mp29502_data(info); ++ int ret; ++ ++ ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, 0); ++ if (ret < 0) ++ return ret; ++ ++ switch (reg) { ++ case PMBUS_VIN_OV_FAULT_LIMIT: ++ /* ++ * The PMBUS_VIN_OV_FAULT_LIMIT[7:0] is the limit value, ++ * and bit8-bit15 should not be changed. The scale of ++ * PMBUS_VIN_OV_FAULT_LIMIT is 500mV/Lsb, but the vin ++ * scale is set to 125mV/Lsb(using r/m/b scale), so ++ * the word data should divide by 4. ++ */ ++ ret = pmbus_read_word_data(client, page, 0xff, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = pmbus_write_word_data(client, page, reg, ++ (ret & ~GENMASK(7, 0)) | ++ FIELD_PREP(GENMASK(7, 0), ++ DIV_ROUND_CLOSEST(word, ++ MP29502_VIN_OV_GAIN))); ++ break; ++ case PMBUS_VIN_UV_WARN_LIMIT: ++ case PMBUS_VIN_UV_FAULT_LIMIT: ++ /* ++ * The PMBUS_VIN_UV_WARN_LIMIT[9:0] and PMBUS_VIN_UV_FAULT_LIMIT[9:0] ++ * are the limit value, and bit10-bit15 should not be changed. ++ */ ++ ret = pmbus_read_word_data(client, page, 0xff, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = pmbus_write_word_data(client, page, reg, ++ (ret & ~GENMASK(9, 0)) | ++ FIELD_PREP(GENMASK(9, 0), ++ word)); ++ break; ++ case PMBUS_VOUT_OV_FAULT_LIMIT: ++ ret = mp29502_write_vout_ov_limit(client, word, data); ++ if (ret < 0) ++ return ret; ++ ++ break; ++ case PMBUS_VOUT_UV_FAULT_LIMIT: ++ ret = pmbus_read_word_data(client, page, 0xff, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = pmbus_write_word_data(client, page, reg, ++ (ret & ~GENMASK(8, 0)) | ++ FIELD_PREP(GENMASK(8, 0), ++ DIV_ROUND_CLOSEST(word * ++ data->vout_bottom_div + ++ MP29502_VOUT_UV_OFFSET * ++ (data->vout_bottom_div + ++ 4 * data->vout_top_div), ++ MP29502_OVUV_LIMIT_SCALE * ++ (data->vout_bottom_div + ++ 4 * data->vout_top_div)))); ++ break; ++ case PMBUS_IOUT_OC_FAULT_LIMIT: ++ case PMBUS_IOUT_OC_WARN_LIMIT: ++ ret = pmbus_write_word_data(client, page, reg, ++ DIV_ROUND_CLOSEST(word * ++ MP29502_READ_IOUT_DIV, ++ MP29502_IOUT_LIMIT_UINT * ++ data->iout_scale)); ++ break; ++ case PMBUS_OT_FAULT_LIMIT: ++ case PMBUS_OT_WARN_LIMIT: ++ /* ++ * The PMBUS_OT_FAULT_LIMIT[7:0] and PMBUS_OT_WARN_LIMIT[7:0] ++ * are the limit value, and bit8-bit15 should not be changed. ++ */ ++ ret = pmbus_read_word_data(client, page, 0xff, reg); ++ if (ret < 0) ++ return ret; ++ ++ ret = pmbus_write_word_data(client, page, reg, ++ (ret & ~GENMASK(7, 0)) | ++ FIELD_PREP(GENMASK(7, 0), ++ word + MP29502_TEMP_LIMIT_OFFSET)); ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ return ret; ++} ++ ++static int mp29502_identify(struct i2c_client *client, struct pmbus_driver_info *info) ++{ ++ int ret; ++ ++ /* Identify vout scale */ ++ ret = mp29502_identify_vout_scale(client, info, 0); ++ if (ret < 0) ++ return ret; ++ ++ /* Identify vout divider. */ ++ ret = mp29502_identify_vout_divider(client, info, 1); ++ if (ret < 0) ++ return ret; ++ ++ /* Identify ovp divider. */ ++ ret = mp29502_identify_ovp_divider(client, info, 1); ++ if (ret < 0) ++ return ret; ++ ++ /* Identify iout scale */ ++ return mp29502_identify_iout_scale(client, info, 0); ++} ++ ++static const struct pmbus_driver_info mp29502_info = { ++ .pages = MP29502_PAGE_NUM, ++ .format[PSC_VOLTAGE_IN] = direct, ++ .format[PSC_TEMPERATURE] = direct, ++ .format[PSC_CURRENT_IN] = direct, ++ .format[PSC_CURRENT_OUT] = direct, ++ .format[PSC_VOLTAGE_OUT] = direct, ++ .format[PSC_POWER] = direct, ++ ++ .m[PSC_VOLTAGE_IN] = 8, ++ .R[PSC_VOLTAGE_IN] = 0, ++ .b[PSC_VOLTAGE_IN] = 0, ++ ++ .m[PSC_VOLTAGE_OUT] = 1, ++ .R[PSC_VOLTAGE_OUT] = 3, ++ .b[PSC_VOLTAGE_OUT] = 0, ++ ++ .m[PSC_TEMPERATURE] = 1, ++ .R[PSC_TEMPERATURE] = 0, ++ .b[PSC_TEMPERATURE] = 0, ++ ++ .m[PSC_CURRENT_IN] = 1, ++ .R[PSC_CURRENT_IN] = 0, ++ .b[PSC_CURRENT_IN] = 0, ++ ++ .m[PSC_CURRENT_OUT] = 1, ++ .R[PSC_CURRENT_OUT] = 0, ++ .b[PSC_CURRENT_OUT] = 0, ++ ++ .m[PSC_POWER] = 1, ++ .R[PSC_POWER] = 0, ++ .b[PSC_POWER] = 0, ++ ++ .func[0] = MP29502_RAIL_FUNC, ++ .read_word_data = mp29502_read_word_data, ++ .read_byte_data = mp29502_read_byte_data, ++ .write_word_data = mp29502_write_word_data, ++ .identify = mp29502_identify, ++}; ++ ++static int mp29502_probe(struct i2c_client *client) ++{ ++ struct pmbus_driver_info *info; ++ struct mp29502_data *data; ++ ++ data = devm_kzalloc(&client->dev, sizeof(struct mp29502_data), ++ GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ memcpy(&data->info, &mp29502_info, sizeof(*info)); ++ info = &data->info; ++ ++ return pmbus_do_probe(client, info); ++} ++ ++static const struct i2c_device_id mp29502_id[] = { ++ {"mp29502", 0}, ++ {} ++}; ++MODULE_DEVICE_TABLE(i2c, mp29502_id); ++ ++static const struct of_device_id __maybe_unused mp29502_of_match[] = { ++ {.compatible = "mps,mp29502"}, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, mp29502_of_match); ++ ++static struct i2c_driver mp29502_driver = { ++ .driver = { ++ .name = "mp29502", ++ .of_match_table = mp29502_of_match, ++ }, ++ .probe = mp29502_probe, ++ .id_table = mp29502_id, ++}; ++ ++module_i2c_driver(mp29502_driver); ++ ++MODULE_AUTHOR("Wensheng Wang Date: Thu, 4 Jan 2024 09:12:29 +0000 -Subject: [PATCH v6.1 9/9] hwmon: (pmbus) Add support for MPS Multi-phase - mp2855 controller +Subject: [PATCH 43/78] hwmon: (pmbus) Add support for MPS Multi-phase mp2855 + controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -27,17 +27,17 @@ The device is available in a TQFN-40 (5mmx5mm) package. Signed-off-by: Vadim Pasternak --- - drivers/hwmon/pmbus/Kconfig | 10 + + drivers/hwmon/pmbus/Kconfig | 10 ++ drivers/hwmon/pmbus/Makefile | 1 + - drivers/hwmon/pmbus/mp2855.c | 380 +++++++++++++++++++++++++++++++++++ + drivers/hwmon/pmbus/mp2855.c | 380 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 391 insertions(+) create mode 100644 drivers/hwmon/pmbus/mp2855.c diff --git a/drivers/hwmon/pmbus/Kconfig b/drivers/hwmon/pmbus/Kconfig -index 77d67344cee4..f173c4195d86 100644 +index 60eabf9..369e409 100644 --- a/drivers/hwmon/pmbus/Kconfig +++ b/drivers/hwmon/pmbus/Kconfig -@@ -290,6 +290,16 @@ config SENSORS_MAX8688 +@@ -319,6 +319,16 @@ config SENSORS_MAX8688 This driver can also be built as a module. If so, the module will be called max8688. @@ -51,24 +51,24 @@ index 77d67344cee4..f173c4195d86 100644 + This driver can also be built as a module. If so, the module will + be called mp2855. + - config SENSORS_MP2888 - tristate "MPS MP2888" + config SENSORS_MP2856 + tristate "MPS MP2856" help diff --git a/drivers/hwmon/pmbus/Makefile b/drivers/hwmon/pmbus/Makefile -index 8e767d7b8c5b..24b38e451bc7 100644 +index 55b0784..a95fc50 100644 --- a/drivers/hwmon/pmbus/Makefile +++ b/drivers/hwmon/pmbus/Makefile -@@ -31,6 +31,7 @@ obj-$(CONFIG_SENSORS_MAX20751) += max20751.o +@@ -34,6 +34,7 @@ obj-$(CONFIG_SENSORS_MAX20751) += max20751.o obj-$(CONFIG_SENSORS_MAX31785) += max31785.o obj-$(CONFIG_SENSORS_MAX34440) += max34440.o obj-$(CONFIG_SENSORS_MAX8688) += max8688.o +obj-$(CONFIG_SENSORS_MP2855) += mp2855.o + obj-$(CONFIG_SENSORS_MP2856) += mp2856.o + obj-$(CONFIG_SENSORS_MP2869) += mp2869.o obj-$(CONFIG_SENSORS_MP2888) += mp2888.o - obj-$(CONFIG_SENSORS_MP2891) += mp2891.o - obj-$(CONFIG_SENSORS_MP2975) += mp2975.o diff --git a/drivers/hwmon/pmbus/mp2855.c b/drivers/hwmon/pmbus/mp2855.c new file mode 100644 -index 000000000000..3cffd0973706 +index 00000000..3cffd09 --- /dev/null +++ b/drivers/hwmon/pmbus/mp2855.c @@ -0,0 +1,380 @@ @@ -211,7 +211,7 @@ index 000000000000..3cffd0973706 + default: + return -ENODATA; + } -+ ++ + return ret; +} + @@ -443,7 +443,7 @@ index 000000000000..3cffd0973706 + .name = "mp2855", + .of_match_table = mp2855_of_match, + }, -+ .probe_new = mp2855_probe, ++ .probe = mp2855_probe, + .id_table = mp2855_id, +}; + @@ -453,5 +453,5 @@ index 000000000000..3cffd0973706 +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(PMBUS); -- -2.20.1 +2.8.4 diff --git a/patches-sonic/0044-platform_data-mlxreg-Add-non-sticky-bit-indication-f.patch b/patches-sonic/0044-platform_data-mlxreg-Add-non-sticky-bit-indication-f.patch new file mode 100644 index 000000000..8d1bd86df --- /dev/null +++ b/patches-sonic/0044-platform_data-mlxreg-Add-non-sticky-bit-indication-f.patch @@ -0,0 +1,42 @@ +From da53757b0d6a86d772fd6fe6768c9213d0bb2aa4 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Fri, 6 Sep 2024 13:59:03 +0300 +Subject: [PATCH 44/78] platform_data/mlxreg: Add non-sticky bit indication + field + +Add non-sticky filed indicating that signal bit is changed to its +previous value after acknowledging. + +Detection of non-sticky signals is to be performed through the reading +event register, while sticky signals are detected through the reading +status register. + +Signed-off-by: Vadim Pasternak +Reviewed-by: Felix Radensky +--- + include/linux/platform_data/mlxreg.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_data/mlxreg.h +index 84c94b3..fca2d7e43 100644 +--- a/include/linux/platform_data/mlxreg.h ++++ b/include/linux/platform_data/mlxreg.h +@@ -184,6 +184,7 @@ struct mlxreg_core_data { + * @inversed: if 0: 0 for signal status is OK, if 1 - 1 is OK; + * @health: true if device has health indication, false in other case; + * @storming_bits: interrupt storming bits mask; ++ * @non_sticky: 1 - indicates that signal bit is changed to the previous value after acknowledging; + */ + struct mlxreg_core_item { + struct mlxreg_core_data *data; +@@ -200,6 +201,7 @@ struct mlxreg_core_item { + u8 inversed; + u8 health; + u32 storming_bits; ++ u8 non_sticky; + }; + + /** +-- +2.8.4 + diff --git a/patches-sonic/0045-platform-mellanox-mlxreg-hotplug-Add-handling-of-non.patch b/patches-sonic/0045-platform-mellanox-mlxreg-hotplug-Add-handling-of-non.patch new file mode 100644 index 000000000..8f997db8e --- /dev/null +++ b/patches-sonic/0045-platform-mellanox-mlxreg-hotplug-Add-handling-of-non.patch @@ -0,0 +1,63 @@ +From b33a8c29d95f0b998f326de0c651e0262cd603cd Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Fri, 6 Sep 2024 14:10:30 +0300 +Subject: [PATCH 45/78] platform/mellanox: mlxreg-hotplug: Add handling of + non-sticky signals + +Add support for non-sticky signals. For such signal status bit is +non-sticky and changes to the previous value after acknowledging. + +Detection of non-sticky signals is to be performed through the reading +event register, while sticky signals are detected through the reading +status register. + +Signed-off-by: Vadim Pasternak +Reviewed-by: Felix Radensky +--- + drivers/platform/mellanox/mlxreg-hotplug.c | 29 +++++++++++++++++++++-------- + 1 file changed, 21 insertions(+), 8 deletions(-) + +diff --git a/drivers/platform/mellanox/mlxreg-hotplug.c b/drivers/platform/mellanox/mlxreg-hotplug.c +index 2b52610..a395969e 100644 +--- a/drivers/platform/mellanox/mlxreg-hotplug.c ++++ b/drivers/platform/mellanox/mlxreg-hotplug.c +@@ -379,15 +379,28 @@ mlxreg_hotplug_work_helper(struct mlxreg_hotplug_priv_data *priv, + if (ret) + goto out; + +- /* Read status. */ +- ret = regmap_read(priv->regmap, item->reg, ®val); +- if (ret) +- goto out; ++ if (item->non_sticky) { ++ /* Read event. */ ++ ret = regmap_read(priv->regmap, item->reg + ++ MLXREG_HOTPLUG_EVENT_OFF, ®val); ++ if (ret) ++ goto out; ++ ++ /* Set asserted bits. */ ++ regval &= item->mask; ++ asserted = regval; ++ } else { ++ /* Read status. */ ++ ret = regmap_read(priv->regmap, item->reg, ®val); ++ if (ret) ++ goto out; ++ ++ /* Set asserted bits and save last status. */ ++ regval &= item->mask; ++ asserted = item->cache ^ regval; ++ item->cache = regval; ++ } + +- /* Set asserted bits and save last status. */ +- regval &= item->mask; +- asserted = item->cache ^ regval; +- item->cache = regval; + for_each_set_bit(bit, &asserted, 8) { + int pos; + +-- +2.8.4 + diff --git a/patches-sonic/0046-platform-mellanox-nvsw-bmc-Add-system-control-and-mo.patch b/patches-sonic/0046-platform-mellanox-nvsw-bmc-Add-system-control-and-mo.patch new file mode 100644 index 000000000..ef97c02fc --- /dev/null +++ b/patches-sonic/0046-platform-mellanox-nvsw-bmc-Add-system-control-and-mo.patch @@ -0,0 +1,4519 @@ +From 9b36f571a51a32214316a7a4afc3c902b9059f48 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Thu, 4 Jul 2024 23:50:27 +0300 +Subject: [PATCH 46/78] platform/mellanox: nvsw-bmc: Add system control and + monitoring driver for Nvidia BMC + +The driver allows system control and monitoring of Nvidia switches +through CPLD/FPGA devices from Based Management Controller SoC. + +This control includes: +- Handling of hotplug events. +- Various resets handling through sysfs attributes. +- Reset cause reports through sysfs attributes. +- Mux attributes for hw components selection. +- General purpose registers attributes. +- LED control. +- FAN control. + +Signed-off-by: Vadim Pasternak +--- + .../devicetree/bindings/trivial-devices.yaml | 5 + + drivers/platform/mellanox/Kconfig | 18 + + drivers/platform/mellanox/Makefile | 2 + + drivers/platform/mellanox/nvsw-bmc-hid162.c | 2773 ++++++++++++++++++++ + drivers/platform/mellanox/nvsw-core.c | 625 +++++ + drivers/platform/mellanox/nvsw-host-l1.c | 745 ++++++ + drivers/platform/mellanox/nvsw.h | 260 ++ + 7 files changed, 4428 insertions(+) + create mode 100644 drivers/platform/mellanox/nvsw-bmc-hid162.c + create mode 100644 drivers/platform/mellanox/nvsw-core.c + create mode 100644 drivers/platform/mellanox/nvsw-host-l1.c + create mode 100644 drivers/platform/mellanox/nvsw.h + +diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml +index a190c56..14568bd 100644 +--- a/Documentation/devicetree/bindings/trivial-devices.yaml ++++ b/Documentation/devicetree/bindings/trivial-devices.yaml +@@ -307,6 +307,11 @@ properties: + - national,lm85 + # I2C ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator + - national,lm92 ++ # Nvidia BMC platform CPLD control ++ - nvidia,hid162 ++ - nvidia,hid176 ++ - nvidia,hid177 ++ - nvidia,hid180 + # Nuvoton Temperature Sensor + - nuvoton,w83773g + # OKI ML86V7667 video decoder +diff --git a/drivers/platform/mellanox/Kconfig b/drivers/platform/mellanox/Kconfig +index e3afbe6..dd6b576 100644 +--- a/drivers/platform/mellanox/Kconfig ++++ b/drivers/platform/mellanox/Kconfig +@@ -105,6 +105,24 @@ config MLXBF_PMC + to performance monitoring counters within various blocks in the + Mellanox BlueField SoC via a sysfs interface. + ++config NVSW_BMC_HID162 ++ tristate "Nvidia BMC CPLD/FPGA Hardware Control and Monitoring" ++ depends on REGMAP_I2C && OF && REGMAP && HWMON ++ help ++ Say Y here to include support for the FPGA/CPLD logic by Baseboard ++ Management Controller equipped on Nvidia switches. ++ This driver can also be built as a module. If so the module ++ will be called nvsw-bmc-hid162. ++ ++config NVSW_HOST_L1 ++ tristate "Nvidia host CPLD/FPGA Hardware Control and Monitoring" ++ depends on REGMAP_I2C && OF && REGMAP && HWMON ++ help ++ Say Y here to include support for the FPGA/CPLD logic by host CPU ++ equipped on Nvidia switches. ++ This driver can also be built as a module. If so the module ++ will be called nvsw-host-l1. ++ + config NVSW_SN2201 + tristate "Nvidia SN2201 platform driver support" + depends on HWMON && I2C +diff --git a/drivers/platform/mellanox/Makefile b/drivers/platform/mellanox/Makefile +index e86723b..4c1aec1 100644 +--- a/drivers/platform/mellanox/Makefile ++++ b/drivers/platform/mellanox/Makefile +@@ -11,4 +11,6 @@ obj-$(CONFIG_MLXREG_DPU) += mlxreg-dpu.o + obj-$(CONFIG_MLXREG_HOTPLUG) += mlxreg-hotplug.o + obj-$(CONFIG_MLXREG_IO) += mlxreg-io.o + obj-$(CONFIG_MLXREG_LC) += mlxreg-lc.o ++obj-$(CONFIG_NVSW_BMC_HID162) += nvsw-bmc-hid162.o nvsw-core.o ++obj-$(CONFIG_NVSW_HOST_L1) += nvsw-host-l1.o nvsw-core.o + obj-$(CONFIG_NVSW_SN2201) += nvsw-sn2201.o +diff --git a/drivers/platform/mellanox/nvsw-bmc-hid162.c b/drivers/platform/mellanox/nvsw-bmc-hid162.c +new file mode 100644 +index 00000000..fbc7382 +--- /dev/null ++++ b/drivers/platform/mellanox/nvsw-bmc-hid162.c +@@ -0,0 +1,2773 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Nvidia BMC platform driver ++ * ++ * Copyright (C) 2025 Nvidia Technologies Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "nvsw.h" ++ ++#define NVSW_HID162_TACHO_SAMPLES 20 ++#define NVSW_HID162_TACHO_DIV 1981 ++ ++/* Configuration for the register map of a device with 2 bytes address space. */ ++static const struct reg_default nvsw_bmc_hid162_reg_def[] = { ++ { NVSW_REG_PWM_CONTROL_OFFSET, 0x00 }, ++}; ++ ++/* Channels vectors. ++ * They contain only the channels, which physically connected to the devices, ++ * empty channels are skipped. ++ */ ++static int nvsw_bmc_hid162_chan1[] = { ++ 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x08, 0x09, 0x11, 0x14, 0x18, 0x20, 0x21, 0x30, 0x31, ++ 0x32, 0x33, 0x34, 0x35, 0x24, 0x0a, ++}; ++ ++static int nvsw_bmc_hid176_chan1[] = { ++ 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x08, 0x09, 0x11, 0x14, 0x18, 0x20, 0x21, 0x30, 0x31, ++ 0x32, 0x33, 0x34, 0x35, 0x24, 0x0a, 0x22, ++}; ++ ++static int nvsw_bmc_hid180_chan1[] = { ++ 0x01, 0x11, 0x21, 0x31, 0x09, 0x02, 0x03, 0x04, 0x14, 0x24, 0x34, 0x05, 0x06, 0x40, 0x41, ++ 0x42, 0x43, 0x0a, 0x0b, 0x1b, ++}; ++ ++static int nvsw_bmc_hid180_chan2[] = { ++ 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, ++}; ++ ++/* Mux configuration. */ ++static struct i2c_mux_regmap_platform_data nvsw_bmc_hid162_mux_data[] = { ++ { ++ .parent = 14, ++ .chan_ids = nvsw_bmc_hid162_chan1, ++ .num_adaps = ARRAY_SIZE(nvsw_bmc_hid162_chan1), ++ .sel_reg_addr = NVSW_REG_MUX1_OFFSET, ++ .reg_size = 1, ++ }, ++}; ++ ++static struct i2c_mux_regmap_platform_data nvsw_bmc_hid176_mux_data[] = { ++ { ++ .parent = 14, ++ .chan_ids = nvsw_bmc_hid176_chan1, ++ .num_adaps = ARRAY_SIZE(nvsw_bmc_hid176_chan1), ++ .sel_reg_addr = NVSW_REG_MUX1_OFFSET, ++ .reg_size = 1, ++ }, ++}; ++ ++static struct i2c_mux_regmap_platform_data nvsw_bmc_hid180_mux_data[] = { ++ { ++ .parent = 14, ++ .chan_ids = nvsw_bmc_hid180_chan1, ++ .num_adaps = ARRAY_SIZE(nvsw_bmc_hid180_chan1), ++ .sel_reg_addr = NVSW_REG_MUX1_OFFSET, ++ .reg_size = 1, ++ }, ++ { ++ .parent = 14, ++ .chan_ids = nvsw_bmc_hid180_chan2, ++ .num_adaps = ARRAY_SIZE(nvsw_bmc_hid180_chan2), ++ .sel_reg_addr = NVSW_REG_MUX2_OFFSET, ++ .reg_size = 1, ++ }, ++}; ++ ++static struct i2c_mux_regmap_platform_data *mux_data[NVSW_MUX_MAX]; ++static struct i2c_board_info *mux_brdinfo[NVSW_MUX_MAX]; ++ ++/* Mux board info. */ ++static struct i2c_board_info nvsw_bmc_hid162_mux_brdinfo = { ++ I2C_BOARD_INFO("i2c-mux-mlxcpld", 0x32), ++}; ++ ++/* Platform hotplug data */ ++static struct mlxreg_core_data nvsw_bmc_hid162_events_items_data[] = { ++ { ++ .label = "power_button", ++ .reg = NVSW_REG_PWRB_OFFSET, ++ .mask = NVSW_PWR_BUTTON_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "amb_temp_sense", ++ .reg = NVSW_REG_PWRB_OFFSET, ++ .mask = NVSW_AMB_TEMP_SENSE_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "graceful_power_off_req", ++ .reg = NVSW_REG_PWRB_OFFSET, ++ .mask = NVSW_GRACEFUL_POWER_OFF_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "cpu_power_off_ready", ++ .reg = NVSW_REG_PWRB_OFFSET, ++ .mask = NVSW_CPU_POWER_OFF_READY_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "cpu_reset", ++ .reg = NVSW_REG_PWRB_OFFSET, ++ .mask = NVSW_CPU_RESET_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "apml_smb_alert", ++ .reg = NVSW_REG_PWRB_OFFSET, ++ .mask = NVSW_APML_SMB_ALERT_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "cpu_unexp_power_off", ++ .reg = NVSW_REG_PWRB_OFFSET, ++ .mask = NVSW_CPU_UNEXP_POWER_OFF_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "uid_push_button", ++ .reg = NVSW_REG_PWRB_OFFSET, ++ .mask = NVSW_UID_PUSH_BUTTON_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid162_asic1_items_data[] = { ++ { ++ .label = "asic1_health", ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASIC_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid162_asic2_items_data[] = { ++ { ++ .label = "asic2_health", ++ .reg = NVSW_REG_ASIC2_HEALTH_OFFSET, ++ .mask = NVSW_ASIC_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid177_asic3_items_data[] = { ++ { ++ .label = "asic3_health", ++ .reg = NVSW_REG_ASIC3_HEALTH_OFFSET, ++ .mask = NVSW_ASIC_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid162_cartridge_items_data[] = { ++ { ++ .label = "cartridge1", ++ .reg = NVSW_REG_FRU1_OFFSET, ++ .mask = BIT(0), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "cartridge2", ++ .reg = NVSW_REG_FRU1_OFFSET, ++ .mask = BIT(1), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "cartridge3", ++ .reg = NVSW_REG_FRU1_OFFSET, ++ .mask = BIT(2), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "cartridge4", ++ .reg = NVSW_REG_FRU1_OFFSET, ++ .mask = BIT(3), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid162_leakage_items_data[] = { ++ { ++ .label = "leakage1", ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = BIT(0), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "leakage2", ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = BIT(1), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "leakage3", ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = BIT(2), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "leakage4", ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = BIT(3), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "leakage5", ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = BIT(4), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "leakage6", ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = BIT(5), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid162_pwr_good_items_data[] = { ++ { ++ .label = "rtc", ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = NVSW_RTC_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "hot_swap_alert", ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = NVSW_HOT_SWAP_ALERT_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid162_alarms_items_data[] = { ++ { ++ .label = "ssd_i2c_alert", ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = NVSW_SSD_I2C_ALERT_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "wd_exp", ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = NVSW_WD_EXP_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "51v_usb", ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = NVSW_5V_USB_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "pcb_temp_sense_1", ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = NVSW_PCB_TEMP1_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "pcb_temp_sense_2", ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = NVSW_PCB_TEMP2_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "sgmii_phy", ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = NVSW_SGMII_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "ssd_pw_good", ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = NVSW_SDD_PG_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "leakage_aggr", ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = NVSW_LEAK_AGGR_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid162_erot_ap_items_data[] = { ++ { ++ .label = "erot_asic1_ap", ++ .reg = NVSW_REG_EROT_OFFSET, ++ .mask = BIT(0), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "erot_asic2_ap", ++ .reg = NVSW_REG_EROT_OFFSET, ++ .mask = BIT(1), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "erot_cpu_ap", ++ .reg = NVSW_REG_EROT_OFFSET, ++ .mask = BIT(2), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid162_erot_error_items_data[] = { ++ { ++ .label = "erot_asic1_error", ++ .reg = NVSW_REG_EROT_ERR_OFFSET, ++ .mask = BIT(0), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "erot_asic2_error", ++ .reg = NVSW_REG_EROT_ERR_OFFSET, ++ .mask = BIT(1), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "erot_cpu_error", ++ .reg = NVSW_REG_EROT_ERR_OFFSET, ++ .mask = BIT(2), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid176_erot_error_items_data[] = { ++ { ++ .label = "erot_cpu_error", ++ .reg = NVSW_REG_EROT_ERR_OFFSET, ++ .mask = BIT(0), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "erot_asic1_error", ++ .reg = NVSW_REG_EROT_ERR_OFFSET, ++ .mask = BIT(1), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "erot_asic2_error", ++ .reg = NVSW_REG_EROT_ERR_OFFSET, ++ .mask = BIT(2), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "erot_asic3_error", ++ .reg = NVSW_REG_EROT_ERR_OFFSET, ++ .mask = BIT(3), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_item nvsw_bmc_hid162_hotplug_items_data[] = { ++ { ++ .data = nvsw_bmc_hid162_events_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_PWRB_OFFSET, ++ .mask = NVSW_PWR_BUTTON_MASK | NVSW_AMB_TEMP_SENSE_MASK | ++ NVSW_GRACEFUL_POWER_OFF_MASK | NVSW_CPU_POWER_OFF_READY_MASK | ++ NVSW_CPU_RESET_MASK | NVSW_APML_SMB_ALERT_MASK | ++ NVSW_CPU_UNEXP_POWER_OFF_MASK | NVSW_UID_PUSH_BUTTON_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_events_items_data), ++ .inversed = 1, ++ .health = false, ++ .non_sticky = true, ++ }, ++ { ++ .data = nvsw_bmc_hid162_asic1_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASIC_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_asic1_items_data), ++ .inversed = 0, ++ .health = true, ++ }, ++ { ++ .data = nvsw_bmc_hid162_asic2_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_ASIC2_HEALTH_OFFSET, ++ .mask = NVSW_ASIC_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_asic2_items_data), ++ .inversed = 0, ++ .health = true, ++ }, ++ { ++ .data = nvsw_bmc_hid162_cartridge_items_data, ++ .aggr_mask = GENMASK(3, 0), ++ .reg = NVSW_REG_FRU1_OFFSET, ++ .mask = NVSW_REG_FRU1_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_cartridge_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++ { ++ .data = nvsw_bmc_hid162_leakage_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = NVSW_LEAK_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_leakage_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++ { ++ .data = nvsw_bmc_hid162_pwr_good_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = NVSW_RTC_MASK | NVSW_HOT_SWAP_ALERT_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_pwr_good_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++ { ++ .data = nvsw_bmc_hid162_alarms_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = NVSW_SSD_I2C_ALERT_MASK | NVSW_WD_EXP_MASK | ++ NVSW_5V_USB_MASK | NVSW_PCB_TEMP1_MASK | ++ NVSW_PCB_TEMP2_MASK | NVSW_SGMII_MASK | ++ NVSW_SDD_PG_MASK | NVSW_LEAK_AGGR_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_alarms_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++ { ++ .data = nvsw_bmc_hid162_erot_ap_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_EROT_OFFSET, ++ .mask = NVSW_EROT_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_erot_ap_items_data), ++ .inversed = 1, ++ .health = false, ++ }, ++ { ++ .data = nvsw_bmc_hid162_erot_error_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_EROT_ERR_OFFSET, ++ .mask = NVSW_EROT_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_erot_error_items_data), ++ .inversed = 1, ++ .health = false, ++ }, ++}; ++ ++static ++struct mlxreg_core_hotplug_platform_data nvsw_bmc_hid162_hotplug = { ++ .items = nvsw_bmc_hid162_hotplug_items_data, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_hotplug_items_data), ++ .cell = NVSW_REG_AGGR_OFFSET, ++ .mask = NVSW_AGGR_MASK | NVSW_AGGR_MASK_COMEX, ++ .cell_low = NVSW_REG_AGGRLO_OFFSET, ++ .mask_low = NVSW_LOW_AGGR_MASK_LOW | NVSW_LOW_AGGR_MASK_ASIC2 | ++ NVSW_LOW_AGGR_MASK_ASIC1, ++}; ++ ++static struct mlxreg_core_item nvsw_bmc_hid176_hotplug_items_data[] = { ++ { ++ .data = nvsw_bmc_hid162_events_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_PWRB_OFFSET, ++ .mask = NVSW_PWR_BUTTON_MASK | NVSW_AMB_TEMP_SENSE_MASK | ++ NVSW_GRACEFUL_POWER_OFF_MASK | NVSW_CPU_POWER_OFF_READY_MASK | ++ NVSW_CPU_RESET_MASK | NVSW_APML_SMB_ALERT_MASK | ++ NVSW_CPU_UNEXP_POWER_OFF_MASK | NVSW_UID_PUSH_BUTTON_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_events_items_data), ++ .inversed = 1, ++ .health = false, ++ .non_sticky = true, ++ }, ++ { ++ .data = nvsw_bmc_hid162_asic1_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASIC_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_asic1_items_data), ++ .inversed = 0, ++ .health = true, ++ }, ++ { ++ .data = nvsw_bmc_hid162_asic2_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_ASIC2_HEALTH_OFFSET, ++ .mask = NVSW_ASIC_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_asic2_items_data), ++ .inversed = 0, ++ .health = true, ++ }, ++ { ++ .data = nvsw_bmc_hid162_leakage_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = NVSW_LEAK_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_leakage_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++ { ++ .data = nvsw_bmc_hid162_pwr_good_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = NVSW_RTC_MASK | NVSW_HOT_SWAP_ALERT_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_pwr_good_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++ { ++ .data = nvsw_bmc_hid162_alarms_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = NVSW_SSD_I2C_ALERT_MASK | NVSW_WD_EXP_MASK | ++ NVSW_5V_USB_MASK | NVSW_PCB_TEMP1_MASK | ++ NVSW_PCB_TEMP2_MASK | NVSW_SGMII_MASK | ++ NVSW_SDD_PG_MASK | NVSW_LEAK_AGGR_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_alarms_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++ { ++ .data = nvsw_bmc_hid176_erot_error_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_EROT_ERR_OFFSET, ++ .mask = NVSW_EROT_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid176_erot_error_items_data), ++ .inversed = 1, ++ .health = false, ++ }, ++}; ++ ++static ++struct mlxreg_core_hotplug_platform_data nvsw_bmc_hid176_hotplug = { ++ .items = nvsw_bmc_hid176_hotplug_items_data, ++ .count = ARRAY_SIZE(nvsw_bmc_hid176_hotplug_items_data), ++ .cell = NVSW_REG_AGGR_OFFSET, ++ .mask = NVSW_AGGR_MASK | NVSW_AGGR_MASK_COMEX, ++ .cell_low = NVSW_REG_AGGRLO_OFFSET, ++ .mask_low = NVSW_LOW_AGGR_MASK_LOW | NVSW_LOW_AGGR_MASK_ASIC2 | ++ NVSW_LOW_AGGR_MASK_ASIC1, ++}; ++ ++static struct mlxreg_core_item nvsw_bmc_hid177_hotplug_items_data[] = { ++ { ++ .data = nvsw_bmc_hid162_events_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_PWRB_OFFSET, ++ .mask = NVSW_PWR_BUTTON_MASK | NVSW_AMB_TEMP_SENSE_MASK | ++ NVSW_GRACEFUL_POWER_OFF_MASK | NVSW_CPU_POWER_OFF_READY_MASK | ++ NVSW_CPU_RESET_MASK | NVSW_APML_SMB_ALERT_MASK | ++ NVSW_CPU_UNEXP_POWER_OFF_MASK | NVSW_UID_PUSH_BUTTON_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_events_items_data), ++ .inversed = 1, ++ .health = false, ++ .non_sticky = true, ++ }, ++ { ++ .data = nvsw_bmc_hid162_asic1_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASIC_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_asic1_items_data), ++ .inversed = 0, ++ .health = true, ++ }, ++ { ++ .data = nvsw_bmc_hid162_asic2_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_ASIC2_HEALTH_OFFSET, ++ .mask = NVSW_ASIC_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_asic2_items_data), ++ .inversed = 0, ++ .health = true, ++ }, ++ { ++ .data = nvsw_bmc_hid177_asic3_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_ASIC3_HEALTH_OFFSET, ++ .mask = NVSW_ASIC_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid177_asic3_items_data), ++ .inversed = 0, ++ .health = true, ++ }, ++ { ++ .data = nvsw_bmc_hid162_leakage_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = NVSW_LEAK_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_leakage_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++ { ++ .data = nvsw_bmc_hid162_pwr_good_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = NVSW_RTC_MASK | NVSW_HOT_SWAP_ALERT_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_pwr_good_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++ { ++ .data = nvsw_bmc_hid162_alarms_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = NVSW_SSD_I2C_ALERT_MASK | NVSW_WD_EXP_MASK | ++ NVSW_5V_USB_MASK | NVSW_PCB_TEMP1_MASK | ++ NVSW_PCB_TEMP2_MASK | NVSW_SGMII_MASK | ++ NVSW_SDD_PG_MASK | NVSW_LEAK_AGGR_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_alarms_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++ { ++ .data = nvsw_bmc_hid176_erot_error_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_EROT_ERR_OFFSET, ++ .mask = NVSW_EROT_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid176_erot_error_items_data), ++ .inversed = 1, ++ .health = false, ++ }, ++}; ++ ++static ++struct mlxreg_core_hotplug_platform_data nvsw_bmc_hid177_hotplug = { ++ .items = nvsw_bmc_hid177_hotplug_items_data, ++ .count = ARRAY_SIZE(nvsw_bmc_hid177_hotplug_items_data), ++ .cell = NVSW_REG_AGGR_OFFSET, ++ .mask = NVSW_AGGR_MASK | NVSW_AGGR_MASK_COMEX, ++ .cell_low = NVSW_REG_AGGRLO_OFFSET, ++ .mask_low = NVSW_LOW_AGGR_MASK_LOW | NVSW_LOW_AGGR_MASK_ASIC3 | ++ NVSW_LOW_AGGR_MASK_ASIC2 | NVSW_LOW_AGGR_MASK_ASIC1, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid180_pg1_events_items_data[] = { ++ { ++ .label = "smbus_alt_pwrconv_1", ++ .reg = NVSW_REG_PG1_OFFSET, ++ .mask = BIT(0), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "3v3_clk_pg", ++ .reg = NVSW_REG_PG1_OFFSET, ++ .mask = BIT(1), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic1_vdd_pg", ++ .reg = NVSW_REG_PG1_OFFSET, ++ .mask = BIT(2), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic1_dvdd_pl0_pg", ++ .reg = NVSW_REG_PG1_OFFSET, ++ .mask = BIT(3), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic1_dvdd_pl1_pg", ++ .reg = NVSW_REG_PG1_OFFSET, ++ .mask = BIT(4), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic1_hvdd_avcc_pg", ++ .reg = NVSW_REG_PG1_OFFSET, ++ .mask = BIT(5), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "1v8_vddio_pg", ++ .reg = NVSW_REG_PG1_OFFSET, ++ .mask = BIT(6), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "vdrv_asic_1_2_pg", ++ .reg = NVSW_REG_PG1_OFFSET, ++ .mask = BIT(7), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid180_pg2_events_items_data[] = { ++ { ++ .label = "vddcr_soc_s5_pg", ++ .reg = NVSW_REG_PG2_OFFSET, ++ .mask = BIT(0), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "vdd_1v8_s5_pg", ++ .reg = NVSW_REG_PG2_OFFSET, ++ .mask = BIT(1), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "vdd_1v8_pg", ++ .reg = NVSW_REG_PG2_OFFSET, ++ .mask = BIT(2), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "ddr_pg", ++ .reg = NVSW_REG_PG2_OFFSET, ++ .mask = BIT(3), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "12v_pg", ++ .reg = NVSW_REG_PG2_OFFSET, ++ .mask = BIT(4), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "vdd_3v3_pg", ++ .reg = NVSW_REG_PG2_OFFSET, ++ .mask = BIT(5), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "3v3_s5_pg", ++ .reg = NVSW_REG_PG2_OFFSET, ++ .mask = BIT(6), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "vddcr_pg", ++ .reg = NVSW_REG_PG2_OFFSET, ++ .mask = BIT(7), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid180_pg3_events_items_data[] = { ++ { ++ .label = "smbus_alt_hotswap", ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = BIT(0), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "3v3_pb_pg", ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = BIT(1), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic2_vdd_pg", ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = BIT(2), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic2_dvdd_pl0_pg", ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = BIT(3), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic2_dvdd_pl1_pg", ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = BIT(4), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic2_hvdd_pg", ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = BIT(5), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "1v8_cpld_pg", ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = BIT(6), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "holder1_pg", ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = BIT(7), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid180_pg4_events_items_data[] = { ++ { ++ .label = "mbus_alt_pwrconv_2", ++ .reg = NVSW_REG_PG3_OFFSET, ++ .mask = BIT(0), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "holder2_pg", ++ .reg = NVSW_REG_PG3_OFFSET, ++ .mask = BIT(1), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic3_vdd_pg", ++ .reg = NVSW_REG_PG3_OFFSET, ++ .mask = BIT(2), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic3_dvdd_pl0_pg", ++ .reg = NVSW_REG_PG3_OFFSET, ++ .mask = BIT(3), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic3_dvdd_pl1_pg", ++ .reg = NVSW_REG_PG3_OFFSET, ++ .mask = BIT(4), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic3_hvdd_pg", ++ .reg = NVSW_REG_PG3_OFFSET, ++ .mask = BIT(5), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "holder3_pg", ++ .reg = NVSW_REG_PG3_OFFSET, ++ .mask = BIT(6), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "vdrv_asic_3_4_pg", ++ .reg = NVSW_REG_PG3_OFFSET, ++ .mask = BIT(7), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid180_pg5_events_items_data[] = { ++ { ++ .label = "holder4_pg", ++ .reg = NVSW_REG_PG4_OFFSET, ++ .mask = BIT(0), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "holder5_pg", ++ .reg = NVSW_REG_PG4_OFFSET, ++ .mask = BIT(1), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic4_vdd_pg", ++ .reg = NVSW_REG_PG4_OFFSET, ++ .mask = BIT(2), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic4_dvdd_pl0_pg", ++ .reg = NVSW_REG_PG4_OFFSET, ++ .mask = BIT(3), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic4_dvdd_pl1_pg", ++ .reg = NVSW_REG_PG4_OFFSET, ++ .mask = BIT(4), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic4_hvdd_pg", ++ .reg = NVSW_REG_PG4_OFFSET, ++ .mask = BIT(5), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "holder_pg", ++ .reg = NVSW_REG_PG4_OFFSET, ++ .mask = BIT(6), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "vdrv_6_pg", ++ .reg = NVSW_REG_PG4_OFFSET, ++ .mask = BIT(7), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid180_asic_items_data[] = { ++ { ++ .label = "asic1_health", ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASIC_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic2_health", ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASIC2_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic3_health", ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASIC3_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic4_health", ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASIC4_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid180_asic_temp_items_data[] = { ++ { ++ .label = "asic1_temp_warn", ++ .reg = NVSW_REG_ASIC2_HEALTH_OFFSET, ++ .mask = BIT(0), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic1_temp_shtdn", ++ .reg = NVSW_REG_ASIC2_HEALTH_OFFSET, ++ .mask = BIT(1), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic2_temp_warn", ++ .reg = NVSW_REG_ASIC2_HEALTH_OFFSET, ++ .mask = BIT(2), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic2_temp_shtdn", ++ .reg = NVSW_REG_ASIC2_HEALTH_OFFSET, ++ .mask = BIT(3), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic3_temp_warn", ++ .reg = NVSW_REG_ASIC2_HEALTH_OFFSET, ++ .mask = BIT(4), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic3_temp_shtdn", ++ .reg = NVSW_REG_ASIC2_HEALTH_OFFSET, ++ .mask = BIT(5), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic4_temp_warn", ++ .reg = NVSW_REG_ASIC2_HEALTH_OFFSET, ++ .mask = BIT(6), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic4_temp_shtdn", ++ .reg = NVSW_REG_ASIC2_HEALTH_OFFSET, ++ .mask = BIT(7), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid180_leakage_items_data[] = { ++ { ++ .label = "leakage1", ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = BIT(0), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "leakage2", ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = BIT(1), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid180_alarms_items_data[] = { ++ { ++ .label = "ssd_i2c_alert", ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = NVSW_SSD_I2C_ALERT_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "wd_exp", ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = NVSW_WD_EXP_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "51v_usb", ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = NVSW_5V_USB_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "ssd_pg", ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = BIT(3), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "leakage_aggr", ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = BIT(4), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid180_alarms2_items_data[] = { ++ { ++ .label = "psys_alert", ++ .reg = NVSW_REG_HEALTH_OFFSET, ++ .mask = BIT(0), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "vdd_mem", ++ .reg = NVSW_REG_HEALTH_OFFSET, ++ .mask = BIT(1), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "svi2_vr_alert", ++ .reg = NVSW_REG_HEALTH_OFFSET, ++ .mask = BIT(2), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "thermtrip_alert", ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = BIT(3), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid180_vr1_pwr_alert_items_data[] = { ++ { ++ .label = "asic1_vdd_pwr_alert", ++ .reg = NVSW_REG_VR1_ALERT_OFFSET, ++ .mask = BIT(0), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic1_avdd_dvdd_pl0_pwr_alert", ++ .reg = NVSW_REG_VR1_ALERT_OFFSET, ++ .mask = BIT(1), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic1_avdd_dvdd_pl1_pwr_alert", ++ .reg = NVSW_REG_VR1_ALERT_OFFSET, ++ .mask = BIT(2), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic1_hvdd_avcc_pwr_alert", ++ .reg = NVSW_REG_VR1_ALERT_OFFSET, ++ .mask = BIT(3), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic2_vdd_pwr_alert", ++ .reg = NVSW_REG_VR1_ALERT_OFFSET, ++ .mask = BIT(4), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic2_avdd_dvdd_pl0_pwr_alert", ++ .reg = NVSW_REG_VR1_ALERT_OFFSET, ++ .mask = BIT(5), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic2_avdd_dvdd_pl1_pwr_alert", ++ .reg = NVSW_REG_VR1_ALERT_OFFSET, ++ .mask = BIT(6), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic2_hvdd_avcc_pwr_alert", ++ .reg = NVSW_REG_VR1_ALERT_OFFSET, ++ .mask = BIT(7), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid180_vr2_pwr_alert_items_data[] = { ++ { ++ .label = "asic3_vdd_pwr_alert", ++ .reg = NVSW_REG_VR2_ALERT_OFFSET, ++ .mask = BIT(0), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic3_avdd_dvdd_pl0_pwr_alert", ++ .reg = NVSW_REG_VR2_ALERT_OFFSET, ++ .mask = BIT(1), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic3_avdd_dvdd_pl1_pwr_alert", ++ .reg = NVSW_REG_VR2_ALERT_OFFSET, ++ .mask = BIT(2), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic3_hvdd_avcc_pwr_alert", ++ .reg = NVSW_REG_VR2_ALERT_OFFSET, ++ .mask = BIT(3), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic4_vdd_pwr_alert", ++ .reg = NVSW_REG_VR2_ALERT_OFFSET, ++ .mask = BIT(4), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic4_avdd_dvdd_pl0_pwr_alert", ++ .reg = NVSW_REG_VR2_ALERT_OFFSET, ++ .mask = BIT(5), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic4_avdd_dvdd_pl1_pwr_alert", ++ .reg = NVSW_REG_VR2_ALERT_OFFSET, ++ .mask = BIT(6), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "asic4_hvdd_avcc_pwr_alert", ++ .reg = NVSW_REG_VR2_ALERT_OFFSET, ++ .mask = BIT(7), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid180_erot_error_items_data[] = { ++ { ++ .label = "erot_cpu_error", ++ .reg = NVSW_REG_EROT_ERR_OFFSET, ++ .mask = BIT(0), ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_item nvsw_bmc_hid180_hotplug_items_data[] = { ++ { ++ .data = nvsw_bmc_hid180_pg1_events_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_PG1_OFFSET, ++ .mask = GENMASK(7, 0), ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_pg1_events_items_data), ++ .inversed = 1, ++ .health = false, ++ .non_sticky = true, ++ }, ++ { ++ .data = nvsw_bmc_hid180_pg2_events_items_data, ++ .aggr_mask = NVSW_AGGR_MASK_COMEX, ++ .reg = NVSW_REG_PG2_OFFSET, ++ .mask = GENMASK(7, 0), ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_pg2_events_items_data), ++ .inversed = 1, ++ .health = false, ++ .non_sticky = true, ++ }, ++ { ++ .data = nvsw_bmc_hid180_pg3_events_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = GENMASK(7, 0), ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_pg3_events_items_data), ++ .inversed = 1, ++ .health = false, ++ .non_sticky = true, ++ }, ++ { ++ .data = nvsw_bmc_hid180_pg4_events_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_PG3_OFFSET, ++ .mask = NVSW_AGGR_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_pg4_events_items_data), ++ .inversed = 1, ++ .health = false, ++ .non_sticky = true, ++ }, ++ { ++ .data = nvsw_bmc_hid180_pg5_events_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_PG4_OFFSET, ++ .mask = GENMASK(7, 0), ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_pg5_events_items_data), ++ .inversed = 1, ++ .health = false, ++ .non_sticky = true, ++ }, ++ { ++ .data = nvsw_bmc_hid180_asic_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASICS_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_asic_items_data), ++ .inversed = 0, ++ .health = true, ++ }, ++ { ++ .data = nvsw_bmc_hid180_asic_temp_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_ASIC2_HEALTH_OFFSET, ++ .mask = NVSW_ASICS_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_asic_temp_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++ { ++ .data = nvsw_bmc_hid180_leakage_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = GENMASK(1, 0), ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_leakage_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++ { ++ .data = nvsw_bmc_hid180_alarms_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = GENMASK(4, 0), ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_alarms_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++ { ++ .data = nvsw_bmc_hid180_alarms2_items_data, ++ .aggr_mask = NVSW_AGGR_MASK_COMEX, ++ .reg = NVSW_REG_HEALTH_OFFSET, ++ .mask = GENMASK(3, 0), ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_alarms2_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++ { ++ .data = nvsw_bmc_hid180_vr1_pwr_alert_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_VR1_ALERT_OFFSET, ++ .mask = GENMASK(7, 0), ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_vr1_pwr_alert_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++ { ++ .data = nvsw_bmc_hid180_vr2_pwr_alert_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_VR2_ALERT_OFFSET, ++ .mask = GENMASK(7, 0), ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_vr2_pwr_alert_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++ { ++ .data = nvsw_bmc_hid180_erot_error_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_EROT_ERR_OFFSET, ++ .mask = BIT(0), ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_erot_error_items_data), ++ .inversed = 1, ++ .health = false, ++ }, ++ { ++ .data = nvsw_bmc_hid162_events_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_PWRB_OFFSET, ++ .mask = NVSW_PWR_BUTTON_MASK | NVSW_AMB_TEMP_SENSE_MASK | ++ NVSW_GRACEFUL_POWER_OFF_MASK | NVSW_CPU_POWER_OFF_READY_MASK | ++ NVSW_CPU_RESET_MASK | NVSW_APML_SMB_ALERT_MASK | ++ NVSW_CPU_UNEXP_POWER_OFF_MASK | NVSW_UID_PUSH_BUTTON_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_events_items_data), ++ .inversed = 1, ++ .health = false, ++ .non_sticky = true, ++ }, ++ { ++ .data = nvsw_bmc_hid162_cartridge_items_data, ++ .aggr_mask = NVSW_AGGR_MASK, ++ .reg = NVSW_REG_FRU1_OFFSET, ++ .mask = NVSW_REG_FRU1_MASK, ++ .count = ARRAY_SIZE(nvsw_bmc_hid162_cartridge_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++}; ++ ++static ++struct mlxreg_core_hotplug_platform_data nvsw_bmc_hid180_hotplug = { ++ .items = nvsw_bmc_hid180_hotplug_items_data, ++ .count = ARRAY_SIZE(nvsw_bmc_hid180_hotplug_items_data), ++ .cell = NVSW_REG_AGGR_OFFSET, ++ .mask = NVSW_AGGR_MASK | NVSW_AGGR_MASK_COMEX, ++ .cell_low = NVSW_REG_AGGRLO_OFFSET, ++ .mask_low = GENMASK(6, 0), ++}; ++ ++/* Platform register access data. */ ++static struct mlxreg_core_data nvsw_bmc_hid162_regio_data[] = { ++ { ++ .label = "cpld1_version", ++ .reg = NVSW_REG_CPLD1_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld2_version", ++ .reg = NVSW_REG_CPLD2_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld3_version", ++ .reg = NVSW_REG_CPLD3_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld4_version", ++ .reg = NVSW_REG_CPLD4_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld1_pn", ++ .reg = NVSW_REG_CPLD1_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld2_pn", ++ .reg = NVSW_REG_CPLD2_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld3_pn", ++ .reg = NVSW_REG_CPLD3_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld4_pn", ++ .reg = NVSW_REG_CPLD4_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld1_version_min", ++ .reg = NVSW_REG_CPLD1_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld2_version_min", ++ .reg = NVSW_REG_CPLD2_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld3_version_min", ++ .reg = NVSW_REG_CPLD3_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld4_version_min", ++ .reg = NVSW_REG_CPLD4_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "fan_dir", ++ .reg = NVSW_REG_GP0_RO_OFFSET, ++ .mask = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "fan_present", ++ .reg = NVSW_REG_FAN_OFFSET, ++ .mask = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpu_mctp_ready", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_shutdown_req", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0644, ++ }, ++ { ++ .label = "vpd_wp", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ .secured = 1, ++ }, ++ { ++ .label = "pcie_asic_reset_dis", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, ++ }, ++ { ++ .label = "shutdown_unlock", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_power_off_ready", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "ignore_next_reset", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0644, ++ }, ++ { ++ .label = "leakage_conn_en", ++ .reg = NVSW_REG_GP6_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0644, ++ }, ++ { ++ .label = "bmc_reset_reg", ++ .reg = NVSW_REG_GP6_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0644, ++ }, ++ { ++ .label = "spi_chnl_select", ++ .reg = NVSW_REG_SPI_CHNL_SELECT, ++ .mask = GENMASK(7, 0), ++ .bit = 1, ++ .mode = 0644, ++ }, ++ { ++ .label = "pwr_converter_prog_en", ++ .reg = NVSW_REG_GP7_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0644, ++ .secured = 1, ++ }, ++ { ++ .label = "graceful_power_off", ++ .reg = NVSW_REG_GP7_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ }, ++ { ++ .label = "bmc_perst_en", ++ .reg = NVSW_REG_GP7_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0200, ++ }, ++ { ++ .label = "bmc_shutdown_unlock", ++ .reg = NVSW_REG_GP7_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0200, ++ }, ++ { ++ .label = "platform_reset", ++ .reg = NVSW_REG_RESET_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0200, ++ }, ++ { ++ .label = "main_brd_reset", ++ .reg = NVSW_REG_RESET_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0200, ++ }, ++ { ++ .label = "nic_reset", ++ .reg = NVSW_REG_RESET_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0200, ++ }, ++ { ++ .label = "tpm_reset", ++ .reg = NVSW_REG_RESET_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0200, ++ }, ++ { ++ .label = "erot_asic3_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0200, ++ }, ++ { ++ .label = "asics_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0200, ++ }, ++ { ++ .label = "sgmii_phy_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0200, ++ }, ++ { ++ .label = "erot_cpu_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0200, ++ }, ++ { ++ .label = "erot_asic1_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0200, ++ }, ++ { ++ .label = "erot_asic2_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0200, ++ }, ++ { ++ .label = "jtag_enable", ++ .reg = NVSW_REG_FIELD_UPGRADE, ++ .mask = GENMASK(1, 0), ++ .bit = 1, ++ .mode = 0644, ++ }, ++ { ++ .label = "non_active_bios_select", ++ .reg = NVSW_REG_SAFE_BIOS_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, ++ }, ++ { ++ .label = "bios_upgrade_fail", ++ .reg = NVSW_REG_SAFE_BIOS_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_image_invert", ++ .reg = NVSW_REG_SAFE_BIOS_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "erot_asic3_recovery", ++ .reg = NVSW_REG_PWM_CONTROL_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, ++ }, ++ { ++ .label = "erot_cpu_recovery", ++ .reg = NVSW_REG_PWM_CONTROL_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, ++ }, ++ { ++ .label = "erot_asic1_recovery", ++ .reg = NVSW_REG_PWM_CONTROL_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "erot_asic2_recovery", ++ .reg = NVSW_REG_PWM_CONTROL_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0644, ++ }, ++ { ++ .label = "pwr_button_halt", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0644, ++ }, ++ { ++ .label = "pwr_cycle", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0200, ++ }, ++ { ++ .label = "pwr_down", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ }, ++ { ++ .label = "aux_pwr_cycle", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0200, ++ }, ++ { ++ .label = "bmc_to_cpu_ctrl", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, ++ }, ++ { ++ .label = "uart_sel", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = NVSW_UART_SEL_MASK, ++ .bit = 7, ++ .mode = 0644, ++ }, ++ { ++ .label = "reset_long_pb", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_short_pb", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_aux_pwr_or_fu", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_swb_pwr_fail", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_pwr_button_or_leak_con", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_swb_wd", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_asic_thermal", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_from_carrier", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_aux_pwr_or_reload", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_comex_pwr_fail", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_platform", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_soc", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_from_erot", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_pwr", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_erot", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_system", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_sw_pwr_off", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_comex_thermal", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_comex_power", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_pwr_converter_fail", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_main_51v", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_mgmt_pwr", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "port80", ++ .reg = NVSW_REG_GP1_RO_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_status", ++ .reg = NVSW_REG_GPCOM0_OFFSET, ++ .mask = NVSW_BIOS_STATUS_MASK, ++ .bit = 2, ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_start_retry", ++ .reg = NVSW_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_active_image", ++ .reg = NVSW_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "ufm_version", ++ .reg = NVSW_REG_UFM_VERSION_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "clk_brd1_boot_fail", ++ .reg = NVSW_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "clk_brd2_boot_fail", ++ .reg = NVSW_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "clk_brd_fail", ++ .reg = NVSW_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, ++ }, ++ { ++ .label = "asic_pg_fail", ++ .reg = NVSW_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "geo_addr", ++ .reg = NVSW_REG_CONFIG2_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data nvsw_bmc_hid162_regio = { ++ .data = nvsw_bmc_hid162_regio_data, ++ .counter = ARRAY_SIZE(nvsw_bmc_hid162_regio_data), ++}; ++ ++static struct mlxreg_core_data nvsw_bmc_hid180_regio_data[] = { ++ { ++ .label = "cpld1_version", ++ .reg = NVSW_REG_CPLD1_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld2_version", ++ .reg = NVSW_REG_CPLD2_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld1_pn", ++ .reg = NVSW_REG_CPLD1_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld2_pn", ++ .reg = NVSW_REG_CPLD2_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld1_version_min", ++ .reg = NVSW_REG_CPLD1_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld2_version_min", ++ .reg = NVSW_REG_CPLD2_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_status", ++ .reg = NVSW_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(3, 1), ++ .bit = 3, ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_start_retry", ++ .reg = NVSW_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_active_image", ++ .reg = NVSW_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "pwr_converter_prog_en", ++ .reg = NVSW_REG_GP7_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_mctp_ready", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_shutdown_req", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "vpd_wp", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ .secured = 1, ++ }, ++ { ++ .label = "pcie_asic_reset_dis", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, ++ }, ++ { ++ .label = "shutdown_unlock", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_power_off_ready", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "pwr_cycle", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0244, ++ }, ++ { ++ .label = "pwr_down", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0200, ++ }, ++ { ++ .label = "aux_pwr_cycle", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0200, ++ }, ++ { ++ .label = "bmc_to_cpu_ctrl", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, ++ }, ++ { ++ .label = "uart_sel", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = NVSW_UART_SEL_MASK, ++ .bit = 7, ++ .mode = 0644, ++ }, ++ { ++ .label = "asics_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ }, ++ { ++ .label = "sgmii_phy_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_erot_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, ++ }, ++ { ++ .label = "mcu1_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "mcu2_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "reset_long_pb", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_short_pb", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_aux_pwr_or_fu", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_swb_dc_dc_pwr_fail", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_pwr_button_or_leak_con", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_swb_wd", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_asic_thermal", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_from_cpld", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_comex_pwr_fail", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_platform", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_soc", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_erot", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_system", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_sw_pwr_off", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_comex_thermal", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_comex_power", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_pwr_converter_fail", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_main_51v", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_mgmt_pwr", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "port80", ++ .reg = NVSW_REG_GP1_RO_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "transport_status", ++ .reg = NVSW_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(1, 0), ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "asics_pg_fail", ++ .reg = NVSW_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "jtag_cap", ++ .reg = NVSW_REG_FU_CAP_OFFSET, ++ .mask = NVSW_FU_CAP_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "jtag_enable", ++ .reg = NVSW_REG_FIELD_UPGRADE, ++ .mask = GENMASK(1, 0), ++ .bit = 1, ++ .mode = 0644, ++ }, ++ { ++ .label = "non_active_bios_select", ++ .reg = NVSW_REG_SAFE_BIOS_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, ++ }, ++ { ++ .label = "bios_upgrade_fail", ++ .reg = NVSW_REG_SAFE_BIOS_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_image_invert", ++ .reg = NVSW_REG_SAFE_BIOS_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "erot_cpu_recovery", ++ .reg = NVSW_REG_PWM_CONTROL_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, ++ }, ++ { ++ .label = "mcu1_recovery", ++ .reg = NVSW_REG_PWM_CONTROL_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "mcu2_recovery", ++ .reg = NVSW_REG_PWM_CONTROL_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_int_enable", ++ .reg = NVSW_REG_GP5_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_tps_upgrade", ++ .reg = NVSW_REG_GP5_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_spi_ctrl", ++ .reg = NVSW_REG_GP5_OFFSET, ++ .mask = GENMASK(4, 2), ++ .bit = 4, ++ .mode = 0644, ++ }, ++ { ++ .label = "ignore_next_reset", ++ .reg = NVSW_REG_GP5_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "leakage_conn_en", ++ .reg = NVSW_REG_GP6_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0644, ++ }, ++ { ++ .label = "bmc_reset_reg", ++ .reg = NVSW_REG_GP6_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0644, ++ }, ++ { ++ .label = "asic_pg_fail", ++ .reg = NVSW_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "spi_chnl_select", ++ .reg = NVSW_REG_SPI_CHNL_SELECT, ++ .mask = GENMASK(7, 0), ++ .bit = 1, ++ .mode = 0644, ++ }, ++ { ++ .label = "config1", ++ .reg = NVSW_REG_CONFIG1_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "config2", ++ .reg = NVSW_REG_CONFIG2_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "config3", ++ .reg = NVSW_REG_CONFIG3_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "graseful_pwr_off", ++ .reg = NVSW_REG_GP7_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data nvsw_bmc_hid180_regio = { ++ .data = nvsw_bmc_hid180_regio_data, ++ .counter = ARRAY_SIZE(nvsw_bmc_hid180_regio_data), ++}; ++ ++/* Platform fan data. */ ++static struct mlxreg_core_data nvsw_bmc_hid162_fan_data[] = { ++ { ++ .label = "pwm1", ++ .reg = NVSW_REG_PWM1_OFFSET, ++ }, ++ { ++ .label = "tacho1", ++ .reg = NVSW_REG_TACHO1_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 1, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho2", ++ .reg = NVSW_REG_TACHO2_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 2, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho3", ++ .reg = NVSW_REG_TACHO3_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 3, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho4", ++ .reg = NVSW_REG_TACHO4_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 4, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho5", ++ .reg = NVSW_REG_TACHO5_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 5, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho6", ++ .reg = NVSW_REG_TACHO6_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 6, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho7", ++ .reg = NVSW_REG_TACHO7_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 7, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho8", ++ .reg = NVSW_REG_TACHO8_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 8, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho9", ++ .reg = NVSW_REG_TACHO9_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 9, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho10", ++ .reg = NVSW_REG_TACHO10_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 10, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho11", ++ .reg = NVSW_REG_TACHO11_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 11, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho12", ++ .reg = NVSW_REG_TACHO12_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = NVSW_REG_FAN_CAP1_OFFSET, ++ .slot = 12, ++ .reg_prsnt = NVSW_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "conf", ++ .mask = NVSW_HID162_TACHO_SAMPLES, ++ .bit = NVSW_HID162_TACHO_DIV, ++ .capability = NVSW_REG_TACHO_SPEED_OFFSET, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data nvsw_bmc_hid162_fan = { ++ .data = nvsw_bmc_hid162_fan_data, ++ .counter = ARRAY_SIZE(nvsw_bmc_hid162_fan_data), ++ .capability = NVSW_REG_FAN_DRW_CAP_OFFSET, ++ .version = 1, ++}; ++ ++/* Platform led data for HI162 system type. */ ++static struct mlxreg_core_data nvsw_bmc_hid162_led_data[] = { ++ { ++ .label = "status:green", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "status:amber", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "power:green", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "power:amber", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "uid:blue", ++ .reg = NVSW_REG_LED5_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "fan:green", ++ .reg = NVSW_REG_LED6_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "fan:amber", ++ .reg = NVSW_REG_LED6_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data nvsw_bmc_hid162_led = { ++ .data = nvsw_bmc_hid162_led_data, ++ .counter = ARRAY_SIZE(nvsw_bmc_hid162_led_data), ++}; ++ ++/* Platform led data for HI1676 system type. */ ++static struct mlxreg_core_data nvsw_bmc_hid176_led_data[] = { ++ { ++ .label = "status:green", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "status:amber", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "power:green", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "power:amber", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "uid:blue", ++ .reg = NVSW_REG_LED5_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "leakage:green", ++ .reg = NVSW_REG_LED7_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "leakage:amber", ++ .reg = NVSW_REG_LED7_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data nvsw_bmc_hid176_led = { ++ .data = nvsw_bmc_hid176_led_data, ++ .counter = ARRAY_SIZE(nvsw_bmc_hid176_led_data), ++}; ++ ++/* Platform led data for HI1676 system type. */ ++static struct mlxreg_core_data nvsw_bmc_hid177_led_data[] = { ++ { ++ .label = "status:green", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "status:amber", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "power:green", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "power:amber", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "uid:blue", ++ .reg = NVSW_REG_LED5_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data nvsw_bmc_hid177_led = { ++ .data = nvsw_bmc_hid177_led_data, ++ .counter = ARRAY_SIZE(nvsw_bmc_hid177_led_data), ++}; ++ ++/* Mux init/exit callbacks. */ ++static int nvsw_bmc_hid162_mux_topology_init(struct nvsw_core *nvsw_core) ++{ ++ int i, err; ++ ++ /* Create mux infrastructure. */ ++ for (i = 0; i < nvsw_core->mux_num; i++) { ++ mux_data[i]->regmap = nvsw_core->regmap; ++ nvsw_core->mux[i] = platform_device_register_resndata(nvsw_core->dev, ++ "i2c-mux-regmap", i, NULL, 0, ++ mux_data[i], ++ sizeof(*mux_data[i])); ++ if (IS_ERR(nvsw_core->mux[i])) { ++ dev_err(nvsw_core->dev, "Failed to create mux infra\n"); ++ err = PTR_ERR(nvsw_core->mux[i]); ++ goto fail_platform_mux_register; ++ } ++ } ++ ++ return 0; ++fail_platform_mux_register: ++ while (--i >= 0) ++ platform_device_unregister(nvsw_core->mux[i]); ++ return err; ++} ++ ++static void nvsw_bmc_hid162_mux_topology_exit(struct nvsw_core *nvsw_core) ++{ ++ int i; ++ ++ for (i = 0; i < nvsw_core->mux_num; i++) { ++ if (nvsw_core->mux[i]) ++ platform_device_unregister(nvsw_core->mux[i]); ++ } ++} ++ ++/* Callbact to set initial values for specific registers. */ ++static int nvsw_bmc_hid162_set_reg_default(struct regmap *regmap) ++{ ++ u32 regval; ++ int err; ++ ++ err = regmap_read(regmap, NVSW_REG_GP6_OFFSET, ®val); ++ if (err) ++ return err; ++ ++ return regmap_write(regmap, NVSW_REG_GP6_OFFSET, regval | NVSW_REG_RESET_MASK); ++} ++ ++/* Callback is used to indicate that all adapter devices has been created. */ ++static int ++nvsw_bmc_hid162_completion_notify(void *handle, struct i2c_adapter *parent, ++ struct i2c_adapter *adapters[]) ++{ ++ /* struct nvsw_core *nvsw_core = handle; */ ++ ++ return 0; ++} ++ ++static int nvsw_bmc_hid162_platform_data_init(struct nvsw_core *nvsw_core) ++{ ++ int i; ++ ++ /* Set system configuration. */ ++ nvsw_core->hid = HID162; ++ nvsw_core->mux_num = ARRAY_SIZE(nvsw_bmc_hid162_mux_data); ++ for (i = 0; i < nvsw_core->mux_num; i++) { ++ mux_data[i] = &nvsw_bmc_hid162_mux_data[i]; ++ mux_data[i]->handle = nvsw_core; ++ mux_data[i]->completion_notify = nvsw_bmc_hid162_completion_notify; ++ mux_brdinfo[i] = &nvsw_bmc_hid162_mux_brdinfo; ++ mux_brdinfo[i]->platform_data = mux_data[i]; ++ } ++ ++ nvsw_core->regio_data = &nvsw_bmc_hid162_regio; ++ nvsw_core->led_data = &nvsw_bmc_hid162_led; ++ nvsw_core->fan_data = &nvsw_bmc_hid162_fan; ++ nvsw_core->hotplug_data = &nvsw_bmc_hid162_hotplug; ++ nvsw_core->mux_init = nvsw_bmc_hid162_mux_topology_init; ++ nvsw_core->mux_exit = nvsw_bmc_hid162_mux_topology_exit; ++ nvsw_core->set_reg_default = nvsw_bmc_hid162_set_reg_default; ++ ++ return 0; ++} ++ ++static int nvsw_bmc_hid176_platform_data_init(struct nvsw_core *nvsw_core) ++{ ++ int i; ++ ++ /* Set system configuration. */ ++ nvsw_core->hid = HID176; ++ nvsw_core->mux_num = ARRAY_SIZE(nvsw_bmc_hid176_mux_data); ++ for (i = 0; i < nvsw_core->mux_num; i++) { ++ mux_data[i] = &nvsw_bmc_hid176_mux_data[i]; ++ mux_data[i]->handle = nvsw_core; ++ mux_data[i]->completion_notify = nvsw_bmc_hid162_completion_notify; ++ mux_brdinfo[i] = &nvsw_bmc_hid162_mux_brdinfo; ++ mux_brdinfo[i]->platform_data = mux_data[i]; ++ } ++ ++ nvsw_core->regio_data = &nvsw_bmc_hid162_regio; ++ nvsw_core->led_data = &nvsw_bmc_hid176_led; ++ nvsw_core->hotplug_data = &nvsw_bmc_hid176_hotplug; ++ nvsw_core->mux_init = nvsw_bmc_hid162_mux_topology_init; ++ nvsw_core->mux_exit = nvsw_bmc_hid162_mux_topology_exit; ++ nvsw_core->set_reg_default = nvsw_bmc_hid162_set_reg_default; ++ ++ return 0; ++} ++ ++static int nvsw_bmc_hid177_platform_data_init(struct nvsw_core *nvsw_core) ++{ ++ int i; ++ ++ /* Set system configuration. */ ++ nvsw_core->hid = HID177; ++ nvsw_core->mux_num = ARRAY_SIZE(nvsw_bmc_hid176_mux_data); ++ for (i = 0; i < nvsw_core->mux_num; i++) { ++ mux_data[i] = &nvsw_bmc_hid176_mux_data[i]; ++ mux_data[i]->handle = nvsw_core; ++ mux_data[i]->completion_notify = nvsw_bmc_hid162_completion_notify; ++ mux_brdinfo[i] = &nvsw_bmc_hid162_mux_brdinfo; ++ mux_brdinfo[i]->platform_data = mux_data[i]; ++ } ++ ++ nvsw_core->regio_data = &nvsw_bmc_hid162_regio; ++ nvsw_core->led_data = &nvsw_bmc_hid177_led; ++ nvsw_core->hotplug_data = &nvsw_bmc_hid177_hotplug; ++ nvsw_core->mux_init = nvsw_bmc_hid162_mux_topology_init; ++ nvsw_core->mux_exit = nvsw_bmc_hid162_mux_topology_exit; ++ nvsw_core->set_reg_default = nvsw_bmc_hid162_set_reg_default; ++ ++ return 0; ++} ++ ++static int nvsw_bmc_hid180_platform_data_init(struct nvsw_core *nvsw_core) ++{ ++ int i; ++ ++ /* Set system configuration. */ ++ nvsw_core->hid = HID180; ++ nvsw_core->mux_num = ARRAY_SIZE(nvsw_bmc_hid180_mux_data); ++ for (i = 0; i < nvsw_core->mux_num; i++) { ++ mux_data[i] = &nvsw_bmc_hid180_mux_data[i]; ++ mux_data[i]->handle = nvsw_core; ++ mux_data[i]->completion_notify = nvsw_bmc_hid162_completion_notify; ++ mux_brdinfo[i] = &nvsw_bmc_hid162_mux_brdinfo; ++ mux_brdinfo[i]->platform_data = mux_data[i]; ++ } ++ ++ nvsw_core->regio_data = &nvsw_bmc_hid180_regio; ++ nvsw_core->led_data = &nvsw_bmc_hid177_led; ++ nvsw_core->hotplug_data = &nvsw_bmc_hid180_hotplug; ++ nvsw_core->mux_init = nvsw_bmc_hid162_mux_topology_init; ++ nvsw_core->mux_exit = nvsw_bmc_hid162_mux_topology_exit; ++ nvsw_core->set_reg_default = nvsw_bmc_hid162_set_reg_default; ++ ++ return 0; ++} ++ ++static int nvsw_bmc_platform_data_init(struct nvsw_core *nvsw_core, enum nvsw_core_hid_type type) ++{ ++ switch (type) { ++ case HID162: ++ return nvsw_bmc_hid162_platform_data_init(nvsw_core); ++ case HID176: ++ return nvsw_bmc_hid176_platform_data_init(nvsw_core); ++ case HID177: ++ return nvsw_bmc_hid177_platform_data_init(nvsw_core); ++ case HID180: ++ return nvsw_bmc_hid180_platform_data_init(nvsw_core); ++ default: ++ return -ENODEV; ++ } ++} ++ ++static int nvsw_bmc_hid162_probe(struct i2c_client *client) ++{ ++ struct device_node *np = client->dev.of_node; ++ enum nvsw_core_hid_type type; ++ struct nvsw_core *nvsw_core; ++ int err; ++ ++ if (!np) ++ return -ENODEV; ++ ++ if (of_device_is_compatible(np, "nvidia,hid162")) ++ type = HID162; ++ else if (of_device_is_compatible(np, "nvidia,hid176")) ++ type = HID176; ++ else if (of_device_is_compatible(np, "nvidia,hid177")) ++ type = HID177; ++ else if (of_device_is_compatible(np, "nvidia,hid180")) ++ type = HID180; ++ else ++ return -ENODEV; ++ ++ nvsw_core = devm_kzalloc(&client->dev, sizeof(*nvsw_core), GFP_KERNEL); ++ if (!nvsw_core) ++ return -ENOMEM; ++ ++ nvsw_core->dev = &client->dev; ++ nvsw_core->client = client; ++ nvsw_core->np = np; ++ nvsw_core->regmap_type = REGMAP_I2C; ++ i2c_set_clientdata(client, nvsw_core); ++ err = nvsw_bmc_platform_data_init(nvsw_core, type); ++ if (err) ++ return err; ++ ++ return nvsw_core_init(nvsw_core); ++} ++ ++static void nvsw_bmc_hid162_remove(struct i2c_client *client) ++{ ++ struct nvsw_core *nvsw_core = i2c_get_clientdata(client); ++ ++ nvsw_core_exit(nvsw_core); ++} ++ ++static const struct i2c_device_id nvsw_bmc_hid162_id[] = { ++ { "hid162", HID162 }, ++ { "hid176", HID176 }, ++ { "hid177", HID177 }, ++ { "hid180", HID180 }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(i2c, nvsw_bmc_hid162_id); ++ ++static const struct of_device_id nvsw_bmc_hid162_dt_match[] = { ++ { .compatible = "nvidia,hid162" }, ++ { .compatible = "nvidia,hid176" }, ++ { .compatible = "nvidia,hid177" }, ++ { .compatible = "nvidia,hid180" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, nvsw_bmc_hid162_dt_match); ++ ++static struct i2c_driver nvsw_bmc_hid162_driver = { ++ .driver = { ++ .name = "nvsw-bmc-hid162", ++ .of_match_table = of_match_ptr(nvsw_bmc_hid162_dt_match), ++ }, ++ .probe = nvsw_bmc_hid162_probe, ++ .remove = nvsw_bmc_hid162_remove, ++ .id_table = nvsw_bmc_hid162_id, ++}; ++ ++module_i2c_driver(nvsw_bmc_hid162_driver); ++ ++MODULE_AUTHOR("Vadim Pasternak "); ++MODULE_DESCRIPTION("Nvidia platform driver"); ++MODULE_LICENSE("Dual BSD/GPL"); +diff --git a/drivers/platform/mellanox/nvsw-core.c b/drivers/platform/mellanox/nvsw-core.c +new file mode 100644 +index 00000000..bfe56ab +--- /dev/null ++++ b/drivers/platform/mellanox/nvsw-core.c +@@ -0,0 +1,625 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Nvidia BMC platform driver ++ * ++ * Copyright (C) 2025 Nvidia Technologies Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "nvsw.h" ++ ++static bool nvsw_writeable_reg(struct device *dev, unsigned int reg) ++{ ++ switch (reg) { ++ case NVSW_REG_PG1_EVENT_OFFSET: ++ case NVSW_REG_PG1_MASK_OFFSET: ++ case NVSW_REG_PG2_EVENT_OFFSET: ++ case NVSW_REG_PG2_MASK_OFFSET: ++ case NVSW_REG_PG3_EVENT_OFFSET: ++ case NVSW_REG_PG3_MASK_OFFSET: ++ case NVSW_REG_PG4_EVENT_OFFSET: ++ case NVSW_REG_RESET_GP1_OFFSET: ++ case NVSW_REG_FIELD_UPGRADE: ++ case NVSW_REG_GP0_OFFSET: ++ case NVSW_REG_GP1_OFFSET: ++ case NVSW_REG_GP7_OFFSET: ++ case NVSW_REG_PWM_CONTROL_OFFSET: ++ case NVSW_REG_RESET_GP2_OFFSET: ++ case NVSW_REG_GP4_OFFSET: ++ case NVSW_REG_GP5_OFFSET: ++ case NVSW_REG_GP6_OFFSET: ++ case NVSW_REG_LED1_OFFSET: ++ case NVSW_REG_LED5_OFFSET: ++ case NVSW_REG_LED6_OFFSET: ++ case NVSW_REG_LED7_OFFSET: ++ case NVSW_REG_AGGRCO_MASK_OFFSET: ++ case NVSW_REG_HEALTH_EVENT_OFFSET: ++ case NVSW_REG_HEALTH_MASK_OFFSET: ++ case NVSW_REG_AGGR_MASK_OFFSET: ++ case NVSW_REG_FU_CAP_OFFSET: ++ case NVSW_REG_BRD4_EVENT_OFFSET: ++ case NVSW_REG_BRD4_MASK_OFFSET: ++ case NVSW_REG_AGGRLO_MASK_OFFSET: ++ case NVSW_REG_BRD1_EVENT_OFFSET: ++ case NVSW_REG_BRD1_MASK_OFFSET: ++ case NVSW_REG_ASIC1_EVENT_OFFSET: ++ case NVSW_REG_ASIC1_MASK_OFFSET: ++ case NVSW_REG_ASIC2_EVENT_OFFSET: ++ case NVSW_REG_ASIC2_MASK_OFFSET: ++ case NVSW_REG_ASIC3_EVENT_OFFSET: ++ case NVSW_REG_ASIC3_MASK_OFFSET: ++ case NVSW_REG_VR1_ALERT_EVENT_OFFSET: ++ case NVSW_REG_VR1_ALERT_MASK_OFFSET: ++ case NVSW_REG_VR2_ALERT_EVENT_OFFSET: ++ case NVSW_REG_VR2_ALERT_MASK_OFFSET: ++ case NVSW_REG_FAN_EVENT_OFFSET: ++ case NVSW_REG_FAN_MASK_OFFSET: ++ case NVSW_REG_PWRB_EVENT_OFFSET: ++ case NVSW_REG_PWRB_MASK_OFFSET: ++ case NVSW_REG_EROT_EVENT_OFFSET: ++ case NVSW_REG_EROT_MASK_OFFSET: ++ case NVSW_REG_EROT_ERR_EVENT_OFFSET: ++ case NVSW_REG_EROT_ERR_MASK_OFFSET: ++ case NVSW_REG_FRU1_EVENT_OFFSET: ++ case NVSW_REG_FRU1_MASK_OFFSET: ++ case NVSW_REG_LEAK_EVENT_OFFSET: ++ case NVSW_REG_LEAK_MASK_OFFSET: ++ case NVSW_REG_SPI_CHNL_SELECT: ++ case NVSW_REG_WD2_TMR_OFFSET: ++ case NVSW_REG_WD2_TLEFT_OFFSET: ++ case NVSW_REG_WD2_ACT_OFFSET: ++ case NVSW_REG_WD3_TMR_OFFSET: ++ case NVSW_REG_WD3_TLEFT_OFFSET: ++ case NVSW_REG_WD3_ACT_OFFSET: ++ case NVSW_REG_PWM1_OFFSET: ++ case NVSW_REG_MUX0_OFFSET: ++ case NVSW_REG_MUX1_OFFSET: ++ case NVSW_REG_MUX2_OFFSET: ++ return true; ++ } ++ return false; ++} ++ ++static bool nvsw_readable_reg(struct device *dev, unsigned int reg) ++{ ++ switch (reg) { ++ case NVSW_REG_CPLD1_VER_OFFSET: ++ case NVSW_REG_CPLD1_PN_OFFSET: ++ case NVSW_REG_CPLD1_PN1_OFFSET: ++ case NVSW_REG_CPLD2_VER_OFFSET: ++ case NVSW_REG_CPLD2_PN_OFFSET: ++ case NVSW_REG_CPLD2_PN1_OFFSET: ++ case NVSW_REG_CPLD3_VER_OFFSET: ++ case NVSW_REG_CPLD3_PN_OFFSET: ++ case NVSW_REG_CPLD3_PN1_OFFSET: ++ case NVSW_REG_CPLD4_VER_OFFSET: ++ case NVSW_REG_CPLD4_PN_OFFSET: ++ case NVSW_REG_CPLD4_PN1_OFFSET: ++ case NVSW_REG_PG1_OFFSET: ++ case NVSW_REG_PG1_EVENT_OFFSET: ++ case NVSW_REG_PG1_MASK_OFFSET: ++ case NVSW_REG_PG2_OFFSET: ++ case NVSW_REG_PG2_EVENT_OFFSET: ++ case NVSW_REG_PG2_MASK_OFFSET: ++ case NVSW_REG_PG3_OFFSET: ++ case NVSW_REG_PG3_EVENT_OFFSET: ++ case NVSW_REG_PG3_MASK_OFFSET: ++ case NVSW_REG_PG4_OFFSET: ++ case NVSW_REG_PG4_EVENT_OFFSET: ++ case NVSW_REG_PG4_MASK_OFFSET: ++ case NVSW_REG_RESET_GP1_OFFSET: ++ case NVSW_REG_FIELD_UPGRADE: ++ case NVSW_REG_SAFE_BIOS_OFFSET: ++ case NVSW_REG_RESET_CAUSE_OFFSET: ++ case NVSW_REG_RESET_CAUSE1_OFFSET: ++ case NVSW_REG_RESET_CAUSE2_OFFSET: ++ case NVSW_REG_LED1_OFFSET: ++ case NVSW_REG_LED5_OFFSET: ++ case NVSW_REG_LED6_OFFSET: ++ case NVSW_REG_LED7_OFFSET: ++ case NVSW_REG_RESET_GP2_OFFSET: ++ case NVSW_REG_GP0_RO_OFFSET: ++ case NVSW_REG_GP1_RO_OFFSET: ++ case NVSW_REG_GP4_RO_OFFSET: ++ case NVSW_REG_GPCOM0_OFFSET: ++ case NVSW_REG_GP0_OFFSET: ++ case NVSW_REG_GP1_OFFSET: ++ case NVSW_REG_GP7_OFFSET: ++ case NVSW_REG_PWM_CONTROL_OFFSET: ++ case NVSW_REG_GP4_OFFSET: ++ case NVSW_REG_GP5_OFFSET: ++ case NVSW_REG_GP6_OFFSET: ++ case NVSW_REG_AGGRCO_OFFSET: ++ case NVSW_REG_AGGRCO_MASK_OFFSET: ++ case NVSW_REG_HEALTH_OFFSET: ++ case NVSW_REG_HEALTH_EVENT_OFFSET: ++ case NVSW_REG_HEALTH_MASK_OFFSET: ++ case NVSW_REG_AGGR_OFFSET: ++ case NVSW_REG_AGGR_MASK_OFFSET: ++ case NVSW_REG_FU_CAP_OFFSET: ++ case NVSW_REG_BRD4_OFFSET: ++ case NVSW_REG_BRD4_EVENT_OFFSET: ++ case NVSW_REG_BRD4_MASK_OFFSET: ++ case NVSW_REG_AGGRLO_OFFSET: ++ case NVSW_REG_AGGRLO_MASK_OFFSET: ++ case NVSW_REG_BRD1_OFFSET: ++ case NVSW_REG_BRD1_EVENT_OFFSET: ++ case NVSW_REG_BRD1_MASK_OFFSET: ++ case NVSW_REG_ASIC1_HEALTH_OFFSET: ++ case NVSW_REG_ASIC1_EVENT_OFFSET: ++ case NVSW_REG_ASIC1_MASK_OFFSET: ++ case NVSW_REG_ASIC2_HEALTH_OFFSET: ++ case NVSW_REG_ASIC2_EVENT_OFFSET: ++ case NVSW_REG_ASIC2_MASK_OFFSET: ++ case NVSW_REG_ASIC3_HEALTH_OFFSET: ++ case NVSW_REG_ASIC3_EVENT_OFFSET: ++ case NVSW_REG_ASIC3_MASK_OFFSET: ++ case NVSW_REG_VR1_ALERT_OFFSET: ++ case NVSW_REG_VR1_ALERT_EVENT_OFFSET: ++ case NVSW_REG_VR1_ALERT_MASK_OFFSET: ++ case NVSW_REG_VR2_ALERT_OFFSET: ++ case NVSW_REG_VR2_ALERT_EVENT_OFFSET: ++ case NVSW_REG_VR2_ALERT_MASK_OFFSET: ++ case NVSW_REG_FAN_OFFSET: ++ case NVSW_REG_FAN_EVENT_OFFSET: ++ case NVSW_REG_FAN_MASK_OFFSET: ++ case NVSW_REG_EROT_OFFSET: ++ case NVSW_REG_EROT_EVENT_OFFSET: ++ case NVSW_REG_EROT_MASK_OFFSET: ++ case NVSW_REG_EROT_ERR_OFFSET: ++ case NVSW_REG_EROT_ERR_EVENT_OFFSET: ++ case NVSW_REG_EROT_ERR_MASK_OFFSET: ++ case NVSW_REG_PWRB_OFFSET: ++ case NVSW_REG_PWRB_EVENT_OFFSET: ++ case NVSW_REG_PWRB_MASK_OFFSET: ++ case NVSW_REG_FRU1_OFFSET: ++ case NVSW_REG_FRU1_EVENT_OFFSET: ++ case NVSW_REG_FRU1_MASK_OFFSET: ++ case NVSW_REG_LEAK_OFFSET: ++ case NVSW_REG_LEAK_EVENT_OFFSET: ++ case NVSW_REG_LEAK_MASK_OFFSET: ++ case NVSW_REG_CPLD1_MVER_OFFSET: ++ case NVSW_REG_CPLD2_MVER_OFFSET: ++ case NVSW_REG_CPLD3_MVER_OFFSET: ++ case NVSW_REG_CPLD4_MVER_OFFSET: ++ case NVSW_REG_PWM1_OFFSET: ++ case NVSW_REG_TACHO1_OFFSET: ++ case NVSW_REG_TACHO2_OFFSET: ++ case NVSW_REG_TACHO3_OFFSET: ++ case NVSW_REG_TACHO4_OFFSET: ++ case NVSW_REG_TACHO5_OFFSET: ++ case NVSW_REG_TACHO6_OFFSET: ++ case NVSW_REG_TACHO7_OFFSET: ++ case NVSW_REG_TACHO8_OFFSET: ++ case NVSW_REG_TACHO9_OFFSET: ++ case NVSW_REG_TACHO10_OFFSET: ++ case NVSW_REG_TACHO11_OFFSET: ++ case NVSW_REG_TACHO12_OFFSET: ++ case NVSW_REG_FAN_CAP1_OFFSET: ++ case NVSW_REG_FAN_DRW_CAP_OFFSET: ++ case NVSW_REG_TACHO_SPEED_OFFSET: ++ case NVSW_REG_CONFIG1_OFFSET: ++ case NVSW_REG_CONFIG2_OFFSET: ++ case NVSW_REG_CONFIG3_OFFSET: ++ case NVSW_REG_SPI_CHNL_SELECT: ++ case NVSW_REG_WD2_TMR_OFFSET: ++ case NVSW_REG_WD2_TLEFT_OFFSET: ++ case NVSW_REG_WD2_ACT_OFFSET: ++ case NVSW_REG_WD3_TMR_OFFSET: ++ case NVSW_REG_WD3_TLEFT_OFFSET: ++ case NVSW_REG_WD3_ACT_OFFSET: ++ case NVSW_REG_MUX0_OFFSET: ++ case NVSW_REG_MUX1_OFFSET: ++ case NVSW_REG_MUX2_OFFSET: ++ case NVSW_REG_UFM_VERSION_OFFSET: ++ return true; ++ } ++ return false; ++} ++ ++static bool nvsw_volatile_reg(struct device *dev, unsigned int reg) ++{ ++ switch (reg) { ++ case NVSW_REG_CPLD1_VER_OFFSET: ++ case NVSW_REG_CPLD1_PN_OFFSET: ++ case NVSW_REG_CPLD1_PN1_OFFSET: ++ case NVSW_REG_CPLD2_VER_OFFSET: ++ case NVSW_REG_CPLD2_PN_OFFSET: ++ case NVSW_REG_CPLD2_PN1_OFFSET: ++ case NVSW_REG_CPLD3_VER_OFFSET: ++ case NVSW_REG_CPLD3_PN_OFFSET: ++ case NVSW_REG_CPLD3_PN1_OFFSET: ++ case NVSW_REG_CPLD4_VER_OFFSET: ++ case NVSW_REG_CPLD4_PN_OFFSET: ++ case NVSW_REG_CPLD4_PN1_OFFSET: ++ case NVSW_REG_PG1_OFFSET: ++ case NVSW_REG_PG1_EVENT_OFFSET: ++ case NVSW_REG_PG1_MASK_OFFSET: ++ case NVSW_REG_PG2_OFFSET: ++ case NVSW_REG_PG2_EVENT_OFFSET: ++ case NVSW_REG_PG2_MASK_OFFSET: ++ case NVSW_REG_PG3_OFFSET: ++ case NVSW_REG_PG3_EVENT_OFFSET: ++ case NVSW_REG_PG3_MASK_OFFSET: ++ case NVSW_REG_PG4_OFFSET: ++ case NVSW_REG_PG4_EVENT_OFFSET: ++ case NVSW_REG_PG4_MASK_OFFSET: ++ case NVSW_REG_RESET_GP1_OFFSET: ++ case NVSW_REG_FIELD_UPGRADE: ++ case NVSW_REG_SAFE_BIOS_OFFSET: ++ case NVSW_REG_RESET_CAUSE_OFFSET: ++ case NVSW_REG_RESET_CAUSE1_OFFSET: ++ case NVSW_REG_RESET_CAUSE2_OFFSET: ++ case NVSW_REG_LED1_OFFSET: ++ case NVSW_REG_LED5_OFFSET: ++ case NVSW_REG_LED6_OFFSET: ++ case NVSW_REG_LED7_OFFSET: ++ case NVSW_REG_RESET_GP2_OFFSET: ++ case NVSW_REG_GP0_RO_OFFSET: ++ case NVSW_REG_GP1_RO_OFFSET: ++ case NVSW_REG_GPCOM0_OFFSET: ++ case NVSW_REG_GP0_OFFSET: ++ case NVSW_REG_GP1_OFFSET: ++ case NVSW_REG_GP7_OFFSET: ++ case NVSW_REG_PWM_CONTROL_OFFSET: ++ case NVSW_REG_GP4_OFFSET: ++ case NVSW_REG_GP5_OFFSET: ++ case NVSW_REG_GP6_OFFSET: ++ case NVSW_REG_AGGRCO_OFFSET: ++ case NVSW_REG_AGGRCO_MASK_OFFSET: ++ case NVSW_REG_HEALTH_OFFSET: ++ case NVSW_REG_HEALTH_EVENT_OFFSET: ++ case NVSW_REG_HEALTH_MASK_OFFSET: ++ case NVSW_REG_AGGR_OFFSET: ++ case NVSW_REG_AGGR_MASK_OFFSET: ++ case NVSW_REG_FU_CAP_OFFSET: ++ case NVSW_REG_BRD4_OFFSET: ++ case NVSW_REG_BRD4_EVENT_OFFSET: ++ case NVSW_REG_BRD4_MASK_OFFSET: ++ case NVSW_REG_AGGRLO_OFFSET: ++ case NVSW_REG_AGGRLO_MASK_OFFSET: ++ case NVSW_REG_BRD1_OFFSET: ++ case NVSW_REG_BRD1_EVENT_OFFSET: ++ case NVSW_REG_BRD1_MASK_OFFSET: ++ case NVSW_REG_ASIC1_HEALTH_OFFSET: ++ case NVSW_REG_ASIC1_EVENT_OFFSET: ++ case NVSW_REG_ASIC1_MASK_OFFSET: ++ case NVSW_REG_ASIC2_HEALTH_OFFSET: ++ case NVSW_REG_ASIC2_EVENT_OFFSET: ++ case NVSW_REG_ASIC2_MASK_OFFSET: ++ case NVSW_REG_ASIC3_HEALTH_OFFSET: ++ case NVSW_REG_ASIC3_EVENT_OFFSET: ++ case NVSW_REG_ASIC3_MASK_OFFSET: ++ case NVSW_REG_VR1_ALERT_OFFSET: ++ case NVSW_REG_VR1_ALERT_EVENT_OFFSET: ++ case NVSW_REG_VR1_ALERT_MASK_OFFSET: ++ case NVSW_REG_VR2_ALERT_OFFSET: ++ case NVSW_REG_VR2_ALERT_EVENT_OFFSET: ++ case NVSW_REG_VR2_ALERT_MASK_OFFSET: ++ case NVSW_REG_FAN_OFFSET: ++ case NVSW_REG_FAN_EVENT_OFFSET: ++ case NVSW_REG_FAN_MASK_OFFSET: ++ case NVSW_REG_EROT_OFFSET: ++ case NVSW_REG_EROT_EVENT_OFFSET: ++ case NVSW_REG_EROT_MASK_OFFSET: ++ case NVSW_REG_EROT_ERR_OFFSET: ++ case NVSW_REG_EROT_ERR_EVENT_OFFSET: ++ case NVSW_REG_EROT_ERR_MASK_OFFSET: ++ case NVSW_REG_PWRB_OFFSET: ++ case NVSW_REG_PWRB_EVENT_OFFSET: ++ case NVSW_REG_PWRB_MASK_OFFSET: ++ case NVSW_REG_FRU1_OFFSET: ++ case NVSW_REG_FRU1_EVENT_OFFSET: ++ case NVSW_REG_FRU1_MASK_OFFSET: ++ case NVSW_REG_LEAK_OFFSET: ++ case NVSW_REG_LEAK_EVENT_OFFSET: ++ case NVSW_REG_LEAK_MASK_OFFSET: ++ case NVSW_REG_GP4_RO_OFFSET: ++ case NVSW_REG_CPLD1_MVER_OFFSET: ++ case NVSW_REG_CPLD2_MVER_OFFSET: ++ case NVSW_REG_CPLD3_MVER_OFFSET: ++ case NVSW_REG_CPLD4_MVER_OFFSET: ++ case NVSW_REG_PWM1_OFFSET: ++ case NVSW_REG_TACHO1_OFFSET: ++ case NVSW_REG_TACHO2_OFFSET: ++ case NVSW_REG_TACHO3_OFFSET: ++ case NVSW_REG_TACHO4_OFFSET: ++ case NVSW_REG_TACHO5_OFFSET: ++ case NVSW_REG_TACHO6_OFFSET: ++ case NVSW_REG_TACHO7_OFFSET: ++ case NVSW_REG_TACHO8_OFFSET: ++ case NVSW_REG_TACHO9_OFFSET: ++ case NVSW_REG_TACHO10_OFFSET: ++ case NVSW_REG_TACHO11_OFFSET: ++ case NVSW_REG_TACHO12_OFFSET: ++ case NVSW_REG_FAN_CAP1_OFFSET: ++ case NVSW_REG_FAN_DRW_CAP_OFFSET: ++ case NVSW_REG_TACHO_SPEED_OFFSET: ++ case NVSW_REG_CONFIG1_OFFSET: ++ case NVSW_REG_CONFIG2_OFFSET: ++ case NVSW_REG_CONFIG3_OFFSET: ++ case NVSW_REG_SPI_CHNL_SELECT: ++ case NVSW_REG_WD2_TMR_OFFSET: ++ case NVSW_REG_WD2_TLEFT_OFFSET: ++ case NVSW_REG_WD2_ACT_OFFSET: ++ case NVSW_REG_WD3_TMR_OFFSET: ++ case NVSW_REG_WD3_TLEFT_OFFSET: ++ case NVSW_REG_WD3_ACT_OFFSET: ++ case NVSW_REG_MUX0_OFFSET: ++ case NVSW_REG_MUX1_OFFSET: ++ case NVSW_REG_MUX2_OFFSET: ++ case NVSW_REG_UFM_VERSION_OFFSET: ++ return true; ++ } ++ return false; ++} ++ ++/* Configuration for the register map of a device with 2 bytes address space. */ ++static const struct reg_default nvsw_core_reg_def[] = { ++ { NVSW_REG_AGGRCO_MASK_OFFSET, GENMASK(1, 0)}, ++ { NVSW_REG_PWM_CONTROL_OFFSET, 0x00 }, ++}; ++ ++static const struct regmap_config nvsw_regmap_i2c_conf = { ++ .reg_bits = 16, ++ .val_bits = 8, ++ .max_register = NVSW_REG_MAX, ++ .cache_type = REGCACHE_FLAT, ++ .reg_defaults = nvsw_core_reg_def, ++ .num_reg_defaults = ARRAY_SIZE(nvsw_core_reg_def), ++ .writeable_reg = nvsw_writeable_reg, ++ .readable_reg = nvsw_readable_reg, ++ .volatile_reg = nvsw_volatile_reg, ++}; ++ ++static const struct reg_default nvsw_reg_def_l1[] = { ++ { NVSW_REG_PWM_CONTROL_OFFSET, 0x00 }, ++ { NVSW_REG_WD2_ACT_OFFSET, 0x00 }, ++ { NVSW_REG_WD3_ACT_OFFSET, 0x00 }, ++ { NVSW_REG_LEAK_MASK_OFFSET, 0x3f }, ++}; ++ ++struct nvsw_io_regmap_context { ++ void __iomem *base; ++}; ++ ++static struct nvsw_io_regmap_context nvsw_io_regmap_ctx; ++ ++static int nvsw_reg_read(void *context, unsigned int reg, unsigned int *val) ++{ ++ struct nvsw_io_regmap_context *ctx = context; ++ ++ *val = ioread8(ctx->base - NVSW_REG_MIN + reg); ++ return 0; ++} ++ ++static int nvsw_reg_write(void *context, unsigned int reg, unsigned int val) ++{ ++ struct nvsw_io_regmap_context *ctx = context; ++ ++ iowrite8(val, ctx->base - NVSW_REG_MIN + reg); ++ return 0; ++} ++ ++static const struct regmap_config nvsw_regmap_conf_l1 = { ++ .reg_bits = 8, ++ .val_bits = 8, ++ .max_register = NVSW_REG_MAX, ++ .cache_type = REGCACHE_FLAT, ++ .writeable_reg = nvsw_writeable_reg, ++ .readable_reg = nvsw_readable_reg, ++ .volatile_reg = nvsw_volatile_reg, ++ .reg_defaults = nvsw_reg_def_l1, ++ .num_reg_defaults = ARRAY_SIZE(nvsw_reg_def_l1), ++ .reg_read = nvsw_reg_read, ++ .reg_write = nvsw_reg_write, ++}; ++ ++static int nvsw_core_platform_init(struct nvsw_core *nvsw_core) ++{ ++ int i, err; ++ ++ /* Add registers io access driver. */ ++ if (nvsw_core->regio_data) { ++ nvsw_core->regio_data->regmap = nvsw_core->regmap; ++ nvsw_core->regio = ++ platform_device_register_resndata(nvsw_core->dev, "mlxreg-io", ++ PLATFORM_DEVID_NONE, NULL, 0, ++ nvsw_core->regio_data, ++ sizeof(*nvsw_core->regio_data)); ++ if (IS_ERR(nvsw_core->regio)) { ++ err = PTR_ERR(nvsw_core->regio); ++ goto fail_platform_io_register; ++ } ++ } ++ ++ /* Add FAN driver. */ ++ if (nvsw_core->fan_data) { ++ nvsw_core->fan_data->regmap = nvsw_core->regmap; ++ nvsw_core->fan = platform_device_register_resndata(nvsw_core->dev, "mlxreg-fan", ++ PLATFORM_DEVID_NONE, NULL, 0, ++ nvsw_core->fan_data, ++ sizeof(*nvsw_core->fan_data)); ++ if (IS_ERR(nvsw_core->fan_data)) { ++ err = PTR_ERR(nvsw_core->fan_data); ++ goto fail_platform_fan_register; ++ } ++ } ++ ++ /* Add LED driver. */ ++ if (nvsw_core->led_data) { ++ nvsw_core->led_data->regmap = nvsw_core->regmap; ++ nvsw_core->led = platform_device_register_resndata(nvsw_core->dev, "leds-mlxreg", ++ PLATFORM_DEVID_NONE, NULL, 0, ++ nvsw_core->led_data, ++ sizeof(*nvsw_core->led_data)); ++ if (IS_ERR(nvsw_core->led)) { ++ err = PTR_ERR(nvsw_core->led); ++ goto fail_platform_leds_register; ++ } ++ } ++ ++ /* Add hotplug driver. */ ++ if (nvsw_core->hotplug_data && nvsw_core->np) { ++ nvsw_core->hotplug_data->irq = nvsw_core->client->irq; ++ dev_info(nvsw_core->dev, "irq %d\n", nvsw_core->hotplug_data->irq); ++ nvsw_core->hotplug_data->regmap = nvsw_core->regmap; ++ nvsw_core->hotplug = ++ platform_device_register_resndata(nvsw_core->dev, "mlxreg-hotplug", ++ PLATFORM_DEVID_NONE, NULL, 0, ++ nvsw_core->hotplug_data, ++ sizeof(*nvsw_core->hotplug_data)); ++ if (IS_ERR(nvsw_core->hotplug)) { ++ err = PTR_ERR(nvsw_core->hotplug); ++ goto fail_platform_hotplug_register; ++ } ++ } ++ ++ for (i = 0; i < ARRAY_SIZE(nvsw_core->wd_data); i++) { ++ if (nvsw_core->wd_data[i]) { ++ nvsw_core->wd_data[i]->regmap = nvsw_core->regmap; ++ nvsw_core->wd[i] = ++ platform_device_register_resndata(nvsw_core->dev, "mlx-wdt", i, ++ NULL, 0, nvsw_core->wd_data[i], ++ sizeof(*nvsw_core->wd_data[i])); ++ if (IS_ERR(nvsw_core->wd[i])) { ++ err = PTR_ERR(nvsw_core->wd[i]); ++ goto fail_platform_wd_register; ++ } ++ } ++ } ++ ++ return 0; ++ ++fail_platform_wd_register: ++ while (i--) ++ platform_device_unregister(nvsw_core->wd[i]); ++fail_platform_hotplug_register: ++ if (nvsw_core->led_data) ++ platform_device_unregister(nvsw_core->led); ++fail_platform_leds_register: ++ if (nvsw_core->fan_data) ++ platform_device_unregister(nvsw_core->fan); ++fail_platform_fan_register: ++ if (nvsw_core->regio_data) ++ platform_device_unregister(nvsw_core->regio); ++fail_platform_io_register: ++ return err; ++} ++ ++static void nvsw_core_platform_exit(struct nvsw_core *nvsw_core) ++{ ++ int i; ++ ++ for (i = NVSW_WD_MAX - 1; i >= 0; i--) ++ platform_device_unregister(nvsw_core->wd[i]); ++ if (nvsw_core->hotplug_data) ++ platform_device_unregister(nvsw_core->hotplug); ++ if (nvsw_core->led_data) ++ platform_device_unregister(nvsw_core->led); ++ if (nvsw_core->fan_data) ++ platform_device_unregister(nvsw_core->fan); ++ if (nvsw_core->regio_data) ++ platform_device_unregister(nvsw_core->regio); ++} ++ ++static int nvsw_core_mux_topology_init(struct nvsw_core *nvsw_core) ++{ ++ return nvsw_core->mux_init(nvsw_core); ++} ++ ++static void nvsw_core_mux_topology_exit(struct nvsw_core *nvsw_core) ++{ ++ nvsw_core->mux_exit(nvsw_core); ++} ++ ++static int nvsw_core_regmap_init(struct nvsw_core *nvsw_core) ++{ ++ int err; ++ ++ switch (nvsw_core->regmap_type) { ++ case REGMAP_I2C: ++ nvsw_core->regmap = devm_regmap_init_i2c(nvsw_core->client, &nvsw_regmap_i2c_conf); ++ break; ++ case REGMAP_IO: ++ if (nvsw_core->port_map) { ++ nvsw_io_regmap_ctx.base = nvsw_core->port_map(nvsw_core); ++ if (!nvsw_io_regmap_ctx.base) ++ return -ENOMEM; ++ } ++ nvsw_core->regmap = devm_regmap_init(nvsw_core->dev, NULL, &nvsw_io_regmap_ctx, ++ &nvsw_regmap_conf_l1); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ if (IS_ERR(nvsw_core->regmap)) { ++ dev_err(nvsw_core->dev, "Failed to create regmap"); ++ return PTR_ERR(nvsw_core->regmap); ++ } ++ ++ /* Sync registers with hardware. */ ++ regcache_mark_dirty(nvsw_core->regmap); ++ err = regcache_sync(nvsw_core->regmap); ++ if (err) { ++ dev_err(nvsw_core->dev, "Failed to sync regmap"); ++ return err; ++ } ++ ++ /* Set registers default values. */ ++ if (nvsw_core->set_reg_default) { ++ err = nvsw_core->set_reg_default(nvsw_core->regmap); ++ if (err) { ++ dev_err(nvsw_core->dev, "Failed to set default regmap"); ++ return err; ++ } ++ } ++ ++ return 0; ++} ++ ++int nvsw_core_init(struct nvsw_core *nvsw_core) ++{ ++ int err; ++ ++ err = nvsw_core_regmap_init(nvsw_core); ++ if (err) ++ return err; ++ ++ err = nvsw_core_mux_topology_init(nvsw_core); ++ if (err) ++ goto nvsw_core_mux_topology_init_fail; ++ ++ err = nvsw_core_platform_init(nvsw_core); ++ if (err) ++ goto nvsw_core_platform_init_fail; ++ ++ return 0; ++nvsw_core_platform_init_fail: ++ nvsw_core_mux_topology_exit(nvsw_core); ++nvsw_core_mux_topology_init_fail: ++ return err; ++} ++EXPORT_SYMBOL(nvsw_core_init); ++ ++void nvsw_core_exit(struct nvsw_core *nvsw_core) ++{ ++ nvsw_core_platform_exit(nvsw_core); ++ nvsw_core_mux_topology_exit(nvsw_core); ++ if (nvsw_core->set_reg_default) ++ nvsw_core->set_reg_default(nvsw_core->regmap); ++} ++EXPORT_SYMBOL(nvsw_core_exit); ++ ++MODULE_AUTHOR("Vadim Pasternak "); ++MODULE_DESCRIPTION("Nvidia platform driver"); ++MODULE_LICENSE("Dual BSD/GPL"); +diff --git a/drivers/platform/mellanox/nvsw-host-l1.c b/drivers/platform/mellanox/nvsw-host-l1.c +new file mode 100644 +index 00000000..ffe248b +--- /dev/null ++++ b/drivers/platform/mellanox/nvsw-host-l1.c +@@ -0,0 +1,745 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Nvidia BMC platform driver ++ * ++ * Copyright (C) 2025 Nvidia Technologies Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "nvsw.h" ++ ++#define NVSW_HOST_DEVICE_NAME "mlxplat" ++ ++/* LPC bus IO offsets */ ++#define NVSW_I2C_BASE_ADRR 0x2000 ++#define NVSW_REG_BASE_ADRR 0x2500 ++#define NVSW_LPC_IO_RANGE 0x100 ++#define NVSW_LPC_PIO_OFFSET 0x10000UL ++#define NVSW_REG_MUX1 (NVSW_REG_MUX1_OFFSET | NVSW_LPC_PIO_OFFSET) ++#define NVSW_REG_MUX2 (NVSW_REG_MUX0_OFFSET | NVSW_LPC_PIO_OFFSET) ++ ++/* Start channel numbers */ ++#define NVSW_PARENT_CH_L1 0 ++#define NVSW_CH1_L1 5 ++ ++/* Regions for LPC I2C controller and LPC base register space */ ++static const struct resource nvsw_host_io_resources[] = { ++ [0] = DEFINE_RES_NAMED(NVSW_I2C_BASE_ADRR, NVSW_LPC_IO_RANGE, ++ "nvsw_cpld_lpc_i2c_ctrl", IORESOURCE_IO), ++ [1] = DEFINE_RES_NAMED(NVSW_REG_BASE_ADRR, NVSW_LPC_IO_RANGE, ++ "nvsw_cpld_lpc_regs", IORESOURCE_IO), ++}; ++ ++/* Platform channels for L1 scale out system family */ ++static const int nvsw_host_l1_mgmt_channels[] = { ++ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, ++ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, ++ 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 48, 49, ++ 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, ++ 65, 66, 67, 68, 69, 70, 71, ++}; ++ ++/* Platform L1 scale out mux data */ ++static struct i2c_mux_reg_platform_data nvsw_host_l1_mux_data[] = { ++ { ++ .parent = NVSW_PARENT_CH_L1, ++ .base_nr = NVSW_CH1_L1, ++ .write_only = 1, ++ .reg = (void __iomem *)NVSW_REG_MUX1, ++ .reg_size = 1, ++ .idle_in_use = 1, ++ .values = nvsw_host_l1_mgmt_channels, ++ .n_values = ARRAY_SIZE(nvsw_host_l1_mgmt_channels), ++ }, ++}; ++ ++static struct platform_device *nvsw_host_dev; ++static struct i2c_mux_reg_platform_data *nvsw_host_mux_data[NVSW_MUX_MAX]; ++static struct mlxreg_core_platform_data *nvsw_led_data; ++static struct mlxreg_core_platform_data *nvsw_regs_io_data; ++static struct mlxreg_core_platform_data *nvsw_wd_data[NVSW_WD_MAX]; ++static int mux_num; ++static enum nvsw_core_hid_type nvsw_host_hid; ++ ++/* Platform register access for l1 systems families data */ ++static struct mlxreg_core_data nvsw_host_l1_regs_io_data[] = { ++ { ++ .label = "cpld1_version", ++ .reg = NVSW_REG_CPLD1_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld2_version", ++ .reg = NVSW_REG_CPLD2_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld1_pn", ++ .reg = NVSW_REG_CPLD1_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld2_pn", ++ .reg = NVSW_REG_CPLD2_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld1_version_min", ++ .reg = NVSW_REG_CPLD1_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld2_version_min", ++ .reg = NVSW_REG_CPLD2_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_status", ++ .reg = NVSW_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(3, 1), ++ .bit = 3, ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_start_retry", ++ .reg = NVSW_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "bios_active_image", ++ .reg = NVSW_REG_GPCOM0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "pwr_converter_prog_en", ++ .reg = NVSW_REG_GP7_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_mctp_ready", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_shutdown_req", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "vpd_wp", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ .secured = 1, ++ }, ++ { ++ .label = "pcie_asic_reset_dis", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, ++ }, ++ { ++ .label = "shutdown_unlock", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_power_off_ready", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "pwr_cycle", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0244, ++ }, ++ { ++ .label = "pwr_down", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0200, ++ }, ++ { ++ .label = "aux_pwr_cycle", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0200, ++ }, ++ { ++ .label = "bmc_to_cpu_ctrl", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, ++ }, ++ { ++ .label = "uart_sel", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = NVSW_UART_SEL_MASK, ++ .bit = 7, ++ .mode = 0644, ++ }, ++ { ++ .label = "hotswap_alert", ++ .reg = NVSW_REG_BRD4_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cartridge1", ++ .reg = NVSW_REG_FRU1_OFFSET, ++ .mask = BIT(0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cartridge2", ++ .reg = NVSW_REG_FRU1_OFFSET, ++ .mask = BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "cartridge3", ++ .reg = NVSW_REG_FRU1_OFFSET, ++ .mask = BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "cartridge4", ++ .reg = NVSW_REG_FRU1_OFFSET, ++ .mask = BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "cartridge_status_clear", ++ .reg = NVSW_REG_FRU1_EVENT_OFFSET, ++ .bit = GENMASK(3, 0), ++ .mode = 0644, ++ }, ++ { ++ .label = "leakage1", ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0444, ++ }, ++ { ++ .label = "leakage2", ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "leakage_status_clear", ++ .reg = NVSW_REG_LEAK_EVENT_OFFSET, ++ .bit = GENMASK(1, 0), ++ .mode = 0644, ++ }, ++ { ++ .label = "asic_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ }, ++ { ++ .label = "sgmii_phy_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, ++ }, ++ { ++ .label = "reset_long_pb", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_short_pb", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_aux_pwr_or_fu", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_swb_dc_dc_pwr_fail", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_pwr_button_or_leak_con", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_swb_wd", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_asic_thermal", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_comex_pwr_fail", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_platform", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_soc", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_system", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_sw_pwr_off", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_comex_thermal", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_comex_power", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_pwr_converter_fail", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_main_51v", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_mgmt_pwr", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "port80", ++ .reg = NVSW_REG_GP1_RO_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "jtag_cap", ++ .reg = NVSW_REG_FU_CAP_OFFSET, ++ .mask = NVSW_FU_CAP_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "jtag_enable", ++ .reg = NVSW_REG_FIELD_UPGRADE, ++ .mask = GENMASK(1, 0), ++ .bit = 1, ++ .mode = 0644, ++ }, ++ { ++ .label = "asic_health", ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASIC_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "asic2_health", ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASIC2_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "asic3_health", ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASIC3_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "asic4_health", ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASIC4_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "asic_pg_fail", ++ .reg = NVSW_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "spi_chnl_select", ++ .reg = NVSW_REG_SPI_CHNL_SELECT, ++ .mask = GENMASK(7, 0), ++ .bit = 1, ++ .mode = 0644, ++ }, ++ { ++ .label = "config1", ++ .reg = NVSW_REG_CONFIG1_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "config2", ++ .reg = NVSW_REG_CONFIG2_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "config3", ++ .reg = NVSW_REG_CONFIG3_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "sgmii_phy", ++ .reg = NVSW_REG_BRD1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "graseful_pwr_off", ++ .reg = NVSW_REG_GP7_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ }, ++ { ++ .label = "power_button_evt", ++ .reg = NVSW_REG_PWRB_EVENT_OFFSET, ++ .mask = GENMASK(7, 0) & ~NVSW_PWR_BUTTON_MASK, ++ .mode = 0644, ++ }, ++ { ++ .label = "power_button_mask", ++ .reg = NVSW_REG_PWRB_MASK_OFFSET, ++ .mask = GENMASK(7, 0) & ~NVSW_PWR_BUTTON_MASK, ++ .mode = 0644, ++ }, ++ { ++ .label = "amb_sens", ++ .reg = NVSW_REG_PWRB_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data nvsw_host_l1_regs_io = { ++ .data = nvsw_host_l1_regs_io_data, ++ .counter = ARRAY_SIZE(nvsw_host_l1_regs_io_data), ++}; ++ ++/* Platform led data for L1 switch systems with liquid cooling (without FANs) */ ++static struct mlxreg_core_data nvsw_host_l1_liquid_coling_led_data[] = { ++ { ++ .label = "status:green", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK ++ }, ++ { ++ .label = "status:amber", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK ++ }, ++ { ++ .label = "power:green", ++ .mode = 0444, ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "power:amber", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "uid:blue", ++ .reg = NVSW_REG_LED5_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data nvsw_host_l1_liquid_coling_led = { ++ .data = nvsw_host_l1_liquid_coling_led_data, ++ .counter = ARRAY_SIZE(nvsw_host_l1_liquid_coling_led_data), ++}; ++ ++/* Watchdog type3 platform data */ ++static struct mlxreg_core_data nvsw_host_wd_main_regs_type3[] = { ++ { ++ .label = "action", ++ .reg = NVSW_REG_WD2_ACT_OFFSET, ++ .mask = NVSW_WD_RESET_ACT_MASK, ++ .bit = 0, ++ }, ++ { ++ .label = "timeout", ++ .reg = NVSW_REG_WD2_TMR_OFFSET, ++ .mask = NVSW_WD_TYPE2_TO_MASK, ++ .health_cntr = NVSW_WD3_DFLT_TIMEOUT, ++ }, ++ { ++ .label = "timeleft", ++ .reg = NVSW_REG_WD2_TMR_OFFSET, ++ .mask = NVSW_WD_TYPE2_TO_MASK, ++ }, ++ { ++ .label = "ping", ++ .reg = NVSW_REG_WD2_ACT_OFFSET, ++ .mask = NVSW_WD_RESET_ACT_MASK, ++ .bit = 0, ++ }, ++ { ++ .label = "reset", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .bit = 6, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_host_wd_aux_regs_type3[] = { ++ { ++ .label = "action", ++ .reg = NVSW_REG_WD3_ACT_OFFSET, ++ .mask = NVSW_WD_FAN_ACT_MASK, ++ .bit = 4, ++ }, ++ { ++ .label = "timeout", ++ .reg = NVSW_REG_WD3_TMR_OFFSET, ++ .mask = NVSW_WD_TYPE2_TO_MASK, ++ .health_cntr = NVSW_WD3_DFLT_TIMEOUT, ++ }, ++ { ++ .label = "timeleft", ++ .reg = NVSW_REG_WD3_TMR_OFFSET, ++ .mask = NVSW_WD_TYPE2_TO_MASK, ++ }, ++ { ++ .label = "ping", ++ .reg = NVSW_REG_WD3_ACT_OFFSET, ++ .mask = NVSW_WD_FAN_ACT_MASK, ++ .bit = 4, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data nvsw_host_wd_set_type3[] = { ++ { ++ .data = nvsw_host_wd_main_regs_type3, ++ .counter = ARRAY_SIZE(nvsw_host_wd_main_regs_type3), ++ .version = MLX_WDT_TYPE3, ++ .identity = "mlx-wdt-main", ++ }, ++ { ++ .data = nvsw_host_wd_aux_regs_type3, ++ .counter = ARRAY_SIZE(nvsw_host_wd_aux_regs_type3), ++ .version = MLX_WDT_TYPE3, ++ .identity = "mlx-wdt-aux", ++ }, ++}; ++ ++/* IO port mapping callback. */ ++static void __iomem *nvsw_host_l1_port_map(struct nvsw_core *nvsw_core) ++{ ++ return devm_ioport_map(nvsw_core->dev, nvsw_host_io_resources[1].start, 1); ++} ++ ++/* Mux init/exit callbacks. */ ++static int nvsw_host_l1_mux_topology_init(struct nvsw_core *nvsw_core) ++{ ++ int i, err; ++ ++ /* Create mux infrastructure. */ ++ for (i = 0; i < nvsw_core->mux_num; i++) { ++ nvsw_core->mux[i] = ++ platform_device_register_resndata(nvsw_core->dev, "i2c-mux-reg", i, NULL, ++ 0, nvsw_host_mux_data[i], ++ sizeof(*nvsw_host_mux_data[i])); ++ if (IS_ERR(nvsw_core->mux[i])) { ++ dev_err(nvsw_core->dev, "Failed to create mux infra\n"); ++ err = PTR_ERR(nvsw_core->mux[i]); ++ goto fail_platform_mux_register; ++ } ++ } ++ ++ return 0; ++fail_platform_mux_register: ++ while (--i >= 0) ++ platform_device_unregister(nvsw_core->mux[i]); ++ return err; ++} ++ ++static void nvsw_host_l1_mux_topology_exit(struct nvsw_core *nvsw_core) ++{ ++ int i; ++ ++ for (i = 0; i < nvsw_core->mux_num; i++) { ++ if (nvsw_core->mux[i]) ++ platform_device_unregister(nvsw_core->mux[i]); ++ } ++} ++ ++static int __init nvsw_host_register_platform_device(void) ++{ ++ nvsw_host_dev = platform_device_register_simple(NVSW_HOST_DEVICE_NAME, -1, ++ nvsw_host_io_resources, ++ ARRAY_SIZE(nvsw_host_io_resources)); ++ if (IS_ERR(nvsw_host_dev)) ++ return PTR_ERR(nvsw_host_dev); ++ return 1; ++} ++ ++static int __init nvsw_host_dmi_l1_switch_matched(const struct dmi_system_id *dmi) ++{ ++ int i; ++ ++ /* Set system configuration. */ ++ nvsw_host_hid = HID180; ++ mux_num = ARRAY_SIZE(nvsw_host_l1_mux_data); ++ for (i = 0; i < mux_num; i++) ++ nvsw_host_mux_data[i] = &nvsw_host_l1_mux_data[i]; ++ nvsw_led_data = &nvsw_host_l1_liquid_coling_led; ++ nvsw_regs_io_data = &nvsw_host_l1_regs_io; ++ for (i = 0; i < ARRAY_SIZE(nvsw_host_wd_set_type3); i++) ++ nvsw_wd_data[i] = &nvsw_host_wd_set_type3[i]; ++ ++ return nvsw_host_register_platform_device(); ++} ++ ++static const struct dmi_system_id nvsw_host_dmi_table[] __initconst = { ++ { ++ .callback = nvsw_host_dmi_l1_switch_matched, ++ .matches = { ++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0023"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI180"), ++ }, ++ }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(dmi, nvsw_host_dmi_table); ++ ++static int nvsw_host_probe(struct platform_device *pdev) ++{ ++ struct nvsw_core *nvsw_core; ++ int i; ++ ++ nvsw_core = devm_kzalloc(&nvsw_host_dev->dev, sizeof(*nvsw_core), GFP_KERNEL); ++ if (!nvsw_core) ++ return -ENOMEM; ++ ++ /* Set system configuration. */ ++ nvsw_core->dev = &nvsw_host_dev->dev; ++ nvsw_core->hid = nvsw_host_hid; ++ nvsw_core->regmap_type = REGMAP_IO; ++ nvsw_core->mux_num = mux_num; ++ for (i = 0; i < ARRAY_SIZE(nvsw_wd_data); i++) ++ nvsw_core->wd_data[i] = nvsw_wd_data[i]; ++ nvsw_core->regio_data = nvsw_regs_io_data; ++ nvsw_core->led_data = nvsw_led_data; ++ nvsw_core->port_map = nvsw_host_l1_port_map; ++ nvsw_core->mux_init = nvsw_host_l1_mux_topology_init; ++ nvsw_core->mux_exit = nvsw_host_l1_mux_topology_exit; ++ platform_set_drvdata(nvsw_host_dev, nvsw_core); ++ ++ return nvsw_core_init(nvsw_core); ++} ++ ++static void nvsw_host_remove(struct platform_device *pdev) ++{ ++ struct nvsw_core *nvsw_core = platform_get_drvdata(nvsw_host_dev); ++ ++ return nvsw_core_exit(nvsw_core); ++} ++ ++static struct platform_driver nvsw_host_driver = { ++ .driver = { ++ .name = NVSW_HOST_DEVICE_NAME, ++ .probe_type = PROBE_FORCE_SYNCHRONOUS, ++ }, ++ .probe = nvsw_host_probe, ++ .remove = nvsw_host_remove, ++}; ++ ++static int __init nvsw_host_init(void) ++{ ++ if (!dmi_check_system(nvsw_host_dmi_table)) ++ return -ENODEV; ++ ++ return platform_driver_register(&nvsw_host_driver); ++} ++module_init(nvsw_host_init); ++ ++static void __exit nvsw_host_exit(void) ++{ ++ if (nvsw_host_dev) ++ platform_device_unregister(nvsw_host_dev); ++ ++ platform_driver_unregister(&nvsw_host_driver); ++} ++module_exit(nvsw_host_exit); ++ ++MODULE_AUTHOR("Vadim Pasternak "); ++MODULE_DESCRIPTION("Nvidia platform driver"); ++MODULE_LICENSE("Dual BSD/GPL"); ++ +diff --git a/drivers/platform/mellanox/nvsw.h b/drivers/platform/mellanox/nvsw.h +new file mode 100644 +index 00000000..b1ae4db +--- /dev/null ++++ b/drivers/platform/mellanox/nvsw.h +@@ -0,0 +1,260 @@ ++/* SPDX-License-Identifier: GPL-2.0+ ++ * ++ * Nvidia BMC platform driver ++ * ++ * Copyright (C) 2025 Nvidia Technologies Ltd. ++ */ ++ ++#ifndef __NVSW_H__ ++#define __NVSW_H__ ++ ++/* I2C bus IO offsets */ ++#define NVSW_REG_CPLD1_VER_OFFSET 0x2500 ++#define NVSW_REG_CPLD2_VER_OFFSET 0x2501 ++#define NVSW_REG_CPLD3_VER_OFFSET 0x2502 ++#define NVSW_REG_CPLD4_VER_OFFSET 0x2503 ++#define NVSW_REG_CPLD1_PN_OFFSET 0x2504 ++#define NVSW_REG_CPLD1_PN1_OFFSET 0x2505 ++#define NVSW_REG_CPLD2_PN_OFFSET 0x2506 ++#define NVSW_REG_CPLD2_PN1_OFFSET 0x2507 ++#define NVSW_REG_CPLD3_PN_OFFSET 0x2508 ++#define NVSW_REG_CPLD3_PN1_OFFSET 0x2509 ++#define NVSW_REG_CPLD4_PN_OFFSET 0x250a ++#define NVSW_REG_CPLD4_PN1_OFFSET 0x250b ++#define NVSW_REG_PG1_OFFSET 0x2511 ++#define NVSW_REG_PG1_EVENT_OFFSET 0x2512 ++#define NVSW_REG_PG1_MASK_OFFSET 0x2513 ++#define NVSW_REG_PG2_OFFSET 0x2514 ++#define NVSW_REG_PG2_EVENT_OFFSET 0x2515 ++#define NVSW_REG_PG2_MASK_OFFSET 0x2516 ++#define NVSW_REG_RESET_GP1_OFFSET 0x2517 ++#define NVSW_REG_RESET_GP2_OFFSET 0x2519 ++#define NVSW_REG_RESET_CAUSE_OFFSET 0x251d ++#define NVSW_REG_RESET_CAUSE1_OFFSET 0x251e ++#define NVSW_REG_RESET_CAUSE2_OFFSET 0x251f ++#define NVSW_REG_LED1_OFFSET 0x2520 ++#define NVSW_REG_LED5_OFFSET 0x2524 ++#define NVSW_REG_LED6_OFFSET 0x2525 ++#define NVSW_REG_LED7_OFFSET 0x2526 ++#define NVSW_REG_GP0_RO_OFFSET 0x252a ++#define NVSW_REG_GP1_RO_OFFSET 0x252c ++#define NVSW_REG_GPCOM0_OFFSET 0x252d ++#define NVSW_REG_GP0_OFFSET 0x252e ++#define NVSW_REG_GP7_OFFSET 0x252f ++#define NVSW_REG_GP1_OFFSET 0x2530 ++#define NVSW_REG_GP4_OFFSET 0x2532 ++#define NVSW_REG_FIELD_UPGRADE 0x2534 ++#define NVSW_REG_SAFE_BIOS_OFFSET 0x2535 ++#define NVSW_REG_PWM_CONTROL_OFFSET 0x2537 ++#define NVSW_REG_GP5_OFFSET 0x2538 ++#define NVSW_REG_GP6_OFFSET 0x2539 ++#define NVSW_REG_AGGR_OFFSET 0x253a ++#define NVSW_REG_AGGR_MASK_OFFSET 0x253b ++#define NVSW_REG_FU_CAP_OFFSET 0x253c ++#define NVSW_REG_BRD4_OFFSET 0x253d ++#define NVSW_REG_BRD4_EVENT_OFFSET 0x253e ++#define NVSW_REG_BRD4_MASK_OFFSET 0x253f ++#define NVSW_REG_AGGRLO_OFFSET 0x2540 ++#define NVSW_REG_AGGRLO_MASK_OFFSET 0x2541 ++#define NVSW_REG_AGGRCO_OFFSET 0x2542 ++#define NVSW_REG_AGGRCO_MASK_OFFSET 0x2543 ++#define NVSW_REG_BRD1_OFFSET 0x2547 ++#define NVSW_REG_BRD1_EVENT_OFFSET 0x2548 ++#define NVSW_REG_BRD1_MASK_OFFSET 0x2549 ++#define NVSW_REG_HEALTH_OFFSET 0x254d ++#define NVSW_REG_HEALTH_EVENT_OFFSET 0x254e ++#define NVSW_REG_HEALTH_MASK_OFFSET 0x254f ++#define NVSW_REG_ASIC1_HEALTH_OFFSET 0x2550 ++#define NVSW_REG_ASIC1_EVENT_OFFSET 0x2551 ++#define NVSW_REG_ASIC1_MASK_OFFSET 0x2552 ++#define NVSW_REG_ASIC2_HEALTH_OFFSET 0x2553 ++#define NVSW_REG_ASIC2_EVENT_OFFSET 0x2554 ++#define NVSW_REG_ASIC2_MASK_OFFSET 0x2555 ++#define NVSW_REG_VR1_ALERT_OFFSET 0x2558 ++#define NVSW_REG_VR1_ALERT_EVENT_OFFSET 0x2559 ++#define NVSW_REG_VR1_ALERT_MASK_OFFSET 0x255a ++#define NVSW_REG_VR2_ALERT_OFFSET 0x255e ++#define NVSW_REG_VR2_ALERT_EVENT_OFFSET 0x255f ++#define NVSW_REG_VR2_ALERT_MASK_OFFSET 0x2560 ++#define NVSW_REG_PG3_OFFSET 0x2576 ++#define NVSW_REG_PG3_EVENT_OFFSET 0x2577 ++#define NVSW_REG_PG3_MASK_OFFSET 0x2578 ++#define NVSW_REG_PG4_OFFSET 0x2579 ++#define NVSW_REG_PG4_EVENT_OFFSET 0x257a ++#define NVSW_REG_PG4_MASK_OFFSET 0x257b ++#define NVSW_REG_ASIC3_HEALTH_OFFSET 0x2582 ++#define NVSW_REG_ASIC3_EVENT_OFFSET 0x2583 ++#define NVSW_REG_ASIC3_MASK_OFFSET 0x2584 ++#define NVSW_REG_FAN_OFFSET 0x2588 ++#define NVSW_REG_FAN_EVENT_OFFSET 0x2589 ++#define NVSW_REG_FAN_MASK_OFFSET 0x258a ++#define NVSW_REG_EROT_OFFSET 0x2591 ++#define NVSW_REG_EROT_EVENT_OFFSET 0x2592 ++#define NVSW_REG_EROT_MASK_OFFSET 0x2593 ++#define NVSW_REG_EROT_ERR_OFFSET 0x2594 ++#define NVSW_REG_EROT_ERR_EVENT_OFFSET 0x2595 ++#define NVSW_REG_EROT_ERR_MASK_OFFSET 0x2596 ++#define NVSW_REG_PWRB_OFFSET 0x2597 ++#define NVSW_REG_PWRB_EVENT_OFFSET 0x2598 ++#define NVSW_REG_PWRB_MASK_OFFSET 0x2599 ++#define NVSW_REG_FRU1_OFFSET 0x25ac ++#define NVSW_REG_FRU1_EVENT_OFFSET 0x25ad ++#define NVSW_REG_FRU1_MASK_OFFSET 0x25ae ++#define NVSW_REG_LEAK_OFFSET 0x25af ++#define NVSW_REG_LEAK_EVENT_OFFSET 0x25b0 ++#define NVSW_REG_LEAK_MASK_OFFSET 0x25b1 ++#define NVSW_REG_GP4_RO_OFFSET 0x25c2 ++#define NVSW_REG_SPI_CHNL_SELECT 0x25c3 ++#define NVSW_REG_WD2_TMR_OFFSET 0x25cd ++#define NVSW_REG_WD2_TLEFT_OFFSET 0x25ce ++#define NVSW_REG_WD2_ACT_OFFSET 0x25cf ++#define NVSW_REG_WD3_TMR_OFFSET 0x25d1 ++#define NVSW_REG_WD3_TLEFT_OFFSET 0x25d2 ++#define NVSW_REG_WD3_ACT_OFFSET 0x25d3 ++#define NVSW_REG_MUX0_OFFSET 0x25da ++#define NVSW_REG_MUX1_OFFSET 0x25db ++#define NVSW_REG_MUX2_OFFSET 0x25dc ++#define NVSW_REG_CPLD1_MVER_OFFSET 0x25de ++#define NVSW_REG_CPLD2_MVER_OFFSET 0x25df ++#define NVSW_REG_CPLD3_MVER_OFFSET 0x25e0 ++#define NVSW_REG_CPLD4_MVER_OFFSET 0x25e1 ++#define NVSW_REG_UFM_VERSION_OFFSET 0x25e2 ++#define NVSW_REG_PWM1_OFFSET 0x25e3 ++#define NVSW_REG_TACHO1_OFFSET 0x25e4 ++#define NVSW_REG_TACHO2_OFFSET 0x25e5 ++#define NVSW_REG_TACHO3_OFFSET 0x25e6 ++#define NVSW_REG_TACHO4_OFFSET 0x25e7 ++#define NVSW_REG_TACHO5_OFFSET 0x25e8 ++#define NVSW_REG_TACHO6_OFFSET 0x25e9 ++#define NVSW_REG_TACHO7_OFFSET 0x25eb ++#define NVSW_REG_TACHO8_OFFSET 0x25ec ++#define NVSW_REG_TACHO9_OFFSET 0x25ed ++#define NVSW_REG_TACHO10_OFFSET 0x25ee ++#define NVSW_REG_TACHO11_OFFSET 0x25ef ++#define NVSW_REG_TACHO12_OFFSET 0x25f0 ++#define NVSW_REG_FAN_CAP1_OFFSET 0x25f5 ++#define NVSW_REG_FAN_DRW_CAP_OFFSET 0x25f7 ++#define NVSW_REG_TACHO_SPEED_OFFSET 0x25f8 ++#define NVSW_REG_CONFIG1_OFFSET 0x25fb ++#define NVSW_REG_CONFIG2_OFFSET 0x25fc ++#define NVSW_REG_CONFIG3_OFFSET 0x25fd ++#define NVSW_REG_MIN 0x2500 ++#define NVSW_REG_MAX 0x26ff ++ ++#define NVSW_AGGR_MASK_COMEX BIT(0) ++#define NVSW_AGGR_MASK BIT(2) ++#define NVSW_LOW_AGGR_MASK_LOW 0xe0 ++#define NVSW_REG_FRU1_MASK GENMASK(3, 0) ++#define NVSW_LEAK_MASK GENMASK(5, 0) ++#define NVSW_SSD_I2C_ALERT_MASK BIT(0) ++#define NVSW_WD_EXP_MASK BIT(1) ++#define NVSW_5V_USB_MASK BIT(2) ++#define NVSW_PCB_TEMP1_MASK BIT(3) ++#define NVSW_PCB_TEMP2_MASK BIT(4) ++#define NVSW_SGMII_MASK BIT(5) ++#define NVSW_SDD_PG_MASK BIT(6) ++#define NVSW_LEAK_AGGR_MASK BIT(7) ++#define NVSW_EROT_MASK GENMASK(2, 0) ++#define NVSW_FAN_NG_MASK GENMASK(6, 0) ++#define NVSW_ASIC_MASK GENMASK(1, 0) ++#define NVSW_ASIC2_MASK GENMASK(3, 2) ++#define NVSW_ASIC3_MASK GENMASK(5, 4) ++#define NVSW_ASIC4_MASK GENMASK(7, 6) ++#define NVSW_ASICS_MASK GENMASK(7, 0) ++#define NVSW_LOW_AGGR_MASK_ASIC1 BIT(0) ++#define NVSW_LOW_AGGR_MASK_ASIC2 BIT(1) ++#define NVSW_LOW_AGGR_MASK_ASIC3 BIT(2) ++#define NVSW_PWR_BUTTON_MASK BIT(0) ++#define NVSW_AMB_TEMP_SENSE_MASK BIT(1) ++#define NVSW_GRACEFUL_POWER_OFF_MASK BIT(2) ++#define NVSW_CPU_POWER_OFF_READY_MASK BIT(3) ++#define NVSW_CPU_RESET_MASK BIT(4) ++#define NVSW_APML_SMB_ALERT_MASK BIT(5) ++#define NVSW_CPU_UNEXP_POWER_OFF_MASK BIT(6) ++#define NVSW_UID_PUSH_BUTTON_MASK BIT(7) ++#define NVSW_RTC_MASK BIT(0) ++#define NVSW_HOT_SWAP_ALERT_MASK BIT(1) ++#define NVSW_LED_LO_NIBBLE_MASK GENMASK(7, 4) ++#define NVSW_LED_HI_NIBBLE_MASK GENMASK(3, 0) ++#define NVSW_UART_SEL_MASK GENMASK(7, 6) ++#define NVSW_BIOS_STATUS_MASK GENMASK(3, 1) ++#define NVSW_REG_RESET_MASK BIT(1) ++#define NVSW_FU_CAP_MASK GENMASK(1, 0) ++#define NVSW_WD_RESET_ACT_MASK GENMASK(7, 1) ++#define NVSW_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4)) ++#define NVSW_WD_TYPE2_TO_MASK 0 ++#define NVSW_WD3_DFLT_TIMEOUT 600 ++ ++#define NVSW_NR_NONE -1 ++#define NVSW_MUX_MAX 2 ++#define NVSW_WD_MAX 2 ++ ++ /* The system type. */ ++enum nvsw_core_hid_type { ++ HID162, ++ HID176, ++ HID177, ++ HID180, ++}; ++ ++ /* The system register map type. */ ++enum nvsw_core_regmap_type { ++ REGMAP_IO, ++ REGMAP_I2C, ++}; ++ ++/* nvsw_core - device private data ++ * hid: hardware Id; ++ * regmap_type: register map type; ++ * @device: device; ++ * @client: I2C client device; ++ * @np: device node; ++ * @regmap: device register map; ++ * @regio_data: register access platform data; ++ * @regio: register access device; ++ * @hotplug_data: hotplug platform data; ++ * @hotplug: hotplug device; ++ * @led: led devices; ++ * @led_data: led platform data; ++ * @fan - fan device; ++ * @fan_data - fan platform data; ++ * @wd - watchdog device; ++ * @wd_data - watchdog platform data; ++ * @port_map - io port mapping; ++ * @set_reg_default - set default registers callback; ++ * @mux_init: mux initialization callback; ++ * @mux_exit: mux de-initialization callback; ++ * @mux: mux devices; ++ * @mux_num: number of mux device; ++ */ ++struct nvsw_core { ++ enum nvsw_core_hid_type hid; ++ enum nvsw_core_regmap_type regmap_type; ++ struct device *dev; ++ struct i2c_client *client; ++ struct device_node *np; ++ struct regmap *regmap; ++ struct mlxreg_core_platform_data *regio_data; ++ struct platform_device *regio; ++ struct mlxreg_core_hotplug_platform_data *hotplug_data; ++ struct platform_device *hotplug; ++ struct platform_device *led; ++ struct mlxreg_core_platform_data *led_data; ++ struct platform_device *fan; ++ struct mlxreg_core_platform_data *fan_data; ++ struct platform_device *wd[NVSW_WD_MAX]; ++ struct mlxreg_core_platform_data *wd_data[NVSW_WD_MAX]; ++ void __iomem *(*port_map)(struct nvsw_core *nvsw_core); ++ int (*set_reg_default)(struct regmap *regmap); ++ int (*mux_init)(struct nvsw_core *nvsw_core); ++ void (*mux_exit)(struct nvsw_core *nvsw_core); ++ struct platform_device *mux[NVSW_MUX_MAX]; ++ u32 mux_num; ++}; ++ ++/* Platform core init/exit functions. */ ++int nvsw_core_init(struct nvsw_core *nvsw_core); ++void nvsw_core_exit(struct nvsw_core *nvsw_core); ++ ++#endif /* !defined(__NVSW_H__) */ ++ +-- +2.8.4 + diff --git a/patches-sonic/0047-hwmon-mlxreg-fan-Prevent-fans-from-getting-stuck-at-.patch b/patches-sonic/0047-hwmon-mlxreg-fan-Prevent-fans-from-getting-stuck-at-.patch new file mode 100644 index 000000000..d6776c203 --- /dev/null +++ b/patches-sonic/0047-hwmon-mlxreg-fan-Prevent-fans-from-getting-stuck-at-.patch @@ -0,0 +1,64 @@ +From cb4bbd807ddd09b237809ac19e120ee3235f27e6 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Wed, 30 Jul 2025 20:41:33 +0300 +Subject: [PATCH 47/78] hwmon: mlxreg-fan: Prevent fans from getting stuck at 0 + RPM + +The fans controlled by the driver can get stuck at 0 RPM if they are +configured below a 20% duty cycle. The driver tries to avoid this by +enforcing a minimum duty cycle of 20%, but this is done after the fans +are registered with the thermal subsystem. This is too late as the +thermal subsystem can set their current state before the driver is able +to enforce the minimum duty cycle. + +Fix by setting the minimum duty cycle before registering the fans with +the thermal subsystem. + +Fixes: d7efb2ebc7b3 ("hwmon: (mlxreg-fan) Extend driver to support multiply cooling devices") +Reported-by: Nikolay Aleksandrov +Tested-by: Nikolay Aleksandrov +Signed-off-by: Ido Schimmel +Signed-off-by: Vadim Pasternak +--- + drivers/hwmon/mlxreg-fan.c | 5 ++--- + drivers/platform/mellanox/nvsw-bmc-hid162.c | 2 +- + 2 files changed, 3 insertions(+), 4 deletions(-) + +diff --git a/drivers/hwmon/mlxreg-fan.c b/drivers/hwmon/mlxreg-fan.c +index 0e9ce70..2cd0b9c 100644 +--- a/drivers/hwmon/mlxreg-fan.c ++++ b/drivers/hwmon/mlxreg-fan.c +@@ -581,15 +581,14 @@ static int mlxreg_fan_cooling_config(struct device *dev, struct mlxreg_fan *fan) + if (!pwm->connected) + continue; + pwm->fan = fan; ++ /* Set minimal PWM speed. */ ++ pwm->last_hwmon_state = MLXREG_FAN_PWM_DUTY2STATE(MLXREG_FAN_MIN_DUTY); + pwm->cdev = devm_thermal_of_cooling_device_register(dev, NULL, mlxreg_fan_name[i], + pwm, &mlxreg_fan_cooling_ops); + if (IS_ERR(pwm->cdev)) { + dev_err(dev, "Failed to register cooling device\n"); + return PTR_ERR(pwm->cdev); + } +- +- /* Set minimal PWM speed. */ +- pwm->last_hwmon_state = MLXREG_FAN_PWM_DUTY2STATE(MLXREG_FAN_MIN_DUTY); + } + + return 0; +diff --git a/drivers/platform/mellanox/nvsw-bmc-hid162.c b/drivers/platform/mellanox/nvsw-bmc-hid162.c +index fbc7382..6ebe5be 100644 +--- a/drivers/platform/mellanox/nvsw-bmc-hid162.c ++++ b/drivers/platform/mellanox/nvsw-bmc-hid162.c +@@ -2012,7 +2012,7 @@ static struct mlxreg_core_data nvsw_bmc_hid180_regio_data[] = { + { + .label = "mcu2_reset", + .reg = NVSW_REG_RESET_GP2_OFFSET, +- .mask = GENMASK(7, 0) & ~BIT(6), ++ .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0644, + }, + { +-- +2.8.4 + diff --git a/patch/0054-platform-mellanox-Introduce-support-for-switches-equ.patch b/patches-sonic/0052-platform-mellanox-Introduce-support-for-switches-equ.patch similarity index 86% rename from patch/0054-platform-mellanox-Introduce-support-for-switches-equ.patch rename to patches-sonic/0052-platform-mellanox-Introduce-support-for-switches-equ.patch index f1c90d620..91ff31d94 100644 --- a/patch/0054-platform-mellanox-Introduce-support-for-switches-equ.patch +++ b/patches-sonic/0052-platform-mellanox-Introduce-support-for-switches-equ.patch @@ -1,8 +1,8 @@ -From 3e4ff8f2195a3dc7b04bb5a1b9fd6b655f78a75e Mon Sep 17 00:00:00 2001 +From 8434a03c6ba631dcfa6e1bbe5d4d42cdeb84caaf Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Mon, 24 Jul 2023 11:10:50 +0000 -Subject: [PATH backport v6.1 54/54] platform: mellanox: Introduce support for - switches equipped with new FPGA device +Subject: [PATCH 52/78] platform: mellanox: Introduce support for switches + equipped with new FPGA device Add support for Nvidia MQM97xx and MSN47xx family switches equipped with new FPGA device. @@ -20,24 +20,25 @@ cannot be connected directly to PCIe root complex). Signed-off-by: Vadim Pasternak Reviewed-by: Michael Shych --- - drivers/platform/x86/mlx-platform.c | 196 ++++++++++++++++++++++++++++ - 1 file changed, 196 insertions(+) + drivers/platform/mellanox/mlx-platform.c | 197 ++++++++++++++++++++++++++++++- + 1 file changed, 196 insertions(+), 1 deletion(-) -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 9021597b5446..46958810e972 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -183,6 +183,9 @@ - #define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb - #define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc +diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c +index 4242b13..c7c3aaa 100644 +--- a/drivers/platform/mellanox/mlx-platform.c ++++ b/drivers/platform/mellanox/mlx-platform.c +@@ -200,7 +200,9 @@ #define MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET 0xfd + #define MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET 0xfe + #define MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET 0xff +- +#define MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET 0x100 +#define MLXPLAT_CPLD_LPC_REG_EXT_MID_OFFSET 0x195 +#define MLXPLAT_CPLD_LPC_REG_EXT_MAX_OFFSET 0x1ff #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100 #define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL -@@ -277,6 +280,7 @@ +@@ -310,6 +312,7 @@ /* Maximum number of possible physical buses equipped on system */ #define MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM 16 #define MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM 24 @@ -45,7 +46,7 @@ index 9021597b5446..46958810e972 100644 /* Number of channels in group */ #define MLXPLAT_CPLD_GRP_CHNL_NUM 8 -@@ -338,6 +342,21 @@ +@@ -375,6 +378,21 @@ #define PCI_DEVICE_ID_LATTICE_I2C_BRIDGE 0x9c2f #define PCI_DEVICE_ID_LATTICE_JTAG_BRIDGE 0x9c30 #define PCI_DEVICE_ID_LATTICE_LPC_BRIDGE 0x9c32 @@ -67,7 +68,7 @@ index 9021597b5446..46958810e972 100644 /* mlxplat_priv - platform private data * @pdev_i2c - i2c controller platform device -@@ -453,6 +472,28 @@ static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = { +@@ -492,6 +510,28 @@ static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = { }; @@ -96,20 +97,20 @@ index 9021597b5446..46958810e972 100644 /* Platform mux configuration variables */ static int mlxplat_max_adap_num; static int mlxplat_mux_num; -@@ -3540,6 +3581,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mask = GENMASK(7, 0) & ~BIT(2), +@@ -4266,6 +4306,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { .mode = 0200, }, -+ { + { + .label = "kexec_activated", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0644, + }, - { ++ { .label = "erot1_reset", .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, -@@ -5065,6 +5112,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) + .mask = GENMASK(7, 0) & ~BIT(6), +@@ -6456,6 +6502,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: @@ -117,7 +118,7 @@ index 9021597b5446..46958810e972 100644 return true; } return false; -@@ -5230,6 +5278,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) +@@ -6639,6 +6686,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET: case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: @@ -125,7 +126,7 @@ index 9021597b5446..46958810e972 100644 return true; } return false; -@@ -5387,6 +5436,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) +@@ -6811,6 +6859,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET: case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: @@ -133,7 +134,7 @@ index 9021597b5446..46958810e972 100644 return true; } return false; -@@ -5417,6 +5467,14 @@ static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = { +@@ -6841,6 +6890,14 @@ static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = { { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, }; @@ -148,7 +149,7 @@ index 9021597b5446..46958810e972 100644 static const struct reg_default mlxplat_mlxcpld_regmap_rack_switch[] = { { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, MLXPLAT_REGMAP_NVSWITCH_PWM_DEFAULT }, { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, -@@ -5545,6 +5603,114 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config_eth_modular = { +@@ -6990,6 +7047,114 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config_smart_switch = { .reg_write = mlxplat_mlxcpld_reg_write, }; @@ -263,7 +264,7 @@ index 9021597b5446..46958810e972 100644 static struct resource mlxplat_mlxcpld_resources[] = { [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug"), }; -@@ -5927,6 +6093,30 @@ static int __init mlxplat_dmi_l1_switch_matched(const struct dmi_system_id *dmi) +@@ -7398,6 +7563,30 @@ static int __init mlxplat_dmi_smart_switch_matched(const struct dmi_system_id *d return mlxplat_register_platform_device(); } @@ -291,22 +292,22 @@ index 9021597b5446..46958810e972 100644 + return 1; +} + - static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { - { - .callback = mlxplat_dmi_default_wc_matched, -@@ -6015,6 +6205,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { - DMI_MATCH(DMI_BOARD_NAME, "VMOD0015"), + static int __init mlxplat_dmi_ng400_hi171_matched(const struct dmi_system_id *dmi) + { + unsigned int i; +@@ -7510,6 +7699,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { }, }, -+ { + { + .callback = mlxplat_dmi_bf3_comex_default_matched, + .matches = { + DMI_MATCH(DMI_BOARD_NAME, "VMOD0016"), + }, + }, - { ++ { .callback = mlxplat_dmi_l1_switch_matched, .matches = { + DMI_MATCH(DMI_BOARD_NAME, "VMOD0017"), -- -2.20.1 +2.8.4 diff --git a/patches-sonic/0053-platform-mellanox-mlx-platform-Add-support-for-new-X.patch b/patches-sonic/0053-platform-mellanox-mlx-platform-Add-support-for-new-X.patch new file mode 100644 index 000000000..e42d1b202 --- /dev/null +++ b/patches-sonic/0053-platform-mellanox-mlx-platform-Add-support-for-new-X.patch @@ -0,0 +1,898 @@ +From 09599160f84a34b5158368ccea34c036c66f480d Mon Sep 17 00:00:00 2001 +From: Oleksandr Shamray +Date: Mon, 4 Aug 2025 19:38:39 +0300 +Subject: [PATCH 53/78] platform: mellanox: mlx-platform: Add support for new + XDR systems + +Add support for QM3400 and QM3000, Nvidia XDR switches. + +QM3400 is a 57.6Tbps switch based on Nvidia Quantum-3 ASIC. +It provides up-to 800Gbps full bidirectional bandwidth per port. +The system supports 36 OSFP cages and fits into standard 2U racks. + +QM3400 Features: + - 36 OSFP ports supporting 2.5Gbps - 800Gbps speeds. + - Air-cooled with 4 + 1 redundant fan units. + - 2 + 2 redundant 2000W PSUs. + - System management board based on Intel Coffee Lake CPU + with secure-boot support. + +QM3000 is a 115.2Tbps switch based on Nvidia Quantum-3 ASIC. +It provides up-to 800Gbps full bidirectional bandwidth per port. +The system supports 72 OSFP cages and fits into standard 4U racks. + +QM3000 Features: + - 72 OSFP ports or 144 aggregated XDR ports supporting 800Gbps speeds. + - Air-cooled with 9 + 1 redundant fan units. + - 4 + 4 redundant 2000W PSUs. + - System management board based on Intel Coffee Lake CPU + with secure-boot support. + +Signed-off-by: Felix Radensky +Reviewed-by: Vadim Pasternak +--- + drivers/platform/mellanox/mlx-platform.c | 421 +++++++++++++++++++++++++++++-- + 1 file changed, 406 insertions(+), 15 deletions(-) + +diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c +index c7c3aaa..de3dbaf 100644 +--- a/drivers/platform/mellanox/mlx-platform.c ++++ b/drivers/platform/mellanox/mlx-platform.c +@@ -102,12 +102,24 @@ + #define MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET 0x70 + #define MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET 0x71 + #define MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET 0x72 ++#define MLXPLAT_CPLD_LPC_REG_CPLD6_VER_OFFSET 0x7c ++#define MLXPLAT_CPLD_LPC_REG_CPLD6_PN_OFFSET 0x7d ++#define MLXPLAT_CPLD_LPC_REG_CPLD6_PN1_OFFSET 0x7e ++#define MLXPLAT_CPLD_LPC_REG_ASIC3_HEALTH_OFFSET 0x82 ++#define MLXPLAT_CPLD_LPC_REG_ASIC3_EVENT_OFFSET 0x83 ++#define MLXPLAT_CPLD_LPC_REG_ASIC3_MASK_OFFSET 0x84 ++#define MLXPLAT_CPLD_LPC_REG_ASIC4_HEALTH_OFFSET 0x85 ++#define MLXPLAT_CPLD_LPC_REG_ASIC4_EVENT_OFFSET 0x86 ++#define MLXPLAT_CPLD_LPC_REG_ASIC4_MASK_OFFSET 0x87 + #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88 + #define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89 + #define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a + #define MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET 0x8b + #define MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET 0x8c + #define MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET 0x8d ++#define MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET 0x8b ++#define MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET 0x8c ++#define MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET 0x8d + #define MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET 0x8e + #define MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET 0x8f + #define MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET 0x90 +@@ -258,6 +270,8 @@ + #define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2 BIT(2) + #define MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT GENMASK(5, 4) + #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6) ++#define MLXPLAT_CPLD_LOW_AGGR_MASK_MULTI_ASICS GENMASK(3, 0) ++#define MLXPLAT_CPLD_LOW_AGGR_MASK_FRU BIT(7) + #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0) + #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0) + #define MLXPLAT_CPLD_PSU_EXT_MASK GENMASK(3, 0) +@@ -268,13 +282,18 @@ + #define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0) + #define MLXPLAT_CPLD_ASIC_XDR_MASK GENMASK(3, 0) + #define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(6, 0) ++#define MLXPLAT_CPLD_FAN_QMB8700_MASK GENMASK(5, 0) + #define MLXPLAT_CPLD_FAN_XDR_MASK GENMASK(7, 0) ++#define MLXPLAT_CPLD_FAN_XDR_EXT_MASK GENMASK(1, 0) + #define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4) + #define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0) + #define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4) + #define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0) + #define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0) + #define MLXPLAT_CPLD_FU_CAP_MASK GENMASK(1, 0) ++#define MLXPLAT_CPLD_PSU_CAP_MASK GENMASK(3, 0) ++#define MLXPLAT_CPLD_FAN_CAP_MASK GENMASK(7, 0) ++#define MLXPLAT_CPLD_ASIC_CAP_MASK GENMASK(7, 0) + #define MLXPLAT_CPLD_BIOS_STATUS_MASK GENMASK(3, 1) + #define MLXPLAT_CPLD_DPU_MASK GENMASK(3, 0) + #define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0) +@@ -326,6 +345,7 @@ + #define MLXPLAT_CPLD_CH4_ETH_MODULAR 51 + #define MLXPLAT_CPLD_CH2_RACK_SWITCH 18 + #define MLXPLAT_CPLD_CH2_NG800 34 ++#define MLXPLAT_CPLD_CH2_XDR 66 + + /* Number of LPC attached MUX platform devices */ + #define MLXPLAT_CPLD_LPC_MUX_DEVS 4 +@@ -682,6 +702,38 @@ static struct i2c_mux_reg_platform_data mlxplat_ng800_mux_data[] = { + + }; + ++/* Platform channels for XDR system family */ ++static const int mlxplat_xdr_channels[] = { ++ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, ++ 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, ++ 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, ++ 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64 ++}; ++ ++/* Platform XDR mux data */ ++static struct i2c_mux_reg_platform_data mlxplat_xdr_mux_data[] = { ++ { ++ .parent = 1, ++ .base_nr = MLXPLAT_CPLD_CH1, ++ .write_only = 1, ++ .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, ++ .reg_size = 1, ++ .idle_in_use = 1, ++ .values = mlxplat_xdr_channels, ++ .n_values = ARRAY_SIZE(mlxplat_xdr_channels), ++ }, ++ { ++ .parent = 1, ++ .base_nr = MLXPLAT_CPLD_CH2_XDR, ++ .write_only = 1, ++ .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, ++ .reg_size = 1, ++ .idle_in_use = 1, ++ .values = mlxplat_msn21xx_channels, ++ .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), ++ }, ++}; ++ + /* Platform hotplug devices */ + static struct i2c_board_info mlxplat_mlxcpld_pwr[] = { + { +@@ -2471,7 +2523,7 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_rack_switch_data = { + .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, + }; + +-/* Platform hotplug XDR and smart switch system family data */ ++/* Platform hotplug XDR system family data */ + static struct mlxreg_core_data mlxplat_mlxcpld_xdr_psu_items_data[] = { + { + .label = "psu1", +@@ -2479,6 +2531,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_psu_items_data[] = { + .mask = BIT(0), + .slot = 1, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +@@ -2487,6 +2540,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_psu_items_data[] = { + .mask = BIT(1), + .slot = 2, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +@@ -2495,6 +2549,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_psu_items_data[] = { + .mask = BIT(2), + .slot = 3, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +@@ -2503,6 +2558,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_psu_items_data[] = { + .mask = BIT(3), + .slot = 4, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +@@ -2511,6 +2567,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_psu_items_data[] = { + .mask = BIT(4), + .slot = 5, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +@@ -2519,6 +2576,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_psu_items_data[] = { + .mask = BIT(5), + .slot = 6, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +@@ -2527,6 +2585,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_psu_items_data[] = { + .mask = BIT(6), + .slot = 7, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + { +@@ -2535,6 +2594,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_psu_items_data[] = { + .mask = BIT(7), + .slot = 8, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + }; +@@ -2546,6 +2606,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_pwr_items_data[] = { + .mask = BIT(0), + .slot = 1, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], + .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, + }, +@@ -2555,6 +2616,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_pwr_items_data[] = { + .mask = BIT(1), + .slot = 2, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], + .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, + }, +@@ -2564,6 +2626,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_pwr_items_data[] = { + .mask = BIT(2), + .slot = 3, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], + .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, + }, +@@ -2573,6 +2636,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_pwr_items_data[] = { + .mask = BIT(3), + .slot = 4, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], + .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, + }, +@@ -2582,6 +2646,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_pwr_items_data[] = { + .mask = BIT(4), + .slot = 5, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[0], + .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, + }, +@@ -2591,6 +2656,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_pwr_items_data[] = { + .mask = BIT(5), + .slot = 6, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[1], + .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, + }, +@@ -2600,6 +2666,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_pwr_items_data[] = { + .mask = BIT(6), + .slot = 7, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[2], + .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, + }, +@@ -2609,11 +2676,23 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_pwr_items_data[] = { + .mask = BIT(7), + .slot = 8, + .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, + .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[3], + .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, + }, + }; + ++static int mlxplat_mlxcpld_xdr_pwr_nr_fixup[] = { ++ MLXPLAT_CPLD_PSU_MSNXXXX_NR, ++ MLXPLAT_CPLD_PSU_MSNXXXX_NR, ++ MLXPLAT_CPLD_PSU_XDR_NR, ++ MLXPLAT_CPLD_PSU_XDR_NR, ++ MLXPLAT_CPLD_PSU_MSNXXXX_NR, ++ MLXPLAT_CPLD_PSU_MSNXXXX_NR, ++ MLXPLAT_CPLD_PSU_XDR_NR, ++ MLXPLAT_CPLD_PSU_XDR_NR, ++}; ++ + static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_items_data[] = { + { + .label = "fan1", +@@ -2621,6 +2700,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_items_data[] = { + .mask = BIT(0), + .slot = 1, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, + .bit = BIT(0), + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, +@@ -2630,6 +2710,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_items_data[] = { + .mask = BIT(1), + .slot = 2, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, + .bit = BIT(1), + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, +@@ -2639,6 +2720,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_items_data[] = { + .mask = BIT(2), + .slot = 3, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, + .bit = BIT(2), + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, +@@ -2648,6 +2730,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_items_data[] = { + .mask = BIT(3), + .slot = 4, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, + .bit = BIT(3), + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, +@@ -2657,6 +2740,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_items_data[] = { + .mask = BIT(4), + .slot = 5, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, + .bit = BIT(4), + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, +@@ -2666,6 +2750,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_items_data[] = { + .mask = BIT(5), + .slot = 6, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, + .bit = BIT(5), + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, +@@ -2675,6 +2760,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_items_data[] = { + .mask = BIT(6), + .slot = 7, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, + .bit = BIT(6), + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, +@@ -2684,11 +2770,55 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_items_data[] = { + .mask = BIT(7), + .slot = 8, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, + .bit = BIT(7), + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + }, + }; + ++static struct mlxreg_core_data mlxplat_mlxcpld_xdr_ext_fan_items_data[] = { ++ { ++ .label = "fan9", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, ++ .mask = BIT(0), ++ .slot = 9, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, ++ .bit = BIT(0), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "fan10", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, ++ .mask = BIT(1), ++ .slot = 10, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, ++ .bit = BIT(1), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "fan11", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, ++ .mask = BIT(2), ++ .slot = 11, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, ++ .bit = BIT(2), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "fan12", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, ++ .mask = BIT(3), ++ .slot = 12, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, ++ .bit = BIT(3), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++}; ++ + static struct mlxreg_core_data mlxplat_mlxcpld_xdr_asic1_items_data[] = { + { + .label = "asic1", +@@ -2696,10 +2826,148 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_asic1_items_data[] = { + .mask = MLXPLAT_CPLD_ASIC_MASK, + .slot = 1, + .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, + .hpdev.nr = MLXPLAT_CPLD_NR_NONE, + } + }; + ++static struct mlxreg_core_data mlxplat_mlxcpld_xdr_asic2_items_data[] = { ++ { ++ .label = "asic2", ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_MASK, ++ .slot = 2, ++ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ } ++}; ++ ++static struct mlxreg_core_data mlxplat_mlxcpld_xdr_asic3_items_data[] = { ++ { ++ .label = "asic3", ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC3_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_MASK, ++ .slot = 3, ++ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ } ++}; ++ ++static struct mlxreg_core_data mlxplat_mlxcpld_xdr_asic4_items_data[] = { ++ { ++ .label = "asic4", ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC4_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, ++ .slot = 4, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ } ++}; ++ ++static struct mlxreg_core_item mlxplat_mlxcpld_xdr_items[] = { ++ { ++ .data = mlxplat_mlxcpld_xdr_psu_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, ++ .mask = MLXPLAT_CPLD_PSU_XDR_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_psu_items_data), ++ .inversed = 1, ++ .health = false, ++ }, ++ { ++ .data = mlxplat_mlxcpld_xdr_pwr_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, ++ .mask = MLXPLAT_CPLD_PWR_XDR_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_pwr_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++ { ++ .data = mlxplat_mlxcpld_xdr_fan_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ .mask = MLXPLAT_CPLD_FAN_XDR_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_CAP_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_items_data), ++ .inversed = 1, ++ .health = false, ++ }, ++ { ++ .data = mlxplat_mlxcpld_xdr_ext_fan_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, ++ .mask = MLXPLAT_CPLD_FAN_XDR_EXT_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_CAP_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_ext_fan_items_data), ++ .inversed = 1, ++ .health = false, ++ }, ++ { ++ .data = mlxplat_mlxcpld_xdr_asic1_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_XDR_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_asic1_items_data), ++ .inversed = 0, ++ .health = true, ++ }, ++ { ++ .data = mlxplat_mlxcpld_xdr_asic2_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_XDR_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_asic2_items_data), ++ .inversed = 0, ++ .health = true, ++ }, ++ { ++ .data = mlxplat_mlxcpld_xdr_asic3_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC3_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_XDR_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_asic3_items_data), ++ .inversed = 0, ++ .health = true, ++ }, ++ { ++ .data = mlxplat_mlxcpld_xdr_asic4_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC4_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_XDR_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_asic4_items_data), ++ .inversed = 0, ++ .health = true, ++ }, ++}; ++ ++static ++struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_xdr_data = { ++ .items = mlxplat_mlxcpld_xdr_items, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_items), ++ .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, ++ .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, ++ .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, ++ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_FRU | MLXPLAT_CPLD_LOW_AGGR_MASK_MULTI_ASICS, ++}; ++ + /* Platform hotplug for smart switch systems families data */ + static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_dpu_ready_data[] = { + { +@@ -3758,7 +4026,7 @@ static struct mlxreg_core_platform_data mlxplat_l1_switch_led_data = { + .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_led_data), + }; + +-/* Platform led data for XDR and smart switch systems */ ++/* Platform led data for XDR systems */ + static struct mlxreg_core_data mlxplat_mlxcpld_xdr_led_data[] = { + { + .label = "status:green", +@@ -3766,9 +4034,9 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_led_data[] = { + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + }, + { +- .label = "status:orange", ++ .label = "status:amber", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, +- .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK + }, + { + .label = "psu:green", +@@ -3776,7 +4044,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_led_data[] = { + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, + { +- .label = "psu:orange", ++ .label = "psu:amber", + .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + }, +@@ -3788,7 +4056,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_led_data[] = { + .slot = 1, + }, + { +- .label = "fan1:orange", ++ .label = "fan1:amber", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +@@ -3802,7 +4070,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_led_data[] = { + .slot = 2, + }, + { +- .label = "fan2:orange", ++ .label = "fan2:amber", + .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +@@ -3816,7 +4084,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_led_data[] = { + .slot = 3, + }, + { +- .label = "fan3:orange", ++ .label = "fan3:amber", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +@@ -3830,7 +4098,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_led_data[] = { + .slot = 4, + }, + { +- .label = "fan4:orange", ++ .label = "fan4:amber", + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +@@ -3844,7 +4112,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_led_data[] = { + .slot = 5, + }, + { +- .label = "fan5:orange", ++ .label = "fan5:amber", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +@@ -3858,7 +4126,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_led_data[] = { + .slot = 6, + }, + { +- .label = "fan6:orange", ++ .label = "fan6:amber", + .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +@@ -3872,7 +4140,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_led_data[] = { + .slot = 7, + }, + { +- .label = "fan7:orange", ++ .label = "fan7:amber", + .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +@@ -3886,7 +4154,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_led_data[] = { + .slot = 8, + }, + { +- .label = "fan8:orange", ++ .label = "fan8:amber", + .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +@@ -3900,7 +4168,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_led_data[] = { + .slot = 9, + }, + { +- .label = "fan9:orange", ++ .label = "fan9:amber", + .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +@@ -3914,7 +4182,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_led_data[] = { + .slot = 10, + }, + { +- .label = "fan10:orange", ++ .label = "fan10:amber", + .reg = MLXPLAT_CPLD_LPC_REG_LED8_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +@@ -4229,6 +4497,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .mode = 0444, + }, + { ++ .label = "cpld6_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD6_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { + .label = "cpld1_pn", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, + .bit = GENMASK(15, 0), +@@ -4264,6 +4538,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .regnum = 2, + }, + { ++ .label = "cpld6_pn", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD6_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { + .label = "cpld1_version_min", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, + .bit = GENMASK(7, 0), +@@ -4294,6 +4575,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .mode = 0444, + }, + { ++ .label = "cpld6_version_min", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD6_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { + .label = "asic_reset", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), +@@ -4483,6 +4770,43 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .mode = 0200, + }, + { ++ .label = "psu3_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0200, ++ }, ++ { ++ .label = "psu4_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0200, ++ }, ++ { ++ .label = "psu5_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0200, ++ }, ++ ++ { ++ .label = "psu6_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0200, ++ }, ++ { ++ .label = "psu7_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0200, ++ }, ++ { ++ .label = "psu8_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0200, ++ }, ++ { + .label = "pwr_cycle", + .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), +@@ -4558,6 +4882,20 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .mode = 0444, + }, + { ++ .label = "asic3_health", ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC3_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "asic4_health", ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC4_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { + .label = "fan_dir", + .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, + .bit = GENMASK(7, 0), +@@ -6449,6 +6787,10 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC3_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC3_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC4_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC4_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET: +@@ -6516,6 +6858,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_CPLD6_VER_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: +@@ -6526,6 +6869,8 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_CPLD6_PN_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_CPLD6_PN1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET: +@@ -6581,6 +6926,10 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC3_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC3_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC4_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC4_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: +@@ -6700,6 +7049,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_CPLD6_VER_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: +@@ -6710,6 +7060,8 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_CPLD6_PN_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_CPLD6_PN1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET: +@@ -6763,6 +7115,10 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC3_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC3_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC4_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC4_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: +@@ -7610,6 +7966,35 @@ static int __init mlxplat_dmi_ng400_hi171_matched(const struct dmi_system_id *dm + return mlxplat_register_platform_device(); + } + ++static int __init mlxplat_dmi_xdr_matched(const struct dmi_system_id *dmi) ++{ ++ int i; ++ const char *sku; ++ ++ sku = dmi_get_system_info(DMI_PRODUCT_SKU); ++ if (!strcmp(sku, "HI158")) { ++ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_xdr_pwr_items_data); i++) ++ mlxplat_mlxcpld_xdr_pwr_items_data[i].hpdev.nr = ++ mlxplat_mlxcpld_xdr_pwr_nr_fixup[i]; ++ } ++ ++ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; ++ mlxplat_mux_num = ARRAY_SIZE(mlxplat_xdr_mux_data); ++ mlxplat_mux_data = mlxplat_xdr_mux_data; ++ mlxplat_hotplug = &mlxplat_mlxcpld_xdr_data; ++ mlxplat_hotplug->deferred_nr = ++ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; ++ mlxplat_led = &mlxplat_xdr_led_data; ++ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; ++ mlxplat_fan = &mlxplat_xdr_fan_data; ++ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) ++ mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; ++ mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; ++ mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; ++ ++ return mlxplat_register_platform_device(); ++} ++ + static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { + { + .callback = mlxplat_dmi_default_wc_matched, +@@ -7711,6 +8096,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { + }, + }, + { ++ .callback = mlxplat_dmi_xdr_matched, ++ .matches = { ++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0018"), ++ }, ++ }, ++ { + .callback = mlxplat_dmi_smart_switch_matched, + .matches = { + DMI_MATCH(DMI_BOARD_NAME, "VMOD0019"), +-- +2.8.4 + diff --git a/patch/0094-i2c-asf-Introduce-MCTP-support-over-ASF-controller.patch b/patches-sonic/0054-i2c-asf-Introduce-MCTP-support-over-ASF-controller.patch similarity index 98% rename from patch/0094-i2c-asf-Introduce-MCTP-support-over-ASF-controller.patch rename to patches-sonic/0054-i2c-asf-Introduce-MCTP-support-over-ASF-controller.patch index 454788c06..6aa7281fe 100644 --- a/patch/0094-i2c-asf-Introduce-MCTP-support-over-ASF-controller.patch +++ b/patches-sonic/0054-i2c-asf-Introduce-MCTP-support-over-ASF-controller.patch @@ -1,8 +1,7 @@ -From 4869f448e1c09fff47290505daa231aa5711b134 Mon Sep 17 00:00:00 2001 +From ad078b328cac385d8cce76f525e30c97d7bf2b18 Mon Sep 17 00:00:00 2001 From: amlakshm Date: Tue, 30 Jan 2024 14:18:35 +0530 -Subject: [PATCH backport 6.1 1/1] i2c: asf: Introduce MCTP support over ASF - controller +Subject: [PATCH 54/78] i2c: asf: Introduce MCTP support over ASF controller Provide driver for AMD ASF controller working as SMBus master and slave. @@ -12,12 +11,12 @@ Signed-off-by: Vadim Pasternak --- drivers/i2c/busses/Kconfig | 10 + drivers/i2c/busses/Makefile | 1 + - drivers/i2c/busses/i2c-asf.c | 934 +++++++++++++++++++++++++++++++++++ + drivers/i2c/busses/i2c-asf.c | 934 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 945 insertions(+) create mode 100644 drivers/i2c/busses/i2c-asf.c diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig -index 9460528c0b1b..d861071755d2 100644 +index 2254abd..7469cf2 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -95,6 +95,16 @@ config I2C_AMD_MP2 @@ -38,10 +37,10 @@ index 9460528c0b1b..d861071755d2 100644 tristate "Hix5hd2 high-speed I2C driver" depends on ARCH_HISI || ARCH_HIX5HD2 || COMPILE_TEST diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile -index e73cdb1d2b5a..3f4914c703c2 100644 +index ecc07c5..35486db 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile -@@ -141,6 +141,7 @@ obj-$(CONFIG_I2C_VIPERBOARD) += i2c-viperboard.o +@@ -144,6 +144,7 @@ obj-$(CONFIG_I2C_VIPERBOARD) += i2c-viperboard.o # Other I2C/SMBus bus drivers obj-$(CONFIG_I2C_ACORN) += i2c-acorn.o @@ -51,7 +50,7 @@ index e73cdb1d2b5a..3f4914c703c2 100644 obj-$(CONFIG_I2C_CROS_EC_TUNNEL) += i2c-cros-ec-tunnel.o diff --git a/drivers/i2c/busses/i2c-asf.c b/drivers/i2c/busses/i2c-asf.c new file mode 100644 -index 000000000000..c3d8ce2b6027 +index 00000000..815d3eb --- /dev/null +++ b/drivers/i2c/busses/i2c-asf.c @@ -0,0 +1,934 @@ @@ -855,7 +854,7 @@ index 000000000000..c3d8ce2b6027 + } + + adap->owner = THIS_MODULE; -+ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; ++ adap->class = I2C_CLASS_HWMON; + adap->algo = &asf_smbus_algorithm_sb800; + + adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL); @@ -990,5 +989,5 @@ index 000000000000..c3d8ce2b6027 +MODULE_DESCRIPTION("ASF SMBus driver"); +MODULE_LICENSE("GPL"); -- -2.20.1 +2.8.4 diff --git a/patch/0099-platform-mellanox-Downstream-Add-support-DGX-flavor-.patch b/patches-sonic/0055-platform-mellanox-Downstream-Add-support-DGX-flavor-.patch similarity index 88% rename from patch/0099-platform-mellanox-Downstream-Add-support-DGX-flavor-.patch rename to patches-sonic/0055-platform-mellanox-Downstream-Add-support-DGX-flavor-.patch index 59f713ddd..4a3c62055 100644 --- a/patch/0099-platform-mellanox-Downstream-Add-support-DGX-flavor-.patch +++ b/patches-sonic/0055-platform-mellanox-Downstream-Add-support-DGX-flavor-.patch @@ -1,7 +1,7 @@ -From fc7c0147a6816741ac6a3323b80e0debbbb6dbd4 Mon Sep 17 00:00:00 2001 +From 817b5cfab9f1eef11a244020caf1987bb37f682e Mon Sep 17 00:00:00 2001 From: Oleksandr Shamray Date: Mon, 9 Dec 2024 13:38:05 +0200 -Subject: [PATCH 08/15] platform: mellanox: Downstream: Add support DGX flavor +Subject: [PATCH 55/78] platform: mellanox: Downstream: Add support DGX flavor of next-generation 800GB/s ethernet switch. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -20,10 +20,10 @@ Signed-off-by: Oleksandr Shamray 1 file changed, 28 insertions(+) diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index 9346c76..0c42da1 100644 +index de3dbaf..3472c99 100644 --- a/drivers/platform/mellanox/mlx-platform.c +++ b/drivers/platform/mellanox/mlx-platform.c -@@ -8677,6 +8677,27 @@ static int __init mlxplat_dmi_ng800_matched(const struct dmi_system_id *dmi) +@@ -7871,6 +7871,27 @@ static int __init mlxplat_dmi_ng800_matched(const struct dmi_system_id *dmi) return mlxplat_register_platform_device(); } @@ -51,7 +51,7 @@ index 9346c76..0c42da1 100644 static int __init mlxplat_dmi_l1_switch_matched(const struct dmi_system_id *dmi) { int i; -@@ -8889,6 +8910,13 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { +@@ -8072,6 +8093,13 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { }, }, { diff --git a/patch/0195-platform-x86-MLX_PLATFORM-select-REGMAP-instead-of-d.patch b/patches-sonic/0195-platform-x86-MLX_PLATFORM-select-REGMAP-instead-of-d.patch similarity index 100% rename from patch/0195-platform-x86-MLX_PLATFORM-select-REGMAP-instead-of-d.patch rename to patches-sonic/0195-platform-x86-MLX_PLATFORM-select-REGMAP-instead-of-d.patch diff --git a/patch/0201-i2c-mlxbf-incorrect-base-address-passed-during-io-wr.patch b/patches-sonic/0201-i2c-mlxbf-incorrect-base-address-passed-during-io-wr.patch similarity index 100% rename from patch/0201-i2c-mlxbf-incorrect-base-address-passed-during-io-wr.patch rename to patches-sonic/0201-i2c-mlxbf-incorrect-base-address-passed-during-io-wr.patch diff --git a/patch/0202-i2c-mlxbf-prevent-stack-overflow-in-mlxbf_i2c_smbus_.patch b/patches-sonic/0202-i2c-mlxbf-prevent-stack-overflow-in-mlxbf_i2c_smbus_.patch similarity index 100% rename from patch/0202-i2c-mlxbf-prevent-stack-overflow-in-mlxbf_i2c_smbus_.patch rename to patches-sonic/0202-i2c-mlxbf-prevent-stack-overflow-in-mlxbf_i2c_smbus_.patch diff --git a/patch/0204-i2c-mlxbf-Fix-frequency-calculation.patch b/patches-sonic/0204-i2c-mlxbf-Fix-frequency-calculation.patch similarity index 100% rename from patch/0204-i2c-mlxbf-Fix-frequency-calculation.patch rename to patches-sonic/0204-i2c-mlxbf-Fix-frequency-calculation.patch diff --git a/patch/0205-i2c-mlxbf-support-lock-mechanism.patch b/patches-sonic/0205-i2c-mlxbf-support-lock-mechanism.patch similarity index 100% rename from patch/0205-i2c-mlxbf-support-lock-mechanism.patch rename to patches-sonic/0205-i2c-mlxbf-support-lock-mechanism.patch diff --git a/patch/0265-hwmon-mlxreg-fan-Return-zero-speed-for-broken-fan.patch b/patches-sonic/0265-hwmon-mlxreg-fan-Return-zero-speed-for-broken-fan.patch similarity index 100% rename from patch/0265-hwmon-mlxreg-fan-Return-zero-speed-for-broken-fan.patch rename to patches-sonic/0265-hwmon-mlxreg-fan-Return-zero-speed-for-broken-fan.patch diff --git a/patch/8000-mlxsw-Use-weak-reverse-dependencies-for-firmware-fla.patch b/patches-sonic/8000-mlxsw-Use-weak-reverse-dependencies-for-firmware-fla.patch similarity index 81% rename from patch/8000-mlxsw-Use-weak-reverse-dependencies-for-firmware-fla.patch rename to patches-sonic/8000-mlxsw-Use-weak-reverse-dependencies-for-firmware-fla.patch index ba8f2fd77..8ed47d5f3 100644 --- a/patch/8000-mlxsw-Use-weak-reverse-dependencies-for-firmware-fla.patch +++ b/patches-sonic/8000-mlxsw-Use-weak-reverse-dependencies-for-firmware-fla.patch @@ -1,8 +1,8 @@ -From 646a7ca330eddb18e915380c9e8296a8cbce3c81 Mon Sep 17 00:00:00 2001 +From 807fd2d518ea43c623268edecdc0b58361188af8 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Wed, 20 Oct 2021 09:49:28 +0000 -Subject: [PATCH backport 6.1.42 40/85] mlxsw: Use weak reverse dependencies - for firmware flashing selection +Subject: [PATCH 56/78] mlxsw: Use weak reverse dependencies for firmware + flashing selection Replace configuration options "select" by "imply". It allows to set 'MLXFW' symbol to 'n' from a direct dependency or with a visible @@ -17,7 +17,7 @@ Signed-off-by: Vadim Pasternak 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/Kconfig b/drivers/net/ethernet/mellanox/mlxsw/Kconfig -index a510bf2cff2f..efc7ec8fa33c 100644 +index 74f7e27..ae11732 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/Kconfig +++ b/drivers/net/ethernet/mellanox/mlxsw/Kconfig @@ -6,7 +6,7 @@ @@ -30,5 +30,5 @@ index a510bf2cff2f..efc7ec8fa33c 100644 help This driver supports Mellanox Technologies Switch ASICs family. -- -2.20.1 +2.8.4 diff --git a/patches-sonic/8001-platform-mlx-platform-Downstream-Add-SPI-path-for-ra.patch b/patches-sonic/8001-platform-mlx-platform-Downstream-Add-SPI-path-for-ra.patch new file mode 100644 index 000000000..94bab3943 --- /dev/null +++ b/patches-sonic/8001-platform-mlx-platform-Downstream-Add-SPI-path-for-ra.patch @@ -0,0 +1,92 @@ +From e598aed4536365af75ab5543364c79123d243104 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Wed, 2 Aug 2023 07:58:51 +0000 +Subject: [PATCH 57/78] platform: mlx-platform: Downstream: Add SPI path for + rack switch for EROT access + +Create spidev for OOB access to External Root of Trusts devices. + +Signed-off-by: Vadim Pasternak +--- + drivers/platform/mellanox/mlx-platform.c | 17 +++++++++++++++++ + drivers/spi/spi.c | 1 + + 2 files changed, 18 insertions(+) + +diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c +index 3472c99..9203ed8 100644 +--- a/drivers/platform/mellanox/mlx-platform.c ++++ b/drivers/platform/mellanox/mlx-platform.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + + #define MLX_PLAT_DEVICE_NAME "mlxplat" + +@@ -3336,6 +3337,16 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_l1_switch_data = { + .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT, + }; + ++static struct spi_board_info rack_switch_switch_spi_board_info[] = { ++ { ++ .modalias = "spidev", ++ .irq = -1, ++ .max_speed_hz = 20000000, ++ .bus_num = 0, ++ .chip_select = 0, ++ }, ++}; ++ + /* Platform hotplug for 800G systems family data */ + static struct mlxreg_core_item mlxplat_mlxcpld_ng800_hi171_items[] = { + { +@@ -7524,6 +7535,7 @@ static struct mlxreg_core_platform_data + *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS]; + static struct mlxreg_core_data *mlxplat_dpu_data[MLXPLAT_CPLD_DPU_MAX_DEVS]; + static const struct regmap_config *mlxplat_regmap_config; ++static struct spi_board_info *mlxplat_spi; + static struct pci_dev *lpc_bridge; + static struct pci_dev *i2c_bridge; + static struct pci_dev *jtag_bridge; +@@ -7846,6 +7858,7 @@ static int __init mlxplat_dmi_rack_switch_matched(const struct dmi_system_id *dm + mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; + mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; + mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_rack_switch; ++ mlxplat_spi = rack_switch_switch_spi_board_info; + + return mlxplat_register_platform_device(); + } +@@ -7911,6 +7924,7 @@ static int __init mlxplat_dmi_l1_switch_matched(const struct dmi_system_id *dmi) + mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_rack_switch; + pm_power_off = mlxplat_poweroff; + mlxplat_reboot_nb = &mlxplat_reboot_default_nb; ++ mlxplat_spi = rack_switch_switch_spi_board_info; + + return mlxplat_register_platform_device(); + } +@@ -8511,6 +8525,9 @@ static int mlxplat_platdevs_init(struct mlxplat_priv *priv) + } + } + ++ if (mlxplat_spi) ++ spi_register_board_info(mlxplat_spi, 1); ++ + /* Add WD drivers. */ + err = mlxplat_mlxcpld_check_wd_capability(priv->regmap); + if (err) +diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c +index 0f3e6e2..1e35969 100644 +--- a/drivers/spi/spi.c ++++ b/drivers/spi/spi.c +@@ -952,6 +952,7 @@ int spi_register_board_info(struct spi_board_info const *info, unsigned n) + + return 0; + } ++EXPORT_SYMBOL(spi_register_board_info); + + /*-------------------------------------------------------------------------*/ + +-- +2.8.4 + diff --git a/patch/8003-mlxsw-i2c-SONIC-ISSU-Prevent-transaction-execution-f.patch b/patches-sonic/8002-mlxsw-i2c-SONIC-ISSU-Prevent-transaction-execution-f.patch similarity index 92% rename from patch/8003-mlxsw-i2c-SONIC-ISSU-Prevent-transaction-execution-f.patch rename to patches-sonic/8002-mlxsw-i2c-SONIC-ISSU-Prevent-transaction-execution-f.patch index f6ce85ff0..87a432d9d 100644 --- a/patch/8003-mlxsw-i2c-SONIC-ISSU-Prevent-transaction-execution-f.patch +++ b/patches-sonic/8002-mlxsw-i2c-SONIC-ISSU-Prevent-transaction-execution-f.patch @@ -1,8 +1,8 @@ -From a2799b0fca7c4b59a6a4903675dcc7d6ba2a6ed2 Mon Sep 17 00:00:00 2001 +From 06d89b5634d1b54b88d63670a411868d5895c5ea Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Thu, 2 Jun 2022 15:34:53 +0300 -Subject: [PATH backport v6.1 1/2] mlxsw: i2c: SONIC: ISSU: Prevent transaction - execution for special chip states +Subject: [PATCH 58/78] mlxsw: i2c: SONIC: ISSU: Prevent transaction execution + for special chip states Do not run transaction in cases chip is in reset or in-service update states. @@ -16,11 +16,11 @@ re-probed again after reset or in-service update is completed. Signed-off-by: Vadim Pasternak --- drivers/net/ethernet/mellanox/mlxsw/cmd.h | 4 ++++ - drivers/net/ethernet/mellanox/mlxsw/i2c.c | 29 ++++++++++++++++++++--- + drivers/net/ethernet/mellanox/mlxsw/i2c.c | 29 ++++++++++++++++++++++++++--- 2 files changed, 30 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/cmd.h b/drivers/net/ethernet/mellanox/mlxsw/cmd.h -index 09bef04b11d1..71fdfc74e322 100644 +index e3271c8..89367bf 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/cmd.h +++ b/drivers/net/ethernet/mellanox/mlxsw/cmd.h @@ -149,6 +149,8 @@ enum mlxsw_cmd_status { @@ -42,7 +42,7 @@ index 09bef04b11d1..71fdfc74e322 100644 return "BAD_PKT"; default: diff --git a/drivers/net/ethernet/mellanox/mlxsw/i2c.c b/drivers/net/ethernet/mellanox/mlxsw/i2c.c -index 8eb32152ee04..43140eccc8bb 100644 +index 1e150ce..605a597 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/i2c.c +++ b/drivers/net/ethernet/mellanox/mlxsw/i2c.c @@ -77,6 +77,7 @@ @@ -101,7 +101,7 @@ index 8eb32152ee04..43140eccc8bb 100644 return err; } -@@ -685,14 +706,16 @@ static int mlxsw_i2c_probe(struct i2c_client *client, +@@ -684,14 +705,16 @@ static int mlxsw_i2c_probe(struct i2c_client *client) /* Wait until go bit is cleared. */ err = mlxsw_i2c_wait_go_bit(client, mlxsw_i2c, &status); if (err) { @@ -122,5 +122,5 @@ index 8eb32152ee04..43140eccc8bb 100644 goto errout; } -- -2.20.1 +2.8.4 diff --git a/patch/8004-mlxsw-minimal-Downstream-Ignore-error-reading-SPAD-r.patch b/patches-sonic/8003-mlxsw-minimal-Downstream-Ignore-error-reading-SPAD-r.patch similarity index 80% rename from patch/8004-mlxsw-minimal-Downstream-Ignore-error-reading-SPAD-r.patch rename to patches-sonic/8003-mlxsw-minimal-Downstream-Ignore-error-reading-SPAD-r.patch index 3a220713e..22f363573 100644 --- a/patch/8004-mlxsw-minimal-Downstream-Ignore-error-reading-SPAD-r.patch +++ b/patches-sonic/8003-mlxsw-minimal-Downstream-Ignore-error-reading-SPAD-r.patch @@ -1,8 +1,8 @@ -From a742d55ed36a0bd3b6346563665b951dad9ad469 Mon Sep 17 00:00:00 2001 +From c52801a7e7ac91a3587199a69459d7c6308725a7 Mon Sep 17 00:00:00 2001 From: root Date: Tue, 5 Apr 2022 21:35:55 +0300 -Subject: [PATH backport v6.1 2/3] mlxsw: minimal: Downstream: Ignore error - reading SPAD register +Subject: [PATCH 59/78] mlxsw: minimal: Downstream: Ignore error reading SPAD + register SPAD register is not supported for IB systems. @@ -12,7 +12,7 @@ Signed-off-by: Vadim Pasternak 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/minimal.c b/drivers/net/ethernet/mellanox/mlxsw/minimal.c -index 15116d9305f8..7396b37bc880 100644 +index 828c650..6faebeb 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/minimal.c +++ b/drivers/net/ethernet/mellanox/mlxsw/minimal.c @@ -53,6 +53,7 @@ struct mlxsw_m_port { @@ -32,5 +32,5 @@ index 15116d9305f8..7396b37bc880 100644 } -- -2.20.1 +2.8.4 diff --git a/patch/8005-leds-leds-mlxreg-Downstream-Send-udev-event-from-led.patch b/patches-sonic/8004-leds-leds-mlxreg-Downstream-Send-udev-event-from-led.patch similarity index 86% rename from patch/8005-leds-leds-mlxreg-Downstream-Send-udev-event-from-led.patch rename to patches-sonic/8004-leds-leds-mlxreg-Downstream-Send-udev-event-from-led.patch index 932b77fde..4364c3587 100644 --- a/patch/8005-leds-leds-mlxreg-Downstream-Send-udev-event-from-led.patch +++ b/patches-sonic/8004-leds-leds-mlxreg-Downstream-Send-udev-event-from-led.patch @@ -1,8 +1,8 @@ -From c8e0a4b95379b40e2fe768f00caee4c8b9fec42f Mon Sep 17 00:00:00 2001 +From 5122a4cbfb006f1fe5ddc069a52a1be725a21c93 Mon Sep 17 00:00:00 2001 From: Michael Shych Date: Mon, 11 Jul 2022 12:51:27 +0300 -Subject: [PATCH v6.1 64/81] leds: leds-mlxreg: Downstream: Send udev event - from leds-mlxreg driver. +Subject: [PATCH 60/78] leds: leds-mlxreg: Downstream: Send udev event from + leds-mlxreg driver. Add sending udev event from leds-mlxreg driver in case of color change. This patch will not be accepted in upstream as it provides no regular flow. @@ -16,18 +16,18 @@ Signed-off-by: Michael Shych 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/leds/leds-mlxreg.c b/drivers/leds/leds-mlxreg.c -index 6ddbfceaceec..236f116567ac 100644 +index 26add3e..a647048 100644 --- a/drivers/leds/leds-mlxreg.c +++ b/drivers/leds/leds-mlxreg.c -@@ -11,6 +11,7 @@ - #include +@@ -10,6 +10,7 @@ + #include #include #include +#include #include /* Codes for LEDs. */ -@@ -131,15 +132,39 @@ mlxreg_led_get_hw(struct mlxreg_led_data *led_data) +@@ -129,15 +130,39 @@ mlxreg_led_get_hw(struct mlxreg_led_data *led_data) return LED_OFF; } @@ -58,17 +58,17 @@ index 6ddbfceaceec..236f116567ac 100644 if (value) - return mlxreg_led_store_hw(led_data, led_data->base_color); + err = mlxreg_led_store_hw(led_data, led_data->base_color); -+ else + else +- return mlxreg_led_store_hw(led_data, MLXREG_LED_IS_OFF); + err = mlxreg_led_store_hw(led_data, MLXREG_LED_IS_OFF); + + if (!err) + return mlxreg_led_udev_event_send(led_data, value); - else -- return mlxreg_led_store_hw(led_data, MLXREG_LED_IS_OFF); ++ else + return err; } static enum led_brightness -- -2.20.1 +2.8.4 diff --git a/patch/8006-i2c-mlxcpld-Downstream-WA-to-avoid-error-for-SMBUS-r.patch b/patches-sonic/8005-i2c-mlxcpld-Downstream-WA-to-avoid-error-for-SMBUS-r.patch similarity index 80% rename from patch/8006-i2c-mlxcpld-Downstream-WA-to-avoid-error-for-SMBUS-r.patch rename to patches-sonic/8005-i2c-mlxcpld-Downstream-WA-to-avoid-error-for-SMBUS-r.patch index 20d658b75..47b51ed13 100644 --- a/patch/8006-i2c-mlxcpld-Downstream-WA-to-avoid-error-for-SMBUS-r.patch +++ b/patches-sonic/8005-i2c-mlxcpld-Downstream-WA-to-avoid-error-for-SMBUS-r.patch @@ -1,8 +1,8 @@ -From 63d8c9838b10472bd5e3c6e5a41596d6d44dd1c8 Mon Sep 17 00:00:00 2001 +From 9ade5581712d6bcaf7413152829f2dfc3a47ca5f Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Thu, 10 Aug 2023 12:03:31 +0000 -Subject: [PATCH backport 6.1.42 1/1] i2c: mlxcpld: Downstream WA to avoid - error for SMBUS read block command +Subject: [PATCH 61/78] i2c: mlxcpld: Downstream WA to avoid error for SMBUS + read block command Due to hardware bug in I2C controller skip handling SMBUS_READ_BLOCK command. @@ -14,7 +14,7 @@ Signed-off-by: Vadim Pasternak 1 file changed, 1 insertion(+) diff --git a/drivers/i2c/busses/i2c-mlxcpld.c b/drivers/i2c/busses/i2c-mlxcpld.c -index 2ce2c324ea4f..fd9def469132 100644 +index ecae755..c3b22aa 100644 --- a/drivers/i2c/busses/i2c-mlxcpld.c +++ b/drivers/i2c/busses/i2c-mlxcpld.c @@ -398,6 +398,7 @@ static int mlxcpld_i2c_wait_for_tc(struct mlxcpld_i2c_priv *priv) @@ -26,5 +26,5 @@ index 2ce2c324ea4f..fd9def469132 100644 &datalen, 1); if (unlikely(datalen > I2C_SMBUS_BLOCK_MAX)) { -- -2.20.1 +2.8.4 diff --git a/patch/8007-hwmon-mlxreg-fan-Downstream-Allow-fan-speed-setting-.patch b/patches-sonic/8006-hwmon-mlxreg-fan-Downstream-Allow-fan-speed-setting-.patch similarity index 91% rename from patch/8007-hwmon-mlxreg-fan-Downstream-Allow-fan-speed-setting-.patch rename to patches-sonic/8006-hwmon-mlxreg-fan-Downstream-Allow-fan-speed-setting-.patch index 69aaa50a7..636f2d143 100644 --- a/patch/8007-hwmon-mlxreg-fan-Downstream-Allow-fan-speed-setting-.patch +++ b/patches-sonic/8006-hwmon-mlxreg-fan-Downstream-Allow-fan-speed-setting-.patch @@ -1,7 +1,7 @@ -From 34758fcde60b934272415849940ee11da6328385 Mon Sep 17 00:00:00 2001 +From fc641945e34d2a6b6bc2a5bd083372c7c71b4198 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Thu, 2 Nov 2023 11:42:47 +0000 -Subject: [PATCH v6.1 81/81] hwmon: (mlxreg-fan): Downstream: Allow fan speed +Subject: [PATCH 62/78] hwmon: (mlxreg-fan): Downstream: Allow fan speed setting granularity of 1 PWM Currently PWM setting is allowed with 10 percent stepping. @@ -30,7 +30,7 @@ Signed-off-by: Vadim Pasternak 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/hwmon/mlxreg-fan.c b/drivers/hwmon/mlxreg-fan.c -index 102a517940f3..1c4adcfd4498 100644 +index 2cd0b9c..61f592c 100644 --- a/drivers/hwmon/mlxreg-fan.c +++ b/drivers/hwmon/mlxreg-fan.c @@ -15,10 +15,15 @@ @@ -52,5 +52,5 @@ index 102a517940f3..1c4adcfd4498 100644 #define MLXREG_FAN_TACHO_DIV_MIN 283 #define MLXREG_FAN_TACHO_DIV_DEF (MLXREG_FAN_TACHO_DIV_MIN * 4) -- -2.20.1 +2.8.4 diff --git a/patch/8008-hwmon-emc2305-Downstream-Allow-fan-speed-setting-gra.patch b/patches-sonic/8007-hwmon-emc2305-Downstream-Allow-fan-speed-setting-gra.patch similarity index 78% rename from patch/8008-hwmon-emc2305-Downstream-Allow-fan-speed-setting-gra.patch rename to patches-sonic/8007-hwmon-emc2305-Downstream-Allow-fan-speed-setting-gra.patch index 603086c0b..e17b6b62e 100644 --- a/patch/8008-hwmon-emc2305-Downstream-Allow-fan-speed-setting-gra.patch +++ b/patches-sonic/8007-hwmon-emc2305-Downstream-Allow-fan-speed-setting-gra.patch @@ -1,8 +1,8 @@ -From 93a52030e9545368c5dee5d38cb939d8efc796ce Mon Sep 17 00:00:00 2001 +From c43e12b088a65e3d4431712f3877969854d7057c Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Thu, 2 Nov 2023 12:18:22 +0000 -Subject: [PATCH v6.1.42 downstream 2/2] hwmon: (emc2305): Downstream: Allow - fan speed setting granularity of 1 PWM +Subject: [PATCH 63/78] hwmon: (emc2305): Downstream: Allow fan speed setting + granularity of 1 PWM Currently PWM setting is allowed with 10 percent stepping. Such configuration is aligned with thermal drivers, which are used to be @@ -30,16 +30,15 @@ Signed-off-by: Vadim Pasternak 1 file changed, 4 insertions(+) diff --git a/drivers/hwmon/emc2305.c b/drivers/hwmon/emc2305.c -index aa1f25add0b6..70be61d32089 100644 +index 4d39fbd..0066138 100644 --- a/drivers/hwmon/emc2305.c +++ b/drivers/hwmon/emc2305.c -@@ -19,7 +19,11 @@ emc2305_normal_i2c[] = { 0x27, 0x2c, 0x2d, 0x2e, 0x2f, 0x4c, 0x4d, I2C_CLIENT_EN +@@ -16,7 +16,11 @@ #define EMC2305_REG_VENDOR 0xfe #define EMC2305_FAN_MAX 0xff #define EMC2305_FAN_MIN 0x00 --#define EMC2305_FAN_MAX_STATE 10 +#ifdef CONFIG_MLXSW_CORE_THERMAL -+#define EMC2305_FAN_MAX_STATE 10 + #define EMC2305_FAN_MAX_STATE 10 +#else +#define EMC2305_FAN_MAX_STATE 255 +#endif @@ -47,5 +46,5 @@ index aa1f25add0b6..70be61d32089 100644 #define EMC2305_VENDOR 0x5d #define EMC2305_REG_PRODUCT_ID 0xfd -- -2.20.1 +2.8.4 diff --git a/patch/8009-hwmon-mlxsw-Downstream-Allow-fan-speed-setting-granu.patch b/patches-sonic/8008-hwmon-mlxsw-Downstream-Allow-fan-speed-setting-granu.patch similarity index 87% rename from patch/8009-hwmon-mlxsw-Downstream-Allow-fan-speed-setting-granu.patch rename to patches-sonic/8008-hwmon-mlxsw-Downstream-Allow-fan-speed-setting-granu.patch index e8649ec3c..33ecd3ba8 100644 --- a/patch/8009-hwmon-mlxsw-Downstream-Allow-fan-speed-setting-granu.patch +++ b/patches-sonic/8008-hwmon-mlxsw-Downstream-Allow-fan-speed-setting-granu.patch @@ -1,7 +1,7 @@ -From 38c77b2f033deb8957aaf1017d0067717b8853cf Mon Sep 17 00:00:00 2001 +From 4b90028daea354041ff3e9d63752019f30f69760 Mon Sep 17 00:00:00 2001 From: Oleksandr Shamray Date: Wed, 8 Nov 2023 14:52:38 +0200 -Subject: [PATCH] hwmon: (mlxsw): Downstream: Allow fan speed setting +Subject: [PATCH 64/78] hwmon: (mlxsw): Downstream: Allow fan speed setting granularity of 1 PWM Currently PWM setting is allowed with 10 percent stepping. @@ -30,11 +30,11 @@ Signed-off-by: Oleksandr Shamray 1 file changed, 5 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/core_thermal.c b/drivers/net/ethernet/mellanox/mlxsw/core_thermal.c -index d062034..cbc9ac2 100644 +index e746cd9..e19f36f2e 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/core_thermal.c +++ b/drivers/net/ethernet/mellanox/mlxsw/core_thermal.c -@@ -21,8 +21,13 @@ - #define MLXSW_THERMAL_ASIC_TEMP_HOT 105000 /* 105C */ +@@ -24,8 +24,13 @@ + #define MLXSW_THERMAL_MODULE_TEMP_HOT 80000 /* 80C */ #define MLXSW_THERMAL_HYSTERESIS_TEMP 5000 /* 5C */ #define MLXSW_THERMAL_MODULE_TEMP_SHIFT (MLXSW_THERMAL_HYSTERESIS_TEMP * 2) +#ifdef CONFIG_MLXSW_CORE_THERMAL diff --git a/patch/8010-mlxsw-i2c-Downstream-Add-retry-mechanism-for-failed-.patch b/patches-sonic/8009-mlxsw-i2c-Downstream-Add-retry-mechanism-for-failed-.patch similarity index 95% rename from patch/8010-mlxsw-i2c-Downstream-Add-retry-mechanism-for-failed-.patch rename to patches-sonic/8009-mlxsw-i2c-Downstream-Add-retry-mechanism-for-failed-.patch index 3351c1996..dafcd8153 100644 --- a/patch/8010-mlxsw-i2c-Downstream-Add-retry-mechanism-for-failed-.patch +++ b/patches-sonic/8009-mlxsw-i2c-Downstream-Add-retry-mechanism-for-failed-.patch @@ -1,8 +1,8 @@ -From 690d6ada04f5bd9a9a57edc7b67e311961fe134c Mon Sep 17 00:00:00 2001 +From c9c143552767e43c24b66a0c256f30c9b10abdb9 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Sun, 19 Nov 2023 13:22:27 +0000 -Subject: [PATCH v6.1 1/1] mlxsw: i2c: Downstream: Add retry mechanism for - failed transactions +Subject: [PATCH 65/78] mlxsw: i2c: Downstream: Add retry mechanism for failed + transactions Sometimes I2C transactions could broken or non-completed because of some noise on I2C line or because ASIC resources is busy handling @@ -15,11 +15,11 @@ is not successful. Signed-off-by: Vadim Pasternak --- - drivers/net/ethernet/mellanox/mlxsw/i2c.c | 33 ++++++++++++++++------- + drivers/net/ethernet/mellanox/mlxsw/i2c.c | 33 ++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/i2c.c b/drivers/net/ethernet/mellanox/mlxsw/i2c.c -index 43140eccc8bb..90d7bfe2865c 100644 +index 605a597..1ecf21f 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/i2c.c +++ b/drivers/net/ethernet/mellanox/mlxsw/i2c.c @@ -51,6 +51,7 @@ @@ -124,5 +124,5 @@ index 43140eccc8bb..90d7bfe2865c 100644 } -- -2.20.1 +2.8.4 diff --git a/patch/8011-mlxsw-minimal-Downstream-Disable-ethtool-interface.patch b/patches-sonic/8010-mlxsw-minimal-Downstream-Disable-ethtool-interface.patch similarity index 75% rename from patch/8011-mlxsw-minimal-Downstream-Disable-ethtool-interface.patch rename to patches-sonic/8010-mlxsw-minimal-Downstream-Disable-ethtool-interface.patch index 16967d44a..20792d8b3 100644 --- a/patch/8011-mlxsw-minimal-Downstream-Disable-ethtool-interface.patch +++ b/patches-sonic/8010-mlxsw-minimal-Downstream-Disable-ethtool-interface.patch @@ -1,8 +1,7 @@ -From c10df5bb36bfe0b73a4b3195e27f7c71b4e4caf1 Mon Sep 17 00:00:00 2001 +From 38714ff080a0e0abc22d0ace3c3b12adcb474ae1 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Sun, 14 Jan 2024 16:46:03 +0000 -Subject: [PATCH v6.1 1/1] mlxsw: minimal: Downstream: Disable ethtool - interface +Subject: [PATCH 66/78] mlxsw: minimal: Downstream: Disable ethtool interface Disable 'ethtool' interface, since it is un-used and just created un-necessary 'netdevice' interfaces. @@ -14,10 +13,10 @@ Signed-off-by: Vadim Pasternak 2 files changed, 4 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/core_env.c b/drivers/net/ethernet/mellanox/mlxsw/core_env.c -index 550475a108ef..c42eed1209a1 100644 +index 294e758..21cee901 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/core_env.c +++ b/drivers/net/ethernet/mellanox/mlxsw/core_env.c -@@ -1403,6 +1403,7 @@ int mlxsw_env_init(struct mlxsw_core *mlxsw_core, +@@ -1474,6 +1474,7 @@ int mlxsw_env_init(struct mlxsw_core *mlxsw_core, if (err) goto err_linecards_event_ops_register; @@ -26,10 +25,10 @@ index 550475a108ef..c42eed1209a1 100644 if (err) goto err_temp_warn_event_register; diff --git a/drivers/net/ethernet/mellanox/mlxsw/minimal.c b/drivers/net/ethernet/mellanox/mlxsw/minimal.c -index 7396b37bc880..5365e6984236 100644 +index 6faebeb..b72434f 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/minimal.c +++ b/drivers/net/ethernet/mellanox/mlxsw/minimal.c -@@ -532,6 +532,8 @@ static int mlxsw_m_ports_create(struct mlxsw_m *mlxsw_m) +@@ -534,6 +534,8 @@ static int mlxsw_m_ports_create(struct mlxsw_m *mlxsw_m) { int err; @@ -38,7 +37,7 @@ index 7396b37bc880..5365e6984236 100644 /* Fill out module to local port mapping array */ err = mlxsw_m_ports_module_map(mlxsw_m); if (err) -@@ -553,6 +555,7 @@ static int mlxsw_m_ports_create(struct mlxsw_m *mlxsw_m) +@@ -555,6 +557,7 @@ static int mlxsw_m_ports_create(struct mlxsw_m *mlxsw_m) static void mlxsw_m_ports_remove(struct mlxsw_m *mlxsw_m) { @@ -47,5 +46,5 @@ index 7396b37bc880..5365e6984236 100644 } -- -2.20.1 +2.8.4 diff --git a/patch/8012-hwmon-pmbus-Downstream-Workaround-for-psu-attributes.patch b/patches-sonic/8011-hwmon-pmbus-Downstream-Workaround-for-psu-attributes.patch similarity index 77% rename from patch/8012-hwmon-pmbus-Downstream-Workaround-for-psu-attributes.patch rename to patches-sonic/8011-hwmon-pmbus-Downstream-Workaround-for-psu-attributes.patch index 312da03d2..91689b7de 100644 --- a/patch/8012-hwmon-pmbus-Downstream-Workaround-for-psu-attributes.patch +++ b/patches-sonic/8011-hwmon-pmbus-Downstream-Workaround-for-psu-attributes.patch @@ -1,7 +1,7 @@ -From b8a552a5eb168b5f53292f639668eec5ece93935 Mon Sep 17 00:00:00 2001 +From 6108367b56ae9df24d5d5869860943a3156ae2db Mon Sep 17 00:00:00 2001 From: Ciju Rajan K Date: Thu, 10 Oct 2024 14:13:28 +0300 -Subject: hwmon: pmbus: Downstream: Workaround for psu attributes +Subject: [PATCH 67/78] hwmon: pmbus: Downstream: Workaround for psu attributes Starting from kernel 5.12.rc-1, pmbus reads are always forced down to chip and get the values directly. Driver @@ -20,10 +20,10 @@ Signed-off-by: Ciju Rajan K 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwmon/pmbus/pmbus_core.c b/drivers/hwmon/pmbus/pmbus_core.c -index 7ec049347..464ba9d5a 100644 +index a68b0a9..943118e 100644 --- a/drivers/hwmon/pmbus/pmbus_core.c +++ b/drivers/hwmon/pmbus/pmbus_core.c -@@ -1173,7 +1173,7 @@ static ssize_t pmbus_set_sensor(struct device *dev, +@@ -1248,7 +1248,7 @@ static ssize_t pmbus_set_sensor(struct device *dev, if (ret < 0) rv = ret; else @@ -33,5 +33,5 @@ index 7ec049347..464ba9d5a 100644 return rv; } -- -2.44.0 +2.8.4 diff --git a/patches-sonic/8013-hwmon-pmbus-mp2975-Clear-interrupts-at-probe.patch b/patches-sonic/8013-hwmon-pmbus-mp2975-Clear-interrupts-at-probe.patch new file mode 100644 index 000000000..282a5e128 --- /dev/null +++ b/patches-sonic/8013-hwmon-pmbus-mp2975-Clear-interrupts-at-probe.patch @@ -0,0 +1,70 @@ +From ac4dfa5e6a8186732ad1fe31ad70052e44222c9f Mon Sep 17 00:00:00 2001 +From: Ciju Rajan K +Date: Tue, 9 Sep 2025 08:48:47 +0300 +Subject: hwmon: pmbus: mp2975: Clear interrupts at probe + +This patch clears the the registers 0xfd & 0x03 +in both the pages to clear any of the stale interrupts. + +NVBug: #5360318 + +Signed-off-by: Ciju Rajan K +--- + drivers/hwmon/pmbus/mp2975.c | 28 ++++++++++++++++++++++++++++ + 1 file changed, 28 insertions(+) + +diff --git a/drivers/hwmon/pmbus/mp2975.c b/drivers/hwmon/pmbus/mp2975.c +index 280bb12f762c..fbaee50c7129 100644 +--- a/drivers/hwmon/pmbus/mp2975.c ++++ b/drivers/hwmon/pmbus/mp2975.c +@@ -38,6 +38,7 @@ + #define MP2975_MFR_UVP_SET 0xe6 + + #define MP2973_MFR_RESO_SET 0xc7 ++#define MP2975_CLEAR_CAT_FAULTS 0xfd + + #define MP2975_VOUT_FORMAT BIT(15) + #define MP2975_VID_STEP_SEL_R1 BIT(4) +@@ -939,6 +940,28 @@ mp2975_vout_per_rail_config_get(struct i2c_client *client, + return 0; + } + ++static int ++mp2975_clear_interrupts(struct i2c_client *client, ++ struct mp2975_data *data) ++{ ++ int i = 0; ++ int ret = 0; ++ ++ for (i = 0; i < data->info.pages; i++) { ++ ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, i); ++ if (ret < 0) ++ return ret; ++ ret = i2c_smbus_write_byte_data(client, PMBUS_CLEAR_FAULTS, 0); ++ if (ret < 0) ++ return ret; ++ ret = i2c_smbus_write_byte_data(client, MP2975_CLEAR_CAT_FAULTS, 0); ++ if (ret < 0) ++ return ret; ++ } ++ ++ return ret; ++} ++ + static const struct pmbus_driver_info mp2975_info = { + .pages = 1, + .format[PSC_VOLTAGE_IN] = linear, +@@ -1068,6 +1091,11 @@ static int mp2975_probe(struct i2c_client *client) + if (ret) + return ret; + ++ /* Clear interrupts. */ ++ ret = mp2975_clear_interrupts(client, data); ++ if (ret) ++ return ret; ++ + return pmbus_do_probe(client, info); + } + +-- +2.47.2 diff --git a/patches-sonic/8014-platform-mellanox-mlxreg-dpu-Debug-trace-for-dpu-pro.patch b/patches-sonic/8014-platform-mellanox-mlxreg-dpu-Debug-trace-for-dpu-pro.patch new file mode 100644 index 000000000..03b7156c0 --- /dev/null +++ b/patches-sonic/8014-platform-mellanox-mlxreg-dpu-Debug-trace-for-dpu-pro.patch @@ -0,0 +1,32 @@ +From e7838edd2acc793f3b43ab04b3693a340273c330 Mon Sep 17 00:00:00 2001 +From: Ciju Rajan K +Date: Fri, 19 Sep 2025 09:51:17 +0300 +Subject: platform: mellanox: mlxreg-dpu: Debug trace for dpu probing + +Signed-off-by: Ciju Rajan K +--- + drivers/platform/mellanox/mlxreg-dpu.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/drivers/platform/mellanox/mlxreg-dpu.c b/drivers/platform/mellanox/mlxreg-dpu.c +index 314385cc1495..3b07c66c87dc 100644 +--- a/drivers/platform/mellanox/mlxreg-dpu.c ++++ b/drivers/platform/mellanox/mlxreg-dpu.c +@@ -530,9 +530,13 @@ static int mlxreg_dpu_probe(struct platform_device *pdev) + if (!data || !data->hpdev.brdinfo) + return -EINVAL; + ++ dev_info(&pdev->dev, "Probing for adapter %d\n", data->hpdev.nr); + data->hpdev.adapter = i2c_get_adapter(data->hpdev.nr); +- if (!data->hpdev.adapter) ++ if (!data->hpdev.adapter) { ++ dev_info(&pdev->dev, "Will try a deferred probing for %d\n", ++ data->hpdev.nr); + return -EPROBE_DEFER; ++ } + + mlxreg_dpu = devm_kzalloc(&pdev->dev, sizeof(*mlxreg_dpu), GFP_KERNEL); + if (!mlxreg_dpu) { +-- +2.47.2 + diff --git a/patch/0098-platform-mellanox-Downstream-Add-support-for-new-Nvi.patch b/patches-sonic/9000-platform-mellanox-Downstream-Add-support-for-new-Nvi.patch similarity index 93% rename from patch/0098-platform-mellanox-Downstream-Add-support-for-new-Nvi.patch rename to patches-sonic/9000-platform-mellanox-Downstream-Add-support-for-new-Nvi.patch index 10aa08474..7f058ea7b 100644 --- a/patch/0098-platform-mellanox-Downstream-Add-support-for-new-Nvi.patch +++ b/patches-sonic/9000-platform-mellanox-Downstream-Add-support-for-new-Nvi.patch @@ -1,7 +1,7 @@ -From 509f23639fc2c60df25171533f8166cf169d7d3d Mon Sep 17 00:00:00 2001 +From a209121e8dc093705e0f3fcc3aad27d4c28d949d Mon Sep 17 00:00:00 2001 From: Oleksandr Shamray Date: Mon, 9 Dec 2024 11:42:37 +0200 -Subject: [PATCH 07/15] platform: mellanox: Downstream: Add support for new +Subject: [PATCH 69/78] platform: mellanox: Downstream: Add support for new Nvidia IB DGX system based on class VMOD0010 This system is based on Nvidia QM9700 64x400G QTM-2 IB switch, with the @@ -12,15 +12,16 @@ Key changes: 2.Dimensions MGX/DGX 1U compliance Signed-off-by: Oleksandr Shamray +Reviewed-by: Vadim Pasternak --- - drivers/platform/mellanox/mlx-platform.c | 456 +++++++++++++++++++++++++++++++ - 1 file changed, 456 insertions(+) + drivers/platform/mellanox/mlx-platform.c | 454 +++++++++++++++++++++++++++++++ + 1 file changed, 454 insertions(+) diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index 5796e46..9346c76 100644 +index 9203ed8..710c21d 100644 --- a/drivers/platform/mellanox/mlx-platform.c +++ b/drivers/platform/mellanox/mlx-platform.c -@@ -822,6 +822,16 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_psu_items_data[] = { +@@ -825,6 +825,16 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_psu_items_data[] = { }, }; @@ -37,7 +38,7 @@ index 5796e46..9346c76 100644 static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_items_data[] = { { .label = "pwr1", -@@ -871,6 +881,15 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_ng800_items_data[] = +@@ -874,6 +884,15 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_ng800_items_data[] = }, }; @@ -53,7 +54,7 @@ index 5796e46..9346c76 100644 static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = { { .label = "fan1", -@@ -1594,6 +1613,45 @@ static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = { +@@ -1497,6 +1516,45 @@ static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = { } }; @@ -99,13 +100,13 @@ index 5796e46..9346c76 100644 static struct mlxreg_core_item mlxplat_mlxcpld_ng800_items[] = { { .data = mlxplat_mlxcpld_default_ng_psu_items_data, -@@ -2081,6 +2139,16 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { +@@ -1549,6 +1607,16 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { }; static +struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_dgx_ext_data = { + .items = mlxplat_mlxcpld_ext_dgx_items, -+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_ext_dgx_items), ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_dgx_items), + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, + .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, @@ -115,13 +116,11 @@ index 5796e46..9346c76 100644 +static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_data = { .items = mlxplat_mlxcpld_ng800_items, - .counter = ARRAY_SIZE(mlxplat_mlxcpld_ng800_items), -@@ -5256,6 +5324,361 @@ static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = { + .count = ARRAY_SIZE(mlxplat_mlxcpld_ng800_items), +@@ -5048,6 +5116,359 @@ static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = { .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data), }; -+ -+ +/* Platform register access for next generation systems families data */ +static struct mlxreg_core_data mlxplat_mlxcpld_dgx_ng_regs_io_data[] = { + { @@ -478,7 +477,7 @@ index 5796e46..9346c76 100644 /* Platform register access for modular systems families data */ static struct mlxreg_core_data mlxplat_mlxcpld_modular_regs_io_data[] = { { -@@ -8117,6 +8540,32 @@ static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi) +@@ -7799,6 +8220,32 @@ static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi) return mlxplat_register_platform_device(); } @@ -511,7 +510,7 @@ index 5796e46..9346c76 100644 static int __init mlxplat_dmi_modular_matched(const struct dmi_system_id *dmi) { int i; -@@ -8421,6 +8870,13 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { +@@ -8095,6 +8542,13 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { }, }, { diff --git a/patch/PCI-ASPM-Fix-link-state-exit-during-switch-upstream.patch b/patches-sonic/PCI-ASPM-Fix-link-state-exit-during-switch-upstream.patch similarity index 100% rename from patch/PCI-ASPM-Fix-link-state-exit-during-switch-upstream.patch rename to patches-sonic/PCI-ASPM-Fix-link-state-exit-during-switch-upstream.patch diff --git a/patch/Support-for-fullcone-nat.patch b/patches-sonic/Support-for-fullcone-nat.patch similarity index 100% rename from patch/Support-for-fullcone-nat.patch rename to patches-sonic/Support-for-fullcone-nat.patch diff --git a/patch/bridge-per-port-multicast-broadcast-flood-flags.patch b/patches-sonic/bridge-per-port-multicast-broadcast-flood-flags.patch similarity index 100% rename from patch/bridge-per-port-multicast-broadcast-flood-flags.patch rename to patches-sonic/bridge-per-port-multicast-broadcast-flood-flags.patch diff --git a/patch/cisco-Enable-static-memory-reservation-for-OIRable-PCIe-de.patch b/patches-sonic/cisco-Enable-static-memory-reservation-for-OIRable-PCIe-de.patch similarity index 95% rename from patch/cisco-Enable-static-memory-reservation-for-OIRable-PCIe-de.patch rename to patches-sonic/cisco-Enable-static-memory-reservation-for-OIRable-PCIe-de.patch index 0b093c85d..cb9141b82 100644 --- a/patch/cisco-Enable-static-memory-reservation-for-OIRable-PCIe-de.patch +++ b/patches-sonic/cisco-Enable-static-memory-reservation-for-OIRable-PCIe-de.patch @@ -20,7 +20,7 @@ index 2ce636937..64155eddc 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -967,6 +967,154 @@ static inline resource_size_t calculate_mem_align(resource_size_t *aligns, - return min_align; + return true; } +#define PLX_RES_MAGIC_VALUE 0xABBA @@ -183,12 +183,12 @@ index 2ce636937..64155eddc 100644 if (!b_res) return -ENOSPC; @@ -1016,6 +1165,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, - list_for_each_entry(dev, &bus->devices, bus_list) { + struct resource *r; int i; + dev_count++; - for (i = 0; i < PCI_NUM_RESOURCES; i++) { - struct resource *r = &dev->resource[i]; + pci_dev_for_each_resource(dev, r, i) { + const char *r_name = pci_resource_name(dev, i); resource_size_t r_size; @@ -1071,6 +1221,28 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, } @@ -216,9 +216,9 @@ index 2ce636937..64155eddc 100644 + } + } + + win_align = window_alignment(bus, b_res->flags); min_align = calculate_mem_align(aligns, max_order); - min_align = max(min_align, window_alignment(bus, b_res->flags)); - size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), min_align); + min_align = max(min_align, win_align); -- 2.26.2 diff --git a/patch/cisco-acpi-spi-nor.patch b/patches-sonic/cisco-acpi-spi-nor.patch similarity index 96% rename from patch/cisco-acpi-spi-nor.patch rename to patches-sonic/cisco-acpi-spi-nor.patch index 8ece7f41f..8dab722c2 100644 --- a/patch/cisco-acpi-spi-nor.patch +++ b/patches-sonic/cisco-acpi-spi-nor.patch @@ -20,9 +20,9 @@ index 2b26a875a..82bbd84a2 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -21,6 +21,7 @@ - #include + #include + #include #include - #include +#include #include "core.h" diff --git a/patch/cisco-add-support-for-ltc2979-chip.patch b/patches-sonic/cisco-add-support-for-ltc2979-chip.patch similarity index 100% rename from patch/cisco-add-support-for-ltc2979-chip.patch rename to patches-sonic/cisco-add-support-for-ltc2979-chip.patch diff --git a/patch/cisco-ds4424-null-of-node.patch b/patches-sonic/cisco-ds4424-null-of-node.patch similarity index 100% rename from patch/cisco-ds4424-null-of-node.patch rename to patches-sonic/cisco-ds4424-null-of-node.patch diff --git a/patch/cisco-hwmon-pmbus_core-pec-support-check.patch b/patches-sonic/cisco-hwmon-pmbus_core-pec-support-check.patch similarity index 100% rename from patch/cisco-hwmon-pmbus_core-pec-support-check.patch rename to patches-sonic/cisco-hwmon-pmbus_core-pec-support-check.patch diff --git a/patch/cisco-mdio-mux-support-acpi.patch b/patches-sonic/cisco-mdio-mux-support-acpi.patch similarity index 92% rename from patch/cisco-mdio-mux-support-acpi.patch rename to patches-sonic/cisco-mdio-mux-support-acpi.patch index bacb5e503..d4a95c78b 100644 --- a/patch/cisco-mdio-mux-support-acpi.patch +++ b/patches-sonic/cisco-mdio-mux-support-acpi.patch @@ -57,8 +57,8 @@ index ccb3ee704..e70c8d36a 100644 + r = fwnode_property_read_u32(child_bus_node, "reg", &v); if (r) { dev_err(dev, - "Error: Failed to find reg for child %pOF\n", - child_bus_node); + "Error: Failed to find reg for child %pOF: %pe\n", + child_bus_node, ERR_PTR(r)); continue; } + r = fwnode_property_read_u32(child_bus_node, "phy_mask", &phy_mask); @@ -68,9 +68,9 @@ index ccb3ee704..e70c8d36a 100644 cb = devm_kzalloc(dev, sizeof(*cb), GFP_KERNEL); if (!cb) { @@ -173,7 +177,12 @@ int mdio_mux_init(struct device *dev, - cb->mii_bus->parent = dev; - cb->mii_bus->read = mdio_mux_read; - cb->mii_bus->write = mdio_mux_write; + cb->mii_bus->read_c45 = mdio_mux_read_c45; + if (parent_bus->write_c45) + cb->mii_bus->write_c45 = mdio_mux_write_c45; - r = of_mdiobus_register(cb->mii_bus, child_bus_node); + cb->mii_bus->phy_mask = phy_mask; + if (is_of_node(child_bus_node)) diff --git a/patch/cisco-mtd-part.patch b/patches-sonic/cisco-mtd-part.patch similarity index 100% rename from patch/cisco-mtd-part.patch rename to patches-sonic/cisco-mtd-part.patch diff --git a/patch/cisco-npu-disable-other-bars.patch b/patches-sonic/cisco-npu-disable-other-bars.patch similarity index 91% rename from patch/cisco-npu-disable-other-bars.patch rename to patches-sonic/cisco-npu-disable-other-bars.patch index a6d800536..38a5f04b4 100644 --- a/patch/cisco-npu-disable-other-bars.patch +++ b/patches-sonic/cisco-npu-disable-other-bars.patch @@ -23,10 +23,10 @@ diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 16fb3d771..0efe3f62a 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c -@@ -6139,3 +6139,48 @@ static void apex_pci_fixup_class(struct pci_dev *pdev) - pdev->d3cold_delay = 1000; - } - DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec); +@@ -6314,3 +6314,48 @@ static void apex_pci_fixup_class(struct pci_dev *pdev) + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout); + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout); + #endif + +#define PCI_DEVICE_ID_LEABA_PACIFIC 0xabcd +#define PCI_DEVICE_ID_LEABA_GIBRALTAR 0xa001 diff --git a/patch/cisco-x86-gpio-config.patch b/patches-sonic/cisco-x86-gpio-config.patch similarity index 100% rename from patch/cisco-x86-gpio-config.patch rename to patches-sonic/cisco-x86-gpio-config.patch diff --git a/patch/driver-arista-i2c-designware-shutdown.patch b/patches-sonic/driver-arista-i2c-designware-shutdown.patch similarity index 79% rename from patch/driver-arista-i2c-designware-shutdown.patch rename to patches-sonic/driver-arista-i2c-designware-shutdown.patch index 268d35a30..d2dbeff2b 100644 --- a/patch/driver-arista-i2c-designware-shutdown.patch +++ b/patches-sonic/driver-arista-i2c-designware-shutdown.patch @@ -22,8 +22,8 @@ diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2 index 01234567..89abcdef 100644 --- a/drivers/i2c/busses/i2c-designware-platdrv.c +++ b/drivers/i2c/busses/i2c-designware-platdrv.c -@@ -350,6 +350,21 @@ static int dw_i2c_plat_remove(struct platform_device *pdev) - return 0; +@@ -333,6 +333,21 @@ static int dw_i2c_plat_remove(struct platform_device *pdev) + reset_control_assert(dev->rst); } +static void dw_i2c_plat_shutdown(struct platform_device *pdev) @@ -32,7 +32,7 @@ index 01234567..89abcdef 100644 + + pm_runtime_get_sync(&pdev->dev); + -+ dev->disable(dev); ++ i2c_dw_disable(dev); + + pm_runtime_dont_use_autosuspend(&pdev->dev); + pm_runtime_put_sync(&pdev->dev); @@ -41,14 +41,14 @@ index 01234567..89abcdef 100644 + reset_control_assert(dev->rst); +} + - #ifdef CONFIG_PM_SLEEP - static int dw_i2c_plat_prepare(struct device *dev) - { -@@ -425,6 +440,7 @@ MODULE_ALIAS("platform:i2c_designware"); + static const struct of_device_id dw_i2c_of_match[] = { + { .compatible = "snps,designware-i2c", }, + { .compatible = "mscc,ocelot-i2c", .data = (void *)MODEL_MSCC_OCELOT }, +@@ -371,6 +386,7 @@ MODULE_ALIAS("platform:i2c_designware"); static struct platform_driver dw_i2c_driver = { .probe = dw_i2c_plat_probe, - .remove = dw_i2c_plat_remove, + .remove_new = dw_i2c_plat_remove, + .shutdown = dw_i2c_plat_shutdown, .driver = { .name = "i2c_designware", - .of_match_table = of_match_ptr(dw_i2c_of_match), + .of_match_table = dw_i2c_of_match, diff --git a/patch/driver-arista-mmcblk-not-working-on-AMD-platforms.patch b/patches-sonic/driver-arista-mmcblk-not-working-on-AMD-platforms.patch similarity index 100% rename from patch/driver-arista-mmcblk-not-working-on-AMD-platforms.patch rename to patches-sonic/driver-arista-mmcblk-not-working-on-AMD-platforms.patch diff --git a/patch/driver-arista-net-tg3-access-regs-indirectly.patch b/patches-sonic/driver-arista-net-tg3-access-regs-indirectly.patch similarity index 100% rename from patch/driver-arista-net-tg3-access-regs-indirectly.patch rename to patches-sonic/driver-arista-net-tg3-access-regs-indirectly.patch diff --git a/patch/driver-arista-net-tg3-disallow-broadcom-default-mac.patch b/patches-sonic/driver-arista-net-tg3-disallow-broadcom-default-mac.patch similarity index 100% rename from patch/driver-arista-net-tg3-disallow-broadcom-default-mac.patch rename to patches-sonic/driver-arista-net-tg3-disallow-broadcom-default-mac.patch diff --git a/patch/driver-arista-net-tg3-dma-mask-4g-sb800.patch b/patches-sonic/driver-arista-net-tg3-dma-mask-4g-sb800.patch similarity index 95% rename from patch/driver-arista-net-tg3-dma-mask-4g-sb800.patch rename to patches-sonic/driver-arista-net-tg3-dma-mask-4g-sb800.patch index 8d307d793..cf5dea2ea 100644 --- a/patch/driver-arista-net-tg3-dma-mask-4g-sb800.patch +++ b/patches-sonic/driver-arista-net-tg3-dma-mask-4g-sb800.patch @@ -41,9 +41,9 @@ index 5143cdd0e..72198ef56 100644 if (!tg3_flag(tp, IS_5788) && tg3_asic_rev(tp) != ASIC_REV_5700) -@@ -17757,7 +17768,7 @@ static int tg3_init_one(struct pci_dev *pdev, +@@ -17796,7 +17807,7 @@ static int tg3_init_one(struct pci_dev *pdev, * On 64-bit systems without IOMMU, use 64-bit dma_mask and - * do DMA address check in tg3_start_xmit(). + * do DMA address check in __tg3_start_xmit(). */ - if (tg3_flag(tp, IS_5788)) + if (tg3_flag(tp, 4G_DMA_ONLY)) diff --git a/patch/driver-arista-pci-reassign-pref-mem.patch b/patches-sonic/driver-arista-pci-reassign-pref-mem.patch similarity index 99% rename from patch/driver-arista-pci-reassign-pref-mem.patch rename to patches-sonic/driver-arista-pci-reassign-pref-mem.patch index b93c28483..1d653923e 100644 --- a/patch/driver-arista-pci-reassign-pref-mem.patch +++ b/patches-sonic/driver-arista-pci-reassign-pref-mem.patch @@ -55,8 +55,8 @@ index 522d2b974..f866adb07 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -31,6 +31,8 @@ obj-$(CONFIG_PCI_ECAM) += ecam.o - obj-$(CONFIG_VGA_ARB) += vgaarb.o - obj-$(CONFIG_PCI_DOE) += doe.o + obj-$(CONFIG_PCI_DYNAMIC_OF_NODES) += of_property.o + obj-$(CONFIG_PCI_NPEM) += npem.o +obj-$(CONFIG_PCI_REASSIGN_PREF_MEM) += setup-prefmem.o + diff --git a/patch/driver-arista-restrict-eMMC-drive-to-50Mhz-from-userland.patch b/patches-sonic/driver-arista-restrict-eMMC-drive-to-50Mhz-from-userland.patch similarity index 100% rename from patch/driver-arista-restrict-eMMC-drive-to-50Mhz-from-userland.patch rename to patches-sonic/driver-arista-restrict-eMMC-drive-to-50Mhz-from-userland.patch diff --git a/patch/driver-at24-fix-odd-length-two-byte-access.patch b/patches-sonic/driver-at24-fix-odd-length-two-byte-access.patch similarity index 100% rename from patch/driver-at24-fix-odd-length-two-byte-access.patch rename to patches-sonic/driver-at24-fix-odd-length-two-byte-access.patch diff --git a/patch/driver-hwmon-lm75b-update.patch b/patches-sonic/driver-hwmon-lm75b-update.patch similarity index 100% rename from patch/driver-hwmon-lm75b-update.patch rename to patches-sonic/driver-hwmon-lm75b-update.patch diff --git a/patch/driver-hwmon-max6658-fix-write-convrate.patch b/patches-sonic/driver-hwmon-max6658-fix-write-convrate.patch similarity index 100% rename from patch/driver-hwmon-max6658-fix-write-convrate.patch rename to patches-sonic/driver-hwmon-max6658-fix-write-convrate.patch diff --git a/patch/driver-hwmon-pmbus-add-dps460-support.patch b/patches-sonic/driver-hwmon-pmbus-add-dps460-support.patch similarity index 100% rename from patch/driver-hwmon-pmbus-add-dps460-support.patch rename to patches-sonic/driver-hwmon-pmbus-add-dps460-support.patch diff --git a/patch/driver-hwmon-pmbus-dni_dps460-add-status-attributes.patch b/patches-sonic/driver-hwmon-pmbus-dni_dps460-add-status-attributes.patch similarity index 100% rename from patch/driver-hwmon-pmbus-dni_dps460-add-status-attributes.patch rename to patches-sonic/driver-hwmon-pmbus-dni_dps460-add-status-attributes.patch diff --git a/patch/driver-hwmon-pmbus-dni_dps460-update-pmbus-core.patch b/patches-sonic/driver-hwmon-pmbus-dni_dps460-update-pmbus-core.patch similarity index 100% rename from patch/driver-hwmon-pmbus-dni_dps460-update-pmbus-core.patch rename to patches-sonic/driver-hwmon-pmbus-dni_dps460-update-pmbus-core.patch diff --git a/patch/driver-hwmon-pmbus-dni_dps460.patch b/patches-sonic/driver-hwmon-pmbus-dni_dps460.patch similarity index 100% rename from patch/driver-hwmon-pmbus-dni_dps460.patch rename to patches-sonic/driver-hwmon-pmbus-dni_dps460.patch diff --git a/patch/driver-hwmon-pmbus-dps1900.patch b/patches-sonic/driver-hwmon-pmbus-dps1900.patch similarity index 100% rename from patch/driver-hwmon-pmbus-dps1900.patch rename to patches-sonic/driver-hwmon-pmbus-dps1900.patch diff --git a/patch/driver-hwmon-pmbus-dps200.patch b/patches-sonic/driver-hwmon-pmbus-dps200.patch similarity index 100% rename from patch/driver-hwmon-pmbus-dps200.patch rename to patches-sonic/driver-hwmon-pmbus-dps200.patch diff --git a/patch/driver-hwmon-pmbus-ucd9200-mlnx.patch b/patches-sonic/driver-hwmon-pmbus-ucd9200-mlnx.patch similarity index 100% rename from patch/driver-hwmon-pmbus-ucd9200-mlnx.patch rename to patches-sonic/driver-hwmon-pmbus-ucd9200-mlnx.patch diff --git a/patch/driver-i2c-bus-intel-ismt-add-delay-param.patch b/patches-sonic/driver-i2c-bus-intel-ismt-add-delay-param.patch similarity index 100% rename from patch/driver-i2c-bus-intel-ismt-add-delay-param.patch rename to patches-sonic/driver-i2c-bus-intel-ismt-add-delay-param.patch diff --git a/patch/driver-net-tg3-add-param-short-preamble-and-reset.patch b/patches-sonic/driver-net-tg3-add-param-short-preamble-and-reset.patch similarity index 100% rename from patch/driver-net-tg3-add-param-short-preamble-and-reset.patch rename to patches-sonic/driver-net-tg3-add-param-short-preamble-and-reset.patch diff --git a/patch/driver-net-tg3-change-dma-mask-for-57766.patch b/patches-sonic/driver-net-tg3-change-dma-mask-for-57766.patch similarity index 97% rename from patch/driver-net-tg3-change-dma-mask-for-57766.patch rename to patches-sonic/driver-net-tg3-change-dma-mask-for-57766.patch index e6af2a65c..8f2adce12 100644 --- a/patch/driver-net-tg3-change-dma-mask-for-57766.patch +++ b/patches-sonic/driver-net-tg3-change-dma-mask-for-57766.patch @@ -22,7 +22,7 @@ index 6a1179935..b1bb1dc55 100644 +++ b/drivers/net/ethernet/broadcom/tg3.c @@ -17794,7 +17794,7 @@ static int tg3_init_one(struct pci_dev *pdev, * On 64-bit systems without IOMMU, use 64-bit dma_mask and - * do DMA address check in tg3_start_xmit(). + * do DMA address check in __tg3_start_xmit(). */ - if (tg3_flag(tp, 4G_DMA_ONLY)) + if (tg3_flag(tp, 4G_DMA_ONLY) || (tg3_asic_rev(tp) == ASIC_REV_57766)) diff --git a/patch/driver-sff-8436-use-nvmem-framework.patch b/patches-sonic/driver-sff-8436-use-nvmem-framework.patch similarity index 100% rename from patch/driver-sff-8436-use-nvmem-framework.patch rename to patches-sonic/driver-sff-8436-use-nvmem-framework.patch diff --git a/patch/driver-sff-8436-use-nvmem_device_read.patch b/patches-sonic/driver-sff-8436-use-nvmem_device_read.patch similarity index 100% rename from patch/driver-sff-8436-use-nvmem_device_read.patch rename to patches-sonic/driver-sff-8436-use-nvmem_device_read.patch diff --git a/patch/driver-support-optoe-EOF_fix.patch b/patches-sonic/driver-support-optoe-EOF_fix.patch similarity index 100% rename from patch/driver-support-optoe-EOF_fix.patch rename to patches-sonic/driver-support-optoe-EOF_fix.patch diff --git a/patch/driver-support-optoe-QSFP_DD.patch b/patches-sonic/driver-support-optoe-QSFP_DD.patch similarity index 100% rename from patch/driver-support-optoe-QSFP_DD.patch rename to patches-sonic/driver-support-optoe-QSFP_DD.patch diff --git a/patch/driver-support-optoe-chunk-offset-fix.patch b/patches-sonic/driver-support-optoe-chunk-offset-fix.patch similarity index 100% rename from patch/driver-support-optoe-chunk-offset-fix.patch rename to patches-sonic/driver-support-optoe-chunk-offset-fix.patch diff --git a/patch/driver-support-optoe-dynamic-write-timeout.patch b/patches-sonic/driver-support-optoe-dynamic-write-timeout.patch similarity index 100% rename from patch/driver-support-optoe-dynamic-write-timeout.patch rename to patches-sonic/driver-support-optoe-dynamic-write-timeout.patch diff --git a/patch/driver-support-optoe-oneaddr-pageable.patch b/patches-sonic/driver-support-optoe-oneaddr-pageable.patch similarity index 100% rename from patch/driver-support-optoe-oneaddr-pageable.patch rename to patches-sonic/driver-support-optoe-oneaddr-pageable.patch diff --git a/patch/driver-support-optoe-twoaddr-a2h-access.patch b/patches-sonic/driver-support-optoe-twoaddr-a2h-access.patch similarity index 100% rename from patch/driver-support-optoe-twoaddr-a2h-access.patch rename to patches-sonic/driver-support-optoe-twoaddr-a2h-access.patch diff --git a/patch/driver-support-optoe-update-to-linux-6.1.patch b/patches-sonic/driver-support-optoe-update-to-linux-6.1.patch similarity index 100% rename from patch/driver-support-optoe-update-to-linux-6.1.patch rename to patches-sonic/driver-support-optoe-update-to-linux-6.1.patch diff --git a/patches-sonic/driver-support-optoe-update-to-linux-6.10.patch b/patches-sonic/driver-support-optoe-update-to-linux-6.10.patch new file mode 100644 index 000000000..9acb0da5b --- /dev/null +++ b/patches-sonic/driver-support-optoe-update-to-linux-6.10.patch @@ -0,0 +1,28 @@ +Index: source_sonic/drivers/misc/eeprom/optoe.c +=================================================================== +--- source_sonic.orig/drivers/misc/eeprom/optoe.c ++++ source_sonic/drivers/misc/eeprom/optoe.c +@@ -1016,13 +1016,13 @@ static struct attribute_group optoe_attr + .attrs = optoe_attrs, + }; + +-static int optoe_probe(struct i2c_client *client, +- const struct i2c_device_id *id) ++static int optoe_probe(struct i2c_client *client) + { + int err; + int use_smbus = 0; + struct optoe_platform_data chip; + struct optoe_data *optoe; ++ const struct i2c_device_id *id; + int num_addresses = 0; + char port_name[MAX_PORT_NAME_LEN]; + +@@ -1045,6 +1045,7 @@ static int optoe_probe(struct i2c_client + "probe, chip provided, flags:0x%x; name: %s\n", + chip.flags, client->name); + } else { ++ id = i2c_match_id(optoe_ids, client); + if (!id->driver_data) { + err = -ENODEV; + goto exit; diff --git a/patch/driver-support-optoe-write-max.patch b/patches-sonic/driver-support-optoe-write-max.patch similarity index 100% rename from patch/driver-support-optoe-write-max.patch rename to patches-sonic/driver-support-optoe-write-max.patch diff --git a/patch/driver-support-optoe-write-max_fix.patch b/patches-sonic/driver-support-optoe-write-max_fix.patch similarity index 100% rename from patch/driver-support-optoe-write-max_fix.patch rename to patches-sonic/driver-support-optoe-write-max_fix.patch diff --git a/patch/driver-support-optoe.patch b/patches-sonic/driver-support-optoe.patch similarity index 100% rename from patch/driver-support-optoe.patch rename to patches-sonic/driver-support-optoe.patch diff --git a/patch/driver-support-sff-8436-eeprom-update.patch b/patches-sonic/driver-support-sff-8436-eeprom-update.patch similarity index 95% rename from patch/driver-support-sff-8436-eeprom-update.patch rename to patches-sonic/driver-support-sff-8436-eeprom-update.patch index a17c7a8dd..1a2fcb964 100644 --- a/patch/driver-support-sff-8436-eeprom-update.patch +++ b/patches-sonic/driver-support-sff-8436-eeprom-update.patch @@ -71,7 +71,7 @@ index 0b6bf312e..f5627bf85 100644 (page ? "Upper" : "Lower"), (page ? (page-1) : page), page_offset, page_len, ret); } } -@@ -780,18 +777,15 @@ static ssize_t sff_8436_macc_write(struct memory_accessor *macc, const char *buf +@@ -780,21 +777,17 @@ static ssize_t sff_8436_macc_write(struct memory_accessor *macc, const char *buf /*-------------------------------------------------------------------------*/ @@ -89,8 +89,12 @@ index 0b6bf312e..f5627bf85 100644 kfree(sff_8436); - return 0; } - static int sff_8436_eeprom_probe(struct i2c_client *client, - const struct i2c_device_id *id) +-static int sff_8436_eeprom_probe(struct i2c_client *client, +- const struct i2c_device_id *id) ++static int sff_8436_eeprom_probe(struct i2c_client *client) + { + int err; + int use_smbus = 0; @@ -821,7 +816,6 @@ static int sff_8436_eeprom_probe(struct i2c_client *client, chip.setup = NULL; diff --git a/patch/driver-support-sff-8436-eeprom.patch b/patches-sonic/driver-support-sff-8436-eeprom.patch similarity index 100% rename from patch/driver-support-sff-8436-eeprom.patch rename to patches-sonic/driver-support-sff-8436-eeprom.patch diff --git a/patch/driver-support-sff-8436-read-write-fix.patch b/patches-sonic/driver-support-sff-8436-read-write-fix.patch similarity index 100% rename from patch/driver-support-sff-8436-read-write-fix.patch rename to patches-sonic/driver-support-sff-8436-read-write-fix.patch diff --git a/patches-sonic/kconfig-exclusions b/patches-sonic/kconfig-exclusions new file mode 100644 index 000000000..756b4ab08 --- /dev/null +++ b/patches-sonic/kconfig-exclusions @@ -0,0 +1,70 @@ +[common] +# Unset STRICT_DEVMEM according to Broadcom's requirement and for CENTEC arm64 arch +CONFIG_STRICT_DEVMEM +# Unset classid and priority network cgroups due to conflict between cgroups v1 and v2 +CONFIG_CGROUP_NET_CLASSID +CONFIG_NET_CLS_CGROUP +CONFIG_NETFILTER_XT_MATCH_CGROUP +CONFIG_CGROUP_NET_PRIO +# Unset to enable UBIFS on flash +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS +###-> mellanox_common-start +###-> mellanox_common-end +CONFIG_DRM +CONFIG_VIDEO_DEV +CONFIG_MEDIA_SUPPORT +CONFIG_MEDIA_CONTROLLER +CONFIG_DVB_CORE +CONFIG_MEDIA_TUNER +CONFIG_MEDIA_ATTACH + +[amd64] +CONFIG_AMD_MEM_ENCRYPT +# Unset X86_PAT according to Broadcom's requirement +CONFIG_X86_PAT +CONFIG_MLXSW_PCI +###-> mellanox_amd64-start +###-> mellanox_amd64-end + +[arm64] +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU + +[marvell-prestera-arm64] +CONFIG_UBIFS_FS_ZSTD +CONFIG_CRYPTO_DEV_SAFEXCEL + +[pensando] +CONFIG_ARM64_VA_BITS_48 + +[armhf] + +[marvell-prestera-armhf] +CONFIG_ARCH_VIRT +CONFIG_ARCH_BCM +CONFIG_ARCH_EXYNOS +CONFIG_ARCH_HIGHBANK +CONFIG_ARCH_MXC +CONFIG_ARCH_MESON +CONFIG_ARCH_OMAP3 +CONFIG_ARCH_OMAP4 +CONFIG_SOC_OMAP5 +CONFIG_SOC_AM33XX +CONFIG_SOC_DRA7XX +CONFIG_ARCH_ROCKCHIP +CONFIG_ARCH_SOCFPGA +CONFIG_ARCH_SUNXI +CONFIG_ARCH_TEGRA +CONFIG_ARCH_VEXPRESS +CONFIG_ARCH_WM8850 +CONFIG_FW_CFG_SYSFS +CONFIG_VORTEX +CONFIG_NTP_PPS +CONFIG_SENSORS_MAX6620 +CONFIG_SND_LX6464ES +CONFIG_EFI +CONFIG_LOCK_DOWN_KERNEL +CONFIG_SECONDARY_TRUSTED_KEYRING +CONFIG_SYSTEM_BLACKLIST_KEYRING + +[mellanox-arm64] + diff --git a/patches-sonic/kconfig-force-inclusions b/patches-sonic/kconfig-force-inclusions new file mode 100644 index 000000000..e14876637 --- /dev/null +++ b/patches-sonic/kconfig-force-inclusions @@ -0,0 +1,3 @@ +[arm64] +CONFIG_COMPAT_VDSO=y +CONFIG_THUMB2_COMPAT_VDSO=y diff --git a/patches-sonic/kconfig-inclusions b/patches-sonic/kconfig-inclusions new file mode 100644 index 000000000..4a1f36a8f --- /dev/null +++ b/patches-sonic/kconfig-inclusions @@ -0,0 +1,247 @@ +[common] +CONFIG_LOG_BUF_SHIFT=20 +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +###-> mellanox_common-start +###-> mellanox_common-end + +[amd64] +CONFIG_SATA_MOBILE_LPM_POLICY=1 +# For Arista +CONFIG_I2C_MUX_PCA9541=m +CONFIG_SENSORS_MAX6697=m +#CONFIG_SENSORS_DPS1900=m # TODO: enable once the DPS1900 patch is re-enabled +CONFIG_PCI_REASSIGN_PREF_MEM=y +# For cig-cs6436 +CONFIG_SERIAL_8250_LPSS=m +# SFF_8436 +CONFIG_EEPROM_SFF_8436=m +# For Dell S6000 +CONFIG_SENSORS_MAX6620=m +CONFIG_PMBUS=m +CONFIG_SENSORS_PMBUS=m +#CONFIG_SENSORS_DNI_DPS460=m # TODO: enable once the DPS460 patch is re-enabled +CONFIG_I2C_MUX_GPIO=m +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_SCH=m +# For Dell Z9100 +CONFIG_I2C_MUX_PCA954x=m +# For Ingrasys S9100 +CONFIG_I2C_GPIO=m +CONFIG_GPIO_PCA953X=m +# For Inventec d7032 +CONFIG_GPIO_ICH=m +# For mitac ly1200 +CONFIG_SENSORS_MAX31790=m +# For optoe +CONFIG_EEPROM_OPTOE=m +###-> mellanox_amd64-start +CONFIG_X86_AMD_PLATFORM_DEVICE=y +CONFIG_MCTP=y +CONFIG_DMI_SYSFS=y +CONFIG_OF=y +CONFIG_EEPROM_AT24=m +CONFIG_AMD_XGBE=m +CONFIG_IGB=m +CONFIG_MLXSW_CORE=m +CONFIG_SERIAL_8250_DW=y +CONFIG_HW_RANDOM_AMD=m +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MUX=m +CONFIG_I2C_SMBUS=m +CONFIG_I2C_I801=m +CONFIG_I2C_DESIGNWARE_PCI=m +CONFIG_I2C_MLXCPLD=m +CONFIG_I2C_SLAVE=y +CONFIG_PINCTRL=y +CONFIG_GPIOLIB=y +CONFIG_SENSORS_K10TEMP=m +CONFIG_SENSORS_DRIVETEMP=m +CONFIG_SENSORS_CORETEMP=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_POWR1220=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_EMC1403=m +CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_STTS751=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_TMP421=m +CONFIG_THERMAL_NETLINK=y +CONFIG_INTEL_PCH_THERMAL=m +CONFIG_WATCHDOG_SYSFS=y +CONFIG_LPC_ICH=m +CONFIG_MFD_INTEL_LPSS_PCI=y +CONFIG_LEDS_MLXREG=m +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_DW_DMAC_PCI=y +CONFIG_MELLANOX_PLATFORM=y +CONFIG_MLX_PLATFORM=m +CONFIG_NET_DEVLINK=y +CONFIG_I2C_MUX_REG=m +CONFIG_I2C_MUX_MLXCPLD=m +CONFIG_REGMAP_I2C=m +CONFIG_IIO_SYSFS_TRIGGER=m +CONFIG_NVME_HWMON=y +CONFIG_MLXSW_CORE_HWMON=y +CONFIG_MLXSW_I2C=m +CONFIG_MLXSW_MINIMAL=m +CONFIG_MLXSW_CORE_THERMAL=n +CONFIG_MLXREG_HOTPLUG=m +CONFIG_MLXREG_IO=m +CONFIG_MLX_WDT=m +CONFIG_MLXREG_LC=m +#CONFIG_MLXREG_DPU=m +CONFIG_SENSORS_MLXREG_FAN=m +CONFIG_GPIO_GENERIC=m +CONFIG_MAX1363=m +CONFIG_SENSORS_TPS53679=m +CONFIG_SENSORS_XDPE122=m +CONFIG_SENSORS_MP2975=m +#CONFIG_SENSORS_MP2855=m +CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2891=m +CONFIG_CPU_THERMAL=y +CONFIG_IGB_HWMON=y +CONFIG_MFD_CORE=y +CONFIG_MFD_INTEL_LPSS=y +CONFIG_TI_ADS1015=m +CONFIG_PINCTRL_INTEL=y +CONFIG_PINCTRL_CANNONLAKE=m +CONFIG_PINCTRL_DENVERTON=m +CONFIG_NVSW_SN2201=m +CONFIG_I2C_DESIGNWARE_PLATFORM=m +CONFIG_I2C_DESIGNWARE_BAYTRAIL=y +CONFIG_I2C_DESIGNWARE_CORE=m +CONFIG_SPI_PXA2XX=m +CONFIG_SENSORS_XDPE152=m +CONFIG_SENSORS_IIO_HWMON=m +CONFIG_SENSORS_LM25066=m +CONFIG_SENSORS_UCD9000=m +CONFIG_SENSORS_UCD9200=m +CONFIG_THERMAL_OF=y +CONFIG_MCTP_FLOWS=y +CONFIG_MCTP_TRANSPORT_I2C=m +CONFIG_I2C_SLAVE_EEPROM=m +#CONFIG_I2C_ASF=m +CONFIG_SPI_AMD=m +CONFIG_PINCTRL_AMD=y +CONFIG_EDAC_AMD64=m +CONFIG_AMD_XGBE_DCB=y +CONFIG_SENSORS_ISL68137=m +###-> mellanox_amd64-end +# For Cisco 8000 +CONFIG_PHYLIB=m +CONFIG_OF_GPIO=y +CONFIG_OF_MDIO=m +CONFIG_MDIO_BUS_MUX_GPIO=m +CONFIG_MDIO_BUS_MUX=m +CONFIG_REGMAP_MMIO=y +CONFIG_TI_TLC4541=m +CONFIG_SENSORS_LTC2978=m +CONFIG_SENSORS_LTC2945=m +CONFIG_SENSORS_TPS40422=m +CONFIG_SENSORS_ADM1275=m +CONFIG_SPI_INTEL_PLATFORM=m +CONFIG_SPI_INTEL=m +# For pensando +CONFIG_IONIC=m +# For AMD Ryzen Embedded processors +CONFIG_PCI_ENDPOINT=y +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_DW_EP=y +CONFIG_PCIE_DW_PLAT=y +CONFIG_PCIE_DW_PLAT_HOST=y +CONFIG_PCIE_DW_PLAT_EP=y +# For Micas +CONFIG_MDIO_BITBANG=m +CONFIG_MDIO_GPIO=m +CONFIG_SPI_GPIO=m +CONFIG_SENSORS_INA3221=m +# For Nokia +CONFIG_RTC_DRV_DS1307=m + +[arm64] +# For enabling SDEI +CONFIG_ARM_SDE_INTERFACE=y +# For Marvell +CONFIG_EEPROM_SFF_8436=m +CONFIG_EEPROM_OPTOE=m +CONFIG_I2C_MUX_GPIO=m +CONFIG_MTD_RAW_NAND=m +CONFIG_MTD_NAND_ECC_SW_BCH=y +CONFIG_MTD_NAND_MARVELL=m +CONFIG_SENSORS_EMC2305=m +CONFIG_PHY_MVEBU_CP110_COMPHY=y +CONFIG_SPI_ORION=m +CONFIG_ARM_SMC_WATCHDOG=m +# For pensando +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_EMBEDDED=y +CONFIG_GENERIC_IRQ_DEBUGFS=y +CONFIG_GPIO_DWAPB=m +CONFIG_IP_PNP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IRQSOFF_TRACER=y +CONFIG_KALLSYMS_ALL=y +CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y +CONFIG_SCHED_TRACER=y +CONFIG_MEMTEST=y +CONFIG_MMC_DEBUG=y +CONFIG_MMC_SDHCI_CADENCE=m +CONFIG_PMBUS=m +CONFIG_SENSORS_PMBUS=m +CONFIG_SENSORS_LTC2978=m +CONFIG_SENSORS_TPS53679=m +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_CLASS=y +CONFIG_SPI_CADENCE_QUADSPI=m +CONFIG_SPI_DESIGNWARE=m +CONFIG_SPI_DW_MMIO=m +CONFIG_SQUASHFS_DECOMP_MULTI=y +CONFIG_PREEMPTIRQ_TRACEPOINTS=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_KEXEC_FILE=y + +[marvell-prestera-arm64] + +[pensando] +CONFIG_ARCH_PENSANDO=y +CONFIG_ARCH_PENSANDO_ELBA_SOC=y +CONFIG_PENSANDO_SOC_PENFW=y +CONFIG_EDAC_ELBA=y +CONFIG_IRQ_PENSANDO=y +CONFIG_MFD_PENSANDO_ELBASR=y +CONFIG_RESET_ELBASR=y +CONFIG_UIO_PCIEMAC=m +CONFIG_UIO_PENMSI1=m +CONFIG_UIO_PENGIC=m +CONFIG_UIO_PENMSI=m +CONFIG_ARM64_VA_BITS_39=y +CONFIG_COMMON_CLK_CS2000_CP=y +CONFIG_I2C_RD1173=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_NO_HZ_FULL=y +CONFIG_RCU_NOCB_CPU=y +CONFIG_VIRT_CPU_ACCOUNTING=y +CONFIG_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_RTC_DRV_ELBA_CPLD=y + +[armhf] +CONFIG_EEPROM_SFF_8436=m +CONFIG_EEPROM_OPTOE=m +CONFIG_I2C_MUX_GPIO=m + +[marvell-prestera-armhf] +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=y + +[nvidia-bluefield] +CONFIG_MMC_DW=y +CONFIG_MMC_DW_PLTFM=y +CONFIG_MMC_DW_BLUEFIELD=y +CONFIG_EFIVAR_FS=y + +[mellanox-arm64] + diff --git a/patches-sonic/kconfig-secure-boot-exclusions b/patches-sonic/kconfig-secure-boot-exclusions new file mode 100644 index 000000000..68fb8c58f --- /dev/null +++ b/patches-sonic/kconfig-secure-boot-exclusions @@ -0,0 +1,20 @@ +[common] + +[amd64] +CONFIG_MODULE_SIG_SHA256 +# For mellanox +CONFIG_SECURITY_LOCKDOWN_LSM +CONFIG_SECURITY_LOCKDOWN_LSM_EARLY +CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE +CONFIG_LOCK_DOWN_IN_EFI_SECURE_BOOT + +[arm64] +CONFIG_MODULE_SIG_SHA256 +# For mellanox +CONFIG_SECURITY_LOCKDOWN_LSM +CONFIG_SECURITY_LOCKDOWN_LSM_EARLY +CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE +CONFIG_LOCK_DOWN_IN_EFI_SECURE_BOOT + +[armhf] + diff --git a/patches-sonic/kconfig-secure-boot-inclusions b/patches-sonic/kconfig-secure-boot-inclusions new file mode 100644 index 000000000..cfd9e900c --- /dev/null +++ b/patches-sonic/kconfig-secure-boot-inclusions @@ -0,0 +1,18 @@ +[common] + +[amd64] +CONFIG_SYSTEM_TRUSTED_KEYS="debian/certs/debian-uefi-certs.pem" +CONFIG_MODULE_SIG_HASH="sha512" +CONFIG_MODULE_SIG_SHA512=y +CONFIG_KEXEC_SIG_FORCE=y +CONFIG_MODULE_SIG_FORCE=y + +[arm64] +CONFIG_SYSTEM_TRUSTED_KEYS="debian/certs/debian-uefi-certs.pem" +CONFIG_MODULE_SIG_HASH="sha512" +CONFIG_MODULE_SIG_SHA512=y +CONFIG_KEXEC_SIG=y +CONFIG_MODULE_SIG_FORCE=y + +[armhf] + diff --git a/patch/kernel-sched-core-fix-cgroup-fork-race.patch b/patches-sonic/kernel-sched-core-fix-cgroup-fork-race.patch similarity index 100% rename from patch/kernel-sched-core-fix-cgroup-fork-race.patch rename to patches-sonic/kernel-sched-core-fix-cgroup-fork-race.patch diff --git a/patch/rtnetlink-catch-EOPNOTSUPP-errors.patch b/patches-sonic/rtnetlink-catch-EOPNOTSUPP-errors.patch similarity index 100% rename from patch/rtnetlink-catch-EOPNOTSUPP-errors.patch rename to patches-sonic/rtnetlink-catch-EOPNOTSUPP-errors.patch diff --git a/patches-sonic/series b/patches-sonic/series new file mode 100644 index 000000000..dac5959ef --- /dev/null +++ b/patches-sonic/series @@ -0,0 +1,215 @@ +# This series applies on GIT commit 18c5597832fcf6988111b05a9a1607ae148723c +# Note: Markers should start with "###->". +# Header should end with .*-start eg: any_description-start +# Footer must end with .*-end eg: any_description-end +# Markers should not be nested + +driver-arista-net-tg3-dma-mask-4g-sb800.patch +driver-arista-net-tg3-disallow-broadcom-default-mac.patch +driver-arista-net-tg3-access-regs-indirectly.patch +driver-arista-pci-reassign-pref-mem.patch +driver-arista-mmcblk-not-working-on-AMD-platforms.patch +driver-arista-restrict-eMMC-drive-to-50Mhz-from-userland.patch +driver-arista-i2c-designware-shutdown.patch +driver-support-sff-8436-eeprom.patch +driver-support-sff-8436-eeprom-update.patch +driver-sff-8436-use-nvmem-framework.patch +driver-sff-8436-use-nvmem_device_read.patch +driver-support-sff-8436-read-write-fix.patch +driver-i2c-bus-intel-ismt-add-delay-param.patch +#driver-hwmon-max6658-fix-write-convrate.patch # TODO: update for current version +#driver-hwmon-pmbus-dni_dps460.patch # TODO: build failure +#driver-hwmon-pmbus-dni_dps460-update-pmbus-core.patch # TODO: disabling for dependency +#driver-hwmon-pmbus-dni_dps460-add-status-attributes.patch # TODO: disabling for depedency +#driver-hwmon-pmbus-dps1900.patch # TODO: build failure +#driver-hwmon-pmbus-dps200.patch # TODO: disabling for dependency +driver-support-optoe.patch +driver-support-optoe-EOF_fix.patch +driver-support-optoe-chunk-offset-fix.patch +driver-support-optoe-QSFP_DD.patch +driver-support-optoe-write-max.patch +driver-support-optoe-write-max_fix.patch +driver-support-optoe-twoaddr-a2h-access.patch +driver-support-optoe-oneaddr-pageable.patch +driver-support-optoe-update-to-linux-6.1.patch +driver-support-optoe-dynamic-write-timeout.patch +driver-support-optoe-update-to-linux-6.10.patch +driver-net-tg3-add-param-short-preamble-and-reset.patch +driver-net-tg3-change-dma-mask-for-57766.patch +0004-dt-bindings-hwmon-Add-missing-documentation-for-lm75.patch +0005-dt-bindings-hwmon-Add-tmp75b-to-lm75.txt.patch +0006-device-tree-bindinds-add-NXP-PCT2075-as-compatible-d.patch +#Support-for-fullcone-nat.patch # TODO(trixie): update for current version + +# +# This series applies on GIT commit 1451b36b2b0d62178e42f648d8a18131af18f7d8 +# Tkernel-sched-core-fix-cgroup-fork-race.patch +# Tconfig-mlnx-sn2700.patch +# Tdriver-at24-fix-odd-length-two-byte-access.patch +# Tdriver-hwmon-lm75b-update.patch +# Tdriver-hwmon-pmbus-add-dps460-support.patch +# Tdriver-hwmon-pmbus-ucd9200-mlnx.patch +# Trtnetlink-catch-EOPNOTSUPP-errors.patch +# Tbridge-per-port-multicast-broadcast-flood-flags.patch +# + +0001-efi-memattr-Ignore-table-if-the-size-is-clearly-bogus.patch + +# Mellanox patches for 5.10 +# TODO(trixie): update for current version +###-> mellanox_sdk-start +0001-psample-define-the-macro-PSAMPLE_MD_EXTENDED_ATTR.patch +0002-drop_monitor-Extend-WJH-buffer-linux-channel.patch +###-> mellanox_sdk-end + +###-> mellanox_hw_mgmt-start +0001-mlxbf-bootctl-Constify-struct-bin_attribute.patch +0002-platform-mellanox-mlxbf-pmc-Add-support-for-monitori.patch +0003-platform-mellanox-mlxbf-pmc-Add-support-for-clock_me.patch +0004-platform-mellanox-mlxbf-bootctl-use-sysfs_emit-inste.patch +0005-platform-mellanox-mlxreg-hotplug-use-sysfs_emit-inst.patch +0006-platform-mellanox-mlxreg-io-use-sysfs_emit-instead-o.patch +0007-mlxbf-bootctl-Support-sysfs-entries-for-RTC-battery-.patch +0008-mlxbf-bootctl-use-sysfs_emit_at-in-secure_boot_fuse_.patch +0009-platform-mellanox-mlxbf-pmc-Support-additional-PMC-b.patch +0010-platform-mellanox-nvsw-sn2200-Fix-.items-in-nvsw_sn2.patch +0011-platform-mellanox-Fix-spelling-and-comment-clarity-i.patch +0015-i2c-mlxcpld-Support-PCIe-mapped-register-space.patch +0016-hwmon-mlxreg-fan-Add-support-for-new-flavour-of-capa.patch +0017-leds-mlxreg-Add-support-for-new-flavour-of-capabilit.patch +0018-leds-mlxreg-Remove-code-for-amber-LED-colour.patch +0019-Extend-driver-to-support-Infineon-Digital-Multi-phas.patch +0020-dt-bindings-trivial-devices-Add-infineon-xdpe1a2g7.patch +0021-leds-mlxreg-Skip-setting-LED-color-during-initializa.patch +0022-i2c-mux-Add-register-map-based-mux-driver.patch +0023-platform-mellanox-Add-support-for-dynamic-I2C-channe.patch +0024-mellanox-Relocate-mlx-platform-driver.patch +0025-platform-mellanox-mlx-platform-Cosmetic-changes.patch +0026-platform-mellanox-Rename-field-to-improve-code-reada.patch +0027-platform-mellanox-mlx-platform-Change-register-name.patch +0028-platform-mellanox-mlxreg-dpu-Add-initial-support-for.patch +0029-platform-mellanox-Introduce-support-of-Nvidia-smart-.patch +0030-hwmon-mlxreg-fan-Separate-methods-of-fan-setting-com.patch +0031-platform-mellanox-indicate-deferred-I2C-bus-creation.patch +0032-platform_data-mlxreg-Add-capability-bit-and-mask-fie.patch +0033-platform-mellanox-mlxreg-hotplug-Add-support-for-new.patch +0034-platform-mellanox-Cosmetic-changes-to-improve-code-s.patch +0035-platform-mellanox-mlx-platform-Add-support-for-new-N.patch +0036-platform-mellanox-mlxreg-dpu-Fix-smatch-warnings.patch +0037-platform-mellanox-mlxreg-io-Extend-number-of-hwmon-a.patch +0038-platform_data-mlxreg-Add-fields-for-interrupt-storm-.patch +0039-platform-mellanox-mlxreg-hotplug-Add-support-for-han.patch +0040-platform-mellanox-mlxreg-dpu-Introduce-completion-ca.patch +0041-hwmon-add-MP2869-MP29608-MP29612-and-MP29816-series-.patch +0042-hwmon-add-MP29502-driver.patch +0043-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2855-c.patch +0044-platform_data-mlxreg-Add-non-sticky-bit-indication-f.patch +0045-platform-mellanox-mlxreg-hotplug-Add-handling-of-non.patch +0046-platform-mellanox-nvsw-bmc-Add-system-control-and-mo.patch +0047-hwmon-mlxreg-fan-Prevent-fans-from-getting-stuck-at-.patch +0052-platform-mellanox-Introduce-support-for-switches-equ.patch +0053-platform-mellanox-mlx-platform-Add-support-for-new-X.patch +0054-i2c-asf-Introduce-MCTP-support-over-ASF-controller.patch +0055-platform-mellanox-Downstream-Add-support-DGX-flavor-.patch +8000-mlxsw-Use-weak-reverse-dependencies-for-firmware-fla.patch +8001-platform-mlx-platform-Downstream-Add-SPI-path-for-ra.patch +8002-mlxsw-i2c-SONIC-ISSU-Prevent-transaction-execution-f.patch +8003-mlxsw-minimal-Downstream-Ignore-error-reading-SPAD-r.patch +8004-leds-leds-mlxreg-Downstream-Send-udev-event-from-led.patch +8005-i2c-mlxcpld-Downstream-WA-to-avoid-error-for-SMBUS-r.patch +8006-hwmon-mlxreg-fan-Downstream-Allow-fan-speed-setting-.patch +8007-hwmon-emc2305-Downstream-Allow-fan-speed-setting-gra.patch +8008-hwmon-mlxsw-Downstream-Allow-fan-speed-setting-granu.patch +8009-mlxsw-i2c-Downstream-Add-retry-mechanism-for-failed-.patch +8010-mlxsw-minimal-Downstream-Disable-ethtool-interface.patch +8011-hwmon-pmbus-Downstream-Workaround-for-psu-attributes.patch +8013-hwmon-pmbus-mp2975-Clear-interrupts-at-probe.patch +8014-platform-mellanox-mlxreg-dpu-Debug-trace-for-dpu-pro.patch +9000-platform-mellanox-Downstream-Add-support-for-new-Nvi.patch +###-> mellanox_hw_mgmt-end + +# Cisco patches for 5.10 kernel +cisco-mtd-part.patch +cisco-mdio-mux-support-acpi.patch +#cisco-x86-gpio-config.patch # Deprecated, GPIOs are effectively unlimited +cisco-acpi-spi-nor.patch +cisco-Enable-static-memory-reservation-for-OIRable-PCIe-de.patch +cisco-npu-disable-other-bars.patch +#cisco-hwmon-pmbus_core-pec-support-check.patch # Upstreamed + +# Nokia patches for 5.10 kernel +#0001-hwmon-emc2305-Fix-unable-to-probe-emc2301-2-3.patch # Upstreamed + +# +# Marvell platform patches for 6.1 kernel +0001-armhf_secondary_boot_online.patch +#0002-arm64-dts-Update-cache-properties-for-marvell.patch # Upstreamed +#0003-arm64-dts-marvell-Add-NAND-flash-controller-to-AC5.patch # Upstreamed +#0004-arm64-dts-ac5-add-mmc-node-and-clock.patch # Upstreamed +0005-dts-ac5-marvell-Add-switching-watchdog-node.patch +#0006-mmc-xenon-Add-ac5-support-via-bounce-buffer.patch # Upstreamed +#0007-usb-ehci-Add-support-for-ac5.patch # Upstreamed but no 64-bit, so the next 0007 +0007-usb-ehci-Add-support-for-ac5-with-DMA-mask-64-bit.patch +0008-mv6xxx-Fix-i2c-lock-due-to-arb-loss.patch +0009-dt-bindings-marvell-Add-ARMADA-7K-properties.patch +0010-dts-marvell-Add-support-for-7020-comexpress.patch +0011-arm64-dts-marvell-Add-Nokia-7215-IXS-A1-board.patch +0015-arm64-dts-marvell-Add-Supermicro-SSE-G3748-board.patch +0016-arm64-dts-marvell-Add-Wistron-ES-1227-54TS-board.patch +0017-Extend-driver-to-support-XMC-XM25QH256C-device.patch +0018-drivers-i2c-fix-after-kdump-crash.patch +0019-irqchip-mvebu-gicp-Clear-pending-interrupts-on-init.patch +0022-arm64-dts-marvell-Add-DTS-for-cn9131-db-comexpress-trixie.patch + +# amd-pensando elba support +# TODO(trixie): update for current version +#0000-Add-support-for-the-TI-TPS53659.patch +#0001-Adding-support-LTC3888.patch +#0002-i2c-designware-Support-stuck-SDA-line-recovery.patch +#0003-i2c-Add-Lattice-RD1173-I2C-controller-driver.patch +#0004-arm64-traps-Call-platform-handler-for-do_serror.patch +#0005-add-quirks-for-the-Pensando-controller.patch +#0006-Pensando-Elba-support-in-the-Cadence-EMMC-host-contr.patch +#0007-spi-dw-Support-Pensando-Elba-custom-chip-select.patch +#0008-Initial-support-for-the-Pensando-Elba-SoC.patch +#0009-drivers-reset-Add-emmc-hardware-reset.patch +#0010-dts-pensnado-Elba-flash-partitions.patch +#0011-drivers-edac-Add-Elba-EDAC-support.patch +#0012-drivers-soc-pensando-dev-capmem-driver.patch +#0013-Interrupt-domain-controllers-for-Elba-ASIC.patch +#0014-drivers-uio-UIO-drivers-for-Elba.patch +#0015-drivers-pensando-soc-Boot-State-Machine-integrtion.patch +#0016-drivers-soc-pensando-crash-dump-driver.patch +#0017-drivers-soc-pensando-Add-the-Reset-Cause-driver.patch +#0018-soc-pensando-pcie-driver.patch +#0019-drivers-soc-pensando-kpcimgr-driver.patch +#0020-dts-pensando-add-mnet-and-mcrypt-devices.patch +#0021-drivers-soc-pensando-sbus-driver.patch +#0022-drivers-soc-pensando-boot_count-to-sysfs-for-kdump.patch +#0023-arch-arm64-boot-dts-psci-support.patch +#0024-drivers-soc-pensando-penfw-driver.patch +#0025-dts-changes-for-mtfuji-and-lipari.patch +#0026-Add-support-for-new-qspi-macronix-flash-mx66u1g45g.patch +#0027-pensando-add-rtc-cpld.patch +#0028-Create-miniaturised-diafgw-partition-for-128MB-flash.patch +#0029-pcie-if-hotplug-enabled-do-immediate-reset-on-panic.patch + +# Security patch +#0001-Change-the-system.map-file-permission-only-readable-.patch + +# Micas patches +0001-fix-os-crash-caused-by-optoe-when-class-switch.patch +0001-tty-8250-HSUART-DMA-be-deactivated-for-DNV-CPU.patch + +# Fix to avoid kernel panic on Kernel 6.1.94 +# https://github.com/sonic-net/sonic-buildimage/issues/20901 +#PCI-ASPM-Fix-link-state-exit-during-switch-upstream.patch # Upstreamed + +# +# +############################################################ +# +# Internal patches will be added below (placeholder) +# Do not add any public patch below this marker +# +############################################################ From b4516399fdfef0c570da7b06d2b374c7cab4e271 Mon Sep 17 00:00:00 2001 From: jamessewart-arista <173153856+jamessewart-arista@users.noreply.github.com> Date: Wed, 3 Dec 2025 17:30:23 +0000 Subject: [PATCH 13/16] PCIe AER printk ratelimiting backport (#520) Signed-off-by: James Sewart --- .../0001-PCI-AER-Simplify-pci_print_aer.patch | 78 +++++ ...pdate-statistics-before-ratelimiting.patch | 68 +++++ ...race-error-event-before-ratelimiting.patch | 69 +++++ ...04-PCI-AER-Simplify-add_error_device.patch | 49 ++++ ...Check-log-level-once-and-remember-it.patch | 128 +++++++++ ...aer_get_device_error_info-aer_print_.patch | 150 ++++++++++ ...OR-UNCOR-error-handling-out-from-aer.patch | 104 +++++++ ...t-correctable-and-non-fatal-error-lo.patch | 221 ++++++++++++++ ...-sysfs-attributes-for-log-ratelimits.patch | 272 ++++++++++++++++++ ...-aer-ratelimiting-sysfs-output-units.patch | 34 +++ ...-Fix-NULL-pointer-access-by-aer_info.patch | 36 +++ ...LL-pointer-dereference-in-aer_rateli.patch | 61 ++++ patches-sonic/series | 14 + 13 files changed, 1284 insertions(+) create mode 100644 patches-sonic/0001-PCI-AER-Simplify-pci_print_aer.patch create mode 100644 patches-sonic/0002-PCI-AER-Update-statistics-before-ratelimiting.patch create mode 100644 patches-sonic/0003-PCI-AER-Trace-error-event-before-ratelimiting.patch create mode 100644 patches-sonic/0004-PCI-AER-Simplify-add_error_device.patch create mode 100644 patches-sonic/0005-PCI-AER-Check-log-level-once-and-remember-it.patch create mode 100644 patches-sonic/0006-PCI-AER-Convert-aer_get_device_error_info-aer_print_.patch create mode 100644 patches-sonic/0007-PCI-AER-Factor-COR-UNCOR-error-handling-out-from-aer.patch create mode 100644 patches-sonic/0008-PCI-AER-Ratelimit-correctable-and-non-fatal-error-lo.patch create mode 100644 patches-sonic/0009-PCI-AER-Add-sysfs-attributes-for-log-ratelimits.patch create mode 100644 patches-sonic/0010-fix-aer-ratelimiting-sysfs-output-units.patch create mode 100644 patches-sonic/0011-PCI-AER-Fix-NULL-pointer-access-by-aer_info.patch create mode 100644 patches-sonic/0012-PCI-AER-Avoid-NULL-pointer-dereference-in-aer_rateli.patch diff --git a/patches-sonic/0001-PCI-AER-Simplify-pci_print_aer.patch b/patches-sonic/0001-PCI-AER-Simplify-pci_print_aer.patch new file mode 100644 index 000000000..0a7a17357 --- /dev/null +++ b/patches-sonic/0001-PCI-AER-Simplify-pci_print_aer.patch @@ -0,0 +1,78 @@ +From 642a9f17e1bce39ecc639ed1e6f959edcd039aef Mon Sep 17 00:00:00 2001 +From: Bjorn Helgaas +Date: Thu, 22 May 2025 18:21:15 -0500 +Subject: [PATCH 01/12] PCI/AER: Simplify pci_print_aer() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Simplify pci_print_aer() by initializing the struct aer_err_info "info" +with a designated initializer list (it was previously initialized with +memset()) and using pci_name(). + +Signed-off-by: Bjorn Helgaas +Tested-by: Krzysztof Wilczyński +Reviewed-by: Ilpo Järvinen +Reviewed-by: Jonathan Cameron +Reviewed-by: Kuppuswamy Sathyanarayanan +Link: https://patch.msgid.link/20250522232339.1525671-10-helgaas@kernel.org +(cherry picked from commit ad9839137cf9fb0f0c2d531bd04bc4382e6f2de9) +--- + drivers/pci/pcie/aer.c | 18 +++++++++--------- + 1 file changed, 9 insertions(+), 9 deletions(-) + +diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c +index 13b8586924ea..7d7fc4a9fec2 100644 +--- a/drivers/pci/pcie/aer.c ++++ b/drivers/pci/pcie/aer.c +@@ -730,7 +730,7 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) + if (info->id && info->error_dev_num > 1 && info->id == id) + pci_err(dev, " Error of this Agent is reported first\n"); + +- trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask), ++ trace_aer_event(pci_name(dev), (info->status & ~info->mask), + info->severity, info->tlp_header_valid, &info->tlp); + } + +@@ -766,7 +766,10 @@ void pci_print_aer(struct pci_dev *dev, int aer_severity, + { + int layer, agent, tlp_header_valid = 0; + u32 status, mask; +- struct aer_err_info info; ++ struct aer_err_info info = { ++ .severity = aer_severity, ++ .first_error = PCI_ERR_CAP_FEP(aer->cap_control), ++ }; + + if (aer_severity == AER_CORRECTABLE) { + status = aer->cor_status; +@@ -777,14 +780,11 @@ void pci_print_aer(struct pci_dev *dev, int aer_severity, + tlp_header_valid = status & AER_LOG_TLP_MASKS; + } + +- layer = AER_GET_LAYER_ERROR(aer_severity, status); +- agent = AER_GET_AGENT(aer_severity, status); +- +- memset(&info, 0, sizeof(info)); +- info.severity = aer_severity; + info.status = status; + info.mask = mask; +- info.first_error = PCI_ERR_CAP_FEP(aer->cap_control); ++ ++ layer = AER_GET_LAYER_ERROR(aer_severity, status); ++ agent = AER_GET_AGENT(aer_severity, status); + + pci_err(dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask); + __aer_print_error(dev, &info); +@@ -798,7 +798,7 @@ void pci_print_aer(struct pci_dev *dev, int aer_severity, + if (tlp_header_valid) + __print_tlp_header(dev, &aer->header_log); + +- trace_aer_event(dev_name(&dev->dev), (status & ~mask), ++ trace_aer_event(pci_name(dev), (status & ~mask), + aer_severity, tlp_header_valid, &aer->header_log); + } + EXPORT_SYMBOL_NS_GPL(pci_print_aer, CXL); +-- +2.47.0 + diff --git a/patches-sonic/0002-PCI-AER-Update-statistics-before-ratelimiting.patch b/patches-sonic/0002-PCI-AER-Update-statistics-before-ratelimiting.patch new file mode 100644 index 000000000..262800624 --- /dev/null +++ b/patches-sonic/0002-PCI-AER-Update-statistics-before-ratelimiting.patch @@ -0,0 +1,68 @@ +From dfcd0e7d5008dffb55517a8207d455cab69dc70c Mon Sep 17 00:00:00 2001 +From: Bjorn Helgaas +Date: Thu, 22 May 2025 18:21:16 -0500 +Subject: [PATCH 02/12] PCI/AER: Update statistics before ratelimiting +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +There are two AER logging entry points: + + - aer_print_error() is used by DPC (dpc_process_error()) and native AER + handling (aer_process_err_devices()). + + - pci_print_aer() is used by GHES (aer_recover_work_func()) and CXL + (cxl_handle_rdport_errors()) + +Both use __aer_print_error() to print the AER error bits. Previously +__aer_print_error() also incremented the AER statistics via +pci_dev_aer_stats_incr(). + +Call pci_dev_aer_stats_incr() early in the entry points instead of in +__aer_print_error() so we update the statistics even if the actual printing +of error bits is rate limited by a future change. + +Signed-off-by: Bjorn Helgaas +Tested-by: Krzysztof Wilczyński +Reviewed-by: Ilpo Järvinen +Reviewed-by: Kuppuswamy Sathyanarayanan +Reviewed-by: Jonathan Cameron +Link: https://patch.msgid.link/20250522232339.1525671-11-helgaas@kernel.org +(cherry picked from commit 88a7765e62b9e4c79c7ca2c7b749ae04f54a5668) +--- + drivers/pci/pcie/aer.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c +index 7d7fc4a9fec2..48a33151d145 100644 +--- a/drivers/pci/pcie/aer.c ++++ b/drivers/pci/pcie/aer.c +@@ -694,7 +694,6 @@ static void __aer_print_error(struct pci_dev *dev, + pci_printk(level, dev, " [%2d] %-22s%s\n", i, errmsg, + info->first_error == i ? " (First)" : ""); + } +- pci_dev_aer_stats_incr(dev, info); + } + + void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) +@@ -703,6 +702,8 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) + int id = pci_dev_id(dev); + const char *level; + ++ pci_dev_aer_stats_incr(dev, info); ++ + if (!info->status) { + pci_err(dev, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n", + aer_error_severity_string[info->severity]); +@@ -783,6 +784,8 @@ void pci_print_aer(struct pci_dev *dev, int aer_severity, + info.status = status; + info.mask = mask; + ++ pci_dev_aer_stats_incr(dev, &info); ++ + layer = AER_GET_LAYER_ERROR(aer_severity, status); + agent = AER_GET_AGENT(aer_severity, status); + +-- +2.47.0 + diff --git a/patches-sonic/0003-PCI-AER-Trace-error-event-before-ratelimiting.patch b/patches-sonic/0003-PCI-AER-Trace-error-event-before-ratelimiting.patch new file mode 100644 index 000000000..eccb87deb --- /dev/null +++ b/patches-sonic/0003-PCI-AER-Trace-error-event-before-ratelimiting.patch @@ -0,0 +1,69 @@ +From b6cbde42bc2406d734511a7b28499f9fda4fd91c Mon Sep 17 00:00:00 2001 +From: Bjorn Helgaas +Date: Thu, 22 May 2025 18:21:17 -0500 +Subject: [PATCH 03/12] PCI/AER: Trace error event before ratelimiting +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +As with the AER statistics, we always want to emit trace events, even if +the actual dmesg logging is rate limited. + +Call trace_aer_event() immediately after pci_dev_aer_stats_incr() so both +happen before ratelimiting. + +Signed-off-by: Bjorn Helgaas +Tested-by: Krzysztof Wilczyński +Reviewed-by: Ilpo Järvinen +Reviewed-by: Kuppuswamy Sathyanarayanan +Link: https://patch.msgid.link/20250522232339.1525671-12-helgaas@kernel.org +(cherry picked from commit 6bb4befbd65fa7f99688fb707e376637e5acfe36) +--- + drivers/pci/pcie/aer.c | 10 ++++------ + 1 file changed, 4 insertions(+), 6 deletions(-) + +diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c +index 48a33151d145..6fc993d05647 100644 +--- a/drivers/pci/pcie/aer.c ++++ b/drivers/pci/pcie/aer.c +@@ -703,6 +703,8 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) + const char *level; + + pci_dev_aer_stats_incr(dev, info); ++ trace_aer_event(pci_name(dev), (info->status & ~info->mask), ++ info->severity, info->tlp_header_valid, &info->tlp); + + if (!info->status) { + pci_err(dev, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n", +@@ -730,9 +732,6 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) + out: + if (info->id && info->error_dev_num > 1 && info->id == id) + pci_err(dev, " Error of this Agent is reported first\n"); +- +- trace_aer_event(pci_name(dev), (info->status & ~info->mask), +- info->severity, info->tlp_header_valid, &info->tlp); + } + + static void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info) +@@ -785,6 +784,8 @@ void pci_print_aer(struct pci_dev *dev, int aer_severity, + info.mask = mask; + + pci_dev_aer_stats_incr(dev, &info); ++ trace_aer_event(pci_name(dev), (status & ~mask), ++ aer_severity, tlp_header_valid, &aer->header_log); + + layer = AER_GET_LAYER_ERROR(aer_severity, status); + agent = AER_GET_AGENT(aer_severity, status); +@@ -800,9 +801,6 @@ void pci_print_aer(struct pci_dev *dev, int aer_severity, + + if (tlp_header_valid) + __print_tlp_header(dev, &aer->header_log); +- +- trace_aer_event(pci_name(dev), (status & ~mask), +- aer_severity, tlp_header_valid, &aer->header_log); + } + EXPORT_SYMBOL_NS_GPL(pci_print_aer, CXL); + +-- +2.47.0 + diff --git a/patches-sonic/0004-PCI-AER-Simplify-add_error_device.patch b/patches-sonic/0004-PCI-AER-Simplify-add_error_device.patch new file mode 100644 index 000000000..b1eeb2357 --- /dev/null +++ b/patches-sonic/0004-PCI-AER-Simplify-add_error_device.patch @@ -0,0 +1,49 @@ +From 824b8af8cc8d81ef95d020dcfcd4338249f1f7de Mon Sep 17 00:00:00 2001 +From: Bjorn Helgaas +Date: Thu, 22 May 2025 18:21:23 -0500 +Subject: [PATCH 04/12] PCI/AER: Simplify add_error_device() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Return -ENOSPC error early so the usual path through add_error_device() is +the straightline code. + +Signed-off-by: Bjorn Helgaas +Reviewed-by: Ilpo Järvinen +Reviewed-by: Kuppuswamy Sathyanarayanan +Link: https://patch.msgid.link/20250522232339.1525671-18-helgaas@kernel.org +(cherry picked from commit d72bae423004aa7b4d94c34a7fd0b48b64305a08) +--- + drivers/pci/pcie/aer.c | 15 +++++++++------ + 1 file changed, 9 insertions(+), 6 deletions(-) + +diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c +index 6fc993d05647..a10a005ca6e9 100644 +--- a/drivers/pci/pcie/aer.c ++++ b/drivers/pci/pcie/aer.c +@@ -811,12 +811,15 @@ EXPORT_SYMBOL_NS_GPL(pci_print_aer, CXL); + */ + static int add_error_device(struct aer_err_info *e_info, struct pci_dev *dev) + { +- if (e_info->error_dev_num < AER_MAX_MULTI_ERR_DEVICES) { +- e_info->dev[e_info->error_dev_num] = pci_dev_get(dev); +- e_info->error_dev_num++; +- return 0; +- } +- return -ENOSPC; ++ int i = e_info->error_dev_num; ++ ++ if (i >= AER_MAX_MULTI_ERR_DEVICES) ++ return -ENOSPC; ++ ++ e_info->dev[i] = pci_dev_get(dev); ++ e_info->error_dev_num++; ++ ++ return 0; + } + + /** +-- +2.47.0 + diff --git a/patches-sonic/0005-PCI-AER-Check-log-level-once-and-remember-it.patch b/patches-sonic/0005-PCI-AER-Check-log-level-once-and-remember-it.patch new file mode 100644 index 000000000..4d5dec043 --- /dev/null +++ b/patches-sonic/0005-PCI-AER-Check-log-level-once-and-remember-it.patch @@ -0,0 +1,128 @@ +From 4355136d6587aa7ce7729aa8f35f898993c5f8a4 Mon Sep 17 00:00:00 2001 +From: Karolina Stolarek +Date: Thu, 22 May 2025 18:21:18 -0500 +Subject: [PATCH 05/12] PCI/AER: Check log level once and remember it +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +When reporting an AER error, we check its type multiple times to determine +the log level for each message. Do this check only in the top-level +functions (aer_isr_one_error(), pci_print_aer()) and save the level in +struct aer_err_info. + +[bhelgaas: save log level in struct aer_err_info instead of passing it +as a parameter] + +Signed-off-by: Karolina Stolarek +Signed-off-by: Bjorn Helgaas +Tested-by: Krzysztof Wilczyński +Reviewed-by: Ilpo Järvinen +Reviewed-by: Kuppuswamy Sathyanarayanan +Reviewed-by: Jonathan Cameron +Link: https://patch.msgid.link/20250522232339.1525671-13-helgaas@kernel.org +(cherry picked from commit c8f6791e33a7757025285db26f3b382cdcb7f7cd) +--- + drivers/pci/pci.h | 1 + + drivers/pci/pcie/aer.c | 18 +++++++++--------- + drivers/pci/pcie/dpc.c | 1 + + 3 files changed, 11 insertions(+), 9 deletions(-) + +diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h +index 65df6d2ac003..ce78241b6302 100644 +--- a/drivers/pci/pci.h ++++ b/drivers/pci/pci.h +@@ -505,6 +505,7 @@ static inline bool pci_dev_is_added(const struct pci_dev *dev) + struct aer_err_info { + struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; + int error_dev_num; ++ const char *level; /* printk level */ + + unsigned int id:16; + +diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c +index a10a005ca6e9..82acb7580fd4 100644 +--- a/drivers/pci/pcie/aer.c ++++ b/drivers/pci/pcie/aer.c +@@ -675,16 +675,14 @@ static void __aer_print_error(struct pci_dev *dev, + { + const char **strings; + unsigned long status = info->status & ~info->mask; +- const char *level, *errmsg; ++ const char *level = info->level; ++ const char *errmsg; + int i; + +- if (info->severity == AER_CORRECTABLE) { ++ if (info->severity == AER_CORRECTABLE) + strings = aer_correctable_error_string; +- level = KERN_WARNING; +- } else { ++ else + strings = aer_uncorrectable_error_string; +- level = KERN_ERR; +- } + + for_each_set_bit(i, &status, 32) { + errmsg = strings[i]; +@@ -700,7 +698,7 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) + { + int layer, agent; + int id = pci_dev_id(dev); +- const char *level; ++ const char *level = info->level; + + pci_dev_aer_stats_incr(dev, info); + trace_aer_event(pci_name(dev), (info->status & ~info->mask), +@@ -715,8 +713,6 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) + layer = AER_GET_LAYER_ERROR(info->severity, info->status); + agent = AER_GET_AGENT(info->severity, info->status); + +- level = (info->severity == AER_CORRECTABLE) ? KERN_WARNING : KERN_ERR; +- + pci_printk(level, dev, "PCIe Bus Error: severity=%s, type=%s, (%s)\n", + aer_error_severity_string[info->severity], + aer_error_layer[layer], aer_agent_string[agent]); +@@ -774,9 +770,11 @@ void pci_print_aer(struct pci_dev *dev, int aer_severity, + if (aer_severity == AER_CORRECTABLE) { + status = aer->cor_status; + mask = aer->cor_mask; ++ info.level = KERN_WARNING; + } else { + status = aer->uncor_status; + mask = aer->uncor_mask; ++ info.level = KERN_ERR; + tlp_header_valid = status & AER_LOG_TLP_MASKS; + } + +@@ -1291,6 +1289,7 @@ static void aer_isr_one_error(struct aer_rpc *rpc, + if (e_src->status & PCI_ERR_ROOT_COR_RCV) { + e_info.id = ERR_COR_ID(e_src->id); + e_info.severity = AER_CORRECTABLE; ++ e_info.level = KERN_WARNING; + + if (e_src->status & PCI_ERR_ROOT_MULTI_COR_RCV) + e_info.multi_error_valid = 1; +@@ -1304,6 +1303,7 @@ static void aer_isr_one_error(struct aer_rpc *rpc, + + if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) { + e_info.id = ERR_UNCOR_ID(e_src->id); ++ e_info.level = KERN_ERR; + + if (e_src->status & PCI_ERR_ROOT_FATAL_RCV) + e_info.severity = AER_FATAL; +diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c +index cdc54315d879..d830696dccec 100644 +--- a/drivers/pci/pcie/dpc.c ++++ b/drivers/pci/pcie/dpc.c +@@ -254,6 +254,7 @@ static int dpc_get_aer_uncorrect_severity(struct pci_dev *dev, + else + info->severity = AER_NONFATAL; + ++ info->level = KERN_ERR; + return 1; + } + +-- +2.47.0 + diff --git a/patches-sonic/0006-PCI-AER-Convert-aer_get_device_error_info-aer_print_.patch b/patches-sonic/0006-PCI-AER-Convert-aer_get_device_error_info-aer_print_.patch new file mode 100644 index 000000000..9b28ef3a7 --- /dev/null +++ b/patches-sonic/0006-PCI-AER-Convert-aer_get_device_error_info-aer_print_.patch @@ -0,0 +1,150 @@ +From a53102a3566e6a29bcd447334791e5515c1e92a3 Mon Sep 17 00:00:00 2001 +From: Bjorn Helgaas +Date: Thu, 22 May 2025 18:21:22 -0500 +Subject: [PATCH 06/12] PCI/AER: Convert aer_get_device_error_info(), + aer_print_error() to index +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Previously aer_get_device_error_info() and aer_print_error() took a pointer +to struct aer_err_info and a pointer to a pci_dev. Typically the pci_dev +was one of the elements of the aer_err_info.dev[] array (DPC was an +exception, where the dev[] array was unused). + +Convert aer_get_device_error_info() and aer_print_error() to take an index +into the aer_err_info.dev[] array instead. A future patch will add +per-device ratelimit information, so the index makes it convenient to find +the ratelimit associated with the device. + +To accommodate DPC, set info->dev[0] to the DPC port before using these +interfaces. + +Signed-off-by: Bjorn Helgaas +Reviewed-by: Ilpo Järvinen +Reviewed-by: Kuppuswamy Sathyanarayanan +Link: https://patch.msgid.link/20250522232339.1525671-17-helgaas@kernel.org +(cherry picked from commit 94bc15c3484aa1dbbd01aee8f9eaa5dc347a01a8) +--- + drivers/pci/pci.h | 5 +++-- + drivers/pci/pcie/aer.c | 33 +++++++++++++++++++++++---------- + drivers/pci/pcie/dpc.c | 8 ++++++-- + 3 files changed, 32 insertions(+), 14 deletions(-) + +diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h +index ce78241b6302..4f64f3f9cdf5 100644 +--- a/drivers/pci/pci.h ++++ b/drivers/pci/pci.h +@@ -522,8 +522,9 @@ struct aer_err_info { + struct pcie_tlp_log tlp; /* TLP Header */ + }; + +-int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); +-void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); ++int aer_get_device_error_info(struct aer_err_info *info, int i); ++void aer_print_error(struct aer_err_info *info, int i); ++ + #endif /* CONFIG_PCIEAER */ + + #ifdef CONFIG_PCIEPORTBUS +diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c +index 82acb7580fd4..94cdf2e0d329 100644 +--- a/drivers/pci/pcie/aer.c ++++ b/drivers/pci/pcie/aer.c +@@ -694,12 +694,18 @@ static void __aer_print_error(struct pci_dev *dev, + } + } + +-void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) ++void aer_print_error(struct aer_err_info *info, int i) + { +- int layer, agent; +- int id = pci_dev_id(dev); ++ struct pci_dev *dev; ++ int layer, agent, id; + const char *level = info->level; + ++ if (WARN_ON_ONCE(i >= AER_MAX_MULTI_ERR_DEVICES)) ++ return; ++ ++ dev = info->dev[i]; ++ id = pci_dev_id(dev); ++ + pci_dev_aer_stats_incr(dev, info); + trace_aer_event(pci_name(dev), (info->status & ~info->mask), + info->severity, info->tlp_header_valid, &info->tlp); +@@ -1200,19 +1206,26 @@ EXPORT_SYMBOL_GPL(aer_recover_queue); + + /** + * aer_get_device_error_info - read error status from dev and store it to info +- * @dev: pointer to the device expected to have a error record + * @info: pointer to structure to store the error record ++ * @i: index into info->dev[] + * + * Return 1 on success, 0 on error. + * + * Note that @info is reused among all error devices. Clear fields properly. + */ +-int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info) ++int aer_get_device_error_info(struct aer_err_info *info, int i) + { +- int type = pci_pcie_type(dev); +- int aer = dev->aer_cap; ++ struct pci_dev *dev; ++ int type, aer; + u32 aercc; + ++ if (i >= AER_MAX_MULTI_ERR_DEVICES) ++ return 0; ++ ++ dev = info->dev[i]; ++ aer = dev->aer_cap; ++ type = pci_pcie_type(dev); ++ + /* Must reset in this function */ + info->status = 0; + info->tlp_header_valid = 0; +@@ -1260,11 +1273,11 @@ static inline void aer_process_err_devices(struct aer_err_info *e_info) + + /* Report all before handle them, not to lost records by reset etc. */ + for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) { +- if (aer_get_device_error_info(e_info->dev[i], e_info)) +- aer_print_error(e_info->dev[i], e_info); ++ if (aer_get_device_error_info(e_info, i)) ++ aer_print_error(e_info, i); + } + for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) { +- if (aer_get_device_error_info(e_info->dev[i], e_info)) ++ if (aer_get_device_error_info(e_info, i)) + handle_error_source(e_info->dev[i], e_info); + } + } +diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c +index d830696dccec..2f147cdf298d 100644 +--- a/drivers/pci/pcie/dpc.c ++++ b/drivers/pci/pcie/dpc.c +@@ -255,6 +255,10 @@ static int dpc_get_aer_uncorrect_severity(struct pci_dev *dev, + info->severity = AER_NONFATAL; + + info->level = KERN_ERR; ++ ++ info->dev[0] = dev; ++ info->error_dev_num = 1; ++ + return 1; + } + +@@ -272,8 +276,8 @@ void dpc_process_error(struct pci_dev *pdev) + pci_warn(pdev, "containment event, status:%#06x: unmasked uncorrectable error detected\n", + status); + if (dpc_get_aer_uncorrect_severity(pdev, &info) && +- aer_get_device_error_info(pdev, &info)) { +- aer_print_error(pdev, &info); ++ aer_get_device_error_info(&info, 0)) { ++ aer_print_error(&info, 0); + pci_aer_clear_nonfatal_status(pdev); + pci_aer_clear_fatal_status(pdev); + } +-- +2.47.0 + diff --git a/patches-sonic/0007-PCI-AER-Factor-COR-UNCOR-error-handling-out-from-aer.patch b/patches-sonic/0007-PCI-AER-Factor-COR-UNCOR-error-handling-out-from-aer.patch new file mode 100644 index 000000000..780e460b6 --- /dev/null +++ b/patches-sonic/0007-PCI-AER-Factor-COR-UNCOR-error-handling-out-from-aer.patch @@ -0,0 +1,104 @@ +From 10d088c074f57db7579af27da91cf0f040215b05 Mon Sep 17 00:00:00 2001 +From: Bjorn Helgaas +Date: Thu, 22 May 2025 18:21:09 -0500 +Subject: [PATCH 07/12] PCI/AER: Factor COR/UNCOR error handling out from + aer_isr_one_error() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +aer_isr_one_error() duplicates the Error Source ID logging and AER error +processing for Correctable Errors and Uncorrectable Errors. Factor out the +duplicated code to aer_isr_one_error_type(). + +aer_isr_one_error() doesn't need the struct aer_rpc pointer, so pass it the +Root Port or RCEC pci_dev pointer instead. + +Signed-off-by: Bjorn Helgaas +Reviewed-by: Ilpo Järvinen +Reviewed-by: Jonathan Cameron +Reviewed-by: Kuppuswamy Sathyanarayanan +Link: https://patch.msgid.link/20250522232339.1525671-4-helgaas@kernel.org +(cherry picked from commit 6fc4dae74afcf29ef82afbaaa9b082893871eda4) +--- + drivers/pci/pcie/aer.c | 36 +++++++++++++++++++++++------------- + 1 file changed, 23 insertions(+), 13 deletions(-) + +diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c +index 94cdf2e0d329..6ec628965cce 100644 +--- a/drivers/pci/pcie/aer.c ++++ b/drivers/pci/pcie/aer.c +@@ -1283,17 +1283,32 @@ static inline void aer_process_err_devices(struct aer_err_info *e_info) + } + + /** +- * aer_isr_one_error - consume an error detected by root port +- * @rpc: pointer to the root port which holds an error ++ * aer_isr_one_error_type - consume a Correctable or Uncorrectable Error ++ * detected by Root Port or RCEC ++ * @root: pointer to Root Port or RCEC that signaled AER interrupt ++ * @info: pointer to AER error info ++ */ ++static void aer_isr_one_error_type(struct pci_dev *root, ++ struct aer_err_info *info) ++{ ++ aer_print_port_info(root, info); ++ ++ if (find_source_device(root, info)) ++ aer_process_err_devices(info); ++} ++ ++/** ++ * aer_isr_one_error - consume error(s) signaled by an AER interrupt from ++ * Root Port or RCEC ++ * @root: pointer to Root Port or RCEC that signaled AER interrupt + * @e_src: pointer to an error source + */ +-static void aer_isr_one_error(struct aer_rpc *rpc, ++static void aer_isr_one_error(struct pci_dev *root, + struct aer_err_source *e_src) + { +- struct pci_dev *pdev = rpc->rpd; + struct aer_err_info e_info; + +- pci_rootport_aer_stats_incr(pdev, e_src); ++ pci_rootport_aer_stats_incr(root, e_src); + + /* + * There is a possibility that both correctable error and +@@ -1308,10 +1323,8 @@ static void aer_isr_one_error(struct aer_rpc *rpc, + e_info.multi_error_valid = 1; + else + e_info.multi_error_valid = 0; +- aer_print_port_info(pdev, &e_info); + +- if (find_source_device(pdev, &e_info)) +- aer_process_err_devices(&e_info); ++ aer_isr_one_error_type(root, &e_info); + } + + if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) { +@@ -1328,10 +1341,7 @@ static void aer_isr_one_error(struct aer_rpc *rpc, + else + e_info.multi_error_valid = 0; + +- aer_print_port_info(pdev, &e_info); +- +- if (find_source_device(pdev, &e_info)) +- aer_process_err_devices(&e_info); ++ aer_isr_one_error_type(root, &e_info); + } + } + +@@ -1352,7 +1362,7 @@ static irqreturn_t aer_isr(int irq, void *context) + return IRQ_NONE; + + while (kfifo_get(&rpc->aer_fifo, &e_src)) +- aer_isr_one_error(rpc, &e_src); ++ aer_isr_one_error(rpc->rpd, &e_src); + return IRQ_HANDLED; + } + +-- +2.47.0 + diff --git a/patches-sonic/0008-PCI-AER-Ratelimit-correctable-and-non-fatal-error-lo.patch b/patches-sonic/0008-PCI-AER-Ratelimit-correctable-and-non-fatal-error-lo.patch new file mode 100644 index 000000000..09e074858 --- /dev/null +++ b/patches-sonic/0008-PCI-AER-Ratelimit-correctable-and-non-fatal-error-lo.patch @@ -0,0 +1,221 @@ +From 3fff4113090e26cb3de64388bb5e91bfb0d02118 Mon Sep 17 00:00:00 2001 +From: Jon Pan-Doh +Date: Thu, 22 May 2025 18:21:24 -0500 +Subject: [PATCH 08/12] PCI/AER: Ratelimit correctable and non-fatal error + logging + +Spammy devices can flood kernel logs with AER errors and slow/stall +execution. Add per-device ratelimits for AER correctable and non-fatal +uncorrectable errors that use the kernel defaults (10 per 5s). Logging of +fatal errors is not ratelimited. + +There are two AER logging entry points: + + - aer_print_error() is used by DPC and native AER + + - pci_print_aer() is used by GHES and CXL + +The native AER aer_print_error() case includes a loop that may log details +from multiple devices, which are ratelimited individually. If we log +details for any device, we also log the Error Source ID from the Root Port +or RCEC. + +If no such device details are found, we still log the Error Source from the +ERR_* Message, ratelimited by the Root Port or RCEC that received it. + +The DPC aer_print_error() case is not ratelimited, since this only happens +for fatal errors. + +The CXL pci_print_aer() case is ratelimited by the Error Source device. + +The GHES pci_print_aer() case is via aer_recover_work_func(), which +searches for the Error Source device. If the device is not found, there's +no per-device ratelimit, so we use a system-wide ratelimit that covers all +error types (correctable, non-fatal, and fatal). + +Sargun at Meta reported internally that a flood of AER errors causes RCU +CPU stall warnings and CSD-lock warnings. + +Tested using aer-inject[1]. Sent 11 AER errors. Observed 10 errors logged +while AER stats (cat /sys/bus/pci/devices//aer_dev_correctable) show +true count of 11. + +[1] https://git.kernel.org/pub/scm/linux/kernel/git/gong.chen/aer-inject.git + +[bhelgaas: commit log, factor out trace_aer_event() and aer_print_rp_info() +changes to previous patches, enable Error Source logging if any downstream +detail will be printed, don't ratelimit fatal errors, "aer_report" -> +"aer_info", "cor_log_ratelimit" -> "correctable_ratelimit", +"uncor_log_ratelimit" -> "nonfatal_ratelimit"] + +Reported-by: Sargun Dhillon +Signed-off-by: Jon Pan-Doh +Signed-off-by: Bjorn Helgaas +Reviewed-by: Kuppuswamy Sathyanarayanan +Link: https://patch.msgid.link/20250522232339.1525671-19-helgaas@kernel.org +(cherry picked from commit a57f2bfb4a5863f83087867c0e671f2418212d23) +--- + drivers/pci/pci.h | 4 ++- + drivers/pci/pcie/aer.c | 68 ++++++++++++++++++++++++++++++++++++++---- + 2 files changed, 66 insertions(+), 6 deletions(-) + +diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h +index 4f64f3f9cdf5..f4372bb39fe2 100644 +--- a/drivers/pci/pci.h ++++ b/drivers/pci/pci.h +@@ -504,13 +504,15 @@ static inline bool pci_dev_is_added(const struct pci_dev *dev) + + struct aer_err_info { + struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; ++ int ratelimit_print[AER_MAX_MULTI_ERR_DEVICES]; + int error_dev_num; + const char *level; /* printk level */ + + unsigned int id:16; + + unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ +- unsigned int __pad1:5; ++ unsigned int root_ratelimit_print:1; /* 0=skip, 1=print */ ++ unsigned int __pad1:4; + unsigned int multi_error_valid:1; + + unsigned int first_error:5; +diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c +index 6ec628965cce..8d0152f4fe50 100644 +--- a/drivers/pci/pcie/aer.c ++++ b/drivers/pci/pcie/aer.c +@@ -27,6 +27,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -84,6 +85,10 @@ struct aer_stats { + u64 rootport_total_cor_errs; + u64 rootport_total_fatal_errs; + u64 rootport_total_nonfatal_errs; ++ ++ /* Ratelimits for errors */ ++ struct ratelimit_state correctable_ratelimit; ++ struct ratelimit_state nonfatal_ratelimit; + }; + + #define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \ +@@ -374,6 +379,11 @@ void pci_aer_init(struct pci_dev *dev) + + dev->aer_stats = kzalloc(sizeof(struct aer_stats), GFP_KERNEL); + ++ ratelimit_state_init(&dev->aer_stats->correctable_ratelimit, ++ DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST); ++ ratelimit_state_init(&dev->aer_stats->nonfatal_ratelimit, ++ DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST); ++ + /* + * We save/restore PCI_ERR_UNCOR_MASK, PCI_ERR_UNCOR_SEVER, + * PCI_ERR_COR_MASK, and PCI_ERR_CAP. Root and Root Complex Event +@@ -670,6 +680,18 @@ static void __print_tlp_header(struct pci_dev *dev, struct pcie_tlp_log *t) + t->dw[0], t->dw[1], t->dw[2], t->dw[3]); + } + ++static int aer_ratelimit(struct pci_dev *dev, unsigned int severity) ++{ ++ switch (severity) { ++ case AER_NONFATAL: ++ return __ratelimit(&dev->aer_stats->nonfatal_ratelimit); ++ case AER_CORRECTABLE: ++ return __ratelimit(&dev->aer_stats->correctable_ratelimit); ++ default: ++ return 1; /* Don't ratelimit fatal errors */ ++ } ++} ++ + static void __aer_print_error(struct pci_dev *dev, + struct aer_err_info *info) + { +@@ -710,6 +732,9 @@ void aer_print_error(struct aer_err_info *info, int i) + trace_aer_event(pci_name(dev), (info->status & ~info->mask), + info->severity, info->tlp_header_valid, &info->tlp); + ++ if (!info->ratelimit_print[i]) ++ return; ++ + if (!info->status) { + pci_err(dev, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n", + aer_error_severity_string[info->severity]); +@@ -791,6 +816,9 @@ void pci_print_aer(struct pci_dev *dev, int aer_severity, + trace_aer_event(pci_name(dev), (status & ~mask), + aer_severity, tlp_header_valid, &aer->header_log); + ++ if (!aer_ratelimit(dev, info.severity)) ++ return; ++ + layer = AER_GET_LAYER_ERROR(aer_severity, status); + agent = AER_GET_AGENT(aer_severity, status); + +@@ -823,6 +851,18 @@ static int add_error_device(struct aer_err_info *e_info, struct pci_dev *dev) + e_info->dev[i] = pci_dev_get(dev); + e_info->error_dev_num++; + ++ /* ++ * Ratelimit AER log messages. "dev" is either the source ++ * identified by the root's Error Source ID or it has an unmasked ++ * error logged in its own AER Capability. Messages are emitted ++ * when "ratelimit_print[i]" is non-zero. If we will print detail ++ * for a downstream device, make sure we print the Error Source ID ++ * from the root as well. ++ */ ++ if (aer_ratelimit(dev, e_info->severity)) { ++ e_info->ratelimit_print[i] = 1; ++ e_info->root_ratelimit_print = 1; ++ } + return 0; + } + +@@ -1150,9 +1190,10 @@ static void aer_recover_work_func(struct work_struct *work) + pdev = pci_get_domain_bus_and_slot(entry.domain, entry.bus, + entry.devfn); + if (!pdev) { +- pr_err("no pci_dev for %04x:%02x:%02x.%x\n", +- entry.domain, entry.bus, +- PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn)); ++ pr_err_ratelimited("%04x:%02x:%02x.%x: no pci_dev found\n", ++ entry.domain, entry.bus, ++ PCI_SLOT(entry.devfn), ++ PCI_FUNC(entry.devfn)); + continue; + } + pci_print_aer(pdev, entry.severity, entry.regs); +@@ -1291,9 +1332,26 @@ static inline void aer_process_err_devices(struct aer_err_info *e_info) + static void aer_isr_one_error_type(struct pci_dev *root, + struct aer_err_info *info) + { +- aer_print_port_info(root, info); ++ bool found; ++ ++ found = find_source_device(root, info); ++ ++ /* ++ * If we're going to log error messages, we've already set ++ * "info->root_ratelimit_print" and "info->ratelimit_print[i]" to ++ * non-zero (which enables printing) because this is either an ++ * ERR_FATAL or we found a device with an error logged in its AER ++ * Capability. ++ * ++ * If we didn't find the Error Source device, at least log the ++ * Requester ID from the ERR_* Message received by the Root Port or ++ * RCEC, ratelimited by the RP or RCEC. ++ */ ++ if (info->root_ratelimit_print || ++ (!found && aer_ratelimit(root, info->severity))) ++ aer_print_port_info(root, info); + +- if (find_source_device(root, info)) ++ if (found) + aer_process_err_devices(info); + } + +-- +2.47.0 + diff --git a/patches-sonic/0009-PCI-AER-Add-sysfs-attributes-for-log-ratelimits.patch b/patches-sonic/0009-PCI-AER-Add-sysfs-attributes-for-log-ratelimits.patch new file mode 100644 index 000000000..70b3ce45c --- /dev/null +++ b/patches-sonic/0009-PCI-AER-Add-sysfs-attributes-for-log-ratelimits.patch @@ -0,0 +1,272 @@ +From d9396d86c78fee6c5eab356abb7e4b86dce1be32 Mon Sep 17 00:00:00 2001 +From: Jon Pan-Doh +Date: Thu, 22 May 2025 18:21:26 -0500 +Subject: [PATCH 09/12] PCI/AER: Add sysfs attributes for log ratelimits + +Allow userspace to read/write log ratelimits per device (including +enable/disable). Create aer/ sysfs directory to store them and any +future AER configs. + +The new sysfs files are: + + /sys/bus/pci/devices/*/aer/correctable_ratelimit_burst + /sys/bus/pci/devices/*/aer/correctable_ratelimit_interval_ms + /sys/bus/pci/devices/*/aer/nonfatal_ratelimit_burst + /sys/bus/pci/devices/*/aer/nonfatal_ratelimit_interval_ms + +The default values are ratelimit_burst=10, ratelimit_interval_ms=5000, so +if we try to emit more than 10 messages in a 5 second period, some are +suppressed. + +Update AER sysfs ABI filename to reflect the broader scope of AER sysfs +attributes (e.g. stats and ratelimits). + + Documentation/ABI/testing/sysfs-bus-pci-devices-aer_stats -> + sysfs-bus-pci-devices-aer + +Tested using aer-inject[1]. Configured correctable log ratelimit to 5. +Sent 6 AER errors. Observed 5 errors logged while AER stats +(cat /sys/bus/pci/devices//aer_dev_correctable) shows 6. + +Disabled ratelimiting and sent 6 more AER errors. Observed all 6 errors +logged and accounted in AER stats (12 total errors). + +[1] https://git.kernel.org/pub/scm/linux/kernel/git/gong.chen/aer-inject.git + +[bhelgaas: note fatal errors are not ratelimited, "aer_report" -> +"aer_info", replace ratelimit_log_enable toggle with *_ratelimit_interval_ms] + +Signed-off-by: Karolina Stolarek +Signed-off-by: Jon Pan-Doh +Signed-off-by: Bjorn Helgaas +Reviewed-by: Kuppuswamy Sathyanarayanan +Link: https://patch.msgid.link/20250522232339.1525671-21-helgaas@kernel.org +(cherry picked from commit b4fe7398def6df344442b884d2288f80205cbd2d) +--- + ...es-aer_stats => sysfs-bus-pci-devices-aer} | 44 ++++++++ + Documentation/PCI/pcieaer-howto.rst | 5 +- + drivers/pci/pci-sysfs.c | 1 + + drivers/pci/pci.h | 1 + + drivers/pci/pcie/aer.c | 105 ++++++++++++++++++ + 5 files changed, 155 insertions(+), 1 deletion(-) + rename Documentation/ABI/testing/{sysfs-bus-pci-devices-aer_stats => sysfs-bus-pci-devices-aer} (72%) + +diff --git a/Documentation/ABI/testing/sysfs-bus-pci-devices-aer_stats b/Documentation/ABI/testing/sysfs-bus-pci-devices-aer +similarity index 72% +rename from Documentation/ABI/testing/sysfs-bus-pci-devices-aer_stats +rename to Documentation/ABI/testing/sysfs-bus-pci-devices-aer +index d1f67bb81d5d..5ed284523956 100644 +--- a/Documentation/ABI/testing/sysfs-bus-pci-devices-aer_stats ++++ b/Documentation/ABI/testing/sysfs-bus-pci-devices-aer +@@ -117,3 +117,47 @@ Date: July 2018 + KernelVersion: 4.19.0 + Contact: linux-pci@vger.kernel.org, rajatja@google.com + Description: Total number of ERR_NONFATAL messages reported to rootport. ++ ++PCIe AER ratelimits ++------------------- ++ ++These attributes show up under all the devices that are AER capable. ++They represent configurable ratelimits of logs per error type. ++ ++See Documentation/PCI/pcieaer-howto.rst for more info on ratelimits. ++ ++What: /sys/bus/pci/devices//aer/correctable_ratelimit_interval_ms ++Date: May 2025 ++KernelVersion: 6.16.0 ++Contact: linux-pci@vger.kernel.org ++Description: Writing 0 disables AER correctable error log ratelimiting. ++ Writing a positive value sets the ratelimit interval in ms. ++ Default is DEFAULT_RATELIMIT_INTERVAL (5000 ms). ++ ++What: /sys/bus/pci/devices//aer/correctable_ratelimit_burst ++Date: May 2025 ++KernelVersion: 6.16.0 ++Contact: linux-pci@vger.kernel.org ++Description: Ratelimit burst for correctable error logs. Writing a value ++ changes the number of errors (burst) allowed per interval ++ before ratelimiting. Reading gets the current ratelimit ++ burst. Default is DEFAULT_RATELIMIT_BURST (10). ++ ++What: /sys/bus/pci/devices//aer/nonfatal_ratelimit_interval_ms ++Date: May 2025 ++KernelVersion: 6.16.0 ++Contact: linux-pci@vger.kernel.org ++Description: Writing 0 disables AER non-fatal uncorrectable error log ++ ratelimiting. Writing a positive value sets the ratelimit ++ interval in ms. Default is DEFAULT_RATELIMIT_INTERVAL ++ (5000 ms). ++ ++What: /sys/bus/pci/devices//aer/nonfatal_ratelimit_burst ++Date: May 2025 ++KernelVersion: 6.16.0 ++Contact: linux-pci@vger.kernel.org ++Description: Ratelimit burst for non-fatal uncorrectable error logs. ++ Writing a value changes the number of errors (burst) ++ allowed per interval before ratelimiting. Reading gets the ++ current ratelimit burst. Default is DEFAULT_RATELIMIT_BURST ++ (10). +diff --git a/Documentation/PCI/pcieaer-howto.rst b/Documentation/PCI/pcieaer-howto.rst +index f013f3b27c82..896d6aea6984 100644 +--- a/Documentation/PCI/pcieaer-howto.rst ++++ b/Documentation/PCI/pcieaer-howto.rst +@@ -85,12 +85,15 @@ In the example, 'Requester ID' means the ID of the device that sent + the error message to the Root Port. Please refer to PCIe specs for other + fields. + ++Ratelimits are exposed in the form of sysfs attributes and configurable. ++See Documentation/ABI/testing/sysfs-bus-pci-devices-aer. ++ + AER Statistics / Counters + ------------------------- + + When PCIe AER errors are captured, the counters / statistics are also exposed + in the form of sysfs attributes which are documented at +-Documentation/ABI/testing/sysfs-bus-pci-devices-aer_stats ++Documentation/ABI/testing/sysfs-bus-pci-devices-aer + + Developer Guide + =============== +diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c +index 5af4a804a4f8..bc7b9974b6d0 100644 +--- a/drivers/pci/pci-sysfs.c ++++ b/drivers/pci/pci-sysfs.c +@@ -1689,6 +1689,7 @@ const struct attribute_group *pci_dev_attr_groups[] = { + &pcie_dev_attr_group, + #ifdef CONFIG_PCIEAER + &aer_stats_attr_group, ++ &aer_attr_group, + #endif + #ifdef CONFIG_PCIEASPM + &aspm_ctrl_attr_group, +diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h +index f4372bb39fe2..fcff31039d17 100644 +--- a/drivers/pci/pci.h ++++ b/drivers/pci/pci.h +@@ -833,6 +833,7 @@ void pci_no_aer(void); + void pci_aer_init(struct pci_dev *dev); + void pci_aer_exit(struct pci_dev *dev); + extern const struct attribute_group aer_stats_attr_group; ++extern const struct attribute_group aer_attr_group; + void pci_aer_clear_fatal_status(struct pci_dev *dev); + int pci_aer_clear_status(struct pci_dev *dev); + int pci_aer_raw_clear_status(struct pci_dev *dev); +diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c +index 8d0152f4fe50..df636016168f 100644 +--- a/drivers/pci/pcie/aer.c ++++ b/drivers/pci/pcie/aer.c +@@ -622,6 +622,111 @@ const struct attribute_group aer_stats_attr_group = { + .is_visible = aer_stats_attrs_are_visible, + }; + ++/* ++ * Ratelimit interval ++ * <=0: disabled with ratelimit.interval = 0 ++ * >0: enabled with ratelimit.interval in ms ++ */ ++#define aer_ratelimit_interval_attr(name, ratelimit) \ ++ static ssize_t \ ++ name##_show(struct device *dev, struct device_attribute *attr, \ ++ char *buf) \ ++ { \ ++ struct pci_dev *pdev = to_pci_dev(dev); \ ++ \ ++ return sysfs_emit(buf, "%d\n", \ ++ pdev->aer_stats->ratelimit.interval); \ ++ } \ ++ \ ++ static ssize_t \ ++ name##_store(struct device *dev, struct device_attribute *attr, \ ++ const char *buf, size_t count) \ ++ { \ ++ struct pci_dev *pdev = to_pci_dev(dev); \ ++ int interval; \ ++ \ ++ if (!capable(CAP_SYS_ADMIN)) \ ++ return -EPERM; \ ++ \ ++ if (kstrtoint(buf, 0, &interval) < 0) \ ++ return -EINVAL; \ ++ \ ++ if (interval <= 0) \ ++ interval = 0; \ ++ else \ ++ interval = msecs_to_jiffies(interval); \ ++ \ ++ pdev->aer_stats->ratelimit.interval = interval; \ ++ \ ++ return count; \ ++ } \ ++ static DEVICE_ATTR_RW(name); ++ ++#define aer_ratelimit_burst_attr(name, ratelimit) \ ++ static ssize_t \ ++ name##_show(struct device *dev, struct device_attribute *attr, \ ++ char *buf) \ ++ { \ ++ struct pci_dev *pdev = to_pci_dev(dev); \ ++ \ ++ return sysfs_emit(buf, "%d\n", \ ++ pdev->aer_stats->ratelimit.burst); \ ++ } \ ++ \ ++ static ssize_t \ ++ name##_store(struct device *dev, struct device_attribute *attr, \ ++ const char *buf, size_t count) \ ++ { \ ++ struct pci_dev *pdev = to_pci_dev(dev); \ ++ int burst; \ ++ \ ++ if (!capable(CAP_SYS_ADMIN)) \ ++ return -EPERM; \ ++ \ ++ if (kstrtoint(buf, 0, &burst) < 0) \ ++ return -EINVAL; \ ++ \ ++ pdev->aer_stats->ratelimit.burst = burst; \ ++ \ ++ return count; \ ++ } \ ++ static DEVICE_ATTR_RW(name); ++ ++#define aer_ratelimit_attrs(name) \ ++ aer_ratelimit_interval_attr(name##_ratelimit_interval_ms, \ ++ name##_ratelimit) \ ++ aer_ratelimit_burst_attr(name##_ratelimit_burst, \ ++ name##_ratelimit) ++ ++aer_ratelimit_attrs(correctable) ++aer_ratelimit_attrs(nonfatal) ++ ++static struct attribute *aer_attrs[] = { ++ &dev_attr_correctable_ratelimit_interval_ms.attr, ++ &dev_attr_correctable_ratelimit_burst.attr, ++ &dev_attr_nonfatal_ratelimit_interval_ms.attr, ++ &dev_attr_nonfatal_ratelimit_burst.attr, ++ NULL ++}; ++ ++static umode_t aer_attrs_are_visible(struct kobject *kobj, ++ struct attribute *a, int n) ++{ ++ struct device *dev = kobj_to_dev(kobj); ++ struct pci_dev *pdev = to_pci_dev(dev); ++ ++ if (!pdev->aer_stats) ++ return 0; ++ ++ return a->mode; ++} ++ ++const struct attribute_group aer_attr_group = { ++ .name = "aer", ++ .attrs = aer_attrs, ++ .is_visible = aer_attrs_are_visible, ++}; ++ + static void pci_dev_aer_stats_incr(struct pci_dev *pdev, + struct aer_err_info *info) + { +-- +2.47.0 + diff --git a/patches-sonic/0010-fix-aer-ratelimiting-sysfs-output-units.patch b/patches-sonic/0010-fix-aer-ratelimiting-sysfs-output-units.patch new file mode 100644 index 000000000..73dada6f1 --- /dev/null +++ b/patches-sonic/0010-fix-aer-ratelimiting-sysfs-output-units.patch @@ -0,0 +1,34 @@ +From f993b05bf9e59ab4a0c41cad1ab956080c5fb027 Mon Sep 17 00:00:00 2001 +From: jamessewart +Date: Mon, 10 Nov 2025 13:45:50 +0000 +Subject: [PATCH 10/12] fix aer ratelimiting sysfs output units + +aer statistics include an interval value that determines the time period over which +to limit error logging. This is stored in jiffies, but the sysfs file configuring it +is supposed to expose milliseconds, the store function converts the input to jiffies +and this change ensures the show implementation converts back to milliseconds + +Signed-off-by: James Sewart +--- + drivers/pci/pcie/aer.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c +index df636016168f..067e305212eb 100644 +--- a/drivers/pci/pcie/aer.c ++++ b/drivers/pci/pcie/aer.c +@@ -634,8 +634,9 @@ const struct attribute_group aer_stats_attr_group = { + { \ + struct pci_dev *pdev = to_pci_dev(dev); \ + \ +- return sysfs_emit(buf, "%d\n", \ +- pdev->aer_stats->ratelimit.interval); \ ++ int interval = pdev->aer_stats->ratelimit.interval; \ ++ interval = jiffies_to_msecs(interval); \ ++ return sysfs_emit(buf, "%d\n", interval); \ + } \ + \ + static ssize_t \ +-- +2.47.0 + diff --git a/patches-sonic/0011-PCI-AER-Fix-NULL-pointer-access-by-aer_info.patch b/patches-sonic/0011-PCI-AER-Fix-NULL-pointer-access-by-aer_info.patch new file mode 100644 index 000000000..4ba0ce643 --- /dev/null +++ b/patches-sonic/0011-PCI-AER-Fix-NULL-pointer-access-by-aer_info.patch @@ -0,0 +1,36 @@ +From 3b9b13868b3051851850d17adf1c22ac87ece220 Mon Sep 17 00:00:00 2001 +From: Vernon Yang +Date: Fri, 5 Sep 2025 02:25:27 +0800 +Subject: [PATCH 11/12] PCI/AER: Fix NULL pointer access by aer_info + +The kzalloc(GFP_KERNEL) may return NULL, so all accesses to aer_info->xxx +will result in kernel panic. Fix it. + +Signed-off-by: Vernon Yang +Signed-off-by: Bjorn Helgaas +Link: https://patch.msgid.link/20250904182527.67371-1-vernon2gm@gmail.com +(cherry picked from commit 0a27bdb14b028fed30a10cec2f945c38cb5ca4fa) +--- + drivers/pci/pcie/aer.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c +index 067e305212eb..f1886e60f5a2 100644 +--- a/drivers/pci/pcie/aer.c ++++ b/drivers/pci/pcie/aer.c +@@ -377,7 +377,11 @@ void pci_aer_init(struct pci_dev *dev) + if (!dev->aer_cap) + return; + +- dev->aer_stats = kzalloc(sizeof(struct aer_stats), GFP_KERNEL); ++ dev->aer_stats = kzalloc(sizeof(*dev->aer_stats), GFP_KERNEL); ++ if (!dev->aer_stats) { ++ dev->aer_cap = 0; ++ return; ++ } + + ratelimit_state_init(&dev->aer_stats->correctable_ratelimit, + DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST); +-- +2.47.0 + diff --git a/patches-sonic/0012-PCI-AER-Avoid-NULL-pointer-dereference-in-aer_rateli.patch b/patches-sonic/0012-PCI-AER-Avoid-NULL-pointer-dereference-in-aer_rateli.patch new file mode 100644 index 000000000..f0fb8d9d0 --- /dev/null +++ b/patches-sonic/0012-PCI-AER-Avoid-NULL-pointer-dereference-in-aer_rateli.patch @@ -0,0 +1,61 @@ +From 5034b584556f1a8fe60d10231ac9a3f687508c54 Mon Sep 17 00:00:00 2001 +From: Breno Leitao +Date: Mon, 29 Sep 2025 02:15:47 -0700 +Subject: [PATCH 12/12] PCI/AER: Avoid NULL pointer dereference in + aer_ratelimit() + +When platform firmware supplies error information to the OS, e.g., via the +ACPI APEI GHES mechanism, it may identify an error source device that +doesn't advertise an AER Capability and therefore dev->aer_info, which +contains AER stats and ratelimiting data, is NULL. + +pci_dev_aer_stats_incr() already checks dev->aer_info for NULL, but +aer_ratelimit() did not, leading to NULL pointer dereferences like this one +from the URL below: + + {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 0 + {1}[Hardware Error]: event severity: corrected + {1}[Hardware Error]: device_id: 0000:00:00.0 + {1}[Hardware Error]: vendor_id: 0x8086, device_id: 0x2020 + {1}[Hardware Error]: aer_cor_status: 0x00001000, aer_cor_mask: 0x00002000 + BUG: kernel NULL pointer dereference, address: 0000000000000264 + RIP: 0010:___ratelimit+0xc/0x1b0 + pci_print_aer+0x141/0x360 + aer_recover_work_func+0xb5/0x130 + +[8086:2020] is an Intel "Sky Lake-E DMI3 Registers" device that claims to +be a Root Port but does not advertise an AER Capability. + +Add a NULL check in aer_ratelimit() to avoid the NULL pointer dereference. +Note that this also prevents ratelimiting these events from GHES. + +Fixes: a57f2bfb4a5863 ("PCI/AER: Ratelimit correctable and non-fatal error logging") +Link: https://lore.kernel.org/r/buduna6darbvwfg3aogl5kimyxkggu3n4romnmq6sozut6axeu@clnx7sfsy457/ +Signed-off-by: Breno Leitao +[bhelgaas: add crash details to commit log] +Signed-off-by: Bjorn Helgaas +Reviewed-by: Kuppuswamy Sathyanarayanan +Cc: stable@vger.kernel.org +Link: https://patch.msgid.link/20250929-aer_crash_2-v1-1-68ec4f81c356@debian.org +(cherry picked from commit deb2f228388ff3a9d0623e3b59a053e9235c341d) +--- + drivers/pci/pcie/aer.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c +index f1886e60f5a2..ac64e5e5c95e 100644 +--- a/drivers/pci/pcie/aer.c ++++ b/drivers/pci/pcie/aer.c +@@ -792,6 +792,9 @@ static void __print_tlp_header(struct pci_dev *dev, struct pcie_tlp_log *t) + + static int aer_ratelimit(struct pci_dev *dev, unsigned int severity) + { ++ if (!dev->aer_stats) ++ return 1; ++ + switch (severity) { + case AER_NONFATAL: + return __ratelimit(&dev->aer_stats->nonfatal_ratelimit); +-- +2.47.0 + diff --git a/patches-sonic/series b/patches-sonic/series index dac5959ef..8d862b559 100644 --- a/patches-sonic/series +++ b/patches-sonic/series @@ -205,6 +205,20 @@ cisco-npu-disable-other-bars.patch # https://github.com/sonic-net/sonic-buildimage/issues/20901 #PCI-ASPM-Fix-link-state-exit-during-switch-upstream.patch # Upstreamed +# +0001-PCI-AER-Simplify-pci_print_aer.patch +0002-PCI-AER-Update-statistics-before-ratelimiting.patch +0003-PCI-AER-Trace-error-event-before-ratelimiting.patch +0004-PCI-AER-Simplify-add_error_device.patch +0005-PCI-AER-Check-log-level-once-and-remember-it.patch +0006-PCI-AER-Convert-aer_get_device_error_info-aer_print_.patch +0007-PCI-AER-Factor-COR-UNCOR-error-handling-out-from-aer.patch +0008-PCI-AER-Ratelimit-correctable-and-non-fatal-error-lo.patch +0009-PCI-AER-Add-sysfs-attributes-for-log-ratelimits.patch +0010-fix-aer-ratelimiting-sysfs-output-units.patch +0011-PCI-AER-Fix-NULL-pointer-access-by-aer_info.patch +0012-PCI-AER-Avoid-NULL-pointer-dereference-in-aer_rateli.patch + # # ############################################################ From b363a5ba84b45ce5111bedc6fd9d96cc897c198b Mon Sep 17 00:00:00 2001 From: Pavan Prakash <120486223+Pavan-Nokia@users.noreply.github.com> Date: Tue, 6 Jan 2026 15:19:10 -0500 Subject: [PATCH 14/16] Add tpm_tis_i2c driver module for arm64 (#524) Signed-off-by: Pavan Prakash --- config.local/arm64/config.sonic | 1 + 1 file changed, 1 insertion(+) diff --git a/config.local/arm64/config.sonic b/config.local/arm64/config.sonic index fb7db2101..2e5fb2069 100644 --- a/config.local/arm64/config.sonic +++ b/config.local/arm64/config.sonic @@ -40,3 +40,4 @@ CONFIG_SQUASHFS_DECOMP_MULTI=y CONFIG_PREEMPTIRQ_TRACEPOINTS=y CONFIG_RING_BUFFER_ALLOW_SWAP=y CONFIG_KEXEC_FILE=y +CONFIG_TCG_TIS_I2C=m From e7fea60c1f304a793c20b7f355ab1b05d06d0763 Mon Sep 17 00:00:00 2001 From: yijingyan2 Date: Wed, 7 Jan 2026 17:25:17 +1100 Subject: [PATCH 15/16] update docker slave name (#523) Signed-off-by: yijingyan2 Co-authored-by: Saikrishna Arcot --- .azure-pipelines/build-template.yml | 5 +---- azure-pipelines.yml | 11 ++++++----- 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/.azure-pipelines/build-template.yml b/.azure-pipelines/build-template.yml index 4cfa93870..d67409d52 100644 --- a/.azure-pipelines/build-template.yml +++ b/.azure-pipelines/build-template.yml @@ -25,9 +25,6 @@ parameters: type: number default: 180 -- name: sonic_slave - type: string - - name: old_artifact_name type: string @@ -51,7 +48,7 @@ jobs: timeoutInMinutes: ${{ parameters.timeout }} container: - image: sonicdev-microsoft.azurecr.io:443/${{ parameters.sonic_slave }}:master + image: sonicdev-microsoft.azurecr.io:443/sonic-slave-trixie:$(BUILD_BRANCH)-${{ parameters.arch }} steps: - checkout: self diff --git a/azure-pipelines.yml b/azure-pipelines.yml index ea2d932ba..205ce2cb6 100644 --- a/azure-pipelines.yml +++ b/azure-pipelines.yml @@ -7,6 +7,12 @@ trigger: branches: include: - "*" +variables: + - name: BUILD_BRANCH + ${{ if eq(variables['Build.Reason'], 'PullRequest') }}: + value: $(System.PullRequest.TargetBranch) + ${{ else }}: + value: $(Build.SourceBranchName) stages: - stage: Build @@ -16,7 +22,6 @@ stages: parameters: arch: amd64 pool: sonicso1ES-amd64 - sonic_slave: sonic-slave-trixie old_artifact_name: sonic-linux-kernel artifact_name: sonic-linux-kernel.amd64 old_linux_deb_pattern: linux-image-*-unsigned_*deb @@ -26,7 +31,6 @@ stages: parameters: arch: amd64 pool: sonicso1ES-amd64 - sonic_slave: sonic-slave-trixie old_artifact_name: sonic-linux-kernel artifact_name: sonic-linux-kernel.amd64.secure old_linux_deb_pattern: linux-image-*-unsigned_*deb @@ -37,7 +41,6 @@ stages: parameters: arch: arm64 pool: sonicso1ES-arm64 - sonic_slave: sonic-slave-trixie-arm64 old_artifact_name: sonic-linux-kernel.arm64 artifact_name: sonic-linux-kernel.arm64 old_linux_deb_pattern: linux-image-*-unsigned_*deb @@ -47,7 +50,6 @@ stages: parameters: arch: armhf pool: sonicso1ES-armhf - sonic_slave: sonic-slave-trixie-armhf old_artifact_name: sonic-linux-kernel.armhf artifact_name: sonic-linux-kernel.armhf old_linux_deb_pattern: linux-image-*-armmp_*deb @@ -58,7 +60,6 @@ stages: arch: arm64 platform: pensando pool: sonicso1ES-arm64 - sonic_slave: sonic-slave-trixie-arm64 old_artifact_name: sonic-linux-kernel.pensando.arm64 artifact_name: sonic-linux-kernel.pensando.arm64 old_linux_deb_pattern: linux-image-*-unsigned_*deb From 6f42104b9a8df275dcbeefe04a7c44fc74ece17e Mon Sep 17 00:00:00 2001 From: Hemanth Kumar Tirupati Date: Thu, 8 Jan 2026 19:09:06 +0000 Subject: [PATCH 16/16] Integrate HW-MGMT 7.0050.2935 Changes ## Patch List * 0056-hwmon-pmbus-mp2845-Add-support-for-MP2845-device.patch : * 0057-hwmon-pmbus-mp5926-Add-support-for-MP5926-device.patch : Signed-off-by: Hemanth Kumar Tirupati --- config.local/amd64/config.sonic | 2 + ...x-mlx-platform-Add-support-for-new-N.patch | 2 +- ...x-nvsw-bmc-Add-system-control-and-mo.patch | 1098 ++++++++++++++++- ...mp2845-Add-support-for-MP2845-device.patch | 555 +++++++++ ...mp5926-Add-support-for-MP5926-device.patch | 253 ++++ ...x-mlxreg-dpu-Debug-trace-for-dpu-pro.patch | 32 - patches-sonic/series | 3 +- 7 files changed, 1886 insertions(+), 59 deletions(-) create mode 100644 patches-sonic/0056-hwmon-pmbus-mp2845-Add-support-for-MP2845-device.patch create mode 100644 patches-sonic/0057-hwmon-pmbus-mp5926-Add-support-for-MP5926-device.patch delete mode 100644 patches-sonic/8014-platform-mellanox-mlxreg-dpu-Debug-trace-for-dpu-pro.patch diff --git a/config.local/amd64/config.sonic b/config.local/amd64/config.sonic index 23bf715f2..c09b6652f 100644 --- a/config.local/amd64/config.sonic +++ b/config.local/amd64/config.sonic @@ -101,6 +101,8 @@ CONFIG_SENSORS_MP2888=m CONFIG_SENSORS_MP2891=m CONFIG_SENSORS_MP2869=m CONFIG_SENSORS_MP29502=m +CONFIG_SENSORS_MP2845=m +CONFIG_SENSORS_MP5926=m CONFIG_GPIO_ICH=m CONFIG_CPU_THERMAL=y CONFIG_IGB_HWMON=y diff --git a/patches-sonic/0035-platform-mellanox-mlx-platform-Add-support-for-new-N.patch b/patches-sonic/0035-platform-mellanox-mlx-platform-Add-support-for-new-N.patch index 23e43ee5f..16cf32bdc 100644 --- a/patches-sonic/0035-platform-mellanox-mlx-platform-Add-support-for-new-N.patch +++ b/patches-sonic/0035-platform-mellanox-mlx-platform-Add-support-for-new-N.patch @@ -118,7 +118,7 @@ index fca8883..a607fd6 100644 + mlxplat_hotplug = &mlxplat_mlxcpld_ng800_hi171_data; + mlxplat_hotplug->deferred_nr = + mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; -+ mlxplat_led = &mlxplat_default_ng_led_data; ++ mlxplat_led = &mlxplat_xdr_led_data; + mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; + mlxplat_fan = &mlxplat_xdr_fan_data; + diff --git a/patches-sonic/0046-platform-mellanox-nvsw-bmc-Add-system-control-and-mo.patch b/patches-sonic/0046-platform-mellanox-nvsw-bmc-Add-system-control-and-mo.patch index ef97c02fc..f8ccbe6df 100644 --- a/patches-sonic/0046-platform-mellanox-nvsw-bmc-Add-system-control-and-mo.patch +++ b/patches-sonic/0046-platform-mellanox-nvsw-bmc-Add-system-control-and-mo.patch @@ -1,7 +1,7 @@ -From 9b36f571a51a32214316a7a4afc3c902b9059f48 Mon Sep 17 00:00:00 2001 +From 2811cc1b7ee9f6ce0242591a2a5a3d133a3c0547 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Thu, 4 Jul 2024 23:50:27 +0300 -Subject: [PATCH 46/78] platform/mellanox: nvsw-bmc: Add system control and +Subject: [PATCH] platform/mellanox: nvsw-bmc: Add system control and monitoring driver for Nvidia BMC The driver allows system control and monitoring of Nvidia switches @@ -18,21 +18,23 @@ This control includes: Signed-off-by: Vadim Pasternak --- - .../devicetree/bindings/trivial-devices.yaml | 5 + - drivers/platform/mellanox/Kconfig | 18 + - drivers/platform/mellanox/Makefile | 2 + - drivers/platform/mellanox/nvsw-bmc-hid162.c | 2773 ++++++++++++++++++++ - drivers/platform/mellanox/nvsw-core.c | 625 +++++ - drivers/platform/mellanox/nvsw-host-l1.c | 745 ++++++ - drivers/platform/mellanox/nvsw.h | 260 ++ - 7 files changed, 4428 insertions(+) + .../devicetree/bindings/trivial-devices.yaml | 5 + + drivers/platform/mellanox/Kconfig | 28 + + drivers/platform/mellanox/Makefile | 3 + + drivers/platform/mellanox/nvsw-bmc-hid162.c | 2773 +++++++++++++++++ + drivers/platform/mellanox/nvsw-core.c | 686 ++++ + drivers/platform/mellanox/nvsw-host-l1.c | 744 +++++ + drivers/platform/mellanox/nvsw-host-spc5.c | 937 ++++++ + drivers/platform/mellanox/nvsw.h | 292 ++ + 8 files changed, 5468 insertions(+) create mode 100644 drivers/platform/mellanox/nvsw-bmc-hid162.c create mode 100644 drivers/platform/mellanox/nvsw-core.c create mode 100644 drivers/platform/mellanox/nvsw-host-l1.c + create mode 100644 drivers/platform/mellanox/nvsw-host-spc5.c create mode 100644 drivers/platform/mellanox/nvsw.h diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml -index a190c56..14568bd 100644 +index a190c5676..14568bd0f 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -307,6 +307,11 @@ properties: @@ -48,10 +50,10 @@ index a190c56..14568bd 100644 - nuvoton,w83773g # OKI ML86V7667 video decoder diff --git a/drivers/platform/mellanox/Kconfig b/drivers/platform/mellanox/Kconfig -index e3afbe6..dd6b576 100644 +index e3afbe62c..521423f4b 100644 --- a/drivers/platform/mellanox/Kconfig +++ b/drivers/platform/mellanox/Kconfig -@@ -105,6 +105,24 @@ config MLXBF_PMC +@@ -105,6 +105,34 @@ config MLXBF_PMC to performance monitoring counters within various blocks in the Mellanox BlueField SoC via a sysfs interface. @@ -65,31 +67,42 @@ index e3afbe6..dd6b576 100644 + will be called nvsw-bmc-hid162. + +config NVSW_HOST_L1 -+ tristate "Nvidia host CPLD/FPGA Hardware Control and Monitoring" ++ tristate "Nvidia L1 host CPLD/FPGA Hardware Control and Monitoring" + depends on REGMAP_I2C && OF && REGMAP && HWMON + help + Say Y here to include support for the FPGA/CPLD logic by host CPU -+ equipped on Nvidia switches. ++ equipped on Nvidia L1 switches. + This driver can also be built as a module. If so the module + will be called nvsw-host-l1. ++ ++config NVSW_HOST_SPC5 ++ tristate "Nvidia SPC5 host CPLD/FPGA Hardware Control and Monitoring" ++ depends on HWMON ++ select REGMAP_I2C ++ help ++ Say Y here to include support for the FPGA/CPLD logic by host CPU ++ equipped on Nvidia SPC5 ethernet switches. ++ This driver can also be built as a module. If so the module ++ will be called nvsw-host-spc5. + config NVSW_SN2201 tristate "Nvidia SN2201 platform driver support" depends on HWMON && I2C diff --git a/drivers/platform/mellanox/Makefile b/drivers/platform/mellanox/Makefile -index e86723b..4c1aec1 100644 +index e86723b44..a7c15b0aa 100644 --- a/drivers/platform/mellanox/Makefile +++ b/drivers/platform/mellanox/Makefile -@@ -11,4 +11,6 @@ obj-$(CONFIG_MLXREG_DPU) += mlxreg-dpu.o +@@ -11,4 +11,7 @@ obj-$(CONFIG_MLXREG_DPU) += mlxreg-dpu.o obj-$(CONFIG_MLXREG_HOTPLUG) += mlxreg-hotplug.o obj-$(CONFIG_MLXREG_IO) += mlxreg-io.o obj-$(CONFIG_MLXREG_LC) += mlxreg-lc.o +obj-$(CONFIG_NVSW_BMC_HID162) += nvsw-bmc-hid162.o nvsw-core.o +obj-$(CONFIG_NVSW_HOST_L1) += nvsw-host-l1.o nvsw-core.o ++obj-$(CONFIG_NVSW_HOST_SPC5) += nvsw-host-spc5.o nvsw-core.o obj-$(CONFIG_NVSW_SN2201) += nvsw-sn2201.o diff --git a/drivers/platform/mellanox/nvsw-bmc-hid162.c b/drivers/platform/mellanox/nvsw-bmc-hid162.c new file mode 100644 -index 00000000..fbc7382 +index 000000000..fbc738231 --- /dev/null +++ b/drivers/platform/mellanox/nvsw-bmc-hid162.c @@ -0,0 +1,2773 @@ @@ -2868,10 +2881,10 @@ index 00000000..fbc7382 +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/drivers/platform/mellanox/nvsw-core.c b/drivers/platform/mellanox/nvsw-core.c new file mode 100644 -index 00000000..bfe56ab +index 000000000..602a7fd85 --- /dev/null +++ b/drivers/platform/mellanox/nvsw-core.c -@@ -0,0 +1,625 @@ +@@ -0,0 +1,686 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Nvidia BMC platform driver @@ -2900,6 +2913,7 @@ index 00000000..bfe56ab + case NVSW_REG_PG3_EVENT_OFFSET: + case NVSW_REG_PG3_MASK_OFFSET: + case NVSW_REG_PG4_EVENT_OFFSET: ++ case NVSW_REG_PG4_MASK_OFFSET: + case NVSW_REG_RESET_GP1_OFFSET: + case NVSW_REG_FIELD_UPGRADE: + case NVSW_REG_GP0_OFFSET: @@ -2977,6 +2991,7 @@ index 00000000..bfe56ab + case NVSW_REG_CPLD4_VER_OFFSET: + case NVSW_REG_CPLD4_PN_OFFSET: + case NVSW_REG_CPLD4_PN1_OFFSET: ++ case NVSW_REG_CPLD7_VER_OFFSET: + case NVSW_REG_PG1_OFFSET: + case NVSW_REG_PG1_EVENT_OFFSET: + case NVSW_REG_PG1_MASK_OFFSET: @@ -2989,6 +3004,12 @@ index 00000000..bfe56ab + case NVSW_REG_PG4_OFFSET: + case NVSW_REG_PG4_EVENT_OFFSET: + case NVSW_REG_PG4_MASK_OFFSET: ++ case NVSW_REG_CPLD6_VER_OFFSET: ++ case NVSW_REG_CPLD6_PN_OFFSET: ++ case NVSW_REG_CPLD6_PN1_OFFSET: ++ case NVSW_REG_CPLD9_VER_OFFSET: ++ case NVSW_REG_CPLD10_PN_OFFSET: ++ case NVSW_REG_CPLD10_PN1_OFFSET: + case NVSW_REG_RESET_GP1_OFFSET: + case NVSW_REG_FIELD_UPGRADE: + case NVSW_REG_SAFE_BIOS_OFFSET: @@ -2999,10 +3020,13 @@ index 00000000..bfe56ab + case NVSW_REG_LED5_OFFSET: + case NVSW_REG_LED6_OFFSET: + case NVSW_REG_LED7_OFFSET: ++ case NVSW_REG_CPLD7_PN_OFFSET: ++ case NVSW_REG_CPLD7_PN1_OFFSET: + case NVSW_REG_RESET_GP2_OFFSET: + case NVSW_REG_GP0_RO_OFFSET: + case NVSW_REG_GP1_RO_OFFSET: + case NVSW_REG_GP4_RO_OFFSET: ++ case NVSW_REG_GP5_RO_OFFSET: + case NVSW_REG_GPCOM0_OFFSET: + case NVSW_REG_GP0_OFFSET: + case NVSW_REG_GP1_OFFSET: @@ -3042,9 +3066,15 @@ index 00000000..bfe56ab + case NVSW_REG_VR2_ALERT_OFFSET: + case NVSW_REG_VR2_ALERT_EVENT_OFFSET: + case NVSW_REG_VR2_ALERT_MASK_OFFSET: ++ case NVSW_REG_CPLD8_PN_OFFSET: ++ case NVSW_REG_CPLD8_PN1_OFFSET: ++ case NVSW_REG_CPLD8_VER_OFFSET: + case NVSW_REG_FAN_OFFSET: + case NVSW_REG_FAN_EVENT_OFFSET: + case NVSW_REG_FAN_MASK_OFFSET: ++ case NVSW_REG_CPLD5_VER_OFFSET: ++ case NVSW_REG_CPLD5_PN_OFFSET: ++ case NVSW_REG_CPLD5_PN1_OFFSET: + case NVSW_REG_EROT_OFFSET: + case NVSW_REG_EROT_EVENT_OFFSET: + case NVSW_REG_EROT_MASK_OFFSET: @@ -3084,16 +3114,26 @@ index 00000000..bfe56ab + case NVSW_REG_CONFIG2_OFFSET: + case NVSW_REG_CONFIG3_OFFSET: + case NVSW_REG_SPI_CHNL_SELECT: ++ case NVSW_REG_CPLD5_MVER_OFFSET: ++ case NVSW_REG_CPLD9_PN_OFFSET: ++ case NVSW_REG_CPLD9_PN1_OFFSET: ++ case NVSW_REG_CPLD10_VER_OFFSET: + case NVSW_REG_WD2_TMR_OFFSET: + case NVSW_REG_WD2_TLEFT_OFFSET: + case NVSW_REG_WD2_ACT_OFFSET: + case NVSW_REG_WD3_TMR_OFFSET: + case NVSW_REG_WD3_TLEFT_OFFSET: + case NVSW_REG_WD3_ACT_OFFSET: ++ case NVSW_REG_CPLD7_MVER_OFFSET: ++ case NVSW_REG_CPLD8_MVER_OFFSET: ++ case NVSW_REG_CPLD9_MVER_OFFSET: ++ case NVSW_REG_CPLD10_MVER_OFFSET: ++ case NVSW_REG_CPLD6_MVER_OFFSET: + case NVSW_REG_MUX0_OFFSET: + case NVSW_REG_MUX1_OFFSET: + case NVSW_REG_MUX2_OFFSET: + case NVSW_REG_UFM_VERSION_OFFSET: ++ case NVSW_REG_PSU_I2C_CAP_OFFSET: + return true; + } + return false; @@ -3114,6 +3154,7 @@ index 00000000..bfe56ab + case NVSW_REG_CPLD4_VER_OFFSET: + case NVSW_REG_CPLD4_PN_OFFSET: + case NVSW_REG_CPLD4_PN1_OFFSET: ++ case NVSW_REG_CPLD7_VER_OFFSET: + case NVSW_REG_PG1_OFFSET: + case NVSW_REG_PG1_EVENT_OFFSET: + case NVSW_REG_PG1_MASK_OFFSET: @@ -3126,6 +3167,12 @@ index 00000000..bfe56ab + case NVSW_REG_PG4_OFFSET: + case NVSW_REG_PG4_EVENT_OFFSET: + case NVSW_REG_PG4_MASK_OFFSET: ++ case NVSW_REG_CPLD6_VER_OFFSET: ++ case NVSW_REG_CPLD6_PN_OFFSET: ++ case NVSW_REG_CPLD6_PN1_OFFSET: ++ case NVSW_REG_CPLD9_VER_OFFSET: ++ case NVSW_REG_CPLD10_PN_OFFSET: ++ case NVSW_REG_CPLD10_PN1_OFFSET: + case NVSW_REG_RESET_GP1_OFFSET: + case NVSW_REG_FIELD_UPGRADE: + case NVSW_REG_SAFE_BIOS_OFFSET: @@ -3136,6 +3183,8 @@ index 00000000..bfe56ab + case NVSW_REG_LED5_OFFSET: + case NVSW_REG_LED6_OFFSET: + case NVSW_REG_LED7_OFFSET: ++ case NVSW_REG_CPLD7_PN_OFFSET: ++ case NVSW_REG_CPLD7_PN1_OFFSET: + case NVSW_REG_RESET_GP2_OFFSET: + case NVSW_REG_GP0_RO_OFFSET: + case NVSW_REG_GP1_RO_OFFSET: @@ -3178,9 +3227,15 @@ index 00000000..bfe56ab + case NVSW_REG_VR2_ALERT_OFFSET: + case NVSW_REG_VR2_ALERT_EVENT_OFFSET: + case NVSW_REG_VR2_ALERT_MASK_OFFSET: ++ case NVSW_REG_CPLD8_PN_OFFSET: ++ case NVSW_REG_CPLD8_PN1_OFFSET: ++ case NVSW_REG_CPLD8_VER_OFFSET: + case NVSW_REG_FAN_OFFSET: + case NVSW_REG_FAN_EVENT_OFFSET: + case NVSW_REG_FAN_MASK_OFFSET: ++ case NVSW_REG_CPLD5_VER_OFFSET: ++ case NVSW_REG_CPLD5_PN_OFFSET: ++ case NVSW_REG_CPLD5_PN1_OFFSET: + case NVSW_REG_EROT_OFFSET: + case NVSW_REG_EROT_EVENT_OFFSET: + case NVSW_REG_EROT_MASK_OFFSET: @@ -3197,6 +3252,7 @@ index 00000000..bfe56ab + case NVSW_REG_LEAK_EVENT_OFFSET: + case NVSW_REG_LEAK_MASK_OFFSET: + case NVSW_REG_GP4_RO_OFFSET: ++ case NVSW_REG_GP5_RO_OFFSET: + case NVSW_REG_CPLD1_MVER_OFFSET: + case NVSW_REG_CPLD2_MVER_OFFSET: + case NVSW_REG_CPLD3_MVER_OFFSET: @@ -3221,9 +3277,18 @@ index 00000000..bfe56ab + case NVSW_REG_CONFIG2_OFFSET: + case NVSW_REG_CONFIG3_OFFSET: + case NVSW_REG_SPI_CHNL_SELECT: ++ case NVSW_REG_CPLD5_MVER_OFFSET: ++ case NVSW_REG_CPLD9_PN_OFFSET: ++ case NVSW_REG_CPLD9_PN1_OFFSET: ++ case NVSW_REG_CPLD10_VER_OFFSET: + case NVSW_REG_WD2_TMR_OFFSET: + case NVSW_REG_WD2_TLEFT_OFFSET: + case NVSW_REG_WD2_ACT_OFFSET: ++ case NVSW_REG_CPLD7_MVER_OFFSET: ++ case NVSW_REG_CPLD8_MVER_OFFSET: ++ case NVSW_REG_CPLD9_MVER_OFFSET: ++ case NVSW_REG_CPLD10_MVER_OFFSET: ++ case NVSW_REG_CPLD6_MVER_OFFSET: + case NVSW_REG_WD3_TMR_OFFSET: + case NVSW_REG_WD3_TLEFT_OFFSET: + case NVSW_REG_WD3_ACT_OFFSET: @@ -3231,6 +3296,7 @@ index 00000000..bfe56ab + case NVSW_REG_MUX1_OFFSET: + case NVSW_REG_MUX2_OFFSET: + case NVSW_REG_UFM_VERSION_OFFSET: ++ case NVSW_REG_PSU_I2C_CAP_OFFSET: + return true; + } + return false; @@ -3311,6 +3377,7 @@ index 00000000..bfe56ab + sizeof(*nvsw_core->regio_data)); + if (IS_ERR(nvsw_core->regio)) { + err = PTR_ERR(nvsw_core->regio); ++ dev_err(nvsw_core->dev, "Failed to register mlxreg-io driver\n"); + goto fail_platform_io_register; + } + } @@ -3337,6 +3404,7 @@ index 00000000..bfe56ab + sizeof(*nvsw_core->led_data)); + if (IS_ERR(nvsw_core->led)) { + err = PTR_ERR(nvsw_core->led); ++ dev_err(nvsw_core->dev, "Failed to register leds-mlxreg driver\n"); + goto fail_platform_leds_register; + } + } @@ -3366,6 +3434,7 @@ index 00000000..bfe56ab + sizeof(*nvsw_core->wd_data[i])); + if (IS_ERR(nvsw_core->wd[i])) { + err = PTR_ERR(nvsw_core->wd[i]); ++ dev_err(nvsw_core->dev, "Failed to register mlx-wdt driver\n"); + goto fail_platform_wd_register; + } + } @@ -3422,6 +3491,11 @@ index 00000000..bfe56ab + switch (nvsw_core->regmap_type) { + case REGMAP_I2C: + nvsw_core->regmap = devm_regmap_init_i2c(nvsw_core->client, &nvsw_regmap_i2c_conf); ++ if (IS_ERR(nvsw_core->regmap)) { ++ dev_err(nvsw_core->dev, "Failed to create I2C regmap\n"); ++ err = PTR_ERR(nvsw_core->regmap); ++ return err; ++ } + break; + case REGMAP_IO: + if (nvsw_core->port_map) { @@ -3499,10 +3573,10 @@ index 00000000..bfe56ab +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/drivers/platform/mellanox/nvsw-host-l1.c b/drivers/platform/mellanox/nvsw-host-l1.c new file mode 100644 -index 00000000..ffe248b +index 000000000..46022cb99 --- /dev/null +++ b/drivers/platform/mellanox/nvsw-host-l1.c -@@ -0,0 +1,745 @@ +@@ -0,0 +1,744 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Nvidia BMC platform driver @@ -4247,13 +4321,955 @@ index 00000000..ffe248b +MODULE_AUTHOR("Vadim Pasternak "); +MODULE_DESCRIPTION("Nvidia platform driver"); +MODULE_LICENSE("Dual BSD/GPL"); +diff --git a/drivers/platform/mellanox/nvsw-host-spc5.c b/drivers/platform/mellanox/nvsw-host-spc5.c +new file mode 100644 +index 000000000..6d1c71cf4 +--- /dev/null ++++ b/drivers/platform/mellanox/nvsw-host-spc5.c +@@ -0,0 +1,937 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Nvidia BMC platform driver ++ * ++ * Copyright (C) 2025 Nvidia Technologies Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "nvsw.h" ++ ++#define NVSW_HOST_DEVICE_NAME "mlxplat" ++ ++/* LPC bus IO offsets */ ++#define NVSW_I2C_BASE_ADRR 0x2000 ++#define NVSW_REG_BASE_ADRR 0x2500 ++#define NVSW_LPC_IO_RANGE 0x100 ++#define NVSW_LPC_PIO_OFFSET 0x10000UL ++#define NVSW_REG_MUX1 (NVSW_REG_MUX1_OFFSET | NVSW_LPC_PIO_OFFSET) ++#define NVSW_REG_MUX2 (NVSW_REG_MUX0_OFFSET | NVSW_LPC_PIO_OFFSET) ++ ++/* Default I2C parent bus number */ ++#define NVSW_CPLD_PHYS_ADAPTER_DEF_NR 5 ++ ++/* Start channel numbers */ ++#define NVSW_PARENT_CH NVSW_CPLD_PHYS_ADAPTER_DEF_NR ++#define NVSW_MUX1_CH NVSW_CPLD_PHYS_ADAPTER_DEF_NR + 1 ++#define NVSW_MUX2_CH 64 ++ ++ ++/* Regions for LPC I2C controller and LPC base register space */ ++static const struct resource nvsw_host_io_resources[] = { ++ [0] = DEFINE_RES_NAMED(NVSW_I2C_BASE_ADRR, NVSW_LPC_IO_RANGE, ++ "nvsw_cpld_lpc_i2c_ctrl", IORESOURCE_IO), ++ [1] = DEFINE_RES_NAMED(NVSW_REG_BASE_ADRR, NVSW_LPC_IO_RANGE, ++ "nvsw_cpld_lpc_regs", IORESOURCE_IO), ++}; ++ ++/* SPC5 platform mgmt board mux channels */ ++static const int nvsw_host_spc5_mgmt_channels[] = { ++ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, ++ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, ++ 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, ++ 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58 ++}; ++ ++/* SPC5 platform ComEx board mux channels */ ++static const int nvsw_host_spc5_comex_channels[] = { ++ 1, 2, 3, 4, 5, 6, 7, 8 ++}; ++ ++/* SPC5 platform mux data */ ++static struct i2c_mux_reg_platform_data nvsw_host_spc5_mux_data[] = { ++ { ++ .parent = NVSW_PARENT_CH, ++ .base_nr = NVSW_MUX1_CH, ++ .write_only = 1, ++ .reg = (void __iomem *)NVSW_REG_MUX1, ++ .reg_size = 1, ++ .idle_in_use = 1, ++ .values = nvsw_host_spc5_mgmt_channels, ++ .n_values = ARRAY_SIZE(nvsw_host_spc5_mgmt_channels), ++ }, ++ { ++ .parent = NVSW_PARENT_CH, ++ .base_nr = NVSW_MUX2_CH, ++ .write_only = 1, ++ .reg = (void __iomem *)NVSW_REG_MUX2, ++ .reg_size = 1, ++ .idle_in_use = 1, ++ .values = nvsw_host_spc5_comex_channels, ++ .n_values = ARRAY_SIZE(nvsw_host_spc5_comex_channels), ++ }, ++}; ++ ++/* SPC5 platform i2c frequency data */ ++static struct mlxreg_core_data nvsw_mlxcpld_i2c_items_data[] = { ++ { ++ .reg = NVSW_REG_PSU_I2C_CAP_OFFSET, ++ .mask = NVSW_I2C_CAP_MASK, ++ .bit = NVSW_I2C_CAP_BIT, ++ }, ++}; ++ ++static struct mlxreg_core_item nvsw_mlxcpld_i2c_items[] = { ++ { ++ .data = nvsw_mlxcpld_i2c_items_data, ++ }, ++}; ++ ++/* SPC5 platform i2c data */ ++static struct mlxreg_core_hotplug_platform_data nvsw_mlxcpld_i2c_data = { ++ .items = nvsw_mlxcpld_i2c_items, ++ .cell = NVSW_REG_AGGR_OFFSET, ++ .mask = NVSW_AGGR_MASK_COMEX, ++ .cell_low = NVSW_REG_AGGRCO_OFFSET, ++ .mask_low = NVSW_LOW_AGGR_MASK_I2C, ++}; ++ ++static struct platform_device *nvsw_host_dev; ++static struct platform_device *nvsw_i2c_dev; ++static struct i2c_mux_reg_platform_data *nvsw_host_mux_data[NVSW_MUX_MAX]; ++static struct mlxreg_core_platform_data *nvsw_led_data; ++static struct mlxreg_core_platform_data *nvsw_regs_io_data; ++static struct mlxreg_core_hotplug_platform_data *nvsw_i2c_data; ++static struct mlxreg_core_platform_data *nvsw_wd_data[NVSW_WD_MAX]; ++static int mux_num; ++static enum nvsw_core_hid_type nvsw_host_hid; ++ ++/* Platform register access for SPC5 systems families data */ ++static struct mlxreg_core_data nvsw_host_spc5_regs_io_data[] = { ++ { ++ .label = "cpld1_version", ++ .reg = NVSW_REG_CPLD1_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld2_version", ++ .reg = NVSW_REG_CPLD2_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld3_version", ++ .reg = NVSW_REG_CPLD3_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld4_version", ++ .reg = NVSW_REG_CPLD4_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld5_version", ++ .reg = NVSW_REG_CPLD5_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld6_version", ++ .reg = NVSW_REG_CPLD6_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld7_version", ++ .reg = NVSW_REG_CPLD7_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld8_version", ++ .reg = NVSW_REG_CPLD8_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld9_version", ++ .reg = NVSW_REG_CPLD9_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld10_version", ++ .reg = NVSW_REG_CPLD10_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld1_pn", ++ .reg = NVSW_REG_CPLD1_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld2_pn", ++ .reg = NVSW_REG_CPLD2_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld3_pn", ++ .reg = NVSW_REG_CPLD3_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld4_pn", ++ .reg = NVSW_REG_CPLD4_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld5_pn", ++ .reg = NVSW_REG_CPLD5_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld6_pn", ++ .reg = NVSW_REG_CPLD6_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld7_pn", ++ .reg = NVSW_REG_CPLD7_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld8_pn", ++ .reg = NVSW_REG_CPLD8_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld9_pn", ++ .reg = NVSW_REG_CPLD9_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld10_pn", ++ .reg = NVSW_REG_CPLD10_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, ++ { ++ .label = "cpld1_version_min", ++ .reg = NVSW_REG_CPLD1_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld2_version_min", ++ .reg = NVSW_REG_CPLD2_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld3_version_min", ++ .reg = NVSW_REG_CPLD3_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld4_version_min", ++ .reg = NVSW_REG_CPLD4_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld5_version_min", ++ .reg = NVSW_REG_CPLD5_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld6_version_min", ++ .reg = NVSW_REG_CPLD6_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld7_version_min", ++ .reg = NVSW_REG_CPLD7_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld8_version_min", ++ .reg = NVSW_REG_CPLD8_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld9_version_min", ++ .reg = NVSW_REG_CPLD9_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "cpld10_version_min", ++ .reg = NVSW_REG_CPLD10_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "pwr_converter_prog_en", ++ .reg = NVSW_REG_GP7_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0644, ++ }, ++ { ++ .label = "graceful_pwr_off", ++ .reg = NVSW_REG_GP7_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_mctp_ready", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_shutdown_req", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "vpd_wp", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ .secured = 1, ++ }, ++ { ++ .label = "pcie_asic_reset_dis", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, ++ }, ++ { ++ .label = "shutdown_unlock", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, ++ }, ++ { ++ .label = "cpu_power_off_ready", ++ .reg = NVSW_REG_GP0_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "pwr_cycle", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0244, ++ }, ++ { ++ .label = "pwr_down", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0200, ++ }, ++ { ++ .label = "aux_pwr_cycle", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0200, ++ }, ++ { ++ .label = "bmc_to_cpu_ctrl", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, ++ }, ++ { ++ .label = "uart_sel", ++ .reg = NVSW_REG_GP1_OFFSET, ++ .mask = NVSW_UART_SEL_MASK, ++ .bit = 7, ++ .mode = 0644, ++ }, ++ { ++ .label = "leakage1", ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0444, ++ }, ++ { ++ .label = "leakage2", ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "leakage3", ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "leakage4", ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "leakage5", ++ .reg = NVSW_REG_LEAK_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "asic_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ }, ++ { ++ .label = "asic1_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0644, ++ }, ++ { ++ .label = "asic2_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "asic3_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, ++ }, ++ { ++ .label = "asic4_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0644, ++ }, ++ { ++ .label = "sgmii_phy_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0644, ++ }, ++ { ++ .label = "reset_long_pb", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_short_pb", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_aux_pwr_or_reload", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_swb_dc_dc_pwr_fail", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_platform", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_swb_wd", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_asic_thermal", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_comex_pwr_fail", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_soc", ++ .reg = NVSW_REG_RESET_CAUSE1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_system", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_sw_pwr_off", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_comex_thermal", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_pwr_converter_fail", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_main_51v", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_mgmt_pwr", ++ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "port80", ++ .reg = NVSW_REG_GP1_RO_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, ++ { ++ .label = "jtag_cap", ++ .reg = NVSW_REG_FU_CAP_OFFSET, ++ .mask = NVSW_FU_CAP_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "jtag_enable", ++ .reg = NVSW_REG_FIELD_UPGRADE, ++ .mask = GENMASK(1, 0), ++ .bit = 1, ++ .mode = 0644, ++ }, ++ { ++ .label = "asic_health", ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASIC_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "asic2_health", ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASIC2_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "asic3_health", ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASIC3_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "asic4_health", ++ .reg = NVSW_REG_ASIC1_HEALTH_OFFSET, ++ .mask = NVSW_ASIC4_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "asic1_pg_fail", ++ .reg = NVSW_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "asic2_pg_fail", ++ .reg = NVSW_REG_GP4_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "asic3_pg_fail", ++ .reg = NVSW_REG_GP5_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0444, ++ }, ++ { ++ .label = "asic4_pg_fail", ++ .reg = NVSW_REG_GP5_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0444, ++ }, ++ { ++ .label = "spi_chnl_select", ++ .reg = NVSW_REG_SPI_CHNL_SELECT, ++ .mask = GENMASK(7, 0), ++ .bit = 1, ++ .mode = 0644, ++ }, ++ { ++ .label = "pdb1_pwr_status", ++ .reg = NVSW_REG_GP0_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0644, ++ }, ++ { ++ .label = "pdb2_pwr_status", ++ .reg = NVSW_REG_GP0_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0644, ++ }, ++ { ++ .label = "pdb3_pwr_status", ++ .reg = NVSW_REG_GP0_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0644, ++ }, ++ { ++ .label = "pdb4_pwr_status", ++ .reg = NVSW_REG_GP0_RO_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0644, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data nvsw_host_spc5_regs_io = { ++ .data = nvsw_host_spc5_regs_io_data, ++ .counter = ARRAY_SIZE(nvsw_host_spc5_regs_io_data), ++}; ++ ++/* SPC5 platform led data */ ++static struct mlxreg_core_data nvsw_host_spc5_led_data[] = { ++ { ++ .label = "status:green", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK ++ }, ++ { ++ .label = "status:amber", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK ++ }, ++ { ++ .label = "power:green", ++ .mode = 0444, ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "power:amber", ++ .reg = NVSW_REG_LED1_OFFSET, ++ .mask = NVSW_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "uid:blue", ++ .reg = NVSW_REG_LED5_OFFSET, ++ .mask = NVSW_LED_LO_NIBBLE_MASK, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data nvsw_host_spc5_led = { ++ .data = nvsw_host_spc5_led_data, ++ .counter = ARRAY_SIZE(nvsw_host_spc5_led_data), ++}; ++ ++/* Watchdog type3 platform data */ ++static struct mlxreg_core_data nvsw_host_wd_main_regs_type3[] = { ++ { ++ .label = "action", ++ .reg = NVSW_REG_WD2_ACT_OFFSET, ++ .mask = NVSW_WD_RESET_ACT_MASK, ++ .bit = 0, ++ }, ++ { ++ .label = "timeout", ++ .reg = NVSW_REG_WD2_TMR_OFFSET, ++ .mask = NVSW_WD_TYPE2_TO_MASK, ++ .health_cntr = NVSW_WD3_DFLT_TIMEOUT, ++ }, ++ { ++ .label = "timeleft", ++ .reg = NVSW_REG_WD2_TMR_OFFSET, ++ .mask = NVSW_WD_TYPE2_TO_MASK, ++ }, ++ { ++ .label = "ping", ++ .reg = NVSW_REG_WD2_ACT_OFFSET, ++ .mask = NVSW_WD_RESET_ACT_MASK, ++ .bit = 0, ++ }, ++ { ++ .label = "reset", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .bit = 6, ++ }, ++}; ++ ++static struct mlxreg_core_data nvsw_host_wd_aux_regs_type3[] = { ++ { ++ .label = "action", ++ .reg = NVSW_REG_WD3_ACT_OFFSET, ++ .mask = NVSW_WD_FAN_ACT_MASK, ++ .bit = 4, ++ }, ++ { ++ .label = "timeout", ++ .reg = NVSW_REG_WD3_TMR_OFFSET, ++ .mask = NVSW_WD_TYPE2_TO_MASK, ++ .health_cntr = NVSW_WD3_DFLT_TIMEOUT, ++ }, ++ { ++ .label = "timeleft", ++ .reg = NVSW_REG_WD3_TMR_OFFSET, ++ .mask = NVSW_WD_TYPE2_TO_MASK, ++ }, ++ { ++ .label = "ping", ++ .reg = NVSW_REG_WD3_ACT_OFFSET, ++ .mask = NVSW_WD_FAN_ACT_MASK, ++ .bit = 4, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data nvsw_host_wd_set_type3[] = { ++ { ++ .data = nvsw_host_wd_main_regs_type3, ++ .counter = ARRAY_SIZE(nvsw_host_wd_main_regs_type3), ++ .version = MLX_WDT_TYPE3, ++ .identity = "mlx-wdt-main", ++ }, ++ { ++ .data = nvsw_host_wd_aux_regs_type3, ++ .counter = ARRAY_SIZE(nvsw_host_wd_aux_regs_type3), ++ .version = MLX_WDT_TYPE3, ++ .identity = "mlx-wdt-aux", ++ }, ++}; ++ ++/* IO port mapping callback. */ ++static void __iomem *nvsw_host_spc5_port_map(struct nvsw_core *nvsw_core) ++{ ++ return devm_ioport_map(nvsw_core->dev, nvsw_host_io_resources[1].start, 1); ++} ++ ++/* Mux init/exit callbacks. */ ++static int nvsw_host_spc5_mux_topology_init(struct nvsw_core *nvsw_core) ++{ ++ int i, err; ++ ++ if (!nvsw_i2c_data) ++ return 0; ++ ++ /* Create i2c infrastructure. */ ++ nvsw_i2c_data->regmap = nvsw_core->regmap; ++ nvsw_i2c_data->handle = nvsw_core; ++ ++ nvsw_i2c_dev = platform_device_register_resndata(nvsw_core->dev, "i2c_mlxcpld", ++ NVSW_CPLD_PHYS_ADAPTER_DEF_NR, NULL, 0, ++ nvsw_i2c_data, sizeof(*nvsw_i2c_data)); ++ if (IS_ERR(nvsw_i2c_dev)) { ++ err = PTR_ERR(nvsw_i2c_dev); ++ return err; ++ } ++ ++ /* Create mux infrastructure. */ ++ for (i = 0; i < nvsw_core->mux_num; i++) { ++ nvsw_core->mux[i] = ++ platform_device_register_resndata(nvsw_core->dev, "i2c-mux-reg", i, NULL, ++ 0, nvsw_host_mux_data[i], ++ sizeof(*nvsw_host_mux_data[i])); ++ if (IS_ERR(nvsw_core->mux[i])) { ++ dev_err(nvsw_core->dev, "Failed to create mux infra\n"); ++ err = PTR_ERR(nvsw_core->mux[i]); ++ goto fail_platform_mux_register; ++ } ++ } ++ ++ return 0; ++fail_platform_mux_register: ++ while (--i >= 0) ++ platform_device_unregister(nvsw_core->mux[i]); ++ return err; ++} ++ ++static void nvsw_host_spc5_mux_topology_exit(struct nvsw_core *nvsw_core) ++{ ++ int i; ++ ++ for (i = 0; i < nvsw_core->mux_num; i++) { ++ if (nvsw_core->mux[i]) ++ platform_device_unregister(nvsw_core->mux[i]); ++ } ++ ++ if (nvsw_i2c_dev) ++ platform_device_unregister(nvsw_i2c_dev); ++} ++ ++static int __init nvsw_host_register_platform_device(void) ++{ ++ nvsw_host_dev = platform_device_register_simple(NVSW_HOST_DEVICE_NAME, -1, ++ nvsw_host_io_resources, ++ ARRAY_SIZE(nvsw_host_io_resources)); ++ if (IS_ERR(nvsw_host_dev)) ++ return PTR_ERR(nvsw_host_dev); ++ return 1; ++} ++ ++static int __init nvsw_host_dmi_spc5_switch_matched(const struct dmi_system_id *dmi) ++{ ++ int i; ++ ++ /* Set system configuration. */ ++ nvsw_host_hid = HID181; ++ mux_num = ARRAY_SIZE(nvsw_host_spc5_mux_data); ++ for (i = 0; i < mux_num; i++) ++ nvsw_host_mux_data[i] = &nvsw_host_spc5_mux_data[i]; ++ nvsw_led_data = &nvsw_host_spc5_led; ++ nvsw_regs_io_data = &nvsw_host_spc5_regs_io; ++ for (i = 0; i < ARRAY_SIZE(nvsw_host_wd_set_type3); i++) ++ nvsw_wd_data[i] = &nvsw_host_wd_set_type3[i]; ++ nvsw_i2c_data = &nvsw_mlxcpld_i2c_data; ++ ++ return nvsw_host_register_platform_device(); ++} ++ ++static const struct dmi_system_id nvsw_host_dmi_table[] __initconst = { ++ { ++ .callback = nvsw_host_dmi_spc5_switch_matched, ++ .matches = { ++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0024"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI181"), ++ }, ++ }, ++ { ++ .callback = nvsw_host_dmi_spc5_switch_matched, ++ .matches = { ++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0024"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI182"), ++ }, ++ }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(dmi, nvsw_host_dmi_table); ++ ++static int nvsw_host_probe(struct platform_device *pdev) ++{ ++ struct nvsw_core *nvsw_core; ++ int i; ++ ++ nvsw_core = devm_kzalloc(&nvsw_host_dev->dev, sizeof(*nvsw_core), GFP_KERNEL); ++ if (!nvsw_core) ++ return -ENOMEM; ++ ++ /* Set system configuration. */ ++ nvsw_core->dev = &nvsw_host_dev->dev; ++ nvsw_core->hid = nvsw_host_hid; ++ nvsw_core->regmap_type = REGMAP_IO; ++ nvsw_core->mux_num = mux_num; ++ for (i = 0; i < ARRAY_SIZE(nvsw_wd_data); i++) ++ nvsw_core->wd_data[i] = nvsw_wd_data[i]; ++ nvsw_core->regio_data = nvsw_regs_io_data; ++ nvsw_core->led_data = nvsw_led_data; ++ nvsw_core->port_map = nvsw_host_spc5_port_map; ++ nvsw_core->mux_init = nvsw_host_spc5_mux_topology_init; ++ nvsw_core->mux_exit = nvsw_host_spc5_mux_topology_exit; ++ platform_set_drvdata(nvsw_host_dev, nvsw_core); ++ ++ return nvsw_core_init(nvsw_core); ++} ++ ++static void nvsw_host_remove(struct platform_device *pdev) ++{ ++ struct nvsw_core *nvsw_core = platform_get_drvdata(nvsw_host_dev); ++ ++ nvsw_core_exit(nvsw_core); ++} ++ ++static struct platform_driver nvsw_host_driver = { ++ .driver = { ++ .name = NVSW_HOST_DEVICE_NAME, ++ .probe_type = PROBE_FORCE_SYNCHRONOUS, ++ }, ++ .probe = nvsw_host_probe, ++ .remove = nvsw_host_remove, ++}; ++ ++static int __init nvsw_host_init(void) ++{ ++ if (!dmi_check_system(nvsw_host_dmi_table)) ++ return -ENODEV; ++ ++ return platform_driver_register(&nvsw_host_driver); ++} ++module_init(nvsw_host_init); ++ ++static void __exit nvsw_host_exit(void) ++{ ++ if (nvsw_host_dev) ++ platform_device_unregister(nvsw_host_dev); ++ ++ platform_driver_unregister(&nvsw_host_driver); ++} ++module_exit(nvsw_host_exit); ++ ++MODULE_AUTHOR("Vadim Pasternak "); ++MODULE_DESCRIPTION("Nvidia platform driver"); ++MODULE_LICENSE("Dual BSD/GPL"); + diff --git a/drivers/platform/mellanox/nvsw.h b/drivers/platform/mellanox/nvsw.h new file mode 100644 -index 00000000..b1ae4db +index 000000000..9a0b48409 --- /dev/null +++ b/drivers/platform/mellanox/nvsw.h -@@ -0,0 +1,260 @@ +@@ -0,0 +1,292 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Nvidia BMC platform driver @@ -4277,6 +5293,7 @@ index 00000000..b1ae4db +#define NVSW_REG_CPLD3_PN1_OFFSET 0x2509 +#define NVSW_REG_CPLD4_PN_OFFSET 0x250a +#define NVSW_REG_CPLD4_PN1_OFFSET 0x250b ++#define NVSW_REG_CPLD7_VER_OFFSET 0x2510 +#define NVSW_REG_PG1_OFFSET 0x2511 +#define NVSW_REG_PG1_EVENT_OFFSET 0x2512 +#define NVSW_REG_PG1_MASK_OFFSET 0x2513 @@ -4292,6 +5309,8 @@ index 00000000..b1ae4db +#define NVSW_REG_LED5_OFFSET 0x2524 +#define NVSW_REG_LED6_OFFSET 0x2525 +#define NVSW_REG_LED7_OFFSET 0x2526 ++#define NVSW_REG_CPLD7_PN_OFFSET 0x2528 ++#define NVSW_REG_CPLD7_PN1_OFFSET 0x2529 +#define NVSW_REG_GP0_RO_OFFSET 0x252a +#define NVSW_REG_GP1_RO_OFFSET 0x252c +#define NVSW_REG_GPCOM0_OFFSET 0x252d @@ -4299,6 +5318,7 @@ index 00000000..b1ae4db +#define NVSW_REG_GP7_OFFSET 0x252f +#define NVSW_REG_GP1_OFFSET 0x2530 +#define NVSW_REG_GP4_OFFSET 0x2532 ++#define NVSW_REG_GP5_RO_OFFSET 0x2533 +#define NVSW_REG_FIELD_UPGRADE 0x2534 +#define NVSW_REG_SAFE_BIOS_OFFSET 0x2535 +#define NVSW_REG_PWM_CONTROL_OFFSET 0x2537 @@ -4332,18 +5352,30 @@ index 00000000..b1ae4db +#define NVSW_REG_VR2_ALERT_OFFSET 0x255e +#define NVSW_REG_VR2_ALERT_EVENT_OFFSET 0x255f +#define NVSW_REG_VR2_ALERT_MASK_OFFSET 0x2560 ++#define NVSW_REG_CPLD8_PN_OFFSET 0x2573 ++#define NVSW_REG_CPLD8_PN1_OFFSET 0x2574 ++#define NVSW_REG_CPLD6_VER_OFFSET 0x2575 +#define NVSW_REG_PG3_OFFSET 0x2576 +#define NVSW_REG_PG3_EVENT_OFFSET 0x2577 +#define NVSW_REG_PG3_MASK_OFFSET 0x2578 +#define NVSW_REG_PG4_OFFSET 0x2579 +#define NVSW_REG_PG4_EVENT_OFFSET 0x257a +#define NVSW_REG_PG4_MASK_OFFSET 0x257b ++#define NVSW_REG_CPLD6_PN_OFFSET 0x257c ++#define NVSW_REG_CPLD6_PN1_OFFSET 0x257d ++#define NVSW_REG_CPLD9_PN_OFFSET 0x257e ++#define NVSW_REG_CPLD9_PN1_OFFSET 0x257f ++#define NVSW_REG_CPLD10_PN_OFFSET 0x2580 ++#define NVSW_REG_CPLD10_PN1_OFFSET 0x2581 +#define NVSW_REG_ASIC3_HEALTH_OFFSET 0x2582 +#define NVSW_REG_ASIC3_EVENT_OFFSET 0x2583 +#define NVSW_REG_ASIC3_MASK_OFFSET 0x2584 +#define NVSW_REG_FAN_OFFSET 0x2588 +#define NVSW_REG_FAN_EVENT_OFFSET 0x2589 +#define NVSW_REG_FAN_MASK_OFFSET 0x258a ++#define NVSW_REG_CPLD5_VER_OFFSET 0x258e ++#define NVSW_REG_CPLD5_PN_OFFSET 0x258f ++#define NVSW_REG_CPLD5_PN1_OFFSET 0x2590 +#define NVSW_REG_EROT_OFFSET 0x2591 +#define NVSW_REG_EROT_EVENT_OFFSET 0x2592 +#define NVSW_REG_EROT_MASK_OFFSET 0x2593 @@ -4361,12 +5393,21 @@ index 00000000..b1ae4db +#define NVSW_REG_LEAK_MASK_OFFSET 0x25b1 +#define NVSW_REG_GP4_RO_OFFSET 0x25c2 +#define NVSW_REG_SPI_CHNL_SELECT 0x25c3 ++#define NVSW_REG_CPLD5_MVER_OFFSET 0x25c4 ++#define NVSW_REG_CPLD8_VER_OFFSET 0x25c8 ++#define NVSW_REG_CPLD9_VER_OFFSET 0x25c9 ++#define NVSW_REG_CPLD10_VER_OFFSET 0x25ca +#define NVSW_REG_WD2_TMR_OFFSET 0x25cd +#define NVSW_REG_WD2_TLEFT_OFFSET 0x25ce +#define NVSW_REG_WD2_ACT_OFFSET 0x25cf +#define NVSW_REG_WD3_TMR_OFFSET 0x25d1 +#define NVSW_REG_WD3_TLEFT_OFFSET 0x25d2 +#define NVSW_REG_WD3_ACT_OFFSET 0x25d3 ++#define NVSW_REG_CPLD7_MVER_OFFSET 0x25d5 ++#define NVSW_REG_CPLD8_MVER_OFFSET 0x25d6 ++#define NVSW_REG_CPLD9_MVER_OFFSET 0x25d7 ++#define NVSW_REG_CPLD10_MVER_OFFSET 0x25d8 ++#define NVSW_REG_CPLD6_MVER_OFFSET 0x25d9 +#define NVSW_REG_MUX0_OFFSET 0x25da +#define NVSW_REG_MUX1_OFFSET 0x25db +#define NVSW_REG_MUX2_OFFSET 0x25dc @@ -4391,6 +5432,7 @@ index 00000000..b1ae4db +#define NVSW_REG_FAN_CAP1_OFFSET 0x25f5 +#define NVSW_REG_FAN_DRW_CAP_OFFSET 0x25f7 +#define NVSW_REG_TACHO_SPEED_OFFSET 0x25f8 ++#define NVSW_REG_PSU_I2C_CAP_OFFSET 0x25f9 +#define NVSW_REG_CONFIG1_OFFSET 0x25fb +#define NVSW_REG_CONFIG2_OFFSET 0x25fc +#define NVSW_REG_CONFIG3_OFFSET 0x25fd @@ -4398,6 +5440,7 @@ index 00000000..b1ae4db +#define NVSW_REG_MAX 0x26ff + +#define NVSW_AGGR_MASK_COMEX BIT(0) ++#define NVSW_LOW_AGGR_MASK_I2C BIT(6) +#define NVSW_AGGR_MASK BIT(2) +#define NVSW_LOW_AGGR_MASK_LOW 0xe0 +#define NVSW_REG_FRU1_MASK GENMASK(3, 0) @@ -4435,11 +5478,14 @@ index 00000000..b1ae4db +#define NVSW_UART_SEL_MASK GENMASK(7, 6) +#define NVSW_BIOS_STATUS_MASK GENMASK(3, 1) +#define NVSW_REG_RESET_MASK BIT(1) ++#define NVSW_MASTER_MASK BIT(5) +#define NVSW_FU_CAP_MASK GENMASK(1, 0) +#define NVSW_WD_RESET_ACT_MASK GENMASK(7, 1) +#define NVSW_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4)) +#define NVSW_WD_TYPE2_TO_MASK 0 +#define NVSW_WD3_DFLT_TIMEOUT 600 ++#define NVSW_I2C_CAP_BIT 0x04 ++#define NVSW_I2C_CAP_MASK GENMASK(5, NVSW_I2C_CAP_BIT) + +#define NVSW_NR_NONE -1 +#define NVSW_MUX_MAX 2 @@ -4451,6 +5497,8 @@ index 00000000..b1ae4db + HID176, + HID177, + HID180, ++ HID181, ++ HID182, +}; + + /* The system register map type. */ @@ -4515,5 +5563,5 @@ index 00000000..b1ae4db +#endif /* !defined(__NVSW_H__) */ + -- -2.8.4 +2.34.1 diff --git a/patches-sonic/0056-hwmon-pmbus-mp2845-Add-support-for-MP2845-device.patch b/patches-sonic/0056-hwmon-pmbus-mp2845-Add-support-for-MP2845-device.patch new file mode 100644 index 000000000..759686528 --- /dev/null +++ b/patches-sonic/0056-hwmon-pmbus-mp2845-Add-support-for-MP2845-device.patch @@ -0,0 +1,555 @@ +From d44afa51c9fad533b29de8a06f43fa94b44959e7 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Wed, 3 Dec 2025 17:07:17 +0200 +Subject: [PATCH hwmon-next 1/2] hwmon: (pmbus/mp2845): Add support for MP2845 + device + +Add support for MPS device MP2845 - Digital Multi-Phase Power +Controller. + +The MP2845 is a Digital, Multi-Phase PWM Controller with PMBus and +PWM-VID manufactured by Monolithic Power Systems (MPS) designed for +efficient power management in high-performance computing applications. + +Signed-off-by: Vadim Pasternak +--- + drivers/hwmon/pmbus/Kconfig | 9 + + drivers/hwmon/pmbus/Makefile | 1 + + drivers/hwmon/pmbus/mp2845.c | 493 +++++++++++++++++++++++++++++++++++ + 3 files changed, 503 insertions(+) + create mode 100644 drivers/hwmon/pmbus/mp2845.c + +diff --git a/drivers/hwmon/pmbus/Kconfig b/drivers/hwmon/pmbus/Kconfig +index a4f02cad92fd..c26b19e3d0e6 100644 +--- a/drivers/hwmon/pmbus/Kconfig ++++ b/drivers/hwmon/pmbus/Kconfig +@@ -319,6 +319,15 @@ config SENSORS_MAX8688 + This driver can also be built as a module. If so, the module will + be called max8688. + ++config SENSORS_MP2845 ++ tristate "MPS MP2845" ++ help ++ If you say yes here you get hardware monitoring support for MPS ++ MP2845 Digital Multi-Phase Power Controller. ++ ++ This driver can also be built as a module. If so, the module will ++ be called mp2845. ++ + config SENSORS_MP2856 + tristate "MPS MP2856" + help +diff --git a/drivers/hwmon/pmbus/Makefile b/drivers/hwmon/pmbus/Makefile +index d00bcc758b97..fec1bf832535 100644 +--- a/drivers/hwmon/pmbus/Makefile ++++ b/drivers/hwmon/pmbus/Makefile +@@ -34,6 +34,7 @@ obj-$(CONFIG_SENSORS_MAX20751) += max20751.o + obj-$(CONFIG_SENSORS_MAX31785) += max31785.o + obj-$(CONFIG_SENSORS_MAX34440) += max34440.o + obj-$(CONFIG_SENSORS_MAX8688) += max8688.o ++obj-$(CONFIG_SENSORS_MP2845) += mp2845.o + obj-$(CONFIG_SENSORS_MP2856) += mp2856.o + obj-$(CONFIG_SENSORS_MP2888) += mp2888.o + obj-$(CONFIG_SENSORS_MP2891) += mp2891.o +diff --git a/drivers/hwmon/pmbus/mp2845.c b/drivers/hwmon/pmbus/mp2845.c +new file mode 100644 +index 000000000000..96d3dc59e84a +--- /dev/null ++++ b/drivers/hwmon/pmbus/mp2845.c +@@ -0,0 +1,493 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Hardware monitoring driver for MPS Digital Controller(MP2845) ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MP2845_IOUT_SCALE_MASK1 GENMASK(5, 3) ++#define MP2845_IOUT_SCALE_MASK2 GENMASK(13, 11) ++ ++#define MFR_VIN_OV_UV_SET 0x71 ++#define MFR_OVUV_OCWARN_THRES 0x75 ++#define MFR_TOTAL_OCP_SET 0x76 ++#define MFR_PROTECT_STATUS1 0x80 ++#define MFR_PROTECT_STATUS2 0x81 ++ ++#define MP2845_VIN_LIMIT_UINT 125 ++#define MP2845_READ_VIN_UINT 3125 ++#define MP2845_READ_VIN_DIV 100 ++#define MP2845_READ_IOUT_UINT 3125 ++#define MP2845_READ_IOUT_DIV 100 ++#define MP2845_READ_VOUT_UINT 5 ++#define MP2845_TEMP_UINT 1000 ++ ++#define MFR_READ_VIN 0xA6 ++#define MFR_READ_VOUT 0xA7 ++#define MFR_READ_IOUT 0xA8 ++#define MFR_READ_TEMP 0xA9 ++#define MFR_MFG_ID_SCALE_VI1 0x77 ++#define MFR_MFG_ID_SCALE_VI2 0x78 ++ ++struct mp2845_data { ++ struct i2c_client *client; ++ int iout_gain[4]; ++ /* lock for preventing concurrency issue */ ++ struct mutex lock; ++}; ++ ++static umode_t mp2845_is_visible(const void *data, enum hwmon_sensor_types type, ++ u32 attr, int channel) ++{ ++ switch (type) { ++ case hwmon_temp: ++ case hwmon_in: ++ case hwmon_curr: ++ return 0444; ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++static int mp2845_read_string(struct device *dev, enum hwmon_sensor_types type, ++ u32 attr, int channel, const char **str) ++{ ++ struct mp2845_data *data; ++ int ret = 0; ++ ++ data = dev_get_drvdata(dev); ++ ++ mutex_lock(&data->lock); ++ ++ switch (type) { ++ case hwmon_in: ++ if (channel == 0) ++ *str = "vin"; ++ else if (channel == 1) ++ *str = "vout1"; ++ else if (channel == 2) ++ *str = "vout2"; ++ else if (channel == 3) ++ *str = "vout3"; ++ else ++ *str = "vout4"; ++ break; ++ case hwmon_curr: ++ if (channel == 0) ++ *str = "iout1"; ++ else if (channel == 1) ++ *str = "iout2"; ++ else if (channel == 2) ++ *str = "iout3"; ++ else ++ *str = "iout4"; ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ mutex_unlock(&data->lock); ++ ++ return ret; ++} ++ ++static int mp2845_read(struct device *dev, enum hwmon_sensor_types type, ++ u32 attr, int channel, long *val) ++{ ++ int ret; ++ struct mp2845_data *data; ++ ++ data = dev_get_drvdata(dev); ++ if (!data) ++ return -ENOMEM; ++ ++ mutex_lock(&data->lock); ++ ++ switch (type) { ++ case hwmon_in: ++ if (channel == 0) { ++ if (attr == hwmon_in_input) { ++ ret = i2c_smbus_write_byte_data(data->client, 0, 0); ++ if (ret < 0) ++ break; ++ ++ ret = i2c_smbus_read_word_data(data->client, MFR_READ_VIN); ++ if (ret < 0) ++ break; ++ ++ *val = DIV_ROUND_CLOSEST((ret & GENMASK(9, 0)) * ++ MP2845_READ_VIN_UINT, ++ MP2845_READ_VIN_DIV); ++ } else if (attr == hwmon_in_crit) { ++ ret = i2c_smbus_write_byte_data(data->client, 0, 0); ++ if (ret < 0) ++ break; ++ ++ ret = i2c_smbus_read_word_data(data->client, MFR_VIN_OV_UV_SET); ++ if (ret < 0) ++ break; ++ ++ *val = FIELD_GET(GENMASK(15, 8), ret) * MP2845_VIN_LIMIT_UINT; ++ } else if (attr == hwmon_in_min) { ++ ret = i2c_smbus_write_byte_data(data->client, 0, 0); ++ if (ret < 0) ++ break; ++ ++ ret = i2c_smbus_read_word_data(data->client, MFR_VIN_OV_UV_SET); ++ if (ret < 0) ++ break; ++ ++ *val = FIELD_GET(GENMASK(7, 0), ret) * MP2845_VIN_LIMIT_UINT; ++ } else if (attr == hwmon_in_crit_alarm) { ++ ret = i2c_smbus_write_byte_data(data->client, 0, 0); ++ if (ret < 0) ++ break; ++ ++ ret = i2c_smbus_read_word_data(data->client, MFR_PROTECT_STATUS2); ++ if (ret < 0) ++ break; ++ ++ *val = FIELD_GET(GENMASK(5, 5), ret); ++ } else { ++ ret = i2c_smbus_write_byte_data(data->client, 0, 0); ++ if (ret < 0) ++ break; ++ ++ ret = i2c_smbus_read_word_data(data->client, MFR_PROTECT_STATUS2); ++ if (ret < 0) ++ break; ++ ++ *val = FIELD_GET(GENMASK(4, 4), ret); ++ } ++ } else { ++ if (attr == hwmon_in_input) { ++ ret = i2c_smbus_write_byte_data(data->client, 0, channel - 1); ++ if (ret < 0) ++ break; ++ ++ ret = i2c_smbus_read_word_data(data->client, MFR_READ_VOUT); ++ if (ret < 0) ++ break; ++ ++ *val = (ret & GENMASK(9, 0)) * MP2845_READ_VOUT_UINT; ++ } else if (attr == hwmon_in_crit_alarm) { ++ ret = i2c_smbus_write_byte_data(data->client, 0, 0); ++ if (ret < 0) ++ break; ++ ++ ret = i2c_smbus_read_word_data(data->client, MFR_PROTECT_STATUS1); ++ if (ret < 0) ++ break; ++ ++ if (channel == 1) ++ *val = FIELD_GET(GENMASK(10, 10), ret); ++ else if (channel == 2) ++ *val = FIELD_GET(GENMASK(7, 7), ret); ++ else if (channel == 3) ++ *val = FIELD_GET(GENMASK(4, 4), ret); ++ else ++ *val = FIELD_GET(GENMASK(1, 1), ret); ++ } else { ++ ret = i2c_smbus_write_byte_data(data->client, 0, 0); ++ if (ret < 0) ++ break; ++ ++ ret = i2c_smbus_read_word_data(data->client, MFR_PROTECT_STATUS1); ++ if (ret < 0) ++ break; ++ ++ if (channel == 1) ++ *val = FIELD_GET(GENMASK(11, 11), ret); ++ else if (channel == 2) ++ *val = FIELD_GET(GENMASK(8, 8), ret); ++ else if (channel == 3) ++ *val = FIELD_GET(GENMASK(5, 5), ret); ++ else ++ *val = FIELD_GET(GENMASK(2, 2), ret); ++ } ++ } ++ break; ++ case hwmon_temp: ++ if (attr == hwmon_temp_input) { ++ ret = i2c_smbus_write_byte_data(data->client, 0, channel); ++ if (ret < 0) ++ break; ++ ++ ret = i2c_smbus_read_word_data(data->client, MFR_READ_TEMP); ++ if (ret < 0) ++ break; ++ ++ *val = ((ret & GENMASK(7, 0)) - 40) * MP2845_TEMP_UINT; ++ } else { ++ ret = i2c_smbus_write_byte_data(data->client, 0, 0); ++ if (ret < 0) ++ break; ++ ++ ret = i2c_smbus_read_word_data(data->client, MFR_PROTECT_STATUS1); ++ if (ret < 0) ++ break; ++ ++ if (channel == 0) { ++ *val = FIELD_GET(GENMASK(12, 12), ret); ++ } else if (channel == 1) { ++ *val = FIELD_GET(GENMASK(14, 14), ret); ++ } else if (channel == 2) { ++ ret = i2c_smbus_read_word_data(data->client, MFR_PROTECT_STATUS2); ++ if (ret < 0) ++ break; ++ ++ *val = FIELD_GET(GENMASK(0, 0), ret); ++ } else { ++ ret = i2c_smbus_read_word_data(data->client, MFR_PROTECT_STATUS2); ++ if (ret < 0) ++ break; ++ ++ *val = FIELD_GET(GENMASK(2, 2), ret); ++ } ++ } ++ break; ++ case hwmon_curr: ++ if (attr == hwmon_curr_input) { ++ ret = i2c_smbus_write_byte_data(data->client, 0, channel); ++ if (ret < 0) ++ break; ++ ++ ret = i2c_smbus_read_word_data(data->client, MFR_READ_IOUT); ++ if (ret < 0) ++ break; ++ ++ *val = DIV_ROUND_CLOSEST((ret & GENMASK(9, 0)) * data->iout_gain[channel] * ++ MP2845_READ_IOUT_UINT, MP2845_READ_IOUT_DIV); ++ } else if (attr == hwmon_curr_max) { ++ ret = i2c_smbus_write_byte_data(data->client, 0, channel); ++ if (ret < 0) ++ break; ++ ++ ret = i2c_smbus_read_word_data(data->client, MFR_OVUV_OCWARN_THRES); ++ if (ret < 0) ++ break; ++ ++ *val = DIV_ROUND_CLOSEST(FIELD_GET(GENMASK(15, 8), ret) * ++ data->iout_gain[channel] * MP2845_READ_IOUT_UINT * ++ 4 * 2, MP2845_READ_IOUT_DIV); ++ } else if (attr == hwmon_curr_crit) { ++ ret = i2c_smbus_write_byte_data(data->client, 0, channel); ++ if (ret < 0) ++ break; ++ ++ ret = i2c_smbus_read_word_data(data->client, MFR_TOTAL_OCP_SET); ++ if (ret < 0) ++ break; ++ ++ *val = DIV_ROUND_CLOSEST(FIELD_GET(GENMASK(15, 8), ret) * ++ data->iout_gain[channel] * MP2845_READ_IOUT_UINT * ++ 4 * 2, MP2845_READ_IOUT_DIV); ++ } else { ++ ret = i2c_smbus_write_byte_data(data->client, 0, 0); ++ if (ret < 0) ++ break; ++ ++ ret = i2c_smbus_read_word_data(data->client, MFR_PROTECT_STATUS1); ++ if (ret < 0) ++ break; ++ ++ if (channel == 0) ++ *val = FIELD_GET(GENMASK(9, 9), ret); ++ else if (channel == 2) ++ *val = FIELD_GET(GENMASK(6, 6), ret); ++ else if (channel == 3) ++ *val = FIELD_GET(GENMASK(3, 3), ret); ++ else ++ *val = FIELD_GET(GENMASK(0, 0), ret); ++ } ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ mutex_unlock(&data->lock); ++ ++ return ret; ++} ++ ++static int ++mp2845_identify_iout_scale(struct mp2845_data *data, int page) ++{ ++ int gain; ++ int ret; ++ ++ ret = i2c_smbus_write_byte_data(data->client, 0x00, page); ++ if (ret < 0) ++ return ret; ++ ++ ret = i2c_smbus_read_word_data(data->client, page == 0 ? MFR_MFG_ID_SCALE_VI2 : ++ MFR_MFG_ID_SCALE_VI1); ++ if (ret < 0) ++ return ret; ++ ++ gain = page == 0 ? FIELD_GET(MP2845_IOUT_SCALE_MASK1, ret) : ++ FIELD_GET(MP2845_IOUT_SCALE_MASK2, ret); ++ switch (gain) { ++ case 1: ++ data->iout_gain[page] = 1; ++ break; ++ case 2: ++ data->iout_gain[page] = 2; ++ break; ++ case 3: ++ data->iout_gain[page] = 4; ++ break; ++ case 4: ++ data->iout_gain[page] = 8; ++ break; ++ case 5: ++ data->iout_gain[page] = 16; ++ break; ++ case 6: ++ data->iout_gain[page] = 32; ++ break; ++ case 7: ++ data->iout_gain[page] = 64; ++ break; ++ default: ++ data->iout_gain[page] = 1; ++ break; ++ } ++ ++ return 0; ++} ++ ++static const struct hwmon_channel_info *mp2845_info[] = { ++ HWMON_CHANNEL_INFO(in, ++ HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_CRIT | HWMON_I_CRIT_ALARM | ++ HWMON_I_LCRIT_ALARM | HWMON_I_LABEL, ++ HWMON_I_INPUT | HWMON_I_CRIT_ALARM | HWMON_I_LCRIT_ALARM | ++ HWMON_I_LABEL, ++ HWMON_I_INPUT | HWMON_I_CRIT_ALARM | HWMON_I_LCRIT_ALARM | ++ HWMON_I_LABEL, ++ HWMON_I_INPUT | HWMON_I_CRIT_ALARM | HWMON_I_LCRIT_ALARM | ++ HWMON_I_LABEL, ++ HWMON_I_INPUT | HWMON_I_CRIT_ALARM | HWMON_I_LCRIT_ALARM | ++ HWMON_I_LABEL), ++ HWMON_CHANNEL_INFO(temp, ++ HWMON_T_INPUT | HWMON_T_CRIT_ALARM, ++ HWMON_T_INPUT | HWMON_T_CRIT_ALARM, ++ HWMON_T_INPUT | HWMON_T_CRIT_ALARM, ++ HWMON_T_INPUT | HWMON_T_CRIT_ALARM), ++ HWMON_CHANNEL_INFO(curr, ++ HWMON_C_INPUT | HWMON_C_CRIT | HWMON_C_CRIT_ALARM | HWMON_C_MAX | ++ HWMON_C_LABEL, ++ HWMON_C_INPUT | HWMON_C_CRIT | HWMON_C_CRIT_ALARM | HWMON_C_MAX | ++ HWMON_C_LABEL, ++ HWMON_C_INPUT | HWMON_C_CRIT | HWMON_C_CRIT_ALARM | HWMON_C_MAX | ++ HWMON_C_LABEL, ++ HWMON_C_INPUT | HWMON_C_CRIT | HWMON_C_CRIT_ALARM | HWMON_C_MAX | ++ HWMON_C_LABEL), ++ NULL ++}; ++ ++static const struct hwmon_ops mp2845_hwmon_ops = { ++ .is_visible = mp2845_is_visible, ++ .read = mp2845_read, ++ .read_string = mp2845_read_string, ++}; ++ ++static const struct hwmon_chip_info mp2845_chip_info = { ++ .ops = &mp2845_hwmon_ops, ++ .info = mp2845_info, ++}; ++ ++static int mp2845_probe(struct i2c_client *client) ++{ ++ struct device *dev = &client->dev; ++ struct device *hwmon_dev; ++ struct mp2845_data *data; ++ int ret; ++ ++ if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA | ++ I2C_FUNC_SMBUS_WORD_DATA)) { ++ dev_err(dev, "check failed, smbus byte and/or word data not supported!\n"); ++ return -ENODEV; ++ } ++ ++ data = devm_kzalloc(dev, sizeof(struct mp2845_data), GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ mutex_init(&data->lock); ++ data->client = client; ++ ++ ret = mp2845_identify_iout_scale(data, 0); ++ if (ret < 0) { ++ dev_err(dev, "unable to identify rail1 iout scale, errno = %d\n", ret); ++ return ret; ++ } ++ ++ ret = mp2845_identify_iout_scale(data, 1); ++ if (ret < 0) { ++ dev_err(dev, "unable to identify rail2 iout scale, errno = %d\n", ret); ++ return ret; ++ } ++ ++ ret = mp2845_identify_iout_scale(data, 2); ++ if (ret < 0) { ++ dev_err(dev, "unable to identify rail3 iout scale, errno = %d\n", ret); ++ return ret; ++ } ++ ++ ret = mp2845_identify_iout_scale(data, 3); ++ if (ret < 0) { ++ dev_err(dev, "unable to identify rail4 iout scale, errno = %d\n", ret); ++ return ret; ++ } ++ ++ hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, ++ data, &mp2845_chip_info, ++ NULL); ++ if (IS_ERR(hwmon_dev)) { ++ dev_err(dev, "unable to register mp2845 hwmon device\n"); ++ return PTR_ERR(hwmon_dev); ++ } ++ ++ dev_info(dev, "%s: sensor '%s'\n", dev_name(hwmon_dev), client->name); ++ ++ return 0; ++} ++ ++static const struct i2c_device_id mp2845_ids[] = { ++ {"mp2845", 0}, ++ {} ++}; ++MODULE_DEVICE_TABLE(i2c, mp2845_ids); ++ ++static const struct of_device_id __maybe_unused mp2845_of_match[] = { ++ {.compatible = "mps,mp2845"}, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, mp2845_of_match); ++ ++static struct i2c_driver mp2845_driver = { ++ .class = I2C_CLASS_HWMON, ++ .driver = { ++ .name = "mp2845", ++ .of_match_table = mp2845_of_match, ++ }, ++ .probe = mp2845_probe, ++ .id_table = mp2845_ids, ++}; ++module_i2c_driver(mp2845_driver); ++ ++MODULE_AUTHOR("Noah Wang "); ++MODULE_DESCRIPTION("MP2845 driver"); ++MODULE_LICENSE("GPL"); +-- +2.34.1 + diff --git a/patches-sonic/0057-hwmon-pmbus-mp5926-Add-support-for-MP5926-device.patch b/patches-sonic/0057-hwmon-pmbus-mp5926-Add-support-for-MP5926-device.patch new file mode 100644 index 000000000..5771c4c3a --- /dev/null +++ b/patches-sonic/0057-hwmon-pmbus-mp5926-Add-support-for-MP5926-device.patch @@ -0,0 +1,253 @@ +From 228bd9ebb65446d2947195655a3657cbba33ce99 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Wed, 3 Dec 2025 19:18:38 +0200 +Subject: [PATCH hwmon-next 2/2] hwmon: (pmbus/mp5926): Add support for device + MP5926 + +Add support for MPS device MP5926. + +The MP5926 is a high voltage hot-swap controller capable of operating +with supplies 8V to 80V. The MP5926 provides a controlled soft start +during hot insertion to ensure a controlled output voltage ramp occurs. + +Signed-off-by: Vadim Pasternak +--- + drivers/hwmon/pmbus/Kconfig | 9 ++ + drivers/hwmon/pmbus/Makefile | 1 + + drivers/hwmon/pmbus/mp5926.c | 192 +++++++++++++++++++++++++++++++++++ + 3 files changed, 202 insertions(+) + create mode 100644 drivers/hwmon/pmbus/mp5926.c + +diff --git a/drivers/hwmon/pmbus/Kconfig b/drivers/hwmon/pmbus/Kconfig +index c26b19e3d0e6..66c83ed64fb1 100644 +--- a/drivers/hwmon/pmbus/Kconfig ++++ b/drivers/hwmon/pmbus/Kconfig +@@ -398,6 +398,15 @@ config SENSORS_MP5920 + This driver can also be built as a module. If so, the module will + be called mp5920. + ++config SENSORS_MP5926 ++ tristate "MPS MP5926" ++ help ++ If you say yes here you get hardware monitoring support for MPS ++ MP5926 Controller. ++ ++ This driver can also be built as a module. If so, the module will ++ be called mp5926. ++ + config SENSORS_MP5990 + tristate "MPS MP5990" + help +diff --git a/drivers/hwmon/pmbus/Makefile b/drivers/hwmon/pmbus/Makefile +index fec1bf832535..5b1d67f26242 100644 +--- a/drivers/hwmon/pmbus/Makefile ++++ b/drivers/hwmon/pmbus/Makefile +@@ -42,6 +42,7 @@ obj-$(CONFIG_SENSORS_MP2975) += mp2975.o + obj-$(CONFIG_SENSORS_MP2993) += mp2993.o + obj-$(CONFIG_SENSORS_MP5023) += mp5023.o + obj-$(CONFIG_SENSORS_MP5920) += mp5920.o ++obj-$(CONFIG_SENSORS_MP5926) += mp5926.o + obj-$(CONFIG_SENSORS_MP5990) += mp5990.o + obj-$(CONFIG_SENSORS_MP9941) += mp9941.o + obj-$(CONFIG_SENSORS_MPQ7932) += mpq7932.o +diff --git a/drivers/hwmon/pmbus/mp5926.c b/drivers/hwmon/pmbus/mp5926.c +new file mode 100644 +index 000000000000..626d945be5b6 +--- /dev/null ++++ b/drivers/hwmon/pmbus/mp5926.c +@@ -0,0 +1,192 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++// ++// mp5926.c - pmbus driver for mps mp5926 ++// ++// Copyright 2025 Monolithic Power Systems, Inc ++// ++// Author: Yuxi Wang ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "pmbus.h" ++ ++/*Common Register*/ ++#define PAGE 0x01 ++#define EFUSE_CFG 0xCF ++#define I_SCALE_SEL 0xC6 ++#define MP5926_FUNC (PMBUS_HAVE_VIN | PMBUS_HAVE_VOUT | PMBUS_HAVE_IIN | PMBUS_HAVE_PIN | \ ++ PMBUS_HAVE_TEMP | PMBUS_HAVE_STATUS_INPUT | PMBUS_HAVE_STATUS_TEMP | \ ++ PMBUS_HAVE_STATUS_VOUT) ++ ++static int mp5926_read_word_data(struct i2c_client *client, int page, int phase, int reg) ++{ ++ int ret; ++ s16 exponent; ++ s32 mantissa; ++ s64 val; ++ ++ switch (reg) { ++ case PMBUS_READ_VIN...PMBUS_READ_VCAP: ++ case PMBUS_READ_IOUT...PMBUS_READ_TEMPERATURE_1: ++ case PMBUS_READ_PIN: ++ case PMBUS_STATUS_WORD: ++ ret = -ENODATA; ++ break; ++ case PMBUS_READ_VOUT: ++ /* The Vout format used by the chip is linear11 and not linear16. ++ * So we transform the value into the direct format defined by PMBus. ++ */ ++ ret = i2c_smbus_read_word_data(client, EFUSE_CFG); ++ if (ret < 0) ++ return ret; ++ if (ret & BIT(12)) { ++ ret = i2c_smbus_read_word_data(client, PMBUS_READ_VOUT); ++ if (ret < 0) ++ return ret; ++ exponent = ((s16)ret) >> 11; ++ mantissa = ((s16)((ret & 0x7ff) << 5)) >> 5; ++ val = mantissa * 1000; ++ if (exponent >= 0) ++ val <<= exponent; ++ else ++ val >>= -exponent; ++ return div_s64(val * 10 + 313L, 625L); ++ } ++ ret = -ENODATA; ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ return ret; ++} ++ ++static int mp5926_read_byte_data(struct i2c_client *client, int page, int reg) ++{ ++ int ret; ++ ++ switch (reg) { ++ case PMBUS_STATUS_BYTE: ++ case PMBUS_STATUS_VOUT: ++ case PMBUS_STATUS_INPUT: ++ case PMBUS_STATUS_TEMPERATURE: ++ case PMBUS_STATUS_CML: ++ case PMBUS_STATUS_MFR_SPECIFIC: ++ ret = -ENODATA; ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ return ret; ++} ++ ++static struct pmbus_driver_info mp5926_info_linear = { ++ .pages = PAGE, ++ .format[PSC_VOLTAGE_IN] = linear, ++ .format[PSC_CURRENT_IN] = linear, ++ .format[PSC_VOLTAGE_OUT] = direct, ++ .format[PSC_TEMPERATURE] = linear, ++ .format[PSC_POWER] = linear, ++ ++ .m[PSC_VOLTAGE_OUT] = 16, ++ .b[PSC_VOLTAGE_OUT] = 0, ++ .R[PSC_VOLTAGE_OUT] = 0, ++ ++ .read_word_data = mp5926_read_word_data, ++ .read_byte_data = mp5926_read_byte_data, ++ .func[0] = MP5926_FUNC, ++}; ++ ++static struct pmbus_driver_info mp5926_info_direct = { ++ .pages = PAGE, ++ .format[PSC_VOLTAGE_IN] = direct, ++ .format[PSC_CURRENT_IN] = direct, ++ .format[PSC_VOLTAGE_OUT] = direct, ++ .format[PSC_TEMPERATURE] = direct, ++ .format[PSC_POWER] = direct, ++ ++ .m[PSC_VOLTAGE_IN] = 16, ++ .b[PSC_VOLTAGE_IN] = 0, ++ .R[PSC_VOLTAGE_IN] = 0, ++ ++ .m[PSC_CURRENT_IN] = 16, ++ .b[PSC_CURRENT_IN] = 0, ++ .R[PSC_CURRENT_IN] = 0, ++ ++ .m[PSC_VOLTAGE_OUT] = 16, ++ .b[PSC_VOLTAGE_OUT] = 0, ++ .R[PSC_VOLTAGE_OUT] = 0, ++ ++ .m[PSC_TEMPERATURE] = 4, ++ .b[PSC_TEMPERATURE] = 0, ++ .R[PSC_TEMPERATURE] = 3, ++ ++ .m[PSC_POWER] = 25, ++ .b[PSC_POWER] = 0, ++ .R[PSC_POWER] = -2, ++ ++ .read_word_data = mp5926_read_word_data, ++ .read_byte_data = mp5926_read_byte_data, ++ .func[0] = MP5926_FUNC, ++}; ++ ++static int mp5926_probe(struct i2c_client *client) ++{ ++ int ret; ++ ++ if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_READ_BYTE_DATA | ++ I2C_FUNC_SMBUS_BLOCK_DATA)) ++ return -ENODEV; ++ ++ ret = i2c_smbus_read_word_data(client, EFUSE_CFG); ++ ++ if (ret < 0) ++ return ret; ++ ++ if (ret & BIT(12)) { ++ ret = pmbus_do_probe(client, &mp5926_info_linear); ++ } else { ++ ret = i2c_smbus_read_word_data(client, I_SCALE_SEL); ++ if (ret < 0) ++ return ret; ++ if (ret & BIT(6)) ++ mp5926_info_direct.m[PSC_CURRENT_IN] = 4; ++ ret = pmbus_do_probe(client, &mp5926_info_direct); ++ } ++ if (!ret) ++ dev_info(&client->dev, "%s chip found\n", client->name); ++ return ret; ++} ++ ++static const struct i2c_device_id mp5926_id[] = { ++ { "mp5926", 0 }, ++ {} ++}; ++MODULE_DEVICE_TABLE(i2c, mp5926_id); ++ ++static const struct of_device_id mp5926_of_match[] = { ++ { .compatible = "mps,mp5926" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, mp5926_of_match); ++ ++static struct i2c_driver mp5926_driver = { ++ .probe = mp5926_probe, ++ .driver = { ++ .name = "mp5926", ++ .of_match_table = mp5926_of_match, ++ }, ++ .id_table = mp5926_id, ++}; ++ ++module_i2c_driver(mp5926_driver); ++MODULE_AUTHOR("Yuxi Wang "); ++MODULE_DESCRIPTION("MPS MP5926 HWMON driver"); ++MODULE_LICENSE("GPL"); ++MODULE_IMPORT_NS(PMBUS); +-- +2.34.1 + diff --git a/patches-sonic/8014-platform-mellanox-mlxreg-dpu-Debug-trace-for-dpu-pro.patch b/patches-sonic/8014-platform-mellanox-mlxreg-dpu-Debug-trace-for-dpu-pro.patch deleted file mode 100644 index 03b7156c0..000000000 --- a/patches-sonic/8014-platform-mellanox-mlxreg-dpu-Debug-trace-for-dpu-pro.patch +++ /dev/null @@ -1,32 +0,0 @@ -From e7838edd2acc793f3b43ab04b3693a340273c330 Mon Sep 17 00:00:00 2001 -From: Ciju Rajan K -Date: Fri, 19 Sep 2025 09:51:17 +0300 -Subject: platform: mellanox: mlxreg-dpu: Debug trace for dpu probing - -Signed-off-by: Ciju Rajan K ---- - drivers/platform/mellanox/mlxreg-dpu.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - -diff --git a/drivers/platform/mellanox/mlxreg-dpu.c b/drivers/platform/mellanox/mlxreg-dpu.c -index 314385cc1495..3b07c66c87dc 100644 ---- a/drivers/platform/mellanox/mlxreg-dpu.c -+++ b/drivers/platform/mellanox/mlxreg-dpu.c -@@ -530,9 +530,13 @@ static int mlxreg_dpu_probe(struct platform_device *pdev) - if (!data || !data->hpdev.brdinfo) - return -EINVAL; - -+ dev_info(&pdev->dev, "Probing for adapter %d\n", data->hpdev.nr); - data->hpdev.adapter = i2c_get_adapter(data->hpdev.nr); -- if (!data->hpdev.adapter) -+ if (!data->hpdev.adapter) { -+ dev_info(&pdev->dev, "Will try a deferred probing for %d\n", -+ data->hpdev.nr); - return -EPROBE_DEFER; -+ } - - mlxreg_dpu = devm_kzalloc(&pdev->dev, sizeof(*mlxreg_dpu), GFP_KERNEL); - if (!mlxreg_dpu) { --- -2.47.2 - diff --git a/patches-sonic/series b/patches-sonic/series index 8d862b559..a23d331be 100644 --- a/patches-sonic/series +++ b/patches-sonic/series @@ -111,6 +111,8 @@ driver-net-tg3-change-dma-mask-for-57766.patch 0053-platform-mellanox-mlx-platform-Add-support-for-new-X.patch 0054-i2c-asf-Introduce-MCTP-support-over-ASF-controller.patch 0055-platform-mellanox-Downstream-Add-support-DGX-flavor-.patch +0056-hwmon-pmbus-mp2845-Add-support-for-MP2845-device.patch +0057-hwmon-pmbus-mp5926-Add-support-for-MP5926-device.patch 8000-mlxsw-Use-weak-reverse-dependencies-for-firmware-fla.patch 8001-platform-mlx-platform-Downstream-Add-SPI-path-for-ra.patch 8002-mlxsw-i2c-SONIC-ISSU-Prevent-transaction-execution-f.patch @@ -124,7 +126,6 @@ driver-net-tg3-change-dma-mask-for-57766.patch 8010-mlxsw-minimal-Downstream-Disable-ethtool-interface.patch 8011-hwmon-pmbus-Downstream-Workaround-for-psu-attributes.patch 8013-hwmon-pmbus-mp2975-Clear-interrupts-at-probe.patch -8014-platform-mellanox-mlxreg-dpu-Debug-trace-for-dpu-pro.patch 9000-platform-mellanox-Downstream-Add-support-for-new-Nvi.patch ###-> mellanox_hw_mgmt-end