From b58843711dcc6afbb06b8fb366c1fac2cbce4262 Mon Sep 17 00:00:00 2001 From: "Travis F. Collins" Date: Sun, 9 Aug 2026 12:18:29 +0000 Subject: [PATCH] fix(hw): select AD9081 122.88 MHz VCXO DT --- examples/lg_ad9081_zcu102_exporter.yaml | 10 ++++++---- examples/lg_ad9081_zcu102_mini2_exporter.yaml | 12 +++++++----- tests/test_ad9081_exporter_profile.py | 7 ++++--- 3 files changed, 17 insertions(+), 12 deletions(-) diff --git a/examples/lg_ad9081_zcu102_exporter.yaml b/examples/lg_ad9081_zcu102_exporter.yaml index 0dc180f..689a52a 100644 --- a/examples/lg_ad9081_zcu102_exporter.yaml +++ b/examples/lg_ad9081_zcu102_exporter.yaml @@ -44,7 +44,9 @@ tlab: release_version: "2023_R2_P1" cache_path: "/tmp/kuiper_cache" kernel_path: "release:zynqmp-common/Image" - # m8_l4 leaves PLL2 unlocked on the lab's AD9081-FMCB-EBZ; m4_l8 - # is hardware-verified to register both RX and TX converter devices. - BOOTBIN_path: "release:zynqmp-zcu102-rev10-ad9081/m4_l8/BOOT.BIN" - device_tree_path: "release:zynqmp-zcu102-rev10-ad9081/m4_l8/system.dtb" + # The lab's AD9081-FMCB-EBZ has a 122.88 MHz VCXO. Pair the m8_l4 + # bitstream with Kuiper's dedicated DT override, whose HMC7044 node sets + # adi,vcxo-frequency=122880000. The ordinary m8_l4 and m4_l8 DTBs set + # 100 MHz and must not be used with this board. + BOOTBIN_path: "release:zynqmp-zcu102-rev10-ad9081/m8_l4/BOOT.BIN" + device_tree_path: "release:zynqmp-zcu102-rev10-ad9081/m8_l4/m8_l4_vcxo122p88/system.dtb" diff --git a/examples/lg_ad9081_zcu102_mini2_exporter.yaml b/examples/lg_ad9081_zcu102_mini2_exporter.yaml index aa34747..23d10c6 100644 --- a/examples/lg_ad9081_zcu102_mini2_exporter.yaml +++ b/examples/lg_ad9081_zcu102_mini2_exporter.yaml @@ -7,7 +7,7 @@ ## carrier=zcu102 \ ## daughter-board=ad9081 \ ## boot-strategy=BootFPGASoC \ -## hdl-config=m4_l8 +## hdl-config=m8_l4_vcxo122p88 ## ## See docs/source/user-guide/hw-ci-v2.md (place-tag-schema section) ## for the full schema. Without those tags, the v2 discovery step @@ -59,7 +59,9 @@ tlab: release_version: "2023_R2_P1" cache_path: "/tmp/kuiper_cache" kernel_path: "release:zynqmp-common/Image" - # m8_l4 leaves PLL2 unlocked on the lab's AD9081-FMCB-EBZ; m4_l8 - # is hardware-verified to register both RX and TX converter devices. - BOOTBIN_path: "release:zynqmp-zcu102-rev10-ad9081/m4_l8/BOOT.BIN" - device_tree_path: "release:zynqmp-zcu102-rev10-ad9081/m4_l8/system.dtb" + # The lab's AD9081-FMCB-EBZ has a 122.88 MHz VCXO. Pair the m8_l4 + # bitstream with Kuiper's dedicated DT override, whose HMC7044 node sets + # adi,vcxo-frequency=122880000. The ordinary m8_l4 and m4_l8 DTBs set + # 100 MHz and must not be used with this board. + BOOTBIN_path: "release:zynqmp-zcu102-rev10-ad9081/m8_l4/BOOT.BIN" + device_tree_path: "release:zynqmp-zcu102-rev10-ad9081/m8_l4/m8_l4_vcxo122p88/system.dtb" diff --git a/tests/test_ad9081_exporter_profile.py b/tests/test_ad9081_exporter_profile.py index d25d467..ffc2349 100644 --- a/tests/test_ad9081_exporter_profile.py +++ b/tests/test_ad9081_exporter_profile.py @@ -10,10 +10,11 @@ @pytest.mark.parametrize("config_path", EXAMPLES) -def test_zcu102_ad9081_uses_hardware_verified_m4_l8_profile(config_path): +def test_zcu102_ad9081_uses_122p88_mhz_vcxo_profile(config_path): document = yaml.safe_load(config_path.read_text()) resources = next(iter(document.values())) release = resources["KuiperRelease"] - assert release["BOOTBIN_path"].endswith("/m4_l8/BOOT.BIN") - assert release["device_tree_path"].endswith("/m4_l8/system.dtb") + assert release["BOOTBIN_path"].endswith("/m8_l4/BOOT.BIN") + assert release["device_tree_path"].endswith("/m8_l4/m8_l4_vcxo122p88/system.dtb") + assert "/m4_l8/" not in release["device_tree_path"]