Hello all,
I’m working on a project where I want to use an ADRV9002 connected to a Zynq-7000 SoC (as ZedBoard) as the RF front-end for srsRAN_4G.
Problem
I’ve seen from past srsRAN issues (e.g. #351 that LTE/eNB operation requires FPGA-based timestamping (64-bit sample counter + timed TX scheduling). Without it, the UE cannot attach since subframe alignment breaks.
The zynq_timestamping repo looks like exactly what I need, but I’m unsure how to adapt it to the ADRV9002 platform.
My Questions
Do I need to integrate zynq_timestamping into the ADRV9002 HDL design to enable timestamped I/Q streaming over DMA? is there already support for the ADRV9002 in this repo?
Integration steps: Which HDL modules should I connect between the ADRV9002 SSI (LVDS/CMOS) interface and the DMA? Do I need to modify the ADI reference HDL design (AXI_ADRV9001) to insert the timestamp logic?
Driver layer: Is libiio support already available in zynq_timestamping, or do I need to modify the ADRV9002 IIO driver to expose send_timed / recv_with_time? Any example on how to connect this with SoapySDR so srsRAN can call rf_soapy_send_timed?
My setup
RF frontend: ADRV9002 (Dual channel RFIC, sample rates 30.72 / 61.44 MS/s).
FPGA: Zynq-7020 (ZedBoard).
Host: Linux PC running srsRAN_4G (ENB + EPC), connected via Ethernet to Zed.
🙏 Any guidance, integration steps, or confirmation that zynq_timestamping is the right starting point for ADRV9002 would be very helpful.
Thanks in advance!
Hello all,
I’m working on a project where I want to use an ADRV9002 connected to a Zynq-7000 SoC (as ZedBoard) as the RF front-end for srsRAN_4G.
Problem
I’ve seen from past srsRAN issues (e.g. #351 that LTE/eNB operation requires FPGA-based timestamping (64-bit sample counter + timed TX scheduling). Without it, the UE cannot attach since subframe alignment breaks.
The zynq_timestamping repo looks like exactly what I need, but I’m unsure how to adapt it to the ADRV9002 platform.
My Questions
Do I need to integrate zynq_timestamping into the ADRV9002 HDL design to enable timestamped I/Q streaming over DMA? is there already support for the ADRV9002 in this repo?
Integration steps: Which HDL modules should I connect between the ADRV9002 SSI (LVDS/CMOS) interface and the DMA? Do I need to modify the ADI reference HDL design (AXI_ADRV9001) to insert the timestamp logic?
Driver layer: Is libiio support already available in zynq_timestamping, or do I need to modify the ADRV9002 IIO driver to expose send_timed / recv_with_time? Any example on how to connect this with SoapySDR so srsRAN can call rf_soapy_send_timed?
My setup
RF frontend: ADRV9002 (Dual channel RFIC, sample rates 30.72 / 61.44 MS/s).
FPGA: Zynq-7020 (ZedBoard).
Host: Linux PC running srsRAN_4G (ENB + EPC), connected via Ethernet to Zed.
🙏 Any guidance, integration steps, or confirmation that zynq_timestamping is the right starting point for ADRV9002 would be very helpful.
Thanks in advance!