Add mechanism to validate that the timestamping mechanism is loaded in the FPGA

[ofontbach]

Add a register in the FPGA so that the software can validate that the correct bitstream is loaded when initializing the RF.

[uptools]

@ofontbach
do you have a specific shell command to check this register you mention ? is it already added?
We already installed the bitstream in the antsdr but still get "Error reading rx ringbuffer. Invalid header" when running srsenb.

[ofontbach]

hi @uptools,
this mechanism has not yet been added. We'll let you know when it becomes available.
As with respect to the antsdr, I can only add to check the specific versions you're using and to follow the guidelines we provide. There are a few related discussions posts which might be helpful. We know of a number of success stories with the antsdr, so I'm confident you'll get it working.

[uptools]

Hi @ofontbach,
Do you know if the antsdr success stories were run with antsdr e200 or e310?
As the differ significantly in their zynq axi and mio configurations, so their interfaces with the fpga are not compatible between them. I guess this may prevent the same zynq_timestamping to run on both.

[ofontbach]

Hi @uptools,

I know of success stories with both, but I was referring to the e310 and using our timestamping solution of course. With the e200, sincerely we have yet to test the timestamping solution, but probably most people will go the UHD way.
As to running the timestamping solution in both of them, well this repo provides the source code, so it's mostly a matter to generate the HDL projects with the right firmware (e.g., targeting the right device) and see how to adapt the driver end (probably based on the standalone firmware provided by MicroPhase.