sim_errors

#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2009.vpi";
S_0x597a8caeef60 .scope package, "$unit" "$unit" 2 1;
 .timescale 0 0;
S_0x597a8cb01e50 .scope module, "uart_tb_errors" "uart_tb_errors" 3 8;
 .timescale -9 -12;
P_0x597a8cb2de30 .param/l "BAUD_RATE" 1 3 11, +C4<00000000000000011100001000000000>;
P_0x597a8cb2de70 .param/l "CLK_FREQ" 1 3 10, +C4<00000010111110101111000010000000>;
P_0x597a8cb2deb0 .param/l "DIVISOR" 1 3 12, +C4<00000000000000000000000110110010>;
v0x597a8cb52fb0_0 .var "clk", 0 0;
v0x597a8cb53070_0 .var/i "fail_count", 31 0;
v0x597a8cb53150_0 .var "inject_enable", 0 0;
v0x597a8cb531f0_0 .var "inject_value", 0 0;
v0x597a8cb532b0_0 .var/i "pass_count", 31 0;
v0x597a8cb53390_0 .var "rst", 0 0;
v0x597a8cb53430_0 .net "rx_data", 7 0, v0x597a8cb518a0_0;  1 drivers
v0x597a8cb534f0_0 .net "rx_done", 0 0, v0x597a8cb51940_0;  1 drivers
v0x597a8cb53590_0 .net "rx_error", 0 0, v0x597a8cb51a00_0;  1 drivers
v0x597a8cb536f0_0 .var "rx_error_latched", 0 0;
v0x597a8cb53790_0 .net "rx_line", 0 0, L_0x597a8cb53d80;  1 drivers
v0x597a8cb53860_0 .var/i "test_num", 31 0;
v0x597a8cb53900_0 .net "tick", 0 0, v0x597a8caec350_0;  1 drivers
v0x597a8cb539a0_0 .net "tx_busy", 0 0, v0x597a8cb52af0_0;  1 drivers
v0x597a8cb53a40_0 .var "tx_data", 7 0;
v0x597a8cb53b10_0 .net "tx_done", 0 0, v0x597a8cb52c70_0;  1 drivers
v0x597a8cb53be0_0 .net "tx_out", 0 0, v0x597a8cb52d30_0;  1 drivers
v0x597a8cb53cb0_0 .var "tx_start", 0 0;
L_0x597a8cb53d80 .functor MUXZ 1, v0x597a8cb52d30_0, v0x597a8cb531f0_0, v0x597a8cb53150_0, C4<>;
S_0x597a8cb020f0 .scope task, "test_data_corruption" "test_data_corruption" 3 142, 3 142 0, S_0x597a8cb01e50;
 .timescale -9 -12;
E_0x597a8cabe570 .event posedge, v0x597a8caf1a50_0;
E_0x597a8caf77b0 .event edge, v0x597a8cb51940_0, v0x597a8cb51a00_0;
E_0x597a8cabe800 .event posedge, v0x597a8caec350_0;
TD_uart_tb_errors.test_data_corruption ;
    %load/vec4 v0x597a8cb53860_0;
    %addi 1, 0, 32;
    %store/vec4 v0x597a8cb53860_0, 0, 32;
    %vpi_call/w 3 145 "$display", "\012--- Test %0d: Data bit corruption (expected limitation) ---", v0x597a8cb53860_0 {0 0 0};
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x597a8cb53150_0, 0, 1;
    %wait E_0x597a8cabe570;
    %delay 1000, 0;
    %pushi/vec4 15, 0, 8;
    %store/vec4 v0x597a8cb53a40_0, 0, 8;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0x597a8cb53cb0_0, 0, 1;
    %wait E_0x597a8cabe570;
    %delay 1000, 0;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x597a8cb53cb0_0, 0, 1;
    %pushi/vec4 4, 0, 32;
T_0.0 %dup/vec4;
    %pushi/vec4 0, 0, 32;
    %cmp/s;
    %jmp/1xz T_0.1, 5;
    %jmp/1 T_0.1, 4;
    %pushi/vec4 1, 0, 32;
    %sub;
    %wait E_0x597a8cabe800;
    %jmp T_0.0;
T_0.1 ;
    %pop/vec4 1;
    %delay 1000, 0;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0x597a8cb53150_0, 0, 1;
    %load/vec4 v0x597a8cb53be0_0;
    %inv;
    %store/vec4 v0x597a8cb531f0_0, 0, 1;
    %pushi/vec4 434, 0, 32;
T_0.2 %dup/vec4;
    %pushi/vec4 0, 0, 32;
    %cmp/s;
    %jmp/1xz T_0.3, 5;
    %jmp/1 T_0.3, 4;
    %pushi/vec4 1, 0, 32;
    %sub;
    %wait E_0x597a8cabe570;
    %jmp T_0.2;
T_0.3 ;
    %pop/vec4 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x597a8cb53150_0, 0, 1;
T_0.4 ;
    %load/vec4 v0x597a8cb534f0_0;
    %load/vec4 v0x597a8cb53590_0;
    %or;
    %cmpi/ne 1, 0, 1;
    %jmp/0xz T_0.5, 6;
    %wait E_0x597a8caf77b0;
    %jmp T_0.4;
T_0.5 ;
    %wait E_0x597a8cabe570;
    %delay 1000, 0;
    %vpi_call/w 3 168 "$display", "Sent    : 0x%02h (%08b)", 8'b00001111, 8'b00001111 {0 0 0};
    %vpi_call/w 3 169 "$display", "Received: 0x%02h (%08b)", v0x597a8cb53430_0, v0x597a8cb53430_0 {0 0 0};
    %vpi_call/w 3 170 "$display", "rx_error: %b", v0x597a8cb53590_0 {0 0 0};
    %load/vec4 v0x597a8cb53430_0;
    %pushi/vec4 15, 0, 8;
    %cmp/ne;
    %flag_get/vec4 6;
    %load/vec4 v0x597a8cb53590_0;
    %nor/r;
    %and;
    %flag_set/vec4 8;
    %jmp/0xz  T_0.6, 8;
    %vpi_call/w 3 173 "$display", "Result: EXPECTED - data corrupted silently, no error flag" {0 0 0};
    %vpi_call/w 3 174 "$display", "        This proves plain UART cannot detect bit errors" {0 0 0};
    %load/vec4 v0x597a8cb532b0_0;
    %addi 1, 0, 32;
    %store/vec4 v0x597a8cb532b0_0, 0, 32;
    %jmp T_0.7;
T_0.6 ;
    %vpi_call/w 3 177 "$display", "Result: Data survived or error flagged - also acceptable" {0 0 0};
    %load/vec4 v0x597a8cb532b0_0;
    %addi 1, 0, 32;
    %store/vec4 v0x597a8cb532b0_0, 0, 32;
T_0.7 ;
    %pushi/vec4 20, 0, 32;
T_0.8 %dup/vec4;
    %pushi/vec4 0, 0, 32;
    %cmp/s;
    %jmp/1xz T_0.9, 5;
    %jmp/1 T_0.9, 4;
    %pushi/vec4 1, 0, 32;
    %sub;
    %wait E_0x597a8cabe570;
    %jmp T_0.8;
T_0.9 ;
    %pop/vec4 1;
    %end;
S_0x597a8cb0f1e0 .scope task, "test_glitch_rejection" "test_glitch_rejection" 3 109, 3 109 0, S_0x597a8cb01e50;
 .timescale -9 -12;
TD_uart_tb_errors.test_glitch_rejection ;
    %load/vec4 v0x597a8cb53860_0;
    %addi 1, 0, 32;
    %store/vec4 v0x597a8cb53860_0, 0, 32;
    %vpi_call/w 3 112 "$display", "\012--- Test %0d: Glitch rejection ---", v0x597a8cb53860_0 {0 0 0};
    %wait E_0x597a8cabe570;
    %delay 1000, 0;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0x597a8cb53150_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x597a8cb531f0_0, 0, 1;
    %pushi/vec4 50, 0, 32;
T_1.10 %dup/vec4;
    %pushi/vec4 0, 0, 32;
    %cmp/s;
    %jmp/1xz T_1.11, 5;
    %jmp/1 T_1.11, 4;
    %pushi/vec4 1, 0, 32;
    %sub;
    %wait E_0x597a8cabe570;
    %jmp T_1.10;
T_1.11 ;
    %pop/vec4 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x597a8cb53150_0, 0, 1;
    %pushi/vec4 434, 0, 32;
T_1.12 %dup/vec4;
    %pushi/vec4 0, 0, 32;
    %cmp/s;
    %jmp/1xz T_1.13, 5;
    %jmp/1 T_1.13, 4;
    %pushi/vec4 1, 0, 32;
    %sub;
    %wait E_0x597a8cabe570;
    %jmp T_1.12;
T_1.13 ;
    %pop/vec4 1;
    %delay 1000, 0;
    %load/vec4 v0x597a8cb52040_0;
    %cmpi/e 0, 0, 2;
    %jmp/0xz  T_1.14, 4;
    %vpi_call/w 3 127 "$display", "Result: PASS - glitch rejected, RX in IDLE" {0 0 0};
    %load/vec4 v0x597a8cb532b0_0;
    %addi 1, 0, 32;
    %store/vec4 v0x597a8cb532b0_0, 0, 32;
    %jmp T_1.15;
T_1.14 ;
    %vpi_call/w 3 130 "$display", "Result: FAIL - RX incorrectly left IDLE (state=%0d)", v0x597a8cb52040_0 {0 0 0};
    %load/vec4 v0x597a8cb53070_0;
    %addi 1, 0, 32;
    %store/vec4 v0x597a8cb53070_0, 0, 32;
T_1.15 ;
    %pushi/vec4 20, 0, 32;
T_1.16 %dup/vec4;
    %pushi/vec4 0, 0, 32;
    %cmp/s;
    %jmp/1xz T_1.17, 5;
    %jmp/1 T_1.17, 4;
    %pushi/vec4 1, 0, 32;
    %sub;
    %wait E_0x597a8cabe570;
    %jmp T_1.16;
T_1.17 ;
    %pop/vec4 1;
    %end;
S_0x597a8cb0f3c0 .scope task, "test_stop_bit_error" "test_stop_bit_error" 3 70, 3 70 0, S_0x597a8cb01e50;
 .timescale -9 -12;
TD_uart_tb_errors.test_stop_bit_error ;
    %load/vec4 v0x597a8cb53860_0;
    %addi 1, 0, 32;
    %store/vec4 v0x597a8cb53860_0, 0, 32;
    %vpi_call/w 3 73 "$display", "\012--- Test %0d: Corrupted stop bit ---", v0x597a8cb53860_0 {0 0 0};
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x597a8cb53150_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x597a8cb536f0_0, 0, 1;
    %wait E_0x597a8cabe570;
    %delay 1000, 0;
    %pushi/vec4 165, 0, 8;
    %store/vec4 v0x597a8cb53a40_0, 0, 8;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0x597a8cb53cb0_0, 0, 1;
    %wait E_0x597a8cabe570;
    %delay 1000, 0;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x597a8cb53cb0_0, 0, 1;
    %pushi/vec4 10, 0, 32;
T_2.18 %dup/vec4;
    %pushi/vec4 0, 0, 32;
    %cmp/s;
    %jmp/1xz T_2.19, 5;
    %jmp/1 T_2.19, 4;
    %pushi/vec4 1, 0, 32;
    %sub;
    %wait E_0x597a8cabe800;
    %jmp T_2.18;
T_2.19 ;
    %pop/vec4 1;
    %delay 1000, 0;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0x597a8cb53150_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x597a8cb531f0_0, 0, 1;
    %pushi/vec4 434, 0, 32;
T_2.20 %dup/vec4;
    %pushi/vec4 0, 0, 32;
    %cmp/s;
    %jmp/1xz T_2.21, 5;
    %jmp/1 T_2.21, 4;
    %pushi/vec4 1, 0, 32;
    %sub;
    %wait E_0x597a8cabe570;
    %jmp T_2.20;
T_2.21 ;
    %pop/vec4 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x597a8cb53150_0, 0, 1;
    %wait E_0x597a8cabe570;
    %delay 100000, 0;
    %load/vec4 v0x597a8cb536f0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_2.22, 8;
    %vpi_call/w 3 95 "$display", "Result: PASS - rx_error correctly asserted" {0 0 0};
    %load/vec4 v0x597a8cb532b0_0;
    %addi 1, 0, 32;
    %store/vec4 v0x597a8cb532b0_0, 0, 32;
    %jmp T_2.23;
T_2.22 ;
    %vpi_call/w 3 98 "$display", "Result: FAIL - rx_error NOT asserted (bug!)" {0 0 0};
    %load/vec4 v0x597a8cb53070_0;
    %addi 1, 0, 32;
    %store/vec4 v0x597a8cb53070_0, 0, 32;
T_2.23 ;
    %pushi/vec4 20, 0, 32;
T_2.24 %dup/vec4;
    %pushi/vec4 0, 0, 32;
    %cmp/s;
    %jmp/1xz T_2.25, 5;
    %jmp/1 T_2.25, 4;
    %pushi/vec4 1, 0, 32;
    %sub;
    %wait E_0x597a8cabe570;
    %jmp T_2.24;
T_2.25 ;
    %pop/vec4 1;
    %end;
S_0x597a8caf9510 .scope module, "u_baud" "baud_gen" 3 41, 4 7 0, S_0x597a8cb01e50;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst";
    .port_info 2 /OUTPUT 1 "tick";
P_0x597a8caf5a90 .param/l "BAUD_RATE" 0 4 9, +C4<00000000000000011100001000000000>;
P_0x597a8caf5ad0 .param/l "CLK_FREQ" 0 4 8, +C4<00000010111110101111000010000000>;
P_0x597a8caf5b10 .param/l "DIVISOR" 1 4 15, +C4<00000000000000000000000110110010>;
v0x597a8caf1a50_0 .net "clk", 0 0, v0x597a8cb52fb0_0;  1 drivers
v0x597a8caf2560_0 .var "count", 8 0;
v0x597a8caf3680_0 .net "rst", 0 0, v0x597a8cb53390_0;  1 drivers
v0x597a8caec350_0 .var "tick", 0 0;
S_0x597a8cb51090 .scope module, "u_rx" "uart_rx" 3 49, 5 9 0, S_0x597a8cb01e50;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst";
    .port_info 2 /INPUT 1 "rx_in";
    .port_info 3 /OUTPUT 8 "rx_data";
    .port_info 4 /OUTPUT 1 "rx_done";
    .port_info 5 /OUTPUT 1 "rx_error";
P_0x597a8cb32970 .param/l "BAUD_RATE" 0 5 20, +C4<00000000000000011100001000000000>;
P_0x597a8cb329b0 .param/l "CLK_FREQ" 0 5 19, +C4<00000010111110101111000010000000>;
P_0x597a8cb329f0 .param/l "DATA" 1 5 28, C4<10>;
P_0x597a8cb32a30 .param/l "DIVISOR" 1 5 22, +C4<00000000000000000000000110110010>;
P_0x597a8cb32a70 .param/l "HALF_DIVISOR" 1 5 23, +C4<00000000000000000000000011011001>;
P_0x597a8cb32ab0 .param/l "IDLE" 1 5 26, C4<00>;
P_0x597a8cb32af0 .param/l "START" 1 5 27, C4<01>;
P_0x597a8cb32b30 .param/l "STOP" 1 5 29, C4<11>;
L_0x597a8caf2440 .functor NOT 1, v0x597a8cb51d00_0, C4<0>, C4<0>, C4<0>;
L_0x597a8caf2ca0 .functor AND 1, v0x597a8cb51b80_0, L_0x597a8caf2440, C4<1>, C4<1>;
v0x597a8caed9f0_0 .net *"_ivl_2", 0 0, L_0x597a8caf2440;  1 drivers
v0x597a8caee310_0 .var "bit_cnt", 2 0;
v0x597a8cb51640_0 .net "clk", 0 0, v0x597a8cb52fb0_0;  alias, 1 drivers
v0x597a8cb516e0_0 .net "rst", 0 0, v0x597a8cb53390_0;  alias, 1 drivers
v0x597a8cb517b0_0 .net "rx", 0 0, v0x597a8cb51d00_0;  1 drivers
v0x597a8cb518a0_0 .var "rx_data", 7 0;
v0x597a8cb51940_0 .var "rx_done", 0 0;
v0x597a8cb51a00_0 .var "rx_error", 0 0;
v0x597a8cb51ac0_0 .net "rx_in", 0 0, L_0x597a8cb53d80;  alias, 1 drivers
v0x597a8cb51b80_0 .var "rx_prev", 0 0;
v0x597a8cb51c40_0 .var "rx_sync1", 0 0;
v0x597a8cb51d00_0 .var "rx_sync2", 0 0;
v0x597a8cb51dc0_0 .var "sample_cnt", 8 0;
v0x597a8cb51ea0_0 .var "shift_reg", 7 0;
v0x597a8cb51f80_0 .net "start_detected", 0 0, L_0x597a8caf2ca0;  1 drivers
v0x597a8cb52040_0 .var "state", 1 0;
S_0x597a8cb521e0 .scope module, "u_tx" "uart_tx" 3 43, 6 7 0, S_0x597a8cb01e50;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst";
    .port_info 2 /INPUT 1 "tick";
    .port_info 3 /INPUT 1 "tx_start";
    .port_info 4 /INPUT 8 "tx_data";
    .port_info 5 /OUTPUT 1 "tx_out";
    .port_info 6 /OUTPUT 1 "tx_busy";
    .port_info 7 /OUTPUT 1 "tx_done";
P_0x597a8cb17ca0 .param/l "DATA" 1 6 19, C4<10>;
P_0x597a8cb17ce0 .param/l "IDLE" 1 6 17, C4<00>;
P_0x597a8cb17d20 .param/l "START" 1 6 18, C4<01>;
P_0x597a8cb17d60 .param/l "STOP" 1 6 20, C4<11>;
v0x597a8cb525a0_0 .var "bit_cnt", 2 0;
v0x597a8cb52680_0 .net "clk", 0 0, v0x597a8cb52fb0_0;  alias, 1 drivers
v0x597a8cb52790_0 .net "rst", 0 0, v0x597a8cb53390_0;  alias, 1 drivers
v0x597a8cb52880_0 .var "shift_reg", 7 0;
v0x597a8cb52920_0 .var "state", 1 0;
v0x597a8cb52a50_0 .net "tick", 0 0, v0x597a8caec350_0;  alias, 1 drivers
v0x597a8cb52af0_0 .var "tx_busy", 0 0;
v0x597a8cb52b90_0 .net "tx_data", 7 0, v0x597a8cb53a40_0;  1 drivers
v0x597a8cb52c70_0 .var "tx_done", 0 0;
v0x597a8cb52d30_0 .var "tx_out", 0 0;
v0x597a8cb52df0_0 .net "tx_start", 0 0, v0x597a8cb53cb0_0;  1 drivers
    .scope S_0x597a8caf9510;
T_3 ;
    %wait E_0x597a8cabe570;
    %load/vec4 v0x597a8caf3680_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_3.0, 8;
    %pushi/vec4 0, 0, 9;
    %assign/vec4 v0x597a8caf2560_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x597a8caec350_0, 0;
    %jmp T_3.1;
T_3.0 ;
    %load/vec4 v0x597a8caf2560_0;
    %pad/u 32;
    %cmpi/e 433, 0, 32;
    %jmp/0xz  T_3.2, 4;
    %pushi/vec4 0, 0, 9;
    %assign/vec4 v0x597a8caf2560_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x597a8caec350_0, 0;
    %jmp T_3.3;
T_3.2 ;
    %load/vec4 v0x597a8caf2560_0;
    %addi 1, 0, 9;
    %assign/vec4 v0x597a8caf2560_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x597a8caec350_0, 0;
T_3.3 ;
T_3.1 ;
    %jmp T_3;
    .thread T_3;
    .scope S_0x597a8cb521e0;
T_4 ;
    %wait E_0x597a8cabe570;
    %load/vec4 v0x597a8cb52790_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_4.0, 8;
    %pushi/vec4 0, 0, 2;
    %assign/vec4 v0x597a8cb52920_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x597a8cb52d30_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x597a8cb52af0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x597a8cb52c70_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v0x597a8cb52880_0, 0;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0x597a8cb525a0_0, 0;
    %jmp T_4.1;
T_4.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x597a8cb52c70_0, 0;
    %load/vec4 v0x597a8cb52920_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 2;
    %cmp/u;
    %jmp/1 T_4.2, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 2;
    %cmp/u;
    %jmp/1 T_4.3, 6;
    %dup/vec4;
    %pushi/vec4 2, 0, 2;
    %cmp/u;
    %jmp/1 T_4.4, 6;
    %dup/vec4;
    %pushi/vec4 3, 0, 2;
    %cmp/u;
    %jmp/1 T_4.5, 6;
    %jmp T_4.6;
T_4.2 ;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x597a8cb52d30_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x597a8cb52af0_0, 0;
    %load/vec4 v0x597a8cb52df0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_4.7, 8;
    %load/vec4 v0x597a8cb52b90_0;
    %assign/vec4 v0x597a8cb52880_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x597a8cb52af0_0, 0;
    %pushi/vec4 1, 0, 2;
    %assign/vec4 v0x597a8cb52920_0, 0;
T_4.7 ;
    %jmp T_4.6;
T_4.3 ;
    %load/vec4 v0x597a8cb52a50_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_4.9, 8;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x597a8cb52d30_0, 0;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0x597a8cb525a0_0, 0;
    %pushi/vec4 2, 0, 2;
    %assign/vec4 v0x597a8cb52920_0, 0;
T_4.9 ;
    %jmp T_4.6;
T_4.4 ;
    %load/vec4 v0x597a8cb52a50_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_4.11, 8;
    %load/vec4 v0x597a8cb52880_0;
    %parti/s 1, 0, 2;
    %assign/vec4 v0x597a8cb52d30_0, 0;
    %pushi/vec4 0, 0, 1;
    %load/vec4 v0x597a8cb52880_0;
    %parti/s 7, 1, 2;
    %concat/vec4; draw_concat_vec4
    %assign/vec4 v0x597a8cb52880_0, 0;
    %load/vec4 v0x597a8cb525a0_0;
    %addi 1, 0, 3;
    %assign/vec4 v0x597a8cb525a0_0, 0;
    %load/vec4 v0x597a8cb525a0_0;
    %cmpi/e 7, 0, 3;
    %jmp/0xz  T_4.13, 4;
    %pushi/vec4 3, 0, 2;
    %assign/vec4 v0x597a8cb52920_0, 0;
T_4.13 ;
T_4.11 ;
    %jmp T_4.6;
T_4.5 ;
    %load/vec4 v0x597a8cb52a50_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_4.15, 8;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x597a8cb52d30_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x597a8cb52c70_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x597a8cb52af0_0, 0;
    %pushi/vec4 0, 0, 2;
    %assign/vec4 v0x597a8cb52920_0, 0;
T_4.15 ;
    %jmp T_4.6;
T_4.6 ;
    %pop/vec4 1;
T_4.1 ;
    %jmp T_4;
    .thread T_4;
    .scope S_0x597a8cb51090;
T_5 ;
    %wait E_0x597a8cabe570;
    %load/vec4 v0x597a8cb51ac0_0;
    %assign/vec4 v0x597a8cb51c40_0, 0;
    %load/vec4 v0x597a8cb51c40_0;
    %assign/vec4 v0x597a8cb51d00_0, 0;
    %jmp T_5;
    .thread T_5;
    .scope S_0x597a8cb51090;
T_6 ;
    %wait E_0x597a8cabe570;
    %load/vec4 v0x597a8cb517b0_0;
    %assign/vec4 v0x597a8cb51b80_0, 0;
    %jmp T_6;
    .thread T_6;
    .scope S_0x597a8cb51090;
T_7 ;
    %wait E_0x597a8cabe570;
    %load/vec4 v0x597a8cb516e0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_7.0, 8;
    %pushi/vec4 0, 0, 2;
    %assign/vec4 v0x597a8cb52040_0, 0;
    %pushi/vec4 0, 0, 9;
    %assign/vec4 v0x597a8cb51dc0_0, 0;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0x597a8caee310_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v0x597a8cb51ea0_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v0x597a8cb518a0_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x597a8cb51940_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x597a8cb51a00_0, 0;
    %jmp T_7.1;
T_7.0 ;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x597a8cb51940_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x597a8cb51a00_0, 0;
    %load/vec4 v0x597a8cb52040_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 2;
    %cmp/u;
    %jmp/1 T_7.2, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 2;
    %cmp/u;
    %jmp/1 T_7.3, 6;
    %dup/vec4;
    %pushi/vec4 2, 0, 2;
    %cmp/u;
    %jmp/1 T_7.4, 6;
    %dup/vec4;
    %pushi/vec4 3, 0, 2;
    %cmp/u;
    %jmp/1 T_7.5, 6;
    %jmp T_7.6;
T_7.2 ;
    %load/vec4 v0x597a8cb51f80_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_7.7, 8;
    %pushi/vec4 0, 0, 9;
    %assign/vec4 v0x597a8cb51dc0_0, 0;
    %pushi/vec4 1, 0, 2;
    %assign/vec4 v0x597a8cb52040_0, 0;
T_7.7 ;
    %jmp T_7.6;
T_7.3 ;
    %load/vec4 v0x597a8cb51dc0_0;
    %pad/u 32;
    %cmpi/e 216, 0, 32;
    %jmp/0xz  T_7.9, 4;
    %pushi/vec4 0, 0, 9;
    %assign/vec4 v0x597a8cb51dc0_0, 0;
    %load/vec4 v0x597a8cb517b0_0;
    %cmpi/e 0, 0, 1;
    %jmp/0xz  T_7.11, 4;
    %pushi/vec4 0, 0, 3;
    %assign/vec4 v0x597a8caee310_0, 0;
    %pushi/vec4 2, 0, 2;
    %assign/vec4 v0x597a8cb52040_0, 0;
    %jmp T_7.12;
T_7.11 ;
    %pushi/vec4 0, 0, 2;
    %assign/vec4 v0x597a8cb52040_0, 0;
T_7.12 ;
    %jmp T_7.10;
T_7.9 ;
    %load/vec4 v0x597a8cb51dc0_0;
    %addi 1, 0, 9;
    %assign/vec4 v0x597a8cb51dc0_0, 0;
T_7.10 ;
    %jmp T_7.6;
T_7.4 ;
    %load/vec4 v0x597a8cb51dc0_0;
    %pad/u 32;
    %cmpi/e 433, 0, 32;
    %jmp/0xz  T_7.13, 4;
    %pushi/vec4 0, 0, 9;
    %assign/vec4 v0x597a8cb51dc0_0, 0;
    %load/vec4 v0x597a8cb517b0_0;
    %load/vec4 v0x597a8cb51ea0_0;
    %parti/s 7, 1, 2;
    %concat/vec4; draw_concat_vec4
    %assign/vec4 v0x597a8cb51ea0_0, 0;
    %load/vec4 v0x597a8caee310_0;
    %addi 1, 0, 3;
    %assign/vec4 v0x597a8caee310_0, 0;
    %load/vec4 v0x597a8caee310_0;
    %cmpi/e 7, 0, 3;
    %jmp/0xz  T_7.15, 4;
    %pushi/vec4 3, 0, 2;
    %assign/vec4 v0x597a8cb52040_0, 0;
T_7.15 ;
    %jmp T_7.14;
T_7.13 ;
    %load/vec4 v0x597a8cb51dc0_0;
    %addi 1, 0, 9;
    %assign/vec4 v0x597a8cb51dc0_0, 0;
T_7.14 ;
    %jmp T_7.6;
T_7.5 ;
    %load/vec4 v0x597a8cb51dc0_0;
    %pad/u 32;
    %cmpi/e 433, 0, 32;
    %jmp/0xz  T_7.17, 4;
    %pushi/vec4 0, 0, 9;
    %assign/vec4 v0x597a8cb51dc0_0, 0;
    %load/vec4 v0x597a8cb517b0_0;
    %cmpi/e 1, 0, 1;
    %jmp/0xz  T_7.19, 4;
    %load/vec4 v0x597a8cb51ea0_0;
    %assign/vec4 v0x597a8cb518a0_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x597a8cb51940_0, 0;
    %jmp T_7.20;
T_7.19 ;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x597a8cb51a00_0, 0;
T_7.20 ;
    %pushi/vec4 0, 0, 2;
    %assign/vec4 v0x597a8cb52040_0, 0;
    %jmp T_7.18;
T_7.17 ;
    %load/vec4 v0x597a8cb51dc0_0;
    %addi 1, 0, 9;
    %assign/vec4 v0x597a8cb51dc0_0, 0;
T_7.18 ;
    %jmp T_7.6;
T_7.6 ;
    %pop/vec4 1;
T_7.1 ;
    %jmp T_7;
    .thread T_7;
    .scope S_0x597a8cb01e50;
T_8 ;
    %wait E_0x597a8cabe570;
    %load/vec4 v0x597a8cb53390_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_8.0, 8;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x597a8cb536f0_0, 0;
    %jmp T_8.1;
T_8.0 ;
    %load/vec4 v0x597a8cb53590_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_8.2, 8;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x597a8cb536f0_0, 0;
T_8.2 ;
T_8.1 ;
    %jmp T_8;
    .thread T_8;
    .scope S_0x597a8cb01e50;
T_9 ;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x597a8cb52fb0_0, 0, 1;
    %end;
    .thread T_9;
    .scope S_0x597a8cb01e50;
T_10 ;
    %delay 10000, 0;
    %load/vec4 v0x597a8cb52fb0_0;
    %inv;
    %store/vec4 v0x597a8cb52fb0_0, 0, 1;
    %jmp T_10;
    .thread T_10;
    .scope S_0x597a8cb01e50;
T_11 ;
    %vpi_call/w 3 58 "$dumpfile", "waveforms/uart_errors.vcd" {0 0 0};
    %vpi_call/w 3 59 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x597a8cb01e50 {0 0 0};
    %end;
    .thread T_11;
    .scope S_0x597a8cb01e50;
T_12 ;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x597a8cb53860_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x597a8cb532b0_0, 0, 32;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x597a8cb53070_0, 0, 32;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x597a8cb53cb0_0, 0, 1;
    %pushi/vec4 0, 0, 8;
    %store/vec4 v0x597a8cb53a40_0, 0, 8;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x597a8cb53150_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x597a8cb531f0_0, 0, 1;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0x597a8cb53390_0, 0, 1;
    %pushi/vec4 10, 0, 32;
T_12.0 %dup/vec4;
    %pushi/vec4 0, 0, 32;
    %cmp/s;
    %jmp/1xz T_12.1, 5;
    %jmp/1 T_12.1, 4;
    %pushi/vec4 1, 0, 32;
    %sub;
    %wait E_0x597a8cabe570;
    %jmp T_12.0;
T_12.1 ;
    %pop/vec4 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x597a8cb53390_0, 0, 1;
    %pushi/vec4 5, 0, 32;
T_12.2 %dup/vec4;
    %pushi/vec4 0, 0, 32;
    %cmp/s;
    %jmp/1xz T_12.3, 5;
    %jmp/1 T_12.3, 4;
    %pushi/vec4 1, 0, 32;
    %sub;
    %wait E_0x597a8cabe570;
    %jmp T_12.2;
T_12.3 ;
    %pop/vec4 1;
    %vpi_call/w 3 199 "$display", "\012=========================================" {0 0 0};
    %vpi_call/w 3 200 "$display", "  UART LAYER 2 - ERROR INJECTION TESTS" {0 0 0};
    %vpi_call/w 3 201 "$display", "=========================================" {0 0 0};
    %fork TD_uart_tb_errors.test_stop_bit_error, S_0x597a8cb0f3c0;
    %join;
    %fork TD_uart_tb_errors.test_glitch_rejection, S_0x597a8cb0f1e0;
    %join;
    %fork TD_uart_tb_errors.test_data_corruption, S_0x597a8cb020f0;
    %join;
    %vpi_call/w 3 207 "$display", "\012=========================================" {0 0 0};
    %vpi_call/w 3 208 "$display", "  SUMMARY" {0 0 0};
    %vpi_call/w 3 209 "$display", "=========================================" {0 0 0};
    %vpi_call/w 3 210 "$display", "Total tests : %0d", v0x597a8cb53860_0 {0 0 0};
    %vpi_call/w 3 211 "$display", "Passed      : %0d", v0x597a8cb532b0_0 {0 0 0};
    %vpi_call/w 3 212 "$display", "Failed      : %0d", v0x597a8cb53070_0 {0 0 0};
    %load/vec4 v0x597a8cb53070_0;
    %cmpi/e 0, 0, 32;
    %flag_mov 8, 4;
    %jmp/0 T_12.4, 8;
    %pushi/vec4 65, 0, 32; draw_string_vec4
    %pushi/vec4 1280057424, 0, 32; draw_string_vec4
    %concat/vec4; draw_string_vec4
    %pushi/vec4 4281171, 0, 24; draw_string_vec4
    %concat/vec4; draw_string_vec4
    %jmp/1 T_12.5, 8;
T_12.4 ; End of true expr.
    %pushi/vec4 1397706053, 0, 32; draw_string_vec4
    %pushi/vec4 541475145, 0, 32; draw_string_vec4
    %concat/vec4; draw_string_vec4
    %pushi/vec4 4998468, 0, 24; draw_string_vec4
    %concat/vec4; draw_string_vec4
    %jmp/0 T_12.5, 8;
 ; End of false expr.
    %blend;
T_12.5;
    %vpi_call/w 3 213 "$display", "Status      : %s", S<0,vec4,u88> {1 0 0};
    %vpi_call/w 3 215 "$display", "=========================================\012" {0 0 0};
    %vpi_call/w 3 217 "$finish" {0 0 0};
    %end;
    .thread T_12;
    .scope S_0x597a8cb01e50;
T_13 ;
    %delay 2000000000, 0;
    %vpi_call/w 3 222 "$display", "WATCHDOG: timeout!" {0 0 0};
    %vpi_call/w 3 223 "$finish" {0 0 0};
    %end;
    .thread T_13;
# The file index is used to find the file name in the following table.
:file_names 7;
    "N/A";
    "<interactive>";
    "-";
    "tb/uart_tb_errors.v";
    "rtl/baud_gen.v";
    "rtl/uart_rx.v";
    "rtl/uart_tx.v";