Unrolled build for #160441

Rollup merge of #160441 - beetrees:inline-asm-fix-powerpc64le, r=Amanieu

PowerPC inline ASM: Fix scalar floats being in the wrong vector lane on little endian

64-bit PowerPC supports both big and little endian, however registers are always big endian. As a consequence of this, the order of vector lanes is reversed on little endian; however scalar `f32` and `f64` are always stored in the actual (big-endian) lane 0. This PR fixes the LLVM ASM fixup to take that into account.

Ping target maintainers: @daltenty @gilamn5tr @amy-kwan @Gelbpunkt @famfo @neuschaefer

Author: rust-timer

compiler/rustc_codegen_llvm/src/asm.rs

@@ -1,7 +1,7 @@
 use std::assert_matches;
 use std::fmt::Write;
 
-use rustc_abi::{BackendRepr, Float, Integer, Primitive, Scalar, Size};
+use rustc_abi::{BackendRepr, Endian, Float, Integer, Primitive, Scalar, Size};
 use rustc_ast::{InlineAsmOptions, InlineAsmTemplatePiece};
 use rustc_codegen_ssa::mir::operand::OperandValue;
 use rustc_codegen_ssa::traits::*;
@@ -12,6 +12,7 @@ use rustc_middle::ty::layout::TyAndLayout;
 use rustc_middle::{bug, span_bug};
 use rustc_span::{Pos, Span, Symbol, sym};
 use rustc_target::asm::*;
+use rustc_target::spec::HasTargetSpec;
 use smallvec::SmallVec;
 use tracing::debug;
 
@@ -1244,24 +1245,16 @@ fn llvm_fixup_input<'ll, 'tcx>(
         (
             PowerPC(PowerPCInlineAsmRegClass::vreg | PowerPCInlineAsmRegClass::vsreg),
             BackendRepr::Scalar(s),
-        ) if s.primitive() == Primitive::Float(Float::F32) => {
-            let value = bx.insert_element(
-                bx.const_undef(bx.type_vector(bx.type_f32(), 4)),
+        ) if let Primitive::Float(float @ (Float::F32 | Float::F64)) = s.primitive() => {
+            let num_lanes = 16 / float.size().bytes();
+            bx.insert_element(
+                bx.const_undef(bx.type_vector(bx.type_from_float(float), num_lanes)),
                 value,
-                bx.const_usize(0),
-            );
-            bx.bitcast(value, bx.type_vector(bx.type_f32(), 4))
-        }
-        (
-            PowerPC(PowerPCInlineAsmRegClass::vreg | PowerPCInlineAsmRegClass::vsreg),
-            BackendRepr::Scalar(s),
-        ) if s.primitive() == Primitive::Float(Float::F64) => {
-            let value = bx.insert_element(
-                bx.const_undef(bx.type_vector(bx.type_f64(), 2)),
-                value,
-                bx.const_usize(0),
-            );
-            bx.bitcast(value, bx.type_vector(bx.type_f64(), 2))
+                bx.const_usize(match bx.target_spec().endian {
+                    Endian::Little => num_lanes - 1,
+                    Endian::Big => 0,
+                }),
+            )
         }
         _ => value,
     }
@@ -1416,16 +1409,15 @@ fn llvm_fixup_output<'ll, 'tcx>(
         (
             PowerPC(PowerPCInlineAsmRegClass::vreg | PowerPCInlineAsmRegClass::vsreg),
             BackendRepr::Scalar(s),
-        ) if s.primitive() == Primitive::Float(Float::F32) => {
-            let value = bx.bitcast(value, bx.type_vector(bx.type_f32(), 4));
-            bx.extract_element(value, bx.const_usize(0))
-        }
-        (
-            PowerPC(PowerPCInlineAsmRegClass::vreg | PowerPCInlineAsmRegClass::vsreg),
-            BackendRepr::Scalar(s),
-        ) if s.primitive() == Primitive::Float(Float::F64) => {
-            let value = bx.bitcast(value, bx.type_vector(bx.type_f64(), 2));
-            bx.extract_element(value, bx.const_usize(0))
+        ) if let Primitive::Float(float @ (Float::F32 | Float::F64)) = s.primitive() => {
+            let num_lanes = 16 / float.size().bytes();
+            bx.extract_element(
+                value,
+                bx.const_usize(match bx.target_spec().endian {
+                    Endian::Little => num_lanes - 1,
+                    Endian::Big => 0,
+                }),
+            )
         }
         _ => value,
     }
@@ -1566,11 +1558,9 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
         (
             PowerPC(PowerPCInlineAsmRegClass::vreg | PowerPCInlineAsmRegClass::vsreg),
             BackendRepr::Scalar(s),
-        ) if s.primitive() == Primitive::Float(Float::F32) => cx.type_vector(cx.type_f32(), 4),
-        (
-            PowerPC(PowerPCInlineAsmRegClass::vreg | PowerPCInlineAsmRegClass::vsreg),
-            BackendRepr::Scalar(s),
-        ) if s.primitive() == Primitive::Float(Float::F64) => cx.type_vector(cx.type_f64(), 2),
+        ) if let Primitive::Float(float @ (Float::F32 | Float::F64)) = s.primitive() => {
+            cx.type_vector(cx.type_from_float(float), 16 / float.size().bytes())
+        }
         _ => layout.llvm_type(cx),
     }
 }