ReleaseNotes.txt

Release Notes

HEAD, planned as v0.14
- Added VHDL export
  (Not yet complete, but the example processor is running on a FPGA.)
- Type of pin numbers changed from int to string to allow FPGA pin names like "U16".
- Added support for BASYS3-Board (*.xdc constrains file is written)
- Added visualization of KV maps (thanks to roy77)
- Breaking changes:
  - To generalize the VHDL export, an XML entity in the *.dig files had to be renamed.
    As a consequence of that the address bits settings in RAMs and ROMs
    are lost. To fix that, reset the number of address bits.
  - Added an enable input to the counter component. If you had used the counter in the
    past you have to set the en input to 1. The function of the overflow output also
    has changed (see tooltip) and now allows the cascading of counters.
  - XOR now can have more than two inputs. If you had used the XOR gate with inverted
    inputs, you have to reselect the inputs to invert.

v0.13, released on 25. Jul 2017
- Introduced a library of sub circuits which are available in every circuit.
  So far, the library contains only the 74xx circuits.
- Added a barrel shifter (thanks to roy77)
- some improvements concerning error messages:
  - In case of oscillations almost all affected components are shown.
  - If an error occurs, the name of the affected circuit file is shown.
  - If an error occurs, the causing sub circuit is highlighted.
  - A warning message shows up if a circuit with unnamed inputs is analysed.
  - A warning message shows up if a circuit with missing pin numbers is exported to a
    hardware-related file.
- Unidirectional FETs are added to overcome certain CMOS issues.
- Added zooming to measurement graphs.
- Test results can be displayed as measurement graphs.
- The Text component is able to show multiple lines.
- Comments are allowed in hex files.
- Some minor bug fixes
- Breaking changes:
  - An input can have "high z" value as its default value.
    All inputs have lost their default values! If you have build a circuit that
    contains test cases that depend on a non-null default value, this tests
    will fail. To resolve this issue, reset the default value.
  - Added an enable input to the T flip-flop
    By default this input is activated now. In circuits which used the T flip-flop
    in the past, the new input needs to be disabled.

v0.12.1, released on 05. Jun 2017
- added a fuse to simulate a PROM or PAL.
- added some more CMOS examples
- Improved flexibility of the splitter.

v0.12, released on 02. Jun 2017
- Added undo/redo functions.
- New wire drawing mode: If a wire is added it is rectangular by default.
  In rectangular mode "F" flips the wire and pressing "D" switches to diagonal mode.
- Added inverted inputs for basic gates and flip-flops.
- Added a locked mode, which avoids the unwanted modification of the circuit.
- Better support for high dpi screens.
- Added DIL packages to allow more "physical" circuits. See examples/74xx.
  Up to now only a view 74xx circuits are available.
- Added a pin number attribute to inputs and outputs.
- Add some functions to make it easier to create 74xx circuits.
- Lots of small usability improvements.
- Added a list of keyboard shortcuts to the documentation.

v0.11.1, released on 02. May 2017
- Added the possibility to open a circuit from the command line.
- The backspace key works like the delete key.
- Avoid extreme long lines in the error message dialog.
- Some minor bug fixes.

v0.11, released on 20. Apr 2017
- Added floating gate FETs.
- Better detecting of missing signals in test cases.
- Better plausibility checks if diodes are used.
- Added a loop command to the test data parser.
  See "cmos/sram.dig" as an example usage of the new loop statement.

v0.10, released on 09. Apr 2017
- User can select the expressions representation format in the settings dialog.
- Better formatting of minimized expressions.
- Easier editing of truth tables
- Mouse actions can be canceled by the ESC key.
- With CTRL + mouse button you can now select and move/delete wires.
- Added a real bidirectional switch and a relay.
- Added N and P channel FETs and some CMOS examples, including a 16 bit SRAM
- Added a rotary encoder
- Added a LED matrix display
- Improved and documented the file import strategy.
- Added a tree view to insert components.
- Added support for the ATF1502 and ATF1504 CPLDs.
- some minor bug fixes

v0.9, released on 03. Feb 2017
- improved documentation
- moved "show listing" functions to the assembly IDE.
- rearrangement of the components in the components menu
- made "don't care" as test case input values functional
- added a better test data parser which supports a "repeat([n])" statement.
  See the "combinatorial/FullAdderCLA.dig" as an example usage of the new "repeat([n])" statement.
- cleanup of splitter behaviour in respect of high z inputs
- fixed an error that caused an exception if a circuit which directly connects an input to an output
  is used as embedded circuit.
- some minor bug fixes

v0.8, released on 20. Nov 2016
- added pull up & pull down resistors and programmable diodes
- added some PLD examples like a simple PLA and GAL
- added GND, VDD and a switch
- added a help dialog for components
- added a simple documentation viewable via the help menu
- fixed "sometimes unwanted start of drawing a wire" problem (hopefully)
- some minor bug fixes

v0.7, released on 22. Aug 2016
- fixed a bug which causes two HighZ values to be not equal during test execution.
- added double buffer to CircuitComponent to make it more responsive
- improved debugging of processors
- some minor bug fixes

v0.6.2, released on 16. Aug 2016
- fixed scrolling bug in input/output orderer
- fixed redraw bug at element rotation
- fixed auto scale bug if element is deleted

v0.6.1, released on 10. Aug 2016
- fixed auto scaling bug which can occur if a new circuit is created
- added missing check for unsaved modifications
- fixed unexpected behaviour of 'C' character in test cases
- some minor bug fixes

v0.6, released on 09. Aug 2016
- fixed sync problems while drawing the circuit
- added Conway's Game of Life example
- some minor bug fixes

v0.5, released on 16. Jul 2016
- creation of state machines with JK-flip-flops
- added creation of JEDEC and CUPL files for GAL16v8 and GAL22v10
- some minor bug fixes

v0.4, released on 12. Jul 2016
- added a graphics card
- some minor bug fixes

v0.3.1, released on 07. Jul 2016
- some minor bug fixes

v0.3, released on 07. Jul 2016
- added testing functions
- some minor bug fixes

v0.2, released on 02. Jul 2016
- added expression parser
- creation of circuits from expressions
- some bug fixes

v0.1, released on 28. Jun 2016
- initial release