bender script emits .svh header files as compile sources (regression in 0.32.0)

[fischeti]

Summary

Since v0.32.0, bender script emits SystemVerilog header files (.svh) that are listed in a package's files: as standalone compile sources. Previously (v0.31.0), such files were recognized as headers of unknown compile type (W28), kept out of the emitted source list, and reachable only via +incdir+.

This is a breaking change for the common convention of listing .svh headers in files: (so bender tracks them) while including them via include_dirs. Compiling a header standalone and via `include causes duplicate definitions — e.g. VCS reports class redefinition and fails elaboration.

Minimal reproduction

Bender.yml:

package:
  name: repro
  authors: ["repro"]

sources:
  - include_dirs:
      - inc
    files:
      - src/tracer.sv       # compiles; `include "trace_item.svh"
      - inc/trace_item.svh  # header: listed in files: for tracking, also on +incdir+inc

src/tracer.sv:

`include "trace_item.svh"
module tracer; endmodule

inc/trace_item.svh:

class trace_item; endclass

Run bender script vcs with each version:

0.31.0 — header excluded from sources, warned as unknown type:

    "+incdir+$ROOT/inc" \
    "$ROOT/src/tracer.sv"

warning[W28]: File with unknown type:
  - /tmp/bender-svh-repro/inc/trace_item.svh

0.32.0 — header now emitted as a compile source:

    "+incdir+$ROOT/inc" \
    "$ROOT/src/tracer.sv" \
    "$ROOT/inc/trace_item.svh"

Diff of the emitted source list (0.31.0 -> 0.32.0):

     "$ROOT/src/tracer.sv"
+    "$ROOT/inc/trace_item.svh"

Real-world impact

cva6 lists its tracer headers in files: (under target: not(synthesis)), alongside the .sv that includes them:

- include_dirs: [core/include, common/local/util]
  files:
    - common/local/util/instr_tracer.sv
    - common/local/util/instr_trace_item.svh
    - common/local/util/ex_trace_item.svh

With 0.32.0, ex_trace_item.svh is both `included (via +incdir+common/local/util) and compiled standalone, so VCS errors:

Error-[CRE] Class redefinition encountered
  The class 'ex_trace_item' is defined more than once.
Error-[SVBENM] End name does not match the begin name
  endclass name is 'ex_trace_item', while the class name is 'ex_trace_item_0'.

-> no top module found -> elaboration fails. (Questa/vsim tolerates the duplicate via separate compilation units, so this surfaces specifically with VCS.)

Environment

• Regression introduced in v0.32.0 (works in v0.31.0)
• bender script vcs (also affects vsim/other script targets)

[fischeti]

Update: digging into the concrete case, the root cause is arguably on the manifest side, not bender.

The headers that triggered this (instr_trace_item.svh / ex_trace_item.svh) were removed from cva6's Bender.yml upstream in openhwgroup/cva6#1493 (2023-10-02), then re-added in the pulp-platform fork (dc1da0b07, 2023-12-22). So upstream already treats listing these headers in files: as incorrect, and 0.32.0's "compile what's in files:" behavior is defensible.

Tracking the manifest fix here: pulp-platform/cva6#71.

[micprog]

I think this slipped in here: 2673472#diff-2d9a3a31ea498099b80abcd103e92887da1c596167f238c485656906d2b8b9e4

[fischeti]

Right! The question is: should .svh be considered as as verilog files too or should I revert it? I think it definitely also makes sense to remove them from the cva6 manifest, as before, those files were just silently filtered out.

[micprog]

Let's remove it - if users would like to parse as systemverilog, users can prefix the file with sv: in the Bender.yml to force systemverilog format for the file.

[fischeti]

makes sense. I opened a PR: #313