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Glossary

Vendors

  • AMD: Advanced Micro Devices, manufacturer of CPLDs (e.g. MACH)
  • Xilinx: manufacturer of CPLDs and in particular FPGAs
  • Intel: Intel Corporation (active in the PLD/FPGA space via its acquisition of Altera)
  • Altera: former PLD/FPGA division of Intel (previously independent; known e.g. for MAX CPLDs)
  • LSC: Lattice Semiconductor Corporation

Software

  • OpenOCD: Open On-Chip Debugger - FOSS software for programming or debugging integrated circuits, capable of executing SVF files

Lattice

  • PALtoGAL: Converts configuration files for PAL devices to GAL

AMD

  • MACHXL: AMD's tool for designing with MACH 3 and MACH 4 PLDs

Xilinx

  • XNF2WIR: Xilinx tool that converts XNF netlists into a WIR format
  • XNF2VST: Xilinx tool that converts/generates VST view files from netlists
  • VIEWlogic: Xilinx tool for graphical/analytical visualization of logic structures
  • VIEWsim: Xilinx tool for simulation/analysis of logic designs

Integrated circuits

PAL

  • PAL33V16: PAL device with 33 inputs and 16 outputs
  • PAL16L8: PAL device with 16 inputs and 8 outputs
  • PAL16R8: PAL device with 16 inputs and 8 outputs
  • PAL18V8: PAL device with 18 inputs and 8 outputs
  • PAL20L10: PAL device with 20 inputs and 10 outputs
  • PAL22V10: PAL device with 22 inputs and 10 outputs
  • PAL24V10: PAL device with 24 inputs and 10 outputs

GAL

  • GAL16V8: GAL device with 16 inputs and 8 outputs
  • GAL20V8: GAL device with 20 inputs and 8 outputs
  • GAL22V10: GAL device with 22 inputs and 10 outputs
  • GAL26V12: GAL device with 26 inputs and 12 outputs
  • GAL30V18: GAL device with 30 inputs and 18 outputs

Altera's MAX family

  • MAX7000: Series of CPLD devices from Altera (Intel), programmed using EEPROM programming
  • MAX7000S: Series of CPLD devices from Altera (Intel), with JTAG and ISP support
  • EPM7032S: Altera MAX7000S-series CPLD with 32 macrocells

AMD's MACH family

  • MACH 1, MACH 2, MACH 3, MACH 4: Serieses of CPLD devices from AMD
  • MACH130: MACH PLD family model (fuse-/LUT-like logic architecture)
  • MACH1230: MACH PLD family model
  • MACH435-15: eight PAL33V16-like blocks connected via a central switch matrix, with 128 synchronous or asynchronous configurable MCs, built-in XOR, and up to 20 PTs per MC

Technological terms

  • PLD: Programmable Logic Device - generic term for devices such as CPLDs and FPGAs that can be configured after manufacturing
  • PLA: Programmable Logic Array - configurable logic device architecture with programmable AND and programmable OR planes
  • PAL: Programmable Array Logic - configurable logic device architecture with a programmable AND plane and fixed OR plane; trademark of AMD
  • EPLD: Erasable Programmable Logic Device - class of PLDs that can be erased in-system (or after disassembly) and reprogrammed
  • PEEL: Programmable Electrically Erasable Logic - term for electrically erasable logic blocks/PLDs
  • GAL: Generic Array Logic - PAL/GAL-like family/variant with electrically erasable logic
  • PT: Product Term - basic AND term in a sum-of-products expression
  • SOP: Sum Of Products - canonical form combining several product terms by ORing them
  • LC: Logic Cell - device-family-specific composition of PTs, logic gates, multiplexers and one DFF
  • LAB: Logic Array Block - grouping of logic cells in a MAX7000 device sharing local routing and control signals
  • PIA: Programmable Interconnect Array - configurable interconnect structure for routing internal signals
  • REG: Register - flip-flop, prominently D-type
  • FF: Flip-flop - one-bit storage element
  • DFF: D-type flip-flop - flip-flop with data input D
  • MUX: Multiplexer - in the context of PLDs, logical entity for routing internal signals according to configuration bits (bitstream)
  • CPLD: Complex Programmable Logic Device - non-volatile programmable logic device family including the Altera MAX7000 series
  • JTAG: Joint Test Action Group - IEEE 1149.x boundary scan interface for communicating with and programming a device
  • ISP: In-System Programming - programming a CPLD or other PLD while it is soldered into the target system, typically via JTAG
  • TAP: Test Access Port - JTAG interface on the device including pins and TAP state machine
  • LCA: Logic Cell Array - term used by Xilinx in the context of XC3000 FPGAs, referring to the configurable fabric
  • CMOS: Complementary Metal-Oxide Semiconductor - semiconductor technology using complementary MOS transistors
  • XACT: Term and trademark of Xilinx
  • XACTOR: Term and trademark of Xilinx
  • ROM: Read-Only Memory - non-volatile memory with fixed, programmed content
  • RAM: Random Access Memory - volatile memory with random access
  • PROM: Programmable ROM - one-time (or limited) programmable ROM type
  • EPROM: Erasable PROM - PROM that can be erased by UV light and reprogrammed
  • EEPROM/E²PROM: Electrically Erasable PROM - PROM that can be erased electrically and reprogrammed
  • ADC: Analog-to-Digital Converter
  • DAC: Digital-to-Analog Converter

Methods

  • PNR: Place and Route - design step mapping logic onto physical device resources and calculating necessary routing between them
  • BST: Boundary Scan Testing - testing integrated circuits via boundary scan chains, typically over JTAG
  • ISC: In-System Configuration - standardized JTAG-based method for configuring programmable logic devices in-circuit
  • OCD: On-chip debugging - observing and controlling a running system via debug logic
  • IEEE 1149.1: JTAG boundary-scan standard defining TAP, instructions and basic test infrastructure for digital ICs
  • IEEE 1532: in-system configuration standard for programmable logic devices building on JTAG (IEEE 1149.1)

Formats

  • BIT: raw bitstream - binary configuration data for a device
  • RBF: Raw Bitstream File - file containing a raw bitstream
  • JEDEC: JEDEC fuse vector - interchange format for fuse/bit mappings, stored as a textual list of configuration bits
  • BSDL: Boundary Scan Description Language - IEEE language describing a device's boundary scan (JTAG) structure
  • PALASM: PAL Assembler - textual language for describing logic equations and pin assignments for PAL- and CPLD-style devices; trademark of AMD
  • FASM: FPGA Assembly - textual, human-readable, feature-based format for specifying logical configurations as an intermediate between place-and-route output and low-level bitstream
  • PLDCONF: Programmable Logic Device Configuration - C-style, human-readable configuration file format used as an intermediate before FASM and bitstream generation
  • POF: Programmable Object File - Altera-proprietary flash/bitstream file format
  • SVF: Serial Vector Format - textual format storing a sequence of JTAG operations e.g. for programming or testing a JTAG-capable device
  • STAPL: Standard Test and Programming Language - JTAG-based test/programming format for PLDs (often output as .jam/.jbc)
  • CUPL: trademark of Logical Devices
  • ABEL: Advanced Boolean Expression Language - text-based input language for PAL/CPLD logic
  • Log/IC: historical design/input tool for logic design (e.g. for PAL/GAL-like devices)
  • PLDesigner: design/engineering tool (historical) for PLD logic design; specific usage depends on vendor/version

PALASM

  • TITLE: directive for naming a design or file
  • DEVICE: directive for selecting target device type or family
  • PIN: directive for assigning logical signals to device pins
  • EQUATIONS: section for specifying Boolean equations for outputs and internal nodes
  • FIELD: directive for defining bit fields in vectors to simplify equations
  • TABLE: directive for describing combinational behaviour as a truth table

SVF

  • STATE: statement for forcing the TAP controller into a specific stable state
  • RUNTEST: statement for keeping the TAP in a state for a given number of TCK cycles or a given time
  • SIR: Shift Instruction Register - statement for shifting a value into the instruction register (IR)
  • SDR: Shift Data Register - statement for shifting a value into the currently selected data register (DR)
  • FREQUENCY: statement for constraining maximum JTAG clock frequency for subsequent operations
  • TRST: statement for declaring use or absence of the TRST reset signal
  • ENDDR / ENDIR: options for defining the TAP end state after DR or IR shifting

JTAG

  • TEST_LOGIC_RESET: TAP state for resetting JTAG logic and returning to a defined idle condition
  • RUN_TEST / IDLE: TAP state for idling or running built-in self-test between scan operations
  • SHIFT_IR: TAP state for shifting bits through the instruction register
  • SHIFT_DR: TAP state for shifting bits through the currently selected data register
  • UPDATE_IR: TAP state for updating instruction register contents from the shift path
  • UPDATE_DR: TAP state for updating data register contents from the shift path
  • PAUSE_IR / PAUSE_DR: TAP states for temporarily pausing shifting of IR or DR while preserving contents
  • BYPASS: instruction selecting a single-bit bypass register for minimal scan length
  • IDCODE: instruction selecting a device identification register containing a fixed ID value
  • SAMPLE / PRELOAD: instruction for sampling pin values into the boundary register and/or preloading boundary-scan data
  • EXTEST: instruction for using boundary-scan cells to drive and sample external pins for board-level testing

BSDL

  • entity: top-level BSDL construct naming the JTAG-capable device
  • generic / port: constructs for declaring configuration parameters and I/O pins of the device
  • TAP_SCAN_IN / TAP_SCAN_OUT / TAP_SCAN_MODE / TAP_SCAN_CLOCK: attributes mapping JTAG pins (TDI, TDO, TMS, TCK) to logical ports
  • INSTRUCTION_LENGTH: attribute giving the number of bits in the instruction register
  • INSTRUCTION_OPCODE: attribute mapping instruction mnemonics (e.g. EXTEST, SAMPLE, BYPASS, IDCODE) to opcode bit patterns
  • BOUNDARY_LENGTH: attribute giving the number of cells in the boundary-scan register
  • BOUNDARY_REGISTER: attribute describing the boundary-scan cells, their associated pins and functions

Signals and registers

Logic

  • OE: Output Enable - signal controlling whether an output driver actively drives a pin
  • CLK: Clock - periodic signal triggering synchronous logic and flip-flops
  • GCLK: Global Clock - dedicated clock distribution network feeding logic cells across the device
  • CLR: Clear - signal asynchronously resetting/clearing logic cells
  • GCLR: Global Clear - dedicated global reset/clear signal asynchronously resetting logic cells

JTAG

  • TMS: Test Mode Select - JTAG control signal steering the TAP controller through its state machine
  • TCK: Test Clock - JTAG clock signal advancing the TAP state machine and shifting data through scan chains
  • TDI: Test Data In - JTAG data input pin for shifting instructions and data into the device
  • TDO: Test Data Out - JTAG data output pin for shifting data and status information out of the device
  • TRST: Test Reset - optional JTAG reset signal for asynchronous reset of the TAP controller
  • ICR: Instruction Control Register - JTAG-accessible register for controlling/configuring in-system configurations (e.g. according to IEEE 1532)

SPI

  • SCLK: Serial Clock - clock signal used for SPI transfers
  • MOSI: Master Out Slave In - data line used for SPI transfers from master to slave
  • MISO: Master In Slave Out - data line used for SPI transfers from slave to master
  • CS: Chip Select - active-select line used to enable a specific SPI slave

I²C

  • SCL: Serial Clock Line - clock line used for I²C transfers
  • SDA: Serial Data Line - bidirectional data line used for I²C transfers

UART

  • TXD: Transmit Data - UART/serial output for sending data
  • RXD: Receive Data - UART/serial input for receiving data
  • RTS: Request To Send - handshake signal indicating that a sender wants to transmit data
  • CTS: Clear To Send - handshake signal that allows the sender to transmit
  • DSR: Data Set Ready - modem/end-device status signal (ready)
  • DCD: Data Carrier Detect - signal indicating that a carrier/connection was detected at the modem
  • DTR: Data Terminal Ready - handshake signal indicating that a terminal is ready

Power

  • VCC: supply voltage (positive operating voltage)
  • VDD: supply voltage (positive voltage for a circuit/logic power domain)
  • VPP: programming voltage - often a higher voltage used for programming/erasing
  • GND: Ground - reference potential (0V)
  • AGND: Analog ground - stabilized reference potential for analog circuits

Links