feat(rtl): replace mock global_mem_controller with AXI4 manager skeleton (#19)

Replaces the original behavioural mock that lived in
src/global_mem_controller.sv with an AXI4-backed skeleton built from the
already-merged primitives (global_mem_axi4_adapter + axi4_mem_model). The
external port surface (core1_* + contr_*) is preserved verbatim so that
upstream consumers (gpu_die.sv, test/behav/*) continue to compile and
simulate without modification — that migration is a separate Phase-3 PR.

Per ADR-006 (Internal bus: AXI4) and the merged PARAMETER_TAXONOMY.md, the
internal AXI4 manager is wired with phys_addr_width=48 and
mem_data_width=256 (proven by test_axi4_widths_wired). External ports stay
at the upstream addr_width=32 / data_width=32, with the adapter
zero-extending into the wider AXI4 bus.

Internal composition:
  core1_*    -> arbiter -> global_mem_axi4_adapter -> AXI4 -> axi4_mem_model
  contr_rd_* -> arbiter (priority below core1, with pending-request latch)
  contr_wr_* -> axi4_mem_model loader back-door (no handshake, single cycle)

Out of scope for this PR (deferred):
  * Real DDR3/DDR5 controller (LiteDRAM) — single instantiation swap.
  * Pipelined / multi-outstanding transactions on either port group.
  * Migration of upstream consumers off the bespoke port surface.

Test evidence (cocotb + Verilator 5.048):
  TESTS=7 PASS=7 FAIL=0 SKIP=0
  - test_reset
  - test_axi4_widths_wired           [proves phys_addr_width=48, mem_data_width=256]
  - test_core1_word_roundtrip        [low addr 0x80]
  - test_core1_high_address          [top of SRAM range, exercises 32-bit addr path]
  - test_contr_loader_then_core1_read [both port groups + cache-line slot]
  - test_contr_readback_via_arbiter  [contr_rd path]
  - test_arbiter_priority_core1_wins [pending-request latch]

Sibling verif/global_mem_axi4_adapter/ regression: TESTS=6 PASS=6 (unchanged).

Closes #2.

Authored by Agent 1 (RTL Architect).

Co-authored-by: Marcos <m@pop.coop>

Author: marcos-mendez