Every now and then, when I make some major change in a module the synthesizer refuses to give me workable files.
I am getting loads of timing errors again. There is a task in quartus called Design Assistant where it gives you coding recommendations. Well, the list is rather large. An easy one to fix is the ripple clock structures. It affects to the way I generate a clk/6 clock and then drive all the logic from it on JT12, for instance. But there are more cases.
I think it was Alastair who suggested to use fewer clocks and more clock enable signals. I am exploring that on JT12 and JT89. I am also using synthesis attributes in order to tell the synthesizer which signal is the clock enable. In verilog this is done with (* direct_enable *) in front of the signal declaration.
Every now and then, when I make some major change in a module the synthesizer refuses to give me workable files.
I am getting loads of timing errors again. There is a task in quartus called Design Assistant where it gives you coding recommendations. Well, the list is rather large. An easy one to fix is the ripple clock structures. It affects to the way I generate a clk/6 clock and then drive all the logic from it on JT12, for instance. But there are more cases.
I think it was Alastair who suggested to use fewer clocks and more clock enable signals. I am exploring that on JT12 and JT89. I am also using synthesis attributes in order to tell the synthesizer which signal is the clock enable. In verilog this is done with
(* direct_enable *)in front of the signal declaration.