AST (Abstract Syntax Tree) from OpenVAF

[EktaBhaskar]

Is there a way to get the AST (Abstract Syntax Tree) out of Lexer->Preprocessor -> Parser modules? I'm new in rust, can't figure out how output of 1 module is stored and passed to another.

[pascalkuthe]

The interface that is exposed by the various frontend crates is the compilation database. The AST for a single Verilog-A file is exposed by BasedDB::parse (in the basedb crate). However, I doubt you will find the AST very useful as its just a very thin wrapper around the raw syntax tree generated by the parser.

OpenVAF builds multiple data structures (collectively called HIR) on top of the AST to extract semantic information (what declaration an identifier resolves to, what types something has etc). This happens in the hir_def and hir_ty crates. The HIR contains significantly more semantic information than the AST but it doesn't contain the information/code needed by circuit simulator. That information/code is generated in the backend (osdi, sim_back, mir, mir_opt, mir_autodiff, hir_lower) and use their own SSA based IR (called MIR).

If you provide me with more information about what you are trying to accomplish I can give you a more detailed answer.