The tool does not seem to work (produce the correct JSONs) for vcd files generated from iverilog's simulator. Is there a specific format for the vcd files that vcd2json expects? Is there a way to get the same from iverilog? Are there other simulators that vcd2json supports part from cver?
Waveform (wavedrom) from JSON for vcd file from iverilog's simulation of timer.v
Waveform (wavedrom) from JSON for vcd file from cver simulation of timer.v
timer_iverilog.vcd
$date Mon Jan 5 23:03:22 2026 $end $version Icarus Verilog $end $timescale 1s $end $scope module tb_timer $end $var wire 1 ! pulse $end $var reg 1 " clock $end $var reg 1 # reset $end $scope module u_timer $end $var wire 1 " clock $end $var wire 1 # reset $end $var wire 1 $ count_eq11 $end $var reg 4 % count [3:0] $end $var reg 1 ! pulse $end $upscope $end $upscope $end $enddefinitions $end $comment Show the parameter values. $end $dumpall $end #0 $dumpvars bx % x$ 0# 0" x! $end #10 1" #20 0" #30 1" #40 0" #50 1" #60 0" #70 1" #80 0" #90 1# 1" #100 0" #110 0$ b0 % 1" #120 0" #130 0! 1" #140 0" #150 1" #160 0" #170 1" #180 0" #190 0# 1" #200 0" #210 b1 % 1" #220 0" #230 b10 % 1" #240 0" #250 b11 % 1" #260 0" #270 b100 % 1" #280 0" #290 b101 % 1" #300 0" #310 b110 % 1" #320 0" #330 b111 % 1" #340 0" #350 b1000 % 1" #360 0" #370 b1001 % 1" #380 0" #390 b1010 % 1" #400 0" #410 1$ b1011 % 1" #420 0" #430 1! 0$ b0 % 1" #440 0" #450 b1 % 0! 1" #460 0" #470 b10 % 1" #480 0" #490 b11 % 1" #500 0" #510 b100 % 1" #520 0" #530 b101 % 1" #540 0" #550 b110 % 1" #560 0" #570 b111 % 1" #580 0" #590 b1000 % 1" #600 0" #610 b1001 % 1" #620 0" #630 b1010 % 1" #640 0" #650 1$ b1011 % 1" #660 0" #670 1! 0$ b0 % 1" #680 0" #690 b1 % 0! 1" #700 0" #710 b10 % 1" #720 0" #730 b11 % 1" #740 0" #750 b100 % 1" #760 0" #770 b101 % 1" #780 0" #790 b110 % 1" #800 0" #810 b111 % 1" #820 0" #830 b1000 % 1" #840 0" #850 b1001 % 1" #860 0" #870 b1010 % 1" #880 0" #890 1$ b1011 % 1" #900 0" #910 1! 0$ b0 % 1" #920 0" #930 b1 % 0! 1" #940 0" #950 b10 % 1" #960 0" #970 b11 % 1" #980 0" #990 b100 % 1" #1000 0"
timer_cver.vcd
$date Tue Jan 6 11:21:31 2026 $end $version GPLCVER_2.12a of 05/16/07 $end $timescale 1 ns $end $scope module tb_timer $end $var reg 1 ! clock $end $var wire 1 " pulse $end $var reg 1 # reset $end $scope module u_timer $end $var wire 1 $ clock $end $var reg 4 % count [3:0] $end $var wire 1 & count_eq11 $end $var reg 1 ' pulse $end $var wire 1 ( reset $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars 0$ bx % x& x' 0( 0! x" 0# $end #10 1" 0& 1' b1111 % 1$ 1! #20 0$ 0! #30 0" 0' b0 % 1$ 1! #40 0$ 0! #50 b1 % 1$ 1! #60 0$ 0! #70 b10 % 1$ 1! #80 0$ 0! #90 1( b11 % 1# 1$ 1! #100 0$ 0! #110 b0 % 1$ 1! #120 0$ 0! #130 1$ 1! #140 0$ 0! #150 1$ 1! #160 0$ 0! #170 1$ 1! #180 0$ 0! #190 0( 0# 1$ 1! #200 0$ 0! #210 b1 % 1$ 1! #220 0$ 0! #230 b10 % 1$ 1! #240 0$ 0! #250 b11 % 1$ 1! #260 0$ 0! #270 b100 % 1$ 1! #280 0$ 0! #290 b101 % 1$ 1! #300 0$ 0! #310 b110 % 1$ 1! #320 0$ 0! #330 b111 % 1$ 1! #340 0$ 0! #350 b1000 % 1$ 1! #360 0$ 0! #370 b1001 % 1$ 1! #380 0$ 0! #390 b1010 % 1$ 1! #400 0$ 0! #410 1& b1011 % 1$ 1! #420 0$ 0! #430 1" 0& 1' b0 % 1$ 1! #440 0$ 0! #450 0" 0' b1 % 1$ 1! #460 0$ 0! #470 b10 % 1$ 1! #480 0$ 0! #490 b11 % 1$ 1! #500 0$ 0! #510 b100 % 1$ 1! #520 0$ 0! #530 b101 % 1$ 1! #540 0$ 0! #550 b110 % 1$ 1! #560 0$ 0! #570 b111 % 1$ 1! #580 0$ 0! #590 b1000 % 1$ 1! #600 0$ 0! #610 b1001 % 1$ 1! #620 0$ 0! #630 b1010 % 1$ 1! #640 0$ 0! #650 1& b1011 % 1$ 1! #660 0$ 0! #670 1" 0& 1' b0 % 1$ 1! #680 0$ 0! #690 0" 0' b1 % 1$ 1! #700 0$ 0! #710 b10 % 1$ 1! #720 0$ 0! #730 b11 % 1$ 1! #740 0$ 0! #750 b100 % 1$ 1! #760 0$ 0! #770 b101 % 1$ 1! #780 0$ 0! #790 b110 % 1$ 1! #800 0$ 0! #810 b111 % 1$ 1! #820 0$ 0! #830 b1000 % 1$ 1! #840 0$ 0! #850 b1001 % 1$ 1! #860 0$ 0! #870 b1010 % 1$ 1! #880 0$ 0! #890 1& b1011 % 1$ 1! #900 0$ 0! #910 1" 0& 1' b0 % 1$ 1! #920 0$ 0! #930 0" 0' b1 % 1$ 1! #940 0$ 0! #950 b10 % 1$ 1! #960 0$ 0! #970 b11 % 1$ 1! #980 0$ 0! #990 b100 % 1$ 1! #1000
The tool does not seem to work (produce the correct JSONs) for vcd files generated from iverilog's simulator. Is there a specific format for the vcd files that vcd2json expects? Is there a way to get the same from iverilog? Are there other simulators that vcd2json supports part from cver?
Waveform (wavedrom) from JSON for vcd file from iverilog's simulation of timer.v
Waveform (wavedrom) from JSON for vcd file from cver simulation of timer.v
timer_iverilog.vcd
$date Mon Jan 5 23:03:22 2026 $end $version Icarus Verilog $end $timescale 1s $end $scope module tb_timer $end $var wire 1 ! pulse $end $var reg 1 " clock $end $var reg 1 # reset $end $scope module u_timer $end $var wire 1 " clock $end $var wire 1 # reset $end $var wire 1 $ count_eq11 $end $var reg 4 % count [3:0] $end $var reg 1 ! pulse $end $upscope $end $upscope $end $enddefinitions $end $comment Show the parameter values. $end $dumpall $end #0 $dumpvars bx % x$ 0# 0" x! $end #10 1" #20 0" #30 1" #40 0" #50 1" #60 0" #70 1" #80 0" #90 1# 1" #100 0" #110 0$ b0 % 1" #120 0" #130 0! 1" #140 0" #150 1" #160 0" #170 1" #180 0" #190 0# 1" #200 0" #210 b1 % 1" #220 0" #230 b10 % 1" #240 0" #250 b11 % 1" #260 0" #270 b100 % 1" #280 0" #290 b101 % 1" #300 0" #310 b110 % 1" #320 0" #330 b111 % 1" #340 0" #350 b1000 % 1" #360 0" #370 b1001 % 1" #380 0" #390 b1010 % 1" #400 0" #410 1$ b1011 % 1" #420 0" #430 1! 0$ b0 % 1" #440 0" #450 b1 % 0! 1" #460 0" #470 b10 % 1" #480 0" #490 b11 % 1" #500 0" #510 b100 % 1" #520 0" #530 b101 % 1" #540 0" #550 b110 % 1" #560 0" #570 b111 % 1" #580 0" #590 b1000 % 1" #600 0" #610 b1001 % 1" #620 0" #630 b1010 % 1" #640 0" #650 1$ b1011 % 1" #660 0" #670 1! 0$ b0 % 1" #680 0" #690 b1 % 0! 1" #700 0" #710 b10 % 1" #720 0" #730 b11 % 1" #740 0" #750 b100 % 1" #760 0" #770 b101 % 1" #780 0" #790 b110 % 1" #800 0" #810 b111 % 1" #820 0" #830 b1000 % 1" #840 0" #850 b1001 % 1" #860 0" #870 b1010 % 1" #880 0" #890 1$ b1011 % 1" #900 0" #910 1! 0$ b0 % 1" #920 0" #930 b1 % 0! 1" #940 0" #950 b10 % 1" #960 0" #970 b11 % 1" #980 0" #990 b100 % 1" #1000 0"timer_cver.vcd
$date Tue Jan 6 11:21:31 2026 $end $version GPLCVER_2.12a of 05/16/07 $end $timescale 1 ns $end $scope module tb_timer $end $var reg 1 ! clock $end $var wire 1 " pulse $end $var reg 1 # reset $end $scope module u_timer $end $var wire 1 $ clock $end $var reg 4 % count [3:0] $end $var wire 1 & count_eq11 $end $var reg 1 ' pulse $end $var wire 1 ( reset $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars 0$ bx % x& x' 0( 0! x" 0# $end #10 1" 0& 1' b1111 % 1$ 1! #20 0$ 0! #30 0" 0' b0 % 1$ 1! #40 0$ 0! #50 b1 % 1$ 1! #60 0$ 0! #70 b10 % 1$ 1! #80 0$ 0! #90 1( b11 % 1# 1$ 1! #100 0$ 0! #110 b0 % 1$ 1! #120 0$ 0! #130 1$ 1! #140 0$ 0! #150 1$ 1! #160 0$ 0! #170 1$ 1! #180 0$ 0! #190 0( 0# 1$ 1! #200 0$ 0! #210 b1 % 1$ 1! #220 0$ 0! #230 b10 % 1$ 1! #240 0$ 0! #250 b11 % 1$ 1! #260 0$ 0! #270 b100 % 1$ 1! #280 0$ 0! #290 b101 % 1$ 1! #300 0$ 0! #310 b110 % 1$ 1! #320 0$ 0! #330 b111 % 1$ 1! #340 0$ 0! #350 b1000 % 1$ 1! #360 0$ 0! #370 b1001 % 1$ 1! #380 0$ 0! #390 b1010 % 1$ 1! #400 0$ 0! #410 1& b1011 % 1$ 1! #420 0$ 0! #430 1" 0& 1' b0 % 1$ 1! #440 0$ 0! #450 0" 0' b1 % 1$ 1! #460 0$ 0! #470 b10 % 1$ 1! #480 0$ 0! #490 b11 % 1$ 1! #500 0$ 0! #510 b100 % 1$ 1! #520 0$ 0! #530 b101 % 1$ 1! #540 0$ 0! #550 b110 % 1$ 1! #560 0$ 0! #570 b111 % 1$ 1! #580 0$ 0! #590 b1000 % 1$ 1! #600 0$ 0! #610 b1001 % 1$ 1! #620 0$ 0! #630 b1010 % 1$ 1! #640 0$ 0! #650 1& b1011 % 1$ 1! #660 0$ 0! #670 1" 0& 1' b0 % 1$ 1! #680 0$ 0! #690 0" 0' b1 % 1$ 1! #700 0$ 0! #710 b10 % 1$ 1! #720 0$ 0! #730 b11 % 1$ 1! #740 0$ 0! #750 b100 % 1$ 1! #760 0$ 0! #770 b101 % 1$ 1! #780 0$ 0! #790 b110 % 1$ 1! #800 0$ 0! #810 b111 % 1$ 1! #820 0$ 0! #830 b1000 % 1$ 1! #840 0$ 0! #850 b1001 % 1$ 1! #860 0$ 0! #870 b1010 % 1$ 1! #880 0$ 0! #890 1& b1011 % 1$ 1! #900 0$ 0! #910 1" 0& 1' b0 % 1$ 1! #920 0$ 0! #930 0" 0' b1 % 1$ 1! #940 0$ 0! #950 b10 % 1$ 1! #960 0$ 0! #970 b11 % 1$ 1! #980 0$ 0! #990 b100 % 1$ 1! #1000