Crash catcher doesn't work on STM32H723 devices. After resetting the controller no dump is found in RAM. I could verify with a debugger that the last writes to RAM look fine before calling NVIC_SystemReset() but appear corrupted afterwards. Thus, the magic word isn't correct and the dump isn't detected. This problem occurs even if D-Cache is disabled, but a D-Cache flush after the dump is also missing in the implementation.
Apparently this issue is caused by the RAM ECC function. The SRAM controller implements a cache to speed up ECC calculation. AXI SRAMs in the H7 are organized in 64 bit words plus 8 ECC bits. For any smaller or unaligned access the write is cached to not having to perform a read-modify-write operation to update the ECC bits. If the CPU is reset before the whole word has been written to SRAM the cached data is lost.
The following FAQ entry in the ST forum describes the issue and a work around:
https://community.st.com/t5/stm32-mcus/faq-stm32-sram-backup-sram-content-is-not-preserved-after-reset/ta-p/861433
There is no explicit way to flush that ECC cache. ST recommends to read and write back the whole RAM in aligned words to make sure all data has been stored to the SRAM.
Furthermore, the modm implementation is missing handling for the regular data cache.
Crash catcher doesn't work on STM32H723 devices. After resetting the controller no dump is found in RAM. I could verify with a debugger that the last writes to RAM look fine before calling
NVIC_SystemReset()but appear corrupted afterwards. Thus, the magic word isn't correct and the dump isn't detected. This problem occurs even if D-Cache is disabled, but a D-Cache flush after the dump is also missing in the implementation.Apparently this issue is caused by the RAM ECC function. The SRAM controller implements a cache to speed up ECC calculation. AXI SRAMs in the H7 are organized in 64 bit words plus 8 ECC bits. For any smaller or unaligned access the write is cached to not having to perform a read-modify-write operation to update the ECC bits. If the CPU is reset before the whole word has been written to SRAM the cached data is lost.
The following FAQ entry in the ST forum describes the issue and a work around:
https://community.st.com/t5/stm32-mcus/faq-stm32-sram-backup-sram-content-is-not-preserved-after-reset/ta-p/861433
There is no explicit way to flush that ECC cache. ST recommends to read and write back the whole RAM in aligned words to make sure all data has been stored to the SRAM.
Furthermore, the modm implementation is missing handling for the regular data cache.