BRAM Improvement to osd.v

[avlixa]

Hi,

I had problems because of too much LUTs use in module org.v with ZXTRES fpga (xilinx A35T) and I could reduce more than 6000 LUTs by changing the way the osd buffer is used so it could infers a BRAM instead of using regs.

I don't know if this behaviour can be improved in others fpgas, you can take a look in
osd.v

Regards,
Antonio.

[gyurco]

Previously address was registered and output was not. Now you flipped the case. Altera FPGAs could handle both, however maybe the best would be to register both address and output.

[avlixa]

The problem with Xilinx is that cannot use BRAM if read and write operations are one synchronous and the other asynchronous. That's why I registered the output. I first try registering both of them but cause a delay in the output signal and the rotated menu is not displayed properly. So I deregistered address to avoid it.

[gyurco]

Of course registering both would require some logic change, too.

[dhadhireddy-gnaneshwar]

i have faced the some of my old projects best solution is to design a buffer externally in such a way that it will use bram. then instantiate that module in the design.