aead: restore s390x fixslice AES test gate and migrate ChaCha20/Poly1305 AVX2/AVX-512 kernels to as_chunks

auth: gate ed25519 AVX2/IFMA point tests behind the ed25519 feature and migrate point chunking to as_chunks
clippy: document missing # Safety on ct-binsec-harness AVX2/IFMA entrypoints

Restoring strict cross-target and feature-matrix validation surfaced four
latent CI failures: s390x test builds referenced the fixslice AES module
after it was excluded from s390x test cfg, x25519-only builds pulled in
ed25519-gated point_avx2 tests that were never feature-gated, and the new
clippy::chunks_exact_to_as_chunks lint plus missing_safety_doc caught real
gaps in the ChaCha20/Poly1305/Ed25519 SIMD kernels and the CT harness.

Author: loadingalias

src/aead/aes.rs

@@ -5766,6 +5766,7 @@ mod tests {
   }
 
   /// FIPS 197 Appendix C.1 against the table-free fixslice AES-128 path.
+  #[cfg(not(target_arch = "s390x"))]
   #[test]
   fn riscv64_fixslice_matches_nist_aes128_vector() {
     let key: [u8; 16] = [
@@ -5784,6 +5785,7 @@ mod tests {
     assert_eq!(block, expected);
   }
 
+  #[cfg(not(target_arch = "s390x"))]
   #[test]
   fn riscv64_fixslice_128_4blocks_matches_portable() {
     let key = [0xC4u8; KEY_SIZE_128];
@@ -5806,6 +5808,7 @@ mod tests {
     assert_eq!(blocks, expected);
   }
 
+  #[cfg(not(target_arch = "s390x"))]
   #[test]
   fn riscv64_fixslice_matches_nist_aes256_vector() {
     let key: [u8; 32] = [
@@ -5825,6 +5828,7 @@ mod tests {
     assert_eq!(block, expected);
   }
 
+  #[cfg(not(target_arch = "s390x"))]
   #[test]
   fn riscv64_fixslice_4blocks_matches_portable() {
     let key = [0x3cu8; KEY_SIZE];

src/aead/chacha20/x86_64_avx2.rs

@@ -44,8 +44,8 @@ unsafe fn xor_keystream_impl(key: &[u8; KEY_SIZE], initial_counter: u32, nonce:
   );
 
   let mut counter = initial_counter;
-  let mut batches = buffer.chunks_exact_mut(BLOCK_SIZE * BLOCKS_PER_BATCH);
-  for chunk in &mut batches {
+  let (batches, remainder) = buffer.as_chunks_mut::<{ BLOCK_SIZE * BLOCKS_PER_BATCH }>();
+  for chunk in batches {
     debug_assert!(counter.checked_add(COUNTERS_PER_BATCH.strict_sub(1)).is_some());
 
     let mut x0 = _mm256_set1_epi32(0x6170_7865u32.cast_signed());
@@ -183,16 +183,14 @@ unsafe fn xor_keystream_impl(key: &[u8; KEY_SIZE], initial_counter: u32, nonce:
     counter = counter.wrapping_add(COUNTERS_PER_BATCH);
   }
 
-  let remainder = batches.into_remainder();
-  let mut x4_batches = remainder.chunks_exact_mut(BLOCK_SIZE * x86_ssse3_x4::BLOCKS_PER_BATCH);
-  for chunk in &mut x4_batches {
+  let (x4_batches, remainder) = remainder.as_chunks_mut::<{ BLOCK_SIZE * x86_ssse3_x4::BLOCKS_PER_BATCH }>();
+  for chunk in x4_batches {
     // SAFETY: AVX2-capable CPUs provide the SSSE3 instructions used by the
     // 4-block tail kernel, and `chunk` is exactly 4 ChaCha20 blocks.
     unsafe { x86_ssse3_x4::xor_blocks(key, counter, nonce, chunk) };
     counter = counter.wrapping_add(x86_ssse3_x4::COUNTERS_PER_BATCH);
   }
 
-  let remainder = x4_batches.into_remainder();
   if !remainder.is_empty() {
     xor_keystream_portable(key, counter, nonce, remainder);
   }

src/aead/chacha20/x86_64_avx512.rs

@@ -36,8 +36,8 @@ pub(super) unsafe fn xor_keystream(
 #[target_feature(enable = "avx512f,avx512vl,avx512bw,avx512dq")]
 unsafe fn xor_keystream_impl(key: &[u8; KEY_SIZE], initial_counter: u32, nonce: &[u8; NONCE_SIZE], buffer: &mut [u8]) {
   let mut counter = initial_counter;
-  let mut batches = buffer.chunks_exact_mut(BLOCK_SIZE * BLOCKS_PER_BATCH);
-  for chunk in &mut batches {
+  let (batches, remainder) = buffer.as_chunks_mut::<{ BLOCK_SIZE * BLOCKS_PER_BATCH }>();
+  for chunk in batches {
     debug_assert!(counter.checked_add(COUNTERS_PER_BATCH.strict_sub(1)).is_some());
 
     let mut x0 = _mm512_set1_epi32(0x6170_7865u32.cast_signed());
@@ -236,16 +236,14 @@ unsafe fn xor_keystream_impl(key: &[u8; KEY_SIZE], initial_counter: u32, nonce:
     counter = counter.wrapping_add(COUNTERS_PER_BATCH);
   }
 
-  let remainder = batches.into_remainder();
-  let mut x4_batches = remainder.chunks_exact_mut(BLOCK_SIZE * x86_ssse3_x4::BLOCKS_PER_BATCH);
-  for chunk in &mut x4_batches {
+  let (x4_batches, remainder) = remainder.as_chunks_mut::<{ BLOCK_SIZE * x86_ssse3_x4::BLOCKS_PER_BATCH }>();
+  for chunk in x4_batches {
     // SAFETY: AVX-512-ready CPUs provide the SSSE3 instructions used by the
     // 4-block tail kernel, and `chunk` is exactly 4 ChaCha20 blocks.
     unsafe { x86_ssse3_x4::xor_blocks(key, counter, nonce, chunk) };
     counter = counter.wrapping_add(x86_ssse3_x4::COUNTERS_PER_BATCH);
   }
 
-  let remainder = x4_batches.into_remainder();
   if !remainder.is_empty() {
     xor_keystream_portable(key, counter, nonce, remainder);
   }

src/aead/poly1305/x86_64_avx2_par4.rs

@@ -703,15 +703,12 @@ pub(super) unsafe fn authenticate_aead_par4(
 
   // Reimplements padded-segment logic from `update_padded_segment` for 4-way batching.
   for segment in [aad, ciphertext] {
-    let mut chunks = segment.chunks_exact(16);
-    for chunk in &mut chunks {
-      let mut block = [0u8; 16];
-      block.copy_from_slice(chunk);
+    let (chunks, rem) = segment.as_chunks::<16>();
+    for chunk in chunks {
       // SAFETY: the caller guarantees AVX2. The loop produces consecutive full blocks; `push_block` preserves
       // `num_cached < 4` and keeps the cache, powers, and accumulator in the same key stream.
-      num_cached = unsafe { push_block(block, &mut cached, num_cached, &mut acc, r1, r2) };
+      num_cached = unsafe { push_block(*chunk, &mut cached, num_cached, &mut acc, r1, r2) };
     }
-    let rem = chunks.remainder();
     if !rem.is_empty() {
       let mut block = [0u8; 16];
       block[..rem.len()].copy_from_slice(rem);

src/auth/ed25519/point_avx2.rs

@@ -490,7 +490,7 @@ pub unsafe fn diag_select_basepoint_cached_avx2_limb_digest(digit: i8) -> [u64;
   let selected = select_signed_cached_avx2(&BASEPOINT_RADIX16_TABLE[0], digit, &affine_k, &identity);
   let fields = selected.0.split();
   let mut out = [0u64; 20];
-  for (chunk, field) in out.chunks_exact_mut(5).zip(fields.iter()) {
+  for (chunk, field) in out.as_chunks_mut::<5>().0.iter_mut().zip(fields.iter()) {
     chunk.copy_from_slice(field.limbs());
   }
   out
@@ -914,7 +914,7 @@ pub unsafe fn diag_select_basepoint_cached_ifma_limb_digest(digit: i8) -> [u64;
   let selected = select_signed_cached_ifma(&BASEPOINT_RADIX16_TABLE[0], digit, &affine_k, &identity);
   let fields = selected.0.split();
   let mut out = [0u64; 20];
-  for (chunk, field) in out.chunks_exact_mut(5).zip(fields.iter()) {
+  for (chunk, field) in out.as_chunks_mut::<5>().0.iter_mut().zip(fields.iter()) {
     chunk.copy_from_slice(field.limbs());
   }
   out
@@ -1085,6 +1085,7 @@ pub(crate) unsafe fn straus_wnaf_vartime_ifma(s: &[u8; 32], h: &[u8; 32], a: &Ex
 
 #[cfg(test)]
 #[cfg(target_arch = "x86_64")]
+#[cfg(feature = "ed25519")]
 mod tests {
   use super::{ExtendedPoint, *};
 
@@ -1320,7 +1321,6 @@ mod tests {
     }
   }
 
-  #[cfg(feature = "ed25519")]
   #[test]
   fn scalar_mul_basepoint_rfc8032_vector1() {
     if !std::arch::is_x86_feature_detected!("avx2") {
@@ -1345,7 +1345,6 @@ mod tests {
     }
   }
 
-  #[cfg(feature = "ed25519")]
   #[test]
   fn straus_matches_scalar() {
     if !std::arch::is_x86_feature_detected!("avx2") {
@@ -1371,7 +1370,6 @@ mod tests {
     }
   }
 
-  #[cfg(feature = "ed25519")]
   #[test]
   fn straus_matches_scalar_large_scalars() {
     if !std::arch::is_x86_feature_detected!("avx2") {

tools/ct-binsec-harness/src/main.rs

@@ -885,6 +885,9 @@ pub extern "C" fn ct_binsec_rsa_private_component_validation_32() -> ! {
 #[unsafe(no_mangle)]
 #[inline(never)]
 #[target_feature(enable = "avx2")]
+/// # Safety
+///
+/// The caller must ensure AVX2 is available before invoking this entrypoint.
 pub unsafe extern "C" fn ct_binsec_ed25519_select_basepoint_cached_avx2() -> ! {
   // SAFETY: This pointer references a fixed harness global with static storage.
   let digit = unsafe { ptr::read_volatile(ptr::addr_of!(CT_BINSEC_ED25519_DIGIT)) };
@@ -905,6 +908,10 @@ pub unsafe extern "C" fn ct_binsec_ed25519_select_basepoint_cached_avx2() -> ! {
 #[unsafe(no_mangle)]
 #[inline(never)]
 #[target_feature(enable = "avx2,avx512ifma,avx512vl")]
+/// # Safety
+///
+/// The caller must ensure AVX2, AVX-512 IFMA, and AVX-512 VL are available
+/// before invoking this entrypoint.
 pub unsafe extern "C" fn ct_binsec_ed25519_select_basepoint_cached_ifma() -> ! {
   // SAFETY: This pointer references a fixed harness global with static storage.
   let digit = unsafe { ptr::read_volatile(ptr::addr_of!(CT_BINSEC_ED25519_DIGIT)) };