device.yml

%YAML 1.1
---
# yaml-language-server: $schema=https://harp-tech.org/draft-02/schema/device.json
device: MultiPwm
whoAmI: 1040
firmwareVersion: "1.2"
hardwareTargets: "1.1"
registers:
  PwmChannel0Frequency: &pwmfreq
    address: 32
    type: Float
    access: Write
    description: Frequency (Hz) of PWM pulses in channel 0.
  PwmChannel1Frequency:
    <<: *pwmfreq
    address: 33
    description: Frequency (Hz) of PWM pulses in channel 1.
  PwmChannel2Frequency:
    <<: *pwmfreq
    address: 34
    description: Frequency (Hz) of PWM pulses in channel 2.
  PwmChannel3Frequency:
    <<: *pwmfreq
    address: 35
    description: Frequency (Hz) of PWM pulses in channel 3.
  PwmChannel0DutyCycle: &pwmduty
    address: 36
    minValue: 0.1
    maxValue: 99.9
    defaultValue: 50
    type: Float
    access: Write
    description: Duty cycle (0-100) of PWM pulses in channel 0.
  PwmChannel1DutyCycle:
    <<: *pwmduty
    address: 37
    description: Duty cycle (0-100) of PWM pulses in channel 1.
  PwmChannel2DutyCycle:
    <<: *pwmduty
    address: 38
    description: Duty cycle (0-100) of PWM pulses in channel 2.
  PwmChannel3DutyCycle:
    <<: *pwmduty
    address: 39
    description: Duty cycle (0-100) of PWM pulses in channel 3.
  PwmChannel0PulseCount: &pwmnum
    address: 40
    type: U32
    access: Write
    description: Total number of pulses to be generated in channel 0.
  PwmChannel1PulseCount:
    <<: *pwmnum
    address: 41
    description: Total number of pulses to be generated in channel 1.
  PwmChannel2PulseCount:
    <<: *pwmnum
    address: 42
    description: Total number of pulses to be generated in channel 2.
  PwmChannel3PulseCount:
    <<: *pwmnum
    address: 43
    description: Total number of pulses to be generated in channel 3.
  PwmChannel0RealFrequency: &pwmfreqreal
    address: 44
    type: Float
    access: Write
    description: Real frequency (Hz) of PWM pulses in channel 0.
  PwmChannel1RealFrequency:
    <<: *pwmfreqreal
    address: 45
    description: Real frequency (Hz) of PWM pulses in channel 1.
  PwmChannel2RealFrequency:
    <<: *pwmfreqreal
    address: 46
    description: Real frequency (Hz) of PWM pulses in channel 2.
  PwmChannel3RealFrequency:
    <<: *pwmfreqreal
    address: 47
    description: Real frequency (Hz) of PWM pulses in channel 3.
  PwmChannel0RealDutyCycle: &pwmdutyreal
    address: 48
    type: Float
    access: Read
    description: Real duty cycle (0-100) of PWM pulses in channel 0.
  PwmChannel1RealDutyCycle:
    <<: *pwmdutyreal
    address: 49
    description: Real duty cycle (0-100) of PWM pulses in channel 1.
  PwmChannel2RealDutyCycle:
    <<: *pwmdutyreal
    address: 50
    description: Real duty cycle (0-100) of PWM pulses in channel 2.
  PwmChannel3RealDutyCycle:
    <<: *pwmdutyreal
    address: 51
    description: Real duty cycle (0-100) of PWM pulses in channel 3.
  PwmChannel0PlaybackMode: &pwmplayback
    address: 52
    type: U8
    access: Write
    maskType: PlaybackMode
    description: Playback mode of channel 0.
  PwmChannel1PlaybackMode:
    <<: *pwmplayback
    address: 53
    description: Playback mode of channel 1.
  PwmChannel2PlaybackMode:
    <<: *pwmplayback
    address: 54
    description: Playback mode of channel 2.
  PwmChannel3PlaybackMode:
    <<: *pwmplayback
    address: 55
    description: Playback mode of channel 3.
  Trigger0Targets: &pwmtrigger
    address: 56
    type: U8
    access: Write
    maskType: PwmChannels
    description: Target channels that will start the PWM sequence if Trigger0 is activated.
  Trigger1Targets:
    <<: *pwmtrigger
    address: 57
    description: Target channels that will start the PWM sequence if Trigger1 is activated.
  Trigger2Targets:
    <<: *pwmtrigger
    address: 58
    description: Target channels that will start the PWM sequence if Trigger2 is activated.
  Trigger3Targets:
    <<: *pwmtrigger
    address: 59
    description: Target channels that will start the PWM sequence if Trigger3 is activated.
  StartSoftwareTrigger: &softtrigger
    address: 60
    type: U8
    access: Write
    maskType: TriggerInputs
    description: Emits a start software-trigger on the channels specified in the mask.
  StopSoftwareTrigger:
    <<: *softtrigger
    address: 61
    maskType: TriggerInputs
    description: Emits a stop software-trigger on the channels specified in the mask.
  ArmPwmChannels:
    address: 62
    type: U8
    access: Write
    maskType: PwmChannels
    description: Arms the PWM channels specified in the mask. Once a PWM is triggered, it must be rearmed.
  Reserved0: &reserved
    address: 63
    type: U8
    access: Read
    visibility: private
    description: Reserved for future use.
  Trigger0Mode: &triggermode
    address: 64
    type: U8
    access: Write
    payloadSpec:
      TriggerMode:
        maskType: TriggerModeConfig
        description: Specifies the trigger mode.
        mask: 0x03
      Polarity:
        maskType: TriggerPolarity
        description: Specifies the polarity of the trigger signal.
        mask: 0x10
    description: Trigger mode of input channel 0.
  Trigger1Mode:
    <<: *triggermode
    address: 65
    description: Trigger mode of input channel 1.
  Trigger2Mode:
    <<: *triggermode
    address: 66
    description: Trigger mode of input channel 2.
  Trigger3Mode:
    <<: *triggermode
    address: 67
    description: Trigger mode of input channel 3.
  RequestEnable:
    address: 68
    type: U8
    access: Write
    maskType: PwmChannels
    description: If set to Low, it will bypass the EnablePwmChannels and ArmPwmChannels register function.
  EnablePwmChannels:
    address: 69
    type: U8
    access: Write
    maskType: PwmChannels
    description: Enable enable
  TriggerAllMode:
    address: 70
    type: U8
    access: Write
    payloadSpec:
      TriggerMode:
        maskType: TriggerAllModeConfig
        description: Specifies the trigger mode.
        mask: 0x03
      Polarity:
        maskType: TriggerPolarity
        description: Specifies the polarity of the trigger signal.
        mask: 0x10
    description: When triggered, all channels will be affected by the event.
  TriggerChannelState:
    address: 71
    type: U8
    access: Read
    maskType: TriggerInputs
    description: Current state of all trigger channel inputs.
  PwmChannelState:
    address: 72
    type: U8
    access: Read
    maskType: PwmChannels
    description: Current state of all PWM channel outputs.
  PwmState:
    address: 73
    type: U8
    access: Event
    maskType: PwmChannels
    description: The state of the PWM for each channel. Emits an event each time a PMW starts or stops.
  EnableEvents:
    address: 74
    type: U8
    access: Write
    maskType: MultiPwmEvents
    description: Enables the generation of events.
bitMasks:
  PwmChannels:
    description: Available PWM output channels.
    bits:
      Channel0: 0x01
      Channel1: 0x02
      Channel2: 0x04
      Channel3: 0x08
  TriggerInputs:
    description: Available trigger input channels.
    bits:
      Channel0: 0x01
      Channel1: 0x02
      Channel2: 0x04
      Channel3: 0x08
  MultiPwmEvents:
    description: Available events that can be enabled/disabled.
    bits:
      Execution: 0x01
groupMasks:
  PlaybackMode:
    description: Available playback modes of the PWM channel.
    values:
      Count: 0
      Infinite: 1
  TriggerModeConfig:
    description: Available operation modes for trigger input channels.
    values:
      Start: 0
      StartAndStop: 1
  TriggerPolarity:
    description: Available polarity options for a trigger mode.
    values:
      Default: 0
      Inverted: 8
  TriggerAllModeConfig:
    description: Available operation modes for "All" trigger input channel.
    values:
      Start: 0
      StartAndStop: 1
      Enable: 2
      EnableAndStop: 3