diff --git a/go.mod b/go.mod
index 14749b391f4..f2f4139ca5d 100644
--- a/go.mod
+++ b/go.mod
@@ -259,7 +259,7 @@ require (
 	github.com/json-iterator/go v1.1.12 // indirect
 	github.com/julienschmidt/httprouter v1.3.0 // indirect
 	github.com/kamstrup/intmap v0.5.2 // indirect
-	github.com/klauspost/cpuid/v2 v2.3.0 // indirect
+	github.com/klauspost/cpuid/v2 v2.4.0 // indirect
 	github.com/klauspost/crc32 v1.3.0 // indirect
 	github.com/knadh/koanf/maps v0.1.2 // indirect
 	github.com/knadh/koanf/providers/confmap v1.0.0 // indirect
diff --git a/go.sum b/go.sum
index 3425ad557ef..a38a92e266a 100644
--- a/go.sum
+++ b/go.sum
@@ -493,8 +493,8 @@ github.com/klauspost/compress v1.15.9/go.mod h1:PhcZ0MbTNciWF3rruxRgKxI5NkcHHrHU
 github.com/klauspost/compress v1.19.1 h1:VsB4HPswih7mmZ8WleSFQ75c/Ui1M4trX5oAsJnhSlk=
 github.com/klauspost/compress v1.19.1/go.mod h1:cwPg85FWrGar70rWktvGQj8/hthj3wpl0PGDogxkrSQ=
 github.com/klauspost/cpuid/v2 v2.0.1/go.mod h1:FInQzS24/EEf25PyTYn52gqo7WaD8xa0213Md/qVLRg=
-github.com/klauspost/cpuid/v2 v2.3.0 h1:S4CRMLnYUhGeDFDqkGriYKdfoFlDnMtqTiI/sFzhA9Y=
-github.com/klauspost/cpuid/v2 v2.3.0/go.mod h1:hqwkgyIinND0mEev00jJYCxPNVRVXFQeu1XKlok6oO0=
+github.com/klauspost/cpuid/v2 v2.4.0 h1:S6Hrbc7+ywsr0r+RLapfGBHfyefhCTwEh3A0tV913Dw=
+github.com/klauspost/cpuid/v2 v2.4.0/go.mod h1:19jmZ9mjzoF//ddRSUsv0zfBTJWh3QJh9FNxZTMrGxU=
 github.com/klauspost/crc32 v1.3.0 h1:sSmTt3gUt81RP655XGZPElI0PelVTZ6YwCRnPSupoFM=
 github.com/klauspost/crc32 v1.3.0/go.mod h1:D7kQaZhnkX/Y0tstFGf8VUzv2UofNGqCjnC3zdHB0Hw=
 github.com/knadh/koanf/maps v0.1.2 h1:RBfmAW5CnZT+PJ1CVc1QSJKf4Xu9kxfQgYVQSu8hpbo=
diff --git a/vendor/github.com/klauspost/cpuid/v2/.goreleaser.yml b/vendor/github.com/klauspost/cpuid/v2/.goreleaser.yml
index 1b695b62c35..14712fe0dda 100644
--- a/vendor/github.com/klauspost/cpuid/v2/.goreleaser.yml
+++ b/vendor/github.com/klauspost/cpuid/v2/.goreleaser.yml
@@ -29,7 +29,7 @@ archives:
     name_template: "cpuid-{{ .Os }}_{{ .Arch }}{{ if .Arm }}v{{ .Arm }}{{ end }}"
     format_overrides:
       - goos: windows
-        format: zip
+        formats: [ 'zip' ]
     files:
       - LICENSE
 checksum:
diff --git a/vendor/github.com/klauspost/cpuid/v2/README.md b/vendor/github.com/klauspost/cpuid/v2/README.md
index 88d68d5286f..a99bbdba361 100644
--- a/vendor/github.com/klauspost/cpuid/v2/README.md
+++ b/vendor/github.com/klauspost/cpuid/v2/README.md
@@ -2,7 +2,7 @@
 Package cpuid provides information about the CPU running the current program.
 
 CPU features are detected on startup, and kept for fast access through the life of the application.
-Currently x86 / x64 (AMD64/i386) and ARM (ARM64) is supported, and no external C (cgo) code is used, which should make the library very easy to use.
+Currently x86 / x64 (AMD64/i386), ARM (ARM64), and RISC-V (RV64) are supported, and no external C (cgo) code is used, which should make the library very easy to use.
 
 You can access the CPU information by accessing the shared CPU variable of the cpuid library.
 
@@ -506,6 +506,74 @@ Exit Code 1
 | SM3          | SM3 instructions                                                 |
 | SM4          | SM4 instructions                                                 |
 | SVE          | Scalable Vector Extension                                        |
+| SVE2         | Scalable Vector Extension 2                                      |
+| SB           | Speculation barrier (SB instruction)                             |
+| SSBS         | Speculative Store Bypass Safe (PSTATE.SSBS)                      |
+| BTI          | Branch Target Identification                                     |
+| FLAGM2       | Condition flag manipulation version 2 (AXFLAG, XAFLAG)           |
+| FRINTTS      | Floating-point to integer rounding (FRINT32Z, FRINT64Z, etc)     |
+| DCPODP       | Data cache clean to Point of Deep Persistence (DC CVADP)         |
+| BF16         | BFloat16 instructions (BFDOT, BFMMLA, etc)                       |
+| I8MM         | Int8 matrix multiplication (SMMLA, UMMLA, USMMLA)                |
+| WFXT         | WFE/WFI with timeout (WFET, WFIT)                                |
+| MOPS         | Memory copy and set instructions (CPYF, SETP, etc)               |
+| HBC          | Hinted conditional branches (BC.cond)                            |
+| CSSC         | Common short sequence compression (ABS, SMAX, UMAX, etc)         |
+
+## riscv64 feature detection
+
+On `riscv64/linux`, CPU features are detected using the `riscv_hwprobe` syscall (Linux 6.4+).
+For older kernels, detection falls back to parsing `/proc/cpuinfo` for the ISA string.
+
+Cache line size is detected via `riscv_hwprobe` (Zicbom block size) or sysfs fallback.
+Other cache and topology information is not yet available.
+
+# RISC-V features:
+
+| Feature Flag   | Description                                        |
+|----------------|----------------------------------------------------|
+| RV_IMA         | IMA base (Integer, Multiply, Atomic)               |
+| RV_C           | Compressed instructions                            |
+| RV_F           | Single-precision FP                                |
+| RV_D           | Double-precision FP                                |
+| RV_V           | Vector extension (V)                               |
+| RV_ZBA         | Address generation                                 |
+| RV_ZBB         | Basic bit manipulation                             |
+| RV_ZBC         | Carry-less multiplication                          |
+| RV_ZBS         | Single-bit manipulation                            |
+| RV_ZICOND      | Integer conditional operations                     |
+| RV_ZIHINTPAUSE | Pause hint                                         |
+| RV_ZICBOM      | Cache block management operations                  |
+| RV_ZICBOZ      | Cache block zero                                   |
+| RV_ZICBOP      | Cache block prefetch                               |
+| RV_ZFA         | Additional floating-point                          |
+| RV_ZFH         | Half-precision FP                                  |
+| RV_ZFHMIN      | Minimal half-precision FP                          |
+| RV_ZTSO        | Total store ordering                               |
+| RV_ZACAS       | Atomic CAS                                         |
+| RV_ZBKB        | Bit-manipulation for crypto                        |
+| RV_ZBKC        | Carry-less multiply for crypto                     |
+| RV_ZBKX        | Crossbar permutations                              |
+| RV_ZKND        | NIST Suite: AES decrypt                            |
+| RV_ZKNE        | NIST Suite: AES encrypt                            |
+| RV_ZKNH        | NIST Suite: SHA-2 (SHA-256/SHA-512)                |
+| RV_ZKSED       | ShangMi Suite: SM4 block cipher                    |
+| RV_ZKSH        | ShangMi Suite: SM3 hash                            |
+| RV_ZKT         | Data-independent execution latency (Crypto)        |
+| RV_ZKN         | NIST Algorithm Suite (combined from individual)    |
+| RV_ZKS         | ShangMi Algorithm Suite (combined from individual) |
+| RV_ZVBB        | Vector Basic Bit-manipulation                      |
+| RV_ZVBC        | Vector Carry-less multiply                         |
+| RV_ZVKB        | Vector Bit-manipulation for crypto                 |
+| RV_ZVKG        | Vector GCM/GMAC                                    |
+| RV_ZVKNED      | NIST Suite: Vector AES encrypt+decrypt             |
+| RV_ZVKNHA      | NIST Suite: Vector SHA-2 (SHA-256)                 |
+| RV_ZVKNHB      | NIST Suite: Vector SHA-2 (SHA-512)                 |
+| RV_ZVKSED      | ShangMi Suite: Vector SM4                          |
+| RV_ZVKSH       | ShangMi Suite: Vector SM3 hash                     |
+| RV_ZVKT        | Vector Data-independent execution latency          |
+| RV_ZVKNG       | NIST Suite with GCM (combined from individual)     |
+| RV_ZVKSG       | ShangMi Suite with GCM (combined from individual)  |
 
 # license
 
diff --git a/vendor/github.com/klauspost/cpuid/v2/cpuid.go b/vendor/github.com/klauspost/cpuid/v2/cpuid.go
index 9cf7738a975..db903f46a47 100644
--- a/vendor/github.com/klauspost/cpuid/v2/cpuid.go
+++ b/vendor/github.com/klauspost/cpuid/v2/cpuid.go
@@ -3,7 +3,7 @@
 // Package cpuid provides information about the CPU running the current program.
 //
 // CPU features are detected on startup, and kept for fast access through the life of the application.
-// Currently x86 / x64 (AMD64) as well as arm64 is supported.
+// Currently x86 / x64 (AMD64), arm64, and riscv64 are supported.
 //
 // You can access the CPU information by accessing the shared CPU variable of the cpuid library.
 //
@@ -17,6 +17,7 @@ import (
 	"math/bits"
 	"os"
 	"runtime"
+	"slices"
 	"strings"
 )
 
@@ -61,6 +62,13 @@ const (
 	SRE
 	Apple
 
+	// RISC-V vendors
+	SiFive
+	StarFive
+	THead
+	Andes
+	SpacemiT
+
 	lastVendor
 )
 
@@ -95,6 +103,7 @@ const (
 	AVX2                                 // AVX2 functions
 	AVX512BF16                           // AVX-512 BFLOAT16 Instructions
 	AVX512BITALG                         // AVX-512 Bit Algorithms
+	AVX512BMM                            // AVX-512 Bit Manipulation Instructions
 	AVX512BW                             // AVX-512 Byte and Word Instructions
 	AVX512CD                             // AVX-512 Conflict Detection Instructions
 	AVX512DQ                             // AVX-512 Doubleword and Quadword Instructions
@@ -139,6 +148,7 @@ const (
 	FMA4                                 // Bulldozer FMA4 functions
 	FP128                                // AMD: When set, the internal FP/SIMD execution datapath is no more than 128-bits wide
 	FP256                                // AMD: When set, the internal FP/SIMD execution datapath is no more than 256-bits wide
+	FRED                                 // Flexible Return and Event Delivery
 	FSRM                                 // Fast Short Rep Mov
 	FXSR                                 // FXSAVE, FXRESTOR instructions, CR4 bit 9
 	FXSROPT                              // FXSAVE/FXRSTOR optimizations
@@ -308,6 +318,19 @@ const (
 	SM3      // SM3 instructions
 	SM4      // SM4 instructions
 	SVE      // Scalable Vector Extension
+	SVE2     // Scalable Vector Extension 2
+	SB       // Speculation barrier (SB instruction)
+	SSBS     // Speculative Store Bypass Safe (PSTATE.SSBS)
+	BTI      // Branch Target Identification
+	FLAGM2   // Condition flag manipulation version 2 (AXFLAG, XAFLAG)
+	FRINTTS  // Floating-point to integer rounding (FRINT32Z, FRINT64Z, etc)
+	DCPODP   // Data cache clean to Point of Deep Persistence (DC CVADP)
+	BF16     // BFloat16 instructions (BFDOT, BFMMLA, etc)
+	I8MM     // Int8 matrix multiplication (SMMLA, UMMLA, USMMLA)
+	WFXT     // WFE/WFI with timeout (WFET, WFIT)
+	MOPS     // Memory copy and set instructions (CPYF, SETP, etc)
+	HBC      // Hinted conditional branches (BC.cond)
+	CSSC     // Common short sequence compression (ABS, SMAX, UMAX, etc)
 
 	// PMU
 	PMU_FIXEDCOUNTER_CYCLES
@@ -315,6 +338,57 @@ const (
 	PMU_FIXEDCOUNTER_INSTRUCTIONS
 	PMU_FIXEDCOUNTER_TOPDOWN_SLOTS
 
+	// RISC-V features
+	RV_IMA         // IMA base (Integer, Multiply, Atomic)
+	RV_C           // Compressed instructions
+	RV_F           // Single-precision FP
+	RV_D           // Double-precision FP
+	RV_V           // Vector extension (V)
+	RV_ZBA         // Address generation
+	RV_ZBB         // Basic bit manipulation
+	RV_ZBC         // Carry-less multiplication
+	RV_ZBS         // Single-bit manipulation
+	RV_ZICOND      // Integer conditional operations
+	RV_ZIHINTPAUSE // Pause hint
+	RV_ZICBOM      // Cache block management operations
+	RV_ZICBOZ      // Cache block zero
+	RV_ZICBOP      // Cache block prefetch
+	RV_ZFA         // Additional floating-point
+	RV_ZFH         // Half-precision FP
+	RV_ZFHMIN      // Minimal half-precision FP
+	RV_ZTSO        // Total store ordering
+	RV_ZACAS       // Atomic CAS
+	// Scalar cryptography
+	RV_ZBKB  // Bit-manipulation for crypto
+	RV_ZBKC  // Carry-less multiply for crypto
+	RV_ZBKX  // Crossbar permutations
+	RV_ZKND  // NIST Suite: AES decrypt
+	RV_ZKNE  // NIST Suite: AES encrypt
+	RV_ZKNH  // NIST Suite: SHA-2 (SHA-256/SHA-512)
+	RV_ZKSED // ShangMi Suite: SM4 block cipher
+	RV_ZKSH  // ShangMi Suite: SM3 hash
+	RV_ZKT   // Data-independent execution latency (Crypto)
+
+	// Scalar crypto suites (combined from individual extensions)
+	RV_ZKN // NIST Algorithm Suite (Zknd+Zkne+Zknh+Zbkb+Zbkc+Zbkx+Zkt)
+	RV_ZKS // ShangMi Algorithm Suite (Zksed+Zksh+Zbkb+Zbkc+Zbkx+Zkt)
+
+	// Vector cryptography
+	RV_ZVBB   // Vector Basic Bit-manipulation
+	RV_ZVBC   // Vector Carry-less multiply
+	RV_ZVKB   // Vector Bit-manipulation for crypto
+	RV_ZVKG   // Vector GCM/GMAC
+	RV_ZVKNED // NIST Suite: Vector AES encrypt+decrypt
+	RV_ZVKNHA // NIST Suite: Vector SHA-2 (SHA-256)
+	RV_ZVKNHB // NIST Suite: Vector SHA-2 (SHA-512)
+	RV_ZVKSED // ShangMi Suite: Vector SM4
+	RV_ZVKSH  // ShangMi Suite: Vector SM3 hash
+	RV_ZVKT   // Vector Data-independent execution latency
+
+	// Vector crypto suites (combined from individual extensions)
+	RV_ZVKNG // NIST Suite with GCM (Zvkned+Zvknhb+Zvkg+Zvkb+Zvkt)
+	RV_ZVKSG // ShangMi Suite with GCM (Zvksed+Zvksh+Zvkg+Zvkb+Zvkt)
+
 	// Keep it last. It automatically defines the size of []flagSet
 	lastID
 
@@ -419,8 +493,8 @@ func Detect() {
 		os.Exit(1)
 	}
 	if disableFlag != nil {
-		s := strings.Split(*disableFlag, ",")
-		for _, feat := range s {
+		s := strings.SplitSeq(*disableFlag, ",")
+		for feat := range s {
 			feat := ParseFeature(strings.TrimSpace(feat))
 			if feat != UNKNOWN {
 				CPU.featureSet.unset(feat)
@@ -471,12 +545,7 @@ func (c *CPUInfo) Has(id FeatureID) bool {
 
 // AnyOf returns whether the CPU supports one or more of the requested features.
 func (c CPUInfo) AnyOf(ids ...FeatureID) bool {
-	for _, id := range ids {
-		if c.featureSet.inSet(id) {
-			return true
-		}
-	}
-	return false
+	return slices.ContainsFunc(ids, c.featureSet.inSet)
 }
 
 // Features contains several features combined for a fast check using
@@ -496,6 +565,11 @@ func (c *CPUInfo) HasAll(f Features) bool {
 	return c.featureSet.hasSetP(f)
 }
 
+// HasOneOf returns whether the CPU supports one or more of the requested features.
+func (c *CPUInfo) HasOneOf(f Features) bool {
+	return c.featureSet.hasOneOf(f)
+}
+
 // https://en.wikipedia.org/wiki/X86-64#Microarchitecture_levels
 var oneOfLevel = CombineFeatures(SYSEE, SYSCALL)
 var level1Features = CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SSE, SSE2)
@@ -503,6 +577,56 @@ var level2Features = CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SSE, SSE2,
 var level3Features = CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SSE, SSE2, CX16, LAHF, POPCNT, SSE3, SSE4, SSE42, SSSE3, AVX, AVX2, BMI1, BMI2, F16C, FMA3, LZCNT, MOVBE, OSXSAVE)
 var level4Features = CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SSE, SSE2, CX16, LAHF, POPCNT, SSE3, SSE4, SSE42, SSSE3, AVX, AVX2, BMI1, BMI2, F16C, FMA3, LZCNT, MOVBE, OSXSAVE, AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL)
 
+// RV_CRYPTO_FEATS contains all RISC-V scalar cryptography instruction extensions (excludes Zkt since it is a timing guarantee, not a computational instruction).
+var RV_CRYPTO_FEATS = CombineFeatures(RV_ZBKB, RV_ZBKC, RV_ZBKX, RV_ZKND, RV_ZKNE, RV_ZKNH, RV_ZKSED, RV_ZKSH)
+
+// RV_VECTOR_CRYPTO_FEATS contains all RISC-V vector cryptography extensions.
+var RV_VECTOR_CRYPTO_FEATS = CombineFeatures(RV_ZVBB, RV_ZVBC, RV_ZVKB, RV_ZVKG, RV_ZVKNED, RV_ZVKNHA, RV_ZVKNHB, RV_ZVKSED, RV_ZVKSH)
+
+// RISC-V application profile feature sets.
+// https://github.com/riscv/riscv-profiles
+var rvProfile20Features = CombineFeatures(RV_IMA, RV_C, RV_F, RV_D)
+var rvProfile22Features = CombineFeatures(RV_IMA, RV_C, RV_F, RV_D, RV_ZBA, RV_ZBB, RV_ZBS, RV_ZFHMIN, RV_ZICBOM, RV_ZICBOP, RV_ZICBOZ, RV_ZIHINTPAUSE)
+var rvProfile23Features = CombineFeatures(RV_IMA, RV_C, RV_F, RV_D, RV_ZBA, RV_ZBB, RV_ZBS, RV_ZFHMIN, RV_ZICBOM, RV_ZICBOP, RV_ZICBOZ, RV_ZIHINTPAUSE, RV_V, RV_ZFA, RV_ZICOND, RV_ZVBB, RV_ZVKB)
+
+// RISC-V crypto suites — combined from individual extensions.
+var rvZKNFeatures = CombineFeatures(RV_ZKND, RV_ZKNE, RV_ZKNH, RV_ZBKB, RV_ZBKC, RV_ZBKX, RV_ZKT)
+var rvZKSFeatures = CombineFeatures(RV_ZKSED, RV_ZKSH, RV_ZBKB, RV_ZBKC, RV_ZBKX, RV_ZKT)
+var rvZVKNFeatures = CombineFeatures(RV_ZVKNED, RV_ZVKNHB, RV_ZVKG, RV_ZVKB, RV_ZVKT)
+var rvZVKSFeatures = CombineFeatures(RV_ZVKSED, RV_ZVKSH, RV_ZVKG, RV_ZVKB, RV_ZVKT)
+
+// ARM64 architecture levels. armV8Levels[m] is the cumulative set of mandatory
+// user-space instruction features added up to and including ARMv8.m that this
+// package can detect. EL1/system-only features (PAN, VHE, CSV2/CSV3, ECV, ...)
+// are excluded since they are irrelevant to user-space code generation, exactly
+// as X64Level ignores non-instruction features.
+//
+// FEAT_SSBS and FEAT_BTI, although mandatory from ARMv8.5, are intentionally NOT
+// required. Both are OS-policy-gated security features (speculative store bypass
+// safety and branch-target identification) that Go code generation never depends
+// on: their HWCAP/sysctl bits are set only when the OS or hypervisor enables the
+// protection, not purely from CPU capability, so they are routinely hidden even
+// on capable silicon (neither a Neoverse N2 Linux guest nor Apple Silicon reports
+// them). Requiring them would cap such CPUs at v8.4. Both are still detected and
+// reported through FeatureSet when present.
+// https://go.dev/wiki/MinimumRequirements#arm64
+var armV8Levels = [...]Features{
+	CombineFeatures(FP, ASIMD),                                                                                                                          // v8.0
+	CombineFeatures(FP, ASIMD, ATOMICS, CRC32, ASIMDRDM),                                                                                                // v8.1
+	CombineFeatures(FP, ASIMD, ATOMICS, CRC32, ASIMDRDM, DCPOP),                                                                                         // v8.2
+	CombineFeatures(FP, ASIMD, ATOMICS, CRC32, ASIMDRDM, DCPOP, JSCVT, FCMA, LRCPC),                                                                     // v8.3
+	CombineFeatures(FP, ASIMD, ATOMICS, CRC32, ASIMDRDM, DCPOP, JSCVT, FCMA, LRCPC, TS),                                                                 // v8.4
+	CombineFeatures(FP, ASIMD, ATOMICS, CRC32, ASIMDRDM, DCPOP, JSCVT, FCMA, LRCPC, TS, SB, FRINTTS, FLAGM2, DCPODP),                                    // v8.5
+	CombineFeatures(FP, ASIMD, ATOMICS, CRC32, ASIMDRDM, DCPOP, JSCVT, FCMA, LRCPC, TS, SB, FRINTTS, FLAGM2, DCPODP, BF16, I8MM),                        // v8.6
+	CombineFeatures(FP, ASIMD, ATOMICS, CRC32, ASIMDRDM, DCPOP, JSCVT, FCMA, LRCPC, TS, SB, FRINTTS, FLAGM2, DCPODP, BF16, I8MM, WFXT),                  // v8.7
+	CombineFeatures(FP, ASIMD, ATOMICS, CRC32, ASIMDRDM, DCPOP, JSCVT, FCMA, LRCPC, TS, SB, FRINTTS, FLAGM2, DCPODP, BF16, I8MM, WFXT, MOPS, HBC),       // v8.8
+	CombineFeatures(FP, ASIMD, ATOMICS, CRC32, ASIMDRDM, DCPOP, JSCVT, FCMA, LRCPC, TS, SB, FRINTTS, FLAGM2, DCPODP, BF16, I8MM, WFXT, MOPS, HBC, CSSC), // v8.9
+}
+
+// armCrypto matches the GOARM64 ",crypto" option: FEAT_AES, FEAT_PMULL,
+// FEAT_SHA1 and FEAT_SHA256.
+var armCrypto = CombineFeatures(AESARM, PMULL, SHA1, SHA2)
+
 // X64Level returns the microarchitecture level detected on the CPU.
 // If features are lacking or non x64 mode, 0 is returned.
 // See https://en.wikipedia.org/wiki/X86-64#Microarchitecture_levels
@@ -525,6 +649,67 @@ func (c CPUInfo) X64Level() int {
 	return 0
 }
 
+// RVProfile returns the RISC-V application profile level.
+// 0 = unknown / base ISA only, 20 = RVA20, 22 = RVA22, 23 = RVA23.
+// Returns 0 on non-RISC-V architectures or if not detected.
+// https://github.com/riscv/riscv-profiles
+func (c CPUInfo) RVProfile() int {
+	switch {
+	case c.featureSet.hasSetP(rvProfile23Features):
+		return 23
+	case c.featureSet.hasSetP(rvProfile22Features):
+		return 22
+	case c.featureSet.hasSetP(rvProfile20Features):
+		return 20
+	default:
+		return 0
+	}
+}
+
+// ARM64Level returns the ARMv8/ARMv9 architecture version supported by the CPU
+// as (major, minor), e.g. 8, 4 for ARMv8.4-A or 9, 0 for ARMv9.0-A.
+// Only mandatory user-space instruction features are considered, so the result
+// is the highest level whose required instructions are all present.
+// Returns 0, 0 on non-arm64 CPUs or when feature detection was unavailable.
+func (c CPUInfo) ARM64Level() (major, minor int) {
+	if !c.featureSet.hasSetP(armV8Levels[0]) {
+		return 0, 0
+	}
+	m8 := 0
+	for m := len(armV8Levels) - 1; m >= 1; m-- {
+		if c.featureSet.hasSetP(armV8Levels[m]) {
+			m8 = m
+			break
+		}
+	}
+	// ARMv9.x mandates everything in ARMv8.(x+5) plus SVE2.
+	if m8 >= 5 && c.featureSet.inSet(SVE2) {
+		return 9, m8 - 5
+	}
+	return 8, m8
+}
+
+// GOARM64 returns a value usable as the GOARM64 build setting for the detected
+// CPU, e.g. "v8.4" or "v9.0,crypto". The ",crypto" suffix is appended when AES,
+// PMULL, SHA1 and SHA256 are all present; the ",lse" suffix is appended in the
+// rare case LSE is present without the rest of the ARMv8.1 feature set.
+// Returns "" on non-arm64 CPUs or when feature detection was unavailable.
+// See https://go.dev/wiki/MinimumRequirements#arm64
+func (c CPUInfo) GOARM64() string {
+	major, minor := c.ARM64Level()
+	if major == 0 {
+		return ""
+	}
+	v := fmt.Sprintf("v%d.%d", major, minor)
+	if major == 8 && minor == 0 && c.featureSet.inSet(ATOMICS) {
+		v += ",lse"
+	}
+	if c.featureSet.hasSetP(armCrypto) {
+		v += ",crypto"
+	}
+	return v
+}
+
 // Disable will disable one or several features.
 func (c *CPUInfo) Disable(ids ...FeatureID) bool {
 	for _, id := range ids {
@@ -771,7 +956,7 @@ func flagSetWith(feat ...FeatureID) flagSet {
 // Will return UNKNOWN if not found.
 func ParseFeature(s string) FeatureID {
 	s = strings.ToUpper(s)
-	for i := firstID; i < lastID; i++ {
+	for i := range lastID {
 		if i.String() == s {
 			return i
 		}
@@ -785,7 +970,7 @@ func (s flagSet) Strings() []string {
 		return []string{""}
 	}
 	r := make([]string, 0)
-	for i := firstID; i < lastID; i++ {
+	for i := range lastID {
 		if s.inSet(i) {
 			r = append(r, i.String())
 		}
@@ -806,7 +991,7 @@ func maxFunctionID() uint32 {
 func brandName() string {
 	if maxExtendedFunction() >= 0x80000004 {
 		v := make([]uint32, 0, 48)
-		for i := uint32(0); i < 3; i++ {
+		for i := range uint32(3) {
 			a, b, c, d := cpuid(0x80000002 + i)
 			v = append(v, a, b, c, d)
 		}
@@ -1075,7 +1260,7 @@ func (c *CPUInfo) cacheSize() {
 		// Hack: When we encounter the same entry 100 times we break.
 		nSame := 0
 		var last uint32
-		for i := uint32(0); i < math.MaxUint32; i++ {
+		for i := range uint32(math.MaxUint32) {
 			eax, ebx, ecx, _ := cpuidex(0x8000001D, i)
 
 			level := (eax >> 5) & 7
@@ -1329,6 +1514,7 @@ func support() flagSet {
 		fs.setIf(eax1&(1<<10) != 0, MOVSB_ZL)
 		fs.setIf(eax1&(1<<11) != 0, STOSB_SHORT)
 		fs.setIf(eax1&(1<<12) != 0, CMPSB_SCADBS_SHORT)
+		fs.setIf(eax1&(1<<17) != 0, FRED)
 		fs.setIf(eax1&(1<<22) != 0, HRESET)
 		fs.setIf(eax1&(1<<23) != 0, AVXIFMA)
 		fs.setIf(eax1&(1<<26) != 0, LAM)
@@ -1562,6 +1748,7 @@ func support() flagSet {
 		fs.setIf((a>>29)&1 == 1, SRSO_NO)
 		fs.setIf((a>>28)&1 == 1, IBPB_BRTYPE)
 		fs.setIf((a>>27)&1 == 1, SBPB)
+		fs.setIf((a>>23)&1 == 1, AVX512BMM)
 		fs.setIf((c>>1)&1 == 1, TSA_L1_NO)
 		fs.setIf((c>>2)&1 == 1, TSA_SQ_NO)
 		fs.setIf((a>>5)&1 == 1, TSA_VERW_CLEAR)
diff --git a/vendor/github.com/klauspost/cpuid/v2/detect_arm64.go b/vendor/github.com/klauspost/cpuid/v2/detect_arm64.go
index 9ae32d607dc..e615b10be7d 100644
--- a/vendor/github.com/klauspost/cpuid/v2/detect_arm64.go
+++ b/vendor/github.com/klauspost/cpuid/v2/detect_arm64.go
@@ -1,7 +1,6 @@
 // Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file.
 
 //go:build arm64 && !gccgo && !noasm && !appengine
-// +build arm64,!gccgo,!noasm,!appengine
 
 package cpuid
 
@@ -189,6 +188,7 @@ func addInfo(c *CPUInfo, safe bool) {
 	f.setIf(instAttrReg0&(0xf<<60) != 0, RNDR)
 	f.setIf(instAttrReg0&(0xf<<56) != 0, TLB)
 	f.setIf(instAttrReg0&(0xf<<52) != 0, TS)
+	f.setIf(instAttrReg0&(0xf<<52) == 2<<52, FLAGM2) // TS == 0b0010 (FEAT_FlagM2)
 	f.setIf(instAttrReg0&(0xf<<48) != 0, FHM)
 	f.setIf(instAttrReg0&(0xf<<44) != 0, ASIMDDP)
 	f.setIf(instAttrReg0&(0xf<<40) != 0, SM4)
@@ -244,6 +244,13 @@ func addInfo(c *CPUInfo, safe bool) {
 	// 	fmt.Println("APA")
 	// }
 	f.setIf(instAttrReg1&(0xf<<0) != 0, DCPOP)
+	f.setIf(instAttrReg1&(0xf<<0) == 2<<0, DCPODP) // DPB == 0b0010 (FEAT_DPB2)
+
+	// Upper ID_AA64ISAR1_EL1 fields, not in the table above.
+	f.setIf(instAttrReg1&(0xf<<32) != 0, FRINTTS) // bits [35:32]
+	f.setIf(instAttrReg1&(0xf<<36) != 0, SB)      // bits [39:36]
+	f.setIf(instAttrReg1&(0xf<<44) != 0, BF16)    // bits [47:44]
+	f.setIf(instAttrReg1&(0xf<<52) != 0, I8MM)    // bits [55:52]
 
 	// Store
 	c.featureSet.or(f)
diff --git a/vendor/github.com/klauspost/cpuid/v2/detect_ref.go b/vendor/github.com/klauspost/cpuid/v2/detect_ref.go
index 574f9389c07..38699f4d78a 100644
--- a/vendor/github.com/klauspost/cpuid/v2/detect_ref.go
+++ b/vendor/github.com/klauspost/cpuid/v2/detect_ref.go
@@ -1,7 +1,6 @@
 // Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file.
 
-//go:build (!amd64 && !386 && !arm64) || gccgo || noasm || appengine
-// +build !amd64,!386,!arm64 gccgo noasm appengine
+//go:build (!amd64 && !386 && !arm64 && !riscv64) || ((amd64 || 386) && (gccgo || noasm || appengine))
 
 package cpuid
 
diff --git a/vendor/github.com/klauspost/cpuid/v2/detect_ref_arm64.go b/vendor/github.com/klauspost/cpuid/v2/detect_ref_arm64.go
new file mode 100644
index 00000000000..d2ea76ba823
--- /dev/null
+++ b/vendor/github.com/klauspost/cpuid/v2/detect_ref_arm64.go
@@ -0,0 +1,19 @@
+// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file.
+
+//go:build arm64 && (gccgo || noasm || appengine)
+
+package cpuid
+
+func initCPU() {
+	cpuid = func(uint32) (a, b, c, d uint32) { return 0, 0, 0, 0 }
+	cpuidex = func(x, y uint32) (a, b, c, d uint32) { return 0, 0, 0, 0 }
+	xgetbv = func(uint32) (a, b uint32) { return 0, 0 }
+	rdtscpAsm = func() (a, b, c, d uint32) { return 0, 0, 0, 0 }
+}
+
+func addInfo(c *CPUInfo, safe bool) {
+	c.CacheLine = 64
+	detectOS(c)
+}
+
+func getVectorLength() (vl, pl uint64) { return 0, 0 }
diff --git a/vendor/github.com/klauspost/cpuid/v2/detect_riscv64.go b/vendor/github.com/klauspost/cpuid/v2/detect_riscv64.go
new file mode 100644
index 00000000000..25381f08982
--- /dev/null
+++ b/vendor/github.com/klauspost/cpuid/v2/detect_riscv64.go
@@ -0,0 +1,16 @@
+// Copyright (c) 2026 Klaus Post, released under MIT License. See LICENSE file.
+
+package cpuid
+
+func getVectorLength() (vl, pl uint64) { return 0, 0 }
+
+func initCPU() {
+	cpuid = func(uint32) (a, b, c, d uint32) { return 0, 0, 0, 0 }
+	cpuidex = func(x, y uint32) (a, b, c, d uint32) { return 0, 0, 0, 0 }
+	xgetbv = func(uint32) (a, b uint32) { return 0, 0 }
+	rdtscpAsm = func() (a, b, c, d uint32) { return 0, 0, 0, 0 }
+}
+
+func addInfo(c *CPUInfo, safe bool) {
+	detectOS(c)
+}
diff --git a/vendor/github.com/klauspost/cpuid/v2/detect_x86.go b/vendor/github.com/klauspost/cpuid/v2/detect_x86.go
index 14a56b9301c..22819ce4a91 100644
--- a/vendor/github.com/klauspost/cpuid/v2/detect_x86.go
+++ b/vendor/github.com/klauspost/cpuid/v2/detect_x86.go
@@ -1,7 +1,6 @@
 // Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file.
 
 //go:build (386 && !gccgo && !noasm && !appengine) || (amd64 && !gccgo && !noasm && !appengine)
-// +build 386,!gccgo,!noasm,!appengine amd64,!gccgo,!noasm,!appengine
 
 package cpuid
 
diff --git a/vendor/github.com/klauspost/cpuid/v2/featureid_string.go b/vendor/github.com/klauspost/cpuid/v2/featureid_string.go
index 2888bae8faa..f88ead13080 100644
--- a/vendor/github.com/klauspost/cpuid/v2/featureid_string.go
+++ b/vendor/github.com/klauspost/cpuid/v2/featureid_string.go
@@ -29,234 +29,292 @@ func _() {
 	_ = x[AVX2-19]
 	_ = x[AVX512BF16-20]
 	_ = x[AVX512BITALG-21]
-	_ = x[AVX512BW-22]
-	_ = x[AVX512CD-23]
-	_ = x[AVX512DQ-24]
-	_ = x[AVX512ER-25]
-	_ = x[AVX512F-26]
-	_ = x[AVX512FP16-27]
-	_ = x[AVX512IFMA-28]
-	_ = x[AVX512PF-29]
-	_ = x[AVX512VBMI-30]
-	_ = x[AVX512VBMI2-31]
-	_ = x[AVX512VL-32]
-	_ = x[AVX512VNNI-33]
-	_ = x[AVX512VP2INTERSECT-34]
-	_ = x[AVX512VPOPCNTDQ-35]
-	_ = x[AVXIFMA-36]
-	_ = x[AVXNECONVERT-37]
-	_ = x[AVXSLOW-38]
-	_ = x[AVXVNNI-39]
-	_ = x[AVXVNNIINT8-40]
-	_ = x[AVXVNNIINT16-41]
-	_ = x[BHI_CTRL-42]
-	_ = x[BMI1-43]
-	_ = x[BMI2-44]
-	_ = x[CETIBT-45]
-	_ = x[CETSS-46]
-	_ = x[CLDEMOTE-47]
-	_ = x[CLMUL-48]
-	_ = x[CLZERO-49]
-	_ = x[CMOV-50]
-	_ = x[CMPCCXADD-51]
-	_ = x[CMPSB_SCADBS_SHORT-52]
-	_ = x[CMPXCHG8-53]
-	_ = x[CPBOOST-54]
-	_ = x[CPPC-55]
-	_ = x[CX16-56]
-	_ = x[EFER_LMSLE_UNS-57]
-	_ = x[ENQCMD-58]
-	_ = x[ERMS-59]
-	_ = x[F16C-60]
-	_ = x[FLUSH_L1D-61]
-	_ = x[FMA3-62]
-	_ = x[FMA4-63]
-	_ = x[FP128-64]
-	_ = x[FP256-65]
-	_ = x[FSRM-66]
-	_ = x[FXSR-67]
-	_ = x[FXSROPT-68]
-	_ = x[GFNI-69]
-	_ = x[HLE-70]
-	_ = x[HRESET-71]
-	_ = x[HTT-72]
-	_ = x[HWA-73]
-	_ = x[HYBRID_CPU-74]
-	_ = x[HYPERVISOR-75]
-	_ = x[IA32_ARCH_CAP-76]
-	_ = x[IA32_CORE_CAP-77]
-	_ = x[IBPB-78]
-	_ = x[IBPB_BRTYPE-79]
-	_ = x[IBRS-80]
-	_ = x[IBRS_PREFERRED-81]
-	_ = x[IBRS_PROVIDES_SMP-82]
-	_ = x[IBS-83]
-	_ = x[IBSBRNTRGT-84]
-	_ = x[IBSFETCHSAM-85]
-	_ = x[IBSFFV-86]
-	_ = x[IBSOPCNT-87]
-	_ = x[IBSOPCNTEXT-88]
-	_ = x[IBSOPSAM-89]
-	_ = x[IBSRDWROPCNT-90]
-	_ = x[IBSRIPINVALIDCHK-91]
-	_ = x[IBS_FETCH_CTLX-92]
-	_ = x[IBS_OPDATA4-93]
-	_ = x[IBS_OPFUSE-94]
-	_ = x[IBS_PREVENTHOST-95]
-	_ = x[IBS_ZEN4-96]
-	_ = x[IDPRED_CTRL-97]
-	_ = x[INT_WBINVD-98]
-	_ = x[INVLPGB-99]
-	_ = x[KEYLOCKER-100]
-	_ = x[KEYLOCKERW-101]
-	_ = x[LAHF-102]
-	_ = x[LAM-103]
-	_ = x[LBRVIRT-104]
-	_ = x[LZCNT-105]
-	_ = x[MCAOVERFLOW-106]
-	_ = x[MCDT_NO-107]
-	_ = x[MCOMMIT-108]
-	_ = x[MD_CLEAR-109]
-	_ = x[MMX-110]
-	_ = x[MMXEXT-111]
-	_ = x[MOVBE-112]
-	_ = x[MOVDIR64B-113]
-	_ = x[MOVDIRI-114]
-	_ = x[MOVSB_ZL-115]
-	_ = x[MOVU-116]
-	_ = x[MPX-117]
-	_ = x[MSRIRC-118]
-	_ = x[MSRLIST-119]
-	_ = x[MSR_PAGEFLUSH-120]
-	_ = x[NRIPS-121]
-	_ = x[NX-122]
-	_ = x[OSXSAVE-123]
-	_ = x[PCONFIG-124]
-	_ = x[POPCNT-125]
-	_ = x[PPIN-126]
-	_ = x[PREFETCHI-127]
-	_ = x[PSFD-128]
-	_ = x[RDPRU-129]
-	_ = x[RDRAND-130]
-	_ = x[RDSEED-131]
-	_ = x[RDTSCP-132]
-	_ = x[RRSBA_CTRL-133]
-	_ = x[RTM-134]
-	_ = x[RTM_ALWAYS_ABORT-135]
-	_ = x[SBPB-136]
-	_ = x[SERIALIZE-137]
-	_ = x[SEV-138]
-	_ = x[SEV_64BIT-139]
-	_ = x[SEV_ALTERNATIVE-140]
-	_ = x[SEV_DEBUGSWAP-141]
-	_ = x[SEV_ES-142]
-	_ = x[SEV_RESTRICTED-143]
-	_ = x[SEV_SNP-144]
-	_ = x[SGX-145]
-	_ = x[SGXLC-146]
-	_ = x[SGXPQC-147]
-	_ = x[SHA-148]
-	_ = x[SME-149]
-	_ = x[SME_COHERENT-150]
-	_ = x[SM3_X86-151]
-	_ = x[SM4_X86-152]
-	_ = x[SPEC_CTRL_SSBD-153]
-	_ = x[SRBDS_CTRL-154]
-	_ = x[SRSO_MSR_FIX-155]
-	_ = x[SRSO_NO-156]
-	_ = x[SRSO_USER_KERNEL_NO-157]
-	_ = x[SSE-158]
-	_ = x[SSE2-159]
-	_ = x[SSE3-160]
-	_ = x[SSE4-161]
-	_ = x[SSE42-162]
-	_ = x[SSE4A-163]
-	_ = x[SSSE3-164]
-	_ = x[STIBP-165]
-	_ = x[STIBP_ALWAYSON-166]
-	_ = x[STOSB_SHORT-167]
-	_ = x[SUCCOR-168]
-	_ = x[SVM-169]
-	_ = x[SVMDA-170]
-	_ = x[SVMFBASID-171]
-	_ = x[SVML-172]
-	_ = x[SVMNP-173]
-	_ = x[SVMPF-174]
-	_ = x[SVMPFT-175]
-	_ = x[SYSCALL-176]
-	_ = x[SYSEE-177]
-	_ = x[TBM-178]
-	_ = x[TDX_GUEST-179]
-	_ = x[TLB_FLUSH_NESTED-180]
-	_ = x[TME-181]
-	_ = x[TOPEXT-182]
-	_ = x[TSA_L1_NO-183]
-	_ = x[TSA_SQ_NO-184]
-	_ = x[TSA_VERW_CLEAR-185]
-	_ = x[TSCRATEMSR-186]
-	_ = x[TSXLDTRK-187]
-	_ = x[VAES-188]
-	_ = x[VMCBCLEAN-189]
-	_ = x[VMPL-190]
-	_ = x[VMSA_REGPROT-191]
-	_ = x[VMX-192]
-	_ = x[VPCLMULQDQ-193]
-	_ = x[VTE-194]
-	_ = x[WAITPKG-195]
-	_ = x[WBNOINVD-196]
-	_ = x[WRMSRNS-197]
-	_ = x[X87-198]
-	_ = x[XGETBV1-199]
-	_ = x[XOP-200]
-	_ = x[XSAVE-201]
-	_ = x[XSAVEC-202]
-	_ = x[XSAVEOPT-203]
-	_ = x[XSAVES-204]
-	_ = x[AESARM-205]
-	_ = x[ARMCPUID-206]
-	_ = x[ASIMD-207]
-	_ = x[ASIMDDP-208]
-	_ = x[ASIMDHP-209]
-	_ = x[ASIMDRDM-210]
-	_ = x[ATOMICS-211]
-	_ = x[CRC32-212]
-	_ = x[DCPOP-213]
-	_ = x[EVTSTRM-214]
-	_ = x[FCMA-215]
-	_ = x[FHM-216]
-	_ = x[FP-217]
-	_ = x[FPHP-218]
-	_ = x[GPA-219]
-	_ = x[JSCVT-220]
-	_ = x[LRCPC-221]
-	_ = x[PMULL-222]
-	_ = x[RNDR-223]
-	_ = x[TLB-224]
-	_ = x[TS-225]
-	_ = x[SHA1-226]
-	_ = x[SHA2-227]
-	_ = x[SHA3-228]
-	_ = x[SHA512-229]
-	_ = x[SM3-230]
-	_ = x[SM4-231]
-	_ = x[SVE-232]
-	_ = x[PMU_FIXEDCOUNTER_CYCLES-233]
-	_ = x[PMU_FIXEDCOUNTER_REFCYCLES-234]
-	_ = x[PMU_FIXEDCOUNTER_INSTRUCTIONS-235]
-	_ = x[PMU_FIXEDCOUNTER_TOPDOWN_SLOTS-236]
-	_ = x[lastID-237]
+	_ = x[AVX512BMM-22]
+	_ = x[AVX512BW-23]
+	_ = x[AVX512CD-24]
+	_ = x[AVX512DQ-25]
+	_ = x[AVX512ER-26]
+	_ = x[AVX512F-27]
+	_ = x[AVX512FP16-28]
+	_ = x[AVX512IFMA-29]
+	_ = x[AVX512PF-30]
+	_ = x[AVX512VBMI-31]
+	_ = x[AVX512VBMI2-32]
+	_ = x[AVX512VL-33]
+	_ = x[AVX512VNNI-34]
+	_ = x[AVX512VP2INTERSECT-35]
+	_ = x[AVX512VPOPCNTDQ-36]
+	_ = x[AVXIFMA-37]
+	_ = x[AVXNECONVERT-38]
+	_ = x[AVXSLOW-39]
+	_ = x[AVXVNNI-40]
+	_ = x[AVXVNNIINT8-41]
+	_ = x[AVXVNNIINT16-42]
+	_ = x[BHI_CTRL-43]
+	_ = x[BMI1-44]
+	_ = x[BMI2-45]
+	_ = x[CETIBT-46]
+	_ = x[CETSS-47]
+	_ = x[CLDEMOTE-48]
+	_ = x[CLMUL-49]
+	_ = x[CLZERO-50]
+	_ = x[CMOV-51]
+	_ = x[CMPCCXADD-52]
+	_ = x[CMPSB_SCADBS_SHORT-53]
+	_ = x[CMPXCHG8-54]
+	_ = x[CPBOOST-55]
+	_ = x[CPPC-56]
+	_ = x[CX16-57]
+	_ = x[EFER_LMSLE_UNS-58]
+	_ = x[ENQCMD-59]
+	_ = x[ERMS-60]
+	_ = x[F16C-61]
+	_ = x[FLUSH_L1D-62]
+	_ = x[FMA3-63]
+	_ = x[FMA4-64]
+	_ = x[FP128-65]
+	_ = x[FP256-66]
+	_ = x[FRED-67]
+	_ = x[FSRM-68]
+	_ = x[FXSR-69]
+	_ = x[FXSROPT-70]
+	_ = x[GFNI-71]
+	_ = x[HLE-72]
+	_ = x[HRESET-73]
+	_ = x[HTT-74]
+	_ = x[HWA-75]
+	_ = x[HYBRID_CPU-76]
+	_ = x[HYPERVISOR-77]
+	_ = x[IA32_ARCH_CAP-78]
+	_ = x[IA32_CORE_CAP-79]
+	_ = x[IBPB-80]
+	_ = x[IBPB_BRTYPE-81]
+	_ = x[IBRS-82]
+	_ = x[IBRS_PREFERRED-83]
+	_ = x[IBRS_PROVIDES_SMP-84]
+	_ = x[IBS-85]
+	_ = x[IBSBRNTRGT-86]
+	_ = x[IBSFETCHSAM-87]
+	_ = x[IBSFFV-88]
+	_ = x[IBSOPCNT-89]
+	_ = x[IBSOPCNTEXT-90]
+	_ = x[IBSOPSAM-91]
+	_ = x[IBSRDWROPCNT-92]
+	_ = x[IBSRIPINVALIDCHK-93]
+	_ = x[IBS_FETCH_CTLX-94]
+	_ = x[IBS_OPDATA4-95]
+	_ = x[IBS_OPFUSE-96]
+	_ = x[IBS_PREVENTHOST-97]
+	_ = x[IBS_ZEN4-98]
+	_ = x[IDPRED_CTRL-99]
+	_ = x[INT_WBINVD-100]
+	_ = x[INVLPGB-101]
+	_ = x[KEYLOCKER-102]
+	_ = x[KEYLOCKERW-103]
+	_ = x[LAHF-104]
+	_ = x[LAM-105]
+	_ = x[LBRVIRT-106]
+	_ = x[LZCNT-107]
+	_ = x[MCAOVERFLOW-108]
+	_ = x[MCDT_NO-109]
+	_ = x[MCOMMIT-110]
+	_ = x[MD_CLEAR-111]
+	_ = x[MMX-112]
+	_ = x[MMXEXT-113]
+	_ = x[MOVBE-114]
+	_ = x[MOVDIR64B-115]
+	_ = x[MOVDIRI-116]
+	_ = x[MOVSB_ZL-117]
+	_ = x[MOVU-118]
+	_ = x[MPX-119]
+	_ = x[MSRIRC-120]
+	_ = x[MSRLIST-121]
+	_ = x[MSR_PAGEFLUSH-122]
+	_ = x[NRIPS-123]
+	_ = x[NX-124]
+	_ = x[OSXSAVE-125]
+	_ = x[PCONFIG-126]
+	_ = x[POPCNT-127]
+	_ = x[PPIN-128]
+	_ = x[PREFETCHI-129]
+	_ = x[PSFD-130]
+	_ = x[RDPRU-131]
+	_ = x[RDRAND-132]
+	_ = x[RDSEED-133]
+	_ = x[RDTSCP-134]
+	_ = x[RRSBA_CTRL-135]
+	_ = x[RTM-136]
+	_ = x[RTM_ALWAYS_ABORT-137]
+	_ = x[SBPB-138]
+	_ = x[SERIALIZE-139]
+	_ = x[SEV-140]
+	_ = x[SEV_64BIT-141]
+	_ = x[SEV_ALTERNATIVE-142]
+	_ = x[SEV_DEBUGSWAP-143]
+	_ = x[SEV_ES-144]
+	_ = x[SEV_RESTRICTED-145]
+	_ = x[SEV_SNP-146]
+	_ = x[SGX-147]
+	_ = x[SGXLC-148]
+	_ = x[SGXPQC-149]
+	_ = x[SHA-150]
+	_ = x[SME-151]
+	_ = x[SME_COHERENT-152]
+	_ = x[SM3_X86-153]
+	_ = x[SM4_X86-154]
+	_ = x[SPEC_CTRL_SSBD-155]
+	_ = x[SRBDS_CTRL-156]
+	_ = x[SRSO_MSR_FIX-157]
+	_ = x[SRSO_NO-158]
+	_ = x[SRSO_USER_KERNEL_NO-159]
+	_ = x[SSE-160]
+	_ = x[SSE2-161]
+	_ = x[SSE3-162]
+	_ = x[SSE4-163]
+	_ = x[SSE42-164]
+	_ = x[SSE4A-165]
+	_ = x[SSSE3-166]
+	_ = x[STIBP-167]
+	_ = x[STIBP_ALWAYSON-168]
+	_ = x[STOSB_SHORT-169]
+	_ = x[SUCCOR-170]
+	_ = x[SVM-171]
+	_ = x[SVMDA-172]
+	_ = x[SVMFBASID-173]
+	_ = x[SVML-174]
+	_ = x[SVMNP-175]
+	_ = x[SVMPF-176]
+	_ = x[SVMPFT-177]
+	_ = x[SYSCALL-178]
+	_ = x[SYSEE-179]
+	_ = x[TBM-180]
+	_ = x[TDX_GUEST-181]
+	_ = x[TLB_FLUSH_NESTED-182]
+	_ = x[TME-183]
+	_ = x[TOPEXT-184]
+	_ = x[TSA_L1_NO-185]
+	_ = x[TSA_SQ_NO-186]
+	_ = x[TSA_VERW_CLEAR-187]
+	_ = x[TSCRATEMSR-188]
+	_ = x[TSXLDTRK-189]
+	_ = x[VAES-190]
+	_ = x[VMCBCLEAN-191]
+	_ = x[VMPL-192]
+	_ = x[VMSA_REGPROT-193]
+	_ = x[VMX-194]
+	_ = x[VPCLMULQDQ-195]
+	_ = x[VTE-196]
+	_ = x[WAITPKG-197]
+	_ = x[WBNOINVD-198]
+	_ = x[WRMSRNS-199]
+	_ = x[X87-200]
+	_ = x[XGETBV1-201]
+	_ = x[XOP-202]
+	_ = x[XSAVE-203]
+	_ = x[XSAVEC-204]
+	_ = x[XSAVEOPT-205]
+	_ = x[XSAVES-206]
+	_ = x[AESARM-207]
+	_ = x[ARMCPUID-208]
+	_ = x[ASIMD-209]
+	_ = x[ASIMDDP-210]
+	_ = x[ASIMDHP-211]
+	_ = x[ASIMDRDM-212]
+	_ = x[ATOMICS-213]
+	_ = x[CRC32-214]
+	_ = x[DCPOP-215]
+	_ = x[EVTSTRM-216]
+	_ = x[FCMA-217]
+	_ = x[FHM-218]
+	_ = x[FP-219]
+	_ = x[FPHP-220]
+	_ = x[GPA-221]
+	_ = x[JSCVT-222]
+	_ = x[LRCPC-223]
+	_ = x[PMULL-224]
+	_ = x[RNDR-225]
+	_ = x[TLB-226]
+	_ = x[TS-227]
+	_ = x[SHA1-228]
+	_ = x[SHA2-229]
+	_ = x[SHA3-230]
+	_ = x[SHA512-231]
+	_ = x[SM3-232]
+	_ = x[SM4-233]
+	_ = x[SVE-234]
+	_ = x[SVE2-235]
+	_ = x[SB-236]
+	_ = x[SSBS-237]
+	_ = x[BTI-238]
+	_ = x[FLAGM2-239]
+	_ = x[FRINTTS-240]
+	_ = x[DCPODP-241]
+	_ = x[BF16-242]
+	_ = x[I8MM-243]
+	_ = x[WFXT-244]
+	_ = x[MOPS-245]
+	_ = x[HBC-246]
+	_ = x[CSSC-247]
+	_ = x[PMU_FIXEDCOUNTER_CYCLES-248]
+	_ = x[PMU_FIXEDCOUNTER_REFCYCLES-249]
+	_ = x[PMU_FIXEDCOUNTER_INSTRUCTIONS-250]
+	_ = x[PMU_FIXEDCOUNTER_TOPDOWN_SLOTS-251]
+	_ = x[RV_IMA-252]
+	_ = x[RV_C-253]
+	_ = x[RV_F-254]
+	_ = x[RV_D-255]
+	_ = x[RV_V-256]
+	_ = x[RV_ZBA-257]
+	_ = x[RV_ZBB-258]
+	_ = x[RV_ZBC-259]
+	_ = x[RV_ZBS-260]
+	_ = x[RV_ZICOND-261]
+	_ = x[RV_ZIHINTPAUSE-262]
+	_ = x[RV_ZICBOM-263]
+	_ = x[RV_ZICBOZ-264]
+	_ = x[RV_ZICBOP-265]
+	_ = x[RV_ZFA-266]
+	_ = x[RV_ZFH-267]
+	_ = x[RV_ZFHMIN-268]
+	_ = x[RV_ZTSO-269]
+	_ = x[RV_ZACAS-270]
+	_ = x[RV_ZBKB-271]
+	_ = x[RV_ZBKC-272]
+	_ = x[RV_ZBKX-273]
+	_ = x[RV_ZKND-274]
+	_ = x[RV_ZKNE-275]
+	_ = x[RV_ZKNH-276]
+	_ = x[RV_ZKSED-277]
+	_ = x[RV_ZKSH-278]
+	_ = x[RV_ZKT-279]
+	_ = x[RV_ZKN-280]
+	_ = x[RV_ZKS-281]
+	_ = x[RV_ZVBB-282]
+	_ = x[RV_ZVBC-283]
+	_ = x[RV_ZVKB-284]
+	_ = x[RV_ZVKG-285]
+	_ = x[RV_ZVKNED-286]
+	_ = x[RV_ZVKNHA-287]
+	_ = x[RV_ZVKNHB-288]
+	_ = x[RV_ZVKSED-289]
+	_ = x[RV_ZVKSH-290]
+	_ = x[RV_ZVKT-291]
+	_ = x[RV_ZVKNG-292]
+	_ = x[RV_ZVKSG-293]
+	_ = x[lastID-294]
 	_ = x[firstID-0]
 }
 
-const _FeatureID_name = "firstIDADXAESNIAMD3DNOWAMD3DNOWEXTAMXBF16AMXFP16AMXINT8AMXFP8AMXTILEAMXTF32AMXCOMPLEXAMXTRANSPOSEAPX_FAVXAVX10AVX10_128AVX10_256AVX10_512AVX2AVX512BF16AVX512BITALGAVX512BWAVX512CDAVX512DQAVX512ERAVX512FAVX512FP16AVX512IFMAAVX512PFAVX512VBMIAVX512VBMI2AVX512VLAVX512VNNIAVX512VP2INTERSECTAVX512VPOPCNTDQAVXIFMAAVXNECONVERTAVXSLOWAVXVNNIAVXVNNIINT8AVXVNNIINT16BHI_CTRLBMI1BMI2CETIBTCETSSCLDEMOTECLMULCLZEROCMOVCMPCCXADDCMPSB_SCADBS_SHORTCMPXCHG8CPBOOSTCPPCCX16EFER_LMSLE_UNSENQCMDERMSF16CFLUSH_L1DFMA3FMA4FP128FP256FSRMFXSRFXSROPTGFNIHLEHRESETHTTHWAHYBRID_CPUHYPERVISORIA32_ARCH_CAPIA32_CORE_CAPIBPBIBPB_BRTYPEIBRSIBRS_PREFERREDIBRS_PROVIDES_SMPIBSIBSBRNTRGTIBSFETCHSAMIBSFFVIBSOPCNTIBSOPCNTEXTIBSOPSAMIBSRDWROPCNTIBSRIPINVALIDCHKIBS_FETCH_CTLXIBS_OPDATA4IBS_OPFUSEIBS_PREVENTHOSTIBS_ZEN4IDPRED_CTRLINT_WBINVDINVLPGBKEYLOCKERKEYLOCKERWLAHFLAMLBRVIRTLZCNTMCAOVERFLOWMCDT_NOMCOMMITMD_CLEARMMXMMXEXTMOVBEMOVDIR64BMOVDIRIMOVSB_ZLMOVUMPXMSRIRCMSRLISTMSR_PAGEFLUSHNRIPSNXOSXSAVEPCONFIGPOPCNTPPINPREFETCHIPSFDRDPRURDRANDRDSEEDRDTSCPRRSBA_CTRLRTMRTM_ALWAYS_ABORTSBPBSERIALIZESEVSEV_64BITSEV_ALTERNATIVESEV_DEBUGSWAPSEV_ESSEV_RESTRICTEDSEV_SNPSGXSGXLCSGXPQCSHASMESME_COHERENTSM3_X86SM4_X86SPEC_CTRL_SSBDSRBDS_CTRLSRSO_MSR_FIXSRSO_NOSRSO_USER_KERNEL_NOSSESSE2SSE3SSE4SSE42SSE4ASSSE3STIBPSTIBP_ALWAYSONSTOSB_SHORTSUCCORSVMSVMDASVMFBASIDSVMLSVMNPSVMPFSVMPFTSYSCALLSYSEETBMTDX_GUESTTLB_FLUSH_NESTEDTMETOPEXTTSA_L1_NOTSA_SQ_NOTSA_VERW_CLEARTSCRATEMSRTSXLDTRKVAESVMCBCLEANVMPLVMSA_REGPROTVMXVPCLMULQDQVTEWAITPKGWBNOINVDWRMSRNSX87XGETBV1XOPXSAVEXSAVECXSAVEOPTXSAVESAESARMARMCPUIDASIMDASIMDDPASIMDHPASIMDRDMATOMICSCRC32DCPOPEVTSTRMFCMAFHMFPFPHPGPAJSCVTLRCPCPMULLRNDRTLBTSSHA1SHA2SHA3SHA512SM3SM4SVEPMU_FIXEDCOUNTER_CYCLESPMU_FIXEDCOUNTER_REFCYCLESPMU_FIXEDCOUNTER_INSTRUCTIONSPMU_FIXEDCOUNTER_TOPDOWN_SLOTSlastID"
+const _FeatureID_name = "firstIDADXAESNIAMD3DNOWAMD3DNOWEXTAMXBF16AMXFP16AMXINT8AMXFP8AMXTILEAMXTF32AMXCOMPLEXAMXTRANSPOSEAPX_FAVXAVX10AVX10_128AVX10_256AVX10_512AVX2AVX512BF16AVX512BITALGAVX512BMMAVX512BWAVX512CDAVX512DQAVX512ERAVX512FAVX512FP16AVX512IFMAAVX512PFAVX512VBMIAVX512VBMI2AVX512VLAVX512VNNIAVX512VP2INTERSECTAVX512VPOPCNTDQAVXIFMAAVXNECONVERTAVXSLOWAVXVNNIAVXVNNIINT8AVXVNNIINT16BHI_CTRLBMI1BMI2CETIBTCETSSCLDEMOTECLMULCLZEROCMOVCMPCCXADDCMPSB_SCADBS_SHORTCMPXCHG8CPBOOSTCPPCCX16EFER_LMSLE_UNSENQCMDERMSF16CFLUSH_L1DFMA3FMA4FP128FP256FREDFSRMFXSRFXSROPTGFNIHLEHRESETHTTHWAHYBRID_CPUHYPERVISORIA32_ARCH_CAPIA32_CORE_CAPIBPBIBPB_BRTYPEIBRSIBRS_PREFERREDIBRS_PROVIDES_SMPIBSIBSBRNTRGTIBSFETCHSAMIBSFFVIBSOPCNTIBSOPCNTEXTIBSOPSAMIBSRDWROPCNTIBSRIPINVALIDCHKIBS_FETCH_CTLXIBS_OPDATA4IBS_OPFUSEIBS_PREVENTHOSTIBS_ZEN4IDPRED_CTRLINT_WBINVDINVLPGBKEYLOCKERKEYLOCKERWLAHFLAMLBRVIRTLZCNTMCAOVERFLOWMCDT_NOMCOMMITMD_CLEARMMXMMXEXTMOVBEMOVDIR64BMOVDIRIMOVSB_ZLMOVUMPXMSRIRCMSRLISTMSR_PAGEFLUSHNRIPSNXOSXSAVEPCONFIGPOPCNTPPINPREFETCHIPSFDRDPRURDRANDRDSEEDRDTSCPRRSBA_CTRLRTMRTM_ALWAYS_ABORTSBPBSERIALIZESEVSEV_64BITSEV_ALTERNATIVESEV_DEBUGSWAPSEV_ESSEV_RESTRICTEDSEV_SNPSGXSGXLCSGXPQCSHASMESME_COHERENTSM3_X86SM4_X86SPEC_CTRL_SSBDSRBDS_CTRLSRSO_MSR_FIXSRSO_NOSRSO_USER_KERNEL_NOSSESSE2SSE3SSE4SSE42SSE4ASSSE3STIBPSTIBP_ALWAYSONSTOSB_SHORTSUCCORSVMSVMDASVMFBASIDSVMLSVMNPSVMPFSVMPFTSYSCALLSYSEETBMTDX_GUESTTLB_FLUSH_NESTEDTMETOPEXTTSA_L1_NOTSA_SQ_NOTSA_VERW_CLEARTSCRATEMSRTSXLDTRKVAESVMCBCLEANVMPLVMSA_REGPROTVMXVPCLMULQDQVTEWAITPKGWBNOINVDWRMSRNSX87XGETBV1XOPXSAVEXSAVECXSAVEOPTXSAVESAESARMARMCPUIDASIMDASIMDDPASIMDHPASIMDRDMATOMICSCRC32DCPOPEVTSTRMFCMAFHMFPFPHPGPAJSCVTLRCPCPMULLRNDRTLBTSSHA1SHA2SHA3SHA512SM3SM4SVESVE2SBSSBSBTIFLAGM2FRINTTSDCPODPBF16I8MMWFXTMOPSHBCCSSCPMU_FIXEDCOUNTER_CYCLESPMU_FIXEDCOUNTER_REFCYCLESPMU_FIXEDCOUNTER_INSTRUCTIONSPMU_FIXEDCOUNTER_TOPDOWN_SLOTSRV_IMARV_CRV_FRV_DRV_VRV_ZBARV_ZBBRV_ZBCRV_ZBSRV_ZICONDRV_ZIHINTPAUSERV_ZICBOMRV_ZICBOZRV_ZICBOPRV_ZFARV_ZFHRV_ZFHMINRV_ZTSORV_ZACASRV_ZBKBRV_ZBKCRV_ZBKXRV_ZKNDRV_ZKNERV_ZKNHRV_ZKSEDRV_ZKSHRV_ZKTRV_ZKNRV_ZKSRV_ZVBBRV_ZVBCRV_ZVKBRV_ZVKGRV_ZVKNEDRV_ZVKNHARV_ZVKNHBRV_ZVKSEDRV_ZVKSHRV_ZVKTRV_ZVKNGRV_ZVKSGlastID"
 
-var _FeatureID_index = [...]uint16{0, 7, 10, 15, 23, 34, 41, 48, 55, 61, 68, 75, 85, 97, 102, 105, 110, 119, 128, 137, 141, 151, 163, 171, 179, 187, 195, 202, 212, 222, 230, 240, 251, 259, 269, 287, 302, 309, 321, 328, 335, 346, 358, 366, 370, 374, 380, 385, 393, 398, 404, 408, 417, 435, 443, 450, 454, 458, 472, 478, 482, 486, 495, 499, 503, 508, 513, 517, 521, 528, 532, 535, 541, 544, 547, 557, 567, 580, 593, 597, 608, 612, 626, 643, 646, 656, 667, 673, 681, 692, 700, 712, 728, 742, 753, 763, 778, 786, 797, 807, 814, 823, 833, 837, 840, 847, 852, 863, 870, 877, 885, 888, 894, 899, 908, 915, 923, 927, 930, 936, 943, 956, 961, 963, 970, 977, 983, 987, 996, 1000, 1005, 1011, 1017, 1023, 1033, 1036, 1052, 1056, 1065, 1068, 1077, 1092, 1105, 1111, 1125, 1132, 1135, 1140, 1146, 1149, 1152, 1164, 1171, 1178, 1192, 1202, 1214, 1221, 1240, 1243, 1247, 1251, 1255, 1260, 1265, 1270, 1275, 1289, 1300, 1306, 1309, 1314, 1323, 1327, 1332, 1337, 1343, 1350, 1355, 1358, 1367, 1383, 1386, 1392, 1401, 1410, 1424, 1434, 1442, 1446, 1455, 1459, 1471, 1474, 1484, 1487, 1494, 1502, 1509, 1512, 1519, 1522, 1527, 1533, 1541, 1547, 1553, 1561, 1566, 1573, 1580, 1588, 1595, 1600, 1605, 1612, 1616, 1619, 1621, 1625, 1628, 1633, 1638, 1643, 1647, 1650, 1652, 1656, 1660, 1664, 1670, 1673, 1676, 1679, 1702, 1728, 1757, 1787, 1793}
+var _FeatureID_index = [...]uint16{0, 7, 10, 15, 23, 34, 41, 48, 55, 61, 68, 75, 85, 97, 102, 105, 110, 119, 128, 137, 141, 151, 163, 172, 180, 188, 196, 204, 211, 221, 231, 239, 249, 260, 268, 278, 296, 311, 318, 330, 337, 344, 355, 367, 375, 379, 383, 389, 394, 402, 407, 413, 417, 426, 444, 452, 459, 463, 467, 481, 487, 491, 495, 504, 508, 512, 517, 522, 526, 530, 534, 541, 545, 548, 554, 557, 560, 570, 580, 593, 606, 610, 621, 625, 639, 656, 659, 669, 680, 686, 694, 705, 713, 725, 741, 755, 766, 776, 791, 799, 810, 820, 827, 836, 846, 850, 853, 860, 865, 876, 883, 890, 898, 901, 907, 912, 921, 928, 936, 940, 943, 949, 956, 969, 974, 976, 983, 990, 996, 1000, 1009, 1013, 1018, 1024, 1030, 1036, 1046, 1049, 1065, 1069, 1078, 1081, 1090, 1105, 1118, 1124, 1138, 1145, 1148, 1153, 1159, 1162, 1165, 1177, 1184, 1191, 1205, 1215, 1227, 1234, 1253, 1256, 1260, 1264, 1268, 1273, 1278, 1283, 1288, 1302, 1313, 1319, 1322, 1327, 1336, 1340, 1345, 1350, 1356, 1363, 1368, 1371, 1380, 1396, 1399, 1405, 1414, 1423, 1437, 1447, 1455, 1459, 1468, 1472, 1484, 1487, 1497, 1500, 1507, 1515, 1522, 1525, 1532, 1535, 1540, 1546, 1554, 1560, 1566, 1574, 1579, 1586, 1593, 1601, 1608, 1613, 1618, 1625, 1629, 1632, 1634, 1638, 1641, 1646, 1651, 1656, 1660, 1663, 1665, 1669, 1673, 1677, 1683, 1686, 1689, 1692, 1696, 1698, 1702, 1705, 1711, 1718, 1724, 1728, 1732, 1736, 1740, 1743, 1747, 1770, 1796, 1825, 1855, 1861, 1865, 1869, 1873, 1877, 1883, 1889, 1895, 1901, 1910, 1924, 1933, 1942, 1951, 1957, 1963, 1972, 1979, 1987, 1994, 2001, 2008, 2015, 2022, 2029, 2037, 2044, 2050, 2056, 2062, 2069, 2076, 2083, 2090, 2099, 2108, 2117, 2126, 2134, 2141, 2149, 2157, 2163}
 
 func (i FeatureID) String() string {
-	if i < 0 || i >= FeatureID(len(_FeatureID_index)-1) {
+	idx := int(i) - 0
+	if i < 0 || idx >= len(_FeatureID_index)-1 {
 		return "FeatureID(" + strconv.FormatInt(int64(i), 10) + ")"
 	}
-	return _FeatureID_name[_FeatureID_index[i]:_FeatureID_index[i+1]]
+	return _FeatureID_name[_FeatureID_index[idx]:_FeatureID_index[idx+1]]
 }
 func _() {
 	// An "invalid array index" compiler error signifies that the constant values have changed.
@@ -293,16 +351,22 @@ func _() {
 	_ = x[ACRN-28]
 	_ = x[SRE-29]
 	_ = x[Apple-30]
-	_ = x[lastVendor-31]
+	_ = x[SiFive-31]
+	_ = x[StarFive-32]
+	_ = x[THead-33]
+	_ = x[Andes-34]
+	_ = x[SpacemiT-35]
+	_ = x[lastVendor-36]
 }
 
-const _Vendor_name = "VendorUnknownIntelAMDVIATransmetaNSCKVMMSVMVMwareXenHVMBhyveHygonSiSRDCAmpereARMBroadcomCaviumDECFujitsuInfineonMotorolaNVIDIAAMCCQualcommMarvellQEMUQNXACRNSREApplelastVendor"
+const _Vendor_name = "VendorUnknownIntelAMDVIATransmetaNSCKVMMSVMVMwareXenHVMBhyveHygonSiSRDCAmpereARMBroadcomCaviumDECFujitsuInfineonMotorolaNVIDIAAMCCQualcommMarvellQEMUQNXACRNSREAppleSiFiveStarFiveTHeadAndesSpacemiTlastVendor"
 
-var _Vendor_index = [...]uint8{0, 13, 18, 21, 24, 33, 36, 39, 43, 49, 55, 60, 65, 68, 71, 77, 80, 88, 94, 97, 104, 112, 120, 126, 130, 138, 145, 149, 152, 156, 159, 164, 174}
+var _Vendor_index = [...]uint8{0, 13, 18, 21, 24, 33, 36, 39, 43, 49, 55, 60, 65, 68, 71, 77, 80, 88, 94, 97, 104, 112, 120, 126, 130, 138, 145, 149, 152, 156, 159, 164, 170, 178, 183, 188, 196, 206}
 
 func (i Vendor) String() string {
-	if i < 0 || i >= Vendor(len(_Vendor_index)-1) {
+	idx := int(i) - 0
+	if i < 0 || idx >= len(_Vendor_index)-1 {
 		return "Vendor(" + strconv.FormatInt(int64(i), 10) + ")"
 	}
-	return _Vendor_name[_Vendor_index[i]:_Vendor_index[i+1]]
+	return _Vendor_name[_Vendor_index[idx]:_Vendor_index[idx+1]]
 }
diff --git a/vendor/github.com/klauspost/cpuid/v2/os_darwin_arm64.go b/vendor/github.com/klauspost/cpuid/v2/os_darwin_arm64.go
index da07522e7cb..addbfc67b8e 100644
--- a/vendor/github.com/klauspost/cpuid/v2/os_darwin_arm64.go
+++ b/vendor/github.com/klauspost/cpuid/v2/os_darwin_arm64.go
@@ -126,4 +126,17 @@ func tryToFillCPUInfoFomSysctl(c *CPUInfo) {
 	setFeature(c, SM3, "hw.optional.arm.FEAT_SM3")                                      // SM3 instructions
 	setFeature(c, SM4, "hw.optional.arm.FEAT_SM4")                                      // SM4 instructions
 	setFeature(c, SVE, "hw.optional.arm.FEAT_SVE")                                      // Scalable Vector Extension
+	setFeature(c, SVE2, "hw.optional.arm.FEAT_SVE2")                                    // Scalable Vector Extension 2
+	setFeature(c, SB, "hw.optional.arm.FEAT_SB")                                        // Speculation barrier
+	setFeature(c, SSBS, "hw.optional.arm.FEAT_SSBS")                                    // Speculative Store Bypass Safe
+	setFeature(c, BTI, "hw.optional.arm.FEAT_BTI")                                      // Branch Target Identification
+	setFeature(c, FLAGM2, "hw.optional.arm.FEAT_FlagM2")                                // Condition flag manipulation version 2
+	setFeature(c, FRINTTS, "hw.optional.arm.FEAT_FRINTTS")                              // Floating-point to integer rounding
+	setFeature(c, DCPODP, "hw.optional.arm.FEAT_DPB2")                                  // Data cache clean to Point of Deep Persistence
+	setFeature(c, BF16, "hw.optional.arm.FEAT_BF16")                                    // BFloat16 instructions
+	setFeature(c, I8MM, "hw.optional.arm.FEAT_I8MM")                                    // Int8 matrix multiplication
+	setFeature(c, WFXT, "hw.optional.arm.FEAT_WFxT")                                    // WFE/WFI with timeout
+	setFeature(c, MOPS, "hw.optional.arm.FEAT_MOPS")                                    // Memory copy and set instructions
+	setFeature(c, HBC, "hw.optional.arm.FEAT_HBC")                                      // Hinted conditional branches
+	setFeature(c, CSSC, "hw.optional.arm.FEAT_CSSC")                                    // Common short sequence compression
 }
diff --git a/vendor/github.com/klauspost/cpuid/v2/os_linux_arm64.go b/vendor/github.com/klauspost/cpuid/v2/os_linux_arm64.go
index d96d24438b3..ea9da404c67 100644
--- a/vendor/github.com/klauspost/cpuid/v2/os_linux_arm64.go
+++ b/vendor/github.com/klauspost/cpuid/v2/os_linux_arm64.go
@@ -115,15 +115,19 @@ const (
 	hwcap2_POE         = 1 << 63
 )
 
+// hwcap2 holds AT_HWCAP2. Unlike hwcap, the arm64 runtime does not expose it
+// through internal/cpu, so detectOS reads it from the auxiliary vector.
+var hwcap2 uint
+
 func detectOS(c *CPUInfo) bool {
 	// For now assuming no hyperthreading is reasonable.
 	c.LogicalCores = runtime.NumCPU()
 	c.PhysicalCores = c.LogicalCores
 	c.ThreadsPerCore = 1
-	if hwcap == 0 {
-		// We did not get values from the runtime.
-		// Try reading /proc/self/auxv
-
+	// hwcap is provided by the runtime through the internal/cpu.HWCap linkname,
+	// but the runtime does not expose HWCAP2 on arm64. Read the auxiliary vector
+	// directly to obtain hwcap2 (and hwcap when the linkname is unavailable).
+	if hwcap == 0 || hwcap2 == 0 {
 		// From https://github.com/golang/sys
 		const (
 			_AT_HWCAP  = 16
@@ -132,37 +136,34 @@ func detectOS(c *CPUInfo) bool {
 			uintSize = int(32 << (^uint(0) >> 63))
 		)
 
-		buf, err := ioutil.ReadFile("/proc/self/auxv")
-		if err != nil {
-			// e.g. on android /proc/self/auxv is not accessible, so silently
-			// ignore the error and leave Initialized = false. On some
-			// architectures (e.g. arm64) doinit() implements a fallback
-			// readout and will set Initialized = true again.
-			return false
-		}
-		bo := binary.LittleEndian
-		for len(buf) >= 2*(uintSize/8) {
-			var tag, val uint
-			switch uintSize {
-			case 32:
-				tag = uint(bo.Uint32(buf[0:]))
-				val = uint(bo.Uint32(buf[4:]))
-				buf = buf[8:]
-			case 64:
-				tag = uint(bo.Uint64(buf[0:]))
-				val = uint(bo.Uint64(buf[8:]))
-				buf = buf[16:]
-			}
-			switch tag {
-			case _AT_HWCAP:
-				hwcap = val
-			case _AT_HWCAP2:
-				// Not used
+		// e.g. on android /proc/self/auxv is not accessible, so silently ignore
+		// the error and fall back to whatever the runtime provided.
+		if buf, err := ioutil.ReadFile("/proc/self/auxv"); err == nil {
+			bo := binary.LittleEndian
+			for len(buf) >= 2*(uintSize/8) {
+				var tag, val uint
+				switch uintSize {
+				case 32:
+					tag = uint(bo.Uint32(buf[0:]))
+					val = uint(bo.Uint32(buf[4:]))
+					buf = buf[8:]
+				case 64:
+					tag = uint(bo.Uint64(buf[0:]))
+					val = uint(bo.Uint64(buf[8:]))
+					buf = buf[16:]
+				}
+				switch tag {
+				case _AT_HWCAP:
+					hwcap = val
+				case _AT_HWCAP2:
+					hwcap2 = val
+				}
 			}
 		}
-		if hwcap == 0 {
-			return false
-		}
+	}
+	if hwcap == 0 {
+		// Nothing detected, e.g. on android or a restricted environment.
+		return false
 	}
 
 	// HWCap was populated by the runtime from the auxiliary vector.
@@ -184,9 +185,9 @@ func detectOS(c *CPUInfo) bool {
 	c.featureSet.setIf(isSet(hwcap, hwcap_JSCVT), JSCVT)
 	c.featureSet.setIf(isSet(hwcap, hwcap_LRCPC), LRCPC)
 	c.featureSet.setIf(isSet(hwcap, hwcap_PMULL), PMULL)
-	c.featureSet.setIf(isSet(hwcap, hwcap2_RNG), RNDR)
-	// c.featureSet.setIf(isSet(hwcap, hwcap_), TLB)
-	// c.featureSet.setIf(isSet(hwcap, hwcap_), TS)
+	c.featureSet.setIf(isSet(hwcap2, hwcap2_RNG), RNDR)
+	// TLB (FEAT_TLBIOS/TLBIRANGE) has no HWCAP bit; only detectable via ID registers.
+	c.featureSet.setIf(isSet(hwcap, hwcap_FLAGM), TS)
 	c.featureSet.setIf(isSet(hwcap, hwcap_SHA1), SHA1)
 	c.featureSet.setIf(isSet(hwcap, hwcap_SHA2), SHA2)
 	c.featureSet.setIf(isSet(hwcap, hwcap_SHA3), SHA3)
@@ -194,6 +195,21 @@ func detectOS(c *CPUInfo) bool {
 	c.featureSet.setIf(isSet(hwcap, hwcap_SM3), SM3)
 	c.featureSet.setIf(isSet(hwcap, hwcap_SM4), SM4)
 	c.featureSet.setIf(isSet(hwcap, hwcap_SVE), SVE)
+	c.featureSet.setIf(isSet(hwcap, hwcap_SB), SB)
+	c.featureSet.setIf(isSet(hwcap, hwcap_SSBS), SSBS)
+
+	// Features reported through the second hardware capability word (HWCAP2).
+	c.featureSet.setIf(isSet(hwcap2, hwcap2_SVE2), SVE2)
+	c.featureSet.setIf(isSet(hwcap2, hwcap2_BTI), BTI)
+	c.featureSet.setIf(isSet(hwcap2, hwcap2_FLAGM2), FLAGM2)
+	c.featureSet.setIf(isSet(hwcap2, hwcap2_FRINT), FRINTTS)
+	c.featureSet.setIf(isSet(hwcap2, hwcap2_DCPODP), DCPODP)
+	c.featureSet.setIf(isSet(hwcap2, hwcap2_BF16), BF16)
+	c.featureSet.setIf(isSet(hwcap2, hwcap2_I8MM), I8MM)
+	c.featureSet.setIf(isSet(hwcap2, hwcap2_WFXT), WFXT)
+	c.featureSet.setIf(isSet(hwcap2, hwcap2_MOPS), MOPS)
+	c.featureSet.setIf(isSet(hwcap2, hwcap2_HBC), HBC)
+	c.featureSet.setIf(isSet(hwcap2, hwcap2_CSSC), CSSC)
 
 	// The Samsung S9+ kernel reports support for atomics, but not all cores
 	// actually support them, resulting in SIGILL. See issue #28431.
diff --git a/vendor/github.com/klauspost/cpuid/v2/os_linux_riscv64.go b/vendor/github.com/klauspost/cpuid/v2/os_linux_riscv64.go
new file mode 100644
index 00000000000..71919a49bd6
--- /dev/null
+++ b/vendor/github.com/klauspost/cpuid/v2/os_linux_riscv64.go
@@ -0,0 +1,225 @@
+// Copyright (c) 2026 Klaus Post, released under MIT License. See LICENSE file.
+
+package cpuid
+
+import (
+	"bufio"
+	"os"
+	"runtime"
+	"strconv"
+	"strings"
+	"unsafe"
+
+	"golang.org/x/sys/unix"
+)
+
+const __NR_riscv_hwprobe = 258
+
+type riscvHWProbePair struct {
+	key   int64
+	value uint64
+}
+
+// Keys from linux/include/uapi/asm/hwprobe.h
+const (
+	riscv_hwprobe_key_mvendorid         = 0
+	riscv_hwprobe_key_marchid           = 1
+	riscv_hwprobe_key_mimpid            = 2
+	riscv_hwprobe_key_base_behavior     = 3
+	riscv_hwprobe_key_ima_ext_0         = 4
+	riscv_hwprobe_key_cpuperf_0         = 5
+	riscv_hwprobe_key_zicbom_block_size = 12
+)
+
+// Bits from linux/arch/riscv/include/uapi/asm/hwprobe.h
+const (
+	riscv_hwprobe_ima_fd          = 1 << 0
+	riscv_hwprobe_ima_c           = 1 << 1
+	riscv_hwprobe_ima_v           = 1 << 2
+	riscv_hwprobe_ext_zba         = 1 << 3
+	riscv_hwprobe_ext_zbb         = 1 << 4
+	riscv_hwprobe_ext_zbs         = 1 << 5
+	riscv_hwprobe_ext_zicboz      = 1 << 6
+	riscv_hwprobe_ext_zbc         = 1 << 7
+	riscv_hwprobe_ext_zbkb        = 1 << 8
+	riscv_hwprobe_ext_zbkc        = 1 << 9
+	riscv_hwprobe_ext_zbkx        = 1 << 10
+	riscv_hwprobe_ext_zknd        = 1 << 11
+	riscv_hwprobe_ext_zkne        = 1 << 12
+	riscv_hwprobe_ext_zknh        = 1 << 13
+	riscv_hwprobe_ext_zksed       = 1 << 14
+	riscv_hwprobe_ext_zksh        = 1 << 15
+	riscv_hwprobe_ext_zkt         = 1 << 16
+	riscv_hwprobe_ext_zvbb        = 1 << 17
+	riscv_hwprobe_ext_zvbc        = 1 << 18
+	riscv_hwprobe_ext_zvkb        = 1 << 19
+	riscv_hwprobe_ext_zvkg        = 1 << 20
+	riscv_hwprobe_ext_zvkned      = 1 << 21
+	riscv_hwprobe_ext_zvknha      = 1 << 22
+	riscv_hwprobe_ext_zvknhb      = 1 << 23
+	riscv_hwprobe_ext_zvksed      = 1 << 24
+	riscv_hwprobe_ext_zvksh       = 1 << 25
+	riscv_hwprobe_ext_zvkt        = 1 << 26
+	riscv_hwprobe_ext_zfh         = 1 << 27
+	riscv_hwprobe_ext_zfhmin      = 1 << 28
+	riscv_hwprobe_ext_zihintntl   = 1 << 29
+	riscv_hwprobe_ext_zvfh        = 1 << 30
+	riscv_hwprobe_ext_zvfhmin     = 1 << 31
+	riscv_hwprobe_ext_zfa         = 1 << 32
+	riscv_hwprobe_ext_ztso        = 1 << 33
+	riscv_hwprobe_ext_zacas       = 1 << 34
+	riscv_hwprobe_ext_zicond      = 1 << 35
+	riscv_hwprobe_ext_zihintpause = 1 << 36
+	riscv_hwprobe_ext_zicbom      = 1 << 55
+	riscv_hwprobe_ext_zicbop      = 1 << 60
+)
+
+func riscvHWProbe(pairs []riscvHWProbePair) int64 {
+	if len(pairs) == 0 {
+		return -1
+	}
+	ret, _, _ := unix.Syscall6(__NR_riscv_hwprobe,
+		uintptr(unsafe.Pointer(&pairs[0])),
+		uintptr(len(pairs)),
+		0, 0, 0, 0)
+	return int64(ret)
+}
+
+func detectOS(c *CPUInfo) bool {
+	c.LogicalCores = runtime.NumCPU()
+	c.PhysicalCores = c.LogicalCores
+	c.ThreadsPerCore = 1
+
+	pairs := []riscvHWProbePair{
+		{key: riscv_hwprobe_key_mvendorid},
+		{key: riscv_hwprobe_key_marchid},
+		{key: riscv_hwprobe_key_mimpid},
+		{key: riscv_hwprobe_key_ima_ext_0},
+		{key: riscv_hwprobe_key_zicbom_block_size},
+	}
+	ret := riscvHWProbe(pairs)
+	if ret == 0 && pairs[3].value != ^uint64(0) {
+		detectFromHWProbe(c, pairs)
+		if pairs[4].value != ^uint64(0) && pairs[4].value > 0 {
+			c.CacheLine = int(pairs[4].value)
+		}
+		return true
+	}
+
+	c.CacheLine = detectCacheLine()
+	return detectFromCPUInfo(c)
+}
+
+func detectFromHWProbe(c *CPUInfo, pairs []riscvHWProbePair) {
+	if pairs[0].value != ^uint64(0) {
+		c.VendorID = riscvVendorID(pairs[0].value)
+		c.VendorString = c.VendorID.String()
+	}
+	if pairs[1].value != ^uint64(0) {
+		c.Model = int(pairs[1].value)
+	}
+	if pairs[2].value != ^uint64(0) {
+		c.Family = int(pairs[2].value)
+	}
+
+	imaExt := pairs[3].value
+
+	if imaExt&riscv_hwprobe_ima_fd != 0 {
+		c.featureSet.set(RV_D)
+		c.featureSet.set(RV_F)
+	}
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ima_c != 0, RV_C)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ima_v != 0, RV_V)
+
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zba != 0, RV_ZBA)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zbb != 0, RV_ZBB)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zbc != 0, RV_ZBC)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zbs != 0, RV_ZBS)
+
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zicbom != 0, RV_ZICBOM)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zicboz != 0, RV_ZICBOZ)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zicbop != 0, RV_ZICBOP)
+
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zicond != 0, RV_ZICOND)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zihintpause != 0, RV_ZIHINTPAUSE)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zfa != 0, RV_ZFA)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zfh != 0, RV_ZFH)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zfhmin != 0, RV_ZFHMIN)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_ztso != 0, RV_ZTSO)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zacas != 0, RV_ZACAS)
+
+	// Scalar cryptography
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zbkb != 0, RV_ZBKB)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zbkc != 0, RV_ZBKC)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zbkx != 0, RV_ZBKX)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zknd != 0, RV_ZKND)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zkne != 0, RV_ZKNE)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zknh != 0, RV_ZKNH)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zksed != 0, RV_ZKSED)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zksh != 0, RV_ZKSH)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zkt != 0, RV_ZKT)
+
+	// Vector cryptography
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zvbb != 0, RV_ZVBB)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zvbc != 0, RV_ZVBC)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zvkb != 0, RV_ZVKB)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zvkg != 0, RV_ZVKG)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zvkned != 0, RV_ZVKNED)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zvknha != 0, RV_ZVKNHA)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zvknhb != 0, RV_ZVKNHB)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zvksed != 0, RV_ZVKSED)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zvksh != 0, RV_ZVKSH)
+	c.featureSet.setIf(imaExt&riscv_hwprobe_ext_zvkt != 0, RV_ZVKT)
+
+	// Crypto suites (combined from individual features)
+	c.featureSet.setIf(c.featureSet.hasSetP(rvZKNFeatures), RV_ZKN)
+	c.featureSet.setIf(c.featureSet.hasSetP(rvZKSFeatures), RV_ZKS)
+	c.featureSet.setIf(c.featureSet.hasSetP(rvZVKNFeatures), RV_ZVKNG)
+	c.featureSet.setIf(c.featureSet.hasSetP(rvZVKSFeatures), RV_ZVKSG)
+
+	// Every Linux-capable riscv64 core has I, M, A base.
+	c.featureSet.set(RV_IMA)
+}
+
+func detectFromCPUInfo(c *CPUInfo) bool {
+	f, err := os.Open("/proc/cpuinfo")
+	if err != nil {
+		return false
+	}
+	defer f.Close()
+
+	scanner := bufio.NewScanner(f)
+	for scanner.Scan() {
+		line := scanner.Text()
+		fields := strings.SplitN(line, ":", 2)
+		if len(fields) < 2 {
+			continue
+		}
+		key := strings.TrimSpace(fields[0])
+		value := strings.TrimSpace(fields[1])
+
+		switch key {
+		case "isa":
+			parseISAString(c, value)
+		case "mvendorid":
+			if vid, err := strconv.ParseUint(value, 0, 64); err == nil {
+				c.VendorID = riscvVendorID(vid)
+				c.VendorString = c.VendorID.String()
+			}
+		case "uarch":
+			c.BrandName = value
+		}
+	}
+	return scanner.Err() == nil
+}
+
+func detectCacheLine() int {
+	data, err := os.ReadFile("/sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size")
+	if err != nil {
+		return 0
+	}
+	if n, err := strconv.Atoi(strings.TrimSpace(string(data))); err == nil && n > 0 {
+		return n
+	}
+	return 0
+}
diff --git a/vendor/github.com/klauspost/cpuid/v2/os_other_arm64.go b/vendor/github.com/klauspost/cpuid/v2/os_other_arm64.go
index 8733ba34363..debc123922e 100644
--- a/vendor/github.com/klauspost/cpuid/v2/os_other_arm64.go
+++ b/vendor/github.com/klauspost/cpuid/v2/os_other_arm64.go
@@ -1,7 +1,6 @@
 // Copyright (c) 2020 Klaus Post, released under MIT License. See LICENSE file.
 
 //go:build arm64 && !linux && !darwin
-// +build arm64,!linux,!darwin
 
 package cpuid
 
diff --git a/vendor/github.com/klauspost/cpuid/v2/os_other_riscv64.go b/vendor/github.com/klauspost/cpuid/v2/os_other_riscv64.go
new file mode 100644
index 00000000000..fd86f7d0562
--- /dev/null
+++ b/vendor/github.com/klauspost/cpuid/v2/os_other_riscv64.go
@@ -0,0 +1,14 @@
+// Copyright (c) 2026 Klaus Post, released under MIT License. See LICENSE file.
+
+//go:build riscv64 && !linux
+
+package cpuid
+
+import "runtime"
+
+func detectOS(c *CPUInfo) bool {
+	c.PhysicalCores = runtime.NumCPU()
+	c.ThreadsPerCore = 1
+	c.LogicalCores = c.PhysicalCores
+	return false
+}
diff --git a/vendor/github.com/klauspost/cpuid/v2/os_safe_linux_arm64.go b/vendor/github.com/klauspost/cpuid/v2/os_safe_linux_arm64.go
index f8f201b5f7b..5b4e8a1b3e0 100644
--- a/vendor/github.com/klauspost/cpuid/v2/os_safe_linux_arm64.go
+++ b/vendor/github.com/klauspost/cpuid/v2/os_safe_linux_arm64.go
@@ -1,7 +1,6 @@
 // Copyright (c) 2021 Klaus Post, released under MIT License. See LICENSE file.
 
 //go:build nounsafe
-// +build nounsafe
 
 package cpuid
 
diff --git a/vendor/github.com/klauspost/cpuid/v2/os_unsafe_linux_arm64.go b/vendor/github.com/klauspost/cpuid/v2/os_unsafe_linux_arm64.go
index 92af622eb8c..00158c21c39 100644
--- a/vendor/github.com/klauspost/cpuid/v2/os_unsafe_linux_arm64.go
+++ b/vendor/github.com/klauspost/cpuid/v2/os_unsafe_linux_arm64.go
@@ -1,7 +1,6 @@
 // Copyright (c) 2021 Klaus Post, released under MIT License. See LICENSE file.
 
 //go:build !nounsafe
-// +build !nounsafe
 
 package cpuid
 
diff --git a/vendor/github.com/klauspost/cpuid/v2/riscv_isa.go b/vendor/github.com/klauspost/cpuid/v2/riscv_isa.go
new file mode 100644
index 00000000000..5a87679bdbd
--- /dev/null
+++ b/vendor/github.com/klauspost/cpuid/v2/riscv_isa.go
@@ -0,0 +1,93 @@
+// Copyright (c) 2026 Klaus Post, released under MIT License. See LICENSE file.
+
+package cpuid
+
+import "strings"
+
+func parseISAString(c *CPUInfo, isa string) {
+	isa = strings.ToLower(isa)
+	extMap := make(map[string]bool)
+	for ext := range strings.SplitSeq(isa, "_") {
+		ext = strings.TrimSpace(ext)
+		if strings.HasPrefix(ext, "rv64") {
+			extMap["i"] = true
+			for _, ch := range ext[4:] {
+				extMap[string(ch)] = true
+			}
+		} else if ext != "" {
+			extMap[ext] = true
+		}
+	}
+
+	if extMap["g"] {
+		extMap["i"] = true
+		extMap["m"] = true
+		extMap["a"] = true
+		extMap["f"] = true
+		extMap["d"] = true
+	}
+
+	c.featureSet.setIf(extMap["i"] && extMap["m"] && extMap["a"], RV_IMA)
+	c.featureSet.setIf(extMap["c"], RV_C)
+	c.featureSet.setIf(extMap["f"], RV_F)
+	c.featureSet.setIf(extMap["d"], RV_D)
+	c.featureSet.setIf(extMap["v"], RV_V)
+	c.featureSet.setIf(extMap["zihintpause"], RV_ZIHINTPAUSE)
+	c.featureSet.setIf(extMap["zba"], RV_ZBA)
+	c.featureSet.setIf(extMap["zbb"], RV_ZBB)
+	c.featureSet.setIf(extMap["zbc"], RV_ZBC)
+	c.featureSet.setIf(extMap["zbs"], RV_ZBS)
+	c.featureSet.setIf(extMap["zicond"], RV_ZICOND)
+	c.featureSet.setIf(extMap["zicbom"], RV_ZICBOM)
+	c.featureSet.setIf(extMap["zicboz"], RV_ZICBOZ)
+	c.featureSet.setIf(extMap["zicbop"], RV_ZICBOP)
+	c.featureSet.setIf(extMap["zfa"], RV_ZFA)
+	c.featureSet.setIf(extMap["zfh"], RV_ZFH)
+	c.featureSet.setIf(extMap["zfhmin"], RV_ZFHMIN)
+	c.featureSet.setIf(extMap["ztso"], RV_ZTSO)
+	c.featureSet.setIf(extMap["zacas"], RV_ZACAS)
+
+	// Scalar cryptography
+	c.featureSet.setIf(extMap["zbkb"], RV_ZBKB)
+	c.featureSet.setIf(extMap["zbkc"], RV_ZBKC)
+	c.featureSet.setIf(extMap["zbkx"], RV_ZBKX)
+	c.featureSet.setIf(extMap["zknd"], RV_ZKND)
+	c.featureSet.setIf(extMap["zkne"], RV_ZKNE)
+	c.featureSet.setIf(extMap["zknh"], RV_ZKNH)
+	c.featureSet.setIf(extMap["zksed"], RV_ZKSED)
+	c.featureSet.setIf(extMap["zksh"], RV_ZKSH)
+	c.featureSet.setIf(extMap["zkt"], RV_ZKT)
+
+	// Vector cryptography
+	c.featureSet.setIf(extMap["zvbb"], RV_ZVBB)
+	c.featureSet.setIf(extMap["zvbc"], RV_ZVBC)
+	c.featureSet.setIf(extMap["zvkb"], RV_ZVKB)
+	c.featureSet.setIf(extMap["zvkg"], RV_ZVKG)
+	c.featureSet.setIf(extMap["zvkned"], RV_ZVKNED)
+	c.featureSet.setIf(extMap["zvknha"], RV_ZVKNHA)
+	c.featureSet.setIf(extMap["zvknhb"], RV_ZVKNHB)
+	c.featureSet.setIf(extMap["zvksed"], RV_ZVKSED)
+	c.featureSet.setIf(extMap["zvksh"], RV_ZVKSH)
+	c.featureSet.setIf(extMap["zvkt"], RV_ZVKT)
+
+	// Crypto suites (combined from individual features or bundle tokens)
+	c.featureSet.setIf(extMap["zkn"] || c.featureSet.hasSetP(rvZKNFeatures), RV_ZKN)
+	c.featureSet.setIf(extMap["zks"] || c.featureSet.hasSetP(rvZKSFeatures), RV_ZKS)
+	c.featureSet.setIf(extMap["zvkng"] || c.featureSet.hasSetP(rvZVKNFeatures), RV_ZVKNG)
+	c.featureSet.setIf(extMap["zvksg"] || c.featureSet.hasSetP(rvZVKSFeatures), RV_ZVKSG)
+}
+
+var riscvVendorMap = map[uint64]Vendor{
+	0x489: SiFive,
+	0x5b7: StarFive,
+	0x5b1: THead,
+	0x31e: Andes,
+	0x710: SpacemiT,
+}
+
+func riscvVendorID(mvendorid uint64) Vendor {
+	if v, ok := riscvVendorMap[mvendorid]; ok {
+		return v
+	}
+	return VendorUnknown
+}
diff --git a/vendor/modules.txt b/vendor/modules.txt
index 523ec35231a..6158d514398 100644
--- a/vendor/modules.txt
+++ b/vendor/modules.txt
@@ -968,8 +968,8 @@ github.com/klauspost/compress/snappy
 github.com/klauspost/compress/zlib
 github.com/klauspost/compress/zstd
 github.com/klauspost/compress/zstd/internal/xxhash
-# github.com/klauspost/cpuid/v2 v2.3.0
-## explicit; go 1.22
+# github.com/klauspost/cpuid/v2 v2.4.0
+## explicit; go 1.24.0
 github.com/klauspost/cpuid/v2
 # github.com/klauspost/crc32 v1.3.0
 ## explicit; go 1.23.0