yariscv/machine.dts at main · fgssfgss/yariscv · GitHub

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/dts-v1/;
/ {
    #address-cells = <2>;
    #size-cells = <2>;
    compatible = "riscv-virtio";
    model = "yariscvemu";

    chosen {
        bootargs = "earlycon=sbi console=liteuart0 init=/init";
        linux,initrd-start = <0x82800000>;
        linux,initrd-end = <0x82c00000>;
    };

    cpus {
        #address-cells = <1>;
        #size-cells = <0>;
        timebase-frequency = <10000000>;

        cpu0: cpu@0 {
            device_type = "cpu";
            reg = <0>;
            compatible = "riscv";
            riscv,isa = "rv32imafdcsu";
            mmu-type = "riscv,sv32";
            clock-frequency = <10000000>;
            cpu0_intc: interrupt-controller {
                #address-cells = <2>;
                #interrupt-cells = <1>;
                compatible = "riscv,cpu-intc";
                interrupt-controller;
            };
        };
    };

    sram: memory@80000000 {
        device_type = "memory";
        reg = <0x0 0x80000000 0x0 0x10000000>;
    };

    soc {
        #address-cells = <2>;
        #size-cells = <2>;
        compatible = "simple-bus";
        ranges;

        clint0: clint@2000000 {
            compatible = "riscv,clint0";
            reg = <0x0 0x2000000 0x0 0xC000>;
            interrupts-extended =  <&cpu0_intc 3 &cpu0_intc 7>;
        };

        plic0: interrupt-controller@c000000 {
            #address-cells = <2>;
            #interrupt-cells = <1>;
            interrupt-controller;
            compatible = "riscv,plic0";
            reg = <0x0 0xC000000 0x0 0x4000000>;
            interrupts-extended = <&cpu0_intc 9>, <&cpu0_intc 11>;
            riscv,ndev = <1>;
            riscv,max-priority = <7>;
        };

        uart0: serial@1000000 {
            compatible = "litex,liteuart";
            device_type = "serial";
            clock-frequency = <0x384000>;
            reg = <0x0 0x1000000 0x0 0x100>;
        };

        virtio_mmio0: virtio@10001000 {
            compatible = "virtio,mmio";
            reg = <0x0 0x10001000 0x0 0x1000>;
            interrupts-extended = <&plic0 1>;
        };
    };
};