From 7e8e12af42c590a7a785fb42a19519384a6fc33a Mon Sep 17 00:00:00 2001
From: Jim Huang <jserv@ccns.ncku.edu.tw>
Date: Mon, 26 Jan 2026 16:25:24 +0800
Subject: [PATCH] Enforce consistent coding style

This applies clang-format to entire codebase:
- 4-space indentation (no tabs)
- Linux kernel brace style (functions: new line, control: same line)
- Right-aligned pointer declarations
- Consistent operator spacing

CI infrastructure:
- Add GitHub Actions workflow for automated style checking
- Add .ci/ scripts for format validation (C, shell, Python)
- Configure clang-format-20, shfmt, and black checks
---
 .ci/check-format.sh                       |  134 +
 .ci/check-newline.sh                      |   55 +
 .ci/common.sh                             |  269 ++
 .clang-format                             |   28 +
 .editorconfig                             |    9 +
 .github/workflows/coding-style.yml        |   87 +
 board/discoveryf4/board.c                 |   45 +-
 board/discoveryf4/board.h                 |   77 +-
 board/discoveryf429/board.c               |   45 +-
 board/discoveryf429/board.h               |   73 +-
 board/netduinoplus2/board.c               |   45 +-
 board/netduinoplus2/board.h               |   81 +-
 board/nucleof429/board.c                  |   49 +-
 board/nucleof429/board.h                  |   75 +-
 board/nucleof429/build.mk                 |    4 +-
 include/debug.h                           |   37 +-
 include/error.h                           |   70 +-
 include/fpage.h                           |   76 +-
 include/fpage_impl.h                      |    8 +-
 include/init_hook.h                       |   32 +-
 include/interrupt.h                       |    2 +-
 include/interrupt_ipc.h                   |   10 +-
 include/ipc.h                             |    2 +
 include/kip.h                             |    2 +-
 include/kprobes.h                         |   55 +-
 include/ksym.h                            |    4 +-
 include/ktimer.h                          |   10 +-
 include/l4/ipc.h                          |   66 +-
 include/l4/kip.h                          |    2 +-
 include/l4/kip_types.h                    |   94 +-
 include/l4/thread.h                       |   25 +-
 include/l4/utcb.h                         |   50 +-
 include/lib/bitmap.h                      |   81 +-
 include/lib/ktable.h                      |   37 +-
 include/lib/queue.h                       |   14 +-
 include/lib/stdarg.h                      |    8 +-
 include/lib/stdio.h                       |   10 +-
 include/lib/stdlib.h                      |   10 +-
 include/lib/string.h                      |    4 +-
 include/memory.h                          |  110 +-
 include/platform/armv7m.h                 |   42 +-
 include/platform/bitops.h                 |    4 +-
 include/platform/breakpoint-hard.h        |    4 +
 include/platform/breakpoint-soft.h        |    4 +
 include/platform/breakpoint.h             |   37 +-
 include/platform/cortex_m.h               |  392 ++-
 include/platform/debug_device.h           |   21 +-
 include/platform/debug_ram.h              |    2 +-
 include/platform/debug_uart.h             |   48 +-
 include/platform/hw_debug.h               |  136 +-
 include/platform/irq.h                    |  316 ++-
 include/platform/link.h                   |   26 +-
 include/platform/mpu.h                    |   30 +-
 include/platform/spinlock.h               |    2 +-
 include/platform/stm32f1/exti.h           |   26 +-
 include/platform/stm32f1/gpio.h           |   67 +-
 include/platform/stm32f1/nvic.h           |  305 ++-
 include/platform/stm32f1/nvic_private.h   |   86 +-
 include/platform/stm32f1/nvic_table.h     |    5 +-
 include/platform/stm32f1/rcc.h            |   32 +-
 include/platform/stm32f1/registers.h      | 1147 +++++---
 include/platform/stm32f1/syscfg.h         |    6 +-
 include/platform/stm32f1/systick.h        |    4 +-
 include/platform/stm32f1/usart.h          |   74 +-
 include/platform/stm32f4/exti.h           |   26 +-
 include/platform/stm32f4/gpio.h           |   68 +-
 include/platform/stm32f4/nvic.h           |  458 ++--
 include/platform/stm32f4/nvic_private.h   |  166 +-
 include/platform/stm32f4/nvic_table.h     |    5 +-
 include/platform/stm32f4/rcc.h            |   38 +-
 include/platform/stm32f4/registers.h      | 2591 +++++++++++-------
 include/platform/stm32f4/syscfg.h         |    7 +-
 include/platform/stm32f4/systick.h        |    4 +-
 include/platform/stm32f4/usart.h          |   74 +-
 include/platform/stm32f429/dma2d.h        |   80 +-
 include/platform/stm32f429/exti.h         |   26 +-
 include/platform/stm32f429/fmc.h          |  122 +-
 include/platform/stm32f429/gpio.h         |  120 +-
 include/platform/stm32f429/i2c.h          |   68 +-
 include/platform/stm32f429/ioe.h          |  152 +-
 include/platform/stm32f429/lcd.h          |   73 +-
 include/platform/stm32f429/ltdc.h         |  151 +-
 include/platform/stm32f429/nvic.h         |  454 ++--
 include/platform/stm32f429/nvic_private.h |  166 +-
 include/platform/stm32f429/nvic_table.h   |    5 +-
 include/platform/stm32f429/rcc.h          |   38 +-
 include/platform/stm32f429/registers.h    | 2990 +++++++++++++--------
 include/platform/stm32f429/sdram.h        |   30 +-
 include/platform/stm32f429/spi.h          |   36 +-
 include/platform/stm32f429/syscfg.h       |    7 +-
 include/platform/stm32f429/systick.h      |    4 +-
 include/platform/stm32f429/usart.h        |   74 +-
 include/sched.h                           |   20 +-
 include/softirq.h                         |   14 +-
 include/syscall.h                         |   24 +-
 include/thread.h                          |  108 +-
 include/types.h                           |   10 +-
 kernel/debug.c                            |   20 +-
 kernel/error.c                            |   70 +-
 kernel/fpage.c                            |  785 +++---
 kernel/init.c                             |   93 +-
 kernel/interrupt.c                        |  369 ++-
 kernel/ipc.c                              |  893 +++---
 kernel/kdb.c                              |  184 +-
 kernel/kip.c                              |    6 +-
 kernel/kprobes.c                          |  163 +-
 kernel/ksym.c                             |   77 +-
 kernel/ktimer.c                           |  532 ++--
 kernel/lib/bsearch.c                      |   37 +-
 kernel/lib/ktable.c                       |  187 +-
 kernel/lib/memcpy.c                       |  260 +-
 kernel/lib/memset.c                       |  158 +-
 kernel/lib/queue.c                        |   45 +-
 kernel/lib/sort.c                         |  106 +-
 kernel/lib/stdio.c                        |  255 +-
 kernel/lib/strcmp.c                       |    5 +-
 kernel/memory.c                           | 1105 ++++----
 kernel/sampling-kdb.c                     |   99 +-
 kernel/sampling.c                         |   80 +-
 kernel/sched.c                            |  379 +--
 kernel/softirq.c                          |   74 +-
 kernel/start.c                            |  116 +-
 kernel/syscall.c                          |  161 +-
 kernel/systhread.c                        |  148 +-
 kernel/thread.c                           |  743 +++--
 kernel/tickless-verify.c                  |  238 +-
 kernel/user-log.c                         |   20 +-
 loader/elf/elf.c                          |  272 +-
 loader/elf/elf32.c                        |  140 +-
 loader/entry.c                            |  105 +-
 loader/include/elf/elf.h                  |   67 +-
 loader/include/elf/elf32.h                |  179 +-
 platform/bitops.c                         |   99 +-
 platform/breakpoint-hard.c                |  231 +-
 platform/breakpoint-soft.c                |   40 +-
 platform/breakpoint.c                     |   70 +-
 platform/debug_device.c                   |   96 +-
 platform/debug_ram.c                      |   32 +-
 platform/debug_uart.c                     |  181 +-
 platform/hw_debug.c                       |   56 +-
 platform/irq.c                            |   32 +-
 platform/kprobes-arch.c                   |  125 +-
 platform/mpu.c                            |   16 +-
 platform/spinlock.c                       |   42 +-
 platform/stm32-common/gpio-f1.c           |  126 +-
 platform/stm32-common/gpio-f4.c           |  179 +-
 platform/stm32-common/hwtimer.c           |   10 +-
 platform/stm32-common/mpu.c               |  347 +--
 platform/stm32-common/nvic.c              |   55 +-
 platform/stm32-common/rcc.c               |  417 +--
 platform/stm32-common/systick.c           |   18 +-
 platform/stm32-common/usart.c             |  157 +-
 platform/stm32f429/dma2d.c                |  100 +-
 platform/stm32f429/fmc.c                  |  135 +-
 platform/stm32f429/i2c.c                  |  218 +-
 platform/stm32f429/ioe.c                  |  430 +--
 platform/stm32f429/lcd.c                  |  842 +++---
 platform/stm32f429/ltdc.c                 |  220 +-
 platform/stm32f429/rcc.c                  |   44 +-
 platform/stm32f429/sdram.c                |  363 +--
 platform/stm32f429/spi.c                  |   72 +-
 scripts/list_init_hooks.py                |   86 +-
 scripts/symmap.py                         |   40 +-
 user/apps/l4test/assert.c                 |   11 +-
 user/apps/l4test/assert.h                 |    2 +-
 user/apps/l4test/ipc.c                    |  386 ++-
 user/apps/l4test/l4test.h                 |   92 +-
 user/apps/l4test/main.c                   |  171 +-
 user/apps/l4test/platform/arch.h          |   10 +-
 user/apps/l4test/string.c                 |   89 +-
 user/apps/l4test/string.h                 |   12 +-
 user/apps/lcd_test/main.c                 |   66 +-
 user/apps/pingpong/main.c                 |   76 +-
 user/apps/tests/main.c                    |  127 +-
 user/apps/tests/test-fault.c              |  196 +-
 user/apps/tests/test-ipc.c                |  449 ++--
 user/apps/tests/test-irq.c                |  103 +-
 user/apps/tests/test-kip.c                |   63 +-
 user/apps/tests/test-safety.c             |  192 +-
 user/apps/tests/test-sched.c              |  188 +-
 user/apps/tests/test-thread.c             |  148 +-
 user/apps/tests/test-timer.c              |   32 +-
 user/apps/tests/tests.h                   |   84 +-
 user/include/l4/ipc.h                     |  109 +-
 user/include/l4/kdebug.h                  |    4 +-
 user/include/l4/kip.h                     |  766 +++---
 user/include/l4/message.h                 |  921 ++++---
 user/include/l4/misc.h                    |   22 +-
 user/include/l4/pagefault.h               |   46 +-
 user/include/l4/pager.h                   |   18 +-
 user/include/l4/platform/arch.h           |  527 ++--
 user/include/l4/platform/kdebug.h         |   76 +-
 user/include/l4/platform/specials.h       |   42 +-
 user/include/l4/platform/syscalls.h       |   11 +-
 user/include/l4/platform/types.h          |   20 +-
 user/include/l4/platform/vregs.h          |  330 ++-
 user/include/l4/schedule.h                |   92 +-
 user/include/l4/space.h                   |   48 +-
 user/include/l4/thread.h                  |  505 ++--
 user/include/l4/types.h                   |  574 ++--
 user/include/libposix/pthread.h           |    3 +-
 user/include/libposix/sys/types.h         |    2 +-
 user/include/libposix/unimplemented.h     |   17 +-
 user/include/user_interrupt.h             |    8 +-
 user/include/user_runtime.h               |   58 +-
 user/lib/io/l4io.c                        |   33 +-
 user/lib/io/semihost-io.c                 |  101 +-
 user/lib/io/user_interrupt.c              |  126 +-
 user/lib/l4/pager.c                       |  517 ++--
 user/lib/l4/platform/syscalls.c           |   98 +-
 user/lib/libposix/fork.c                  |    4 +-
 user/lib/libposix/pthread.c               |   72 +-
 user/root_thread.c                        |  233 +-
 213 files changed, 18232 insertions(+), 15618 deletions(-)
 create mode 100755 .ci/check-format.sh
 create mode 100755 .ci/check-newline.sh
 create mode 100644 .ci/common.sh
 create mode 100644 .clang-format
 create mode 100644 .editorconfig
 create mode 100644 .github/workflows/coding-style.yml

diff --git a/.ci/check-format.sh b/.ci/check-format.sh
new file mode 100755
index 00000000..455bf3d4
--- /dev/null
+++ b/.ci/check-format.sh
@@ -0,0 +1,134 @@
+#!/usr/bin/env bash
+# Copyright (c) 2025 The F9 Microkernel Project. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Format validation for C, shell, and Python files
+# The -e is not set because we want to collect all format mismatches at once
+
+set -u -o pipefail
+
+# In CI environment, require all formatting tools to be present
+# GitHub Actions sets CI=true automatically (also accepts CI=1, CI=yes, etc.)
+REQUIRE_TOOLS="false"
+if [ -n "${CI:-}" ]; then
+	REQUIRE_TOOLS="true"
+fi
+
+C_FORMAT_EXIT=0
+SH_FORMAT_EXIT=0
+PY_FORMAT_EXIT=0
+
+# Use git ls-files to exclude submodules and untracked files
+# F9 Microkernel structure: include/, kernel/, platform/, user/, board/, loader/
+# Exclude: externals/ (third-party code with own style)
+C_SOURCES=()
+while IFS= read -r file; do
+	[ -n "$file" ] && C_SOURCES+=("$file")
+done < <(git ls-files -- 'include/*.h' 'include/**/*.h' 'kernel/*.c' 'platform/*.c' 'platform/**/*.c' 'platform/*.h' 'platform/**/*.h' 'user/*.c' 'user/**/*.c' 'user/*.h' 'user/**/*.h' 'board/*.c' 'board/**/*.c' 'board/*.h' 'board/**/*.h' 'loader/*.c' 'loader/**/*.c' 'loader/*.h' 'loader/**/*.h' | grep -v '^externals/' || true)
+
+if [ ${#C_SOURCES[@]} -gt 0 ]; then
+	# Try clang-format with version suffix first, then generic
+	CLANG_FORMAT=""
+	for cmd in clang-format-21 clang-format-20 clang-format-19 clang-format; do
+		if command -v "$cmd" >/dev/null 2>&1; then
+			CLANG_FORMAT="$cmd"
+			break
+		fi
+	done
+
+	if [ -n "$CLANG_FORMAT" ]; then
+		echo "Checking ${#C_SOURCES[@]} C/C++ files with $CLANG_FORMAT..."
+		$CLANG_FORMAT -n --Werror "${C_SOURCES[@]}"
+		C_FORMAT_EXIT=$?
+		if [ $C_FORMAT_EXIT -eq 0 ]; then
+			echo "  ✓ All C/C++ files properly formatted"
+		else
+			echo "  ✗ C/C++ format violations found" >&2
+		fi
+	else
+		if [ "$REQUIRE_TOOLS" = "true" ]; then
+			echo "ERROR: clang-format not found (required in CI)" >&2
+			C_FORMAT_EXIT=1
+		else
+			echo "Skipping C format check: clang-format not found" >&2
+		fi
+	fi
+else
+	echo "No C/C++ files to check"
+fi
+
+SH_SOURCES=()
+while IFS= read -r file; do
+	[ -n "$file" ] && SH_SOURCES+=("$file")
+done < <(git ls-files -- '*.sh' '.ci/*.sh' 'scripts/*.sh' | grep -v '^externals/' || true)
+
+if [ ${#SH_SOURCES[@]} -gt 0 ]; then
+	if command -v shfmt >/dev/null 2>&1; then
+		echo "Checking ${#SH_SOURCES[@]} shell scripts with shfmt..."
+		MISMATCHED_SH=$(shfmt -l "${SH_SOURCES[@]}")
+		if [ -n "$MISMATCHED_SH" ]; then
+			echo "  ✗ The following shell scripts need formatting:" >&2
+			printf '    %s\n' $MISMATCHED_SH >&2
+			echo "  Run: shfmt -w \$(git ls-files '*.sh' '.ci/*.sh' 'scripts/*.sh')" >&2
+			SH_FORMAT_EXIT=1
+		else
+			echo "  ✓ All shell scripts properly formatted"
+		fi
+	else
+		if [ "$REQUIRE_TOOLS" = "true" ]; then
+			echo "ERROR: shfmt not found (required in CI)" >&2
+			SH_FORMAT_EXIT=1
+		else
+			echo "Skipping shell script format check: shfmt not found" >&2
+		fi
+	fi
+else
+	echo "No shell scripts to check"
+fi
+
+PY_SOURCES=()
+while IFS= read -r file; do
+	[ -n "$file" ] && PY_SOURCES+=("$file")
+done < <(git ls-files -- 'scripts/*.py' | grep -v '^externals/' || true)
+
+if [ ${#PY_SOURCES[@]} -gt 0 ]; then
+	if command -v black >/dev/null 2>&1; then
+		echo "Checking ${#PY_SOURCES[@]} Python files with black..."
+		black --check --quiet "${PY_SOURCES[@]}" 2>&1
+		PY_FORMAT_EXIT=$?
+		if [ $PY_FORMAT_EXIT -eq 0 ]; then
+			echo "  ✓ All Python files properly formatted"
+		else
+			echo "  ✗ Python format violations found" >&2
+			echo "  Run: black scripts/*.py" >&2
+		fi
+	else
+		if [ "$REQUIRE_TOOLS" = "true" ]; then
+			echo "ERROR: black not found (required in CI)" >&2
+			PY_FORMAT_EXIT=1
+		else
+			echo "Skipping Python format check: black not found" >&2
+		fi
+	fi
+else
+	echo "No Python files to check"
+fi
+
+# Summary
+echo ""
+echo "Format check summary:"
+echo "  C/C++:  $([ $C_FORMAT_EXIT -eq 0 ] && echo "✓ PASS" || echo "✗ FAIL")"
+echo "  Shell:  $([ $SH_FORMAT_EXIT -eq 0 ] && echo "✓ PASS" || echo "✗ FAIL")"
+echo "  Python: $([ $PY_FORMAT_EXIT -eq 0 ] && echo "✓ PASS" || echo "✗ FAIL")"
+
+# Use logical OR to avoid exit code overflow (codes are mod 256)
+if [ $C_FORMAT_EXIT -ne 0 ] || [ $SH_FORMAT_EXIT -ne 0 ] || [ $PY_FORMAT_EXIT -ne 0 ]; then
+	echo ""
+	echo "Format check FAILED"
+	exit 1
+fi
+
+echo ""
+echo "Format check PASSED"
+exit 0
diff --git a/.ci/check-newline.sh b/.ci/check-newline.sh
new file mode 100755
index 00000000..2d6a2e01
--- /dev/null
+++ b/.ci/check-newline.sh
@@ -0,0 +1,55 @@
+#!/usr/bin/env bash
+# Copyright (c) 2025 The F9 Microkernel Project. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Check all tracked text files for trailing newlines
+# Excludes: externals/ (third-party code), binary files, build artifacts
+# Reference: https://medium.com/@alexey.inkin/how-to-force-newline-at-end-of-files-and-why-you-should-do-it-fdf76d1d090e
+
+set -e -u -o pipefail
+
+ret=0
+show=0
+checked=0
+failed=0
+echo "Checking for missing trailing newlines..."
+
+while IFS= read -rd '' f; do
+	# Skip excluded directories and files
+	case "$f" in
+	externals/*) continue ;;                   # Third-party code
+	.config | .config.* | build/*) continue ;; # Build artifacts
+	*.bin | *.elf | *.o | *.a) continue ;;     # Binaries
+	esac
+
+	# Skip empty files (e.g., __init__.py markers)
+	[ -s "$f" ] || continue
+
+	# Only check text files
+	if file --mime-encoding "$f" | grep -qv binary; then
+		checked=$((checked + 1))
+		tail -c1 <"$f" | read -r _ || show=1
+		if [ $show -eq 1 ]; then
+			echo "  ✗ Missing newline: $f" >&2
+			failed=$((failed + 1))
+			ret=1
+			show=0
+		fi
+	fi
+done < <(git ls-files -z)
+
+# Summary
+echo ""
+echo "Newline check summary:"
+echo "  Files checked: $checked"
+if [ $ret -eq 0 ]; then
+	echo "  Result: ✓ PASS - All files end with newline"
+else
+	echo "  Files failed: $failed"
+	echo "  Result: ✗ FAIL - Some files missing trailing newline" >&2
+	echo ""
+	echo "To fix: Add newline to end of each file listed above" >&2
+fi
+
+exit $ret
diff --git a/.ci/common.sh b/.ci/common.sh
new file mode 100644
index 00000000..25a18d4f
--- /dev/null
+++ b/.ci/common.sh
@@ -0,0 +1,269 @@
+#!/usr/bin/env bash
+
+# Copyright (c) 2026 The F9 Microkernel Project. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Common utilities for CI scripts
+# Can be sourced by other scripts or executed directly
+
+# Bash strict mode (enabled only when executed directly, not sourced)
+if ! (return 0 2>/dev/null); then
+	set -euo pipefail
+fi
+
+# Platform detection
+# Supported: Linux/x86_64, Linux/aarch64, macOS/arm64, macOS/x86_64
+
+MACHINE_TYPE=$(uname -m)
+OS_TYPE=$(uname -s)
+
+check_platform() {
+	case "${MACHINE_TYPE}/${OS_TYPE}" in
+	x86_64/Linux | aarch64/Linux | arm64/Darwin | x86_64/Darwin) ;;
+
+	*)
+		print_error "Unsupported platform: ${MACHINE_TYPE}/${OS_TYPE}"
+		print_error "Supported: Linux/x86_64, Linux/aarch64, macOS/arm64, macOS/x86_64"
+		exit 1
+		;;
+	esac
+}
+
+if [ "${OS_TYPE}" = "Linux" ]; then
+	PARALLEL=-j$(nproc)
+else
+	PARALLEL=-j$(sysctl -n hw.logicalcpu)
+fi
+
+# Color output helpers
+RED='\033[0;31m'
+GREEN='\033[0;32m'
+YELLOW='\033[1;33m'
+NC='\033[0m' # No Color
+
+print_success() {
+	echo -e "${GREEN}[SUCCESS]${NC} $1"
+}
+
+print_error() {
+	echo -e "${RED}[ERROR]${NC} $1" >&2
+}
+
+print_warning() {
+	echo -e "${YELLOW}[WARNING]${NC} $1"
+}
+
+# Assertion function for tests
+# Usage: ASSERT <condition> <error_message>
+ASSERT() {
+	local condition=$1
+	shift
+	local message="$*"
+
+	if ! eval "${condition}"; then
+		print_error "Assertion failed: ${message}"
+		print_error "Condition: ${condition}"
+		return 1
+	fi
+}
+
+# Cleanup function registry
+CLEANUP_FUNCS=()
+
+register_cleanup() {
+	CLEANUP_FUNCS+=("$1")
+}
+
+cleanup() {
+	local func
+	for func in "${CLEANUP_FUNCS[@]-}"; do
+		[ -n "${func}" ] || continue
+		eval "${func}" || true
+	done
+}
+
+trap cleanup EXIT
+
+# Universal download utility with curl/wget compatibility
+# Provides consistent interface regardless of which tool is available
+# Security: Enforces HTTPS and supports optional checksum verification
+
+# Detect available download tool (lazy initialization)
+detect_download_tool() {
+	if [ -n "${DOWNLOAD_TOOL:-}" ]; then
+		return 0
+	fi
+
+	if command -v curl >/dev/null 2>&1; then
+		DOWNLOAD_TOOL="curl"
+	elif command -v wget >/dev/null 2>&1; then
+		DOWNLOAD_TOOL="wget"
+	else
+		print_error "Neither curl nor wget is available"
+		return 1
+	fi
+}
+
+# Validate URL uses HTTPS (security requirement)
+# Usage: validate_url <url>
+# Returns: 0 if valid HTTPS URL, 1 otherwise
+validate_url() {
+	local url="$1"
+	case "$url" in
+	https://*)
+		return 0
+		;;
+	http://*)
+		print_error "HTTP URLs are not allowed for security reasons: $url"
+		print_error "Use HTTPS instead"
+		return 1
+		;;
+	*)
+		print_error "Invalid URL scheme (must be HTTPS): $url"
+		return 1
+		;;
+	esac
+}
+
+# Verify file checksum
+# Usage: verify_checksum <file> <expected_sha256>
+# Returns: 0 if checksum matches, 1 otherwise
+verify_checksum() {
+	local file="$1"
+	local expected="$2"
+
+	if [ -z "$expected" ]; then
+		return 0 # No checksum provided, skip verification
+	fi
+
+	local actual
+	if command -v sha256sum >/dev/null 2>&1; then
+		actual=$(sha256sum "$file" | cut -d' ' -f1)
+	elif command -v shasum >/dev/null 2>&1; then
+		actual=$(shasum -a 256 "$file" | cut -d' ' -f1)
+	else
+		print_warning "No SHA256 tool available, skipping checksum verification"
+		return 0
+	fi
+
+	if [ "$actual" != "$expected" ]; then
+		print_error "Checksum mismatch for $file"
+		print_error "Expected: $expected"
+		print_error "Actual:   $actual"
+		return 1
+	fi
+
+	return 0
+}
+
+# Download to stdout
+# Usage: download_to_stdout <url>
+download_to_stdout() {
+	detect_download_tool || return 1
+	local url="$1"
+	validate_url "$url" || return 1
+
+	case "$DOWNLOAD_TOOL" in
+	curl)
+		curl -fS --retry 5 --retry-delay 2 --retry-max-time 60 -sL "$url"
+		;;
+	wget)
+		wget -qO- "$url"
+		;;
+	esac
+}
+
+# Download to file with optional checksum verification
+# Usage: download_to_file <url> <output_file> [expected_sha256]
+download_to_file() {
+	detect_download_tool || return 1
+	local url="$1"
+	local output="$2"
+	local checksum="${3:-}"
+
+	validate_url "$url" || return 1
+
+	local download_status
+	case "$DOWNLOAD_TOOL" in
+	curl)
+		curl -fS --retry 5 --retry-delay 2 --retry-max-time 60 -sL -o "$output" "$url"
+		download_status=$?
+		;;
+	wget)
+		wget -q -O "$output" "$url"
+		download_status=$?
+		;;
+	esac
+
+	if [ $download_status -ne 0 ]; then
+		print_error "Download failed: $url"
+		return $download_status
+	fi
+
+	# Verify checksum if provided
+	if [ -n "$checksum" ]; then
+		verify_checksum "$output" "$checksum" || {
+			rm -f "$output"
+			return 1
+		}
+	fi
+
+	return 0
+}
+
+# Download silently (no progress, suitable for CI)
+# Usage: download_silent <url>
+download_silent() {
+	download_to_stdout "$@"
+}
+
+# Check if URL is accessible (HTTPS only)
+# Usage: check_url <url>
+# Returns: 0 if accessible, 1 otherwise
+check_url() {
+	detect_download_tool || return 1
+	local url="$1"
+	validate_url "$url" || return 1
+
+	case "$DOWNLOAD_TOOL" in
+	curl)
+		curl -fS --retry 5 --retry-delay 2 --retry-max-time 60 -sL --head "$url" >/dev/null 2>&1
+		;;
+	wget)
+		wget --spider -q "$url" 2>/dev/null
+		;;
+	esac
+}
+
+# F9 Microkernel specific utilities
+
+# Get project root directory (location of .config file)
+get_project_root() {
+	local dir="$PWD"
+	while [ "$dir" != "/" ]; do
+		if [ -f "$dir/.config" ] || [ -f "$dir/Makefile" ]; then
+			echo "$dir"
+			return 0
+		fi
+		dir=$(dirname "$dir")
+	done
+	print_error "Not in F9 Microkernel project directory"
+	return 1
+}
+
+# Check if running in git repository
+is_git_repo() {
+	git rev-parse --git-dir >/dev/null 2>&1
+}
+
+# Get current git branch name
+get_git_branch() {
+	git rev-parse --abbrev-ref HEAD 2>/dev/null
+}
+
+# Count files matching pattern
+count_files() {
+	local pattern="$1"
+	find . -name "$pattern" -type f | wc -l | tr -d ' '
+}
diff --git a/.clang-format b/.clang-format
new file mode 100644
index 00000000..b5217340
--- /dev/null
+++ b/.clang-format
@@ -0,0 +1,28 @@
+BasedOnStyle: Chromium
+Language: Cpp
+MaxEmptyLinesToKeep: 3
+IndentCaseLabels: false
+AllowShortIfStatementsOnASingleLine: false
+AllowShortCaseLabelsOnASingleLine: false
+AllowShortLoopsOnASingleLine: false
+DerivePointerAlignment: false
+PointerAlignment: Right
+SpaceAfterCStyleCast: true
+TabWidth: 4
+UseTab: Never
+IndentWidth: 4
+BreakBeforeBraces: Linux
+AccessModifierOffset: -4
+ForEachMacros:
+  - for_each_in_ktable
+  - for_each_in_bitmap
+AttributeMacros:
+  - UNUSED
+  - __ALIGNED
+  - PACKED
+  - MUST_TAIL
+  - FORCE_INLINE
+StatementAttributeLikeMacros:
+  - IIF
+StatementMacros:
+  - __UNREACHABLE
diff --git a/.editorconfig b/.editorconfig
new file mode 100644
index 00000000..6b5708c0
--- /dev/null
+++ b/.editorconfig
@@ -0,0 +1,9 @@
+# Top-level EditorConfig file
+root = true
+
+# Shell script settings - use tabs (shfmt default)
+[*.sh]
+indent_style = tab
+end_of_line = lf
+trim_trailing_whitespace = true
+insert_final_newline = true
diff --git a/.github/workflows/coding-style.yml b/.github/workflows/coding-style.yml
new file mode 100644
index 00000000..bb8fa373
--- /dev/null
+++ b/.github/workflows/coding-style.yml
@@ -0,0 +1,87 @@
+name: Coding Style
+
+on:
+  push:
+    branches: [master]
+  pull_request:
+    branches: [master]
+
+permissions:
+  contents: read
+
+jobs:
+  detect-code-related-file-changes:
+    runs-on: ubuntu-24.04
+    timeout-minutes: 5
+    outputs:
+      has_code_related_changes: ${{ steps.filter.outputs.code }}
+    steps:
+      - uses: actions/checkout@v6
+      - uses: dorny/paths-filter@v3
+        id: filter
+        with:
+          filters: |
+            code:
+              - '**/*.c'
+              - '**/*.h'
+              - '**/*.sh'
+              - '**/*.py'
+              - '.clang-format'
+              - '.ci/**'
+              - '.github/workflows/**'
+
+  coding-style:
+    needs: [detect-code-related-file-changes]
+    if: needs.detect-code-related-file-changes.outputs.has_code_related_changes == 'true'
+    timeout-minutes: 10
+    runs-on: ubuntu-24.04
+
+    steps:
+      - uses: actions/checkout@v6
+
+      - name: Install formatting tools
+        run: |
+          set -euo pipefail
+
+          # Install clang-format (Ubuntu 24.04 compatible GPG key method)
+          sudo apt-get update
+          sudo apt-get install -y --no-install-recommends gnupg
+          sudo mkdir -p /etc/apt/keyrings
+
+          # Download and verify LLVM GPG key
+          curl -fsSL --retry 3 --connect-timeout 20 --proto '=https' \
+            -o /tmp/llvm-snapshot.gpg.key \
+            https://apt.llvm.org/llvm-snapshot.gpg.key
+          gpg --batch --quiet --with-colons --show-keys /tmp/llvm-snapshot.gpg.key \
+            | awk -F: '$1=="fpr"{print $10}' | grep -Fxq "6084F3CF814B57C1CF12EFD515CF4D18AF4F7421"
+
+          sudo gpg --dearmor -o /etc/apt/keyrings/llvm.gpg < /tmp/llvm-snapshot.gpg.key
+          sudo chmod 644 /etc/apt/keyrings/llvm.gpg
+          rm /tmp/llvm-snapshot.gpg.key
+
+          echo "deb [signed-by=/etc/apt/keyrings/llvm.gpg] https://apt.llvm.org/noble/ llvm-toolchain-noble-20 main" \
+            | sudo tee /etc/apt/sources.list.d/llvm.list
+          sudo apt-get update
+          sudo apt-get install -y --no-install-recommends clang-format-20 || \
+            sudo apt-get install -y --no-install-recommends clang-format-19 || \
+            sudo apt-get install -y --no-install-recommends clang-format
+
+          # Install shfmt for shell script formatting
+          SHFMT_URL="https://github.com/mvdan/sh/releases/download"
+          SHFMT_VER="v3.12.0"
+          SHFMT_SHA256="d9fbb2a9c33d13f47e7618cf362a914d029d02a6df124064fff04fd688a745ea"
+          curl -fsSL --retry 3 --connect-timeout 20 --proto '=https' \
+            -o /tmp/shfmt \
+            ${SHFMT_URL}/${SHFMT_VER}/shfmt_${SHFMT_VER}_linux_amd64
+          printf '%s  %s\n' "${SHFMT_SHA256}" /tmp/shfmt | sha256sum -c
+          chmod +x /tmp/shfmt
+          sudo mv /tmp/shfmt /usr/local/bin/shfmt
+
+          # Install black for Python formatting
+          python3 -m pip install --disable-pip-version-check --no-cache-dir black==24.10.0
+
+      - name: Check trailing newlines
+        run: .ci/check-newline.sh
+
+      - name: Check code formatting
+        run: .ci/check-format.sh
diff --git a/board/discoveryf4/board.c b/board/discoveryf4/board.c
index 4a7db186..d6434a5e 100644
--- a/board/discoveryf4/board.c
+++ b/board/discoveryf4/board.c
@@ -3,30 +3,31 @@
  * found in the LICENSE file.
  */
 
+#include "board.h"
 #include <platform/stm32f4/gpio.h>
 #include <platform/stm32f4/usart.h>
-#include "board.h"
 
 struct usart_dev console_uart = {
-	.u_num = 4,
-	.baud = 115200,
-	BOARD_USART_CONFIGS
-	.tx = {
-		.port = BOARD_USART_TX_IO_PORT,
-		.pin = BOARD_USART_TX_IO_PIN,
-		.pupd = GPIO_PUPDR_NONE,
-		.type = GPIO_MODER_ALT,
-		.func = BOARD_USART_FUNC,
-		.o_type = GPIO_OTYPER_PP,
-		.speed = GPIO_OSPEEDR_50M,
-	},
-	.rx = {
-		.port = BOARD_USART_RX_IO_PORT,
-		.pin = BOARD_USART_RX_IO_PIN,
-		.pupd = GPIO_PUPDR_NONE,
-		.type = GPIO_MODER_ALT,
-		.func = BOARD_USART_FUNC,
-		.o_type = GPIO_OTYPER_PP,
-		.speed = GPIO_OSPEEDR_50M,
-	},
+    .u_num = 4,
+    .baud = 115200,
+    BOARD_USART_CONFIGS.tx =
+        {
+            .port = BOARD_USART_TX_IO_PORT,
+            .pin = BOARD_USART_TX_IO_PIN,
+            .pupd = GPIO_PUPDR_NONE,
+            .type = GPIO_MODER_ALT,
+            .func = BOARD_USART_FUNC,
+            .o_type = GPIO_OTYPER_PP,
+            .speed = GPIO_OSPEEDR_50M,
+        },
+    .rx =
+        {
+            .port = BOARD_USART_RX_IO_PORT,
+            .pin = BOARD_USART_RX_IO_PIN,
+            .pupd = GPIO_PUPDR_NONE,
+            .type = GPIO_MODER_ALT,
+            .func = BOARD_USART_FUNC,
+            .o_type = GPIO_OTYPER_PP,
+            .speed = GPIO_OSPEEDR_50M,
+        },
 };
diff --git a/board/discoveryf4/board.h b/board/discoveryf4/board.h
index db76910c..36e0617d 100644
--- a/board/discoveryf4/board.h
+++ b/board/discoveryf4/board.h
@@ -6,58 +6,55 @@
 #ifndef DISCOVERYF4_BOARD_H_
 #define DISCOVERYF4_BOARD_H_
 
-#include <platform/stm32f4/registers.h>
 #include <platform/stm32f4/gpio.h>
-#include <platform/stm32f4/usart.h>
 #include <platform/stm32f4/nvic.h>
+#include <platform/stm32f4/registers.h>
 #include <platform/stm32f4/systick.h>
+#include <platform/stm32f4/usart.h>
 
 extern struct usart_dev console_uart;
 
 #if defined(CONFIG_DBGPORT_USE_USART1)
 
-#define BOARD_UART_DEVICE	USART1_IRQn
-#define BOARD_UART_HANDLER	USART1_HANDLER
-#define BOARD_USART_FUNC	af_usart1
-#define BOARD_USART_CONFIGS			\
-	.base = USART1_BASE,			\
-	.rcc_apbenr = RCC_USART1_APBENR,	\
-	.rcc_reset = RCC_APB2RSTR_USART1RST,
-#define BOARD_USART_TX_IO_PORT	GPIOA
-#define BOARD_USART_TX_IO_PIN	9
-#define BOARD_USART_RX_IO_PORT	GPIOA
-#define BOARD_USART_RX_IO_PIN	10
+#define BOARD_UART_DEVICE USART1_IRQn
+#define BOARD_UART_HANDLER USART1_HANDLER
+#define BOARD_USART_FUNC af_usart1
+#define BOARD_USART_CONFIGS                               \
+    .base = USART1_BASE, .rcc_apbenr = RCC_USART1_APBENR, \
+    .rcc_reset = RCC_APB2RSTR_USART1RST,
+#define BOARD_USART_TX_IO_PORT GPIOA
+#define BOARD_USART_TX_IO_PIN 9
+#define BOARD_USART_RX_IO_PORT GPIOA
+#define BOARD_USART_RX_IO_PIN 10
 
 
 #elif defined(CONFIG_DBGPORT_USE_USART2)
 
-#define BOARD_UART_DEVICE	USART2_IRQn
-#define BOARD_UART_HANDLER	USART2_HANDLER
-#define BOARD_USART_FUNC	af_usart2
-#define BOARD_USART_CONFIGS			\
-	.base = USART2_BASE,			\
-	.rcc_apbenr = RCC_USART2_APBENR,	\
-	.rcc_reset = RCC_APB1RSTR_USART2RST,
-#define BOARD_USART_TX_IO_PORT	GPIOA
-#define BOARD_USART_TX_IO_PIN	2
-#define BOARD_USART_RX_IO_PORT	GPIOA
-#define BOARD_USART_RX_IO_PIN	3
-
-#else	/* default: USART4 */
-	/* CONFIG_DBGPORT_USE_USART4 */
-
-#define BOARD_UART_DEVICE	UART4_IRQn
-#define BOARD_UART_HANDLER	UART4_HANDLER
-#define BOARD_USART_FUNC	af_uart4
-#define BOARD_USART_CONFIGS			\
-	.base = UART4_BASE,			\
-	.rcc_apbenr = RCC_UART4_APBENR,		\
-	.rcc_reset = RCC_APB1RSTR_USART4RST,
-#define BOARD_USART_TX_IO_PORT	GPIOA
-#define BOARD_USART_TX_IO_PIN	0
-#define BOARD_USART_RX_IO_PORT	GPIOA
-#define BOARD_USART_RX_IO_PIN	1
+#define BOARD_UART_DEVICE USART2_IRQn
+#define BOARD_UART_HANDLER USART2_HANDLER
+#define BOARD_USART_FUNC af_usart2
+#define BOARD_USART_CONFIGS                               \
+    .base = USART2_BASE, .rcc_apbenr = RCC_USART2_APBENR, \
+    .rcc_reset = RCC_APB1RSTR_USART2RST,
+#define BOARD_USART_TX_IO_PORT GPIOA
+#define BOARD_USART_TX_IO_PIN 2
+#define BOARD_USART_RX_IO_PORT GPIOA
+#define BOARD_USART_RX_IO_PIN 3
+
+#else /* default: USART4 */
+/* CONFIG_DBGPORT_USE_USART4 */
+
+#define BOARD_UART_DEVICE UART4_IRQn
+#define BOARD_UART_HANDLER UART4_HANDLER
+#define BOARD_USART_FUNC af_uart4
+#define BOARD_USART_CONFIGS                             \
+    .base = UART4_BASE, .rcc_apbenr = RCC_UART4_APBENR, \
+    .rcc_reset = RCC_APB1RSTR_USART4RST,
+#define BOARD_USART_TX_IO_PORT GPIOA
+#define BOARD_USART_TX_IO_PIN 0
+#define BOARD_USART_RX_IO_PORT GPIOA
+#define BOARD_USART_RX_IO_PIN 1
 
 #endif
 
-#endif	/* DISCOVERYF4_BOARD_H_ */
+#endif /* DISCOVERYF4_BOARD_H_ */
diff --git a/board/discoveryf429/board.c b/board/discoveryf429/board.c
index ab0f2a06..22d902ac 100644
--- a/board/discoveryf429/board.c
+++ b/board/discoveryf429/board.c
@@ -3,30 +3,31 @@
  * found in the LICENSE file.
  */
 
+#include "board.h"
 #include <platform/stm32f429/gpio.h>
 #include <platform/stm32f429/usart.h>
-#include "board.h"
 
 struct usart_dev console_uart = {
-	.u_num = 4,
-	.baud = 115200,
-	BOARD_USART_CONFIGS
-	.tx = {
-		.port = BOARD_USART_TX_IO_PORT,
-		.pin = BOARD_USART_TX_IO_PIN,
-		.pupd = GPIO_PUPDR_NONE,
-		.type = GPIO_MODER_ALT,
-		.func = BOARD_USART_FUNC,
-		.o_type = GPIO_OTYPER_PP,
-		.speed = GPIO_OSPEEDR_50M,
-	},
-	.rx = {
-		.port = BOARD_USART_RX_IO_PORT,
-		.pin = BOARD_USART_RX_IO_PIN,
-		.pupd = GPIO_PUPDR_NONE,
-		.type = GPIO_MODER_ALT,
-		.func = BOARD_USART_FUNC,
-		.o_type = GPIO_OTYPER_PP,
-		.speed = GPIO_OSPEEDR_50M,
-	},
+    .u_num = 4,
+    .baud = 115200,
+    BOARD_USART_CONFIGS.tx =
+        {
+            .port = BOARD_USART_TX_IO_PORT,
+            .pin = BOARD_USART_TX_IO_PIN,
+            .pupd = GPIO_PUPDR_NONE,
+            .type = GPIO_MODER_ALT,
+            .func = BOARD_USART_FUNC,
+            .o_type = GPIO_OTYPER_PP,
+            .speed = GPIO_OSPEEDR_50M,
+        },
+    .rx =
+        {
+            .port = BOARD_USART_RX_IO_PORT,
+            .pin = BOARD_USART_RX_IO_PIN,
+            .pupd = GPIO_PUPDR_NONE,
+            .type = GPIO_MODER_ALT,
+            .func = BOARD_USART_FUNC,
+            .o_type = GPIO_OTYPER_PP,
+            .speed = GPIO_OSPEEDR_50M,
+        },
 };
diff --git a/board/discoveryf429/board.h b/board/discoveryf429/board.h
index 02a5367f..489cd490 100644
--- a/board/discoveryf429/board.h
+++ b/board/discoveryf429/board.h
@@ -6,58 +6,55 @@
 #ifndef DISCOVERYF429_BOARD_H_
 #define DISCOVERYF429_BOARD_H_
 
-#include <platform/stm32f429/registers.h>
 #include <platform/stm32f429/gpio.h>
-#include <platform/stm32f429/usart.h>
 #include <platform/stm32f429/nvic.h>
+#include <platform/stm32f429/registers.h>
 #include <platform/stm32f429/systick.h>
+#include <platform/stm32f429/usart.h>
 
 extern struct usart_dev console_uart;
 
 #if defined(CONFIG_DBGPORT_USE_USART1)
 
-#define BOARD_UART_DEVICE	USART1_IRQn
-#define BOARD_UART_HANDLER	USART1_HANDLER
-#define BOARD_USART_FUNC	af_usart1
-#define BOARD_USART_CONFIGS			\
-	.base = USART1_BASE,			\
-	.rcc_apbenr = RCC_USART1_APBENR,	\
-	.rcc_reset = RCC_APB2RSTR_USART1RST,
-#define BOARD_USART_TX_IO_PORT	GPIOA
-#define BOARD_USART_TX_IO_PIN	9
-#define BOARD_USART_RX_IO_PORT	GPIOA
-#define BOARD_USART_RX_IO_PIN	10
+#define BOARD_UART_DEVICE USART1_IRQn
+#define BOARD_UART_HANDLER USART1_HANDLER
+#define BOARD_USART_FUNC af_usart1
+#define BOARD_USART_CONFIGS                               \
+    .base = USART1_BASE, .rcc_apbenr = RCC_USART1_APBENR, \
+    .rcc_reset = RCC_APB2RSTR_USART1RST,
+#define BOARD_USART_TX_IO_PORT GPIOA
+#define BOARD_USART_TX_IO_PIN 9
+#define BOARD_USART_RX_IO_PORT GPIOA
+#define BOARD_USART_RX_IO_PIN 10
 
 
 #elif defined(CONFIG_DBGPORT_USE_USART2)
 
-#define BOARD_UART_DEVICE	USART2_IRQn
-#define BOARD_UART_HANDLER	USART2_HANDLER
-#define BOARD_USART_FUNC	af_usart2
-#define BOARD_USART_CONFIGS			\
-	.base = USART2_BASE,			\
-	.rcc_apbenr = RCC_USART2_APBENR,	\
-	.rcc_reset = RCC_APB1RSTR_USART2RST,
-#define BOARD_USART_TX_IO_PORT	GPIOD
-#define BOARD_USART_TX_IO_PIN	5
-#define BOARD_USART_RX_IO_PORT	GPIOD
-#define BOARD_USART_RX_IO_PIN	6
-
-#else	/* default: USART4 */
+#define BOARD_UART_DEVICE USART2_IRQn
+#define BOARD_UART_HANDLER USART2_HANDLER
+#define BOARD_USART_FUNC af_usart2
+#define BOARD_USART_CONFIGS                               \
+    .base = USART2_BASE, .rcc_apbenr = RCC_USART2_APBENR, \
+    .rcc_reset = RCC_APB1RSTR_USART2RST,
+#define BOARD_USART_TX_IO_PORT GPIOD
+#define BOARD_USART_TX_IO_PIN 5
+#define BOARD_USART_RX_IO_PORT GPIOD
+#define BOARD_USART_RX_IO_PIN 6
+
+#else /* default: USART4 */
 /* CONFIG_DBGPORT_USE_USART4 */
 
-#define BOARD_UART_DEVICE	UART4_IRQn
-#define BOARD_UART_HANDLER	UART4_HANDLER
-#define BOARD_USART_FUNC	af_uart4
-#define BOARD_USART_CONFIGS			\
-	.base = UART4_BASE,			\
-	.rcc_apbenr = RCC_UART4_APBENR,		\
-	.rcc_reset = RCC_APB1RSTR_USART4RST,
-#define BOARD_USART_TX_IO_PORT	GPIOC
-#define BOARD_USART_TX_IO_PIN	11
-#define BOARD_USART_RX_IO_PORT	GPIOC
-#define BOARD_USART_RX_IO_PIN	10
+#define BOARD_UART_DEVICE UART4_IRQn
+#define BOARD_UART_HANDLER UART4_HANDLER
+#define BOARD_USART_FUNC af_uart4
+#define BOARD_USART_CONFIGS                             \
+    .base = UART4_BASE, .rcc_apbenr = RCC_UART4_APBENR, \
+    .rcc_reset = RCC_APB1RSTR_USART4RST,
+#define BOARD_USART_TX_IO_PORT GPIOC
+#define BOARD_USART_TX_IO_PIN 11
+#define BOARD_USART_RX_IO_PORT GPIOC
+#define BOARD_USART_RX_IO_PIN 10
 
 #endif
 
-#endif	/* DISCOVERYF429_BOARD_H_ */
+#endif /* DISCOVERYF429_BOARD_H_ */
diff --git a/board/netduinoplus2/board.c b/board/netduinoplus2/board.c
index ac3b9c2b..3e2f51d6 100644
--- a/board/netduinoplus2/board.c
+++ b/board/netduinoplus2/board.c
@@ -3,30 +3,31 @@
  * found in the LICENSE file.
  */
 
+#include "board.h"
 #include <platform/stm32f4/gpio.h>
 #include <platform/stm32f4/usart.h>
-#include "board.h"
 
 struct usart_dev console_uart = {
-	.u_num = 2,
-	.baud = 115200,
-	BOARD_USART_CONFIGS
-	.tx = {
-		.port = BOARD_USART_TX_IO_PORT,
-		.pin = BOARD_USART_TX_IO_PIN,
-		.pupd = GPIO_PUPDR_NONE,
-		.type = GPIO_MODER_ALT,
-		.func = BOARD_USART_FUNC,
-		.o_type = GPIO_OTYPER_PP,
-		.speed = GPIO_OSPEEDR_50M,
-	},
-	.rx = {
-		.port = BOARD_USART_RX_IO_PORT,
-		.pin = BOARD_USART_RX_IO_PIN,
-		.pupd = GPIO_PUPDR_NONE,
-		.type = GPIO_MODER_ALT,
-		.func = BOARD_USART_FUNC,
-		.o_type = GPIO_OTYPER_PP,
-		.speed = GPIO_OSPEEDR_50M,
-	},
+    .u_num = 2,
+    .baud = 115200,
+    BOARD_USART_CONFIGS.tx =
+        {
+            .port = BOARD_USART_TX_IO_PORT,
+            .pin = BOARD_USART_TX_IO_PIN,
+            .pupd = GPIO_PUPDR_NONE,
+            .type = GPIO_MODER_ALT,
+            .func = BOARD_USART_FUNC,
+            .o_type = GPIO_OTYPER_PP,
+            .speed = GPIO_OSPEEDR_50M,
+        },
+    .rx =
+        {
+            .port = BOARD_USART_RX_IO_PORT,
+            .pin = BOARD_USART_RX_IO_PIN,
+            .pupd = GPIO_PUPDR_NONE,
+            .type = GPIO_MODER_ALT,
+            .func = BOARD_USART_FUNC,
+            .o_type = GPIO_OTYPER_PP,
+            .speed = GPIO_OSPEEDR_50M,
+        },
 };
diff --git a/board/netduinoplus2/board.h b/board/netduinoplus2/board.h
index 917a6abb..ab6fb7da 100644
--- a/board/netduinoplus2/board.h
+++ b/board/netduinoplus2/board.h
@@ -6,60 +6,57 @@
 #ifndef NETDUINOPLUS2_BOARD_H_
 #define NETDUINOPLUS2_BOARD_H_
 
-#include <platform/stm32f4/registers.h>
 #include <platform/stm32f4/gpio.h>
-#include <platform/stm32f4/usart.h>
 #include <platform/stm32f4/nvic.h>
+#include <platform/stm32f4/registers.h>
 #include <platform/stm32f4/systick.h>
+#include <platform/stm32f4/usart.h>
 
 extern struct usart_dev console_uart;
 
 #if defined(CONFIG_DBGPORT_USE_USART1)
 
-#define BOARD_UART_DEVICE	USART1_IRQn
-#define BOARD_UART_HANDLER	USART1_HANDLER
-#define BOARD_USART_FUNC	af_usart1
-#define BOARD_USART_CONFIGS			\
-	.base = USART1_BASE,			\
-	.rcc_apbenr = RCC_USART1_APBENR,	\
-	.rcc_reset = RCC_APB2RSTR_USART1RST,
-#define BOARD_USART_TX_IO_PORT	GPIOA
-#define BOARD_USART_TX_IO_PIN	9
-#define BOARD_USART_RX_IO_PORT	GPIOA
-#define BOARD_USART_RX_IO_PIN	10
+#define BOARD_UART_DEVICE USART1_IRQn
+#define BOARD_UART_HANDLER USART1_HANDLER
+#define BOARD_USART_FUNC af_usart1
+#define BOARD_USART_CONFIGS                               \
+    .base = USART1_BASE, .rcc_apbenr = RCC_USART1_APBENR, \
+    .rcc_reset = RCC_APB2RSTR_USART1RST,
+#define BOARD_USART_TX_IO_PORT GPIOA
+#define BOARD_USART_TX_IO_PIN 9
+#define BOARD_USART_RX_IO_PORT GPIOA
+#define BOARD_USART_RX_IO_PIN 10
 
 #elif defined(CONFIG_DBGPORT_USE_USART4)
 
-#define BOARD_UART_DEVICE	UART4_IRQn
-#define BOARD_UART_HANDLER	UART4_HANDLER
-#define BOARD_USART_FUNC	af_uart4
-#define BOARD_USART_CONFIGS			\
-	.base = UART4_BASE,			\
-	.rcc_apbenr = RCC_UART4_APBENR,		\
-	.rcc_reset = RCC_APB1RSTR_USART4RST,
-#define BOARD_USART_TX_IO_PORT	GPIOA
-#define BOARD_USART_TX_IO_PIN	0
-#define BOARD_USART_RX_IO_PORT	GPIOA
-#define BOARD_USART_RX_IO_PIN	1
-
-#else	/* default: USART2 */
-	/* CONFIG_DBGPORT_USE_USART2
-	 * Note: QEMU routes USART1 to the console by default.
-	 * Use CONFIG_DBGPORT_USE_USART1 for QEMU emulation.
-	 */
+#define BOARD_UART_DEVICE UART4_IRQn
+#define BOARD_UART_HANDLER UART4_HANDLER
+#define BOARD_USART_FUNC af_uart4
+#define BOARD_USART_CONFIGS                             \
+    .base = UART4_BASE, .rcc_apbenr = RCC_UART4_APBENR, \
+    .rcc_reset = RCC_APB1RSTR_USART4RST,
+#define BOARD_USART_TX_IO_PORT GPIOA
+#define BOARD_USART_TX_IO_PIN 0
+#define BOARD_USART_RX_IO_PORT GPIOA
+#define BOARD_USART_RX_IO_PIN 1
+
+#else /* default: USART2 */
+/* CONFIG_DBGPORT_USE_USART2
+ * Note: QEMU routes USART1 to the console by default.
+ * Use CONFIG_DBGPORT_USE_USART1 for QEMU emulation.
+ */
 
-#define BOARD_UART_DEVICE	USART2_IRQn
-#define BOARD_UART_HANDLER	USART2_HANDLER
-#define BOARD_USART_FUNC	af_usart2
-#define BOARD_USART_CONFIGS			\
-	.base = USART2_BASE,			\
-	.rcc_apbenr = RCC_USART2_APBENR,	\
-	.rcc_reset = RCC_APB1RSTR_USART2RST,
-#define BOARD_USART_TX_IO_PORT	GPIOA
-#define BOARD_USART_TX_IO_PIN	2
-#define BOARD_USART_RX_IO_PORT	GPIOA
-#define BOARD_USART_RX_IO_PIN	3
+#define BOARD_UART_DEVICE USART2_IRQn
+#define BOARD_UART_HANDLER USART2_HANDLER
+#define BOARD_USART_FUNC af_usart2
+#define BOARD_USART_CONFIGS                               \
+    .base = USART2_BASE, .rcc_apbenr = RCC_USART2_APBENR, \
+    .rcc_reset = RCC_APB1RSTR_USART2RST,
+#define BOARD_USART_TX_IO_PORT GPIOA
+#define BOARD_USART_TX_IO_PIN 2
+#define BOARD_USART_RX_IO_PORT GPIOA
+#define BOARD_USART_RX_IO_PIN 3
 
 #endif
 
-#endif	/* NETDUINOPLUS2_BOARD_H_ */
+#endif /* NETDUINOPLUS2_BOARD_H_ */
diff --git a/board/nucleof429/board.c b/board/nucleof429/board.c
index eba363b3..916eafc5 100644
--- a/board/nucleof429/board.c
+++ b/board/nucleof429/board.c
@@ -1,32 +1,33 @@
-/* Copyright (c) 2016 The F9 Microkernel Project. All rights reserved.
+/* Copyright (c) 2026 The F9 Microkernel Project. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "board.h"
 #include <platform/stm32f429/gpio.h>
 #include <platform/stm32f429/usart.h>
-#include "board.h"
 
 struct usart_dev console_uart = {
-	.u_num = 3,
-	.baud = 115200,
-	BOARD_USART_CONFIGS
-	.tx = {
-		.port = BOARD_USART_TX_IO_PORT,
-		.pin = BOARD_USART_TX_IO_PIN,
-		.pupd = GPIO_PUPDR_NONE,
-		.type = GPIO_MODER_ALT,
-		.func = BOARD_USART_FUNC,
-		.o_type = GPIO_OTYPER_PP,
-		.speed = GPIO_OSPEEDR_50M,
-	},
-	.rx = {
-		.port = BOARD_USART_RX_IO_PORT,
-		.pin = BOARD_USART_RX_IO_PIN,
-		.pupd = GPIO_PUPDR_NONE,
-		.type = GPIO_MODER_ALT,
-		.func = BOARD_USART_FUNC,
-		.o_type = GPIO_OTYPER_PP,
-		.speed = GPIO_OSPEEDR_50M,
-	},
-};
\ No newline at end of file
+    .u_num = 3,
+    .baud = 115200,
+    BOARD_USART_CONFIGS.tx =
+        {
+            .port = BOARD_USART_TX_IO_PORT,
+            .pin = BOARD_USART_TX_IO_PIN,
+            .pupd = GPIO_PUPDR_NONE,
+            .type = GPIO_MODER_ALT,
+            .func = BOARD_USART_FUNC,
+            .o_type = GPIO_OTYPER_PP,
+            .speed = GPIO_OSPEEDR_50M,
+        },
+    .rx =
+        {
+            .port = BOARD_USART_RX_IO_PORT,
+            .pin = BOARD_USART_RX_IO_PIN,
+            .pupd = GPIO_PUPDR_NONE,
+            .type = GPIO_MODER_ALT,
+            .func = BOARD_USART_FUNC,
+            .o_type = GPIO_OTYPER_PP,
+            .speed = GPIO_OSPEEDR_50M,
+        },
+};
diff --git a/board/nucleof429/board.h b/board/nucleof429/board.h
index c015db5c..ce2e92a8 100644
--- a/board/nucleof429/board.h
+++ b/board/nucleof429/board.h
@@ -6,57 +6,54 @@
 #ifndef NUCLEO_F429_BOARD_H_
 #define NUCLEO_F429_BOARD_H_
 
-#include <platform/stm32f429/registers.h>
 #include <platform/stm32f429/gpio.h>
-#include <platform/stm32f429/usart.h>
 #include <platform/stm32f429/nvic.h>
+#include <platform/stm32f429/registers.h>
 #include <platform/stm32f429/systick.h>
+#include <platform/stm32f429/usart.h>
 
 extern struct usart_dev console_uart;
 
 #if defined(CONFIG_DBGPORT_USE_USART1)
 
-#define BOARD_UART_DEVICE	USART1_IRQn
-#define BOARD_UART_HANDLER	USART1_HANDLER
-#define BOARD_USART_FUNC	af_usart1
-#define BOARD_USART_CONFIGS			\
-	.base = USART1_BASE,			\
-	.rcc_apbenr = RCC_USART1_APBENR,	\
-	.rcc_reset = RCC_APB2RSTR_USART1RST,
-#define BOARD_USART_TX_IO_PORT	GPIOB
-#define BOARD_USART_TX_IO_PIN	6
-#define BOARD_USART_RX_IO_PORT	GPIOB
-#define BOARD_USART_RX_IO_PIN	7
+#define BOARD_UART_DEVICE USART1_IRQn
+#define BOARD_UART_HANDLER USART1_HANDLER
+#define BOARD_USART_FUNC af_usart1
+#define BOARD_USART_CONFIGS                               \
+    .base = USART1_BASE, .rcc_apbenr = RCC_USART1_APBENR, \
+    .rcc_reset = RCC_APB2RSTR_USART1RST,
+#define BOARD_USART_TX_IO_PORT GPIOB
+#define BOARD_USART_TX_IO_PIN 6
+#define BOARD_USART_RX_IO_PORT GPIOB
+#define BOARD_USART_RX_IO_PIN 7
 
 
 #elif defined(CONFIG_DBGPORT_USE_USART2)
 
-#define BOARD_UART_DEVICE	USART2_IRQn
-#define BOARD_UART_HANDLER	USART2_HANDLER
-#define BOARD_USART_FUNC	af_usart2
-#define BOARD_USART_CONFIGS			\
-	.base = USART2_BASE,			\
-	.rcc_apbenr = RCC_USART2_APBENR,	\
-	.rcc_reset = RCC_APB1RSTR_USART2RST,
-#define BOARD_USART_TX_IO_PORT	GPIOD
-#define BOARD_USART_TX_IO_PIN	5
-#define BOARD_USART_RX_IO_PORT	GPIOD
-#define BOARD_USART_RX_IO_PIN	6
-
-#else	/* default: USART3 (ST-LINK virtual COM port on Nucleo-F429ZI) */
-
-#define BOARD_UART_DEVICE	USART3_IRQn
-#define BOARD_UART_HANDLER	USART3_HANDLER
-#define BOARD_USART_FUNC	af_usart3
-#define BOARD_USART_CONFIGS			\
-	.base = USART3_BASE,			\
-	.rcc_apbenr = RCC_USART3_APBENR,	\
-	.rcc_reset = RCC_APB1RSTR_USART3RST,
-#define BOARD_USART_TX_IO_PORT	GPIOD
-#define BOARD_USART_TX_IO_PIN	8
-#define BOARD_USART_RX_IO_PORT	GPIOD
-#define BOARD_USART_RX_IO_PIN	9
+#define BOARD_UART_DEVICE USART2_IRQn
+#define BOARD_UART_HANDLER USART2_HANDLER
+#define BOARD_USART_FUNC af_usart2
+#define BOARD_USART_CONFIGS                               \
+    .base = USART2_BASE, .rcc_apbenr = RCC_USART2_APBENR, \
+    .rcc_reset = RCC_APB1RSTR_USART2RST,
+#define BOARD_USART_TX_IO_PORT GPIOD
+#define BOARD_USART_TX_IO_PIN 5
+#define BOARD_USART_RX_IO_PORT GPIOD
+#define BOARD_USART_RX_IO_PIN 6
+
+#else /* default: USART3 (ST-LINK virtual COM port on Nucleo-F429ZI) */
+
+#define BOARD_UART_DEVICE USART3_IRQn
+#define BOARD_UART_HANDLER USART3_HANDLER
+#define BOARD_USART_FUNC af_usart3
+#define BOARD_USART_CONFIGS                               \
+    .base = USART3_BASE, .rcc_apbenr = RCC_USART3_APBENR, \
+    .rcc_reset = RCC_APB1RSTR_USART3RST,
+#define BOARD_USART_TX_IO_PORT GPIOD
+#define BOARD_USART_TX_IO_PIN 8
+#define BOARD_USART_RX_IO_PORT GPIOD
+#define BOARD_USART_RX_IO_PIN 9
 
 #endif
 
-#endif	/* NUCLEO_F429_BOARD_H_ */
+#endif /* NUCLEO_F429_BOARD_H_ */
diff --git a/board/nucleof429/build.mk b/board/nucleof429/build.mk
index d2bed613..ebe981e8 100644
--- a/board/nucleof429/build.mk
+++ b/board/nucleof429/build.mk
@@ -1,4 +1,4 @@
-# Copyright (c) 2016 The F9 Microkernel Project. All rights reserved.
+# Copyright (c) 2026 The F9 Microkernel Project. All rights reserved.
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -7,4 +7,4 @@ PLATFORM := stm32
 STM32_VARIANT := f4
 
 board-y = board.o
-loader-board-y = board.loader.o
\ No newline at end of file
+loader-board-y = board.loader.o
diff --git a/include/debug.h b/include/debug.h
index 9bdd2e6c..248ea8b3 100644
--- a/include/debug.h
+++ b/include/debug.h
@@ -7,31 +7,38 @@
 #define DEBUG_H_
 
 #include <types.h>
+
 #include <lib/stdarg.h>
 #include <lib/stdio.h>
 #include <platform/debug_device.h>
 
 typedef enum {
-	DL_EMERG	= 0x0000,
-	DL_BASIC	= 0x8000,
-	DL_KDB 		= 0x4000,
-	DL_KTABLE	= 0x0001,
-	DL_SOFTIRQ	= 0x0002,
-	DL_THREAD	= 0x0004,
-	DL_KTIMER	= 0x0008,
-	DL_SYSCALL	= 0x0010,
-	DL_SCHEDULE	= 0x0020,
-	DL_MEMORY	= 0x0040,
-	DL_IPC		= 0x0080
+    DL_EMERG = 0x0000,
+    DL_BASIC = 0x8000,
+    DL_KDB = 0x4000,
+    DL_KTABLE = 0x0001,
+    DL_SOFTIRQ = 0x0002,
+    DL_THREAD = 0x0004,
+    DL_KTIMER = 0x0008,
+    DL_SYSCALL = 0x0010,
+    DL_SCHEDULE = 0x0020,
+    DL_MEMORY = 0x0040,
+    DL_IPC = 0x0080
 } dbg_layer_t;
 
 #ifndef CONFIG_DEBUG
-#define dbg_puts(x)		do {} while(0)
-#define dbg_printf(...)		do {} while(0)
-#define dbg_vprintf(...)	do {} while(0)
+#define dbg_puts(x) \
+    do {            \
+    } while (0)
+#define dbg_printf(...) \
+    do {                \
+    } while (0)
+#define dbg_vprintf(...) \
+    do {                 \
+    } while (0)
 
 #else
-#define dbg_puts(x)	__l4_puts(x)
+#define dbg_puts(x) __l4_puts(x)
 void dbg_printf(dbg_layer_t layer, char *fmt, ...);
 void dbg_vprintf(dbg_layer_t layer, char *fmt, va_list va);
 
diff --git a/include/error.h b/include/error.h
index 6d81b2b7..9b72fb66 100644
--- a/include/error.h
+++ b/include/error.h
@@ -13,44 +13,42 @@
  * Userspace errors
  */
 enum user_error_t {
-	UE_NO_PRIVILIGE 	= 1,
-	UE_OUT_OF_MEM		= 8,
-
-	/**
-	 * ThreadControl errors
-	 * see L4 X.2 R7 Reference, Page 24-25
-	 *
-	 * Invalid UTCB is not used because we have no Utcb Area
-	 */
-	UE_TC_NOT_AVAILABLE	= 2,
-	UE_TC_INVAL_SPACE	= 3,
-	UE_TC_INVAL_SCHED	= 4,
-	UE_TC_INVAL_UTCB	= 6,		/* Not used */
-
-	/**
-	 * Ipc errors
-	 * see L4 X.2 R7 Reference, Page 67-68
-	 *
-	 * NOTE: Message overflow may also occur if MR's are not enough
-	 */
-
-	UE_IPC_PHASE_SEND	= 0,
-	UE_IPC_PHASE_RECV	= 1,
-
-	UE_IPC_TIMEOUT		= 1 << 1,
-	UE_IPC_NOT_EXIST	= 2 << 1,
-	UE_IPC_CANCELED		= 3 << 1,
-
-	UE_IPC_MSG_OVERFLOW	= 4 << 1,
-	UE_IPC_XFER_TIMEOUT	= 5 << 1,
-	UE_IPC_XFER_TIMEOUT2	= 6 << 1,
-	UE_IPC_ABORTED		= 7 << 1
+    UE_NO_PRIVILIGE = 1,
+    UE_OUT_OF_MEM = 8,
+
+    /**
+     * ThreadControl errors
+     * see L4 X.2 R7 Reference, Page 24-25
+     *
+     * Invalid UTCB is not used because we have no Utcb Area
+     */
+    UE_TC_NOT_AVAILABLE = 2,
+    UE_TC_INVAL_SPACE = 3,
+    UE_TC_INVAL_SCHED = 4,
+    UE_TC_INVAL_UTCB = 6, /* Not used */
+
+    /**
+     * Ipc errors
+     * see L4 X.2 R7 Reference, Page 67-68
+     *
+     * NOTE: Message overflow may also occur if MR's are not enough
+     */
+
+    UE_IPC_PHASE_SEND = 0,
+    UE_IPC_PHASE_RECV = 1,
+
+    UE_IPC_TIMEOUT = 1 << 1,
+    UE_IPC_NOT_EXIST = 2 << 1,
+    UE_IPC_CANCELED = 3 << 1,
+
+    UE_IPC_MSG_OVERFLOW = 4 << 1,
+    UE_IPC_XFER_TIMEOUT = 5 << 1,
+    UE_IPC_XFER_TIMEOUT2 = 6 << 1,
+    UE_IPC_ABORTED = 7 << 1
 };
 
-#define assert(cond) \
-	assert_impl(cond, #cond, __func__)
-#define panic(...) \
-	panic_impl(__VA_ARGS__)
+#define assert(cond) assert_impl(cond, #cond, __func__)
+#define panic(...) panic_impl(__VA_ARGS__)
 
 void set_caller_error(enum user_error_t error);
 void set_user_error(tcb_t *thread, enum user_error_t error);
diff --git a/include/fpage.h b/include/fpage.h
index ba518115..f2e822d8 100644
--- a/include/fpage.h
+++ b/include/fpage.h
@@ -9,49 +9,40 @@
 #include <memory.h>
 #include <types.h>
 
-#define FPAGE_ALWAYS    0x1     /*! Fpage is always mapped in MPU */
-#define FPAGE_CLONE     0x2     /*! Fpage is mapped from other AS */
-#define FPAGE_MAPPED    0x4     /*! Fpage is mapped with MAP (
-				   unavailable in original AS) */
+#define FPAGE_ALWAYS 0x1 /*! Fpage is always mapped in MPU */
+#define FPAGE_CLONE 0x2  /*! Fpage is mapped from other AS */
+/*! Fpage is mapped with MAP (unavailable in original AS) */
+#define FPAGE_MAPPED 0x4
 
 /**
  * Flexible page (fpage_t)
- *
- * as_next - next in address space chain
- * map_next - next in mappings chain (cycle list)
- *
- * base - base address of fpage
- * shift - size of fpage == 1 << shift
- * rwx - access bits
- * mpid - id of memory pool
- * flags - flags
  */
 struct fpage {
-	struct fpage *as_next;
-	struct fpage *map_next;
-	struct fpage *mpu_next;
+    struct fpage *as_next;  /* next in address space chain */
+    struct fpage *map_next; /* next in mappings chain (cycle list) */
+    struct fpage *mpu_next; /* next in MPU region list */
 
-	union {
-		struct {
-			uint32_t base;
-			uint32_t mpid : 6;
-			uint32_t flags : 6;
-			uint32_t shift : 16;
-			uint32_t rwx : 4;
-		} fpage;
-		uint32_t raw[2];
-	};
+    union {
+        struct {
+            uint32_t base;       /* base address of fpage */
+            uint32_t mpid : 6;   /* id of memory pool */
+            uint32_t flags : 6;  /* flags */
+            uint32_t shift : 16; /* size of fpage == 1 << shift */
+            uint32_t rwx : 4;    /* access bits */
+        } fpage;
+        uint32_t raw[2];
+    };
 
 #ifdef CONFIG_KDB
-	int used;
-#endif /* CONFIG_KDB */
+    int used; /* fpage allocation tracking for KDB */
+#endif        /* CONFIG_KDB */
 };
 
 typedef struct fpage fpage_t;
 
-#define FPAGE_BASE(fp) 	(fp)->fpage.base
-#define FPAGE_SIZE(fp)  (1 << (fp)->fpage.shift)
-#define FPAGE_END(fp)	(FPAGE_BASE(fp) + FPAGE_SIZE(fp))
+#define FPAGE_BASE(fp) (fp)->fpage.base
+#define FPAGE_SIZE(fp) (1 << (fp)->fpage.shift)
+#define FPAGE_END(fp) (FPAGE_BASE(fp) + FPAGE_SIZE(fp))
 
 /**
  * Remove fpage from a linked list (as_next or mpu_next chain).
@@ -70,20 +61,21 @@ typedef struct fpage fpage_t;
  * @param first  Name of list head field in as (e.g., first, mpu_first)
  * @param next   Name of next pointer field in fpage (e.g., as_next, mpu_next)
  */
-#define remove_fpage_from_list(as, fpage, first, next) do {	\
-	fpage_t **_curr = &(as)->first;				\
-	while (*_curr && *_curr != (fpage)) {			\
-		_curr = &(*_curr)->next;			\
-	}							\
-	if (*_curr) {						\
-		*_curr = (*_curr)->next;			\
-	}							\
-} while (0)
+#define remove_fpage_from_list(as, fpage, first, next) \
+    do {                                               \
+        fpage_t **_curr = &(as)->first;                \
+        while (*_curr && *_curr != (fpage)) {          \
+            _curr = &(*_curr)->next;                   \
+        }                                              \
+        if (*_curr) {                                  \
+            *_curr = (*_curr)->next;                   \
+        }                                              \
+    } while (0)
 
 static inline int addr_in_fpage(memptr_t addr, fpage_t *fpage, int incl_end)
 {
-	return ((addr >= FPAGE_BASE(fpage) && addr < FPAGE_END(fpage)) ||
-			(incl_end && addr == FPAGE_END(fpage)));
+    return ((addr >= FPAGE_BASE(fpage) && addr < FPAGE_END(fpage)) ||
+            (incl_end && addr == FPAGE_END(fpage)));
 }
 
 #endif /* FPAGE_H_ */
diff --git a/include/fpage_impl.h b/include/fpage_impl.h
index fbbdea43..19b6f0ba 100644
--- a/include/fpage_impl.h
+++ b/include/fpage_impl.h
@@ -11,8 +11,12 @@ void fpages_init(void);
 fpage_t *split_fpage(as_t *as, fpage_t *fpage, memptr_t split, int rl);
 
 int assign_fpages(as_t *as, memptr_t base, size_t size);
-int assign_fpages_ext(int mpid, as_t *as, memptr_t base, size_t size,
-                      fpage_t **pfirst, fpage_t **plast);
+int assign_fpages_ext(int mpid,
+                      as_t *as,
+                      memptr_t base,
+                      size_t size,
+                      fpage_t **pfirst,
+                      fpage_t **plast);
 
 int map_fpage(as_t *src, as_t *dst, fpage_t *fpage, map_action_t action);
 int unmap_fpage(as_t *as, fpage_t *fpage);
diff --git a/include/init_hook.h b/include/init_hook.h
index 4feeb754..30375930 100644
--- a/include/init_hook.h
+++ b/include/init_hook.h
@@ -7,29 +7,29 @@
 #define INIT_HOOK_H_
 
 enum init_levels {
-	INIT_LEVEL_EARLIEST		= 1,
-	INIT_LEVEL_PLATFORM_EARLY 	= 0x1000,
-	INIT_LEVEL_PLATFORM		= 0x2000,
-	INIT_LEVEL_KERNEL_EARLY		= 0x3000,
-	INIT_LEVEL_KERNEL		= 0x4000,
-	INIT_LEVEL_LAST			= 0xFFFFFFFF,
+    INIT_LEVEL_EARLIEST = 1,
+    INIT_LEVEL_PLATFORM_EARLY = 0x1000,
+    INIT_LEVEL_PLATFORM = 0x2000,
+    INIT_LEVEL_KERNEL_EARLY = 0x3000,
+    INIT_LEVEL_KERNEL = 0x4000,
+    INIT_LEVEL_LAST = 0xFFFFFFFF,
 };
 
 typedef void (*init_hook_t)(void);
 
 typedef struct {
-	unsigned int level;
-	init_hook_t hook;
-	const char *hook_name;
+    unsigned int level;
+    init_hook_t hook;
+    const char *hook_name;
 } init_struct;
 
-#define INIT_HOOK(_hook, _level)					\
-	const init_struct _init_struct_##_hook				\
-			__attribute__((section(".init_hook"))) = {	\
-		.level = _level,					\
-		.hook = _hook,						\
-		.hook_name = #_hook,					\
-	};
+#define INIT_HOOK(_hook, _level)                   \
+    const init_struct _init_struct_##_hook         \
+        __attribute__((section(".init_hook"))) = { \
+            .level = _level,                       \
+            .hook = _hook,                         \
+            .hook_name = #_hook,                   \
+    };
 
 int run_init_hook(unsigned int level);
 
diff --git a/include/interrupt.h b/include/interrupt.h
index c4ead034..c4d39d03 100644
--- a/include/interrupt.h
+++ b/include/interrupt.h
@@ -1,7 +1,7 @@
 #ifndef INTERRUPT_H_
 #define INTERRUPT_H_
 
-#define DEFAULT_PRIORITY	1
+#define DEFAULT_PRIORITY 1
 
 void user_interrupt_config(tcb_t *from);
 void user_interrupt_handler_update(tcb_t *thr);
diff --git a/include/interrupt_ipc.h b/include/interrupt_ipc.h
index 2d8de9ba..7e220526 100644
--- a/include/interrupt_ipc.h
+++ b/include/interrupt_ipc.h
@@ -10,15 +10,11 @@ enum {
     IRQ_IPC_PRIORITY = 4
 };
 
-#define IRQ_IPC_MSG_NUM	IRQ_IPC_PRIORITY
+#define IRQ_IPC_MSG_NUM IRQ_IPC_PRIORITY
 
 /* irq actions */
-enum {
-    USER_IRQ_ENABLE = 0,
-    USER_IRQ_DISABLE = 1,
-    USER_IRQ_FREE = 2
-};
+enum { USER_IRQ_ENABLE = 0, USER_IRQ_DISABLE = 1, USER_IRQ_FREE = 2 };
 
-#define USER_INTERRUPT_LABEL	0x928
+#define USER_INTERRUPT_LABEL 0x928
 
 #endif
diff --git a/include/ipc.h b/include/ipc.h
index 8f96d977..40439fb2 100644
--- a/include/ipc.h
+++ b/include/ipc.h
@@ -9,6 +9,8 @@
 #include <l4/ipc.h>
 #include <types.h>
 
+typedef struct tcb tcb_t;
+
 void sys_ipc(uint32_t *param1);
 uint32_t ipc_deliver(void *data);
 
diff --git a/include/kip.h b/include/kip.h
index bde7850b..7085df37 100644
--- a/include/kip.h
+++ b/include/kip.h
@@ -6,8 +6,8 @@
 #ifndef KIP_H_
 #define KIP_H_
 
-#include <stdint.h>
 #include <l4/kip.h>
+#include <stdint.h>
 
 extern kip_t kip;
 extern kip_mem_desc_t *mem_desc;
diff --git a/include/kprobes.h b/include/kprobes.h
index 92297e92..32e63e38 100644
--- a/include/kprobes.h
+++ b/include/kprobes.h
@@ -6,49 +6,52 @@
 #ifndef KPROBES_H
 #define KPROBES_H
 
-#include <types.h>
 #include <platform/breakpoint.h>
+#include <types.h>
 
-#define is_thumb32(inst) ((unsigned)(inst) >= 0xe800)
+#define is_thumb32(inst) ((unsigned) (inst) >= 0xe800)
 
 enum kp_register_t {
-	/* Saved by DebugMon Handler */
-	KP_REG_R4,
-	KP_REG_R5,
-	KP_REG_R6,
-	KP_REG_R7,
-	KP_REG_R8,
-	KP_REG_R9,
-	KP_REG_R10,
-	KP_REG_R11,
+    /* Saved by DebugMon Handler */
+    KP_REG_R4,
+    KP_REG_R5,
+    KP_REG_R6,
+    KP_REG_R7,
+    KP_REG_R8,
+    KP_REG_R9,
+    KP_REG_R10,
+    KP_REG_R11,
 };
 
 struct kprobe;
 struct kretprobe;
 
-typedef int (*kprobe_pre_handler_t) (struct kprobe *kp, uint32_t *stack,
-				     uint32_t *kp_regs);
-typedef int (*kprobe_post_handler_t) (struct kprobe *kp, uint32_t *stack,
-				      uint32_t *kp_regs);
-typedef int (*kretprobe_handler_t) (struct kprobe *kp, uint32_t *stack,
-				      uint32_t *kp_regs);
+typedef int (*kprobe_pre_handler_t)(struct kprobe *kp,
+                                    uint32_t *stack,
+                                    uint32_t *kp_regs);
+typedef int (*kprobe_post_handler_t)(struct kprobe *kp,
+                                     uint32_t *stack,
+                                     uint32_t *kp_regs);
+typedef int (*kretprobe_handler_t)(struct kprobe *kp,
+                                   uint32_t *stack,
+                                   uint32_t *kp_regs);
 
 struct kprobe {
-	void *addr;
-	kprobe_pre_handler_t pre_handler;
-	kprobe_post_handler_t post_handler;
-	struct breakpoint *bkpt;
-	void *step_addr;
-	struct kprobe *next;
+    void *addr;
+    kprobe_pre_handler_t pre_handler;
+    kprobe_post_handler_t post_handler;
+    struct breakpoint *bkpt;
+    void *step_addr;
+    struct kprobe *next;
 };
 
 int kprobe_register(struct kprobe *p);
 int kprobe_unregister(struct kprobe *p);
 
 struct kretprobe {
-	struct kprobe kp;
-	kretprobe_handler_t handler;
-	void *backup_addr;
+    struct kprobe kp;
+    kretprobe_handler_t handler;
+    void *backup_addr;
 };
 
 int kretprobe_register(struct kretprobe *p);
diff --git a/include/ksym.h b/include/ksym.h
index 507f4b0c..18941a88 100644
--- a/include/ksym.h
+++ b/include/ksym.h
@@ -10,8 +10,8 @@
 #define MAX_KSYM 512
 
 typedef struct ksym {
-	void *addr;
-	int strid;
+    void *addr;
+    int strid;
 } ksym_t;
 
 void ksym_init(void);
diff --git a/include/ktimer.h b/include/ktimer.h
index adf3604a..0c1a5edc 100644
--- a/include/ktimer.h
+++ b/include/ktimer.h
@@ -6,6 +6,8 @@
 #ifndef KTIMER_H_
 #define KTIMER_H_
 
+#include <types.h>
+
 void ktimer_handler(void);
 
 /* Returns 0 if successfully handled
@@ -15,11 +17,11 @@ typedef uint32_t (*ktimer_event_handler_t)(void *data);
 
 
 typedef struct ktimer_event {
-	struct ktimer_event *next;
-	ktimer_event_handler_t handler;
+    struct ktimer_event *next;
+    ktimer_event_handler_t handler;
 
-	uint32_t delta;
-	void *data;
+    uint32_t delta;
+    void *data;
 } ktimer_event_t;
 
 void ktimer_event_init(void);
diff --git a/include/l4/ipc.h b/include/l4/ipc.h
index 2d37aa4b..cfccae99 100644
--- a/include/l4/ipc.h
+++ b/include/l4/ipc.h
@@ -7,47 +7,47 @@
 #define L4_IPC_H_
 
 #define IPC_TI_MAP_GRANT 0x8
-#define IPC_TI_GRANT 	 0x2
+#define IPC_TI_GRANT 0x2
 
-#define IPC_MR_COUNT	16
+#define IPC_MR_COUNT 16
 
 typedef union {
-	struct {
-		/* Number of words */
-		uint32_t n_untyped : 6;
-		uint32_t n_typed : 6;
-
-		uint32_t flags : 4;	/* Type of operation */
-		uint16_t label;
-	} s;
-	uint32_t raw;
+    struct {
+        /* Number of words */
+        uint32_t n_untyped : 6;
+        uint32_t n_typed : 6;
+
+        uint32_t flags : 4; /* Type of operation */
+        uint16_t label;
+    } s;
+    uint32_t raw;
 } ipc_msg_tag_t;
 
 typedef union {
-	struct {
-		uint32_t	header : 4;
-		uint32_t	dummy  : 28;
-	} s;
-	struct {
-		uint32_t	header : 4;
-		uint32_t	base  : 28;
-	} map;
-	uint32_t raw;
+    struct {
+        uint32_t header : 4;
+        uint32_t dummy : 28;
+    } s;
+    struct {
+        uint32_t header : 4;
+        uint32_t base : 28;
+    } map;
+    uint32_t raw;
 } ipc_typed_item;
 
 typedef union {
-	uint16_t raw;
-	struct {
-		uint32_t	m : 10;
-		uint32_t	e : 5;
-		uint32_t	a : 1;
-	} period;
-	struct {
-		uint32_t	m : 10;
-		uint32_t	c : 1;
-		uint32_t	e : 4;
-		uint32_t	a : 1;
-	} point;
+    uint16_t raw;
+    struct {
+        uint32_t m : 10;
+        uint32_t e : 5;
+        uint32_t a : 1;
+    } period;
+    struct {
+        uint32_t m : 10;
+        uint32_t c : 1;
+        uint32_t e : 4;
+        uint32_t a : 1;
+    } point;
 } ipc_time_t;
 
-#endif	/* L4_IPC_H_ */
+#endif /* L4_IPC_H_ */
diff --git a/include/l4/kip.h b/include/l4/kip.h
index eebbf41d..4febfffe 100644
--- a/include/l4/kip.h
+++ b/include/l4/kip.h
@@ -8,4 +8,4 @@
 
 #include <l4/kip_types.h>
 
-#endif	/* L4_KIP_H_ */
+#endif /* L4_KIP_H_ */
diff --git a/include/l4/kip_types.h b/include/l4/kip_types.h
index e0e67edb..940dc6e0 100644
--- a/include/l4/kip_types.h
+++ b/include/l4/kip_types.h
@@ -16,76 +16,76 @@
  * NOTE: kip_mem_desc_t differs from L4 X.2 standard
  */
 typedef struct {
-	uint32_t 	base;	/* Last 6 bits contains poolid */
-	uint32_t	size;	/* Last 6 bits contains tag */
+    uint32_t base; /* Last 6 bits contains poolid */
+    uint32_t size; /* Last 6 bits contains tag */
 } kip_mem_desc_t;
 
 typedef union {
-	struct {
-		uint8_t  version;
-		uint8_t  subversion;
-		uint8_t  reserved;
-	} s;
-	uint32_t raw;
+    struct {
+        uint8_t version;
+        uint8_t subversion;
+        uint8_t reserved;
+    } s;
+    uint32_t raw;
 } kip_apiversion_t;
 
 typedef union {
-	struct {
-		uint32_t  reserved : 28;
-		uint32_t  ww : 2;
-		uint32_t  ee : 2;
-	} s;
-	uint32_t raw;
+    struct {
+        uint32_t reserved : 28;
+        uint32_t ww : 2;
+        uint32_t ee : 2;
+    } s;
+    uint32_t raw;
 } kip_apiflags_t;
 
 typedef union {
-	struct {
-		uint16_t memory_desc_ptr;
-		uint16_t n;
-	} s;
-	uint32_t raw;
+    struct {
+        uint16_t memory_desc_ptr;
+        uint16_t n;
+    } s;
+    uint32_t raw;
 } kip_memory_info_t;
 
 typedef union {
-	struct {
-		uint32_t user_base;
-		uint32_t system_base;
-	} s;
-	uint32_t raw;
+    struct {
+        uint32_t user_base;
+        uint32_t system_base;
+    } s;
+    uint32_t raw;
 } kip_threadinfo_t;
 
 struct kip {
-	/* First 256 bytes of KIP are compliant with L4 reference
-	 * manual version X.2 and built in into flash (lower kip)
-	 */
-	uint32_t kernel_id;
-	kip_apiversion_t api_version;
-	kip_apiflags_t api_flags;
-	uint32_t kern_desc_ptr;
+    /* First 256 bytes of KIP are compliant with L4 reference
+     * manual version X.2 and built in into flash (lower kip)
+     */
+    uint32_t kernel_id;
+    kip_apiversion_t api_version;
+    kip_apiflags_t api_flags;
+    uint32_t kern_desc_ptr;
 
-	uint32_t reserved1[17];
+    uint32_t reserved1[17];
 
-	kip_memory_info_t memory_info;
+    kip_memory_info_t memory_info;
 
-	uint32_t reserved2[20];
+    uint32_t reserved2[20];
 
-	uint32_t utcb_info;		/* Unimplemented */
-	uint32_t kip_area_info;		/* Unimplemented */
+    uint32_t utcb_info;     /* Unimplemented */
+    uint32_t kip_area_info; /* Unimplemented */
 
-	uint32_t reserved3[2];
+    uint32_t reserved3[2];
 
-	uint32_t boot_info;		/* Unimplemented */
-	uint32_t proc_desc_ptr;		/* Unimplemented */
-	uint32_t clock_info;		/* Unimplemented */
-	kip_threadinfo_t thread_info;
-	uint32_t processor_info;	/* Unimplemented */
+    uint32_t boot_info;     /* Unimplemented */
+    uint32_t proc_desc_ptr; /* Unimplemented */
+    uint32_t clock_info;    /* Unimplemented */
+    kip_threadinfo_t thread_info;
+    uint32_t processor_info; /* Unimplemented */
 
-	/* Syscalls are ignored because we use SVC/PendSV instead of
-	 * mapping SC into thread's address space
-	 */
-	uint32_t syscalls[12];
+    /* Syscalls are ignored because we use SVC/PendSV instead of
+     * mapping SC into thread's address space
+     */
+    uint32_t syscalls[12];
 };
 
 typedef struct kip kip_t;
 
-#endif	/* L4_KIP_TYPES_H_ */
+#endif /* L4_KIP_TYPES_H_ */
diff --git a/include/l4/thread.h b/include/l4/thread.h
index 4eb88833..dc0fad32 100644
--- a/include/l4/thread.h
+++ b/include/l4/thread.h
@@ -9,17 +9,18 @@
 #include <platform/armv7m.h>
 #include <platform/link.h>
 
-#define L4_NILTHREAD		0
-#define L4_ANYTHREAD		0xFFFFFFFF
+#define L4_NILTHREAD 0
+#define L4_ANYTHREAD 0xFFFFFFFF
 
-#define DECLARE_THREAD(name, sub) \
-	void name(void) __attribute__ ((naked));	\
-	void __USER_TEXT name(void)			\
-	{						\
-		register void *kip_ptr asm ("r0");	\
-		register void *utcb_ptr asm ("r1");	\
-		sub(kip_ptr, utcb_ptr);			\
-		while (1);				\
-	}
+#define DECLARE_THREAD(name, sub)           \
+    void name(void) __attribute__((naked)); \
+    void __USER_TEXT name(void)             \
+    {                                       \
+        register void *kip_ptr asm("r0");   \
+        register void *utcb_ptr asm("r1");  \
+        sub(kip_ptr, utcb_ptr);             \
+        while (1)                           \
+            ;                               \
+    }
 
-#endif	/* L4_THREAD_H_ */
+#endif /* L4_THREAD_H_ */
diff --git a/include/l4/utcb.h b/include/l4/utcb.h
index 0dca63a8..8c425796 100644
--- a/include/l4/utcb.h
+++ b/include/l4/utcb.h
@@ -9,33 +9,33 @@
 #include <types.h>
 
 struct utcb {
-/* +0w */
-	l4_thread_t t_globalid;
-	uint32_t	processor_no;
-	uint32_t 	user_defined_handle;	/* NOT used by kernel */
-	l4_thread_t	t_pager;
-/* +4w */
-	uint32_t	exception_handler;
-	uint32_t	flags;		/* COP/PREEMPT flags (not used) */
-	uint32_t	xfer_timeouts;
-	uint32_t	error_code;
-/* +8w */
-	l4_thread_t	intended_receiver;
-	l4_thread_t	sender;
-	uint32_t	thread_word_1;
-	uint32_t	thread_word_2;
-/* +12w */
-	uint32_t	mr[8];		/* MRs 8-15 (0-8 are laying in
-					   r4..r11 [thread's context]) */
-/* +20w */
-	uint32_t	br[8];
-/* +28w */
-	uint32_t	reserved[4];
-/* +32w */
+    /* +0w */
+    l4_thread_t t_globalid;
+    uint32_t processor_no;
+    uint32_t user_defined_handle; /* NOT used by kernel */
+    l4_thread_t t_pager;
+    /* +4w */
+    uint32_t exception_handler;
+    uint32_t flags; /* COP/PREEMPT flags (not used) */
+    uint32_t xfer_timeouts;
+    uint32_t error_code;
+    /* +8w */
+    l4_thread_t intended_receiver;
+    l4_thread_t sender;
+    uint32_t thread_word_1;
+    uint32_t thread_word_2;
+    /* +12w */
+    uint32_t mr[8]; /* MRs 8-15 (0-8 are laying in
+               r4..r11 [thread's context]) */
+                    /* +20w */
+    uint32_t br[8];
+    /* +28w */
+    uint32_t reserved[4];
+    /* +32w */
 };
 
 typedef struct utcb utcb_t;
 
-#define UTCB_SIZE		128
+#define UTCB_SIZE 128
 
-#endif	/* L4_UTCB_H_ */
+#endif /* L4_UTCB_H_ */
diff --git a/include/lib/bitmap.h b/include/lib/bitmap.h
index fd23bc74..f5e72563 100644
--- a/include/lib/bitmap.h
+++ b/include/lib/bitmap.h
@@ -6,8 +6,8 @@
 #ifndef LIB_BITMAP_H_
 #define LIB_BITMAP_H_
 
-#include <platform/link.h>
 #include <platform/bitops.h>
+#include <platform/link.h>
 #include <types.h>
 
 /**
@@ -22,9 +22,9 @@
  * it is simply number of bit.
  */
 
-#define BITMAP_ALIGN	32
+#define BITMAP_ALIGN 32
 #define DECLARE_BITMAP(name, size) \
-	static __BITMAP uint32_t name [ALIGNED(size, BITMAP_ALIGN)];
+    static __BITMAP uint32_t name[ALIGNED(size, BITMAP_ALIGN)];
 
 typedef uint32_t *bitmap_ptr_t;
 
@@ -33,87 +33,82 @@ typedef uint32_t *bitmap_ptr_t;
 typedef uint8_t *bitmap_cursor_t;
 
 /* Generate address in bit-band region */
-#define BITBAND_ADDR_SHIFT 	5
-#define ADDR_BITBAND(addr) \
-	(bitmap_cursor_t) (0x22000000 + \
-	                   ((((ptr_t) addr) & 0xFFFFF) << BITBAND_ADDR_SHIFT))
-#define BIT_SHIFT	 		2
-
-#define bitmap_cursor(bitmap, bit) \
-	((ADDR_BITBAND(bitmap) + (bit << BIT_SHIFT)))
-#define bitmap_cursor_id(cursor) \
-	(((ptr_t) cursor & ((1 << (BITBAND_ADDR_SHIFT + BIT_SHIFT)) - 1)) >> BIT_SHIFT)
-#define bitmap_cursor_goto_next(cursor) \
-	cursor += 1 << BIT_SHIFT
+#define BITBAND_ADDR_SHIFT 5
+#define ADDR_BITBAND(addr)         \
+    (bitmap_cursor_t)(0x22000000 + \
+                      ((((ptr_t) addr) & 0xFFFFF) << BITBAND_ADDR_SHIFT))
+#define BIT_SHIFT 2
+
+#define bitmap_cursor(bitmap, bit) ((ADDR_BITBAND(bitmap) + (bit << BIT_SHIFT)))
+#define bitmap_cursor_id(cursor)                                         \
+    (((ptr_t) cursor & ((1 << (BITBAND_ADDR_SHIFT + BIT_SHIFT)) - 1)) >> \
+     BIT_SHIFT)
+#define bitmap_cursor_goto_next(cursor) cursor += 1 << BIT_SHIFT
 
 static inline void bitmap_set_bit(bitmap_cursor_t cursor)
 {
-	*cursor = 1;
+    *cursor = 1;
 }
 
 static inline void bitmap_clear_bit(bitmap_cursor_t cursor)
 {
-	*cursor = 0;
+    *cursor = 0;
 }
 
 static inline int bitmap_get_bit(bitmap_cursor_t cursor)
 {
-	return *cursor;
+    return *cursor;
 }
 
 static inline int bitmap_test_and_set_bit(bitmap_cursor_t cursor)
 {
-	return test_and_set_word((uint32_t *) cursor);
+    return test_and_set_word((uint32_t *) cursor);
 }
 
 #else
 
 typedef struct {
-	bitmap_ptr_t bc_bitmap;
-	int bc_bit;
+    bitmap_ptr_t bc_bitmap;
+    int bc_bit;
 } bitmap_cursor_t;
 
-#define bitmap_cursor(bitmap, bit) \
-	(bitmap_cursor_t) { .bc_bitmap = bitmap, .bc_bit = bit }
-#define bitmap_cursor_id(cursor) \
-	cursor.bc_bit
-#define bitmap_cursor_goto_next(cursor) \
-	cursor.bc_bit++
-
-#define BITOFF(bit) \
-	(bit % BITMAP_ALIGN)		/* bit offset inside 32-bit word */
-#define BITMASK(bit) \
-	(1 << BITOFF(bit))		/* Mask used for bit number N */
-#define BITINDEX(bit) \
-	(bit / BITMAP_ALIGN)		/* Bit index in bitmap array */
-#define BITWORD(cursor) \
-	cursor.bc_bitmap[BITINDEX(cursor.bc_bit)]
+#define bitmap_cursor(bitmap, bit)         \
+    (bitmap_cursor_t)                      \
+    {                                      \
+        .bc_bitmap = bitmap, .bc_bit = bit \
+    }
+#define bitmap_cursor_id(cursor) cursor.bc_bit
+#define bitmap_cursor_goto_next(cursor) cursor.bc_bit++
+
+#define BITOFF(bit) (bit % BITMAP_ALIGN)   /* bit offset inside 32-bit word */
+#define BITMASK(bit) (1 << BITOFF(bit))    /* Mask used for bit number N */
+#define BITINDEX(bit) (bit / BITMAP_ALIGN) /* Bit index in bitmap array */
+#define BITWORD(cursor) cursor.bc_bitmap[BITINDEX(cursor.bc_bit)]
 
 static inline void bitmap_set_bit(bitmap_cursor_t cursor)
 {
-	BITWORD(cursor) |= BITMASK(cursor.bc_bit);
+    BITWORD(cursor) |= BITMASK(cursor.bc_bit);
 }
 
 static inline void bitmap_clear_bit(bitmap_cursor_t cursor)
 {
-	BITWORD(cursor) &= ~BITMASK(cursor.bc_bit);
+    BITWORD(cursor) &= ~BITMASK(cursor.bc_bit);
 }
 
 static inline int bitmap_get_bit(bitmap_cursor_t cursor)
 {
-	return (BITWORD(cursor) >> BITOFF(cursor.bc_bit)) & 0x1;
+    return (BITWORD(cursor) >> BITOFF(cursor.bc_bit)) & 0x1;
 }
 
 static inline int bitmap_test_and_set_bit(bitmap_cursor_t cursor)
 {
-	return test_and_set_bit(&BITWORD(cursor), BITMASK(cursor.bc_bit));
+    return test_and_set_bit(&BITWORD(cursor), BITMASK(cursor.bc_bit));
 }
 
 #endif
 
 #define for_each_in_bitmap(cursor, bitmap, size, start) \
-	for (cursor = bitmap_cursor(bitmap, start); \
-	     bitmap_cursor_id(cursor) < size;	\
-	     bitmap_cursor_goto_next(cursor))
+    for (cursor = bitmap_cursor(bitmap, start);         \
+         bitmap_cursor_id(cursor) < size; bitmap_cursor_goto_next(cursor))
 
 #endif /* LIB_BITMAP_H_ */
diff --git a/include/lib/ktable.h b/include/lib/ktable.h
index 114d4812..8dc4942e 100644
--- a/include/lib/ktable.h
+++ b/include/lib/ktable.h
@@ -6,36 +6,35 @@
 #ifndef LIB_KTABLE_H_
 #define LIB_KTABLE_H_
 
+#include <lib/bitmap.h>
 #include <platform/armv7m.h>
 #include <platform/link.h>
-#include <lib/bitmap.h>
 #include <types.h>
 
 struct ktable {
-	char *tname;
-	bitmap_ptr_t bitmap;
-	ptr_t data;
-	size_t num;
-	size_t size;
+    char *tname;
+    bitmap_ptr_t bitmap;
+    ptr_t data;
+    size_t num;
+    size_t size;
 };
 
 typedef struct ktable ktable_t;
 
-#define DECLARE_KTABLE(type, name, num_)			\
-	DECLARE_BITMAP(kt_ ## name ## _bitmap, num_);		\
-	static __KTABLE type kt_ ## name ## _data[num_];	\
-	ktable_t name = {					\
-			.tname = #name,				\
-			.bitmap = kt_ ## name ## _bitmap,	\
-			.data = (ptr_t) kt_ ## name ## _data,	\
-			.num = num_, .size = sizeof(type)	\
-	}
+#define DECLARE_KTABLE(type, name, num_)               \
+    DECLARE_BITMAP(kt_##name##_bitmap, num_);          \
+    static __KTABLE type kt_##name##_data[num_];       \
+    ktable_t name = {.tname = #name,                   \
+                     .bitmap = kt_##name##_bitmap,     \
+                     .data = (ptr_t) kt_##name##_data, \
+                     .num = num_,                      \
+                     .size = sizeof(type)}
 
 void ktable_init(ktable_t *kt);
 int ktable_is_allocated(ktable_t *kt, int i);
 void *ktable_alloc_id(ktable_t *kt, int i);
 void *ktable_alloc(ktable_t *kt);
-void  ktable_free(ktable_t *kt, void *element);
+void ktable_free(ktable_t *kt, void *element);
 
 uint32_t ktable_getid(ktable_t *kt, void *element);
 
@@ -50,8 +49,8 @@ uint32_t ktable_getid(ktable_t *kt, void *element);
  * 	 ...
  * }
  * */
-#define for_each_in_ktable(el, idx, kt)	\
-	for (el = (typeof(el)) (kt)->data, idx = 0; idx < (kt)->num; ++idx, ++el) \
-		if (bitmap_get_bit(bitmap_cursor((kt)->bitmap, idx)) == 1)
+#define for_each_in_ktable(el, idx, kt)                                       \
+    for (el = (typeof(el)) (kt)->data, idx = 0; idx < (kt)->num; ++idx, ++el) \
+        if (bitmap_get_bit(bitmap_cursor((kt)->bitmap, idx)) == 1)
 
 #endif /* LIB_KTABLE_H_ */
diff --git a/include/lib/queue.h b/include/lib/queue.h
index e578cbb7..adc8093b 100644
--- a/include/lib/queue.h
+++ b/include/lib/queue.h
@@ -8,18 +8,18 @@
 
 #include <types.h>
 
-#define QUEUE_OK		0x0
-#define	QUEUE_OVERFLOW		0x1
-#define	QUEUE_EMPTY		0x2
+#define QUEUE_OK 0x0
+#define QUEUE_OVERFLOW 0x1
+#define QUEUE_EMPTY 0x2
 
 /**
  * Queue control block
  */
 struct queue_t {
-	uint8_t *data;		/*!< pointer to the starting position of buffer */
-	uint32_t top;		/*!< queue top */
-	uint32_t end;		/*!< queue end */
-	size_t size;		/*!< the size of the allocated queue */
+    uint8_t *data; /*!< pointer to the starting position of buffer */
+    uint32_t top;  /*!< queue top */
+    uint32_t end;  /*!< queue end */
+    size_t size;   /*!< the size of the allocated queue */
 };
 
 /**
diff --git a/include/lib/stdarg.h b/include/lib/stdarg.h
index 71031303..0b370f95 100644
--- a/include/lib/stdarg.h
+++ b/include/lib/stdarg.h
@@ -5,9 +5,9 @@
 
 typedef __builtin_va_list va_list;
 
-#define va_start(v,l)	__builtin_va_start((v),l)
-#define va_end(v)	__builtin_va_end(v)
-#define va_arg(v,l)	__builtin_va_arg((v),l)
+#define va_start(v, l) __builtin_va_start((v), l)
+#define va_end(v) __builtin_va_end(v)
+#define va_arg(v, l) __builtin_va_arg((v), l)
 
 #else
 
@@ -15,4 +15,4 @@ typedef __builtin_va_list va_list;
 
 #endif
 
-#endif	/* LIB_STDARG_H_ */
+#endif /* LIB_STDARG_H_ */
diff --git a/include/lib/stdio.h b/include/lib/stdio.h
index ed48e057..0429476c 100644
--- a/include/lib/stdio.h
+++ b/include/lib/stdio.h
@@ -6,14 +6,16 @@
 #ifndef LIB_STDIO_H_
 #define LIB_STDIO_H_
 
-#include <types.h>
 #include <lib/stdarg.h>
+#include <types.h>
 
-#define EOF     (-1)
+#define EOF (-1)
 
 #ifdef CONFIG_STDIO_NODEV
-#define __l4_putchar(chr)	do { } while (0)
-#define __l4_getchar()		(EOF)
+#define __l4_putchar(chr) \
+    do {                  \
+    } while (0)
+#define __l4_getchar() (EOF)
 #else
 void __l4_putchar(uint8_t chr);
 uint8_t __l4_getchar(void);
diff --git a/include/lib/stdlib.h b/include/lib/stdlib.h
index c836c63b..7fb2e854 100644
--- a/include/lib/stdlib.h
+++ b/include/lib/stdlib.h
@@ -6,9 +6,13 @@
 #ifndef LIB_STDLIB_H_
 #define LIB_STDLIB_H_
 
+#include <types.h>
+
 void sort(void *, size_t, size_t, int (*)(const void *, const void *));
-void *bsearch(const void *key, const void *base0,
-		size_t nmemb, size_t size,
-		int (*compar)(const void *, const void *));
+void *bsearch(const void *key,
+              const void *base0,
+              size_t nmemb,
+              size_t size,
+              int (*compar)(const void *, const void *));
 
 #endif
diff --git a/include/lib/string.h b/include/lib/string.h
index 70e40c47..7d59171a 100644
--- a/include/lib/string.h
+++ b/include/lib/string.h
@@ -3,8 +3,8 @@
  * found in the LICENSE file.
  */
 
-#ifndef	LIB_STRING_H_
-#define	LIB_STRING_H_
+#ifndef LIB_STRING_H_
+#define LIB_STRING_H_
 
 #include <types.h>
 
diff --git a/include/memory.h b/include/memory.h
index 33abb816..9918e01d 100644
--- a/include/memory.h
+++ b/include/memory.h
@@ -6,9 +6,9 @@
 #ifndef MEMORY_H_
 #define MEMORY_H_
 
-#include <types.h>
 #include <fpage.h>
 #include <platform/link.h>
+#include <types.h>
 
 /*
  * Each address space is associated with one or more thread.
@@ -18,12 +18,12 @@
 typedef enum { MAP, GRANT, UNMAP } map_action_t;
 
 typedef struct {
-	uint32_t as_spaceid;	/*! Space Identifier */
-	struct fpage *first;	/*! head of fpage list */
+    uint32_t as_spaceid; /*! Space Identifier */
+    struct fpage *first; /*! head of fpage list */
 
-	struct fpage *mpu_first;	/*! head of MPU fpage list */
-	struct fpage *mpu_stack_first;	/*! head of MPU stack fpage list */
-	uint32_t shared;	/*! Reference count: number of threads using this AS */
+    struct fpage *mpu_first;       /*! head of MPU fpage list */
+    struct fpage *mpu_stack_first; /*! head of MPU stack fpage list */
+    uint32_t shared; /*! Reference count: number of threads using this AS */
 } as_t;
 
 /*
@@ -44,38 +44,39 @@ void as_put(as_t *as);
  */
 typedef struct {
 #ifdef CONFIG_DEBUG
-	char *name;
+    char *name;
 #endif
 
-	memptr_t start;
-	memptr_t end;
+    memptr_t start;
+    memptr_t end;
 
-	uint32_t flags;
-	uint32_t tag;
+    uint32_t flags;
+    uint32_t tag;
 } mempool_t;
 
 /* Kernel permissions flags */
-#define MP_KR		0x0001
-#define MP_KW		0x0002
-#define MP_KX		0x0004
+#define MP_KR 0x0001
+#define MP_KW 0x0002
+#define MP_KX 0x0004
 
 /* Userspace permissions flags */
-#define MP_UR		0x0010
-#define MP_UW		0x0020
-#define MP_UX		0x0040
+#define MP_UR 0x0010
+#define MP_UW 0x0020
+#define MP_UX 0x0040
 
 /* Fpage type */
-#define MP_NO_FPAGE	0x0000		/*! Not mappable */
-#define MP_SRAM		0x0100		/*! Fpage in SRAM: granularity 1 << */
-#define MP_AHB_RAM	0x0200		/*! Fpage in AHB SRAM: granularity 64 words, bit bang mappings */
-#define MP_DEVICES	0x0400		/*! Fpage in AHB/APB0/AHB0: granularity 16 kB */
-#define MP_MEMPOOL	0x0800		/*! Entire mempool is mapped  */
+#define MP_NO_FPAGE 0x0000 /*! Not mappable */
+#define MP_SRAM 0x0100     /*! Fpage in SRAM: granularity 1 << */
+#define MP_AHB_RAM \
+    0x0200 /*! Fpage in AHB SRAM: granularity 64 words, bit bang mappings */
+#define MP_DEVICES 0x0400 /*! Fpage in AHB/APB0/AHB0: granularity 16 kB */
+#define MP_MEMPOOL 0x0800 /*! Entire mempool is mapped  */
 
 /* Map memory from mempool always (for example text is mapped always because
  * without it thread couldn't run)
  * other fpages mapped on request because we limited in MPU resources)
  */
-#define MP_MAP_ALWAYS 	0x1000
+#define MP_MAP_ALWAYS 0x1000
 
 /*
  * MP_FPAGE_MASK: Bitmask for fpage type flags (bits 8-11).
@@ -83,7 +84,7 @@ typedef struct {
  * Mempools with MP_NO_FPAGE (0x0000) cannot have fpages allocated from them.
  * Used to protect kernel memory (KTEXT, KDATA, KBSS) from being mapped.
  */
-#define MP_FPAGE_MASK	0x0F00
+#define MP_FPAGE_MASK 0x0F00
 
 #define MP_USER_PERM(mpflags) ((mpflags & 0xF0) >> 4)
 
@@ -91,43 +92,35 @@ typedef struct {
 #define INVALID_FPAGE_REGION 0xffffffff
 
 typedef enum {
-	MPT_KERNEL_TEXT,
-	MPT_KERNEL_DATA,
-	MPT_USER_TEXT,
-	MPT_USER_DATA,
-	MPT_AVAILABLE,
-	MPT_DEVICES,
-	MPT_UNKNOWN = -1
+    MPT_KERNEL_TEXT,
+    MPT_KERNEL_DATA,
+    MPT_USER_TEXT,
+    MPT_USER_DATA,
+    MPT_AVAILABLE,
+    MPT_DEVICES,
+    MPT_UNKNOWN = -1
 } mempool_tag_t;
 
 /* If fpage_size = 0, memory is not allocable */
 #ifdef CONFIG_DEBUG
 #define DECLARE_MEMPOOL(name_, start_, end_, flags_, tag_) \
-{						\
-	.name = name_,				\
-	.start = (memptr_t) (start_),		\
-	.end  = (memptr_t) (end_),		\
-	.flags = flags_,			\
-	.tag = tag_				\
-}
+    {.name = name_,                                        \
+     .start = (memptr_t) (start_),                         \
+     .end = (memptr_t) (end_),                             \
+     .flags = flags_,                                      \
+     .tag = tag_}
 #else
-#define DECLARE_MEMPOOL(name_, start_, end_, flags_, tag_) 	\
-{						\
-	.start = (memptr_t) (start_),		\
-	.end  = (memptr_t) (end_),		\
-	.flags = flags_,			\
-	.tag = tag_				\
-}
+#define DECLARE_MEMPOOL(name_, start_, end_, flags_, tag_) \
+    {.start = (memptr_t) (start_),                         \
+     .end = (memptr_t) (end_),                             \
+     .flags = flags_,                                      \
+     .tag = tag_}
 #endif
 
 #define DECLARE_MEMPOOL_2(name, prefix, flags, tag) \
-	DECLARE_MEMPOOL(name, \
-			&(prefix ## _start), &(prefix ## _end), flags, tag)
+    DECLARE_MEMPOOL(name, &(prefix##_start), &(prefix##_end), flags, tag)
 
-typedef enum {
-	MPU_DISABLED,
-	MPU_ENABLED
-} mpu_state_t;
+typedef enum { MPU_DISABLED, MPU_ENABLED } mpu_state_t;
 
 void memory_init(void);
 
@@ -143,13 +136,20 @@ mempool_t *mempool_getbyid(int mpid);
  */
 int addr_is_fpage_aligned(memptr_t addr);
 
-int map_area(as_t *src, as_t *dst, memptr_t base, size_t size,
-		map_action_t action, int is_privileged);
+int map_area(as_t *src,
+             as_t *dst,
+             memptr_t base,
+             size_t size,
+             map_action_t action,
+             int is_privileged);
 
 as_t *as_create(uint32_t as_spaceid);
 void as_destroy(as_t *as);
-void as_setup_mpu(as_t *as, memptr_t sp, memptr_t pc,
-		memptr_t stack_base, size_t stack_size);
+void as_setup_mpu(as_t *as,
+                  memptr_t sp,
+                  memptr_t pc,
+                  memptr_t stack_base,
+                  size_t stack_size);
 void as_map_user(as_t *as);
 void as_map_ktext(as_t *as);
 
diff --git a/include/platform/armv7m.h b/include/platform/armv7m.h
index 00b125f4..c5086510 100644
--- a/include/platform/armv7m.h
+++ b/include/platform/armv7m.h
@@ -10,37 +10,35 @@
 
 static inline void wait_for_interrupt(void)
 {
-	__asm__ __volatile__ ("wfi");
+    __asm__ __volatile__("wfi");
 }
 
 static inline uint32_t read_msp(void)
 {
-	uint32_t result;
+    uint32_t result;
 
-	__asm__ __volatile__ (
-		"mrs r0, msp\n"
-		"mov %0, r0"
-		: "=r"(result)
-		:
-		: "r0"
-	);
+    __asm__ __volatile__(
+        "mrs r0, msp\n"
+        "mov %0, r0"
+        : "=r"(result)
+        :
+        : "r0");
 
-	return result;
+    return result;
 }
 
 enum register_stack_t {
-	/* Saved by hardware */
-	REG_R0,
-	REG_R1,
-	REG_R2,
-	REG_R3,
-	REG_R12,
-	REG_LR,
-	REG_PC,
-	REG_xPSR
+    /* Saved by hardware */
+    REG_R0,
+    REG_R1,
+    REG_R2,
+    REG_R3,
+    REG_R12,
+    REG_LR,
+    REG_PC,
+    REG_xPSR
 };
 
-#define RESERVED_STACK \
-	(8 * sizeof(uint32_t))
+#define RESERVED_STACK (8 * sizeof(uint32_t))
 
-#endif	/* PLATFORM_ARMV7M_H_ */
+#endif /* PLATFORM_ARMV7M_H_ */
diff --git a/include/platform/bitops.h b/include/platform/bitops.h
index 7609ce35..1a0a9828 100644
--- a/include/platform/bitops.h
+++ b/include/platform/bitops.h
@@ -8,11 +8,11 @@
 
 #include <types.h>
 
-typedef	uint32_t atomic_t;
+typedef uint32_t atomic_t;
 
 /* Atomic ops */
 void atomic_set(atomic_t *atom, atomic_t newval);
-uint32_t atomic_get(atomic_t* atom);
+uint32_t atomic_get(atomic_t *atom);
 
 uint32_t test_and_set_word(uint32_t *word);
 uint32_t test_and_set_bit(uint32_t *word, int bitmask);
diff --git a/include/platform/breakpoint-hard.h b/include/platform/breakpoint-hard.h
index 2265b1a2..117125f4 100644
--- a/include/platform/breakpoint-hard.h
+++ b/include/platform/breakpoint-hard.h
@@ -1,6 +1,10 @@
 #ifndef PLATFORM_HARD_BREAKPOINT_H_
 #define PLATFORM_HARD_BREAKPOINT_H_
 
+#include <types.h>
+
+struct breakpoint;
+
 void hard_breakpoint_pool_init(void);
 struct breakpoint *hard_breakpoint_config(uint32_t addr, struct breakpoint *b);
 #endif
diff --git a/include/platform/breakpoint-soft.h b/include/platform/breakpoint-soft.h
index 9ff7319e..1872ea40 100644
--- a/include/platform/breakpoint-soft.h
+++ b/include/platform/breakpoint-soft.h
@@ -1,6 +1,10 @@
 #ifndef PLATFORM_SOFT_BREAKPOINT_H_
 #define PLATFORM_SOFT_BREAKPOINT_H_
 
+#include <types.h>
+
+struct breakpoint;
+
 void soft_breakpoint_pool_init(void);
 struct breakpoint *soft_breakpoint_config(uint32_t addr, struct breakpoint *b);
 #endif
diff --git a/include/platform/breakpoint.h b/include/platform/breakpoint.h
index fb161860..941f7a7a 100644
--- a/include/platform/breakpoint.h
+++ b/include/platform/breakpoint.h
@@ -5,35 +5,38 @@
 #ifndef BREAKPOINT_H_
 #define BREAKPOINT_H_
 
+#include <types.h>
+
 enum {
-	BKPT_NONE,
-	BKPT_HARD,
-	BKPT_SOFT,
+    BKPT_NONE,
+    BKPT_HARD,
+    BKPT_SOFT,
 };
 
-struct breakpoint{
-	uint16_t type;
-	union{
-		uint16_t hard_breakpoint_id;
-		uint16_t back_instr;
-		uint16_t raw_data;
-	};
-	uint32_t addr;
-	void (*enable)(struct breakpoint *b);
-	void (*disable)(struct breakpoint *b);
-	void (*release)(struct breakpoint *b);
+struct breakpoint {
+    uint16_t type;
+    union {
+        uint16_t hard_breakpoint_id;
+        uint16_t back_instr;
+        uint16_t raw_data;
+    };
+    uint32_t addr;
+    void (*enable)(struct breakpoint *b);
+    void (*disable)(struct breakpoint *b);
+    void (*release)(struct breakpoint *b);
 };
 
 void breakpoint_pool_init(void);
 
 struct breakpoint *breakpoint_install(uint32_t addr);
-void breakpoint_uninstall(struct breakpoint* b);
+void breakpoint_uninstall(struct breakpoint *b);
 
 int get_breakpoint_id(struct breakpoint *b);
 
 void enable_breakpoint(struct breakpoint *b);
 void disable_breakpoint(struct breakpoint *b);
 
-#define BKPT_MAX_NUM	10
-#define breakpoint_type_by_addr(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
+#define BKPT_MAX_NUM 10
+#define breakpoint_type_by_addr(addr) \
+    ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
 #endif
diff --git a/include/platform/cortex_m.h b/include/platform/cortex_m.h
index f7c89d8b..78d4ef6a 100644
--- a/include/platform/cortex_m.h
+++ b/include/platform/cortex_m.h
@@ -8,211 +8,343 @@
  * the block contains no instructions, the compiler may
  * not optimize it away, and is told that the value may
  * change and should not be relied upon. */
-inline void READ_AND_DISCARD(volatile uint32_t *reg) __attribute__((always_inline));
-inline void READ_AND_DISCARD(volatile uint32_t *reg) {
-    asm volatile ("" : "=m" (*reg) : "r" (*reg));
+inline void READ_AND_DISCARD(volatile uint32_t *reg)
+    __attribute__((always_inline));
+inline void READ_AND_DISCARD(volatile uint32_t *reg)
+{
+    asm volatile("" : "=m"(*reg) : "r"(*reg));
 }
 
 inline uint8_t FAULTMASK(void) __attribute__((always_inline));
-inline uint8_t FAULTMASK(void) {
+inline uint8_t FAULTMASK(void)
+{
     uint8_t val;
 
-    asm("mrs    %[val], faultmask"
-        :[val] "=r" (val)
-        ::);
+    asm("mrs    %[val], faultmask" : [val] "=r"(val)::);
 
     return val;
 }
 
 inline uint8_t IPSR(void) __attribute__((always_inline));
-inline uint8_t IPSR(void) {
+inline uint8_t IPSR(void)
+{
     uint8_t val;
 
-    asm("mrs    %[val], ipsr"
-        :[val] "=r" (val)
-        ::);
+    asm("mrs    %[val], ipsr" : [val] "=r"(val)::);
 
     return val;
 }
 
 inline uint32_t *PSP(void) __attribute__((always_inline));
-inline uint32_t *PSP(void) {
+inline uint32_t *PSP(void)
+{
     uint32_t *val;
 
-    asm("mrs    %[val], psp"
-        :[val] "=r" (val)
-        ::);
+    asm("mrs    %[val], psp" : [val] "=r"(val)::);
 
     return val;
 }
 
 inline uint32_t *MSP(void) __attribute__((always_inline));
-inline uint32_t *MSP(void) {
+inline uint32_t *MSP(void)
+{
     uint32_t *val;
 
-    asm("mrs    %[val], msp"
-        :[val] "=r" (val)
-        ::);
+    asm("mrs    %[val], msp" : [val] "=r"(val)::);
 
     return val;
 }
 
 /* Memory barriers required after MPU updates */
 inline void __DSB(void) __attribute__((always_inline));
-inline void __DSB(void) {
-    asm volatile ("dsb" ::: "memory");
+inline void __DSB(void)
+{
+    asm volatile("dsb" ::: "memory");
 }
 
 inline void __ISB(void) __attribute__((always_inline));
-inline void __ISB(void) {
-    asm volatile ("isb" ::: "memory");
+inline void __ISB(void)
+{
+    asm volatile("isb" ::: "memory");
 }
 
 /* Cortex M4 General Registers */
 
 /* System Control Map */
-#define SCS_BASE                        (uint32_t) (0xE000E000)                                 /* System Control Space Base Address */
-#define SYSTICK_BASE                    (SCS_BASE + 0x0010)                                     /* Systick Registers Base Address */
-#define NVIC_BASE                       (SCS_BASE + 0x0100)                                     /* Nested Vector Interrupt Control */
-#define SCB_BASE                        (SCS_BASE + 0x0D00)                                     /* System Control Block Base Address */
-#define DCB_BASE                        (SCS_BASE + 0x0DF0)                                     /* Debug Control Block Base Address */
-#define MPU_BASE                        (SCB_BASE + 0x0090)                                     /* MPU Block Base Address */
-#define FPU_BASE                        (SCB_BASE + 0x0230)                                     /* FPU Block Base Address */
+#define SCS_BASE                                                              \
+    (uint32_t) (0xE000E000)              /* System Control Space Base Address \
+                                          */
+#define SYSTICK_BASE (SCS_BASE + 0x0010) /* Systick Registers Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100)    /* Nested Vector Interrupt Control */
+#define SCB_BASE (SCS_BASE + 0x0D00)     /* System Control Block Base Address */
+#define DCB_BASE (SCS_BASE + 0x0DF0)     /* Debug Control Block Base Address */
+#define MPU_BASE (SCB_BASE + 0x0090)     /* MPU Block Base Address */
+#define FPU_BASE (SCB_BASE + 0x0230)     /* FPU Block Base Address */
 
 /* SysTick Timer */
-#define SYSTICK_CTL                     (volatile uint32_t *) (SYSTICK_BASE)                    /* Control register for SysTick timer peripheral */
-#define SYSTICK_RELOAD                  (volatile uint32_t *) (SYSTICK_BASE + 0x04)             /* Value assumed by timer upon reload */
-#define SYSTICK_VAL                     (volatile uint32_t *) (SYSTICK_BASE + 0x08)             /* Current value of timer */
-#define SYSTICK_CAL                     (volatile uint32_t *) (SYSTICK_BASE + 0x0C)             /* Calibration settings/value register */
+#define SYSTICK_CTL    \
+    (volatile uint32_t \
+         *) (SYSTICK_BASE) /* Control register for SysTick timer peripheral */
+#define SYSTICK_RELOAD                    \
+    (volatile uint32_t *) (SYSTICK_BASE + \
+                           0x04) /* Value assumed by timer upon reload */
+#define SYSTICK_VAL \
+    (volatile uint32_t *) (SYSTICK_BASE + 0x08) /* Current value of timer */
+#define SYSTICK_CAL                       \
+    (volatile uint32_t *) (SYSTICK_BASE + \
+                           0x0C) /* Calibration settings/value register */
 
 /* Nested Vector Interrupt Controller */
-#define NVIC_ISER0                      (volatile uint32_t *) (NVIC_BASE + 0x000)               /* Interrupt set-enable register 0 */
-#define NVIC_ISER1                      (volatile uint32_t *) (NVIC_BASE + 0x004)               /* Interrupt set-enable register 1 */
-#define NVIC_ISER2                      (volatile uint32_t *) (NVIC_BASE + 0x008)               /* Interrupt set-enable register 2 */
-#define NVIC_ISER3                      (volatile uint32_t *) (NVIC_BASE + 0x00C)               /* Interrupt set-enable register 3 */
-#define NVIC_ICER0                      (volatile uint32_t *) (NVIC_BASE + 0x080)               /* Interrupt clear-enable register 0 */
-#define NVIC_ICER1                      (volatile uint32_t *) (NVIC_BASE + 0x084)               /* Interrupt clear-enable register 1 */
-#define NVIC_ICER2                      (volatile uint32_t *) (NVIC_BASE + 0x088)               /* Interrupt clear-enable register 2 */
-#define NVIC_ISPR0                      (volatile uint32_t *) (NVIC_BASE + 0x100)               /* Interrupt set-pending register 0 */
-#define NVIC_ICPR0                      (volatile uint32_t *) (NVIC_BASE + 0x180)               /* Interrupt clear-pending register 0 */
-#define NVIC_ICPR1                      (volatile uint32_t *) (NVIC_BASE + 0x184)               /* Interrupt clear-pending register 1 */
-#define NVIC_ICPR2                      (volatile uint32_t *) (NVIC_BASE + 0x188)               /* Interrupt clear-pending register 2 */
-#define NVIC_IPR(n)                     (volatile uint8_t *)  (NVIC_BASE + 0x300 + n)           /* Interrupt n priority register */
+#define NVIC_ISER0                     \
+    (volatile uint32_t *) (NVIC_BASE + \
+                           0x000) /* Interrupt set-enable register 0 */
+#define NVIC_ISER1                     \
+    (volatile uint32_t *) (NVIC_BASE + \
+                           0x004) /* Interrupt set-enable register 1 */
+#define NVIC_ISER2                     \
+    (volatile uint32_t *) (NVIC_BASE + \
+                           0x008) /* Interrupt set-enable register 2 */
+#define NVIC_ISER3                     \
+    (volatile uint32_t *) (NVIC_BASE + \
+                           0x00C) /* Interrupt set-enable register 3 */
+#define NVIC_ICER0                     \
+    (volatile uint32_t *) (NVIC_BASE + \
+                           0x080) /* Interrupt clear-enable register 0 */
+#define NVIC_ICER1                     \
+    (volatile uint32_t *) (NVIC_BASE + \
+                           0x084) /* Interrupt clear-enable register 1 */
+#define NVIC_ICER2                     \
+    (volatile uint32_t *) (NVIC_BASE + \
+                           0x088) /* Interrupt clear-enable register 2 */
+#define NVIC_ISPR0                     \
+    (volatile uint32_t *) (NVIC_BASE + \
+                           0x100) /* Interrupt set-pending register 0 */
+#define NVIC_ICPR0                     \
+    (volatile uint32_t *) (NVIC_BASE + \
+                           0x180) /* Interrupt clear-pending register 0 */
+#define NVIC_ICPR1                     \
+    (volatile uint32_t *) (NVIC_BASE + \
+                           0x184) /* Interrupt clear-pending register 1 */
+#define NVIC_ICPR2                     \
+    (volatile uint32_t *) (NVIC_BASE + \
+                           0x188) /* Interrupt clear-pending register 2 */
+#define NVIC_IPR(n)                           \
+    (volatile uint8_t *) (NVIC_BASE + 0x300 + \
+                          n) /* Interrupt n priority register */
 
 /* System Control Block (SCB) */
-#define SCB_ICSR                        (volatile uint32_t *) (SCB_BASE + 0x004)                /* Interrupt Control and State Register */
-#define SCB_VTOR                        (volatile uint32_t *) (SCB_BASE + 0x008)                /* Vector Table Offset Register */
-#define SCB_AIRCR                       (volatile uint32_t *) (SCB_BASE + 0x00c)                /* Application Interrupt/Reset Control Register */
-#define SCB_SCR                         (volatile uint32_t *) (SCB_BASE + 0x010)                /* System Control Register */
-#define SCB_CCR                         (volatile uint32_t *) (SCB_BASE + 0x014)                /* Configuration and Control Register */
-#define SCB_SHPR                        (volatile uint8_t *)  (SCB_BASE + 0x018)                /* System Handler Priority Register */
-#define SCB_SHCSR                       (volatile uint32_t *) (SCB_BASE + 0x024)                /* System Handler Control and State Register */
-#define SCB_CFSR                        (volatile uint32_t *) (SCB_BASE + 0x028)                /* Configurable fault status register - Describes Usage, Bus, and Memory faults */
-#define SCB_HFSR                        (volatile uint32_t *) (SCB_BASE + 0x02C)                /* Hard fault status register - Describes hard fault */
-#define SCB_DFSR                        (volatile uint32_t *) (SCB_BASE + 0x030)                /* Debug fault status register -- Describes debug event */
-#define SCB_MMFAR                       (volatile uint32_t *) (SCB_BASE + 0x034)                /* Memory management fault address register - Address that caused fault */
-#define SCB_BFAR                        (volatile uint32_t *) (SCB_BASE + 0x038)                /* Bus fault address register - Address that caused fault */
-#define SCB_CPACR                       (volatile uint32_t *) (SCB_BASE + 0x088)                /* Coprocessor (FPU) Access Control Register */
+#define SCB_ICSR                      \
+    (volatile uint32_t *) (SCB_BASE + \
+                           0x004) /* Interrupt Control and State Register */
+#define SCB_VTOR                                                             \
+    (volatile uint32_t *) (SCB_BASE + 0x008) /* Vector Table Offset Register \
+                                              */
+#define SCB_AIRCR                                                           \
+    (volatile uint32_t *) (SCB_BASE + 0x00c) /* Application Interrupt/Reset \
+                                                Control Register */
+#define SCB_SCR \
+    (volatile uint32_t *) (SCB_BASE + 0x010) /* System Control Register */
+#define SCB_CCR                       \
+    (volatile uint32_t *) (SCB_BASE + \
+                           0x014) /* Configuration and Control Register */
+#define SCB_SHPR                     \
+    (volatile uint8_t *) (SCB_BASE + \
+                          0x018) /* System Handler Priority Register */
+#define SCB_SHCSR      \
+    (volatile uint32_t \
+         *) (SCB_BASE + 0x024) /* System Handler Control and State Register */
+#define SCB_CFSR                                                       \
+    (volatile uint32_t                                                 \
+         *) (SCB_BASE + 0x028) /* Configurable fault status register - \
+                                  Describes Usage, Bus, and Memory faults */
+#define SCB_HFSR                                                             \
+    (volatile uint32_t *) (SCB_BASE + 0x02C) /* Hard fault status register - \
+                                                Describes hard fault */
+#define SCB_DFSR                                                               \
+    (volatile uint32_t *) (SCB_BASE + 0x030) /* Debug fault status register -- \
+                                                Describes debug event */
+#define SCB_MMFAR                                                             \
+    (volatile uint32_t *) (SCB_BASE +                                         \
+                           0x034) /* Memory management fault address register \
+                                     - Address that caused fault */
+#define SCB_BFAR                                                             \
+    (volatile uint32_t *) (SCB_BASE + 0x038) /* Bus fault address register - \
+                                                Address that caused fault */
+#define SCB_CPACR      \
+    (volatile uint32_t \
+         *) (SCB_BASE + 0x088) /* Coprocessor (FPU) Access Control Register */
 
 /* Debug Control Block (DCB) */
-#define DCB_DHCSR                       (volatile uint32_t *) (DCB_BASE + 0x000)                /* Debug Halting Control and Status Register*/
-#define DCB_DCRSR                       (volatile uint32_t *) (DCB_BASE + 0x004)                /* Debug Core Register Selector Register */
-#define DCB_DCRDR                       (volatile uint32_t *) (DCB_BASE + 0x008)                /* Debug Core Register Data Register */
-#define DCB_DEMCR                       (volatile uint32_t *) (DCB_BASE + 0x00C)                /* Debug Exception and Monitor Control Register */
+#define DCB_DHCSR      \
+    (volatile uint32_t \
+         *) (DCB_BASE + 0x000) /* Debug Halting Control and Status Register*/
+#define DCB_DCRSR                     \
+    (volatile uint32_t *) (DCB_BASE + \
+                           0x004) /* Debug Core Register Selector Register */
+#define DCB_DCRDR                     \
+    (volatile uint32_t *) (DCB_BASE + \
+                           0x008) /* Debug Core Register Data Register */
+#define DCB_DEMCR                                                           \
+    (volatile uint32_t *) (DCB_BASE + 0x00C) /* Debug Exception and Monitor \
+                                                Control Register */
 
 /* Memory Protection Unit (MPU)
  * ST PM0214 (Cortex M4 Programming Manual) pg. 195 */
-#define MPU_TYPER                       (volatile uint32_t *) (MPU_BASE + 0x00)                 /* MPU Type Register - Describes HW MPU */
-#define MPU_CTRL                        (volatile uint32_t *) (MPU_BASE + 0x04)                 /* MPU Control Register */
-#define MPU_RNR                         (volatile uint32_t *) (MPU_BASE + 0x08)                 /* MPU Region Number Register */
-#define MPU_RBAR                        (volatile uint32_t *) (MPU_BASE + 0x0C)                 /* MPU Region Base Address Register */
-#define MPU_RASR                        (volatile uint32_t *) (MPU_BASE + 0x10)                 /* MPU Region Attribute and Size Register */
+#define MPU_TYPER                     \
+    (volatile uint32_t *) (MPU_BASE + \
+                           0x00) /* MPU Type Register - Describes HW MPU */
+#define MPU_CTRL \
+    (volatile uint32_t *) (MPU_BASE + 0x04) /* MPU Control Register */
+#define MPU_RNR \
+    (volatile uint32_t *) (MPU_BASE + 0x08) /* MPU Region Number Register */
+#define MPU_RBAR                      \
+    (volatile uint32_t *) (MPU_BASE + \
+                           0x0C) /* MPU Region Base Address Register */
+#define MPU_RASR                      \
+    (volatile uint32_t *) (MPU_BASE + \
+                           0x10) /* MPU Region Attribute and Size Register */
 
 /* Floating Point Unit (FPU)
  * ST PM0214 (Cortex M4 Programming Manual) pg. 236 */
-#define FPU_CCR                         (volatile uint32_t *) (FPU_BASE + 0x04)                 /* FPU Context Control Register */
-#define FPU_CAR                         (volatile uint32_t *) (FPU_BASE + 0x08)                 /* FPU Context Address Register */
+#define FPU_CCR \
+    (volatile uint32_t *) (FPU_BASE + 0x04) /* FPU Context Control Register */
+#define FPU_CAR \
+    (volatile uint32_t *) (FPU_BASE + 0x08) /* FPU Context Address Register */
 
 /**********************************************************************************************************************************************/
 
 /* System Control Block */
-#define SCB_ICSR_PENDSVCLR              (uint32_t) (1 << 27)                                    /* Clear PendSV interrupt */
-#define SCB_ICSR_PENDSVSET              (uint32_t) (1 << 28)                                    /* Set PendSV interrupt */
-#define SCB_ICSR_RETTOBASE				(uint32_t) (1 << 11)									/* Whether there are preempted active exceptions */
-
-#define SCB_SCR_SLEEPONEXIT             (uint32_t) (1 << 1)                                     /* Sleep on return from interrupt routine */
-#define SCB_SCR_SLEEPDEEP               (uint32_t) (1 << 2)                                     /* Use deep sleep as low power mode */
-#define SCB_SCR_SEVONPEND               (uint32_t) (1 << 4)                                     /* Send event on pending exception */
-
-#define SCB_CCR_STKALIGN                (uint32_t) (1 << 9)                                     /* Stack 8-byte alignment on exception entry */
-
-#define SCB_SHCSR_MEMFAULTENA           (uint32_t) (1 << 16)                                    /* Enables Memory Management Fault */
-#define SCB_SHCSR_BUSFAULTENA           (uint32_t) (1 << 17)                                    /* Enables Bus Fault */
-#define SCB_SHCSR_USEFAULTENA           (uint32_t) (1 << 18)                                    /* Enables Usage Fault */
+#define SCB_ICSR_PENDSVCLR (uint32_t) (1 << 27) /* Clear PendSV interrupt */
+#define SCB_ICSR_PENDSVSET (uint32_t) (1 << 28) /* Set PendSV interrupt */
+#define SCB_ICSR_RETTOBASE \
+    (uint32_t) (1 << 11) /* Whether there are preempted active exceptions */
+
+#define SCB_SCR_SLEEPONEXIT \
+    (uint32_t) (1 << 1) /* Sleep on return from interrupt routine */
+#define SCB_SCR_SLEEPDEEP \
+    (uint32_t) (1 << 2) /* Use deep sleep as low power mode */
+#define SCB_SCR_SEVONPEND \
+    (uint32_t) (1 << 4) /* Send event on pending exception */
+
+#define SCB_CCR_STKALIGN \
+    (uint32_t) (1 << 9) /* Stack 8-byte alignment on exception entry */
+
+#define SCB_SHCSR_MEMFAULTENA \
+    (uint32_t) (1 << 16) /* Enables Memory Management Fault */
+#define SCB_SHCSR_BUSFAULTENA (uint32_t) (1 << 17) /* Enables Bus Fault */
+#define SCB_SHCSR_USEFAULTENA (uint32_t) (1 << 18) /* Enables Usage Fault */
 
 /* Hard Fault Status Register */
-#define SCB_HFSR_VECTTBL                (uint32_t) (1 << 1)                                     /* Vector table hard fault.  Bus fault on vector table read during exception handling. */
-#define SCB_HFSR_FORCED                 (uint32_t) (1 << 30)                                    /* Forced hard fault.  Escalation of another fault. */
-#define SCB_HFSR_DEBUGEVT               (uint32_t) (1 << 31)                                    /* Indicates when a debug event has occured. */
+#define SCB_HFSR_VECTTBL                                                       \
+    (uint32_t) (1 << 1) /* Vector table hard fault.  Bus fault on vector table \
+                           read during exception handling. */
+#define SCB_HFSR_FORCED                                                      \
+    (uint32_t) (1 << 30) /* Forced hard fault.  Escalation of another fault. \
+                          */
+#define SCB_HFSR_DEBUGEVT \
+    (uint32_t) (1 << 31) /* Indicates when a debug event has occured. */
 
 /* Debug Fault Status Register */
-#define SCB_DFSR_HALTED                 (uint32_t) (1 << 0)                                     /* Indicates a 'single-step' debug event was generated. */
-#define SCB_DFSR_BKPT                   (uint32_t) (1 << 1)                                     /* Indicates a breakpoint event was generated. */
-#define SCB_DFSR_DWTTRAP                (uint32_t) (1 << 2)                                     /* Indicates a debug event was generated by DWT. */
+#define SCB_DFSR_HALTED                                              \
+    (uint32_t) (1 << 0) /* Indicates a 'single-step' debug event was \
+                           generated. */
+#define SCB_DFSR_BKPT \
+    (uint32_t) (1 << 1) /* Indicates a breakpoint event was generated. */
+#define SCB_DFSR_DWTTRAP \
+    (uint32_t) (1 << 2) /* Indicates a debug event was generated by DWT. */
 
 /* Memory Management Fault Status Register */
-#define SCB_MMFSR_IACCVIOL              (uint8_t)  (1 << 0)                                     /* Instruction access violation.  No address in MMFAR */
-#define SCB_MMFSR_DACCVIOL              (uint8_t)  (1 << 1)                                     /* Data access violation.  Address in MMFAR */
-#define SCB_MMFSR_MUNSTKERR             (uint8_t)  (1 << 3)                                     /* Fault on unstacking from exception.  No address in MMAR */
-#define SCB_MMFSR_MSTKERR               (uint8_t)  (1 << 4)                                     /* Fault on stacking for exception.  No address in MMFAR */
-#define SCB_MMFSR_MLSPERR               (uint8_t)  (1 << 5)                                     /* Fault during FP lazy state preservation. */
-#define SCB_MMFSR_MMARVALID             (uint8_t)  (1 << 7)                                     /* MMFAR holds valid address */
+#define SCB_MMFSR_IACCVIOL                                                   \
+    (uint8_t) (1 << 0) /* Instruction access violation.  No address in MMFAR \
+                        */
+#define SCB_MMFSR_DACCVIOL \
+    (uint8_t) (1 << 1) /* Data access violation.  Address in MMFAR */
+#define SCB_MMFSR_MUNSTKERR                                                  \
+    (uint8_t) (1 << 3) /* Fault on unstacking from exception.  No address in \
+                          MMAR */
+#define SCB_MMFSR_MSTKERR                                                 \
+    (uint8_t) (1 << 4) /* Fault on stacking for exception.  No address in \
+                          MMFAR */
+#define SCB_MMFSR_MLSPERR \
+    (uint8_t) (1 << 5) /* Fault during FP lazy state preservation. */
+#define SCB_MMFSR_MMARVALID (uint8_t) (1 << 7) /* MMFAR holds valid address */
 
 /* Bus Fault Status Register */
-#define SCB_BFSR_IBUSERR                (uint8_t)  (1 << 0)                                     /* Instruction bus error.  No address in BFAR */
-#define SCB_BFSR_PRECISERR              (uint8_t)  (1 << 1)                                     /* Precise data bus error.  Address in BFAR */
-#define SCB_BFSR_IMPRECISERR            (uint8_t)  (1 << 2)                                     /* Imprecise data bus error.  No address in BFAR */
-#define SCB_BFSR_UNSTKERR               (uint8_t)  (1 << 3)                                     /* Fault on unstacking from exception.  No address in BFAR */
-#define SCB_BFSR_STKERR                 (uint8_t)  (1 << 4)                                     /* Fault on stacking for exception.  No address in BFAR */
-#define SCB_BFSR_LSPERR                 (uint8_t)  (1 << 5)                                     /* Fault on FP lazy state preservation. */
-#define SCB_BFSR_BFARVALID              (uint8_t)  (1 << 7)                                     /* BFAR holds valid address */
+#define SCB_BFSR_IBUSERR \
+    (uint8_t) (1 << 0) /* Instruction bus error.  No address in BFAR */
+#define SCB_BFSR_PRECISERR \
+    (uint8_t) (1 << 1) /* Precise data bus error.  Address in BFAR */
+#define SCB_BFSR_IMPRECISERR \
+    (uint8_t) (1 << 2) /* Imprecise data bus error.  No address in BFAR */
+#define SCB_BFSR_UNSTKERR                                                    \
+    (uint8_t) (1 << 3) /* Fault on unstacking from exception.  No address in \
+                          BFAR */
+#define SCB_BFSR_STKERR                                                        \
+    (uint8_t) (1 << 4) /* Fault on stacking for exception.  No address in BFAR \
+                        */
+#define SCB_BFSR_LSPERR \
+    (uint8_t) (1 << 5) /* Fault on FP lazy state preservation. */
+#define SCB_BFSR_BFARVALID (uint8_t) (1 << 7) /* BFAR holds valid address */
 
 /* Usage Fault Status Register */
-#define SCB_UFSR_UNDEFINSTR             (uint16_t) (1 << 0)                                     /* Undefined instruction */
-#define SCB_UFSR_INVSTATE               (uint16_t) (1 << 1)                                     /* Invalid state - PC stacked for exception return attempts illegal use of epsr */
-#define SCB_UFSR_INVPC                  (uint16_t) (1 << 2)                                     /* Invalid PC load */
-#define SCB_UFSR_NOCP                   (uint16_t) (1 << 3)                                     /* No coprocessor */
-#define SCB_UFSR_UNALIGNED              (uint16_t) (1 << 8)                                     /* Unaligned access */
-#define SCB_UFSR_DIVBYZERO              (uint16_t) (1 << 9)                                     /* Divide by zero */
-
-#define SCB_CPACR_CP10_FULL             (uint32_t) (0x3 << 20)                                  /* Access privileges for coprocessor 10 (FPU) */
-#define SCB_CPACR_CP11_FULL             (uint32_t) (0x3 << 22)                                  /* Access privileges for coprocessor 11 (FPU) */
+#define SCB_UFSR_UNDEFINSTR (uint16_t) (1 << 0) /* Undefined instruction */
+#define SCB_UFSR_INVSTATE                                                  \
+    (uint16_t) (1 << 1) /* Invalid state - PC stacked for exception return \
+                           attempts illegal use of epsr */
+#define SCB_UFSR_INVPC (uint16_t) (1 << 2)     /* Invalid PC load */
+#define SCB_UFSR_NOCP (uint16_t) (1 << 3)      /* No coprocessor */
+#define SCB_UFSR_UNALIGNED (uint16_t) (1 << 8) /* Unaligned access */
+#define SCB_UFSR_DIVBYZERO (uint16_t) (1 << 9) /* Divide by zero */
+
+#define SCB_CPACR_CP10_FULL \
+    (uint32_t) (0x3 << 20) /* Access privileges for coprocessor 10 (FPU) */
+#define SCB_CPACR_CP11_FULL \
+    (uint32_t) (0x3 << 22) /* Access privileges for coprocessor 11 (FPU) */
 
 /* Debug Exception and Monitor Control Register */
-#define DCB_DEMCR_MON_EN                (uint32_t) (1 << 16)                                    /* Enable the DebugMonitor Exception */
-#define DCB_DEMCR_MON_STEP              (uint32_t) (1 << 18)                                    /* Make step request pending */
-#define DCB_DEMCR_TRCENA                (uint32_t) (1 << 24)                                    /* Global enable for all DWT and ITM features */
+#define DCB_DEMCR_MON_EN \
+    (uint32_t) (1 << 16) /* Enable the DebugMonitor Exception */
+#define DCB_DEMCR_MON_STEP                            \
+    (uint32_t) (1 << 18) /* Make step request pending \
+                          */
+#define DCB_DEMCR_TRCENA \
+    (uint32_t) (1 << 24) /* Global enable for all DWT and ITM features */
 
 /* Memory Protection Unit */
 /* See pg. 183 in STM32F4 Prog Ref (PM0214) */
-#define MPU_CTRL_ENABLE                 (uint32_t) (1 << 0)                                     /* Enables MPU */
-#define MPU_CTRL_HFNMIENA               (uint32_t) (1 << 1)                                     /* Enables MPU during Hardfault, NMI, and Faultmask handlers */
-#define MPU_CTRL_PRIVDEFENA             (uint32_t) (1 << 2)                                     /* Enable privileged software access to default memory map */
-
-#define MPU_RASR_ENABLE                 (uint32_t) (1 << 0)                                     /* Enable region */
-#define MPU_RASR_SIZE(x)                (uint32_t) (x << 1)                                     /* Region size (2^(x+1) bytes) */
-#define MPU_RASR_SHARE_CACHE_WBACK      (uint32_t) (1 << 16) | (1 << 17) | (1 << 18)            /* Sharable, Cachable, Write-Back */
-#define MPU_RASR_SHARE_NOCACHE_WBACK    (uint32_t) (1 << 16) | (0 << 17) | (1 << 18)            /* Sharable, Not Cachable, Write-Back */
-#define MPU_RASR_AP_PRIV_NO_UN_NO       (uint32_t) (0 << 24)                                    /* No access for any */
-#define MPU_RASR_AP_PRIV_RW_UN_NO       (uint32_t) (1 << 24)                                    /* No access for any */
-#define MPU_RASR_AP_PRIV_RW_UN_RO       (uint32_t) (2 << 24)                                    /* Unprivileged Read Only Permissions */
-#define MPU_RASR_AP_PRIV_RW_UN_RW       (uint32_t) (3 << 24)                                    /* All RW Permissions */
-#define MPU_RASR_AP_PRIV_RO_UN_NO       (uint32_t) (5 << 24)                                    /* Privileged RO Permissions, Unpriv no access */
-#define MPU_RASR_AP_PRIV_RO_UN_RO       (uint32_t) (6 << 24)                                    /* All RO Permissions */
-#define MPU_RASR_XN                     (uint32_t) (1 << 28)                                    /* MPU Region Execute Never */
+#define MPU_CTRL_ENABLE (uint32_t) (1 << 0) /* Enables MPU */
+#define MPU_CTRL_HFNMIENA                                                   \
+    (uint32_t) (1 << 1) /* Enables MPU during Hardfault, NMI, and Faultmask \
+                           handlers */
+#define MPU_CTRL_PRIVDEFENA                                                    \
+    (uint32_t) (1 << 2) /* Enable privileged software access to default memory \
+                           map */
+
+#define MPU_RASR_ENABLE (uint32_t) (1 << 0)  /* Enable region */
+#define MPU_RASR_SIZE(x) (uint32_t) (x << 1) /* Region size (2^(x+1) bytes) */
+#define MPU_RASR_SHARE_CACHE_WBACK     \
+    (uint32_t) (1 << 16) | (1 << 17) | \
+        (1 << 18) /* Sharable, Cachable, Write-Back */
+#define MPU_RASR_SHARE_NOCACHE_WBACK   \
+    (uint32_t) (1 << 16) | (0 << 17) | \
+        (1 << 18) /* Sharable, Not Cachable, Write-Back */
+#define MPU_RASR_AP_PRIV_NO_UN_NO (uint32_t) (0 << 24) /* No access for any */
+#define MPU_RASR_AP_PRIV_RW_UN_NO (uint32_t) (1 << 24) /* No access for any */
+#define MPU_RASR_AP_PRIV_RW_UN_RO \
+    (uint32_t) (2 << 24) /* Unprivileged Read Only Permissions */
+#define MPU_RASR_AP_PRIV_RW_UN_RW              \
+    (uint32_t) (3 << 24) /* All RW Permissions \
+                          */
+#define MPU_RASR_AP_PRIV_RO_UN_NO \
+    (uint32_t) (5 << 24) /* Privileged RO Permissions, Unpriv no access */
+#define MPU_RASR_AP_PRIV_RO_UN_RO                              \
+    (uint32_t) (6 << 24)                 /* All RO Permissions \
+                                          */
+#define MPU_RASR_XN (uint32_t) (1 << 28) /* MPU Region Execute Never */
 
 /* Floating Point Unit (FPU)
  * ST PM0214 (Cortex M4 Programming Manual) pg. 236 */
-#define FPU_CCR_ASPEN                   (uint32_t) (1 << 31)                                    /* FPU Automatic State Preservation */
+#define FPU_CCR_ASPEN \
+    (uint32_t) (1 << 31) /* FPU Automatic State Preservation */
 
 #endif
diff --git a/include/platform/debug_device.h b/include/platform/debug_device.h
index a298ee26..99aa88a5 100644
--- a/include/platform/debug_device.h
+++ b/include/platform/debug_device.h
@@ -5,12 +5,11 @@
 
 #ifndef DEBUG_DEVICE_H_
 #define DEBUG_DEVICE_H_
-#include <types.h>
 #include <debug.h>
+#include <types.h>
 
-#if defined (CONFIG_DEBUG) && \
-      (defined(CONFIG_DEBUG_DEV_UART) || \
-       defined(CONFIG_DEBUG_DEV_RAM))
+#if defined(CONFIG_DEBUG) && \
+    (defined(CONFIG_DEBUG_DEV_UART) || defined(CONFIG_DEBUG_DEV_RAM))
 
 #define DEBUG_DEVICE_EXIST
 #endif
@@ -20,22 +19,22 @@
  */
 typedef enum {
 #ifdef CONFIG_DEBUG_DEV_UART
-	DBG_DEV_UART,
+    DBG_DEV_UART,
 #endif
 #ifdef CONFIG_DEBUG_DEV_RAM
-	DBG_DEV_RAM,
+    DBG_DEV_RAM,
 #endif
-	DBG_DEV_MAX
+    DBG_DEV_MAX
 } dbg_dev_id_t;
 
 /*
  * Object context of an debug IO device. Including handlers ... etc
  */
 typedef struct {
-	dbg_dev_id_t	dev_id;
-	uint8_t 	(*getchar)(void);
-	void 		(*putchar)(uint8_t);
-	void 		(*start_panic)(void);
+    dbg_dev_id_t dev_id;
+    uint8_t (*getchar)(void);
+    void (*putchar)(uint8_t);
+    void (*start_panic)(void);
 } dbg_dev_t;
 
 
diff --git a/include/platform/debug_ram.h b/include/platform/debug_ram.h
index 27f3f740..be0094cd 100644
--- a/include/platform/debug_ram.h
+++ b/include/platform/debug_ram.h
@@ -9,7 +9,7 @@
 #include <types.h>
 
 /* Default debug ram buffer size */
-#define DBG_RAM_BUFSIZE    0x2000
+#define DBG_RAM_BUFSIZE 0x2000
 
 void dbg_ram_init(void);
 
diff --git a/include/platform/debug_uart.h b/include/platform/debug_uart.h
index a4776daf..4e085140 100644
--- a/include/platform/debug_uart.h
+++ b/include/platform/debug_uart.h
@@ -6,38 +6,38 @@
 #ifndef PLATFORM_DEBUG_UART_H_
 #define PLATFORM_DEBUG_UART_H_
 
-#include <types.h>
 #include <lib/queue.h>
+#include <types.h>
 
-#define IER_RBR		0x01
-#define IER_THRE	0x02
-#define IER_RLS		0x04
+#define IER_RBR 0x01
+#define IER_THRE 0x02
+#define IER_RLS 0x04
 
-#define IIR_PEND	0x01
-#define IIR_RLS		0x03
-#define IIR_RDA		0x02
-#define IIR_CTI		0x06
-#define IIR_THRE	0x01
+#define IIR_PEND 0x01
+#define IIR_RLS 0x03
+#define IIR_RDA 0x02
+#define IIR_CTI 0x06
+#define IIR_THRE 0x01
 
-#define LSR_RDR		0x01
-#define LSR_OE		0x02
-#define LSR_PE		0x04
-#define LSR_FE		0x08
-#define LSR_BI		0x10
-#define LSR_THRE	0x20
-#define LSR_TEMT	0x40
-#define LSR_RXFE	0x80
+#define LSR_RDR 0x01
+#define LSR_OE 0x02
+#define LSR_PE 0x04
+#define LSR_FE 0x08
+#define LSR_BI 0x10
+#define LSR_THRE 0x20
+#define LSR_TEMT 0x40
+#define LSR_RXFE 0x80
 
-#define SEND_BUFSIZE    2048
-#define RECV_BUFSIZE    32
+#define SEND_BUFSIZE 2048
+#define RECV_BUFSIZE 32
 
 struct dbg_uart_t {
-	uint32_t status;
-	uint32_t ready;
+    uint32_t status;
+    uint32_t ready;
 
-	/* Queues for RX and TX */
-	struct queue_t tx;
-	struct queue_t rx;
+    /* Queues for RX and TX */
+    struct queue_t tx;
+    struct queue_t rx;
 };
 
 void dbg_uart_init(void);
diff --git a/include/platform/hw_debug.h b/include/platform/hw_debug.h
index 78d7f350..a6d47986 100644
--- a/include/platform/hw_debug.h
+++ b/include/platform/hw_debug.h
@@ -9,78 +9,98 @@
 #include <stdint.h>
 
 typedef struct {
-	uint32_t comp;
-	uint32_t mask;
-	uint32_t func;
-	uint32_t reserved;
+    uint32_t comp;
+    uint32_t mask;
+    uint32_t func;
+    uint32_t reserved;
 } dwt_comp_t;
 
 /* DWT: Data Watchpoint and Trace unit Registers */
-#define DWT_BASE		(uint32_t) (0xE0001000)
-#define DWT_CTRL		(volatile uint32_t *) (DWT_BASE)		/*!< Control Register */
-#define DWT_CYCCNT		(volatile uint32_t *) (DWT_BASE + 0x04)		/*!< Cycle Count Register */
-#define DWT_CPICNT		(volatile uint32_t *) (DWT_BASE + 0x08)		/*!< CPI Count Register */
-#define DWT_EXCCNT		(volatile uint32_t *) (DWT_BASE + 0x0c)		/*!< Exception Overhead Count Register */
-#define DWT_SLEEPCNT		(volatile uint32_t *) (DWT_BASE + 0x10)		/*!< Sleep Count Register */
-#define DWT_LSUCNT		(volatile uint32_t *) (DWT_BASE + 0x14)		/*!< LSU Count Register */
-#define DWT_FOLDCNT		(volatile uint32_t *) (DWT_BASE + 0x18)		/*!< Folded-instruction Count Register */
-#define DWT_PCSR		(volatile uint32_t *) (DWT_BASE + 0x1c)		/*!< Program Counter Sample Register */
-#define DWT_COMP		(volatile dwt_comp_t *) (DWT_BASE + 0x20)	/*!< Comparator Registers */
+#define DWT_BASE (uint32_t) (0xE0001000)
+#define DWT_CTRL (volatile uint32_t *) (DWT_BASE) /*!< Control Register */
+#define DWT_CYCCNT \
+    (volatile uint32_t *) (DWT_BASE + 0x04) /*!< Cycle Count Register */
+#define DWT_CPICNT \
+    (volatile uint32_t *) (DWT_BASE + 0x08) /*!< CPI Count Register */
+#define DWT_EXCCNT                    \
+    (volatile uint32_t *) (DWT_BASE + \
+                           0x0c) /*!< Exception Overhead Count Register */
+#define DWT_SLEEPCNT \
+    (volatile uint32_t *) (DWT_BASE + 0x10) /*!< Sleep Count Register */
+#define DWT_LSUCNT \
+    (volatile uint32_t *) (DWT_BASE + 0x14) /*!< LSU Count Register */
+#define DWT_FOLDCNT                   \
+    (volatile uint32_t *) (DWT_BASE + \
+                           0x18) /*!< Folded-instruction Count Register */
+#define DWT_PCSR                      \
+    (volatile uint32_t *) (DWT_BASE + \
+                           0x1c) /*!< Program Counter Sample Register */
+#define DWT_COMP \
+    (volatile dwt_comp_t *) (DWT_BASE + 0x20) /*!< Comparator Registers */
 
 /* DWT Comparator Function Register */
-#define DWT_FUNC_DISABLE	(uint32_t) (0 << 0)	/*!< Comparator disabled */
-#define DWT_FUNC_DADDR_RO	(uint32_t) (5 << 0)	/*!< Watch read-only data-access */
-#define DWT_FUNC_DADDR_WO	(uint32_t) (6 << 0)	/*!< Watch write-only data-access */
-#define DWT_FUNC_DADDR_RW	(uint32_t) (7 << 0)	/*!< Watch read-write data-access */
-#define DWT_FUNC_CYCMATCH	(uint32_t) (1 << 7)	/*!< Enable cycle count comparison */
-#define DWT_FUNC_DATAVMATCH	(uint32_t) (1 << 8)	/*!< Enable data value comparison */
-#define DWT_FUNC_DATASZ_BYTE	(uint32_t) (0 << 10)	/*!< Size of data compared: 00 = Byte */
-#define DWT_FUNC_DATASZ_HWORD	(uint32_t) (1 << 10)	/*!< Size of data compared: 01 = Half-Word */
-#define DWT_FUNC_DATASZ_WORD	(uint32_t) (2 << 10)	/*!< Size of data compared: 10 = Word */
-#define DWT_FUNC_MATCHED	(uint32_t) (1 << 24)	/*!< Operation defined by FUNC matched */
+#define DWT_FUNC_DISABLE (uint32_t) (0 << 0) /*!< Comparator disabled */
+#define DWT_FUNC_DADDR_RO \
+    (uint32_t) (5 << 0) /*!< Watch read-only data-access */
+#define DWT_FUNC_DADDR_WO \
+    (uint32_t) (6 << 0) /*!< Watch write-only data-access */
+#define DWT_FUNC_DADDR_RW \
+    (uint32_t) (7 << 0) /*!< Watch read-write data-access */
+#define DWT_FUNC_CYCMATCH \
+    (uint32_t) (1 << 7) /*!< Enable cycle count comparison */
+#define DWT_FUNC_DATAVMATCH \
+    (uint32_t) (1 << 8) /*!< Enable data value comparison */
+#define DWT_FUNC_DATASZ_BYTE \
+    (uint32_t) (0 << 10) /*!< Size of data compared: 00 = Byte */
+#define DWT_FUNC_DATASZ_HWORD \
+    (uint32_t) (1 << 10) /*!< Size of data compared: 01 = Half-Word */
+#define DWT_FUNC_DATASZ_WORD \
+    (uint32_t) (2 << 10) /*!< Size of data compared: 10 = Word */
+#define DWT_FUNC_MATCHED \
+    (uint32_t) (1 << 24) /*!< Operation defined by FUNC matched */
 
 /* FPB Flash Patch and Breakpoint unit Registers */
-#define FPB_MAX_COMP		6
-#define FPB_BASE		(uint32_t) (0xE0002000)
-#define FPB_CTRL		(volatile uint32_t *) (FPB_BASE)
-#define FPB_REMAP		(volatile uint32_t *) (FPB_BASE + 0x04)
-#define FPB_COMP		(volatile uint32_t *) (FPB_BASE + 0x08)
+#define FPB_MAX_COMP 6
+#define FPB_BASE (uint32_t) (0xE0002000)
+#define FPB_CTRL (volatile uint32_t *) (FPB_BASE)
+#define FPB_REMAP (volatile uint32_t *) (FPB_BASE + 0x04)
+#define FPB_COMP (volatile uint32_t *) (FPB_BASE + 0x08)
 
-#define FPB_CTRL_ENABLE		(uint32_t) (1 << 0)
-#define FPB_CTRL_KEY		(uint32_t) (1 << 1)
+#define FPB_CTRL_ENABLE (uint32_t) (1 << 0)
+#define FPB_CTRL_KEY (uint32_t) (1 << 1)
 
-#define FPB_COMP_ENABLE		(uint32_t) (1 << 0)
-#define FPB_COMP_REPLACE_LOWER	(uint32_t) (1 << 30)
-#define FPB_COMP_REPLACE_UPPER	(uint32_t) (2 << 30)
+#define FPB_COMP_ENABLE (uint32_t) (1 << 0)
+#define FPB_COMP_REPLACE_LOWER (uint32_t) (1 << 30)
+#define FPB_COMP_REPLACE_UPPER (uint32_t) (2 << 30)
 
 /* FP_COMPx: 000:COMP_ADDR:00 */
 /* Ref: ARMv7-M Architecture Reference Manual, page.C1-65 */
 #define FPB_COMP_ADDR_MASK 0x1FFFFFFC
-#define cpu_enable_single_step()				\
-	do {							\
-		*DCB_DEMCR |= DCB_DEMCR_MON_STEP;		\
-	} while (0)
-#define cpu_disable_single_step()				\
-	do {							\
-		*DCB_DEMCR &= ~DCB_DEMCR_MON_STEP;		\
-	} while (0)
+#define cpu_enable_single_step()          \
+    do {                                  \
+        *DCB_DEMCR |= DCB_DEMCR_MON_STEP; \
+    } while (0)
+#define cpu_disable_single_step()          \
+    do {                                   \
+        *DCB_DEMCR &= ~DCB_DEMCR_MON_STEP; \
+    } while (0)
 
-#define enable_bkptid(id)					\
-	do {							\
-		*(FPB_COMP + (id)) |= FPB_COMP_ENABLE;		\
-	} while (0)
-#define disable_bkptid(id)					\
-	do {							\
-		*(FPB_COMP + (id)) &= ~FPB_COMP_ENABLE;		\
-	} while (0)
+#define enable_bkptid(id)                      \
+    do {                                       \
+        *(FPB_COMP + (id)) |= FPB_COMP_ENABLE; \
+    } while (0)
+#define disable_bkptid(id)                      \
+    do {                                        \
+        *(FPB_COMP + (id)) &= ~FPB_COMP_ENABLE; \
+    } while (0)
 
-#define enable_all_hard_breakpoints()					\
-	do {							\
-		*FPB_CTRL = FPB_CTRL_KEY | FPB_CTRL_ENABLE;	\
-	} while (0)
-#define disable_all_hard_breakpoints()					\
-	do {							\
-		*FPB_CTRL = FPB_CTRL_KEY | ~FPB_CTRL_ENABLE;	\
-	} while (0)
+#define enable_all_hard_breakpoints()               \
+    do {                                            \
+        *FPB_CTRL = FPB_CTRL_KEY | FPB_CTRL_ENABLE; \
+    } while (0)
+#define disable_all_hard_breakpoints()               \
+    do {                                             \
+        *FPB_CTRL = FPB_CTRL_KEY | ~FPB_CTRL_ENABLE; \
+    } while (0)
 
 #endif /* PLATFORM_HW_DEBUG_H_ */
diff --git a/include/platform/irq.h b/include/platform/irq.h
index d0159edc..6a057c1e 100644
--- a/include/platform/irq.h
+++ b/include/platform/irq.h
@@ -6,23 +6,23 @@
 #ifndef PLATFORM_IRQ_H_
 #define PLATFORM_IRQ_H_
 
-#include <softirq.h>
-#include <thread.h>
-#include <sched.h>
 #include <error.h>
-#include <platform/link.h>
 #include <platform/cortex_m.h>
+#include <platform/link.h>
+#include <sched.h>
+#include <softirq.h>
+#include <thread.h>
 
 void irq_init(void);
 
 static inline void irq_disable(void)
 {
-	__asm__ __volatile__ ("cpsid i" ::: "memory");
+    __asm__ __volatile__("cpsid i" ::: "memory");
 }
 
 static inline void irq_enable(void)
 {
-	__asm__ __volatile__ ("cpsie i" ::: "memory");
+    __asm__ __volatile__("cpsie i" ::: "memory");
 }
 
 /*
@@ -32,35 +32,31 @@ static inline void irq_enable(void)
  */
 static inline uint32_t irq_save_flags(void)
 {
-	uint32_t flags;
-	__asm__ __volatile__ (
-		"mrs %0, primask\n\t"
-		"cpsid i"
-		: "=r" (flags) :: "memory");
-	return flags;
+    uint32_t flags;
+    __asm__ __volatile__(
+        "mrs %0, primask\n\t"
+        "cpsid i"
+        : "=r"(flags)::"memory");
+    return flags;
 }
 
 static inline void irq_restore_flags(uint32_t flags)
 {
-	__asm__ __volatile__ (
-		"msr primask, %0"
-		:: "r" (flags) : "memory");
+    __asm__ __volatile__("msr primask, %0" ::"r"(flags) : "memory");
 }
 
 static inline void irq_svc(void)
 {
-	__asm__ __volatile__ ("svc #0");
+    __asm__ __volatile__("svc #0");
 }
 
 static inline int irq_number(void)
 {
-	int irqno;
+    int irqno;
 
-	__asm__ __volatile__ (
-		"mrs %0, ipsr"
-		: "=r" (irqno));
+    __asm__ __volatile__("mrs %0, ipsr" : "=r"(irqno));
 
-	return irqno;
+    return irqno;
 }
 
 /*
@@ -76,11 +72,11 @@ extern volatile uint32_t __irq_saved_regs[8];
  * MUST be called at very start of naked handler before any C expressions.
  * Uses only r0-r3 which are caller-saved and safe to clobber.
  */
-#define irq_save_regs_only()						\
-	__asm__ __volatile__ (						\
-		"ldr r0, =__irq_saved_regs\n\t"				\
-		"stm r0, {r4-r11}"					\
-		::: "r0", "memory")
+#define irq_save_regs_only()            \
+    __asm__ __volatile__(               \
+        "ldr r0, =__irq_saved_regs\n\t" \
+        "stm r0, {r4-r11}" ::           \
+            : "r0", "memory")
 
 /*
  * irq_save()
@@ -89,74 +85,71 @@ extern volatile uint32_t __irq_saved_regs[8];
  * Assumes irq_save_regs_only() was called first in naked handler.
  * Copies saved regs from global to ctx->regs.
  */
-#define __irq_save(ctx)							\
-	{								\
-		uint32_t *_regs = (uint32_t *)(ctx)->regs;		\
-		extern volatile uint32_t __irq_saved_regs[8];		\
-		/* Explicit unrolled copy to prevent loop mis-optimization */ \
-		_regs[0] = __irq_saved_regs[0];				\
-		_regs[1] = __irq_saved_regs[1];				\
-		_regs[2] = __irq_saved_regs[2];				\
-		_regs[3] = __irq_saved_regs[3];				\
-		_regs[4] = __irq_saved_regs[4];				\
-		_regs[5] = __irq_saved_regs[5];				\
-		_regs[6] = __irq_saved_regs[6];				\
-		_regs[7] = __irq_saved_regs[7];				\
-	}								\
-	__asm__ __volatile__ ("and r4, lr, 0xf":::"r4");		\
-	__asm__ __volatile__ ("teq r4, #0x9");				\
-	__asm__ __volatile__ ("ite eq");				\
-	__asm__ __volatile__ ("mrseq r0, msp"::: "r0");			\
-	__asm__ __volatile__ ("mrsne r0, psp"::: "r0");			\
-	__asm__ __volatile__ ("mov %0, r0" : "=r" ((ctx)->sp));		\
-	__asm__ __volatile__ ("mov %0, lr" : "=r" ((ctx)->ret));
+#define __irq_save(ctx)                                               \
+    {                                                                 \
+        uint32_t *_regs = (uint32_t *) (ctx)->regs;                   \
+        extern volatile uint32_t __irq_saved_regs[8];                 \
+        /* Explicit unrolled copy to prevent loop mis-optimization */ \
+        _regs[0] = __irq_saved_regs[0];                               \
+        _regs[1] = __irq_saved_regs[1];                               \
+        _regs[2] = __irq_saved_regs[2];                               \
+        _regs[3] = __irq_saved_regs[3];                               \
+        _regs[4] = __irq_saved_regs[4];                               \
+        _regs[5] = __irq_saved_regs[5];                               \
+        _regs[6] = __irq_saved_regs[6];                               \
+        _regs[7] = __irq_saved_regs[7];                               \
+    }                                                                 \
+    __asm__ __volatile__("and r4, lr, 0xf" ::: "r4");                 \
+    __asm__ __volatile__("teq r4, #0x9");                             \
+    __asm__ __volatile__("ite eq");                                   \
+    __asm__ __volatile__("mrseq r0, msp" ::: "r0");                   \
+    __asm__ __volatile__("mrsne r0, psp" ::: "r0");                   \
+    __asm__ __volatile__("mov %0, r0" : "=r"((ctx)->sp));             \
+    __asm__ __volatile__("mov %0, lr" : "=r"((ctx)->ret));
 
 #ifdef CONFIG_FPU
-#define irq_save(ctx)							\
-	__asm__ __volatile__ ("cpsid i");				\
-	(ctx)->fp_flag = 0;						\
-	__irq_save(ctx);						\
-	__asm__ __volatile__ ("tst lr, 0x10");				\
-	__asm__ __volatile__ ("bne no_fp");				\
-	__asm__ __volatile__ ("mov r3, %0"				\
-			: : "r" ((ctx)->fp_regs) : "r3");		\
-	__asm__ __volatile__ ("vstm r3!, {d8-d15}"			\
-			::: "r3");					\
-	__asm__ __volatile__ ("mov r4, 0x1": : :"r4");			\
-	__asm__ __volatile__ ("stm r3, {r4}");				\
-	__asm__ __volatile__ ("no_fp:");
-#else	/* ! CONFIG_FPU */
-#define irq_save(ctx)							\
-	__asm__ __volatile__ ("cpsid i");				\
-	__irq_save(ctx);
+#define irq_save(ctx)                                                  \
+    __asm__ __volatile__("cpsid i");                                   \
+    (ctx)->fp_flag = 0;                                                \
+    __irq_save(ctx);                                                   \
+    __asm__ __volatile__("tst lr, 0x10");                              \
+    __asm__ __volatile__("bne no_fp");                                 \
+    __asm__ __volatile__("mov r3, %0" : : "r"((ctx)->fp_regs) : "r3"); \
+    __asm__ __volatile__("vstm r3!, {d8-d15}" ::: "r3");               \
+    __asm__ __volatile__("mov r4, 0x1" : : : "r4");                    \
+    __asm__ __volatile__("stm r3, {r4}");                              \
+    __asm__ __volatile__("no_fp:");
+#else /* ! CONFIG_FPU */
+#define irq_save(ctx)                \
+    __asm__ __volatile__("cpsid i"); \
+    __irq_save(ctx);
 #endif
 
-#define __irq_restore(ctx)						\
-	__asm__ __volatile__ ("mov lr, %0" : : "r" ((ctx)->ret));	\
-	__asm__ __volatile__ ("mov r0, %0" : : "r" ((ctx)->sp));	\
-	__asm__ __volatile__ ("mov r2, %0" : : "r" ((ctx)->ctl));	\
-	__asm__ __volatile__ ("and r4, lr, 0xf":::"r4");		\
-	__asm__ __volatile__ ("teq r4, #0x9");				\
-	__asm__ __volatile__ ("ite eq");				\
-	__asm__ __volatile__ ("msreq msp, r0");				\
-	__asm__ __volatile__ ("msrne psp, r0");				\
-	__asm__ __volatile__ ("mov r0, %0" : : "r" ((ctx)->regs));	\
-	__asm__ __volatile__ ("ldm r0, {r4-r11}");			\
-	__asm__ __volatile__ ("msr control, r2\n\tisb" ::: "memory");
+#define __irq_restore(ctx)                                   \
+    __asm__ __volatile__("mov lr, %0" : : "r"((ctx)->ret));  \
+    __asm__ __volatile__("mov r0, %0" : : "r"((ctx)->sp));   \
+    __asm__ __volatile__("mov r2, %0" : : "r"((ctx)->ctl));  \
+    __asm__ __volatile__("and r4, lr, 0xf" ::: "r4");        \
+    __asm__ __volatile__("teq r4, #0x9");                    \
+    __asm__ __volatile__("ite eq");                          \
+    __asm__ __volatile__("msreq msp, r0");                   \
+    __asm__ __volatile__("msrne psp, r0");                   \
+    __asm__ __volatile__("mov r0, %0" : : "r"((ctx)->regs)); \
+    __asm__ __volatile__("ldm r0, {r4-r11}");                \
+    __asm__ __volatile__("msr control, r2\n\tisb" ::: "memory");
 
 #ifdef CONFIG_FPU
-#define irq_restore(ctx)						\
-	__irq_restore(ctx);						\
-	if ((ctx)->fp_flag) {						\
-		__asm__ __volatile__ ("mov r0, %0" 			\
-				: : "r" ((ctx)->fp_regs): "r0");	\
-		__asm__ __volatile__ ("vldm r0, {d8-d15}");		\
-	}								\
-	__asm__ __volatile__ ("cpsie i");
-#else	/* ! CONFIG_FPU */
+#define irq_restore(ctx)                                                   \
+    __irq_restore(ctx);                                                    \
+    if ((ctx)->fp_flag) {                                                  \
+        __asm__ __volatile__("mov r0, %0" : : "r"((ctx)->fp_regs) : "r0"); \
+        __asm__ __volatile__("vldm r0, {d8-d15}");                         \
+    }                                                                      \
+    __asm__ __volatile__("cpsie i");
+#else /* ! CONFIG_FPU */
 #define irq_restore(ctx) \
-	__irq_restore(ctx);						\
-	__asm__ __volatile__ ("cpsie i");
+    __irq_restore(ctx);  \
+    __asm__ __volatile__("cpsie i");
 #endif
 
 /* Initial context switches to kernel.
@@ -164,69 +157,72 @@ extern volatile uint32_t __irq_saved_regs[8];
  * When interrupts are enabled, it will jump to interrupt handler
  * and then return to normal execution of kernel code.
  */
-#define init_ctx_switch(ctx, pc) \
-	__asm__ __volatile__ ("mov r0, %0" : : "r" ((ctx)->sp));	\
-	__asm__ __volatile__ ("msr msp, r0");				\
-	__asm__ __volatile__ ("mov r1, %0" : : "r" (pc));		\
-	__asm__ __volatile__ ("cpsie i");				\
-	__asm__ __volatile__ ("bx r1");
-
-#define irq_enter()							\
-	__asm__ __volatile__ ("push {lr}");
-
-#define irq_return()							\
-	__asm__ __volatile__ ("pop {lr}");				\
-	__asm__ __volatile__ ("bx lr");
-
-#define context_switch(from, to)					\
-	{								\
-		__asm__ __volatile__ ("pop {lr}");			\
-		irq_save(&(from)->ctx);					\
-		thread_switch((to));					\
-		irq_restore(&(to)->ctx);				\
-		__asm__ __volatile__ ("bx lr");				\
-	}
-
-#define schedule_in_irq()						\
-	{								\
-		register tcb_t *sel;					\
-		sel = schedule_select();				\
-		/* Check current thread canary before any return path.	\
-		 * Catches overflow that occurred while thread ran. */	\
-		if (!thread_check_canary((tcb_t *)current)) {		\
-			panic("Stack overflow (current): tid=%t, "	\
-			      "stack_base=%p, canary=%p\n",		\
-			      current->t_globalid, current->stack_base,	\
-			      current->stack_base ?			\
-			      *((uint32_t *)current->stack_base) : 0);	\
-		}							\
-		if (sel != current) {					\
-			/* Check next thread before switching to it */	\
-			if (!thread_check_canary(sel)) {		\
-				panic("Stack overflow (next): tid=%t, "	\
-				      "stack_base=%p, canary=%p\n",	\
-				      sel->t_globalid, sel->stack_base,	\
-				      sel->stack_base ?			\
-				      *((uint32_t *)sel->stack_base) : 0); \
-			}						\
-			context_switch(current, sel);			\
-		} else {						\
-			/* No context switch - restore saved registers	\
-			 * and return via irq_return path */		\
-			extern volatile uint32_t __irq_saved_regs[8];	\
-			__asm__ __volatile__ (				\
-				"mov r0, %0\n\t"			\
-				"ldm r0, {r4-r11}"			\
-				: : "r" (__irq_saved_regs) : "r0");	\
-		}							\
-	}
-
-#define request_schedule()						\
-	do { *SCB_ICSR |= SCB_ICSR_PENDSVSET; } while (0)
-
-
-#define NO_PREEMPTED_IRQ						\
-	(*SCB_ICSR & SCB_ICSR_RETTOBASE)
+#define init_ctx_switch(ctx, pc)                           \
+    __asm__ __volatile__("mov r0, %0" : : "r"((ctx)->sp)); \
+    __asm__ __volatile__("msr msp, r0");                   \
+    __asm__ __volatile__("mov r1, %0" : : "r"(pc));        \
+    __asm__ __volatile__("cpsie i");                       \
+    __asm__ __volatile__("bx r1");
+
+#define irq_enter() __asm__ __volatile__("push {lr}");
+
+#define irq_return()                  \
+    __asm__ __volatile__("pop {lr}"); \
+    __asm__ __volatile__("bx lr");
+
+#define context_switch(from, to)          \
+    {                                     \
+        __asm__ __volatile__("pop {lr}"); \
+        irq_save(&(from)->ctx);           \
+        thread_switch((to));              \
+        irq_restore(&(to)->ctx);          \
+        __asm__ __volatile__("bx lr");    \
+    }
+
+#define schedule_in_irq()                                                   \
+    {                                                                       \
+        register tcb_t *sel;                                                \
+        sel = schedule_select();                                            \
+        /* Check current thread canary before any return path.              \
+         * Catches overflow that occurred while thread ran. */              \
+        if (!thread_check_canary((tcb_t *) current)) {                      \
+            panic(                                                          \
+                "Stack overflow (current): tid=%t, "                        \
+                "stack_base=%p, canary=%p\n",                               \
+                current->t_globalid, current->stack_base,                   \
+                current->stack_base ? *((uint32_t *) current->stack_base)   \
+                                    : 0);                                   \
+        }                                                                   \
+        if (sel != current) {                                               \
+            /* Check next thread before switching to it */                  \
+            if (!thread_check_canary(sel)) {                                \
+                panic(                                                      \
+                    "Stack overflow (next): tid=%t, "                       \
+                    "stack_base=%p, canary=%p\n",                           \
+                    sel->t_globalid, sel->stack_base,                       \
+                    sel->stack_base ? *((uint32_t *) sel->stack_base) : 0); \
+            }                                                               \
+            context_switch(current, sel);                                   \
+        } else {                                                            \
+            /* No context switch - restore saved registers                  \
+             * and return via irq_return path */                            \
+            extern volatile uint32_t __irq_saved_regs[8];                   \
+            __asm__ __volatile__(                                           \
+                "mov r0, %0\n\t"                                            \
+                "ldm r0, {r4-r11}"                                          \
+                :                                                           \
+                : "r"(__irq_saved_regs)                                     \
+                : "r0");                                                    \
+        }                                                                   \
+    }
+
+#define request_schedule()               \
+    do {                                 \
+        *SCB_ICSR |= SCB_ICSR_PENDSVSET; \
+    } while (0)
+
+
+#define NO_PREEMPTED_IRQ (*SCB_ICSR & SCB_ICSR_RETTOBASE)
 
 /*
  * Context is switched when the selected thead is different
@@ -237,16 +233,16 @@ extern volatile uint32_t __irq_saved_regs[8];
  * thread's structure or to kernel_ctx
  * */
 
-#define IRQ_HANDLER(name, sub)						\
-	void name(void) __NAKED;					\
-	void name(void)							\
-	{								\
-		irq_enter();						\
-		sub();							\
-		request_schedule();					\
-		irq_return();						\
-	}
+#define IRQ_HANDLER(name, sub) \
+    void name(void) __NAKED;   \
+    void name(void)            \
+    {                          \
+        irq_enter();           \
+        sub();                 \
+        request_schedule();    \
+        irq_return();          \
+    }
 
 extern volatile tcb_t *current;
 
-#endif	/* PLATFORM_IRQ_H_ */
+#endif /* PLATFORM_IRQ_H_ */
diff --git a/include/platform/link.h b/include/platform/link.h
index cb7c75ac..902d168e 100644
--- a/include/platform/link.h
+++ b/include/platform/link.h
@@ -64,26 +64,26 @@ extern uint32_t mem0_start;
 extern uint32_t mem1_start;
 #endif
 
-#define __BSS 			__attribute__ ((section(".bss")))
-#define __ISR_VECTOR		__attribute__ ((section(".isr_vector")))
+#define __BSS __attribute__((section(".bss")))
+#define __ISR_VECTOR __attribute__((section(".isr_vector")))
 #ifndef LOADER
-#define __KIP 			__attribute__ ((section(".kip")))
-#define __KTABLE		__attribute__ ((section(".ktable")))
+#define __KIP __attribute__((section(".kip")))
+#define __KTABLE __attribute__((section(".ktable")))
 
 #ifdef CONFIG_BITMAP_BITBAND
-#define __BITMAP		__attribute__ ((section(".bitmap_bitband")))
+#define __BITMAP __attribute__((section(".bitmap_bitband")))
 #else
-#define __BITMAP		__attribute__ ((section(".bitmap")))
+#define __BITMAP __attribute__((section(".bitmap")))
 #endif
 
-#define __USER_TEXT		__attribute__ ((section(".user_text")))
-#define __USER_DATA		__attribute__ ((section(".user_data")))
-#define __USER_BSS		__attribute__ ((section(".user_bss")))
-#define __USER_SC		__attribute__ ((section(".syscall")))
+#define __USER_TEXT __attribute__((section(".user_text")))
+#define __USER_DATA __attribute__((section(".user_data")))
+#define __USER_BSS __attribute__((section(".user_bss")))
+#define __USER_SC __attribute__((section(".syscall")))
 #endif
 
-#define __PACKED		__attribute__ ((packed))
+#define __PACKED __attribute__((packed))
 
-#define __NAKED 		__attribute__ ((naked))
+#define __NAKED __attribute__((naked))
 
-#endif	/* PLATFORM_LINK_H_ */
+#endif /* PLATFORM_LINK_H_ */
diff --git a/include/platform/mpu.h b/include/platform/mpu.h
index 319385be..a6084960 100644
--- a/include/platform/mpu.h
+++ b/include/platform/mpu.h
@@ -8,28 +8,30 @@
 
 #include <memory.h>
 
-#define MPU_BASE_ADDR		0xE000ED9C	/* Region Base Address Register (RBAR) */
-#define MPU_ATTR_ADDR		0xE000EDA0	/* Region Attribute and Size Register (RASR) */
-#define MPU_CTRL_ADDR		0xE000ED94	/* MPU Control Register (CTRL) */
-#define MPU_RNR_ADDR		0xE000ED98	/* Region Number Register (RNR) */
+#define MPU_BASE_ADDR 0xE000ED9C /* Region Base Address Register (RBAR) */
+#define MPU_ATTR_ADDR                                                         \
+    0xE000EDA0                   /* Region Attribute and Size Register (RASR) \
+                                  */
+#define MPU_CTRL_ADDR 0xE000ED94 /* MPU Control Register (CTRL) */
+#define MPU_RNR_ADDR 0xE000ED98  /* Region Number Register (RNR) */
 
-#define MPU_FAULT_STATUS_ADDR	0xE000ED28
-#define MPU_FAULT_ADDRESS_ADDR	0xE000ED34
+#define MPU_FAULT_STATUS_ADDR 0xE000ED28
+#define MPU_FAULT_ADDRESS_ADDR 0xE000ED34
 
-#define MPU_REGION_MASK		0xFFFFFFE0
+#define MPU_REGION_MASK 0xFFFFFFE0
 
 /* 0x4 is PRIVDEFENA bit that allows access from kernel */
-#define MPU_PRIVDEFENA		4
+#define MPU_PRIVDEFENA 4
 
-#define MPU_MEM_FAULT		0x80
-#define MPU_MSTKERR		0x10
-#define MPU_MUSTKERR		0x08
-#define MPU_DACCVIOL		0x02
-#define	MPU_IACCVIOL		0x01
+#define MPU_MEM_FAULT 0x80
+#define MPU_MSTKERR 0x10
+#define MPU_MUSTKERR 0x08
+#define MPU_DACCVIOL 0x02
+#define MPU_IACCVIOL 0x01
 
 void mpu_setup_region(int n, fpage_t *fp);
 void mpu_enable(mpu_state_t i);
 void __memmanage_handler(void);
 int mpu_select_lru(as_t *as, uint32_t addr);
 
-#endif	/* PLATFORM_MPU_H_ */
+#endif /* PLATFORM_MPU_H_ */
diff --git a/include/platform/spinlock.h b/include/platform/spinlock.h
index bb3cd386..cec0dd0f 100644
--- a/include/platform/spinlock.h
+++ b/include/platform/spinlock.h
@@ -10,7 +10,7 @@
 
 typedef uint32_t spinlock_t;
 
-#define SPINLOCK_INITIALIZER 	0x0
+#define SPINLOCK_INITIALIZER 0x0
 
 /* Basic spinlock ops for ARMv7M architecture */
 int spinlock_trylock(spinlock_t *sl);
diff --git a/include/platform/stm32f1/exti.h b/include/platform/stm32f1/exti.h
index 9bd11e92..a2ec7536 100644
--- a/include/platform/stm32f1/exti.h
+++ b/include/platform/stm32f1/exti.h
@@ -1,27 +1,27 @@
 #ifndef PLATFORM_STM32F1_EXTI_H_
 #define PLATFORM_STM32F1_EXTI_H_
 
-#include <platform/stm32f1/registers.h>
 #include <platform/stm32f1/gpio.h>
+#include <platform/stm32f1/registers.h>
 
 /* EXTI mode */
-#define EXTI_INTERRUPT_MODE				0x0
-#define EXTI_EVENT_MODE					0x4
+#define EXTI_INTERRUPT_MODE 0x0
+#define EXTI_EVENT_MODE 0x4
 
 /* EXTI trigger type */
-#define EXTI_RISING_TRIGGER				0x8
-#define EXTI_FALLING_TRIGGER			0xc
-#define EXTI_RISING_FALLING_TRIGGER		0x10
+#define EXTI_RISING_TRIGGER 0x8
+#define EXTI_FALLING_TRIGGER 0xc
+#define EXTI_RISING_FALLING_TRIGGER 0x10
 
-#define EXTI_LINE(x)	((uint32_t)0x1 << x)
+#define EXTI_LINE(x) ((uint32_t) 0x1 << x)
 
 struct exti_regs {
-	volatile uint32_t IMR;
-	volatile uint32_t EMR;
-	volatile uint32_t RTSR;
-	volatile uint32_t FTSR;
-	volatile uint32_t SWIER;
-	volatile uint32_t PR;
+    volatile uint32_t IMR;
+    volatile uint32_t EMR;
+    volatile uint32_t RTSR;
+    volatile uint32_t FTSR;
+    volatile uint32_t SWIER;
+    volatile uint32_t PR;
 };
 
 
diff --git a/include/platform/stm32f1/gpio.h b/include/platform/stm32f1/gpio.h
index a525f3e0..768e7cdd 100644
--- a/include/platform/stm32f1/gpio.h
+++ b/include/platform/stm32f1/gpio.h
@@ -36,40 +36,43 @@ struct gpio_cfg {
 };
 
 /* GPIO Alternative Function */
-#define     af_spi1             ((uint32_t)0x00000001)
-#define     af_i2c1             ((uint32_t)0x00000002)
-#define     af_usart1           ((uint32_t)0x00000004)
-#define     af_usart2           ((uint32_t)0x00000008)
-#define     af_partial_usart3   ((uint32_t)0x00140010)
-#define     af_full_usart3      ((uint32_t)0x00140030)
-#define     af_partial_tim1     ((uint32_t)0x00160040)
-#define     af_full_tim1        ((uint32_t)0x001600C0)
-#define     af_partial_tim2_1   ((uint32_t)0x00180100)
-#define     af_partial_tim2_2   ((uint32_t)0x00180200)
-#define     af_full_tim2        ((uint32_t)0x00180300)
-#define     af_partial_tim3     ((uint32_t)0x001A0800)
-#define     af_full_tim3        ((uint32_t)0x001A0C00)
-#define     af_tim4             ((uint32_t)0x00001000)
-#define     af_can1_1           ((uint32_t)0x001D4000)
-#define     af_can1_2           ((uint32_t)0x001D6000)
-#define     af_pd01             ((uint32_t)0x00008000)
-#define     af_tim5_ch4         ((uint32_t)0x00200001)
-#define     af_adc1_ext_inj     ((uint32_t)0x00200002)
-#define     af_adc1_ext_reg     ((uint32_t)0x00200004)
-#define     af_adc2_ext_inj     ((uint32_t)0x00200008)
-#define     af_adc2_ext_reg     ((uint32_t)0x00200010)
-#define     af_eth              ((uint32_t)0x00200020)
-#define     af_can2             ((uint32_t)0x00200040)
-#define     af_swj_nojtrst      ((uint32_t)0x00300100)
-#define     af_swj_jtagdisable  ((uint32_t)0x00300200)
-#define     af_swj_disable      ((uint32_t)0x00300400)
-#define     af_spi3             ((uint32_t)0x00201100)
-#define     af_tim2itr1_ptp_sof ((uint32_t)0x00202000)
-#define     af_ptp_pps          ((uint32_t)0x00200400)
-#define     af_tim1_dma         ((uint32_t)0x80000010)
+#define af_spi1 ((uint32_t) 0x00000001)
+#define af_i2c1 ((uint32_t) 0x00000002)
+#define af_usart1 ((uint32_t) 0x00000004)
+#define af_usart2 ((uint32_t) 0x00000008)
+#define af_partial_usart3 ((uint32_t) 0x00140010)
+#define af_full_usart3 ((uint32_t) 0x00140030)
+#define af_partial_tim1 ((uint32_t) 0x00160040)
+#define af_full_tim1 ((uint32_t) 0x001600C0)
+#define af_partial_tim2_1 ((uint32_t) 0x00180100)
+#define af_partial_tim2_2 ((uint32_t) 0x00180200)
+#define af_full_tim2 ((uint32_t) 0x00180300)
+#define af_partial_tim3 ((uint32_t) 0x001A0800)
+#define af_full_tim3 ((uint32_t) 0x001A0C00)
+#define af_tim4 ((uint32_t) 0x00001000)
+#define af_can1_1 ((uint32_t) 0x001D4000)
+#define af_can1_2 ((uint32_t) 0x001D6000)
+#define af_pd01 ((uint32_t) 0x00008000)
+#define af_tim5_ch4 ((uint32_t) 0x00200001)
+#define af_adc1_ext_inj ((uint32_t) 0x00200002)
+#define af_adc1_ext_reg ((uint32_t) 0x00200004)
+#define af_adc2_ext_inj ((uint32_t) 0x00200008)
+#define af_adc2_ext_reg ((uint32_t) 0x00200010)
+#define af_eth ((uint32_t) 0x00200020)
+#define af_can2 ((uint32_t) 0x00200040)
+#define af_swj_nojtrst ((uint32_t) 0x00300100)
+#define af_swj_jtagdisable ((uint32_t) 0x00300200)
+#define af_swj_disable ((uint32_t) 0x00300400)
+#define af_spi3 ((uint32_t) 0x00201100)
+#define af_tim2itr1_ptp_sof ((uint32_t) 0x00202000)
+#define af_ptp_pps ((uint32_t) 0x00200400)
+#define af_tim1_dma ((uint32_t) 0x80000010)
 
 void gpio_config(struct gpio_cfg *cfg);
-void gpio_config_output(uint8_t port, uint8_t pin, uint8_t mode, uint8_t ospeed);
+void gpio_config_output(uint8_t port,
+                        uint8_t pin,
+                        uint8_t mode,
+                        uint8_t ospeed);
 void gpio_config_input(uint8_t port, uint8_t pin, uint8_t mode);
 void gpio_out_high(uint8_t port, uint8_t pin);
 void gpio_out_low(uint8_t port, uint8_t pin);
diff --git a/include/platform/stm32f1/nvic.h b/include/platform/stm32f1/nvic.h
index 08cf49c5..75812ed3 100644
--- a/include/platform/stm32f1/nvic.h
+++ b/include/platform/stm32f1/nvic.h
@@ -6,188 +6,205 @@
 #ifndef __PLATFORM_STM32F1_NVIC_H__
 #define __PLATFORM_STM32F1_NVIC_H__
 
-#include <platform/stm32f1/registers.h>
 #include <platform/cortex_m.h>
+#include <platform/stm32f1/registers.h>
 
-#define IRQ_ENABLE	1
-#define IRQ_DISABLE	0
+#define IRQ_ENABLE 1
+#define IRQ_DISABLE 0
 
 typedef enum IRQn {
-	/* Cortex-M4 Processor Exceptions Numbers */
-	NonMaskableInt_IRQn	= -14,	/*!< 2 Non Maskable Interrupt */
-	MemoryManagement_IRQn	= -12,	/*!< 4 Cortex-M4 Memory Management Interrupt */
-	BusFault_IRQn		= -11,	/*!< 5 Cortex-M4 Bus Fault Interrupt */
-	UsageFault_IRQn		= -10,	/*!< 6 Cortex-M4 Usage Fault Interrupt */
-	SVCall_IRQn		= -5,	/*!< 11 Cortex-M4 SV Call Interrupt */
-	DebugMonitor_IRQn	= -4,	/*!< 12 Cortex-M4 Debug Monitor Interrupt */
-	PendSV_IRQn		= -2,	/*!< 14 Cortex-M4 Pend SV Interrupt */
-	SysTick_IRQn		= -1,	/*!< 15 Cortex-M4 System Tick Interrupt */
-
-	/* STM32 specific Interrupt Numbers */
-	WWDG_IRQn		= 0,	/*!< Window WatchDog Interrupt */
-	PVD_IRQn		= 1,	/*!< PVD through EXTI Line detection Interrupt */
-	TAMP_STAMP_IRQn		= 2,	/*!< Tamper and TimeStamp interrupts through the EXTI line */
-	RTC_WKUP_IRQn		= 3,	/*!< RTC Wakeup interrupt through the EXTI line */
-	FLASH_IRQn		= 4,	/*!< FLASH global Interrupt */
-	RCC_IRQn		= 5,	/*!< RCC global Interrupt */
-	EXTI0_IRQn		= 6,	/*!< EXTI Line0 Interrupt */
-	EXTI1_IRQn		= 7,	/*!< EXTI Line1 Interrupt */
-	EXTI2_IRQn		= 8,	/*!< EXTI Line2 Interrupt */
-	EXTI3_IRQn		= 9,	/*!< EXTI Line3 Interrupt */
-	EXTI4_IRQn		= 10,	/*!< EXTI Line4 Interrupt */
-	DMA_Stream0_IRQn	= 11,	/*!< DMA1 Stream 0 global Interrupt */
-	DMA_Stream1_IRQn	= 12,	/*!< DMA1 Stream 1 global Interrupt */
-	DMA_Stream2_IRQn	= 13,	/*!< DMA1 Stream 2 global Interrupt */
-	DMA_Stream3_IRQn	= 14,	/*!< DMA1 Stream 3 global Interrupt */
-	DMA_Stream4_IRQn	= 15,	/*!< DMA1 Stream 4 global Interrupt */
-	DMA_Stream5_IRQn	= 16,	/*!< DMA1 Stream 5 global Interrupt */
-	DMA_Stream6_IRQn	= 17,	/*!< DMA1 Stream 6 global Interrupt */
-	ADC_IRQn		= 18,	/*!< ADC1, ADC2 and ADC3 global Interrupts */
-	CAN1_TX_IRQn		= 19,	/*!< CAN1 TX Interrupt */
-	CAN1_RX0_IRQn		= 20,	/*!< CAN1 RX0 Interrupt */
-	CAN1_RX1_IRQn		= 21,	/*!< CAN1 RX1 Interrupt */
-	CAN1_SCE_IRQn		= 22,	/*!< CAN1 SCE Interrupt */
-	EXTI9_5_IRQn		= 23,	/*!< External Line[9:5] Interrupts */
-	TIM1_BRK_IRQn	= 24,	/*!< TIM1 Break interrupt */
-	TIM1_UP_IRQn	= 25,	/*!< TIM1 Update Interrupt */
-	TIM1_TRG_COM_IRQn	= 26,	/*!< TIM1 Trigger and Commutation Interrupt */
-	TIM1_CC_IRQn		= 27,	/*!< TIM1 Capture Compare Interrupt */
-	TIM2_IRQn		= 28,	/*!< TIM2 global Interrupt */
-	TIM3_IRQn		= 29,	/*!< TIM3 global Interrupt */
-	TIM4_IRQn		= 30,	/*!< TIM4 global Interrupt */
-	I2C1_EV_IRQn		= 31,	/*!< I2C1 Event Interrupt */
-	I2C1_ER_IRQn		= 32,	/*!< I2C1 Error Interrupt */
-	I2C2_EV_IRQn		= 33,	/*!< I2C2 Event Interrupt */
-	I2C2_ER_IRQn		= 34,	/*!< I2C2 Error Interrupt */
-	SPI1_IRQn		= 35,	/*!< SPI1 global Interrupt */
-	SPI2_IRQn		= 36,	/*!< SPI2 global Interrupt */
-	USART1_IRQn		= 37,	/*!< USART1 global Interrupt */
-	USART2_IRQn		= 38,	/*!< USART2 global Interrupt */
-	USART3_IRQn		= 39,	/*!< USART3 global Interrupt */
-	EXTI15_10_IRQn		= 40,	/*!< External Line[15:10] Interrupts */
-	RTC_Alarm_IRQn		= 41,	/*!< RTC Alarm (A and B) through EXTI Line Interrupt */
-	OTG_FS_WKUP_IRQn	= 42,	/*!< USB OTG FS Wakeup through EXTI line interrupt */
-	IRQn_NUM,
+    /* Cortex-M4 Processor Exceptions Numbers */
+    NonMaskableInt_IRQn = -14,   /*!< 2 Non Maskable Interrupt */
+    MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+    BusFault_IRQn = -11,         /*!< 5 Cortex-M4 Bus Fault Interrupt */
+    UsageFault_IRQn = -10,       /*!< 6 Cortex-M4 Usage Fault Interrupt */
+    SVCall_IRQn = -5,            /*!< 11 Cortex-M4 SV Call Interrupt */
+    DebugMonitor_IRQn = -4,      /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+    PendSV_IRQn = -2,            /*!< 14 Cortex-M4 Pend SV Interrupt */
+    SysTick_IRQn = -1,           /*!< 15 Cortex-M4 System Tick Interrupt */
+
+    /* STM32 specific Interrupt Numbers */
+    WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+    PVD_IRQn = 1,  /*!< PVD through EXTI Line detection Interrupt */
+    TAMP_STAMP_IRQn =
+        2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+    RTC_WKUP_IRQn = 3,      /*!< RTC Wakeup interrupt through the EXTI line */
+    FLASH_IRQn = 4,         /*!< FLASH global Interrupt */
+    RCC_IRQn = 5,           /*!< RCC global Interrupt */
+    EXTI0_IRQn = 6,         /*!< EXTI Line0 Interrupt */
+    EXTI1_IRQn = 7,         /*!< EXTI Line1 Interrupt */
+    EXTI2_IRQn = 8,         /*!< EXTI Line2 Interrupt */
+    EXTI3_IRQn = 9,         /*!< EXTI Line3 Interrupt */
+    EXTI4_IRQn = 10,        /*!< EXTI Line4 Interrupt */
+    DMA_Stream0_IRQn = 11,  /*!< DMA1 Stream 0 global Interrupt */
+    DMA_Stream1_IRQn = 12,  /*!< DMA1 Stream 1 global Interrupt */
+    DMA_Stream2_IRQn = 13,  /*!< DMA1 Stream 2 global Interrupt */
+    DMA_Stream3_IRQn = 14,  /*!< DMA1 Stream 3 global Interrupt */
+    DMA_Stream4_IRQn = 15,  /*!< DMA1 Stream 4 global Interrupt */
+    DMA_Stream5_IRQn = 16,  /*!< DMA1 Stream 5 global Interrupt */
+    DMA_Stream6_IRQn = 17,  /*!< DMA1 Stream 6 global Interrupt */
+    ADC_IRQn = 18,          /*!< ADC1, ADC2 and ADC3 global Interrupts */
+    CAN1_TX_IRQn = 19,      /*!< CAN1 TX Interrupt */
+    CAN1_RX0_IRQn = 20,     /*!< CAN1 RX0 Interrupt */
+    CAN1_RX1_IRQn = 21,     /*!< CAN1 RX1 Interrupt */
+    CAN1_SCE_IRQn = 22,     /*!< CAN1 SCE Interrupt */
+    EXTI9_5_IRQn = 23,      /*!< External Line[9:5] Interrupts */
+    TIM1_BRK_IRQn = 24,     /*!< TIM1 Break interrupt */
+    TIM1_UP_IRQn = 25,      /*!< TIM1 Update Interrupt */
+    TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+    TIM1_CC_IRQn = 27,      /*!< TIM1 Capture Compare Interrupt */
+    TIM2_IRQn = 28,         /*!< TIM2 global Interrupt */
+    TIM3_IRQn = 29,         /*!< TIM3 global Interrupt */
+    TIM4_IRQn = 30,         /*!< TIM4 global Interrupt */
+    I2C1_EV_IRQn = 31,      /*!< I2C1 Event Interrupt */
+    I2C1_ER_IRQn = 32,      /*!< I2C1 Error Interrupt */
+    I2C2_EV_IRQn = 33,      /*!< I2C2 Event Interrupt */
+    I2C2_ER_IRQn = 34,      /*!< I2C2 Error Interrupt */
+    SPI1_IRQn = 35,         /*!< SPI1 global Interrupt */
+    SPI2_IRQn = 36,         /*!< SPI2 global Interrupt */
+    USART1_IRQn = 37,       /*!< USART1 global Interrupt */
+    USART2_IRQn = 38,       /*!< USART2 global Interrupt */
+    USART3_IRQn = 39,       /*!< USART3 global Interrupt */
+    EXTI15_10_IRQn = 40,    /*!< External Line[15:10] Interrupts */
+    RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+    OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+    IRQn_NUM,
 } IRQn_Type;
 
 #define MAX_IRQn FPU_IRQn
 
 /* Define device IRQ handler name */
-#define WWDG_HANDLER                nvic_handler0
-#define PVD_HANDLER                 nvic_handler1
-#define TAMP_STAMP_HANDLER          nvic_handler2
-#define RTC_WKUP_HANDLER            nvic_handler3
-#define FLASH_HANDLER               nvic_handler4
-#define RCC_HANDLER                 nvic_handler5
-#define EXTI0_HANDLER               nvic_handler6
-#define EXTI1_HANDLER               nvic_handler7
-#define EXTI2_HANDLER               nvic_handler8
-#define EXTI3_HANDLER               nvic_handler9
-#define EXTI4_HANDLER               nvic_handler10
-#define DMA1_Stream0_HANDLER        nvic_handler11
-#define DMA1_Stream1_HANDLER        nvic_handler12
-#define DMA1_Stream2_HANDLER        nvic_handler13
-#define DMA1_Stream3_HANDLER        nvic_handler14
-#define DMA1_Stream4_HANDLER        nvic_handler15
-#define DMA1_Stream5_HANDLER        nvic_handler16
-#define DMA1_Stream6_HANDLER        nvic_handler17
-#define ADC_HANDLER                 nvic_handler18
-#define CAN1_TX_HANDLER             nvic_handler19
-#define CAN1_RX0_HANDLER            nvic_handler20
-#define CAN1_RX1_HANDLER            nvic_handler21
-#define CAN1_SCE_HANDLER            nvic_handler22
-#define EXTI9_5_HANDLER             nvic_handler23
-#define TIM1_BRK_HANDLER            nvic_handler24
-#define TIM1_UP_HANDLER             nvic_handler25
-#define TIM1_TRG_COM_HANDLER        nvic_handler26
-#define TIM1_CC_HANDLER             nvic_handler27
-#define TIM2_HANDLER                nvic_handler28
-#define TIM3_HANDLER                nvic_handler29
-#define TIM4_HANDLER                nvic_handler30
-#define I2C1_EV_HANDLER             nvic_handler31
-#define I2C1_ER_HANDLER             nvic_handler32
-#define I2C2_EV_HANDLER             nvic_handler33
-#define I2C2_ER_HANDLER             nvic_handler34
-#define SPI1_HANDLER                nvic_handler35
-#define SPI2_HANDLER                nvic_handler36
-#define USART1_HANDLER              nvic_handler37
-#define USART2_HANDLER              nvic_handler38
-#define USART2_HANDLER              nvic_handler38
-#define USART3_HANDLER              nvic_handler39
-#define EXTI15_10_HANDLER           nvic_handler40
-#define RTC_Alarm_HANDLER           nvic_handler41
-#define OTG_FS_WKUP_HANDLER         nvic_handler42
-
-#define IRQ_VEC_N_HANDLER_DECLARE(n) \
-	void nvic_handler##n (void);
-
-#define IRQ_VEC_N_OP	IRQ_VEC_N_HANDLER_DECLARE
+#define WWDG_HANDLER nvic_handler0
+#define PVD_HANDLER nvic_handler1
+#define TAMP_STAMP_HANDLER nvic_handler2
+#define RTC_WKUP_HANDLER nvic_handler3
+#define FLASH_HANDLER nvic_handler4
+#define RCC_HANDLER nvic_handler5
+#define EXTI0_HANDLER nvic_handler6
+#define EXTI1_HANDLER nvic_handler7
+#define EXTI2_HANDLER nvic_handler8
+#define EXTI3_HANDLER nvic_handler9
+#define EXTI4_HANDLER nvic_handler10
+#define DMA1_Stream0_HANDLER nvic_handler11
+#define DMA1_Stream1_HANDLER nvic_handler12
+#define DMA1_Stream2_HANDLER nvic_handler13
+#define DMA1_Stream3_HANDLER nvic_handler14
+#define DMA1_Stream4_HANDLER nvic_handler15
+#define DMA1_Stream5_HANDLER nvic_handler16
+#define DMA1_Stream6_HANDLER nvic_handler17
+#define ADC_HANDLER nvic_handler18
+#define CAN1_TX_HANDLER nvic_handler19
+#define CAN1_RX0_HANDLER nvic_handler20
+#define CAN1_RX1_HANDLER nvic_handler21
+#define CAN1_SCE_HANDLER nvic_handler22
+#define EXTI9_5_HANDLER nvic_handler23
+#define TIM1_BRK_HANDLER nvic_handler24
+#define TIM1_UP_HANDLER nvic_handler25
+#define TIM1_TRG_COM_HANDLER nvic_handler26
+#define TIM1_CC_HANDLER nvic_handler27
+#define TIM2_HANDLER nvic_handler28
+#define TIM3_HANDLER nvic_handler29
+#define TIM4_HANDLER nvic_handler30
+#define I2C1_EV_HANDLER nvic_handler31
+#define I2C1_ER_HANDLER nvic_handler32
+#define I2C2_EV_HANDLER nvic_handler33
+#define I2C2_ER_HANDLER nvic_handler34
+#define SPI1_HANDLER nvic_handler35
+#define SPI2_HANDLER nvic_handler36
+#define USART1_HANDLER nvic_handler37
+#define USART2_HANDLER nvic_handler38
+#define USART2_HANDLER nvic_handler38
+#define USART3_HANDLER nvic_handler39
+#define EXTI15_10_HANDLER nvic_handler40
+#define RTC_Alarm_HANDLER nvic_handler41
+#define OTG_FS_WKUP_HANDLER nvic_handler42
+
+#define IRQ_VEC_N_HANDLER_DECLARE(n) void nvic_handler##n(void);
+
+#define IRQ_VEC_N_OP IRQ_VEC_N_HANDLER_DECLARE
 #include "platform/stm32f1/nvic_private.h"
 #undef IRQ_VEC_N_OP
 
 typedef struct {
-	volatile uint32_t ISER[8];	/*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-	uint32_t RESERVED0[24];
-	volatile uint32_t ICER[8];	/*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-	uint32_t RSERVED1[24];
-	volatile uint32_t ISPR[8];	/*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-	uint32_t RESERVED2[24];
-	volatile uint32_t ICPR[8];	/*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-	uint32_t RESERVED3[24];
-	volatile uint32_t IABR[8];	/*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-	uint32_t RESERVED4[56];
-	volatile uint8_t  IP[240];	/*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-	uint32_t RESERVED5[644];
-	volatile uint32_t STIR;		/*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+    volatile uint32_t
+        ISER[8]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[24];
+    volatile uint32_t
+        ICER[8]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[24];
+    volatile uint32_t
+        ISPR[8]; /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[24];
+    volatile uint32_t
+        ICPR[8]; /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[24];
+    volatile uint32_t
+        IABR[8]; /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+    uint32_t RESERVED4[56];
+    volatile uint8_t IP[240]; /*!< Offset: 0x300 (R/W)  Interrupt Priority
+                                 Register (8Bit wide) */
+    uint32_t RESERVED5[644];
+    volatile uint32_t
+        STIR; /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
 } NVIC_Type;
 
-#define NVIC_PriorityGroup_0         ((uint32_t) 0x700) /*!< 0 bits for pre-emption priority
-								4 bits for subpriority */
-#define NVIC_PriorityGroup_1         ((uint32_t) 0x600) /*!< 1 bits for pre-emption priority
-								3 bits for subpriority */
-#define NVIC_PriorityGroup_2         ((uint32_t) 0x500) /*!< 2 bits for pre-emption priority
-								2 bits for subpriority */
-#define NVIC_PriorityGroup_3         ((uint32_t) 0x400) /*!< 3 bits for pre-emption priority
-								1 bits for subpriority */
-#define NVIC_PriorityGroup_4         ((uint32_t) 0x300) /*!< 4 bits for pre-emption priority
-								0 bits for subpriority */
-#define NVIC \
-	((NVIC_Type *) NVIC_BASE)
-
-
-void NVIC_SetPriority(IRQn_Type IRQn, uint8_t group_priority, uint8_t sub_priority);
+#define NVIC_PriorityGroup_0                                \
+    ((uint32_t) 0x700) /*!< 0 bits for pre-emption priority \
+4 bits for subpriority */
+#define NVIC_PriorityGroup_1                                \
+    ((uint32_t) 0x600) /*!< 1 bits for pre-emption priority \
+3 bits for subpriority */
+#define NVIC_PriorityGroup_2                                \
+    ((uint32_t) 0x500) /*!< 2 bits for pre-emption priority \
+2 bits for subpriority */
+#define NVIC_PriorityGroup_3                                \
+    ((uint32_t) 0x400) /*!< 3 bits for pre-emption priority \
+1 bits for subpriority */
+#define NVIC_PriorityGroup_4                                \
+    ((uint32_t) 0x300) /*!< 4 bits for pre-emption priority \
+0 bits for subpriority */
+#define NVIC ((NVIC_Type *) NVIC_BASE)
+
+
+void NVIC_SetPriority(IRQn_Type IRQn,
+                      uint8_t group_priority,
+                      uint8_t sub_priority);
 void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
 
-inline static void  NVIC_EnableIRQ(IRQn_Type IRQn)
+inline static void NVIC_EnableIRQ(IRQn_Type IRQn)
 {
-	NVIC->ISER[((uint32_t) IRQn >> 0x5)] = (1 << ((uint32_t)(IRQn) & 0x1f));
+    NVIC->ISER[((uint32_t) IRQn >> 0x5)] = (1 << ((uint32_t) (IRQn) & 0x1f));
 }
 
 inline static void NVIC_DisableIRQ(IRQn_Type IRQn)
 {
-	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+    NVIC->ICER[((uint32_t) (IRQn) >> 5)] = (1 << ((uint32_t) (IRQn) & 0x1F));
 }
 
 inline static uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
-	return (uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] &
-	                   (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0);
+    return (uint32_t) ((NVIC->ISPR[(uint32_t) (IRQn) >> 5] &
+                        (1 << ((uint32_t) (IRQn) & 0x1F)))
+                           ? 1
+                           : 0);
 }
 
 inline static void NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
-	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+    NVIC->ISPR[((uint32_t) (IRQn) >> 5)] = (1 << ((uint32_t) (IRQn) & 0x1F));
 }
 
 inline static void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
-	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+    NVIC->ICPR[((uint32_t) (IRQn) >> 5)] = (1 << ((uint32_t) (IRQn) & 0x1F));
 }
 
 inline static uint32_t NVIC_GetActive(IRQn_Type IRQn)
 {
-	return (uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] &
-	                  (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0);
+    return (uint32_t) ((NVIC->IABR[(uint32_t) (IRQn) >> 5] &
+                        (1 << ((uint32_t) (IRQn) & 0x1F)))
+                           ? 1
+                           : 0);
 }
 
 int nvic_is_setup(int irq);
diff --git a/include/platform/stm32f1/nvic_private.h b/include/platform/stm32f1/nvic_private.h
index 275d769c..49964455 100644
--- a/include/platform/stm32f1/nvic_private.h
+++ b/include/platform/stm32f1/nvic_private.h
@@ -2,216 +2,216 @@
 
 /* This header is only included internally. */
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_WWDG_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_WWDG_USER_IRQ))
 IRQ_VEC_N_OP(0)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_PVD_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_PVD_USER_IRQ))
 IRQ_VEC_N_OP(1)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TAMP_STAMP_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TAMP_STAMP_USER_IRQ))
 IRQ_VEC_N_OP(2)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_RTC_WKUP_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_RTC_WKUP_USER_IRQ))
 IRQ_VEC_N_OP(3)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_FLASH_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_FLASH_USER_IRQ))
 IRQ_VEC_N_OP(4)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_RCC_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_RCC_USER_IRQ))
 IRQ_VEC_N_OP(5)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_EXTI0_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_EXTI0_USER_IRQ))
 IRQ_VEC_N_OP(6)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_EXTI1_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_EXTI1_USER_IRQ))
 IRQ_VEC_N_OP(7)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_EXTI2_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_EXTI2_USER_IRQ))
 IRQ_VEC_N_OP(8)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_EXTI3_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_EXTI3_USER_IRQ))
 IRQ_VEC_N_OP(9)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_EXTI4_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_EXTI4_USER_IRQ))
 IRQ_VEC_N_OP(10)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA_Stream0_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA_Stream0_USER_IRQ))
 IRQ_VEC_N_OP(11)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA_Stream1_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA_Stream1_USER_IRQ))
 IRQ_VEC_N_OP(12)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA_Stream2_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA_Stream2_USER_IRQ))
 IRQ_VEC_N_OP(13)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA_Stream3_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA_Stream3_USER_IRQ))
 IRQ_VEC_N_OP(14)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA_Stream4_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA_Stream4_USER_IRQ))
 IRQ_VEC_N_OP(15)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA_Stream5_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA_Stream5_USER_IRQ))
 IRQ_VEC_N_OP(16)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA_Stream6_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA_Stream6_USER_IRQ))
 IRQ_VEC_N_OP(17)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_ADC_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_ADC_USER_IRQ))
 IRQ_VEC_N_OP(18)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CAN1_TX_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CAN1_TX_USER_IRQ))
 IRQ_VEC_N_OP(19)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CAN1_RX_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CAN1_RX_USER_IRQ))
 IRQ_VEC_N_OP(20)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CAN1_RX1_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CAN1_RX1_USER_IRQ))
 IRQ_VEC_N_OP(21)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CAN1_SCE_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CAN1_SCE_USER_IRQ))
 IRQ_VEC_N_OP(22)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_EXTI9_5_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_EXTI9_5_USER_IRQ))
 IRQ_VEC_N_OP(23)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM1_BRK_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM1_BRK_USER_IRQ))
 IRQ_VEC_N_OP(24)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM1_UP_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM1_UP_USER_IRQ))
 IRQ_VEC_N_OP(25)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM1_TRG_COM_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM1_TRG_COM_USER_IRQ))
 IRQ_VEC_N_OP(26)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM1_CC_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM1_CC_USER_IRQ))
 IRQ_VEC_N_OP(27)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM2_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM2_USER_IRQ))
 IRQ_VEC_N_OP(28)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM3_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM3_USER_IRQ))
 IRQ_VEC_N_OP(29)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM4_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM4_USER_IRQ))
 IRQ_VEC_N_OP(30)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_I2C1_EV_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_I2C1_EV_USER_IRQ))
 IRQ_VEC_N_OP(31)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_I2C1_ER_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_I2C1_ER_USER_IRQ))
 IRQ_VEC_N_OP(32)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_I2C2_EV_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_I2C2_EV_USER_IRQ))
 IRQ_VEC_N_OP(33)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_I2C2_ER_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_I2C2_ER_USER_IRQ))
 IRQ_VEC_N_OP(34)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_SPI1_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_SPI1_USER_IRQ))
 IRQ_VEC_N_OP(35)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_SPI2_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_SPI2_USER_IRQ))
 IRQ_VEC_N_OP(36)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_USART1_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_USART1_USER_IRQ))
 IRQ_VEC_N_OP(37)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_USART2_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_USART2_USER_IRQ))
 IRQ_VEC_N_OP(38)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_USART3_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_USART3_USER_IRQ))
 IRQ_VEC_N_OP(39)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_EXTI15_10_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_EXTI15_10_USER_IRQ))
 IRQ_VEC_N_OP(40)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_RTC_Alarm_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_RTC_Alarm_USER_IRQ))
 IRQ_VEC_N_OP(41)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_OTG_FS_WKUP_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_OTG_FS_WKUP_USER_IRQ))
 IRQ_VEC_N_OP(42)
 #endif
diff --git a/include/platform/stm32f1/nvic_table.h b/include/platform/stm32f1/nvic_table.h
index baa34c0c..dd315201 100644
--- a/include/platform/stm32f1/nvic_table.h
+++ b/include/platform/stm32f1/nvic_table.h
@@ -1,8 +1,7 @@
 /* NVIC platform-speific table generator */
 
-#define IRQ_HANDLER_FUNC(n) \
-        nvic_handler##n,
+#define IRQ_HANDLER_FUNC(n) nvic_handler##n,
 
-#define IRQ_VEC_N_OP    IRQ_HANDLER_FUNC
+#define IRQ_VEC_N_OP IRQ_HANDLER_FUNC
 #include "platform/stm32f1/nvic_private.h"
 #undef IRQ_VEC_N_OP
diff --git a/include/platform/stm32f1/rcc.h b/include/platform/stm32f1/rcc.h
index efac7bae..93c83de5 100644
--- a/include/platform/stm32f1/rcc.h
+++ b/include/platform/stm32f1/rcc.h
@@ -3,24 +3,24 @@
 
 #include <platform/stm32f1/registers.h>
 struct rcc_clocks {
-	uint32_t sysclk_freq;
-	uint32_t hclk_freq;
-	uint32_t pclk1_freq;
-	uint32_t pclk2_freq;
+    uint32_t sysclk_freq;
+    uint32_t hclk_freq;
+    uint32_t pclk1_freq;
+    uint32_t pclk2_freq;
 };
 
 /* RCC_FLAG definition */
-#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
-#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
-#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
-#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
-#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
-#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
-#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
-#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
-#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
-#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
-#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
+#define RCC_FLAG_HSIRDY ((uint8_t) 0x21)
+#define RCC_FLAG_HSERDY ((uint8_t) 0x31)
+#define RCC_FLAG_PLLRDY ((uint8_t) 0x39)
+#define RCC_FLAG_LSERDY ((uint8_t) 0x41)
+#define RCC_FLAG_LSIRDY ((uint8_t) 0x61)
+#define RCC_FLAG_PINRST ((uint8_t) 0x7A)
+#define RCC_FLAG_PORRST ((uint8_t) 0x7B)
+#define RCC_FLAG_SFTRST ((uint8_t) 0x7C)
+#define RCC_FLAG_IWDGRST ((uint8_t) 0x7D)
+#define RCC_FLAG_WWDGRST ((uint8_t) 0x7E)
+#define RCC_FLAG_LPWRRST ((uint8_t) 0x7F)
 
 void sys_clock_init(void);
 void RCC_AHBPeriphClockCmd(uint32_t rcc_AHB, uint8_t enable);
@@ -30,6 +30,6 @@ void RCC_APB1PeriphResetCmd(uint32_t rcc_APB1, uint8_t enable);
 void RCC_APB2PeriphClockCmd(uint32_t rcc_APB2, uint8_t enable);
 void RCC_APB2PeriphResetCmd(uint32_t rcc_APB2, uint8_t enable);
 uint8_t RCC_GetFlagStatus(uint8_t flag);
-void RCC_GetClocksFreq(struct rcc_clocks* clock);
+void RCC_GetClocksFreq(struct rcc_clocks *clock);
 
 #endif
diff --git a/include/platform/stm32f1/registers.h b/include/platform/stm32f1/registers.h
index 23668641..13520565 100644
--- a/include/platform/stm32f1/registers.h
+++ b/include/platform/stm32f1/registers.h
@@ -8,499 +8,760 @@
 #define STM32F1X
 
 /* Memory Map */
-#define MEMORY_BASE                     (uint32_t) (0x00000000)                                 /* Base of memory map */
-#define FLASH_BASE                      (uint32_t) (0x08000000)                                 /* Flash Memory Base Address */
-#define SRAM_BASE                       (uint32_t) (0x20000000)                                 /* SRAM Base Address */
+#define MEMORY_BASE (uint32_t) (0x00000000) /* Base of memory map */
+#define FLASH_BASE (uint32_t) (0x08000000)  /* Flash Memory Base Address */
+#define SRAM_BASE (uint32_t) (0x20000000)   /* SRAM Base Address */
 
 /* Peripheral Map */
-#define PERIPH_BASE                     (uint32_t) (0x40000000)                                 /* Peripheral base address */
-#define PRIV_PERIPH_BASE                (uint32_t) (0xED000000)                                 /* Private peripheral base address */
-#define APB1PERIPH_BASE                 (PERIPH_BASE)
-#define APB2PERIPH_BASE                 (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE                  (PERIPH_BASE + 0x20000)
+#define PERIPH_BASE (uint32_t) (0x40000000) /* Peripheral base address */
+#define PRIV_PERIPH_BASE \
+    (uint32_t) (0xED000000) /* Private peripheral base address */
+#define APB1PERIPH_BASE (PERIPH_BASE)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
 
 
 
 /* APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
-#define USB_BASE              (APB1PERIPH_BASE + 0x5C00)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
-#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define USB_BASE (APB1PERIPH_BASE + 0x5C00)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
 
 /* APB2 peripherals */
-#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
-#define GPIO_BASE(port)       (APB2PERIPH_BASE + 0x0800 + (0x400*port))                        /* GPIO Port base address */
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIO_BASE(port) \
+    (APB2PERIPH_BASE + 0x0800 + (0x400 * port)) /* GPIO Port base address */
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
 
 /* AHB */
-#define DMA_BASE                        (AHBPERIPH_BASE)                                        /* DMA base address */
-#define RCC_BASE                        (AHBPERIPH_BASE + 0x1000)                               /* Reset and Clock Control base address */
-#define FLASH_R_BASE                    (AHBPERIPH_BASE + 0x2000)                               /* Flash registers base address */
-#define CRC_BASE                        (AHBPERIPH_BASE + 0x3000)                               /* CRC base address */
+#define DMA_BASE (AHBPERIPH_BASE) /* DMA base address */
+#define RCC_BASE \
+    (AHBPERIPH_BASE + 0x1000) /* Reset and Clock Control base address */
+#define FLASH_R_BASE \
+    (AHBPERIPH_BASE + 0x2000)              /* Flash registers base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000) /* CRC base address */
 
 /* Timer 1 (TIM1) */
-#define TIM1_CR1                        (volatile uint32_t *) (TIM1_BASE + 0x00)                /* TIM1 control register 1 */
-#define TIM1_CR2                        (volatile uint32_t *) (TIM1_BASE + 0x04)                /* TIM1 control register 2 */
-#define TIM1_SMCR                       (volatile uint32_t *) (TIM1_BASE + 0x08)                /* TIM1 slave mode control register */
-#define TIM1_DIER                       (volatile uint32_t *) (TIM1_BASE + 0x0C)                /* TIM1 DMA/Interrupt enable register */
-#define TIM1_SR                         (volatile uint32_t *) (TIM1_BASE + 0x10)                /* TIM1 status register */
-#define TIM1_EGR                        (volatile uint32_t *) (TIM1_BASE + 0x14)                /* TIM1 event generation register */
-#define TIM1_CCMR1                      (volatile uint32_t *) (TIM1_BASE + 0x18)                /* TIM1 capture/compare mode register 1 */
-#define TIM1_CCMR2                      (volatile uint32_t *) (TIM1_BASE + 0x1C)                /* TIM1 capture/compare mode register 2 */
-#define TIM1_CCER                       (volatile uint32_t *) (TIM1_BASE + 0x20)                /* TIM1 capture/compare enable register */
-#define TIM1_CNT                        (volatile uint32_t *) (TIM1_BASE + 0x24)                /* TIM1 counter */
-#define TIM1_PSC                        (volatile uint32_t *) (TIM1_BASE + 0x28)                /* TIM1 prescaler */
-#define TIM1_ARR                        (volatile uint32_t *) (TIM1_BASE + 0x2C)                /* TIM1 auto-reload register */
-#define TIM1_CCR1                       (volatile uint32_t *) (TIM1_BASE + 0x34)                /* TIM1 capture/compare register 1 */
-#define TIM1_CCR2                       (volatile uint32_t *) (TIM1_BASE + 0x38)                /* TIM1 capture/compare register 2 */
-#define TIM1_CCR3                       (volatile uint32_t *) (TIM1_BASE + 0x3C)                /* TIM1 capture/compare register 3 */
-#define TIM1_CCR4                       (volatile uint32_t *) (TIM1_BASE + 0x40)                /* TIM1 capture/compare register 4 */
-#define TIM1_DCR                        (volatile uint32_t *) (TIM1_BASE + 0x48)                /* TIM1 DMA control register */
-#define TIM1_DMAR                       (volatile uint32_t *) (TIM1_BASE + 0x4C)                /* TIM1 DMA address for full transfer */
-#define TIM1_OR                         (volatile uint32_t *) (TIM1_BASE + 0x50)                /* TIM1 option register */
-
-#define TIM2_CR1                        (volatile uint32_t *) (TIM2_BASE + 0x00)                /* TIM2 control register 1 */
-#define TIM2_CR2                        (volatile uint32_t *) (TIM2_BASE + 0x04)                /* TIM2 control register 2 */
-#define TIM2_SMCR                       (volatile uint32_t *) (TIM2_BASE + 0x08)                /* TIM2 slave mode control register */
-#define TIM2_DIER                       (volatile uint32_t *) (TIM2_BASE + 0x0C)                /* TIM2 DMA/Interrupt enable register */
-#define TIM2_SR                         (volatile uint32_t *) (TIM2_BASE + 0x10)                /* TIM2 status register */
-#define TIM2_EGR                        (volatile uint32_t *) (TIM2_BASE + 0x14)                /* TIM2 event generation register */
-#define TIM2_CCMR1                      (volatile uint32_t *) (TIM2_BASE + 0x18)                /* TIM2 capture/compare mode register 1 */
-#define TIM2_CCMR2                      (volatile uint32_t *) (TIM2_BASE + 0x1C)                /* TIM2 capture/compare mode register 2 */
-#define TIM2_CCER                       (volatile uint32_t *) (TIM2_BASE + 0x20)                /* TIM2 capture/compare enable register */
-#define TIM2_CNT                        (volatile uint32_t *) (TIM2_BASE + 0x24)                /* TIM2 counter */
-#define TIM2_PSC                        (volatile uint32_t *) (TIM2_BASE + 0x28)                /* TIM2 prescaler */
-#define TIM2_ARR                        (volatile uint32_t *) (TIM2_BASE + 0x2C)                /* TIM2 auto-reload register */
-#define TIM2_CCR1                       (volatile uint32_t *) (TIM2_BASE + 0x34)                /* TIM2 capture/compare register 1 */
-#define TIM2_CCR2                       (volatile uint32_t *) (TIM2_BASE + 0x38)                /* TIM2 capture/compare register 2 */
-#define TIM2_CCR3                       (volatile uint32_t *) (TIM2_BASE + 0x3C)                /* TIM2 capture/compare register 3 */
-#define TIM2_CCR4                       (volatile uint32_t *) (TIM2_BASE + 0x40)                /* TIM2 capture/compare register 4 */
-#define TIM2_DCR                        (volatile uint32_t *) (TIM2_BASE + 0x48)                /* TIM2 DMA control register */
-#define TIM2_DMAR                       (volatile uint32_t *) (TIM2_BASE + 0x4C)                /* TIM2 DMA address for full transfer */
-#define TIM2_OR                         (volatile uint32_t *) (TIM2_BASE + 0x50)                /* TIM2 option register */
+#define TIM1_CR1 \
+    (volatile uint32_t *) (TIM1_BASE + 0x00) /* TIM1 control register 1 */
+#define TIM1_CR2 \
+    (volatile uint32_t *) (TIM1_BASE + 0x04) /* TIM1 control register 2 */
+#define TIM1_SMCR                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x08) /* TIM1 slave mode control register */
+#define TIM1_DIER                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x0C) /* TIM1 DMA/Interrupt enable register */
+#define TIM1_SR \
+    (volatile uint32_t *) (TIM1_BASE + 0x10) /* TIM1 status register */
+#define TIM1_EGR                       \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x14) /* TIM1 event generation register */
+#define TIM1_CCMR1                     \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x18) /* TIM1 capture/compare mode register 1 */
+#define TIM1_CCMR2                     \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x1C) /* TIM1 capture/compare mode register 2 */
+#define TIM1_CCER                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x20) /* TIM1 capture/compare enable register */
+#define TIM1_CNT (volatile uint32_t *) (TIM1_BASE + 0x24) /* TIM1 counter */
+#define TIM1_PSC (volatile uint32_t *) (TIM1_BASE + 0x28) /* TIM1 prescaler */
+#define TIM1_ARR \
+    (volatile uint32_t *) (TIM1_BASE + 0x2C) /* TIM1 auto-reload register */
+#define TIM1_CCR1                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x34) /* TIM1 capture/compare register 1 */
+#define TIM1_CCR2                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x38) /* TIM1 capture/compare register 2 */
+#define TIM1_CCR3                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x3C) /* TIM1 capture/compare register 3 */
+#define TIM1_CCR4                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x40) /* TIM1 capture/compare register 4 */
+#define TIM1_DCR \
+    (volatile uint32_t *) (TIM1_BASE + 0x48) /* TIM1 DMA control register */
+#define TIM1_DMAR                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x4C) /* TIM1 DMA address for full transfer */
+#define TIM1_OR \
+    (volatile uint32_t *) (TIM1_BASE + 0x50) /* TIM1 option register */
+
+#define TIM2_CR1 \
+    (volatile uint32_t *) (TIM2_BASE + 0x00) /* TIM2 control register 1 */
+#define TIM2_CR2 \
+    (volatile uint32_t *) (TIM2_BASE + 0x04) /* TIM2 control register 2 */
+#define TIM2_SMCR                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x08) /* TIM2 slave mode control register */
+#define TIM2_DIER                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x0C) /* TIM2 DMA/Interrupt enable register */
+#define TIM2_SR \
+    (volatile uint32_t *) (TIM2_BASE + 0x10) /* TIM2 status register */
+#define TIM2_EGR                       \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x14) /* TIM2 event generation register */
+#define TIM2_CCMR1                     \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x18) /* TIM2 capture/compare mode register 1 */
+#define TIM2_CCMR2                     \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x1C) /* TIM2 capture/compare mode register 2 */
+#define TIM2_CCER                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x20) /* TIM2 capture/compare enable register */
+#define TIM2_CNT (volatile uint32_t *) (TIM2_BASE + 0x24) /* TIM2 counter */
+#define TIM2_PSC (volatile uint32_t *) (TIM2_BASE + 0x28) /* TIM2 prescaler */
+#define TIM2_ARR \
+    (volatile uint32_t *) (TIM2_BASE + 0x2C) /* TIM2 auto-reload register */
+#define TIM2_CCR1                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x34) /* TIM2 capture/compare register 1 */
+#define TIM2_CCR2                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x38) /* TIM2 capture/compare register 2 */
+#define TIM2_CCR3                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x3C) /* TIM2 capture/compare register 3 */
+#define TIM2_CCR4                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x40) /* TIM2 capture/compare register 4 */
+#define TIM2_DCR \
+    (volatile uint32_t *) (TIM2_BASE + 0x48) /* TIM2 DMA control register */
+#define TIM2_DMAR                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x4C) /* TIM2 DMA address for full transfer */
+#define TIM2_OR \
+    (volatile uint32_t *) (TIM2_BASE + 0x50) /* TIM2 option register */
 /* Power Control (PWR) */
-#define PWR_CR                          (volatile uint32_t *) (PWR_BASE + 0x00)                 /* Power Control Register */
-#define PWR_CSR                         (volatile uint32_t *) (PWR_BASE + 0x04)                 /* Power Control/Status Register */
+#define PWR_CR \
+    (volatile uint32_t *) (PWR_BASE + 0x00) /* Power Control Register */
+#define PWR_CSR                                                              \
+    (volatile uint32_t *) (PWR_BASE + 0x04) /* Power Control/Status Register \
+                                             */
 
 /* SPI */
-#define SPI_BASE(port)                  (port)                                                  /* Temporary SPI base */
-#define SPI_CR1(port)                   (volatile uint32_t *) (SPI_BASE(port) + 0x00)           /* SPI control register 1 */
-#define SPI_CR2(port)                   (volatile uint32_t *) (SPI_BASE(port) + 0x04)           /* SPI control register 2 */
-#define SPI_SR(port)                    (volatile uint32_t *) (SPI_BASE(port) + 0x08)           /* SPI status register */
-#define SPI_DR(port)                    (volatile uint32_t *) (SPI_BASE(port) + 0x0c)           /* SPI data register */
-#define SPI_CRCPR(port)                 (volatile uint32_t *) (SPI_BASE(port) + 0x10)           /* SPI CRC polynomial register */
-#define SPI_RXCRCR(port)                (volatile uint32_t *) (SPI_BASE(port) + 0x14)           /* SPI RX CRC register */
-#define SPI_TXCRCR(port)                (volatile uint32_t *) (SPI_BASE(port) + 0x18)           /* SPI TX CRC register */
-#define SPI_I2SCFGR(port)               (volatile uint32_t *) (SPI_BASE(port) + 0x1c)           /* SPI I2C configuration register */
-#define SPI_I2SPR(port)                 (volatile uint32_t *) (SPI_BASE(port) + 0x20)           /* SPI I2C prescaler register */
+#define SPI_BASE(port) (port) /* Temporary SPI base */
+#define SPI_CR1(port) \
+    (volatile uint32_t *) (SPI_BASE(port) + 0x00) /* SPI control register 1 */
+#define SPI_CR2(port) \
+    (volatile uint32_t *) (SPI_BASE(port) + 0x04) /* SPI control register 2 */
+#define SPI_SR(port) \
+    (volatile uint32_t *) (SPI_BASE(port) + 0x08) /* SPI status register */
+#define SPI_DR(port) \
+    (volatile uint32_t *) (SPI_BASE(port) + 0x0c) /* SPI data register */
+#define SPI_CRCPR(port)                     \
+    (volatile uint32_t *) (SPI_BASE(port) + \
+                           0x10) /* SPI CRC polynomial register */
+#define SPI_RXCRCR(port) \
+    (volatile uint32_t *) (SPI_BASE(port) + 0x14) /* SPI RX CRC register */
+#define SPI_TXCRCR(port) \
+    (volatile uint32_t *) (SPI_BASE(port) + 0x18) /* SPI TX CRC register */
+#define SPI_I2SCFGR(port)                   \
+    (volatile uint32_t *) (SPI_BASE(port) + \
+                           0x1c) /* SPI I2C configuration register */
+#define SPI_I2SPR(port)                     \
+    (volatile uint32_t *) (SPI_BASE(port) + \
+                           0x20) /* SPI I2C prescaler register */
 
 /* I2C */
-#define I2C_CR1(port)                   (volatile uint32_t *) (I2C_BASE(port) + 0x00)           /* I2C control register 1 */
-#define I2C_CR2(port)                   (volatile uint32_t *) (I2C_BASE(port) + 0x04)           /* I2C control register 2 */
-#define I2C_OAR1(port)                  (volatile uint32_t *) (I2C_BASE(port) + 0x08)           /* I2C own address register 1 */
-#define I2C_OAR2(port)                  (volatile uint32_t *) (I2C_BASE(port) + 0x0C)           /* I2C own address register 2 */
-#define I2C_DR(port)                    (volatile uint32_t *) (I2C_BASE(port) + 0x10)           /* I2C data register */
-#define I2C_SR1(port)                   (volatile uint32_t *) (I2C_BASE(port) + 0x14)           /* I2C status register 1 */
-#define I2C_SR2(port)                   (volatile uint32_t *) (I2C_BASE(port) + 0x18)           /* I2C status register 2 */
-#define I2C_CCR(port)                   (volatile uint32_t *) (I2C_BASE(port) + 0x1C)           /* I2C clock control register */
-#define I2C_TRISE(port)                 (volatile uint32_t *) (I2C_BASE(port) + 0x20)           /* I2C TRISE register */
+#define I2C_CR1(port) \
+    (volatile uint32_t *) (I2C_BASE(port) + 0x00) /* I2C control register 1 */
+#define I2C_CR2(port) \
+    (volatile uint32_t *) (I2C_BASE(port) + 0x04) /* I2C control register 2 */
+#define I2C_OAR1(port)                      \
+    (volatile uint32_t *) (I2C_BASE(port) + \
+                           0x08) /* I2C own address register 1 */
+#define I2C_OAR2(port)                      \
+    (volatile uint32_t *) (I2C_BASE(port) + \
+                           0x0C) /* I2C own address register 2 */
+#define I2C_DR(port) \
+    (volatile uint32_t *) (I2C_BASE(port) + 0x10) /* I2C data register */
+#define I2C_SR1(port) \
+    (volatile uint32_t *) (I2C_BASE(port) + 0x14) /* I2C status register 1 */
+#define I2C_SR2(port) \
+    (volatile uint32_t *) (I2C_BASE(port) + 0x18) /* I2C status register 2 */
+#define I2C_CCR(port)                       \
+    (volatile uint32_t *) (I2C_BASE(port) + \
+                           0x1C) /* I2C clock control register */
+#define I2C_TRISE(port) \
+    (volatile uint32_t *) (I2C_BASE(port) + 0x20) /* I2C TRISE register */
 
 /* USART 1 */
-#define USART1_SR                       (volatile uint32_t *) (USART1_BASE + 0x00)              /* USART1 status register */
-#define USART1_DR                       (volatile uint32_t *) (USART1_BASE + 0x04)              /* USART1 data register */
-#define USART1_BRR                      (volatile uint32_t *) (USART1_BASE + 0x08)              /* USART1 baud rate register */
-#define USART1_CR1                      (volatile uint32_t *) (USART1_BASE + 0x0C)              /* USART1 control register 1 */
-#define USART1_CR2                      (volatile uint32_t *) (USART1_BASE + 0x10)              /* USART1 control register 2 */
-#define USART1_CR3                      (volatile uint32_t *) (USART1_BASE + 0x14)              /* USART1 control register 3 */
-#define USART1_GTPR                     (volatile uint32_t *) (USART1_BASE + 0x18)              /* USART1 gaurd time and prescale register */
+#define USART1_SR \
+    (volatile uint32_t *) (USART1_BASE + 0x00) /* USART1 status register */
+#define USART1_DR \
+    (volatile uint32_t *) (USART1_BASE + 0x04) /* USART1 data register */
+#define USART1_BRR \
+    (volatile uint32_t *) (USART1_BASE + 0x08) /* USART1 baud rate register */
+#define USART1_CR1 \
+    (volatile uint32_t *) (USART1_BASE + 0x0C) /* USART1 control register 1 */
+#define USART1_CR2 \
+    (volatile uint32_t *) (USART1_BASE + 0x10) /* USART1 control register 2 */
+#define USART1_CR3 \
+    (volatile uint32_t *) (USART1_BASE + 0x14) /* USART1 control register 3 */
+#define USART1_GTPR                      \
+    (volatile uint32_t *) (USART1_BASE + \
+                           0x18) /* USART1 gaurd time and prescale register */
 
 /* GPIO Port (GPIO) */
-#define GPIO_CRL(port)                  (volatile uint32_t *) (GPIO_BASE(port) + 0x00)          /* Port configuration low register */
-#define GPIO_CRH(port)                  (volatile uint32_t *) (GPIO_BASE(port) + 0x04)          /* Port configuration high register */
-#define GPIO_IDR(port)                  (volatile uint32_t *) (GPIO_BASE(port) + 0x08)          /* Port input data register */
-#define GPIO_ODR(port)                  (volatile uint32_t *) (GPIO_BASE(port) + 0x0C)          /* Port output data register */
-#define GPIO_BSRR(port)                 (volatile uint32_t *) (GPIO_BASE(port) + 0x10)          /* Port bit set/reset register */
-#define GPIO_BRR(port)                  (volatile uint32_t *) (GPIO_BASE(port) + 0x14)          /* Port bit reset register */
-#define GPIO_LCKR(port)                 (volatile uint32_t *) (GPIO_BASE(port) + 0x18)          /* Port configuration lock register */
+#define GPIO_CRL(port)                       \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x00) /* Port configuration low register */
+#define GPIO_CRH(port)                       \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x04) /* Port configuration high register */
+#define GPIO_IDR(port)                       \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x08) /* Port input data register */
+#define GPIO_ODR(port)                       \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x0C) /* Port output data register */
+#define GPIO_BSRR(port)                      \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x10) /* Port bit set/reset register */
+#define GPIO_BRR(port)                                                        \
+    (volatile uint32_t *) (GPIO_BASE(port) + 0x14) /* Port bit reset register \
+                                                    */
+#define GPIO_LCKR(port)                      \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x18) /* Port configuration lock register */
 
 /* Reset and Clock Control (RCC) */
-#define RCC_CR                          (volatile uint32_t *) (RCC_BASE + 0x00)                 /* Clock Control Register */
-#define RCC_CFGR                        (volatile uint32_t *) (RCC_BASE + 0x04)                 /* Clock Configuration Register */
-#define RCC_CIR                         (volatile uint32_t *) (RCC_BASE + 0x08)                 /* Clock Interrupt Register */
-#define RCC_APB2RSTR                    (volatile uint32_t *) (RCC_BASE + 0x0C)                 /* APB2 reset Register */
-#define RCC_APB1RSTR                    (volatile uint32_t *) (RCC_BASE + 0x10)                 /* APB1 reset Register */
-#define RCC_AHBENR                      (volatile uint32_t *) (RCC_BASE + 0x14)                 /* AHB Enable Register */
-#define RCC_APB2ENR                     (volatile uint32_t *) (RCC_BASE + 0x18)                 /* APB2 Peripheral Clock Enable Register */
-#define RCC_APB1ENR                     (volatile uint32_t *) (RCC_BASE + 0x1C)                 /* APB1 Peripheral Clock Enable Register */
-#define RCC_BDCR                        (volatile uint32_t *) (RCC_BASE + 0x20)                 /* RCC Backup Domain Control Register */
-#define RCC_CSR                         (volatile uint32_t *) (RCC_BASE + 0x24)                 /* RCC Clock Control & Status Register */
-#define RCC_AHBRSTR                     (volatile uint32_t *) (RCC_BASE + 0x28)                 /* AHB reset Register */
+#define RCC_CR \
+    (volatile uint32_t *) (RCC_BASE + 0x00) /* Clock Control Register */
+#define RCC_CFGR \
+    (volatile uint32_t *) (RCC_BASE + 0x04) /* Clock Configuration Register */
+#define RCC_CIR \
+    (volatile uint32_t *) (RCC_BASE + 0x08) /* Clock Interrupt Register */
+#define RCC_APB2RSTR \
+    (volatile uint32_t *) (RCC_BASE + 0x0C) /* APB2 reset Register */
+#define RCC_APB1RSTR \
+    (volatile uint32_t *) (RCC_BASE + 0x10) /* APB1 reset Register */
+#define RCC_AHBENR \
+    (volatile uint32_t *) (RCC_BASE + 0x14) /* AHB Enable Register */
+#define RCC_APB2ENR                   \
+    (volatile uint32_t *) (RCC_BASE + \
+                           0x18) /* APB2 Peripheral Clock Enable Register */
+#define RCC_APB1ENR                   \
+    (volatile uint32_t *) (RCC_BASE + \
+                           0x1C) /* APB1 Peripheral Clock Enable Register */
+#define RCC_BDCR                      \
+    (volatile uint32_t *) (RCC_BASE + \
+                           0x20) /* RCC Backup Domain Control Register */
+#define RCC_CSR                       \
+    (volatile uint32_t *) (RCC_BASE + \
+                           0x24) /* RCC Clock Control & Status Register */
+#define RCC_AHBRSTR \
+    (volatile uint32_t *) (RCC_BASE + 0x28) /* AHB reset Register */
 
 /* APB1 RCC ENR */
-#define RCC_TIM2_APBENR					RCC_APB1ENR
-#define RCC_TIM3_APBENR					RCC_APB1ENR
-#define RCC_TIM4_APBENR					RCC_APB1ENR
-#define RCC_RTC_APBENR					RCC_APB1ENR
-#define RCC_WWDG_APBENR					RCC_APB1ENR
-#define RCC_IWDG_APBENR					RCC_APB1ENR
-#define RCC_SPI2_APBENR					RCC_APB1ENR
-#define RCC_USART2_APBENR				RCC_APB1ENR
-#define RCC_USART3_APBENR				RCC_APB1ENR
-#define RCC_I2C1_APBENR					RCC_APB1ENR
-#define RCC_I2C2_APBENR					RCC_APB1ENR
-#define RCC_CAN1_APBENR					RCC_APB1ENR
-#define RCC_BKP_APBENR					RCC_APB1ENR
-#define RCC_PWR_APBENR					RCC_APB1ENR
+#define RCC_TIM2_APBENR RCC_APB1ENR
+#define RCC_TIM3_APBENR RCC_APB1ENR
+#define RCC_TIM4_APBENR RCC_APB1ENR
+#define RCC_RTC_APBENR RCC_APB1ENR
+#define RCC_WWDG_APBENR RCC_APB1ENR
+#define RCC_IWDG_APBENR RCC_APB1ENR
+#define RCC_SPI2_APBENR RCC_APB1ENR
+#define RCC_USART2_APBENR RCC_APB1ENR
+#define RCC_USART3_APBENR RCC_APB1ENR
+#define RCC_I2C1_APBENR RCC_APB1ENR
+#define RCC_I2C2_APBENR RCC_APB1ENR
+#define RCC_CAN1_APBENR RCC_APB1ENR
+#define RCC_BKP_APBENR RCC_APB1ENR
+#define RCC_PWR_APBENR RCC_APB1ENR
 
 /* APB2 RCC ENR */
-#define RCC_AFIO_APBENR 				RCC_APB2ENR
-#define RCC_EXTI_APBENR 				RCC_APB2ENR
-#define RCC_GPIO_APBENR					RCC_APB2ENR
-#define RCC_ADC1_APBENR					RCC_APB2ENR
-#define RCC_ADC2_APBENR					RCC_APB2ENR
-#define RCC_TIM1_APBENR					RCC_APB2ENR
-#define RCC_SPI1_APBENR					RCC_APB2ENR
-#define RCC_USART1_APBENR				RCC_APB2ENR
+#define RCC_AFIO_APBENR RCC_APB2ENR
+#define RCC_EXTI_APBENR RCC_APB2ENR
+#define RCC_GPIO_APBENR RCC_APB2ENR
+#define RCC_ADC1_APBENR RCC_APB2ENR
+#define RCC_ADC2_APBENR RCC_APB2ENR
+#define RCC_TIM1_APBENR RCC_APB2ENR
+#define RCC_SPI1_APBENR RCC_APB2ENR
+#define RCC_USART1_APBENR RCC_APB2ENR
 
 /* Flash Registers (FLASH) */
-#define FLASH_ACR                       (volatile uint32_t *) (FLASH_R_BASE + 0x00)             /* Flash Access Control Register */
+#define FLASH_ACR                         \
+    (volatile uint32_t *) (FLASH_R_BASE + \
+                           0x00) /* Flash Access Control Register */
 
 /* Direct Memory Access  (DMA) */
-#define DMA_LISR                       (volatile uint32_t *) (DMA_BASE + 0x00)                  /* DMA interrupt status register */
-#define DMA_IFCR                       (volatile uint32_t *) (DMA_BASE + 0x04)                  /* DMA interrupt flag clear register */
+#define DMA_LISR                                                             \
+    (volatile uint32_t *) (DMA_BASE + 0x00) /* DMA interrupt status register \
+                                             */
+#define DMA_IFCR                      \
+    (volatile uint32_t *) (DMA_BASE + \
+                           0x04) /* DMA interrupt flag clear register */
 /* Channel n */
-#define DMA_CR_C(n)                    (volatile uint32_t *) (DMA_BASE + 0x08 + (0x14*n))      /* DMA stream n configuration register */
-#define DMA_NDTR_C(n)                  (volatile uint32_t *) (DMA_BASE + 0x0C + (0x14*n))      /* DMA stream n number of data register */
-#define DMA_PAR_C(n)                   (volatile uint32_t *) (DMA_BASE + 0x10 + (0x14*n))      /* DMA stream n peripheral address register */
-#define DMA_MAR_C(n)                   (volatile uint32_t *) (DMA_BASE + 0x14 + (0x14*n))      /* DMA stream n memory 0 address register */
+#define DMA_CR_C(n)                          \
+    (volatile uint32_t *) (DMA_BASE + 0x08 + \
+                           (0x14 *           \
+                            n)) /* DMA stream n configuration register */
+#define DMA_NDTR_C(n)                        \
+    (volatile uint32_t *) (DMA_BASE + 0x0C + \
+                           (0x14 *           \
+                            n)) /* DMA stream n number of data register */
+#define DMA_PAR_C(n)                         \
+    (volatile uint32_t *) (DMA_BASE + 0x10 + \
+                           (0x14 *           \
+                            n)) /* DMA stream n peripheral address register */
+#define DMA_MAR_C(n)                         \
+    (volatile uint32_t *) (DMA_BASE + 0x14 + \
+                           (0x14 *           \
+                            n)) /* DMA stream n memory 0 address register */
 
 /**********************************************************************************************************************************************/
 
 /* Bit Masks - See RM0090 Reference Manual for STM32F4 for details */
 
-#define RCC_CR_HSION                    (uint32_t) (1 << 0)                                     /* HSI clock enable */
-#define RCC_CR_HSIRDY                   (uint32_t) (1 << 1)                                     /* HSI ready */
-#define RCC_CR_HSITRIM_M                (uint32_t) (0xF8 << 0)                                  /* HSI trimming mask */
-#define RCC_CR_HSICAL_M                 (uint32_t) (0xFF << 8)                                  /* HSI calibration mask */
-#define RCC_CR_HSEON                    (uint32_t) (1 << 16)                                    /* HSE clock enable */
-#define RCC_CR_HSERDY                   (uint32_t) (1 << 17)                                    /* HSE ready */
-#define RCC_CR_HSEBYP                   (uint32_t) (1 << 18)                                    /* HSE bypass */
-#define RCC_CR_CSSON                    (uint32_t) (1 << 19)                                    /* Clock security system enable */
-#define RCC_CR_PLLON                    (uint32_t) (1 << 24)                                    /* Main PLL enable */
-#define RCC_CR_PLLRDY                   (uint32_t) (1 << 25)                                    /* Main PLL clock ready */
-
-#define RCC_CFGR_SW_M                   (uint32_t) (3 << 0)                                     /* System clock switch mask */
-#define RCC_CFGR_SW_HSI                 (uint32_t) (0 << 0)                                     /* System clock switch - HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                 (uint32_t) (1 << 0)                                     /* System clock switch - HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                 (uint32_t) (2 << 0)                                     /* System clock switch - PLL selected as system clock */
-#define RCC_CFGR_SWS_M                  (uint32_t) (3 << 2)                                     /* System clock switch status mask */
-#define RCC_CFGR_SWS_HSI                (uint32_t) (0 << 2)                                     /* System clock switch status - HSI used as system clock */
-#define RCC_CFGR_SWS_HSE                (uint32_t) (1 << 2)                                     /* System clock switch status - HSE used as system clock */
-#define RCC_CFGR_SWS_PLL                (uint32_t) (2 << 2)                                     /* System clock switch status - PLL used as system clock */
-#define RCC_CFGR_HPRE_M                 (uint32_t) (0xF << 4)                                   /* AHB prescaler mask */
-#define RCC_CFGR_HPRE_DIV1              (uint32_t) (0x0 << 4)                                   /* AHB prescaler - SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2              (uint32_t) (0x8 << 4)                                   /* AHB prescaler - SYSCLK/2 */
-#define RCC_CFGR_HPRE_DIV4              (uint32_t) (0x9 << 4)                                   /* AHB prescaler - SYSCLK/4 */
-#define RCC_CFGR_HPRE_DIV8              (uint32_t) (0xA << 4)                                   /* AHB prescaler - SYSCLK/8 */
-#define RCC_CFGR_HPRE_DIV16             (uint32_t) (0xB << 4)                                   /* AHB prescaler - SYSCLK/16 */
-#define RCC_CFGR_HPRE_DIV64             (uint32_t) (0xC << 4)                                   /* AHB prescaler - SYSCLK/64 */
-#define RCC_CFGR_HPRE_DIV128            (uint32_t) (0xD << 4)                                   /* AHB prescaler - SYSCLK/128 */
-#define RCC_CFGR_HPRE_DIV256            (uint32_t) (0xE << 4)                                   /* AHB prescaler - SYSCLK/256 */
-#define RCC_CFGR_HPRE_DIV512            (uint32_t) (0xF << 4)                                   /* AHB prescaler - SYSCLK/512 */
-#define RCC_CFGR_PPRE1_M                (uint32_t) (0x7 << 8)                                   /* APB low speed prescaler mask */
-#define RCC_CFGR_PPRE1_DIV1             (uint32_t) (0x0 << 8)                                   /* APB low speed prescaler - HCLK/1 */
-#define RCC_CFGR_PPRE1_DIV2             (uint32_t) (0x4 << 8)                                   /* APB low speed prescaler - HCLK/2 */
-#define RCC_CFGR_PPRE1_DIV4             (uint32_t) (0x5 << 8)                                   /* APB low speed prescaler - HCLK/4 */
-#define RCC_CFGR_PPRE1_DIV8             (uint32_t) (0x6 << 8)                                   /* APB low speed prescaler - HCLK/8 */
-#define RCC_CFGR_PPRE1_DIV16            (uint32_t) (0x7 << 8)                                   /* APB low speed prescaler - HCLK/16 */
-#define RCC_CFGR_PPRE2_M                (uint32_t) (0x38 << 8)                                  /* APB high speec prescaler mask */
-#define RCC_CFGR_PPRE2_DIV1             (uint32_t) (0x0 << 8)                                   /* APB high speed prescaler - HCLK/1 */
-#define RCC_CFGR_PPRE2_DIV2             (uint32_t) (0x20 << 8)                                  /* APB high speed prescaler - HCLK/2 */
-#define RCC_CFGR_PPRE2_DIV4             (uint32_t) (0x28 << 8)                                  /* APB high speed prescaler - HCLK/4 */
-#define RCC_CFGR_PPRE2_DIV8             (uint32_t) (0x30 << 8)                                  /* APB high speed prescaler - HCLK/8 */
-#define RCC_CFGR_PPRE2_DIV16            (uint32_t) (0x38 << 8)                                  /* APB high speed prescaler - HCLK/16 */
-#define RCC_CFGR_RTCPRE_M               (uint32_t) (0x1F << 16)                                 /* HSE division factor for RTC clock mask */
-#define RCC_CFGR_RTCPRE(n)              (uint32_t) (n << 16)                                    /* HSE division factor for RTC clock */
-
-#define RCC_AHBRSTR_ETHMACRST          (uint32_t) (1 << 14)                                    /* Ethernet MAC reset */
-#define RCC_AHBRSTR_OTGFSRST           (uint32_t) (1 << 12)                                    /* USB OTG FS reset */
-
-#define RCC_APB1RSTR_TIM2RST            (uint32_t) (1 << 0)                                     /* TIM2 reset */
-#define RCC_APB1RSTR_TIM3RST            (uint32_t) (1 << 1)                                     /* TIM3 reset */
-#define RCC_APB1RSTR_TIM4RST            (uint32_t) (1 << 2)                                     /* TIM4 reset */
-#define RCC_APB1RSTR_WWDGRST            (uint32_t) (1 << 11)                                    /* Window watchdog reset */
-#define RCC_APB1RSTR_SPI2RST            (uint32_t) (1 << 14)                                    /* SPI2 reset */
-#define RCC_APB1RSTR_USART2RST          (uint32_t) (1 << 17)                                    /* USART2 reset */
-#define RCC_APB1RSTR_USART3RST          (uint32_t) (1 << 18)                                    /* USART3 reset */
-#define RCC_APB1RSTR_I2C1RST            (uint32_t) (1 << 21)                                    /* I2C1 reset */
-#define RCC_APB1RSTR_I2C2RST            (uint32_t) (1 << 22)                                    /* I2C2 reset */
-#define RCC_APB1RSTR_CAN1RST            (uint32_t) (1 << 25)                                    /* CAN1 reset */
-#define RCC_APB1RSTR_BKPRST             (uint32_t) (1 << 27)                                    /* Backup interface reset */
-#define RCC_APB1RSTR_PWRRST             (uint32_t) (1 << 28)                                    /* Power interface reset */
-#define RCC_APB1RSTR_DACRST             (uint32_t) (1 << 29)                                    /* DAC reset */
-
-#define RCC_APB2RSTR_AFIORST            (uint32_t) (1 << 0)                                     /* Alternate Function I/O reset */
-#define RCC_APB2RSTR_IOPARST            (uint32_t) (1 << 2)                                     /* Alternate Function I/O port A reset */
-#define RCC_APB2RSTR_IOPBRST            (uint32_t) (1 << 3)                                     /* Alternate Function I/O port B reset */
-#define RCC_APB2RSTR_IOPCRST            (uint32_t) (1 << 4)                                     /* Alternate Function I/O port C reset */
-#define RCC_APB2RSTR_IOPDRST            (uint32_t) (1 << 5)                                     /* Alternate Function I/O port D reset */
-#define RCC_APB2RSTR_IOPERST            (uint32_t) (1 << 6)                                     /* Alternate Function I/O port E reset */
-#define RCC_APB2RSTR_ADC1RST            (uint32_t) (1 << 9)                                     /* ADC 1 interface reset */
-#define RCC_APB2RSTR_ADC2RST            (uint32_t) (1 << 10)                                    /* ADC 2 interface reset */
-#define RCC_APB2RSTR_TIM1RST            (uint32_t) (1 << 11)                                    /* TIM1 reset */
-#define RCC_APB2RSTR_SPI1RST            (uint32_t) (1 << 12)                                    /* SPI 1 reset */
-#define RCC_APB2RSTR_USART1RST          (uint32_t) (1 << 14)                                    /* USART1 reset */
-
-#define RCC_AHBENR_DMA1EN               (uint16_t) (1 << 0)                                     /* DMA1 clock enable */
-#define RCC_AHBENR_SRAMEN               (uint16_t) (1 << 2)                                     /* SRAM interface clock enable */
-#define RCC_AHBENR_FLITFEN              (uint16_t) (1 << 4)                                     /* FLITF clock enable */
-#define RCC_AHBENR_CRCEN                (uint16_t) (1 << 6)                                     /* CRC clock enable */
-
-#define RCC_APB1ENR_TIM2EN              (uint32_t) (1 << 0)                                     /* TIM2 clock enable */
-#define RCC_APB1ENR_TIM3EN              (uint32_t) (1 << 1)                                     /* TIM3 clock enable */
-#define RCC_APB1ENR_TIM4EN              (uint32_t) (1 << 2)                                     /* TIM4 clock enable */
-#define RCC_APB1ENR_WWDGEN              (uint32_t) (1 << 11)                                    /* Window watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN              (uint32_t) (1 << 14)                                    /* SPI2 clock enable */
-#define RCC_APB1ENR_USART2EN            (uint32_t) (1 << 17)                                    /* USART2 clock enable */
-#define RCC_APB1ENR_USART3EN            (uint32_t) (1 << 18)                                    /* USART3 clock enable */
-#define RCC_APB1ENR_I2C1EN              (uint32_t) (1 << 21)                                    /* I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN              (uint32_t) (1 << 22)                                    /* I2C2 clock enable */
-#define RCC_APB1ENR_CAN1EN              (uint32_t) (1 << 25)                                    /* CAN1 clock enable */
-#define RCC_APB1ENR_BKPEN               (uint32_t) (1 << 27)                                    /* Backup interface clock enable */
-#define RCC_APB1ENR_PWREN               (uint32_t) (1 << 28)                                    /* Power interface clock enable */
-
-#define RCC_APB2ENR_AFIOEN              (uint32_t) (1 << 0)                                     /* Alternate Function I/O clock enable */
-#define RCC_APB2ENR_IOPAEN              (uint32_t) (1 << 2)                                     /* Alternate Function I/O port A clock enable */
-#define RCC_APB2ENR_IOPBEN              (uint32_t) (1 << 3)                                     /* Alternate Function I/O port B clock enable */
-#define RCC_APB2ENR_IOPCEN              (uint32_t) (1 << 4)                                     /* Alternate Function I/O port C clock enable */
-#define RCC_APB2ENR_IOPDEN              (uint32_t) (1 << 5)                                     /* Alternate Function I/O port D clock enable */
-#define RCC_APB2ENR_IOPEEN              (uint32_t) (1 << 6)                                     /* Alternate Function I/O port E clock enable */
-#define RCC_APB2ENR_ADC1EN              (uint32_t) (1 << 9)                                     /* ADC 1 interface clock enable */
-#define RCC_APB2ENR_ADC2EN              (uint32_t) (1 << 10)                                    /* ADC 2 interface clock enable */
-#define RCC_APB2ENR_TIM1EN              (uint32_t) (1 << 11)                                    /* TIM1 clock enable */
-#define RCC_APB2ENR_SPI1EN              (uint32_t) (1 << 12)                                    /* SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN            (uint32_t) (1 << 14)                                     /* USART1 clock enable */
-
-#define FLASH_ACR_PRFTEN                (uint32_t) (1 << 4)                                     /* Prefetch enable */
-#define FLASH_ACR_LATENCY_M             (uint32_t) (3 << 0)                                     /* Latency mask */
-#define FLASH_ACR_LATENCY(n)            (uint32_t) (n << 0)                                     /* Latency - n wait states */
+#define RCC_CR_HSION (uint32_t) (1 << 0)        /* HSI clock enable */
+#define RCC_CR_HSIRDY (uint32_t) (1 << 1)       /* HSI ready */
+#define RCC_CR_HSITRIM_M (uint32_t) (0xF8 << 0) /* HSI trimming mask */
+#define RCC_CR_HSICAL_M (uint32_t) (0xFF << 8)  /* HSI calibration mask */
+#define RCC_CR_HSEON (uint32_t) (1 << 16)       /* HSE clock enable */
+#define RCC_CR_HSERDY (uint32_t) (1 << 17)      /* HSE ready */
+#define RCC_CR_HSEBYP (uint32_t) (1 << 18)      /* HSE bypass */
+#define RCC_CR_CSSON (uint32_t) (1 << 19)  /* Clock security system enable */
+#define RCC_CR_PLLON (uint32_t) (1 << 24)  /* Main PLL enable */
+#define RCC_CR_PLLRDY (uint32_t) (1 << 25) /* Main PLL clock ready */
+
+#define RCC_CFGR_SW_M (uint32_t) (3 << 0) /* System clock switch mask */
+#define RCC_CFGR_SW_HSI                                                       \
+    (uint32_t) (0 << 0) /* System clock switch - HSI selected as system clock \
+                         */
+#define RCC_CFGR_SW_HSE                                                       \
+    (uint32_t) (1 << 0) /* System clock switch - HSE selected as system clock \
+                         */
+#define RCC_CFGR_SW_PLL                                                       \
+    (uint32_t) (2 << 0) /* System clock switch - PLL selected as system clock \
+                         */
+#define RCC_CFGR_SWS_M                                     \
+    (uint32_t) (3 << 2) /* System clock switch status mask \
+                         */
+#define RCC_CFGR_SWS_HSI                                                   \
+    (uint32_t) (0 << 2) /* System clock switch status - HSI used as system \
+                           clock */
+#define RCC_CFGR_SWS_HSE                                                   \
+    (uint32_t) (1 << 2) /* System clock switch status - HSE used as system \
+                           clock */
+#define RCC_CFGR_SWS_PLL                                                   \
+    (uint32_t) (2 << 2) /* System clock switch status - PLL used as system \
+                           clock */
+#define RCC_CFGR_HPRE_M (uint32_t) (0xF << 4) /* AHB prescaler mask */
+#define RCC_CFGR_HPRE_DIV1 \
+    (uint32_t) (0x0 << 4) /* AHB prescaler - SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2                            \
+    (uint32_t) (0x8 << 4) /* AHB prescaler - SYSCLK/2 \
+                           */
+#define RCC_CFGR_HPRE_DIV4                            \
+    (uint32_t) (0x9 << 4) /* AHB prescaler - SYSCLK/4 \
+                           */
+#define RCC_CFGR_HPRE_DIV8                            \
+    (uint32_t) (0xA << 4) /* AHB prescaler - SYSCLK/8 \
+                           */
+#define RCC_CFGR_HPRE_DIV16 \
+    (uint32_t) (0xB << 4) /* AHB prescaler - SYSCLK/16 */
+#define RCC_CFGR_HPRE_DIV64 \
+    (uint32_t) (0xC << 4) /* AHB prescaler - SYSCLK/64 */
+#define RCC_CFGR_HPRE_DIV128 \
+    (uint32_t) (0xD << 4) /* AHB prescaler - SYSCLK/128 */
+#define RCC_CFGR_HPRE_DIV256 \
+    (uint32_t) (0xE << 4) /* AHB prescaler - SYSCLK/256 */
+#define RCC_CFGR_HPRE_DIV512 \
+    (uint32_t) (0xF << 4) /* AHB prescaler - SYSCLK/512 */
+#define RCC_CFGR_PPRE1_M \
+    (uint32_t) (0x7 << 8) /* APB low speed prescaler mask */
+#define RCC_CFGR_PPRE1_DIV1 \
+    (uint32_t) (0x0 << 8) /* APB low speed prescaler - HCLK/1 */
+#define RCC_CFGR_PPRE1_DIV2 \
+    (uint32_t) (0x4 << 8) /* APB low speed prescaler - HCLK/2 */
+#define RCC_CFGR_PPRE1_DIV4 \
+    (uint32_t) (0x5 << 8) /* APB low speed prescaler - HCLK/4 */
+#define RCC_CFGR_PPRE1_DIV8 \
+    (uint32_t) (0x6 << 8) /* APB low speed prescaler - HCLK/8 */
+#define RCC_CFGR_PPRE1_DIV16 \
+    (uint32_t) (0x7 << 8) /* APB low speed prescaler - HCLK/16 */
+#define RCC_CFGR_PPRE2_M \
+    (uint32_t) (0x38 << 8) /* APB high speec prescaler mask */
+#define RCC_CFGR_PPRE2_DIV1 \
+    (uint32_t) (0x0 << 8) /* APB high speed prescaler - HCLK/1 */
+#define RCC_CFGR_PPRE2_DIV2 \
+    (uint32_t) (0x20 << 8) /* APB high speed prescaler - HCLK/2 */
+#define RCC_CFGR_PPRE2_DIV4 \
+    (uint32_t) (0x28 << 8) /* APB high speed prescaler - HCLK/4 */
+#define RCC_CFGR_PPRE2_DIV8 \
+    (uint32_t) (0x30 << 8) /* APB high speed prescaler - HCLK/8 */
+#define RCC_CFGR_PPRE2_DIV16 \
+    (uint32_t) (0x38 << 8) /* APB high speed prescaler - HCLK/16 */
+#define RCC_CFGR_RTCPRE_M \
+    (uint32_t) (0x1F << 16) /* HSE division factor for RTC clock mask */
+#define RCC_CFGR_RTCPRE(n) \
+    (uint32_t) (n << 16) /* HSE division factor for RTC clock */
+
+#define RCC_AHBRSTR_ETHMACRST (uint32_t) (1 << 14) /* Ethernet MAC reset */
+#define RCC_AHBRSTR_OTGFSRST (uint32_t) (1 << 12)  /* USB OTG FS reset */
+
+#define RCC_APB1RSTR_TIM2RST (uint32_t) (1 << 0)    /* TIM2 reset */
+#define RCC_APB1RSTR_TIM3RST (uint32_t) (1 << 1)    /* TIM3 reset */
+#define RCC_APB1RSTR_TIM4RST (uint32_t) (1 << 2)    /* TIM4 reset */
+#define RCC_APB1RSTR_WWDGRST (uint32_t) (1 << 11)   /* Window watchdog reset */
+#define RCC_APB1RSTR_SPI2RST (uint32_t) (1 << 14)   /* SPI2 reset */
+#define RCC_APB1RSTR_USART2RST (uint32_t) (1 << 17) /* USART2 reset */
+#define RCC_APB1RSTR_USART3RST (uint32_t) (1 << 18) /* USART3 reset */
+#define RCC_APB1RSTR_I2C1RST (uint32_t) (1 << 21)   /* I2C1 reset */
+#define RCC_APB1RSTR_I2C2RST (uint32_t) (1 << 22)   /* I2C2 reset */
+#define RCC_APB1RSTR_CAN1RST (uint32_t) (1 << 25)   /* CAN1 reset */
+#define RCC_APB1RSTR_BKPRST (uint32_t) (1 << 27)    /* Backup interface reset */
+#define RCC_APB1RSTR_PWRRST (uint32_t) (1 << 28)    /* Power interface reset */
+#define RCC_APB1RSTR_DACRST (uint32_t) (1 << 29)    /* DAC reset */
+
+#define RCC_APB2RSTR_AFIORST \
+    (uint32_t) (1 << 0) /* Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST \
+    (uint32_t) (1 << 2) /* Alternate Function I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST \
+    (uint32_t) (1 << 3) /* Alternate Function I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST \
+    (uint32_t) (1 << 4) /* Alternate Function I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST \
+    (uint32_t) (1 << 5) /* Alternate Function I/O port D reset */
+#define RCC_APB2RSTR_IOPERST \
+    (uint32_t) (1 << 6) /* Alternate Function I/O port E reset */
+#define RCC_APB2RSTR_ADC1RST (uint32_t) (1 << 9)    /* ADC 1 interface reset */
+#define RCC_APB2RSTR_ADC2RST (uint32_t) (1 << 10)   /* ADC 2 interface reset */
+#define RCC_APB2RSTR_TIM1RST (uint32_t) (1 << 11)   /* TIM1 reset */
+#define RCC_APB2RSTR_SPI1RST (uint32_t) (1 << 12)   /* SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST (uint32_t) (1 << 14) /* USART1 reset */
+
+#define RCC_AHBENR_DMA1EN (uint16_t) (1 << 0) /* DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN                                                     \
+    (uint16_t) (1 << 2)                        /* SRAM interface clock enable \
+                                                */
+#define RCC_AHBENR_FLITFEN (uint16_t) (1 << 4) /* FLITF clock enable */
+#define RCC_AHBENR_CRCEN (uint16_t) (1 << 6)   /* CRC clock enable */
+
+#define RCC_APB1ENR_TIM2EN (uint32_t) (1 << 0) /* TIM2 clock enable */
+#define RCC_APB1ENR_TIM3EN (uint32_t) (1 << 1) /* TIM3 clock enable */
+#define RCC_APB1ENR_TIM4EN (uint32_t) (1 << 2) /* TIM4 clock enable */
+#define RCC_APB1ENR_WWDGEN \
+    (uint32_t) (1 << 11) /* Window watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN (uint32_t) (1 << 14)   /* SPI2 clock enable */
+#define RCC_APB1ENR_USART2EN (uint32_t) (1 << 17) /* USART2 clock enable */
+#define RCC_APB1ENR_USART3EN (uint32_t) (1 << 18) /* USART3 clock enable */
+#define RCC_APB1ENR_I2C1EN (uint32_t) (1 << 21)   /* I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN (uint32_t) (1 << 22)   /* I2C2 clock enable */
+#define RCC_APB1ENR_CAN1EN (uint32_t) (1 << 25)   /* CAN1 clock enable */
+#define RCC_APB1ENR_BKPEN \
+    (uint32_t) (1 << 27) /* Backup interface clock enable */
+#define RCC_APB1ENR_PWREN \
+    (uint32_t) (1 << 28) /* Power interface clock enable */
+
+#define RCC_APB2ENR_AFIOEN \
+    (uint32_t) (1 << 0) /* Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN \
+    (uint32_t) (1 << 2) /* Alternate Function I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN \
+    (uint32_t) (1 << 3) /* Alternate Function I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN \
+    (uint32_t) (1 << 4) /* Alternate Function I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN \
+    (uint32_t) (1 << 5) /* Alternate Function I/O port D clock enable */
+#define RCC_APB2ENR_IOPEEN \
+    (uint32_t) (1 << 6) /* Alternate Function I/O port E clock enable */
+#define RCC_APB2ENR_ADC1EN \
+    (uint32_t) (1 << 9) /* ADC 1 interface clock enable */
+#define RCC_APB2ENR_ADC2EN \
+    (uint32_t) (1 << 10) /* ADC 2 interface clock enable */
+#define RCC_APB2ENR_TIM1EN (uint32_t) (1 << 11)   /* TIM1 clock enable */
+#define RCC_APB2ENR_SPI1EN (uint32_t) (1 << 12)   /* SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN (uint32_t) (1 << 14) /* USART1 clock enable */
+
+#define FLASH_ACR_PRFTEN (uint32_t) (1 << 4)     /* Prefetch enable */
+#define FLASH_ACR_LATENCY_M (uint32_t) (3 << 0)  /* Latency mask */
+#define FLASH_ACR_LATENCY(n) (uint32_t) (n << 0) /* Latency - n wait states */
 
 /* TIMx */
-#define TIMx_CR1_CEN                    (uint32_t) (1 << 0)                                     /* TIMx counter enable */
-#define TIMx_CR1_UDIS                   (uint32_t) (1 << 1)                                     /* TIMx update disable */
-#define TIMx_CR1_URS                    (uint32_t) (1 << 2)                                     /* TIMx update request source */
-#define TIMx_CR1_OPM                    (uint32_t) (1 << 3)                                     /* TIMx one-pulse mode */
-#define TIMx_CR1_DIR_DOWN               (uint32_t) (1 << 4)                                     /* TIMx downcounter */
-#define TIMx_CR1_CMS_EDGE               (uint32_t) (0 << 5)                                     /* TIMx center-aligned mode selection - counter up or down depending on DIR bit */
-#define TIMx_CR1_CMS_CM1                (uint32_t) (1 << 5)                                     /* TIMx center-aligned mode selection - up and down, compare flags set down */
-#define TIMx_CR1_CMS_CM2                (uint32_t) (2 << 5)                                     /* TIMx center-aligned mode selection - up and down, compare flags set up */
-#define TIMx_CR1_CMS_CM3                (uint32_t) (3 << 5)                                     /* TIMx center-aligned mode selection - up and down, compare flags set up/down */
-#define TIMx_CR1_ARPE                   (uint32_t) (1 << 7)                                     /* TIMx auto-reload preload enable */
-#define TIMx_CR1_CKD_1                  (uint32_t) (0 << 8)                                     /* TIMx clock division 1 */
-#define TIMx_CR1_CKD_2                  (uint32_t) (1 << 8)                                     /* TIMx clock division 2 */
-#define TIMx_CR1_CKD_4                  (uint32_t) (2 << 8)                                     /* TIMx clock division 4 */
-
-#define TIMx_CR2_CCDS                   (uint32_t) (1 << 3)                                     /* TIMx capture/compare DMA requests send when update event occurs */
-#define TIMx_CR2_MMS_RST                (uint32_t) (0 << 4)                                     /* TIMx master mode - reset */
-#define TIMx_CR2_MMS_EN                 (uint32_t) (1 << 4)                                     /* TIMx master mode - enable */
-#define TIMx_CR2_MMS_UP                 (uint32_t) (2 << 4)                                     /* TIMx master mode - update */
-#define TIMx_CR2_MMS_CMP_PUL            (uint32_t) (3 << 4)                                     /* TIMx master mode - compare pulse */
-#define TIMx_CR2_MMS_CMP_OC1            (uint32_t) (4 << 4)                                     /* TIMx master mode - compare OC1 */
-#define TIMx_CR2_MMS_CMP_OC2            (uint32_t) (5 << 4)                                     /* TIMx master mode - compare OC2 */
-#define TIMx_CR2_MMS_CMP_OC3            (uint32_t) (6 << 4)                                     /* TIMx master mode - compare OC3 */
-#define TIMx_CR2_MMS_CMP_OC4            (uint32_t) (7 << 4)                                     /* TIMx master mode - compare OC4 */
-#define TIMx_CR2_TI1_123                (uint32_t) (1 << 7)                                     /* TIMx CH1, CH2, CH3 pins connected to TI1 */
-
-#define TIMx_DIER_UIE                   (uint32_t) (1 << 0)                                     /* TIMx update interrupt enable */
-#define TIMx_DIER_CC1IE                 (uint32_t) (1 << 1)                                     /* TIMx CC1 interrupt enable */
-#define TIMx_DIER_CC2IE                 (uint32_t) (1 << 2)                                     /* TIMx CC2 interrupt enable */
-#define TIMx_DIER_CC3IE                 (uint32_t) (1 << 3)                                     /* TIMx CC3 interrupt enable */
-#define TIMx_DIER_CC4IE                 (uint32_t) (1 << 4)                                     /* TIMx CC4 interrupt enable */
-#define TIMx_DIER_TIE                   (uint32_t) (1 << 6)                                     /* TIMx trigger interrupt enable */
-#define TIMx_DIER_UDE                   (uint32_t) (1 << 8)                                     /* TIMx update DMA request enable */
-#define TIMx_DIER_CC1DE                 (uint32_t) (1 << 9)                                     /* TIMx CC1 DMA request enable */
-#define TIMx_DIER_CC2DE                 (uint32_t) (1 << 10)                                    /* TIMx CC2 DMA request enable */
-#define TIMx_DIER_CC3DE                 (uint32_t) (1 << 11)                                    /* TIMx CC3 DMA request enable */
-#define TIMx_DIER_CC4DE                 (uint32_t) (1 << 12)                                    /* TIMx CC4 DMA request enable */
-#define TIMx_DIER_TDE                   (uint32_t) (1 << 14)                                    /* TIMx trigger DMA request enable */
+#define TIMx_CR1_CEN (uint32_t) (1 << 0)      /* TIMx counter enable */
+#define TIMx_CR1_UDIS (uint32_t) (1 << 1)     /* TIMx update disable */
+#define TIMx_CR1_URS (uint32_t) (1 << 2)      /* TIMx update request source */
+#define TIMx_CR1_OPM (uint32_t) (1 << 3)      /* TIMx one-pulse mode */
+#define TIMx_CR1_DIR_DOWN (uint32_t) (1 << 4) /* TIMx downcounter */
+#define TIMx_CR1_CMS_EDGE                                                     \
+    (uint32_t) (0 << 5) /* TIMx center-aligned mode selection - counter up or \
+                           down depending on DIR bit */
+#define TIMx_CR1_CMS_CM1                                                     \
+    (uint32_t) (1 << 5) /* TIMx center-aligned mode selection - up and down, \
+                           compare flags set down */
+#define TIMx_CR1_CMS_CM2                                                     \
+    (uint32_t) (2 << 5) /* TIMx center-aligned mode selection - up and down, \
+                           compare flags set up */
+#define TIMx_CR1_CMS_CM3                                                     \
+    (uint32_t) (3 << 5) /* TIMx center-aligned mode selection - up and down, \
+                           compare flags set up/down */
+#define TIMx_CR1_ARPE                                                         \
+    (uint32_t) (1 << 7)                    /* TIMx auto-reload preload enable \
+                                            */
+#define TIMx_CR1_CKD_1 (uint32_t) (0 << 8) /* TIMx clock division 1 */
+#define TIMx_CR1_CKD_2 (uint32_t) (1 << 8) /* TIMx clock division 2 */
+#define TIMx_CR1_CKD_4 (uint32_t) (2 << 8) /* TIMx clock division 4 */
+
+#define TIMx_CR2_CCDS                                                         \
+    (uint32_t) (1 << 3) /* TIMx capture/compare DMA requests send when update \
+                           event occurs */
+#define TIMx_CR2_MMS_RST (uint32_t) (0 << 4) /* TIMx master mode - reset */
+#define TIMx_CR2_MMS_EN (uint32_t) (1 << 4)  /* TIMx master mode - enable */
+#define TIMx_CR2_MMS_UP (uint32_t) (2 << 4)  /* TIMx master mode - update */
+#define TIMx_CR2_MMS_CMP_PUL \
+    (uint32_t) (3 << 4) /* TIMx master mode - compare pulse */
+#define TIMx_CR2_MMS_CMP_OC1 \
+    (uint32_t) (4 << 4) /* TIMx master mode - compare OC1 */
+#define TIMx_CR2_MMS_CMP_OC2 \
+    (uint32_t) (5 << 4) /* TIMx master mode - compare OC2 */
+#define TIMx_CR2_MMS_CMP_OC3 \
+    (uint32_t) (6 << 4) /* TIMx master mode - compare OC3 */
+#define TIMx_CR2_MMS_CMP_OC4 \
+    (uint32_t) (7 << 4) /* TIMx master mode - compare OC4 */
+#define TIMx_CR2_TI1_123 \
+    (uint32_t) (1 << 7) /* TIMx CH1, CH2, CH3 pins connected to TI1 */
+
+#define TIMx_DIER_UIE (uint32_t) (1 << 0)   /* TIMx update interrupt enable */
+#define TIMx_DIER_CC1IE (uint32_t) (1 << 1) /* TIMx CC1 interrupt enable */
+#define TIMx_DIER_CC2IE (uint32_t) (1 << 2) /* TIMx CC2 interrupt enable */
+#define TIMx_DIER_CC3IE (uint32_t) (1 << 3) /* TIMx CC3 interrupt enable */
+#define TIMx_DIER_CC4IE (uint32_t) (1 << 4) /* TIMx CC4 interrupt enable */
+#define TIMx_DIER_TIE (uint32_t) (1 << 6)   /* TIMx trigger interrupt enable */
+#define TIMx_DIER_UDE (uint32_t) (1 << 8)   /* TIMx update DMA request enable */
+#define TIMx_DIER_CC1DE (uint32_t) (1 << 9) /* TIMx CC1 DMA request enable */
+#define TIMx_DIER_CC2DE (uint32_t) (1 << 10) /* TIMx CC2 DMA request enable */
+#define TIMx_DIER_CC3DE (uint32_t) (1 << 11) /* TIMx CC3 DMA request enable */
+#define TIMx_DIER_CC4DE (uint32_t) (1 << 12) /* TIMx CC4 DMA request enable */
+#define TIMx_DIER_TDE                                       \
+    (uint32_t) (1 << 14) /* TIMx trigger DMA request enable \
+                          */
 
 /* SPI */
-#define SPI_CR1_CPHA                    (uint32_t) (1 << 0)                                     /* SPI clock phase */
-#define SPI_CR1_CPOL                    (uint32_t) (1 << 1)                                     /* SPI clock polarity */
-#define SPI_CR1_MSTR                    (uint32_t) (1 << 2)                                     /* SPI master selection */
-#define SPI_CR1_BR_2                    (uint32_t) (0 << 3)                                     /* SPI baud rate = fPCLK/2 */
-#define SPI_CR1_BR_4                    (uint32_t) (1 << 3)                                     /* SPI baud rate = fPCLK/4 */
-#define SPI_CR1_BR_8                    (uint32_t) (2 << 3)                                     /* SPI baud rate = fPCLK/8 */
-#define SPI_CR1_BR_16                   (uint32_t) (3 << 3)                                     /* SPI baud rate = fPCLK/16 */
-#define SPI_CR1_BR_32                   (uint32_t) (4 << 3)                                     /* SPI baud rate = fPCLK/32 */
-#define SPI_CR1_BR_64                   (uint32_t) (5 << 3)                                     /* SPI baud rate = fPCLK/64 */
-#define SPI_CR1_BR_128                  (uint32_t) (6 << 3)                                     /* SPI baud rate = fPCLK/128 */
-#define SPI_CR1_BR_256                  (uint32_t) (7 << 3)                                     /* SPI baud rate = fPCLK/256 */
-#define SPI_CR1_SPE                     (uint32_t) (1 << 6)                                     /* SPI enable */
-#define SPI_CR1_LSBFIRST                (uint32_t) (1 << 7)                                     /* SPI LSB transmitted first */
-#define SPI_CR1_SSI                     (uint32_t) (1 << 8)                                     /* SPI internal slave select */
-#define SPI_CR1_SSM                     (uint32_t) (1 << 9)                                     /* SPI software slave management */
-#define SPI_CR1_DFF                     (uint32_t) (1 << 11)                                    /* SPI data frame format (0 = 8bit, 1 = 16bit) */
-#define SPI_SR_RXNE                     (uint32_t) (1 << 0)                                     /* SPI receive not empty */
-#define SPI_SR_TXNE                     (uint32_t) (1 << 1)                                     /* SPI transmit not empty */
-#define SPI_SR_CHSIDE                   (uint32_t) (1 << 2)                                     /* SPI channel side */
-#define SPI_SR_UDR                      (uint32_t) (1 << 3)                                     /* SPI underrun flag */
-#define SPI_SR_CRCERR                   (uint32_t) (1 << 4)                                     /* SPI CRC error flag */
-#define SPI_SR_MODF                     (uint32_t) (1 << 5)                                     /* SPI mode fault */
-#define SPI_SR_OVR                      (uint32_t) (1 << 6)                                     /* SPI overrun flag */
-#define SPI_SR_BSY                      (uint32_t) (1 << 7)                                     /* SPI busy flag */
-#define SPI_SR_TIRFE                    (uint32_t) (1 << 8)                                     /* SPI TI frame format error */
+#define SPI_CR1_CPHA (uint32_t) (1 << 0)     /* SPI clock phase */
+#define SPI_CR1_CPOL (uint32_t) (1 << 1)     /* SPI clock polarity */
+#define SPI_CR1_MSTR (uint32_t) (1 << 2)     /* SPI master selection */
+#define SPI_CR1_BR_2 (uint32_t) (0 << 3)     /* SPI baud rate = fPCLK/2 */
+#define SPI_CR1_BR_4 (uint32_t) (1 << 3)     /* SPI baud rate = fPCLK/4 */
+#define SPI_CR1_BR_8 (uint32_t) (2 << 3)     /* SPI baud rate = fPCLK/8 */
+#define SPI_CR1_BR_16 (uint32_t) (3 << 3)    /* SPI baud rate = fPCLK/16 */
+#define SPI_CR1_BR_32 (uint32_t) (4 << 3)    /* SPI baud rate = fPCLK/32 */
+#define SPI_CR1_BR_64 (uint32_t) (5 << 3)    /* SPI baud rate = fPCLK/64 */
+#define SPI_CR1_BR_128 (uint32_t) (6 << 3)   /* SPI baud rate = fPCLK/128 */
+#define SPI_CR1_BR_256 (uint32_t) (7 << 3)   /* SPI baud rate = fPCLK/256 */
+#define SPI_CR1_SPE (uint32_t) (1 << 6)      /* SPI enable */
+#define SPI_CR1_LSBFIRST (uint32_t) (1 << 7) /* SPI LSB transmitted first */
+#define SPI_CR1_SSI (uint32_t) (1 << 8)      /* SPI internal slave select */
+#define SPI_CR1_SSM (uint32_t) (1 << 9)      /* SPI software slave management */
+#define SPI_CR1_DFF \
+    (uint32_t) (1 << 11) /* SPI data frame format (0 = 8bit, 1 = 16bit) */
+#define SPI_SR_RXNE (uint32_t) (1 << 0)   /* SPI receive not empty */
+#define SPI_SR_TXNE (uint32_t) (1 << 1)   /* SPI transmit not empty */
+#define SPI_SR_CHSIDE (uint32_t) (1 << 2) /* SPI channel side */
+#define SPI_SR_UDR (uint32_t) (1 << 3)    /* SPI underrun flag */
+#define SPI_SR_CRCERR (uint32_t) (1 << 4) /* SPI CRC error flag */
+#define SPI_SR_MODF (uint32_t) (1 << 5)   /* SPI mode fault */
+#define SPI_SR_OVR (uint32_t) (1 << 6)    /* SPI overrun flag */
+#define SPI_SR_BSY (uint32_t) (1 << 7)    /* SPI busy flag */
+#define SPI_SR_TIRFE (uint32_t) (1 << 8)  /* SPI TI frame format error */
 
 /* I2C */
-#define I2C_CR1_PE                      (uint32_t) (1 << 0)                                     /* I2C peripheral enable */
-#define I2C_CR1_SMBUS                   (uint32_t) (1 << 1)                                     /* I2C SMBus mode */
-#define I2C_CR1_SMBTYPE                 (uint32_t) (1 << 3)                                     /* I2C SMBus type (0=Device, 1=Host) */
-#define I2C_CR1_ENARP                   (uint32_t) (1 << 4)                                     /* I2C enable ARP */
-#define I2C_CR1_ENPEC                   (uint32_t) (1 << 5)                                     /* I2C enable PEC */
-#define I2C_CR1_ENGC                    (uint32_t) (1 << 6)                                     /* I2C enable general call */
-#define I2C_CR1_NOSTRETCH               (uint32_t) (1 << 7)                                     /* I2C clock stretching disable */
-#define I2C_CR1_START                   (uint32_t) (1 << 8)                                     /* I2C START generation */
-#define I2C_CR1_STOP                    (uint32_t) (1 << 9)                                     /* I2C STOP generation */
-#define I2C_CR1_ACK                     (uint32_t) (1 << 10)                                    /* I2C ACK enable */
-#define I2C_CR1_POS                     (uint32_t) (1 << 11)                                    /* I2C ACK/PEC position */
-#define I2C_CR1_PEC                     (uint32_t) (1 << 12)                                    /* I2C packet error checking */
-#define I2C_CR1_ALERT                   (uint32_t) (1 << 13)                                    /* I2C SMBus alert */
-#define I2C_CR1_SWRST                   (uint32_t) (1 << 15)                                    /* I2C software reset */
-
-#define I2C_CR2_FREQ(n)                 (uint32_t) (n << 0)                                     /* I2C clock frequency */
-#define I2C_CR2_ITERREN                 (uint32_t) (1 << 8)                                     /* I2C error interrupt enable */
-#define I2C_CR2_ITEVTEN                 (uint32_t) (1 << 9)                                     /* I2C event interrupt enable */
-#define I2C_CR2_ITBUFEN                 (uint32_t) (1 << 10)                                    /* I2C buffer interrupt enable */
-#define I2C_CR2_DMAEN                   (uint32_t) (1 << 11)                                    /* I2C DMA requests enable */
-#define I2C_CR2_LAST                    (uint32_t) (1 << 12)                                    /* I2C DMA last transfer */
-
-#define I2C_OAR1_ADD10(n)               (uint32_t) (n << 0)                                     /* I2C interface address (10-bit) */
-#define I2C_OAR1_ADD7(n)                (uint32_t) (n << 1)                                     /* I2C interface address (7-bit) */
-#define I2C_OAR1_ADDMODE                (uint32_t) (1 << 15)                                    /* I2C interface address mode (1=10-bit) */
-
-#define I2C_OAR2_ENDUAL                 (uint32_t) (1 << 0)                                     /* I2C dual address mode enable */
-#define I2C_OAR2_ADD2(n)                (uint32_t) (n << 1)                                     /* I2C interface address 2 (7-bit) */
-
-#define I2C_SR1_SB                      (uint32_t) (1 << 0)                                     /* I2C start bit generated */
-#define I2C_SR1_ADDR                    (uint32_t) (1 << 1)                                     /* I2C address sent/matched */
-#define I2C_SR1_BTF                     (uint32_t) (1 << 2)                                     /* I2C byte transfer finished */
-#define I2C_SR1_ADD10                   (uint32_t) (1 << 3)                                     /* I2C 10-bit header sent */
-#define I2C_SR1_STOPF                   (uint32_t) (1 << 4)                                     /* I2C stop detection */
-#define I2C_SR1_RXNE                    (uint32_t) (1 << 6)                                     /* I2C DR not empty */
-#define I2C_SR1_TXE                     (uint32_t) (1 << 7)                                     /* I2C DR empty */
-#define I2C_SR1_BERR                    (uint32_t) (1 << 8)                                     /* I2C bus error */
-#define I2C_SR1_ARLO                    (uint32_t) (1 << 9)                                     /* I2C attribution lost */
-#define I2C_SR1_AF                      (uint32_t) (1 << 10)                                    /* I2C acknowledge failure */
-#define I2C_SR1_OVR                     (uint32_t) (1 << 11)                                    /* I2C overrun/underrun */
-#define I2C_SR1_PECERR                  (uint32_t) (1 << 12)                                    /* I2C PEC error in reception */
-#define I2C_SR1_TIMEOUT                 (uint32_t) (1 << 14)                                    /* I2C timeout or tlow error */
-#define I2C_SR1_SMBALERT                (uint32_t) (1 << 15)                                    /* I2C SMBus alert */
-
-#define I2C_SR2_MSL                     (uint32_t) (1 << 0)                                     /* I2C master/slave */
-#define I2C_SR2_BUSY                    (uint32_t) (1 << 1)                                     /* I2C bus busy */
-#define I2C_SR2_TRA                     (uint32_t) (1 << 2)                                     /* I2C transmitter/receiver */
-#define I2C_SR2_GENCALL                 (uint32_t) (1 << 4)                                     /* I2C general call address */
-#define I2C_SR2_SMBDEFAULT              (uint32_t) (1 << 5)                                     /* I2C SMBus device default address */
-#define I2C_SR2_SMBHOST                 (uint32_t) (1 << 6)                                     /* I2C SMBus host header */
-#define I2C_SR2_DUALF                   (uint32_t) (1 << 7)                                     /* I2C dual flag */
-#define I2C_SR2_PEC(r)                  (uint32_t) (r >> 8)                                     /* I2C packet error checking register */
-
-#define I2C_CCR_CCR(n)                  (uint32_t) (n & 0x0FFF)                                 /* I2C clock control register */
-#define I2C_CCR_DUTY                    (uint32_t) (1 << 14)                                    /* I2C fast mode duty cycle */
-#define I2C_CCR_FS                      (uint32_t) (1 << 15)                                    /* I2C master mode selection */
+#define I2C_CR1_PE (uint32_t) (1 << 0)    /* I2C peripheral enable */
+#define I2C_CR1_SMBUS (uint32_t) (1 << 1) /* I2C SMBus mode */
+#define I2C_CR1_SMBTYPE \
+    (uint32_t) (1 << 3) /* I2C SMBus type (0=Device, 1=Host) */
+#define I2C_CR1_ENARP (uint32_t) (1 << 4) /* I2C enable ARP */
+#define I2C_CR1_ENPEC (uint32_t) (1 << 5) /* I2C enable PEC */
+#define I2C_CR1_ENGC (uint32_t) (1 << 6)  /* I2C enable general call */
+#define I2C_CR1_NOSTRETCH                                                  \
+    (uint32_t) (1 << 7)                    /* I2C clock stretching disable \
+                                            */
+#define I2C_CR1_START (uint32_t) (1 << 8)  /* I2C START generation */
+#define I2C_CR1_STOP (uint32_t) (1 << 9)   /* I2C STOP generation */
+#define I2C_CR1_ACK (uint32_t) (1 << 10)   /* I2C ACK enable */
+#define I2C_CR1_POS (uint32_t) (1 << 11)   /* I2C ACK/PEC position */
+#define I2C_CR1_PEC (uint32_t) (1 << 12)   /* I2C packet error checking */
+#define I2C_CR1_ALERT (uint32_t) (1 << 13) /* I2C SMBus alert */
+#define I2C_CR1_SWRST (uint32_t) (1 << 15) /* I2C software reset */
+
+#define I2C_CR2_FREQ(n) (uint32_t) (n << 0)  /* I2C clock frequency */
+#define I2C_CR2_ITERREN (uint32_t) (1 << 8)  /* I2C error interrupt enable */
+#define I2C_CR2_ITEVTEN (uint32_t) (1 << 9)  /* I2C event interrupt enable */
+#define I2C_CR2_ITBUFEN (uint32_t) (1 << 10) /* I2C buffer interrupt enable */
+#define I2C_CR2_DMAEN (uint32_t) (1 << 11)   /* I2C DMA requests enable */
+#define I2C_CR2_LAST (uint32_t) (1 << 12)    /* I2C DMA last transfer */
+
+#define I2C_OAR1_ADD10(n) \
+    (uint32_t) (n << 0) /* I2C interface address (10-bit) */
+#define I2C_OAR1_ADD7(n)                                 \
+    (uint32_t) (n << 1) /* I2C interface address (7-bit) \
+                         */
+#define I2C_OAR1_ADDMODE \
+    (uint32_t) (1 << 15) /* I2C interface address mode (1=10-bit) */
+
+#define I2C_OAR2_ENDUAL (uint32_t) (1 << 0) /* I2C dual address mode enable */
+#define I2C_OAR2_ADD2(n) \
+    (uint32_t) (n << 1) /* I2C interface address 2 (7-bit) */
+
+#define I2C_SR1_SB (uint32_t) (1 << 0)        /* I2C start bit generated */
+#define I2C_SR1_ADDR (uint32_t) (1 << 1)      /* I2C address sent/matched */
+#define I2C_SR1_BTF (uint32_t) (1 << 2)       /* I2C byte transfer finished */
+#define I2C_SR1_ADD10 (uint32_t) (1 << 3)     /* I2C 10-bit header sent */
+#define I2C_SR1_STOPF (uint32_t) (1 << 4)     /* I2C stop detection */
+#define I2C_SR1_RXNE (uint32_t) (1 << 6)      /* I2C DR not empty */
+#define I2C_SR1_TXE (uint32_t) (1 << 7)       /* I2C DR empty */
+#define I2C_SR1_BERR (uint32_t) (1 << 8)      /* I2C bus error */
+#define I2C_SR1_ARLO (uint32_t) (1 << 9)      /* I2C attribution lost */
+#define I2C_SR1_AF (uint32_t) (1 << 10)       /* I2C acknowledge failure */
+#define I2C_SR1_OVR (uint32_t) (1 << 11)      /* I2C overrun/underrun */
+#define I2C_SR1_PECERR (uint32_t) (1 << 12)   /* I2C PEC error in reception */
+#define I2C_SR1_TIMEOUT (uint32_t) (1 << 14)  /* I2C timeout or tlow error */
+#define I2C_SR1_SMBALERT (uint32_t) (1 << 15) /* I2C SMBus alert */
+
+#define I2C_SR2_MSL (uint32_t) (1 << 0)     /* I2C master/slave */
+#define I2C_SR2_BUSY (uint32_t) (1 << 1)    /* I2C bus busy */
+#define I2C_SR2_TRA (uint32_t) (1 << 2)     /* I2C transmitter/receiver */
+#define I2C_SR2_GENCALL (uint32_t) (1 << 4) /* I2C general call address */
+#define I2C_SR2_SMBDEFAULT \
+    (uint32_t) (1 << 5) /* I2C SMBus device default address */
+#define I2C_SR2_SMBHOST (uint32_t) (1 << 6) /* I2C SMBus host header */
+#define I2C_SR2_DUALF (uint32_t) (1 << 7)   /* I2C dual flag */
+#define I2C_SR2_PEC(r) \
+    (uint32_t) (r >> 8) /* I2C packet error checking register */
+
+#define I2C_CCR_CCR(n)                                                  \
+    (uint32_t) (n & 0x0FFF)               /* I2C clock control register \
+                                           */
+#define I2C_CCR_DUTY (uint32_t) (1 << 14) /* I2C fast mode duty cycle */
+#define I2C_CCR_FS (uint32_t) (1 << 15)   /* I2C master mode selection */
 
 /* USART */
-#define USART_SR_TC                     (uint32_t) (1 << 6)                                     /* USART Transmission Complete */
-#define USART_SR_RXNE                   (uint32_t) (1 << 5)                                     /* USART Read data register not empty */
+#define USART_SR_TC (uint32_t) (1 << 6) /* USART Transmission Complete */
+#define USART_SR_RXNE \
+    (uint32_t) (1 << 5) /* USART Read data register not empty */
 
 /* USART_CR1 */
-#define USART_CR1_OVER8                 (uint32_t) (1 << 15)                                    /* Oversampling mode */
-#define USART_CR1_UE                    (uint32_t) (1 << 13)                                    /* USART Enable */
-#define USART_CR1_M9                    (uint32_t) (1 << 12)                                    /* World length 1: 9 bits, 0: 8bits */
-#define USART_CR1_WAKE                  (uint32_t) (1 << 11)                                    /* Wakeup method */
-#define USART_CR1_PCE                   (uint32_t) (1 << 10)                                    /* PCE Parity control enable */
-#define USART_CR1_PS                    (uint32_t) (1 << 9)                                     /* Parity selection */
-#define USART_CR1_PEIE                  (uint32_t) (1 << 8)                                     /* PE Interrupt enable */
-#define USART_CR1_TXEIE                 (uint32_t) (1 << 7)                                     /* TXE interrupt enable */
-#define USART_CR1_TCIE                  (uint32_t) (1 << 6)                                     /* Transmission complete interrupt enable */
-#define USART_CR1_RXNEIE                (uint32_t) (1 << 5)                                     /* RXNE Interrupt Enable */
-#define USART_CR1_IDLEIE                (uint32_t) (1 << 4)                                     /* IDEL INterrupt Enable */
-#define USART_CR1_TE                    (uint32_t) (1 << 3)                                     /* USART Transmit Enable */
-#define USART_CR1_RE                    (uint32_t) (1 << 2)                                     /* USART Receive Enable */
-#define USART_CR1_RWU                   (uint32_t) (1 << 1)
-#define USART_CR1_SBK                   (uint32_t) (1 << 0)                                     /* Send break characters */
-
-#define USART_CR3_DMAR_EN               (uint32_t) (1 << 6)                                     /* USART DMA Receive Enable */
-#define USART_CR3_DMAT_EN               (uint32_t) (1 << 7)                                     /* USART DMA Transmit Enable */
+#define USART_CR1_OVER8 (uint32_t) (1 << 15) /* Oversampling mode */
+#define USART_CR1_UE (uint32_t) (1 << 13)    /* USART Enable */
+#define USART_CR1_M9                                         \
+    (uint32_t) (1 << 12) /* World length 1: 9 bits, 0: 8bits \
+                          */
+#define USART_CR1_WAKE (uint32_t) (1 << 11) /* Wakeup method */
+#define USART_CR1_PCE (uint32_t) (1 << 10)  /* PCE Parity control enable */
+#define USART_CR1_PS (uint32_t) (1 << 9)    /* Parity selection */
+#define USART_CR1_PEIE (uint32_t) (1 << 8)  /* PE Interrupt enable */
+#define USART_CR1_TXEIE (uint32_t) (1 << 7) /* TXE interrupt enable */
+#define USART_CR1_TCIE \
+    (uint32_t) (1 << 6) /* Transmission complete interrupt enable */
+#define USART_CR1_RXNEIE (uint32_t) (1 << 5) /* RXNE Interrupt Enable */
+#define USART_CR1_IDLEIE (uint32_t) (1 << 4) /* IDEL INterrupt Enable */
+#define USART_CR1_TE (uint32_t) (1 << 3)     /* USART Transmit Enable */
+#define USART_CR1_RE (uint32_t) (1 << 2)     /* USART Receive Enable */
+#define USART_CR1_RWU (uint32_t) (1 << 1)
+#define USART_CR1_SBK (uint32_t) (1 << 0) /* Send break characters */
+
+#define USART_CR3_DMAR_EN (uint32_t) (1 << 6) /* USART DMA Receive Enable */
+#define USART_CR3_DMAT_EN (uint32_t) (1 << 7) /* USART DMA Transmit Enable */
 
 /* GPIO */
-#define GPIOA                           (uint8_t)  (0)                                          /* GPIO Port A */
-#define GPIOB                           (uint8_t)  (1)                                          /* GPIO Port B */
-#define GPIOC                           (uint8_t)  (2)                                          /* GPIO Port C */
-#define GPIOD                           (uint8_t)  (3)                                          /* GPIO Port D */
-#define GPIOE                           (uint8_t)  (4)                                          /* GPIO Port E */
-
-#define GPIO_CR_PIN(n)                  (uint32_t) (4*n)                                        /* Pin bitshift */
-#define GPIO_CR_M(n)                    (uint32_t) (0x3 << 4*n)                                 /* Pin mask */
-
-#define GPIO_OSPEED_10M                 (uint32_t) (0x1)                                        /* Output speed 10MHz */
-#define GPIO_OSPEED_2M                  (uint32_t) (0x2)                                        /* Output speed 2MHz */
-#define GPIO_OSPEED_50M                 (uint32_t) (0x3)                                        /* Output speed 50MHz */
-
-#define GPIO_MODE_IN_ANALOG             (uint32_t) (0x00)                                       /* Input analog mode */
-#define GPIO_MODE_IN_FLOAT              (uint32_t) (0x01)                                       /* Input floating point mode */
-#define GPIO_MODE_IN_PD                 (uint32_t) (0x0A)                                       /* Input push down mode */
-#define GPIO_MODE_IN_PU                 (uint32_t) (0x12)                                       /* Input pull up mode */
-#define GPIO_MODE_OUT_PP                (uint32_t) (0x04)                                       /* Output push-pull mode */
-#define GPIO_MODE_OUT_OD                (uint32_t) (0x05)                                       /* Output open-drain mode */
-#define GPIO_MODE_OUT_ALT_PP            (uint32_t) (0x06)                                       /* Output alternate function push-pull mode */
-#define GPIO_MODE_OUT_ALT_OD            (uint32_t) (0x07)                                       /* Output alternate function open-drain mode */
-
-#define GPIO_IDR_PIN(n)                 (uint32_t) (1 << n)                                     /* Input for pin n */
-
-#define GPIO_ODR_PIN(n)                 (uint32_t) (1 << n)                                     /* Output for pin n */
-
-#define GPIO_BSRR_BS(n)                 (uint32_t) (1 << n)                                     /* Set pin n */
-#define GPIO_BSRR_BR(n)                 (uint32_t) (1 << (n+16))                                /* Reset pin n */
-#define GPIO_BRR_BR(n)                  (uint16_t) (1 << n)                                     /* Reset pin n */
-#define GPIO_LCKR_LCK(n)                (uint32_t) (1 << n)                                     /* Lock pin n */
+#define GPIOA (uint8_t) (0) /* GPIO Port A */
+#define GPIOB (uint8_t) (1) /* GPIO Port B */
+#define GPIOC (uint8_t) (2) /* GPIO Port C */
+#define GPIOD (uint8_t) (3) /* GPIO Port D */
+#define GPIOE (uint8_t) (4) /* GPIO Port E */
+
+#define GPIO_CR_PIN(n) (uint32_t) (4 * n)      /* Pin bitshift */
+#define GPIO_CR_M(n) (uint32_t) (0x3 << 4 * n) /* Pin mask */
+
+#define GPIO_OSPEED_10M (uint32_t) (0x1) /* Output speed 10MHz */
+#define GPIO_OSPEED_2M (uint32_t) (0x2)  /* Output speed 2MHz */
+#define GPIO_OSPEED_50M (uint32_t) (0x3) /* Output speed 50MHz */
+
+#define GPIO_MODE_IN_ANALOG (uint32_t) (0x00) /* Input analog mode */
+#define GPIO_MODE_IN_FLOAT (uint32_t) (0x01)  /* Input floating point mode */
+#define GPIO_MODE_IN_PD (uint32_t) (0x0A)     /* Input push down mode */
+#define GPIO_MODE_IN_PU (uint32_t) (0x12)     /* Input pull up mode */
+#define GPIO_MODE_OUT_PP (uint32_t) (0x04)    /* Output push-pull mode */
+#define GPIO_MODE_OUT_OD (uint32_t) (0x05)    /* Output open-drain mode */
+#define GPIO_MODE_OUT_ALT_PP \
+    (uint32_t) (0x06) /* Output alternate function push-pull mode */
+#define GPIO_MODE_OUT_ALT_OD \
+    (uint32_t) (0x07) /* Output alternate function open-drain mode */
+
+#define GPIO_IDR_PIN(n) (uint32_t) (1 << n) /* Input for pin n */
+
+#define GPIO_ODR_PIN(n) (uint32_t) (1 << n) /* Output for pin n */
+
+#define GPIO_BSRR_BS(n) (uint32_t) (1 << n)        /* Set pin n */
+#define GPIO_BSRR_BR(n) (uint32_t) (1 << (n + 16)) /* Reset pin n */
+#define GPIO_BRR_BR(n) (uint16_t) (1 << n)         /* Reset pin n */
+#define GPIO_LCKR_LCK(n) (uint32_t) (1 << n)       /* Lock pin n */
 
 /* DMA */
-#define DMA_ISR_GIF(n)                  (uint32_t) (0x1 << ((n-1)*4))                           /* DMA Channel n Global interrupt flag */
-#define DMA_ISR_TCIF(n)                 (uint32_t) (0x2 << ((n-1)*4))                           /* DMA Channel n Transfer Complete flag */
-#define DMA_ISR_HTIF(n)                 (uint32_t) (0x4 << ((n-1)*4))                           /* DMA Channel n Half Transfer flag */
-#define DMA_ISR_TEIF(n)                 (uint32_t) (0x8 << ((n-1)*4))                           /* DMA Channel n Transfer Error flag */
-
-#define DMA_IFCR_CGIF(n)                (uint32_t) (0x1 << ((n-1)*4))                           /* DMA Channel n Global interrupt clear */
-#define DMA_IFCR_CTCIF(n)               (uint32_t) (0x2 << ((n-1)*4))                           /* DMA Channel n Transfer Complete clear */
-#define DMA_IFCR_CHTIF(n)               (uint32_t) (0x4 << ((n-1)*4))                           /* DMA Channel n Half Transfer clear */
-#define DMA_IFCR_CTEIF(n)               (uint32_t) (0x8 << ((n-1)*4))                           /* DMA Channel n Transfer Error clear */
-
-#define DMA_CCR_EN                      (uint16_t) (1 << 0)                                     /* DMA Channel enable */
-#define DMA_CCR_TCIE                    (uint16_t) (1 << 1)                                     /* DMA Channel transfer complete interrupt enable */
-#define DMA_CCR_HTIE                    (uint16_t) (1 << 2)                                     /* DMA Channel half transfer interrupt enable */
-#define DMA_CCR_TEIE                    (uint16_t) (1 << 3)                                     /* DMA Channel transfer error interrupt error enable */
-#define DMA_CCR_DIR                     (uint16_t) (1 << 4)                                     /* DMA Channel data transfer direction */
-#define DMA_CCR_CIRC                    (uint16_t) (1 << 5)                                     /* DMA Channel circular mode */
-#define DMA_CCR_PINC                    (uint16_t) (1 << 6)                                     /* DMA Channel peripheral increment mode */
-#define DMA_CCR_MINC                    (uint16_t) (1 << 7)                                     /* DMA Channel Memory increment mode */
-#define DMA_CCR_PL                      (uint16_t) (3 << 12)                                    /* DMA Channel Priority level mask */
-#define DMA_CCR_MEM2MEM                 (uint16_t) (1 << 14)                                    /* DMA Channel Memory to memory mode */
+#define DMA_ISR_GIF(n)                                                       \
+    (uint32_t) (0x1 << ((n - 1) * 4)) /* DMA Channel n Global interrupt flag \
+                                       */
+#define DMA_ISR_TCIF(n)                                                       \
+    (uint32_t) (0x2 << ((n - 1) * 4)) /* DMA Channel n Transfer Complete flag \
+                                       */
+#define DMA_ISR_HTIF(n) \
+    (uint32_t) (0x4 << ((n - 1) * 4)) /* DMA Channel n Half Transfer flag */
+#define DMA_ISR_TEIF(n) \
+    (uint32_t) (0x8 << ((n - 1) * 4)) /* DMA Channel n Transfer Error flag */
+
+#define DMA_IFCR_CGIF(n)                                                      \
+    (uint32_t) (0x1 << ((n - 1) * 4)) /* DMA Channel n Global interrupt clear \
+                                       */
+#define DMA_IFCR_CTCIF(n)         \
+    (uint32_t) (0x2 << ((n - 1) * \
+                        4)) /* DMA Channel n Transfer Complete clear */
+#define DMA_IFCR_CHTIF(n) \
+    (uint32_t) (0x4 << ((n - 1) * 4)) /* DMA Channel n Half Transfer clear */
+#define DMA_IFCR_CTEIF(n) \
+    (uint32_t) (0x8 << ((n - 1) * 4)) /* DMA Channel n Transfer Error clear */
+
+#define DMA_CCR_EN (uint16_t) (1 << 0) /* DMA Channel enable */
+#define DMA_CCR_TCIE \
+    (uint16_t) (1 << 1) /* DMA Channel transfer complete interrupt enable */
+#define DMA_CCR_HTIE \
+    (uint16_t) (1 << 2) /* DMA Channel half transfer interrupt enable */
+#define DMA_CCR_TEIE                                                         \
+    (uint16_t) (1 << 3) /* DMA Channel transfer error interrupt error enable \
+                         */
+#define DMA_CCR_DIR \
+    (uint16_t) (1 << 4) /* DMA Channel data transfer direction */
+#define DMA_CCR_CIRC (uint16_t) (1 << 5) /* DMA Channel circular mode */
+#define DMA_CCR_PINC \
+    (uint16_t) (1 << 6) /* DMA Channel peripheral increment mode */
+#define DMA_CCR_MINC                                                         \
+    (uint16_t) (1 << 7)                 /* DMA Channel Memory increment mode \
+                                         */
+#define DMA_CCR_PL (uint16_t) (3 << 12) /* DMA Channel Priority level mask */
+#define DMA_CCR_MEM2MEM \
+    (uint16_t) (1 << 14) /* DMA Channel Memory to memory mode */
 
 #endif
diff --git a/include/platform/stm32f1/syscfg.h b/include/platform/stm32f1/syscfg.h
index 89da8dd8..fc3c5375 100644
--- a/include/platform/stm32f1/syscfg.h
+++ b/include/platform/stm32f1/syscfg.h
@@ -1,7 +1,7 @@
 /* Copyright (c) 2014 The F9 Microkernel Project. All rights reserved.
-* Use of this source code is governed by a BSD-style license that can be
-* found in the LICENSE file.
-*/
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
 
 #ifndef PLATFORM_STM32F10_SYSCFG_H_
 #define PLATFORM_STM32F10_SYSCFG_H_
diff --git a/include/platform/stm32f1/systick.h b/include/platform/stm32f1/systick.h
index 6351e530..f1f15f2c 100644
--- a/include/platform/stm32f1/systick.h
+++ b/include/platform/stm32f1/systick.h
@@ -3,8 +3,8 @@
 
 #include <platform/stm32f1/registers.h>
 
-#define CORE_CLOCK		(0x044aa200) /* 72MHz */
-#define SYSTICK_MAXRELOAD	(0x00ffffff)
+#define CORE_CLOCK (0x044aa200) /* 72MHz */
+#define SYSTICK_MAXRELOAD (0x00ffffff)
 
 void init_systick(uint32_t tick_reload, uint32_t tick_next_reload);
 void systick_disable(void);
diff --git a/include/platform/stm32f1/usart.h b/include/platform/stm32f1/usart.h
index 1abaef72..e5e5dbfd 100644
--- a/include/platform/stm32f1/usart.h
+++ b/include/platform/stm32f1/usart.h
@@ -6,55 +6,57 @@
 #ifndef PLATFORM_STM32F1_USART_H_
 #define PLATFORM_STM32F1_USART_H_
 
-#include <platform/stm32f1/registers.h>
 #include <platform/stm32f1/gpio.h>
+#include <platform/stm32f1/registers.h>
 
 struct usart_dev {
-	uint32_t u_num;
-	uint32_t baud;
-	uint32_t base;
-	volatile uint32_t *rcc_apbenr;
-	uint32_t rcc_reset;
-	struct gpio_cfg tx;
-	struct gpio_cfg rx;
+    uint32_t u_num;
+    uint32_t baud;
+    uint32_t base;
+    volatile uint32_t *rcc_apbenr;
+    uint32_t rcc_reset;
+    struct gpio_cfg tx;
+    struct gpio_cfg rx;
 };
 
 #define USART_NUM 3
 
 /* status bit */
-#define USART_CTS	((uint16_t) (0x1 << 9))
-#define USART_LBD	((uint16_t) (0x1 << 8))
-#define USART_TXE	((uint16_t) (0x1 << 7))
-#define USART_TC	((uint16_t) (0x1 << 6))
-#define USART_RXNE	((uint16_t) (0x1 << 5))
-#define USART_IDLE	((uint16_t) (0x1 << 4))
-#define USART_ORE	((uint16_t) (0x1 << 3))
-#define USART_NF	((uint16_t) (0x1 << 2))
-#define USART_FE	((uint16_t) (0x1 << 1))
-#define USART_PE	((uint16_t) (0x1 << 0))
-
-
-#define USART_IT_CR1	(0xc << 8)
-#define USART_IT_CR2	(0x10 << 8)
-#define USART_IT_CR3	(0x14 << 8)
-
-#define USART_IT_PE	((uint16_t) USART_IT_CR1 | 0x8)
-#define USART_IT_TXE	((uint16_t) USART_IT_CR1 | 0x7)
-#define USART_IT_TC	((uint16_t) USART_IT_CR1 | 0x6)
-#define USART_IT_RXNE	((uint16_t) USART_IT_CR1 | 0x5)
-#define USART_IT_IDLE	((uint16_t) USART_IT_CR1 | 0x4)
-#define USART_IT_LBD	((uint16_t) USART_IT_CR2 | 0x6)
-#define USART_IT_CTS	((uint16_t) USART_IT_CR3 | 0xa)
-#define USART_IT_ERR	((uint16_t) USART_IT_CR3 | 0x0)
-
-#define USART_IT_ENB_REG_OFFSET(USART_IT)	((USART_IT >> 8) & 0xff)
-#define USART_IT_POSITION(USART_IT)		(USART_IT & 0xff)
+#define USART_CTS ((uint16_t) (0x1 << 9))
+#define USART_LBD ((uint16_t) (0x1 << 8))
+#define USART_TXE ((uint16_t) (0x1 << 7))
+#define USART_TC ((uint16_t) (0x1 << 6))
+#define USART_RXNE ((uint16_t) (0x1 << 5))
+#define USART_IDLE ((uint16_t) (0x1 << 4))
+#define USART_ORE ((uint16_t) (0x1 << 3))
+#define USART_NF ((uint16_t) (0x1 << 2))
+#define USART_FE ((uint16_t) (0x1 << 1))
+#define USART_PE ((uint16_t) (0x1 << 0))
+
+
+#define USART_IT_CR1 (0xc << 8)
+#define USART_IT_CR2 (0x10 << 8)
+#define USART_IT_CR3 (0x14 << 8)
+
+#define USART_IT_PE ((uint16_t) USART_IT_CR1 | 0x8)
+#define USART_IT_TXE ((uint16_t) USART_IT_CR1 | 0x7)
+#define USART_IT_TC ((uint16_t) USART_IT_CR1 | 0x6)
+#define USART_IT_RXNE ((uint16_t) USART_IT_CR1 | 0x5)
+#define USART_IT_IDLE ((uint16_t) USART_IT_CR1 | 0x4)
+#define USART_IT_LBD ((uint16_t) USART_IT_CR2 | 0x6)
+#define USART_IT_CTS ((uint16_t) USART_IT_CR3 | 0xa)
+#define USART_IT_ERR ((uint16_t) USART_IT_CR3 | 0x0)
+
+#define USART_IT_ENB_REG_OFFSET(USART_IT) ((USART_IT >> 8) & 0xff)
+#define USART_IT_POSITION(USART_IT) (USART_IT & 0xff)
 
 void usart_init(struct usart_dev *usart);
 void usart_putc(struct usart_dev *usart, uint8_t c);
 uint8_t usart_getc(struct usart_dev *usart);
 int usart_status(struct usart_dev *usart, uint16_t st);
 int usart_interrupt_status(struct usart_dev *usart, uint16_t it);
-void usart_config_interrupt(struct usart_dev *usart, uint16_t it, uint8_t state);
+void usart_config_interrupt(struct usart_dev *usart,
+                            uint16_t it,
+                            uint8_t state);
 
 #endif /* PLATFORM_STM32F1_USART_H_ */
diff --git a/include/platform/stm32f4/exti.h b/include/platform/stm32f4/exti.h
index 4d24628c..3f7e772b 100644
--- a/include/platform/stm32f4/exti.h
+++ b/include/platform/stm32f4/exti.h
@@ -1,27 +1,27 @@
 #ifndef PLATFORM_STM32F4_EXTI_H_
 #define PLATFORM_STM32F4_EXTI_H_
 
-#include <platform/stm32f4/registers.h>
 #include <platform/stm32f4/gpio.h>
+#include <platform/stm32f4/registers.h>
 
 /* EXTI mode */
-#define EXTI_INTERRUPT_MODE				0x0
-#define EXTI_EVENT_MODE					0x4
+#define EXTI_INTERRUPT_MODE 0x0
+#define EXTI_EVENT_MODE 0x4
 
 /* EXTI trigger type */
-#define EXTI_RISING_TRIGGER				0x8
-#define EXTI_FALLING_TRIGGER			0xc
-#define EXTI_RISING_FALLING_TRIGGER		0x10
+#define EXTI_RISING_TRIGGER 0x8
+#define EXTI_FALLING_TRIGGER 0xc
+#define EXTI_RISING_FALLING_TRIGGER 0x10
 
-#define EXTI_LINE(x)	((uint32_t)0x1 << x)
+#define EXTI_LINE(x) ((uint32_t) 0x1 << x)
 
 struct exti_regs {
-	volatile uint32_t IMR;
-	volatile uint32_t EMR;
-	volatile uint32_t RTSR;
-	volatile uint32_t FTSR;
-	volatile uint32_t SWIER;
-	volatile uint32_t PR;
+    volatile uint32_t IMR;
+    volatile uint32_t EMR;
+    volatile uint32_t RTSR;
+    volatile uint32_t FTSR;
+    volatile uint32_t SWIER;
+    volatile uint32_t PR;
 };
 
 
diff --git a/include/platform/stm32f4/gpio.h b/include/platform/stm32f4/gpio.h
index 67c3bf6e..3be2cefc 100644
--- a/include/platform/stm32f4/gpio.h
+++ b/include/platform/stm32f4/gpio.h
@@ -38,40 +38,40 @@ struct gpio_cfg {
 };
 
 /* GPIO Alternative Function */
-#define     af_system           AF0
-#define     af_tim1             AF1
-#define     af_tim2             AF1
-#define     af_tim3             AF2
-#define     af_tim4             AF2
-#define     af_tim5             AF2
-#define     af_tim8             AF3
-#define     af_tim9             AF3
-#define     af_tim10            AF3
-#define     af_tim11            AF3
-#define     af_i2c1             AF4
-#define     af_i2c2             AF4
-#define     af_i2c3             AF4
-#define     af_spi1             AF5
-#define     af_spi2             AF5
-#define     af_spi3             AF6
-#define     af_usart1           AF7
-#define     af_usart2           AF7
-#define     af_usart3		AF7
-#define     af_uart4		AF8
-#define     af_uart5		AF8
-#define     af_usart6           AF8
-#define     af_can1             AF9
-#define     af_can2             AF9
-#define     af_tim12            AF9
-#define     af_tim13            AF9
-#define     af_tim14            AF9
-#define     af_otg_fs           AF10
-#define     af_otg_hs           AF10
-#define     af_eth              AF11
-#define     af_fsmc             AF12
-#define     af_sdio             AF12
-#define     af_dcmi             AF13
-#define     af_eventout         AF15
+#define af_system AF0
+#define af_tim1 AF1
+#define af_tim2 AF1
+#define af_tim3 AF2
+#define af_tim4 AF2
+#define af_tim5 AF2
+#define af_tim8 AF3
+#define af_tim9 AF3
+#define af_tim10 AF3
+#define af_tim11 AF3
+#define af_i2c1 AF4
+#define af_i2c2 AF4
+#define af_i2c3 AF4
+#define af_spi1 AF5
+#define af_spi2 AF5
+#define af_spi3 AF6
+#define af_usart1 AF7
+#define af_usart2 AF7
+#define af_usart3 AF7
+#define af_uart4 AF8
+#define af_uart5 AF8
+#define af_usart6 AF8
+#define af_can1 AF9
+#define af_can2 AF9
+#define af_tim12 AF9
+#define af_tim13 AF9
+#define af_tim14 AF9
+#define af_otg_fs AF10
+#define af_otg_hs AF10
+#define af_eth AF11
+#define af_fsmc AF12
+#define af_sdio AF12
+#define af_dcmi AF13
+#define af_eventout AF15
 
 void gpio_config(struct gpio_cfg *cfg);
 void gpio_config_output(uint8_t port, uint8_t pin, uint8_t pupd, uint8_t speed);
diff --git a/include/platform/stm32f4/nvic.h b/include/platform/stm32f4/nvic.h
index d27acbc6..930a799e 100644
--- a/include/platform/stm32f4/nvic.h
+++ b/include/platform/stm32f4/nvic.h
@@ -6,267 +6,291 @@
 #ifndef __PLATFORM_STM32F4_NVIC_H__
 #define __PLATFORM_STM32F4_NVIC_H__
 
-#include <platform/stm32f4/registers.h>
 #include <platform/cortex_m.h>
+#include <platform/stm32f4/registers.h>
 
-#define IRQ_ENABLE	1
-#define IRQ_DISABLE	0
+#define IRQ_ENABLE 1
+#define IRQ_DISABLE 0
 
 typedef enum IRQn {
-	/* Cortex-M4 Processor Exceptions Numbers */
-	NonMaskableInt_IRQn	= -14,	/*!< 2 Non Maskable Interrupt */
-	MemoryManagement_IRQn	= -12,	/*!< 4 Cortex-M4 Memory Management Interrupt */
-	BusFault_IRQn		= -11,	/*!< 5 Cortex-M4 Bus Fault Interrupt */
-	UsageFault_IRQn		= -10,	/*!< 6 Cortex-M4 Usage Fault Interrupt */
-	SVCall_IRQn		= -5,	/*!< 11 Cortex-M4 SV Call Interrupt */
-	DebugMonitor_IRQn	= -4,	/*!< 12 Cortex-M4 Debug Monitor Interrupt */
-	PendSV_IRQn		= -2,	/*!< 14 Cortex-M4 Pend SV Interrupt */
-	SysTick_IRQn		= -1,	/*!< 15 Cortex-M4 System Tick Interrupt */
+    /* Cortex-M4 Processor Exceptions Numbers */
+    NonMaskableInt_IRQn = -14,   /*!< 2 Non Maskable Interrupt */
+    MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+    BusFault_IRQn = -11,         /*!< 5 Cortex-M4 Bus Fault Interrupt */
+    UsageFault_IRQn = -10,       /*!< 6 Cortex-M4 Usage Fault Interrupt */
+    SVCall_IRQn = -5,            /*!< 11 Cortex-M4 SV Call Interrupt */
+    DebugMonitor_IRQn = -4,      /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+    PendSV_IRQn = -2,            /*!< 14 Cortex-M4 Pend SV Interrupt */
+    SysTick_IRQn = -1,           /*!< 15 Cortex-M4 System Tick Interrupt */
 
-	/* STM32 specific Interrupt Numbers */
-	WWDG_IRQn		= 0,	/*!< Window WatchDog Interrupt */
-	PVD_IRQn		= 1,	/*!< PVD through EXTI Line detection Interrupt */
-	TAMP_STAMP_IRQn		= 2,	/*!< Tamper and TimeStamp interrupts through the EXTI line */
-	RTC_WKUP_IRQn		= 3,	/*!< RTC Wakeup interrupt through the EXTI line */
-	FLASH_IRQn		= 4,	/*!< FLASH global Interrupt */
-	RCC_IRQn		= 5,	/*!< RCC global Interrupt */
-	EXTI0_IRQn		= 6,	/*!< EXTI Line0 Interrupt */
-	EXTI1_IRQn		= 7,	/*!< EXTI Line1 Interrupt */
-	EXTI2_IRQn		= 8,	/*!< EXTI Line2 Interrupt */
-	EXTI3_IRQn		= 9,	/*!< EXTI Line3 Interrupt */
-	EXTI4_IRQn		= 10,	/*!< EXTI Line4 Interrupt */
-	DMA1_Stream0_IRQn	= 11,	/*!< DMA1 Stream 0 global Interrupt */
-	DMA1_Stream1_IRQn	= 12,	/*!< DMA1 Stream 1 global Interrupt */
-	DMA1_Stream2_IRQn	= 13,	/*!< DMA1 Stream 2 global Interrupt */
-	DMA1_Stream3_IRQn	= 14,	/*!< DMA1 Stream 3 global Interrupt */
-	DMA1_Stream4_IRQn	= 15,	/*!< DMA1 Stream 4 global Interrupt */
-	DMA1_Stream5_IRQn	= 16,	/*!< DMA1 Stream 5 global Interrupt */
-	DMA1_Stream6_IRQn	= 17,	/*!< DMA1 Stream 6 global Interrupt */
-	ADC_IRQn		= 18,	/*!< ADC1, ADC2 and ADC3 global Interrupts */
-	CAN1_TX_IRQn		= 19,	/*!< CAN1 TX Interrupt */
-	CAN1_RX0_IRQn		= 20,	/*!< CAN1 RX0 Interrupt */
-	CAN1_RX1_IRQn		= 21,	/*!< CAN1 RX1 Interrupt */
-	CAN1_SCE_IRQn		= 22,	/*!< CAN1 SCE Interrupt */
-	EXTI9_5_IRQn		= 23,	/*!< External Line[9:5] Interrupts */
-	TIM1_BRK_TIM9_IRQn	= 24,	/*!< TIM1 Break interrupt and TIM9 global interrupt */
-	TIM1_UP_TIM10_IRQn	= 25,	/*!< TIM1 Update Interrupt and TIM10 global interrupt */
-	TIM1_TRG_COM_TIM11_IRQn	= 26,	/*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-	TIM1_CC_IRQn		= 27,	/*!< TIM1 Capture Compare Interrupt */
-	TIM2_IRQn		= 28,	/*!< TIM2 global Interrupt */
-	TIM3_IRQn		= 29,	/*!< TIM3 global Interrupt */
-	TIM4_IRQn		= 30,	/*!< TIM4 global Interrupt */
-	I2C1_EV_IRQn		= 31,	/*!< I2C1 Event Interrupt */
-	I2C1_ER_IRQn		= 32,	/*!< I2C1 Error Interrupt */
-	I2C2_EV_IRQn		= 33,	/*!< I2C2 Event Interrupt */
-	I2C2_ER_IRQn		= 34,	/*!< I2C2 Error Interrupt */
-	SPI1_IRQn		= 35,	/*!< SPI1 global Interrupt */
-	SPI2_IRQn		= 36,	/*!< SPI2 global Interrupt */
-	USART1_IRQn		= 37,	/*!< USART1 global Interrupt */
-	USART2_IRQn		= 38,	/*!< USART2 global Interrupt */
-	USART3_IRQn		= 39,	/*!< USART3 global Interrupt */
-	EXTI15_10_IRQn		= 40,	/*!< External Line[15:10] Interrupts */
-	RTC_Alarm_IRQn		= 41,	/*!< RTC Alarm (A and B) through EXTI Line Interrupt */
-	OTG_FS_WKUP_IRQn	= 42,	/*!< USB OTG FS Wakeup through EXTI line interrupt */
-	TIM8_BRK_TIM12_IRQn	= 43,	/*!< TIM8 Break Interrupt and TIM12 global interrupt */
-	TIM8_UP_TIM13_IRQn	= 44,	/*!< TIM8 Update Interrupt and TIM13 global interrupt */
-	TIM8_TRG_COM_TIM14_IRQn	= 45,	/*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-	TIM8_CC_IRQn		= 46,	/*!< TIM8 Capture Compare Interrupt */
-	DMA1_Stream7_IRQn	= 47,	/*!< DMA1 Stream7 Interrupt */
-	FSMC_IRQn		= 48,	/*!< FSMC global Interrupt */
-	SDIO_IRQn		= 49,	/*!< SDIO global Interrupt */
-	TIM5_IRQn		= 50,	/*!< TIM5 global Interrupt */
-	SPI3_IRQn		= 51,	/*!< SPI3 global Interrupt */
-	UART4_IRQn		= 52,	/*!< UART4 global Interrupt */
-	UART5_IRQn		= 53,	/*!< UART5 global Interrupt */
-	TIM6_DAC_IRQn		= 54,	/*!< TIM6 global and DAC1&2 underrun error interrupts */
-	TIM7_IRQn		= 55,	/*!< TIM7 global interrupt */
-	DMA2_Stream0_IRQn	= 56,	/*!< DMA2 Stream 0 global Interrupt */
-	DMA2_Stream1_IRQn	= 57,	/*!< DMA2 Stream 1 global Interrupt */
-	DMA2_Stream2_IRQn	= 58,	/*!< DMA2 Stream 2 global Interrupt */
-	DMA2_Stream3_IRQn	= 59,	/*!< DMA2 Stream 3 global Interrupt */
-	DMA2_Stream4_IRQn	= 60,	/*!< DMA2 Stream 4 global Interrupt */
-	ETH_IRQn		= 61,	/*!< Ethernet global Interrupt */
-	ETH_WKUP_IRQn		= 62,	/*!< Ethernet Wakeup through EXTI line Interrupt */
-	CAN2_TX_IRQn		= 63,	/*!< CAN2 TX Interrupt */
-	CAN2_RX0_IRQn		= 64,	/*!< CAN2 RX0 Interrupt */
-	CAN2_RX1_IRQn		= 65,	/*!< CAN2 RX1 Interrupt */
-	CAN2_SCE_IRQn		= 66,	/*!< CAN2 SCE Interrupt */
-	OTG_FS_IRQn		= 67,	/*!< USB OTG FS global Interrupt */
-	DMA2_Stream5_IRQn	= 68,	/*!< DMA2 Stream 5 global interrupt */
-	DMA2_Stream6_IRQn	= 69,	/*!< DMA2 Stream 6 global interrupt */
-	DMA2_Stream7_IRQn	= 70,	/*!< DMA2 Stream 7 global interrupt */
-	USART6_IRQn		= 71,	/*!< USART6 global interrupt */
-	I2C3_EV_IRQn		= 72,	/*!< I2C3 event interrupt */
-	I2C3_ER_IRQn		= 73,	/*!< I2C3 error interrupt */
-	OTG_HS_EP1_OUT_IRQn	= 74,	/*!< USB OTG HS End Point 1 Out global interrupt */
-	OTG_HS_EP1_IN_IRQn	= 75,	/*!< USB OTG HS End Point 1 In global interrupt */
-	OTG_HS_WKUP_IRQn	= 76,	/*!< USB OTG HS Wakeup through EXTI interrupt */
-	OTG_HS_IRQn		= 77,	/*!< USB OTG HS global interrupt */
-	DCMI_IRQn		= 78,	/*!< DCMI global interrupt */
-	CRYP_IRQn		= 79,	/*!< CRYP crypto global interrupt */
-	HASH_RNG_IRQn		= 80,	/*!< Hash and Rng global interrupt */
-	FPU_IRQn		= 81,	/*!< FPU global interrupt */
-	IRQn_NUM,
+    /* STM32 specific Interrupt Numbers */
+    WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+    PVD_IRQn = 1,  /*!< PVD through EXTI Line detection Interrupt */
+    TAMP_STAMP_IRQn =
+        2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+    RTC_WKUP_IRQn = 3,      /*!< RTC Wakeup interrupt through the EXTI line */
+    FLASH_IRQn = 4,         /*!< FLASH global Interrupt */
+    RCC_IRQn = 5,           /*!< RCC global Interrupt */
+    EXTI0_IRQn = 6,         /*!< EXTI Line0 Interrupt */
+    EXTI1_IRQn = 7,         /*!< EXTI Line1 Interrupt */
+    EXTI2_IRQn = 8,         /*!< EXTI Line2 Interrupt */
+    EXTI3_IRQn = 9,         /*!< EXTI Line3 Interrupt */
+    EXTI4_IRQn = 10,        /*!< EXTI Line4 Interrupt */
+    DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+    DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+    DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+    DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+    DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+    DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+    DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+    ADC_IRQn = 18,          /*!< ADC1, ADC2 and ADC3 global Interrupts */
+    CAN1_TX_IRQn = 19,      /*!< CAN1 TX Interrupt */
+    CAN1_RX0_IRQn = 20,     /*!< CAN1 RX0 Interrupt */
+    CAN1_RX1_IRQn = 21,     /*!< CAN1 RX1 Interrupt */
+    CAN1_SCE_IRQn = 22,     /*!< CAN1 SCE Interrupt */
+    EXTI9_5_IRQn = 23,      /*!< External Line[9:5] Interrupts */
+    TIM1_BRK_TIM9_IRQn =
+        24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+    TIM1_UP_TIM10_IRQn =
+        25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+    TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt
+                                     and TIM11 global interrupt */
+    TIM1_CC_IRQn = 27,            /*!< TIM1 Capture Compare Interrupt */
+    TIM2_IRQn = 28,               /*!< TIM2 global Interrupt */
+    TIM3_IRQn = 29,               /*!< TIM3 global Interrupt */
+    TIM4_IRQn = 30,               /*!< TIM4 global Interrupt */
+    I2C1_EV_IRQn = 31,            /*!< I2C1 Event Interrupt */
+    I2C1_ER_IRQn = 32,            /*!< I2C1 Error Interrupt */
+    I2C2_EV_IRQn = 33,            /*!< I2C2 Event Interrupt */
+    I2C2_ER_IRQn = 34,            /*!< I2C2 Error Interrupt */
+    SPI1_IRQn = 35,               /*!< SPI1 global Interrupt */
+    SPI2_IRQn = 36,               /*!< SPI2 global Interrupt */
+    USART1_IRQn = 37,             /*!< USART1 global Interrupt */
+    USART2_IRQn = 38,             /*!< USART2 global Interrupt */
+    USART3_IRQn = 39,             /*!< USART3 global Interrupt */
+    EXTI15_10_IRQn = 40,          /*!< External Line[15:10] Interrupts */
+    RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+    OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+    TIM8_BRK_TIM12_IRQn =
+        43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+    TIM8_UP_TIM13_IRQn =
+        44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+    TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt
+                                     and TIM14 global interrupt */
+    TIM8_CC_IRQn = 46,            /*!< TIM8 Capture Compare Interrupt */
+    DMA1_Stream7_IRQn = 47,       /*!< DMA1 Stream7 Interrupt */
+    FSMC_IRQn = 48,               /*!< FSMC global Interrupt */
+    SDIO_IRQn = 49,               /*!< SDIO global Interrupt */
+    TIM5_IRQn = 50,               /*!< TIM5 global Interrupt */
+    SPI3_IRQn = 51,               /*!< SPI3 global Interrupt */
+    UART4_IRQn = 52,              /*!< UART4 global Interrupt */
+    UART5_IRQn = 53,              /*!< UART5 global Interrupt */
+    TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+    TIM7_IRQn = 55,     /*!< TIM7 global interrupt */
+    DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+    DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+    DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+    DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+    DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+    ETH_IRQn = 61,          /*!< Ethernet global Interrupt */
+    ETH_WKUP_IRQn = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt */
+    CAN2_TX_IRQn = 63,      /*!< CAN2 TX Interrupt */
+    CAN2_RX0_IRQn = 64,     /*!< CAN2 RX0 Interrupt */
+    CAN2_RX1_IRQn = 65,     /*!< CAN2 RX1 Interrupt */
+    CAN2_SCE_IRQn = 66,     /*!< CAN2 SCE Interrupt */
+    OTG_FS_IRQn = 67,       /*!< USB OTG FS global Interrupt */
+    DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+    DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+    DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+    USART6_IRQn = 71,       /*!< USART6 global interrupt */
+    I2C3_EV_IRQn = 72,      /*!< I2C3 event interrupt */
+    I2C3_ER_IRQn = 73,      /*!< I2C3 error interrupt */
+    OTG_HS_EP1_OUT_IRQn =
+        74,                  /*!< USB OTG HS End Point 1 Out global interrupt */
+    OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+    OTG_HS_WKUP_IRQn = 76,   /*!< USB OTG HS Wakeup through EXTI interrupt */
+    OTG_HS_IRQn = 77,        /*!< USB OTG HS global interrupt */
+    DCMI_IRQn = 78,          /*!< DCMI global interrupt */
+    CRYP_IRQn = 79,          /*!< CRYP crypto global interrupt */
+    HASH_RNG_IRQn = 80,      /*!< Hash and Rng global interrupt */
+    FPU_IRQn = 81,           /*!< FPU global interrupt */
+    IRQn_NUM,
 } IRQn_Type;
 
 #define MAX_IRQn FPU_IRQn
 
 /* Define device IRQ handler name */
-#define WWDG_HANDLER                nvic_handler0
-#define PVD_HANDLER                 nvic_handler1
-#define TAMP_STAMP_HANDLER          nvic_handler2
-#define RTC_WKUP_HANDLER            nvic_handler3
-#define FLASH_HANDLER               nvic_handler4
-#define RCC_HANDLER                 nvic_handler5
-#define EXTI0_HANDLER               nvic_handler6
-#define EXTI1_HANDLER               nvic_handler7
-#define EXTI2_HANDLER               nvic_handler8
-#define EXTI3_HANDLER               nvic_handler9
-#define EXTI4_HANDLER               nvic_handler10
-#define DMA1_Stream0_HANDLER        nvic_handler11
-#define DMA1_Stream1_HANDLER        nvic_handler12
-#define DMA1_Stream2_HANDLER        nvic_handler13
-#define DMA1_Stream3_HANDLER        nvic_handler14
-#define DMA1_Stream4_HANDLER        nvic_handler15
-#define DMA1_Stream5_HANDLER        nvic_handler16
-#define DMA1_Stream6_HANDLER        nvic_handler17
-#define ADC_HANDLER                 nvic_handler18
-#define CAN1_TX_HANDLER             nvic_handler19
-#define CAN1_RX0_HANDLER            nvic_handler20
-#define CAN1_RX1_HANDLER            nvic_handler21
-#define CAN1_SCE_HANDLER            nvic_handler22
-#define EXTI9_5_HANDLER             nvic_handler23
-#define TIM1_BRK_TIM9_HANDLER       nvic_handler24
-#define TIM1_UP_TIM10_HANDLER       nvic_handler25
-#define TIM1_TRG_COM_TIM11_HANDLER  nvic_handler26
-#define TIM1_CC_HANDLER             nvic_handler27
-#define TIM2_HANDLER                nvic_handler28
-#define TIM3_HANDLER                nvic_handler29
-#define TIM4_HANDLER                nvic_handler30
-#define I2C1_EV_HANDLER             nvic_handler31
-#define I2C1_ER_HANDLER             nvic_handler32
-#define I2C2_EV_HANDLER             nvic_handler33
-#define I2C2_ER_HANDLER             nvic_handler34
-#define SPI1_HANDLER                nvic_handler35
-#define SPI2_HANDLER                nvic_handler36
-#define USART1_HANDLER              nvic_handler37
-#define USART2_HANDLER              nvic_handler38
-#define USART2_HANDLER              nvic_handler38
-#define USART3_HANDLER              nvic_handler39
-#define EXTI15_10_HANDLER           nvic_handler40
-#define RTC_Alarm_HANDLER           nvic_handler41
-#define OTG_FS_WKUP_HANDLER         nvic_handler42
-#define TIM8_BRK_TIM12_HANDLER      nvic_handler43
-#define TIM8_UP_TIM13_HANDLER       nvic_handler44
-#define TIM8_TRG_COM_TIM14_HANDLER  nvic_handler45
-#define TIM8_CC_HANDLER             nvic_handler46
-#define DMA1_Stream7_HANDLER        nvic_handler47
-#define FSMC_HANDLER                nvic_handler48
-#define SDIO_HANDLER                nvic_handler49
-#define TIM5_HANDLER                nvic_handler50
-#define SPI3_HANDLER                nvic_handler51
-#define UART4_HANDLER               nvic_handler52
-#define UART5_HANDLER               nvic_handler53
-#define TIM6_DAC_HANDLER            nvic_handler54
-#define TIM7_HANDLER                nvic_handler55
-#define DMA2_Stream0_HANDLER        nvic_handler56
-#define DMA2_Stream1_HANDLER        nvic_handler57
-#define DMA2_Stream2_HANDLER        nvic_handler58
-#define DMA2_Stream3_HANDLER        nvic_handler59
-#define DMA2_Stream4_HANDLER        nvic_handler60
-#define ETH_HANDLER                 nvic_handler61
-#define ETH_WKUP_HANDLER            nvic_handler62
-#define CAN2_TX_HANDLER             nvic_handler63
-#define CAN2_RX0_HANDLER            nvic_handler64
-#define CAN2_RX1_HANDLER            nvic_handler65
-#define CAN2_SCE_HANDLER            nvic_handler66
-#define OTG_FS_HANDLER              nvic_handler67
-#define DMA2_Stream5_HANDLER        nvic_handler68
-#define DMA2_Stream6_HANDLER        nvic_handler69
-#define DMA2_Stream7_HANDLER        nvic_handler70
-#define USART6_HANDLER              nvic_handler71
-#define I2C3_EV_HANDLER             nvic_handler72
-#define I2C3_ER_HANDLER             nvic_handler73
-#define OTG_HS_EP1_OUT_HANDLER      nvic_handler74
-#define OTG_HS_EP1_IN_HANDLER       nvic_handler75
-#define OTG_HS_WKUP_HANDLER         nvic_handler76
-#define OTG_HS_HANDLER              nvic_handler77
-#define DCMI_HANDLER                nvic_handler78
-#define CRYP_HANDLER                nvic_handler79
-#define HASH_RNG_HANDLER            nvic_handler80
-#define FPU_HANDLER                 nvic_handler81
+#define WWDG_HANDLER nvic_handler0
+#define PVD_HANDLER nvic_handler1
+#define TAMP_STAMP_HANDLER nvic_handler2
+#define RTC_WKUP_HANDLER nvic_handler3
+#define FLASH_HANDLER nvic_handler4
+#define RCC_HANDLER nvic_handler5
+#define EXTI0_HANDLER nvic_handler6
+#define EXTI1_HANDLER nvic_handler7
+#define EXTI2_HANDLER nvic_handler8
+#define EXTI3_HANDLER nvic_handler9
+#define EXTI4_HANDLER nvic_handler10
+#define DMA1_Stream0_HANDLER nvic_handler11
+#define DMA1_Stream1_HANDLER nvic_handler12
+#define DMA1_Stream2_HANDLER nvic_handler13
+#define DMA1_Stream3_HANDLER nvic_handler14
+#define DMA1_Stream4_HANDLER nvic_handler15
+#define DMA1_Stream5_HANDLER nvic_handler16
+#define DMA1_Stream6_HANDLER nvic_handler17
+#define ADC_HANDLER nvic_handler18
+#define CAN1_TX_HANDLER nvic_handler19
+#define CAN1_RX0_HANDLER nvic_handler20
+#define CAN1_RX1_HANDLER nvic_handler21
+#define CAN1_SCE_HANDLER nvic_handler22
+#define EXTI9_5_HANDLER nvic_handler23
+#define TIM1_BRK_TIM9_HANDLER nvic_handler24
+#define TIM1_UP_TIM10_HANDLER nvic_handler25
+#define TIM1_TRG_COM_TIM11_HANDLER nvic_handler26
+#define TIM1_CC_HANDLER nvic_handler27
+#define TIM2_HANDLER nvic_handler28
+#define TIM3_HANDLER nvic_handler29
+#define TIM4_HANDLER nvic_handler30
+#define I2C1_EV_HANDLER nvic_handler31
+#define I2C1_ER_HANDLER nvic_handler32
+#define I2C2_EV_HANDLER nvic_handler33
+#define I2C2_ER_HANDLER nvic_handler34
+#define SPI1_HANDLER nvic_handler35
+#define SPI2_HANDLER nvic_handler36
+#define USART1_HANDLER nvic_handler37
+#define USART2_HANDLER nvic_handler38
+#define USART2_HANDLER nvic_handler38
+#define USART3_HANDLER nvic_handler39
+#define EXTI15_10_HANDLER nvic_handler40
+#define RTC_Alarm_HANDLER nvic_handler41
+#define OTG_FS_WKUP_HANDLER nvic_handler42
+#define TIM8_BRK_TIM12_HANDLER nvic_handler43
+#define TIM8_UP_TIM13_HANDLER nvic_handler44
+#define TIM8_TRG_COM_TIM14_HANDLER nvic_handler45
+#define TIM8_CC_HANDLER nvic_handler46
+#define DMA1_Stream7_HANDLER nvic_handler47
+#define FSMC_HANDLER nvic_handler48
+#define SDIO_HANDLER nvic_handler49
+#define TIM5_HANDLER nvic_handler50
+#define SPI3_HANDLER nvic_handler51
+#define UART4_HANDLER nvic_handler52
+#define UART5_HANDLER nvic_handler53
+#define TIM6_DAC_HANDLER nvic_handler54
+#define TIM7_HANDLER nvic_handler55
+#define DMA2_Stream0_HANDLER nvic_handler56
+#define DMA2_Stream1_HANDLER nvic_handler57
+#define DMA2_Stream2_HANDLER nvic_handler58
+#define DMA2_Stream3_HANDLER nvic_handler59
+#define DMA2_Stream4_HANDLER nvic_handler60
+#define ETH_HANDLER nvic_handler61
+#define ETH_WKUP_HANDLER nvic_handler62
+#define CAN2_TX_HANDLER nvic_handler63
+#define CAN2_RX0_HANDLER nvic_handler64
+#define CAN2_RX1_HANDLER nvic_handler65
+#define CAN2_SCE_HANDLER nvic_handler66
+#define OTG_FS_HANDLER nvic_handler67
+#define DMA2_Stream5_HANDLER nvic_handler68
+#define DMA2_Stream6_HANDLER nvic_handler69
+#define DMA2_Stream7_HANDLER nvic_handler70
+#define USART6_HANDLER nvic_handler71
+#define I2C3_EV_HANDLER nvic_handler72
+#define I2C3_ER_HANDLER nvic_handler73
+#define OTG_HS_EP1_OUT_HANDLER nvic_handler74
+#define OTG_HS_EP1_IN_HANDLER nvic_handler75
+#define OTG_HS_WKUP_HANDLER nvic_handler76
+#define OTG_HS_HANDLER nvic_handler77
+#define DCMI_HANDLER nvic_handler78
+#define CRYP_HANDLER nvic_handler79
+#define HASH_RNG_HANDLER nvic_handler80
+#define FPU_HANDLER nvic_handler81
 
 
-#define IRQ_VEC_N_HANDLER_DECLARE(n) \
-	void nvic_handler##n (void);
+#define IRQ_VEC_N_HANDLER_DECLARE(n) void nvic_handler##n(void);
 
-#define IRQ_VEC_N_OP	IRQ_VEC_N_HANDLER_DECLARE
+#define IRQ_VEC_N_OP IRQ_VEC_N_HANDLER_DECLARE
 #include "platform/stm32f4/nvic_private.h"
 #undef IRQ_VEC_N_OP
 
 typedef struct {
-	volatile uint32_t ISER[8];	/*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-	uint32_t RESERVED0[24];
-	volatile uint32_t ICER[8];	/*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-	uint32_t RSERVED1[24];
-	volatile uint32_t ISPR[8];	/*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-	uint32_t RESERVED2[24];
-	volatile uint32_t ICPR[8];	/*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-	uint32_t RESERVED3[24];
-	volatile uint32_t IABR[8];	/*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-	uint32_t RESERVED4[56];
-	volatile uint8_t  IP[240];	/*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-	uint32_t RESERVED5[644];
-	volatile uint32_t STIR;		/*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+    volatile uint32_t
+        ISER[8]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[24];
+    volatile uint32_t
+        ICER[8]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[24];
+    volatile uint32_t
+        ISPR[8]; /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[24];
+    volatile uint32_t
+        ICPR[8]; /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[24];
+    volatile uint32_t
+        IABR[8]; /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+    uint32_t RESERVED4[56];
+    volatile uint8_t IP[240]; /*!< Offset: 0x300 (R/W)  Interrupt Priority
+                                 Register (8Bit wide) */
+    uint32_t RESERVED5[644];
+    volatile uint32_t
+        STIR; /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
 } NVIC_Type;
 
-#define NVIC_PriorityGroup_0         ((uint32_t) 0x700) /*!< 0 bits for pre-emption priority
-								4 bits for subpriority */
-#define NVIC_PriorityGroup_1         ((uint32_t) 0x600) /*!< 1 bits for pre-emption priority
-								3 bits for subpriority */
-#define NVIC_PriorityGroup_2         ((uint32_t) 0x500) /*!< 2 bits for pre-emption priority
-								2 bits for subpriority */
-#define NVIC_PriorityGroup_3         ((uint32_t) 0x400) /*!< 3 bits for pre-emption priority
-								1 bits for subpriority */
-#define NVIC_PriorityGroup_4         ((uint32_t) 0x300) /*!< 4 bits for pre-emption priority
-								0 bits for subpriority */
-#define NVIC \
-	((NVIC_Type *) NVIC_BASE)
+#define NVIC_PriorityGroup_0                                \
+    ((uint32_t) 0x700) /*!< 0 bits for pre-emption priority \
+4 bits for subpriority */
+#define NVIC_PriorityGroup_1                                \
+    ((uint32_t) 0x600) /*!< 1 bits for pre-emption priority \
+3 bits for subpriority */
+#define NVIC_PriorityGroup_2                                \
+    ((uint32_t) 0x500) /*!< 2 bits for pre-emption priority \
+2 bits for subpriority */
+#define NVIC_PriorityGroup_3                                \
+    ((uint32_t) 0x400) /*!< 3 bits for pre-emption priority \
+1 bits for subpriority */
+#define NVIC_PriorityGroup_4                                \
+    ((uint32_t) 0x300) /*!< 4 bits for pre-emption priority \
+0 bits for subpriority */
+#define NVIC ((NVIC_Type *) NVIC_BASE)
 
 
-void NVIC_SetPriority(IRQn_Type IRQn, uint8_t group_priority, uint8_t sub_priority);
+void NVIC_SetPriority(IRQn_Type IRQn,
+                      uint8_t group_priority,
+                      uint8_t sub_priority);
 void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
 
-inline static void  NVIC_EnableIRQ(IRQn_Type IRQn)
+inline static void NVIC_EnableIRQ(IRQn_Type IRQn)
 {
-	NVIC->ISER[((uint32_t) IRQn >> 0x5)] = (1 << ((uint32_t)(IRQn) & 0x1f));
+    NVIC->ISER[((uint32_t) IRQn >> 0x5)] = (1 << ((uint32_t) (IRQn) & 0x1f));
 }
 
 inline static void NVIC_DisableIRQ(IRQn_Type IRQn)
 {
-	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+    NVIC->ICER[((uint32_t) (IRQn) >> 5)] = (1 << ((uint32_t) (IRQn) & 0x1F));
 }
 
 inline static uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
-	return (uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] &
-	                   (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0);
+    return (uint32_t) ((NVIC->ISPR[(uint32_t) (IRQn) >> 5] &
+                        (1 << ((uint32_t) (IRQn) & 0x1F)))
+                           ? 1
+                           : 0);
 }
 
 inline static void NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
-	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+    NVIC->ISPR[((uint32_t) (IRQn) >> 5)] = (1 << ((uint32_t) (IRQn) & 0x1F));
 }
 
 inline static void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
-	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+    NVIC->ICPR[((uint32_t) (IRQn) >> 5)] = (1 << ((uint32_t) (IRQn) & 0x1F));
 }
 
 inline static uint32_t NVIC_GetActive(IRQn_Type IRQn)
 {
-	return (uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] &
-	                  (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0);
+    return (uint32_t) ((NVIC->IABR[(uint32_t) (IRQn) >> 5] &
+                        (1 << ((uint32_t) (IRQn) & 0x1F)))
+                           ? 1
+                           : 0);
 }
 
 int nvic_is_setup(int irq);
diff --git a/include/platform/stm32f4/nvic_private.h b/include/platform/stm32f4/nvic_private.h
index 1f55ebbc..d459ba41 100644
--- a/include/platform/stm32f4/nvic_private.h
+++ b/include/platform/stm32f4/nvic_private.h
@@ -1,410 +1,410 @@
 /* This header is only included internally. */
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_WWDG_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_WWDG_USER_IRQ))
 IRQ_VEC_N_OP(0)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_PVD_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_PVD_USER_IRQ))
 IRQ_VEC_N_OP(1)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TAMP_STAMP_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TAMP_STAMP_USER_IRQ))
 IRQ_VEC_N_OP(2)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_RTC_WKUP_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_RTC_WKUP_USER_IRQ))
 IRQ_VEC_N_OP(3)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_FLASH_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_FLASH_USER_IRQ))
 IRQ_VEC_N_OP(4)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_RCC_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_RCC_USER_IRQ))
 IRQ_VEC_N_OP(5)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_EXTI0_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_EXTI0_USER_IRQ))
 IRQ_VEC_N_OP(6)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_EXTI1_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_EXTI1_USER_IRQ))
 IRQ_VEC_N_OP(7)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_EXTI2_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_EXTI2_USER_IRQ))
 IRQ_VEC_N_OP(8)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_EXTI3_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_EXTI3_USER_IRQ))
 IRQ_VEC_N_OP(9)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_EXTI4_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_EXTI4_USER_IRQ))
 IRQ_VEC_N_OP(10)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream0_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream0_USER_IRQ))
 IRQ_VEC_N_OP(11)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream1_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream1_USER_IRQ))
 IRQ_VEC_N_OP(12)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream2_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream2_USER_IRQ))
 IRQ_VEC_N_OP(13)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream3_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream3_USER_IRQ))
 IRQ_VEC_N_OP(14)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream4_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream4_USER_IRQ))
 IRQ_VEC_N_OP(15)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream5_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream5_USER_IRQ))
 IRQ_VEC_N_OP(16)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream6_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream6_USER_IRQ))
 IRQ_VEC_N_OP(17)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_ADC_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_ADC_USER_IRQ))
 IRQ_VEC_N_OP(18)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CAN1_TX_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CAN1_TX_USER_IRQ))
 IRQ_VEC_N_OP(19)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CAN1_RX_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CAN1_RX_USER_IRQ))
 IRQ_VEC_N_OP(20)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CAN1_RX1_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CAN1_RX1_USER_IRQ))
 IRQ_VEC_N_OP(21)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CAN1_SCE_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CAN1_SCE_USER_IRQ))
 IRQ_VEC_N_OP(22)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_EXTI9_5_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_EXTI9_5_USER_IRQ))
 IRQ_VEC_N_OP(23)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM1_BRK_TIM9_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM1_BRK_TIM9_USER_IRQ))
 IRQ_VEC_N_OP(24)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM1_UP_TIM10_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM1_UP_TIM10_USER_IRQ))
 IRQ_VEC_N_OP(25)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM1_TRG_COM_TIM11_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM1_TRG_COM_TIM11_USER_IRQ))
 IRQ_VEC_N_OP(26)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM1_CC_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM1_CC_USER_IRQ))
 IRQ_VEC_N_OP(27)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM2_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM2_USER_IRQ))
 IRQ_VEC_N_OP(28)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM3_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM3_USER_IRQ))
 IRQ_VEC_N_OP(29)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM4_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM4_USER_IRQ))
 IRQ_VEC_N_OP(30)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_I2C1_EV_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_I2C1_EV_USER_IRQ))
 IRQ_VEC_N_OP(31)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_I2C1_ER_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_I2C1_ER_USER_IRQ))
 IRQ_VEC_N_OP(32)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_I2C2_EV_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_I2C2_EV_USER_IRQ))
 IRQ_VEC_N_OP(33)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_I2C2_ER_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_I2C2_ER_USER_IRQ))
 IRQ_VEC_N_OP(34)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_SPI1_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_SPI1_USER_IRQ))
 IRQ_VEC_N_OP(35)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_SPI2_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_SPI2_USER_IRQ))
 IRQ_VEC_N_OP(36)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_USART1_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_USART1_USER_IRQ))
 IRQ_VEC_N_OP(37)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_USART2_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_USART2_USER_IRQ))
 IRQ_VEC_N_OP(38)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_USART3_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_USART3_USER_IRQ))
 IRQ_VEC_N_OP(39)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_EXTI15_10_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_EXTI15_10_USER_IRQ))
 IRQ_VEC_N_OP(40)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_RTC_Alarm_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_RTC_Alarm_USER_IRQ))
 IRQ_VEC_N_OP(41)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_OTG_FS_WKUP_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_OTG_FS_WKUP_USER_IRQ))
 IRQ_VEC_N_OP(42)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM8_BRK_TIM12_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM8_BRK_TIM12_USER_IRQ))
 IRQ_VEC_N_OP(43)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM8_UP_TIM13_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM8_UP_TIM13_USER_IRQ))
 IRQ_VEC_N_OP(44)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM8_TRG_COM_TIM14_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM8_TRG_COM_TIM14_USER_IRQ))
 IRQ_VEC_N_OP(45)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM8_CC_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM8_CC_USER_IRQ))
 IRQ_VEC_N_OP(46)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream7_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream7_USER_IRQ))
 IRQ_VEC_N_OP(47)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_FSMC_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_FSMC_USER_IRQ))
 IRQ_VEC_N_OP(48)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_SDIO_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_SDIO_USER_IRQ))
 IRQ_VEC_N_OP(49)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM5_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM5_USER_IRQ))
 IRQ_VEC_N_OP(50)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_SPI3_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_SPI3_USER_IRQ))
 IRQ_VEC_N_OP(51)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_UART4_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_UART4_USER_IRQ))
 IRQ_VEC_N_OP(52)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_UART5_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_UART5_USER_IRQ))
 IRQ_VEC_N_OP(53)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM6_DAC_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM6_DAC_USER_IRQ))
 IRQ_VEC_N_OP(54)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM7_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM7_USER_IRQ))
 IRQ_VEC_N_OP(55)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream0_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream0_USER_IRQ))
 IRQ_VEC_N_OP(56)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream1_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream1_USER_IRQ))
 IRQ_VEC_N_OP(57)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream2_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream2_USER_IRQ))
 IRQ_VEC_N_OP(58)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream3_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream3_USER_IRQ))
 IRQ_VEC_N_OP(59)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream4_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream4_USER_IRQ))
 IRQ_VEC_N_OP(60)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_ETH_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_ETH_USER_IRQ))
 IRQ_VEC_N_OP(61)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_ETH_WKUP_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_ETH_WKUP_USER_IRQ))
 IRQ_VEC_N_OP(62)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CAN2_TX_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CAN2_TX_USER_IRQ))
 IRQ_VEC_N_OP(63)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CAN2_RX0_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CAN2_RX0_USER_IRQ))
 IRQ_VEC_N_OP(64)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CAN2_RX1_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CAN2_RX1_USER_IRQ))
 IRQ_VEC_N_OP(65)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CAN2_SCE_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CAN2_SCE_USER_IRQ))
 IRQ_VEC_N_OP(66)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_OTG_FS_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_OTG_FS_USER_IRQ))
 IRQ_VEC_N_OP(67)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream5_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream5_USER_IRQ))
 IRQ_VEC_N_OP(68)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream6_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream6_USER_IRQ))
 IRQ_VEC_N_OP(69)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream7_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream7_USER_IRQ))
 IRQ_VEC_N_OP(70)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_USART6_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_USART6_USER_IRQ))
 IRQ_VEC_N_OP(71)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_I2C3_EV_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_I2C3_EV_USER_IRQ))
 IRQ_VEC_N_OP(72)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_I2C3_ER_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_I2C3_ER_USER_IRQ))
 IRQ_VEC_N_OP(73)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_OTG_HS_EP1_OUT_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_OTG_HS_EP1_OUT_USER_IRQ))
 IRQ_VEC_N_OP(74)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_OTG_HS_EP1_IN_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_OTG_HS_EP1_IN_USER_IRQ))
 IRQ_VEC_N_OP(75)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_OTG_HS_WKUP_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_OTG_HS_WKUP_USER_IRQ))
 IRQ_VEC_N_OP(76)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_OTG_HS_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_OTG_HS_USER_IRQ))
 IRQ_VEC_N_OP(77)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DCMI_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DCMI_USER_IRQ))
 IRQ_VEC_N_OP(78)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CRYP_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CRYP_USER_IRQ))
 IRQ_VEC_N_OP(79)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_HASH_RNG_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_HASH_RNG_USER_IRQ))
 IRQ_VEC_N_OP(80)
 #endif
 
-#if !defined(USER_INTERRUPT) || (\
-	defined(USER_INTERRUPT) && defined(CONFIG_FPU_USER_IRQ))
+#if !defined(USER_INTERRUPT) || \
+    (defined(USER_INTERRUPT) && defined(CONFIG_FPU_USER_IRQ))
 IRQ_VEC_N_OP(81)
 #endif
diff --git a/include/platform/stm32f4/nvic_table.h b/include/platform/stm32f4/nvic_table.h
index 19ace9d5..e5d323cc 100644
--- a/include/platform/stm32f4/nvic_table.h
+++ b/include/platform/stm32f4/nvic_table.h
@@ -1,8 +1,7 @@
 /* NVIC platform-speific table generator */
 
-#define IRQ_HANDLER_FUNC(n) \
-        nvic_handler##n,
+#define IRQ_HANDLER_FUNC(n) nvic_handler##n,
 
-#define IRQ_VEC_N_OP    IRQ_HANDLER_FUNC
+#define IRQ_VEC_N_OP IRQ_HANDLER_FUNC
 #include "platform/stm32f4/nvic_private.h"
 #undef IRQ_VEC_N_OP
diff --git a/include/platform/stm32f4/rcc.h b/include/platform/stm32f4/rcc.h
index 38906e63..153bc450 100644
--- a/include/platform/stm32f4/rcc.h
+++ b/include/platform/stm32f4/rcc.h
@@ -3,27 +3,27 @@
 
 #include <platform/stm32f4/registers.h>
 struct rcc_clocks {
-	uint32_t sysclk_freq;
-	uint32_t hclk_freq;
-	uint32_t pclk1_freq;
-	uint32_t pclk2_freq;
+    uint32_t sysclk_freq;
+    uint32_t hclk_freq;
+    uint32_t pclk1_freq;
+    uint32_t pclk2_freq;
 };
 
 /* RCC_FLAG definition */
-#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
-#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
-#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
-#define RCC_FLAG_PLLI2SRDY               ((uint8_t)0x3B)
-#define RCC_FLAG_PLLSAIRDY               ((uint8_t)0x3D)
-#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
-#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
-#define RCC_FLAG_BORRST                  ((uint8_t)0x79)
-#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
-#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
-#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
-#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
-#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
-#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
+#define RCC_FLAG_HSIRDY ((uint8_t) 0x21)
+#define RCC_FLAG_HSERDY ((uint8_t) 0x31)
+#define RCC_FLAG_PLLRDY ((uint8_t) 0x39)
+#define RCC_FLAG_PLLI2SRDY ((uint8_t) 0x3B)
+#define RCC_FLAG_PLLSAIRDY ((uint8_t) 0x3D)
+#define RCC_FLAG_LSERDY ((uint8_t) 0x41)
+#define RCC_FLAG_LSIRDY ((uint8_t) 0x61)
+#define RCC_FLAG_BORRST ((uint8_t) 0x79)
+#define RCC_FLAG_PINRST ((uint8_t) 0x7A)
+#define RCC_FLAG_PORRST ((uint8_t) 0x7B)
+#define RCC_FLAG_SFTRST ((uint8_t) 0x7C)
+#define RCC_FLAG_IWDGRST ((uint8_t) 0x7D)
+#define RCC_FLAG_WWDGRST ((uint8_t) 0x7E)
+#define RCC_FLAG_LPWRRST ((uint8_t) 0x7F)
 
 void sys_clock_init(void);
 void RCC_AHB1PeriphClockCmd(uint32_t rcc_AHB1, uint8_t enable);
@@ -33,6 +33,6 @@ void RCC_APB1PeriphResetCmd(uint32_t rcc_APB1, uint8_t enable);
 void RCC_APB2PeriphClockCmd(uint32_t rcc_APB2, uint8_t enable);
 void RCC_APB2PeriphResetCmd(uint32_t rcc_APB2, uint8_t enable);
 uint8_t RCC_GetFlagStatus(uint8_t flag);
-void RCC_GetClocksFreq(struct rcc_clocks* clock);
+void RCC_GetClocksFreq(struct rcc_clocks *clock);
 
 #endif
diff --git a/include/platform/stm32f4/registers.h b/include/platform/stm32f4/registers.h
index 101276ac..804c40a4 100644
--- a/include/platform/stm32f4/registers.h
+++ b/include/platform/stm32f4/registers.h
@@ -8,1030 +8,1727 @@
 #define STM32F4X
 
 /* Memory Map */
-#define MEMORY_BASE                     (uint32_t) (0x00000000)                                 /* Base of memory map */
-#define FLASH_BASE                      (uint32_t) (0x08000000)                                 /* Flash Memory Base Address */
-#define RAM_BASE                        (uint32_t) (0x20000000)                                 /* RAM Base Address */
-#define ETHRAM_BASE                     (uint32_t) (0x2001C000)                                 /* ETHRAM Base Address */
-#define CCMRAM_BASE                     (uint32_t) (0x10000000)                                 /* CCMRAM Base Address - Accessible only to CPU */
+#define MEMORY_BASE (uint32_t) (0x00000000) /* Base of memory map */
+#define FLASH_BASE (uint32_t) (0x08000000)  /* Flash Memory Base Address */
+#define RAM_BASE (uint32_t) (0x20000000)    /* RAM Base Address */
+#define ETHRAM_BASE (uint32_t) (0x2001C000) /* ETHRAM Base Address */
+#define CCMRAM_BASE \
+    (uint32_t) (0x10000000) /* CCMRAM Base Address - Accessible only to CPU */
 
 /* Peripheral Map */
-#define PERIPH_BASE                     (uint32_t) (0x40000000)                                 /* Peripheral base address */
-#define PRIV_PERIPH_BASE                (uint32_t) (0xED000000)                                 /* Private peripheral base address */
-#define APB1PERIPH_BASE                 (PERIPH_BASE)
-#define APB2PERIPH_BASE                 (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE                 (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE                 (PERIPH_BASE + 0x10000000)
+#define PERIPH_BASE (uint32_t) (0x40000000) /* Peripheral base address */
+#define PRIV_PERIPH_BASE \
+    (uint32_t) (0xED000000) /* Private peripheral base address */
+#define APB1PERIPH_BASE (PERIPH_BASE)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
 
 
 
 /* APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
 
 /* APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
 
 /* AHB */
-#define GPIO_BASE(port)                 (AHB1PERIPH_BASE + (0x400*port))                        /* GPIO Port base address */
-#define RCC_BASE                        (AHB1PERIPH_BASE + 0x3800)                              /* Reset and Clock Control base address */
-#define FLASH_R_BASE                    (AHB1PERIPH_BASE + 0x3C00)                              /* Flash registers base address */
-#define DMA1_BASE                       (AHB1PERIPH_BASE + 0x6000)                              /* DMA1 base address */
-#define DMA2_BASE                       (AHB1PERIPH_BASE + 0x6400)                              /* DMA2 base address */
-#define USB_FS_BASE                     (AHB2PERIPH_BASE + 0x0000)                              /* USB OTG FS base address */
+#define GPIO_BASE(port) \
+    (AHB1PERIPH_BASE + (0x400 * port)) /* GPIO Port base address */
+#define RCC_BASE \
+    (AHB1PERIPH_BASE + 0x3800) /* Reset and Clock Control base address */
+#define FLASH_R_BASE \
+    (AHB1PERIPH_BASE + 0x3C00)               /* Flash registers base address */
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) /* DMA1 base address */
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) /* DMA2 base address */
+#define USB_FS_BASE (AHB2PERIPH_BASE + 0x0000) /* USB OTG FS base address */
 
 
 /* Timer 1 (TIM1) */
-#define TIM1_CR1                        (volatile uint32_t *) (TIM1_BASE + 0x00)                /* TIM1 control register 1 */
-#define TIM1_CR2                        (volatile uint32_t *) (TIM1_BASE + 0x04)                /* TIM1 control register 2 */
-#define TIM1_SMCR                       (volatile uint32_t *) (TIM1_BASE + 0x08)                /* TIM1 slave mode control register */
-#define TIM1_DIER                       (volatile uint32_t *) (TIM1_BASE + 0x0C)                /* TIM1 DMA/Interrupt enable register */
-#define TIM1_SR                         (volatile uint32_t *) (TIM1_BASE + 0x10)                /* TIM1 status register */
-#define TIM1_EGR                        (volatile uint32_t *) (TIM1_BASE + 0x14)                /* TIM1 event generation register */
-#define TIM1_CCMR1                      (volatile uint32_t *) (TIM1_BASE + 0x18)                /* TIM1 capture/compare mode register 1 */
-#define TIM1_CCMR2                      (volatile uint32_t *) (TIM1_BASE + 0x1C)                /* TIM1 capture/compare mode register 2 */
-#define TIM1_CCER                       (volatile uint32_t *) (TIM1_BASE + 0x20)                /* TIM1 capture/compare enable register */
-#define TIM1_CNT                        (volatile uint32_t *) (TIM1_BASE + 0x24)                /* TIM1 counter */
-#define TIM1_PSC                        (volatile uint32_t *) (TIM1_BASE + 0x28)                /* TIM1 prescaler */
-#define TIM1_ARR                        (volatile uint32_t *) (TIM1_BASE + 0x2C)                /* TIM1 auto-reload register */
-#define TIM1_CCR1                       (volatile uint32_t *) (TIM1_BASE + 0x34)                /* TIM1 capture/compare register 1 */
-#define TIM1_CCR2                       (volatile uint32_t *) (TIM1_BASE + 0x38)                /* TIM1 capture/compare register 2 */
-#define TIM1_CCR3                       (volatile uint32_t *) (TIM1_BASE + 0x3C)                /* TIM1 capture/compare register 3 */
-#define TIM1_CCR4                       (volatile uint32_t *) (TIM1_BASE + 0x40)                /* TIM1 capture/compare register 4 */
-#define TIM1_DCR                        (volatile uint32_t *) (TIM1_BASE + 0x48)                /* TIM1 DMA control register */
-#define TIM1_DMAR                       (volatile uint32_t *) (TIM1_BASE + 0x4C)                /* TIM1 DMA address for full transfer */
-#define TIM1_OR                         (volatile uint32_t *) (TIM1_BASE + 0x50)                /* TIM1 option register */
-
-#define TIM2_CR1                        (volatile uint32_t *) (TIM2_BASE + 0x00)                /* TIM2 control register 1 */
-#define TIM2_CR2                        (volatile uint32_t *) (TIM2_BASE + 0x04)                /* TIM2 control register 2 */
-#define TIM2_SMCR                       (volatile uint32_t *) (TIM2_BASE + 0x08)                /* TIM2 slave mode control register */
-#define TIM2_DIER                       (volatile uint32_t *) (TIM2_BASE + 0x0C)                /* TIM2 DMA/Interrupt enable register */
-#define TIM2_SR                         (volatile uint32_t *) (TIM2_BASE + 0x10)                /* TIM2 status register */
-#define TIM2_EGR                        (volatile uint32_t *) (TIM2_BASE + 0x14)                /* TIM2 event generation register */
-#define TIM2_CCMR1                      (volatile uint32_t *) (TIM2_BASE + 0x18)                /* TIM2 capture/compare mode register 1 */
-#define TIM2_CCMR2                      (volatile uint32_t *) (TIM2_BASE + 0x1C)                /* TIM2 capture/compare mode register 2 */
-#define TIM2_CCER                       (volatile uint32_t *) (TIM2_BASE + 0x20)                /* TIM2 capture/compare enable register */
-#define TIM2_CNT                        (volatile uint32_t *) (TIM2_BASE + 0x24)                /* TIM2 counter */
-#define TIM2_PSC                        (volatile uint32_t *) (TIM2_BASE + 0x28)                /* TIM2 prescaler */
-#define TIM2_ARR                        (volatile uint32_t *) (TIM2_BASE + 0x2C)                /* TIM2 auto-reload register */
-#define TIM2_CCR1                       (volatile uint32_t *) (TIM2_BASE + 0x34)                /* TIM2 capture/compare register 1 */
-#define TIM2_CCR2                       (volatile uint32_t *) (TIM2_BASE + 0x38)                /* TIM2 capture/compare register 2 */
-#define TIM2_CCR3                       (volatile uint32_t *) (TIM2_BASE + 0x3C)                /* TIM2 capture/compare register 3 */
-#define TIM2_CCR4                       (volatile uint32_t *) (TIM2_BASE + 0x40)                /* TIM2 capture/compare register 4 */
-#define TIM2_DCR                        (volatile uint32_t *) (TIM2_BASE + 0x48)                /* TIM2 DMA control register */
-#define TIM2_DMAR                       (volatile uint32_t *) (TIM2_BASE + 0x4C)                /* TIM2 DMA address for full transfer */
-#define TIM2_OR                         (volatile uint32_t *) (TIM2_BASE + 0x50)                /* TIM2 option register */
+#define TIM1_CR1 \
+    (volatile uint32_t *) (TIM1_BASE + 0x00) /* TIM1 control register 1 */
+#define TIM1_CR2 \
+    (volatile uint32_t *) (TIM1_BASE + 0x04) /* TIM1 control register 2 */
+#define TIM1_SMCR                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x08) /* TIM1 slave mode control register */
+#define TIM1_DIER                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x0C) /* TIM1 DMA/Interrupt enable register */
+#define TIM1_SR \
+    (volatile uint32_t *) (TIM1_BASE + 0x10) /* TIM1 status register */
+#define TIM1_EGR                       \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x14) /* TIM1 event generation register */
+#define TIM1_CCMR1                     \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x18) /* TIM1 capture/compare mode register 1 */
+#define TIM1_CCMR2                     \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x1C) /* TIM1 capture/compare mode register 2 */
+#define TIM1_CCER                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x20) /* TIM1 capture/compare enable register */
+#define TIM1_CNT (volatile uint32_t *) (TIM1_BASE + 0x24) /* TIM1 counter */
+#define TIM1_PSC (volatile uint32_t *) (TIM1_BASE + 0x28) /* TIM1 prescaler */
+#define TIM1_ARR \
+    (volatile uint32_t *) (TIM1_BASE + 0x2C) /* TIM1 auto-reload register */
+#define TIM1_CCR1                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x34) /* TIM1 capture/compare register 1 */
+#define TIM1_CCR2                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x38) /* TIM1 capture/compare register 2 */
+#define TIM1_CCR3                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x3C) /* TIM1 capture/compare register 3 */
+#define TIM1_CCR4                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x40) /* TIM1 capture/compare register 4 */
+#define TIM1_DCR \
+    (volatile uint32_t *) (TIM1_BASE + 0x48) /* TIM1 DMA control register */
+#define TIM1_DMAR                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x4C) /* TIM1 DMA address for full transfer */
+#define TIM1_OR \
+    (volatile uint32_t *) (TIM1_BASE + 0x50) /* TIM1 option register */
+
+#define TIM2_CR1 \
+    (volatile uint32_t *) (TIM2_BASE + 0x00) /* TIM2 control register 1 */
+#define TIM2_CR2 \
+    (volatile uint32_t *) (TIM2_BASE + 0x04) /* TIM2 control register 2 */
+#define TIM2_SMCR                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x08) /* TIM2 slave mode control register */
+#define TIM2_DIER                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x0C) /* TIM2 DMA/Interrupt enable register */
+#define TIM2_SR \
+    (volatile uint32_t *) (TIM2_BASE + 0x10) /* TIM2 status register */
+#define TIM2_EGR                       \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x14) /* TIM2 event generation register */
+#define TIM2_CCMR1                     \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x18) /* TIM2 capture/compare mode register 1 */
+#define TIM2_CCMR2                     \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x1C) /* TIM2 capture/compare mode register 2 */
+#define TIM2_CCER                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x20) /* TIM2 capture/compare enable register */
+#define TIM2_CNT (volatile uint32_t *) (TIM2_BASE + 0x24) /* TIM2 counter */
+#define TIM2_PSC (volatile uint32_t *) (TIM2_BASE + 0x28) /* TIM2 prescaler */
+#define TIM2_ARR \
+    (volatile uint32_t *) (TIM2_BASE + 0x2C) /* TIM2 auto-reload register */
+#define TIM2_CCR1                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x34) /* TIM2 capture/compare register 1 */
+#define TIM2_CCR2                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x38) /* TIM2 capture/compare register 2 */
+#define TIM2_CCR3                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x3C) /* TIM2 capture/compare register 3 */
+#define TIM2_CCR4                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x40) /* TIM2 capture/compare register 4 */
+#define TIM2_DCR \
+    (volatile uint32_t *) (TIM2_BASE + 0x48) /* TIM2 DMA control register */
+#define TIM2_DMAR                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x4C) /* TIM2 DMA address for full transfer */
+#define TIM2_OR \
+    (volatile uint32_t *) (TIM2_BASE + 0x50) /* TIM2 option register */
 /* Power Control (PWR) */
-#define PWR_CR                          (volatile uint32_t *) (PWR_BASE + 0x00)                 /* Power Control Register */
-#define PWR_CSR                         (volatile uint32_t *) (PWR_BASE + 0x04)                 /* Power Control/Status Register */
+#define PWR_CR \
+    (volatile uint32_t *) (PWR_BASE + 0x00) /* Power Control Register */
+#define PWR_CSR                                                              \
+    (volatile uint32_t *) (PWR_BASE + 0x04) /* Power Control/Status Register \
+                                             */
 
 /* SPI */
-#define SPI_CR1(port)                   (volatile uint32_t *) (SPI_BASE(port) + 0x00)           /* SPI control register 1 */
-#define SPI_CR2(port)                   (volatile uint32_t *) (SPI_BASE(port) + 0x04)           /* SPI control register 2 */
-#define SPI_SR(port)                    (volatile uint32_t *) (SPI_BASE(port) + 0x08)           /* SPI status register */
-#define SPI_DR(port)                    (volatile uint32_t *) (SPI_BASE(port) + 0x0c)           /* SPI data register */
-#define SPI_CRCPR(port)                 (volatile uint32_t *) (SPI_BASE(port) + 0x10)           /* SPI CRC polynomial register */
-#define SPI_RXCRCR(port)                (volatile uint32_t *) (SPI_BASE(port) + 0x14)           /* SPI RX CRC register */
-#define SPI_TXCRCR(port)                (volatile uint32_t *) (SPI_BASE(port) + 0x18)           /* SPI TX CRC register */
-#define SPI_I2SCFGR(port)               (volatile uint32_t *) (SPI_BASE(port) + 0x1c)           /* SPI I2C configuration register */
-#define SPI_I2SPR(port)                 (volatile uint32_t *) (SPI_BASE(port) + 0x20)           /* SPI I2C prescaler register */
+#define SPI_CR1(port) \
+    (volatile uint32_t *) (SPI_BASE(port) + 0x00) /* SPI control register 1 */
+#define SPI_CR2(port) \
+    (volatile uint32_t *) (SPI_BASE(port) + 0x04) /* SPI control register 2 */
+#define SPI_SR(port) \
+    (volatile uint32_t *) (SPI_BASE(port) + 0x08) /* SPI status register */
+#define SPI_DR(port) \
+    (volatile uint32_t *) (SPI_BASE(port) + 0x0c) /* SPI data register */
+#define SPI_CRCPR(port)                     \
+    (volatile uint32_t *) (SPI_BASE(port) + \
+                           0x10) /* SPI CRC polynomial register */
+#define SPI_RXCRCR(port) \
+    (volatile uint32_t *) (SPI_BASE(port) + 0x14) /* SPI RX CRC register */
+#define SPI_TXCRCR(port) \
+    (volatile uint32_t *) (SPI_BASE(port) + 0x18) /* SPI TX CRC register */
+#define SPI_I2SCFGR(port)                   \
+    (volatile uint32_t *) (SPI_BASE(port) + \
+                           0x1c) /* SPI I2C configuration register */
+#define SPI_I2SPR(port)                     \
+    (volatile uint32_t *) (SPI_BASE(port) + \
+                           0x20) /* SPI I2C prescaler register */
 
 /* I2C */
-#define I2C_CR1(port)                   (volatile uint32_t *) (I2C_BASE(port) + 0x00)           /* I2C control register 1 */
-#define I2C_CR2(port)                   (volatile uint32_t *) (I2C_BASE(port) + 0x04)           /* I2C control register 2 */
-#define I2C_OAR1(port)                  (volatile uint32_t *) (I2C_BASE(port) + 0x08)           /* I2C own address register 1 */
-#define I2C_OAR2(port)                  (volatile uint32_t *) (I2C_BASE(port) + 0x0C)           /* I2C own address register 2 */
-#define I2C_DR(port)                    (volatile uint32_t *) (I2C_BASE(port) + 0x10)           /* I2C data register */
-#define I2C_SR1(port)                   (volatile uint32_t *) (I2C_BASE(port) + 0x14)           /* I2C status register 1 */
-#define I2C_SR2(port)                   (volatile uint32_t *) (I2C_BASE(port) + 0x18)           /* I2C status register 2 */
-#define I2C_CCR(port)                   (volatile uint32_t *) (I2C_BASE(port) + 0x1C)           /* I2C clock control register */
-#define I2C_TRISE(port)                 (volatile uint32_t *) (I2C_BASE(port) + 0x20)           /* I2C TRISE register */
+#define I2C_CR1(port) \
+    (volatile uint32_t *) (I2C_BASE(port) + 0x00) /* I2C control register 1 */
+#define I2C_CR2(port) \
+    (volatile uint32_t *) (I2C_BASE(port) + 0x04) /* I2C control register 2 */
+#define I2C_OAR1(port)                      \
+    (volatile uint32_t *) (I2C_BASE(port) + \
+                           0x08) /* I2C own address register 1 */
+#define I2C_OAR2(port)                      \
+    (volatile uint32_t *) (I2C_BASE(port) + \
+                           0x0C) /* I2C own address register 2 */
+#define I2C_DR(port) \
+    (volatile uint32_t *) (I2C_BASE(port) + 0x10) /* I2C data register */
+#define I2C_SR1(port) \
+    (volatile uint32_t *) (I2C_BASE(port) + 0x14) /* I2C status register 1 */
+#define I2C_SR2(port) \
+    (volatile uint32_t *) (I2C_BASE(port) + 0x18) /* I2C status register 2 */
+#define I2C_CCR(port)                       \
+    (volatile uint32_t *) (I2C_BASE(port) + \
+                           0x1C) /* I2C clock control register */
+#define I2C_TRISE(port) \
+    (volatile uint32_t *) (I2C_BASE(port) + 0x20) /* I2C TRISE register */
 
 /* USART 1 */
-#define USART1_SR                       (volatile uint32_t *) (USART1_BASE + 0x00)              /* USART1 status register */
-#define USART1_DR                       (volatile uint32_t *) (USART1_BASE + 0x04)              /* USART1 data register */
-#define USART1_BRR                      (volatile uint32_t *) (USART1_BASE + 0x08)              /* USART1 baud rate register */
-#define USART1_CR1                      (volatile uint32_t *) (USART1_BASE + 0x0C)              /* USART1 control register 1 */
-#define USART1_CR2                      (volatile uint32_t *) (USART1_BASE + 0x10)              /* USART1 control register 2 */
-#define USART1_CR3                      (volatile uint32_t *) (USART1_BASE + 0x14)              /* USART1 control register 3 */
-#define USART1_GTPR                     (volatile uint32_t *) (USART1_BASE + 0x18)              /* USART1 gaurd time and prescale register */
+#define USART1_SR \
+    (volatile uint32_t *) (USART1_BASE + 0x00) /* USART1 status register */
+#define USART1_DR \
+    (volatile uint32_t *) (USART1_BASE + 0x04) /* USART1 data register */
+#define USART1_BRR \
+    (volatile uint32_t *) (USART1_BASE + 0x08) /* USART1 baud rate register */
+#define USART1_CR1 \
+    (volatile uint32_t *) (USART1_BASE + 0x0C) /* USART1 control register 1 */
+#define USART1_CR2 \
+    (volatile uint32_t *) (USART1_BASE + 0x10) /* USART1 control register 2 */
+#define USART1_CR3 \
+    (volatile uint32_t *) (USART1_BASE + 0x14) /* USART1 control register 3 */
+#define USART1_GTPR                      \
+    (volatile uint32_t *) (USART1_BASE + \
+                           0x18) /* USART1 gaurd time and prescale register */
 
 /* GPIO Port (GPIO) */
-#define GPIO_MODER(port)                (volatile uint32_t *) (GPIO_BASE(port) + 0x00)          /* Port mode register */
-#define GPIO_OTYPER(port)               (volatile uint32_t *) (GPIO_BASE(port) + 0x04)          /* Port output type register */
-#define GPIO_OSPEEDR(port)              (volatile uint32_t *) (GPIO_BASE(port) + 0x08)          /* Port output speed register */
-#define GPIO_PUPDR(port)                (volatile uint32_t *) (GPIO_BASE(port) + 0x0C)          /* Port pull up/down register */
-#define GPIO_IDR(port)                  (volatile uint32_t *) (GPIO_BASE(port) + 0x10)          /* Port input data register */
-#define GPIO_ODR(port)                  (volatile uint32_t *) (GPIO_BASE(port) + 0x14)          /* Port output data register */
-#define GPIO_BSRR(port)                 (volatile uint32_t *) (GPIO_BASE(port) + 0x18)          /* Port bit set/reset register */
-#define GPIO_LCKR(port)                 (volatile uint32_t *) (GPIO_BASE(port) + 0x1C)          /* Port configuration lock register */
-#define GPIO_AFRL(port)                 (volatile uint32_t *) (GPIO_BASE(port) + 0x20)          /* Port alternate function low register */
-#define GPIO_AFRH(port)                 (volatile uint32_t *) (GPIO_BASE(port) + 0x24)          /* Port alternate function high register */
+#define GPIO_MODER(port) \
+    (volatile uint32_t *) (GPIO_BASE(port) + 0x00) /* Port mode register */
+#define GPIO_OTYPER(port)                    \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x04) /* Port output type register */
+#define GPIO_OSPEEDR(port)                   \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x08) /* Port output speed register */
+#define GPIO_PUPDR(port)                     \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x0C) /* Port pull up/down register */
+#define GPIO_IDR(port)                       \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x10) /* Port input data register */
+#define GPIO_ODR(port)                       \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x14) /* Port output data register */
+#define GPIO_BSRR(port)                      \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x18) /* Port bit set/reset register */
+#define GPIO_LCKR(port)                      \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x1C) /* Port configuration lock register */
+#define GPIO_AFRL(port)                      \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x20) /* Port alternate function low register */
+#define GPIO_AFRH(port)                      \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x24) /* Port alternate function high register */
 
 /* Reset and Clock Control (RCC) */
-#define RCC_CR                          (volatile uint32_t *) (RCC_BASE + 0x00)                 /* Clock Control Register */
-#define RCC_PLLCFGR                     (volatile uint32_t *) (RCC_BASE + 0x04)                 /* PLL Configuration Register */
-#define RCC_CFGR                        (volatile uint32_t *) (RCC_BASE + 0x08)                 /* Clock Configuration Register */
-#define RCC_CIR                         (volatile uint32_t *) (RCC_BASE + 0x0C)                 /* Clock Interrupt Register */
-#define RCC_AHB1RSTR                    (volatile uint32_t *) (RCC_BASE + 0x10)                 /* AHB1 reset Register */
-#define RCC_APB1RSTR                    (volatile uint32_t *) (RCC_BASE + 0x20)                 /* APB1 reset Register */
-#define RCC_APB2RSTR                    (volatile uint32_t *) (RCC_BASE + 0x24)                 /* APB2 reset Register */
-#define RCC_AHB1ENR                     (volatile uint32_t *) (RCC_BASE + 0x30)                 /* AHB1 Enable Register */
-#define RCC_AHB2ENR                     (volatile uint32_t *) (RCC_BASE + 0x34)                 /* AHB2 Enable Register */
-#define RCC_APB1ENR                     (volatile uint32_t *) (RCC_BASE + 0x40)                 /* APB1 Peripheral Clock Enable Register */
-#define RCC_APB2ENR                     (volatile uint32_t *) (RCC_BASE + 0x44)                 /* APB2 Peripheral Clock Enable Register */
-#define RCC_BDCR                        (volatile uint32_t *) (RCC_BASE + 0x70)                 /* RCC Backup Domain Control Register */
-#define RCC_CSR                         (volatile uint32_t *) (RCC_BASE + 0x74)                 /* RCC Clock Control & Status Register */
-#define RCC_PLLSAICFGR                  (volatile uint32_t *) (RCC_BASE + 0x88)                 /* RCC PLLSAI Configuration register */
-#define RCC_DCKCFGR                     (volatile uint32_t *) (RCC_BASE + 0x8C)                 /* RCC Dedicated Clocks Configuration register */
+#define RCC_CR \
+    (volatile uint32_t *) (RCC_BASE + 0x00) /* Clock Control Register */
+#define RCC_PLLCFGR \
+    (volatile uint32_t *) (RCC_BASE + 0x04) /* PLL Configuration Register */
+#define RCC_CFGR \
+    (volatile uint32_t *) (RCC_BASE + 0x08) /* Clock Configuration Register */
+#define RCC_CIR \
+    (volatile uint32_t *) (RCC_BASE + 0x0C) /* Clock Interrupt Register */
+#define RCC_AHB1RSTR \
+    (volatile uint32_t *) (RCC_BASE + 0x10) /* AHB1 reset Register */
+#define RCC_APB1RSTR \
+    (volatile uint32_t *) (RCC_BASE + 0x20) /* APB1 reset Register */
+#define RCC_APB2RSTR \
+    (volatile uint32_t *) (RCC_BASE + 0x24) /* APB2 reset Register */
+#define RCC_AHB1ENR \
+    (volatile uint32_t *) (RCC_BASE + 0x30) /* AHB1 Enable Register */
+#define RCC_AHB2ENR \
+    (volatile uint32_t *) (RCC_BASE + 0x34) /* AHB2 Enable Register */
+#define RCC_APB1ENR                   \
+    (volatile uint32_t *) (RCC_BASE + \
+                           0x40) /* APB1 Peripheral Clock Enable Register */
+#define RCC_APB2ENR                   \
+    (volatile uint32_t *) (RCC_BASE + \
+                           0x44) /* APB2 Peripheral Clock Enable Register */
+#define RCC_BDCR                      \
+    (volatile uint32_t *) (RCC_BASE + \
+                           0x70) /* RCC Backup Domain Control Register */
+#define RCC_CSR                       \
+    (volatile uint32_t *) (RCC_BASE + \
+                           0x74) /* RCC Clock Control & Status Register */
+#define RCC_PLLSAICFGR                \
+    (volatile uint32_t *) (RCC_BASE + \
+                           0x88) /* RCC PLLSAI Configuration register */
+#define RCC_DCKCFGR                                                 \
+    (volatile uint32_t *) (RCC_BASE + 0x8C) /* RCC Dedicated Clocks \
+                                               Configuration register */
 
 /* SYSCFG */
-#define SYSCFG_MEMRMP					(volatile uint32_t *)(SYSCFG_BASE + 0x0)				/* Memory remap register */
-#define SYSCFG_PMC						(volatile uint32_t *)(SYSCFG_BASE + 0x4)				/* Peripheral mode config register */
-#define SYSCFG_EXTICR1					(volatile uint32_t *)(SYSCFG_BASE + 0x8)				/* External INT config register1 */
-#define SYSCFG_EXTICR2					(volatile uint32_t *)(SYSCFG_BASE + 0xc)				/* External INT config register2 */
-#define SYSCFG_EXTICR3					(volatile uint32_t *)(SYSCFG_BASE + 0x10)				/* External INT config register3 */
-#define SYSCFG_EXTICR4					(volatile uint32_t *)(SYSCFG_BASE + 0x14)				/* External INT config register4 */
-#define SYSCFG_CMPCR					(volatile uint32_t *)(SYSCFG_BASE + 0x20)				/* Compensation cell control register*/
+#define SYSCFG_MEMRMP \
+    (volatile uint32_t *) (SYSCFG_BASE + 0x0) /* Memory remap register */
+#define SYSCFG_PMC                       \
+    (volatile uint32_t *) (SYSCFG_BASE + \
+                           0x4) /* Peripheral mode config register */
+#define SYSCFG_EXTICR1                   \
+    (volatile uint32_t *) (SYSCFG_BASE + \
+                           0x8) /* External INT config register1 */
+#define SYSCFG_EXTICR2                   \
+    (volatile uint32_t *) (SYSCFG_BASE + \
+                           0xc) /* External INT config register2 */
+#define SYSCFG_EXTICR3                   \
+    (volatile uint32_t *) (SYSCFG_BASE + \
+                           0x10) /* External INT config register3 */
+#define SYSCFG_EXTICR4                   \
+    (volatile uint32_t *) (SYSCFG_BASE + \
+                           0x14) /* External INT config register4 */
+#define SYSCFG_CMPCR                     \
+    (volatile uint32_t *) (SYSCFG_BASE + \
+                           0x20) /* Compensation cell control register*/
 
 
 
 /* APB1 RCC ENR */
-#define RCC_TIM2_APBENR					RCC_APB1ENR
-#define RCC_TIM3_APBENR					RCC_APB1ENR
-#define RCC_TIM4_APBENR					RCC_APB1ENR
-#define RCC_TIM5_APBENR					RCC_APB1ENR
-#define RCC_TIM6_APBENR					RCC_APB1ENR
-#define RCC_TIM7_APBENR					RCC_APB1ENR
-#define RCC_TIM12_APBENR				RCC_APB1ENR
-#define RCC_TIM13_APBENR				RCC_APB1ENR
-#define RCC_TIM14_APBENR				RCC_APB1ENR
-#define RCC_WWDG_APBENR					RCC_APB1ENR
-#define RCC_SPI2_APBENR					RCC_APB1ENR
-#define RCC_SPI3_APBENR					RCC_APB1ENR
-#define RCC_USART2_APBENR				RCC_APB1ENR
-#define RCC_USART3_APBENR				RCC_APB1ENR
-#define RCC_UART4_APBENR				RCC_APB1ENR
-#define RCC_UART5_APBENR				RCC_APB1ENR
-#define RCC_I2C1_APBENR					RCC_APB1ENR
-#define RCC_I2C2_APBENR					RCC_APB1ENR
-#define RCC_I2C3_APBENR					RCC_APB1ENR
-#define RCC_CAN1_APBENR					RCC_APB1ENR
-#define RCC_CAN2_APBENR					RCC_APB1ENR
-#define RCC_PWR_APBENR					RCC_APB1ENR
-#define RCC_DAC_APBENR					RCC_APB1ENR
+#define RCC_TIM2_APBENR RCC_APB1ENR
+#define RCC_TIM3_APBENR RCC_APB1ENR
+#define RCC_TIM4_APBENR RCC_APB1ENR
+#define RCC_TIM5_APBENR RCC_APB1ENR
+#define RCC_TIM6_APBENR RCC_APB1ENR
+#define RCC_TIM7_APBENR RCC_APB1ENR
+#define RCC_TIM12_APBENR RCC_APB1ENR
+#define RCC_TIM13_APBENR RCC_APB1ENR
+#define RCC_TIM14_APBENR RCC_APB1ENR
+#define RCC_WWDG_APBENR RCC_APB1ENR
+#define RCC_SPI2_APBENR RCC_APB1ENR
+#define RCC_SPI3_APBENR RCC_APB1ENR
+#define RCC_USART2_APBENR RCC_APB1ENR
+#define RCC_USART3_APBENR RCC_APB1ENR
+#define RCC_UART4_APBENR RCC_APB1ENR
+#define RCC_UART5_APBENR RCC_APB1ENR
+#define RCC_I2C1_APBENR RCC_APB1ENR
+#define RCC_I2C2_APBENR RCC_APB1ENR
+#define RCC_I2C3_APBENR RCC_APB1ENR
+#define RCC_CAN1_APBENR RCC_APB1ENR
+#define RCC_CAN2_APBENR RCC_APB1ENR
+#define RCC_PWR_APBENR RCC_APB1ENR
+#define RCC_DAC_APBENR RCC_APB1ENR
 
 /* APB2 RCC ENR */
-#define RCC_TIM1_APBENR					RCC_APB2ENR
-#define RCC_TIM8_APBENR					RCC_APB2ENR
-#define RCC_USART1_APBENR				RCC_APB2ENR
-#define RCC_USART6_APBENR				RCC_APB2ENR
-#define RCC_ADC1_APBENR					RCC_APB2ENR
-#define RCC_ADC2_APBENR					RCC_APB2ENR
-#define RCC_ADC3_APBENR					RCC_APB2ENR
-#define RCC_SDIO_APBENR					RCC_APB2ENR
-#define RCC_SPI1_APBENR					RCC_APB2ENR
-#define RCC_SYSCFG_APBENR				RCC_APB2ENR
-#define RCC_TIM9_APBENR					RCC_APB2ENR
-#define RCC_TIM10_APBENR				RCC_APB2ENR
-#define RCC_TIM11_APBENR				RCC_APB2ENR
+#define RCC_TIM1_APBENR RCC_APB2ENR
+#define RCC_TIM8_APBENR RCC_APB2ENR
+#define RCC_USART1_APBENR RCC_APB2ENR
+#define RCC_USART6_APBENR RCC_APB2ENR
+#define RCC_ADC1_APBENR RCC_APB2ENR
+#define RCC_ADC2_APBENR RCC_APB2ENR
+#define RCC_ADC3_APBENR RCC_APB2ENR
+#define RCC_SDIO_APBENR RCC_APB2ENR
+#define RCC_SPI1_APBENR RCC_APB2ENR
+#define RCC_SYSCFG_APBENR RCC_APB2ENR
+#define RCC_TIM9_APBENR RCC_APB2ENR
+#define RCC_TIM10_APBENR RCC_APB2ENR
+#define RCC_TIM11_APBENR RCC_APB2ENR
 
 /* Flash Registers (FLASH) */
-#define FLASH_ACR                       (volatile uint32_t *) (FLASH_R_BASE + 0x00)             /* Flash Access Control Register */
+#define FLASH_ACR                         \
+    (volatile uint32_t *) (FLASH_R_BASE + \
+                           0x00) /* Flash Access Control Register */
 
 /* Direct Memory Access 1 (DMA) */
-#define DMA1_LISR                       (volatile uint32_t *) (DMA1_BASE + 0x00)                /* DMA1 low interrupt status register */
-#define DMA1_HISR                       (volatile uint32_t *) (DMA1_BASE + 0x04)                /* DMA1 high interrupt status register */
-#define DMA1_LIFCR                      (volatile uint32_t *) (DMA1_BASE + 0x08)                /* DMA1 low interrupt flag clear register */
-#define DMA1_HIFCR                      (volatile uint32_t *) (DMA1_BASE + 0x0C)                /* DMA1 high interrupt flag clear register */
+#define DMA1_LISR                      \
+    (volatile uint32_t *) (DMA1_BASE + \
+                           0x00) /* DMA1 low interrupt status register */
+#define DMA1_HISR                      \
+    (volatile uint32_t *) (DMA1_BASE + \
+                           0x04) /* DMA1 high interrupt status register */
+#define DMA1_LIFCR                     \
+    (volatile uint32_t *) (DMA1_BASE + \
+                           0x08) /* DMA1 low interrupt flag clear register */
+#define DMA1_HIFCR                     \
+    (volatile uint32_t *) (DMA1_BASE + \
+                           0x0C) /* DMA1 high interrupt flag clear register */
 /* Stream n */
-#define DMA1_CR_S(n)                    (volatile uint32_t *) (DMA1_BASE + 0x10 + (0x18*n))     /* DMA1 stream n configuration register */
-#define DMA1_NDTR_S(n)                  (volatile uint32_t *) (DMA1_BASE + 0x14 + (0x18*n))     /* DMA1 stream n number of data register */
-#define DMA1_PAR_S(n)                   (volatile uint32_t *) (DMA1_BASE + 0x18 + (0x18*n))     /* DMA1 stream n peripheral address register */
-#define DMA1_M0AR_S(n)                  (volatile uint32_t *) (DMA1_BASE + 0x1C + (0x18*n))     /* DMA1 stream n memory 0 address register */
-#define DMA1_M1AR_S(n)                  (volatile uint32_t *) (DMA1_BASE + 0x20 + (0x18*n))     /* DMA1 stream n memory 1 address register */
-#define DMA1_FCR_S(n)                   (volatile uint32_t *) (DMA1_BASE + 0x24 + (0x18*n))     /* DMA1 stream n FIFO control register */
+#define DMA1_CR_S(n)                          \
+    (volatile uint32_t *) (DMA1_BASE + 0x10 + \
+                           (0x18 *            \
+                            n)) /* DMA1 stream n configuration register */
+#define DMA1_NDTR_S(n)                        \
+    (volatile uint32_t *) (DMA1_BASE + 0x14 + \
+                           (0x18 *            \
+                            n)) /* DMA1 stream n number of data register */
+#define DMA1_PAR_S(n)           \
+    (volatile uint32_t          \
+         *) (DMA1_BASE + 0x18 + \
+             (0x18 * n)) /* DMA1 stream n peripheral address register */
+#define DMA1_M0AR_S(n)                        \
+    (volatile uint32_t *) (DMA1_BASE + 0x1C + \
+                           (0x18 *            \
+                            n)) /* DMA1 stream n memory 0 address register */
+#define DMA1_M1AR_S(n)                        \
+    (volatile uint32_t *) (DMA1_BASE + 0x20 + \
+                           (0x18 *            \
+                            n)) /* DMA1 stream n memory 1 address register */
+#define DMA1_FCR_S(n)                         \
+    (volatile uint32_t *) (DMA1_BASE + 0x24 + \
+                           (0x18 *            \
+                            n)) /* DMA1 stream n FIFO control register */
 
 /* Direct Memory Access 2 (DMA) */
-#define DMA2_LISR                       (volatile uint32_t *) (DMA2_BASE + 0x00)                /* DMA2 low interrupt status register */
-#define DMA2_HISR                       (volatile uint32_t *) (DMA2_BASE + 0x04)                /* DMA2 high interrupt status register */
-#define DMA2_LIFCR                      (volatile uint32_t *) (DMA2_BASE + 0x08)                /* DMA2 low interrupt flag clear register */
-#define DMA2_HIFCR                      (volatile uint32_t *) (DMA2_BASE + 0x0C)                /* DMA2 high interrupt flag clear register */
+#define DMA2_LISR                      \
+    (volatile uint32_t *) (DMA2_BASE + \
+                           0x00) /* DMA2 low interrupt status register */
+#define DMA2_HISR                      \
+    (volatile uint32_t *) (DMA2_BASE + \
+                           0x04) /* DMA2 high interrupt status register */
+#define DMA2_LIFCR                     \
+    (volatile uint32_t *) (DMA2_BASE + \
+                           0x08) /* DMA2 low interrupt flag clear register */
+#define DMA2_HIFCR                     \
+    (volatile uint32_t *) (DMA2_BASE + \
+                           0x0C) /* DMA2 high interrupt flag clear register */
 /* Stream n */
-#define DMA2_CR_S(n)                    (volatile uint32_t *) (DMA2_BASE + 0x10 + (0x18*n))     /* DMA2 stream n configuration register */
-#define DMA2_NDTR_S(n)                  (volatile uint32_t *) (DMA2_BASE + 0x14 + (0x18*n))     /* DMA2 stream n number of data register */
-#define DMA2_PAR_S(n)                   (volatile uint32_t *) (DMA2_BASE + 0x18 + (0x18*n))     /* DMA2 stream n peripheral address register */
-#define DMA2_M0AR_S(n)                  (volatile uint32_t *) (DMA2_BASE + 0x1C + (0x18*n))     /* DMA2 stream n memory 0 address register */
-#define DMA2_M1AR_S(n)                  (volatile uint32_t *) (DMA2_BASE + 0x20 + (0x18*n))     /* DMA2 stream n memory 1 address register */
-#define DMA2_FCR_S(n)                   (volatile uint32_t *) (DMA2_BASE + 0x24 + (0x18*n))     /* DMA2 stream n FIFO control register */
+#define DMA2_CR_S(n)                          \
+    (volatile uint32_t *) (DMA2_BASE + 0x10 + \
+                           (0x18 *            \
+                            n)) /* DMA2 stream n configuration register */
+#define DMA2_NDTR_S(n)                        \
+    (volatile uint32_t *) (DMA2_BASE + 0x14 + \
+                           (0x18 *            \
+                            n)) /* DMA2 stream n number of data register */
+#define DMA2_PAR_S(n)           \
+    (volatile uint32_t          \
+         *) (DMA2_BASE + 0x18 + \
+             (0x18 * n)) /* DMA2 stream n peripheral address register */
+#define DMA2_M0AR_S(n)                        \
+    (volatile uint32_t *) (DMA2_BASE + 0x1C + \
+                           (0x18 *            \
+                            n)) /* DMA2 stream n memory 0 address register */
+#define DMA2_M1AR_S(n)                        \
+    (volatile uint32_t *) (DMA2_BASE + 0x20 + \
+                           (0x18 *            \
+                            n)) /* DMA2 stream n memory 1 address register */
+#define DMA2_FCR_S(n)                         \
+    (volatile uint32_t *) (DMA2_BASE + 0x24 + \
+                           (0x18 *            \
+                            n)) /* DMA2 stream n FIFO control register */
 
 /* USB OTG Full-Speed */
 /* Global Control and Status Registers */
-#define USB_FS_GOTGCTL                  (volatile uint32_t *) (USB_FS_BASE + 0x0000)            /* USB control and status register */
-#define USB_FS_GOTGINT                  (volatile uint32_t *) (USB_FS_BASE + 0x0004)            /* USB interrupt register */
-#define USB_FS_GAHBCFG                  (volatile uint32_t *) (USB_FS_BASE + 0x0008)            /* USB AHB configuration register */
-#define USB_FS_GUSBCFG                  (volatile uint32_t *) (USB_FS_BASE + 0x000C)            /* USB USB configuration register */
-#define USB_FS_GRSTCTL                  (volatile uint32_t *) (USB_FS_BASE + 0x0010)            /* USB reset control register */
-#define USB_FS_GINTSTS                  (volatile uint32_t *) (USB_FS_BASE + 0x0014)            /* USB core interrupt register */
-#define USB_FS_GINTMSK                  (volatile uint32_t *) (USB_FS_BASE + 0x0018)            /* USB interrupt mask register */
-#define USB_FS_GRXSTSR                  (volatile uint32_t *) (USB_FS_BASE + 0x001C)            /* USB receive status debug read register */
-#define USB_FS_GRXSTSP                  (volatile uint32_t *) (USB_FS_BASE + 0x0020)            /* USB receive status debug read and pop register */
-#define USB_FS_GRXFSIZ                  (volatile uint32_t *) (USB_FS_BASE + 0x0024)            /* USB receive FIFO size register */
-#define USB_FS_DIEPTXF0                 (volatile uint32_t *) (USB_FS_BASE + 0x0028)            /* USB endpoint 0 transmit FIFO size register */
-#define USB_FS_HNPTXFSIZ                (volatile uint32_t *) (USB_FS_BASE + 0x0028)            /* USB host non-periodic transmit FIFO size register */
-#define USB_FS_HNPTXSTS                 (volatile uint32_t *) (USB_FS_BASE + 0x002C)            /* USB host non-periodic transmit FIFO/queue status register */
-#define USB_FS_GCCFG                    (volatile uint32_t *) (USB_FS_BASE + 0x0038)            /* USB general core configuration register */
-#define USB_FS_CID                      (volatile uint32_t *) (USB_FS_BASE + 0x003C)            /* USB core ID register */
-#define USB_FS_HPTXFSIZ                 (volatile uint32_t *) (USB_FS_BASE + 0x0100)            /* USB host periodic transmit FIFO size register */
-#define USB_FS_DIEPTXF1                 (volatile uint32_t *) (USB_FS_BASE + 0x0104)            /* USB device IN endpoint transmit FIFO size register 1 */
-#define USB_FS_DIEPTXF2                 (volatile uint32_t *) (USB_FS_BASE + 0x0108)            /* USB device IN endpoint transmit FIFO size register 2 */
-#define USB_FS_DIEPTXF3                 (volatile uint32_t *) (USB_FS_BASE + 0x010C)            /* USB device IN endpoint transmit FIFO size register 3 */
+#define USB_FS_GOTGCTL                   \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x0000) /* USB control and status register */
+#define USB_FS_GOTGINT \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0004) /* USB interrupt register */
+#define USB_FS_GAHBCFG                   \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x0008) /* USB AHB configuration register */
+#define USB_FS_GUSBCFG                   \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x000C) /* USB USB configuration register */
+#define USB_FS_GRSTCTL                   \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x0010) /* USB reset control register */
+#define USB_FS_GINTSTS                   \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x0014) /* USB core interrupt register */
+#define USB_FS_GINTMSK                   \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x0018) /* USB interrupt mask register */
+#define USB_FS_GRXSTSR                                                       \
+    (volatile uint32_t *) (USB_FS_BASE + 0x001C) /* USB receive status debug \
+                                                    read register */
+#define USB_FS_GRXSTSP                                                       \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0020) /* USB receive status debug \
+                                                    read and pop register */
+#define USB_FS_GRXFSIZ                   \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x0024) /* USB receive FIFO size register */
+#define USB_FS_DIEPTXF0                                                     \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0028) /* USB endpoint 0 transmit \
+                                                    FIFO size register */
+#define USB_FS_HNPTXFSIZ   \
+    (volatile uint32_t     \
+         *) (USB_FS_BASE + \
+             0x0028) /* USB host non-periodic transmit FIFO size register */
+#define USB_FS_HNPTXSTS                                              \
+    (volatile uint32_t *) (USB_FS_BASE +                             \
+                           0x002C) /* USB host non-periodic transmit \
+                                      FIFO/queue status register */
+#define USB_FS_GCCFG                                                 \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0038) /* USB general core \
+                                                    configuration register */
+#define USB_FS_CID \
+    (volatile uint32_t *) (USB_FS_BASE + 0x003C) /* USB core ID register */
+#define USB_FS_HPTXFSIZ                                                        \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0100) /* USB host periodic transmit \
+                                                    FIFO size register */
+#define USB_FS_DIEPTXF1                                                    \
+    (volatile uint32_t *) (USB_FS_BASE +                                   \
+                           0x0104) /* USB device IN endpoint transmit FIFO \
+                                      size register 1 */
+#define USB_FS_DIEPTXF2                                                    \
+    (volatile uint32_t *) (USB_FS_BASE +                                   \
+                           0x0108) /* USB device IN endpoint transmit FIFO \
+                                      size register 2 */
+#define USB_FS_DIEPTXF3                                                    \
+    (volatile uint32_t *) (USB_FS_BASE +                                   \
+                           0x010C) /* USB device IN endpoint transmit FIFO \
+                                      size register 3 */
 
 /* Host-mode Registers */
 /* ... */
 
 /* Device-mode Registers */
-#define USB_FS_DCFG                     (volatile uint32_t *) (USB_FS_BASE + 0x0800)            /* USB device configuration register */
-#define USB_FS_DCTL                     (volatile uint32_t *) (USB_FS_BASE + 0x0804)            /* USB device control register */
-#define USB_FS_DSTS                     (volatile uint32_t *) (USB_FS_BASE + 0x0808)            /* USB device status register */
-#define USB_FS_DSTS                     (volatile uint32_t *) (USB_FS_BASE + 0x0808)            /* USB device status register */
-#define USB_FS_DIEPMSK                  (volatile uint32_t *) (USB_FS_BASE + 0x0810)            /* USB device IN endpoint common interrupt mask register */
-#define USB_FS_DOEPMSK                  (volatile uint32_t *) (USB_FS_BASE + 0x0814)            /* USB device OUT endpoint common interrupt mask register */
-#define USB_FS_DAINT                    (volatile uint32_t *) (USB_FS_BASE + 0x0818)            /* USB device all endpoints interrupt register */
-#define USB_FS_DAINTMSK                 (volatile uint32_t *) (USB_FS_BASE + 0x081C)            /* USB device all endpoints interrupt mask register */
-#define USB_FS_DVBUSDIS                 (volatile uint32_t *) (USB_FS_BASE + 0x0828)            /* USB device VBUS discharge time register */
-#define USB_FS_DVBUSPULSE               (volatile uint32_t *) (USB_FS_BASE + 0x082C)            /* USB device VBUS pulse time register */
-#define USB_FS_DIEPEMPMSK               (volatile uint32_t *) (USB_FS_BASE + 0x0834)            /* USB device IN endpoint FIFO empty interrupt mask register */
-#define USB_FS_DIEPCTL0                 (volatile uint32_t *) (USB_FS_BASE + 0x0900)            /* USB device IN endpoint 0 control register */
-#define USB_FS_DIEPCTL(n)               (volatile uint32_t *) (USB_FS_BASE + 0x0900 + n*0x20)   /* USB device endpoint n control register */
-#define USB_FS_DIEPINT(n)               (volatile uint32_t *) (USB_FS_BASE + 0x0908 + n*0x20)   /* USB device endpoint n interrupt register */
-#define USB_FS_DIEPTSIZ0                (volatile uint32_t *) (USB_FS_BASE + 0x0910)            /* USB device IN endpoint 0 transfer size register */
-#define USB_FS_DIEPTSIZ(n)              (volatile uint32_t *) (USB_FS_BASE + 0x0910 + n*0x20)   /* USB device OUT endpoint n transfer size register */
-#define USB_FS_DTXFSTS(n)               (volatile uint32_t *) (USB_FS_BASE + 0x0918 + n*0x20)   /* USB device IN endpoint n FIFO status register */
-#define USB_FS_DOEPCTL0                 (volatile uint32_t *) (USB_FS_BASE + 0x0B00)            /* USB device OUT endpoint 0 control register */
-#define USB_FS_DOEPCTL(n)               (volatile uint32_t *) (USB_FS_BASE + 0x0B00 + n*0x20)   /* USB device endpoint n control register */
-#define USB_FS_DOEPINT(n)               (volatile uint32_t *) (USB_FS_BASE + 0x0B08 + n*0x20)   /* USB device endpoint 1 interrupt register */
-#define USB_FS_DOEPTSIZ0                (volatile uint32_t *) (USB_FS_BASE + 0x0B10)            /* USB device OUT endpoint 0 transfer size register */
-#define USB_FS_DOEPTSIZ(n)              (volatile uint32_t *) (USB_FS_BASE + 0x0B10 + n*0x20)   /* USB device OUT endpoint n transfer size register */
+#define USB_FS_DCFG                      \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x0800) /* USB device configuration register */
+#define USB_FS_DCTL                      \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x0804) /* USB device control register */
+#define USB_FS_DSTS                      \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x0808) /* USB device status register */
+#define USB_FS_DSTS                      \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x0808) /* USB device status register */
+#define USB_FS_DIEPMSK                                                        \
+    (volatile uint32_t *) (USB_FS_BASE +                                      \
+                           0x0810) /* USB device IN endpoint common interrupt \
+                                      mask register */
+#define USB_FS_DOEPMSK                                                         \
+    (volatile uint32_t *) (USB_FS_BASE +                                       \
+                           0x0814) /* USB device OUT endpoint common interrupt \
+                                      mask register */
+#define USB_FS_DAINT                                                         \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0818) /* USB device all endpoints \
+                                                    interrupt register */
+#define USB_FS_DAINTMSK                                                      \
+    (volatile uint32_t *) (USB_FS_BASE + 0x081C) /* USB device all endpoints \
+                                                    interrupt mask register */
+#define USB_FS_DVBUSDIS                                                       \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0828) /* USB device VBUS discharge \
+                                                    time register */
+#define USB_FS_DVBUSPULSE                \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x082C) /* USB device VBUS pulse time register */
+#define USB_FS_DIEPEMPMSK                                               \
+    (volatile uint32_t *) (USB_FS_BASE +                                \
+                           0x0834) /* USB device IN endpoint FIFO empty \
+                                      interrupt mask register */
+#define USB_FS_DIEPCTL0                                                      \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0900) /* USB device IN endpoint 0 \
+                                                    control register */
+#define USB_FS_DIEPCTL(n)           \
+    (volatile uint32_t              \
+         *) (USB_FS_BASE + 0x0900 + \
+             n * 0x20) /* USB device endpoint n control register */
+#define USB_FS_DIEPINT(n)           \
+    (volatile uint32_t              \
+         *) (USB_FS_BASE + 0x0908 + \
+             n * 0x20) /* USB device endpoint n interrupt register */
+#define USB_FS_DIEPTSIZ0                                                     \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0910) /* USB device IN endpoint 0 \
+                                                    transfer size register */
+#define USB_FS_DIEPTSIZ(n)          \
+    (volatile uint32_t              \
+         *) (USB_FS_BASE + 0x0910 + \
+             n * 0x20) /* USB device OUT endpoint n transfer size register */
+#define USB_FS_DTXFSTS(n)           \
+    (volatile uint32_t              \
+         *) (USB_FS_BASE + 0x0918 + \
+             n * 0x20) /* USB device IN endpoint n FIFO status register */
+#define USB_FS_DOEPCTL0                                                       \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0B00) /* USB device OUT endpoint 0 \
+                                                    control register */
+#define USB_FS_DOEPCTL(n)           \
+    (volatile uint32_t              \
+         *) (USB_FS_BASE + 0x0B00 + \
+             n * 0x20) /* USB device endpoint n control register */
+#define USB_FS_DOEPINT(n)           \
+    (volatile uint32_t              \
+         *) (USB_FS_BASE + 0x0B08 + \
+             n * 0x20) /* USB device endpoint 1 interrupt register */
+#define USB_FS_DOEPTSIZ0                                                      \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0B10) /* USB device OUT endpoint 0 \
+                                                    transfer size register */
+#define USB_FS_DOEPTSIZ(n)          \
+    (volatile uint32_t              \
+         *) (USB_FS_BASE + 0x0B10 + \
+             n * 0x20) /* USB device OUT endpoint n transfer size register */
 
 /* Data FIFO Registers */
-#define USB_FS_DFIFO_EP(n)              (volatile uint32_t *) (USB_FS_BASE + 0x1000 + n*0x1000) /* USB endpoint n data FIFO base address */
+#define USB_FS_DFIFO_EP(n)          \
+    (volatile uint32_t              \
+         *) (USB_FS_BASE + 0x1000 + \
+             n * 0x1000) /* USB endpoint n data FIFO base address */
 
 /* Power and Clock Gating Registers */
-#define USB_FS_PCGCR                    (volatile uint32_t *) (USB_FS_BASE + 0x0E00)            /* USB power and clock gating control register */
+#define USB_FS_PCGCR                                                           \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0E00) /* USB power and clock gating \
+                                                    control register */
 
 
 /**********************************************************************************************************************************************/
 
 /* Bit Masks - See RM0090 Reference Manual for STM32F4 for details */
-#define PWR_CR_VOS                      (uint16_t) (1 << 14)                                    /* Regulator voltage scaling output selection */
-
-#define HSI_VALUE                       (uint32_t) (16000000)                                   /* HSI value in Hz */
-#define HSE_VALUE                       (uint32_t) (1 << 27)                                    /* HSE value in Hz */
-
-#define RCC_CR_HSION                    (uint32_t) (1 << 0)                                     /* HSI clock enable */
-#define RCC_CR_HSIRDY                   (uint32_t) (1 << 1)                                     /* HSI ready */
-#define RCC_CR_HSITRIM_M                (uint32_t) (0x1F << 3)                                  /* HSI trimming mask */
-#define RCC_CR_HSITRIM(n)               (uint32_t) (n << 3)                                     /* HSI trimming */
-#define RCC_CR_HSICAL_M                 (uint32_t) (0xFF << 8)                                  /* HSI calibration mask */
-#define RCC_CR_HSEON                    (uint32_t) (1 << 16)                                    /* HSE clock enable */
-#define RCC_CR_HSERDY                   (uint32_t) (1 << 17)                                    /* HSE ready */
-#define RCC_CR_HSEBYP                   (uint32_t) (1 << 18)                                    /* HSE bypass */
-#define RCC_CR_CSSON                    (uint32_t) (1 << 19)                                    /* Clock security system enable */
-#define RCC_CR_PLLON                    (uint32_t) (1 << 24)                                    /* Main PLL enable */
-#define RCC_CR_PLLRDY                   (uint32_t) (1 << 25)                                    /* Main PLL clock ready */
-#define RCC_CR_PLLI2SON                 (uint32_t) (1 << 26)                                    /* PLLI2S enable */
-#define RCC_CR_PLLI2SRDY                (uint32_t) (1 << 27)                                    /* PLLI2S clock ready */
-
-#define RCC_PLLCFGR_RESET               (uint32_t) (0x24003010)                                 /* PLLCFGR register reset value */
-#define RCC_PLLCFGR_PLLSRC_HSE          (uint32_t) (1 << 22)                                    /* HSE oscillator selected as clock entry */
-#define RCC_PLLCFGR_PLLM                (uint32_t) (0x003F)
-#define RCC_PLLCFGR_PLLN                (uint32_t) (0x7FC0)
-#define RCC_PLLCFGR_PLLP                (uint32_t) (0x00030000)
-
-#define RCC_CFGR_SW_M                   (uint32_t) (3 << 0)                                     /* System clock switch mask */
-#define RCC_CFGR_SW_HSI                 (uint32_t) (0 << 0)                                     /* System clock switch - HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                 (uint32_t) (1 << 0)                                     /* System clock switch - HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                 (uint32_t) (2 << 0)                                     /* System clock switch - PLL selected as system clock */
-#define RCC_CFGR_SWS_M                  (uint32_t) (3 << 2)                                     /* System clock switch status mask */
-#define RCC_CFGR_SWS_HSI                (uint32_t) (0 << 2)                                     /* System clock switch status - HSI used as system clock */
-#define RCC_CFGR_SWS_HSE                (uint32_t) (1 << 2)                                     /* System clock switch status - HSE used as system clock */
-#define RCC_CFGR_SWS_PLL                (uint32_t) (2 << 2)                                     /* System clock switch status - PLL used as system clock */
-#define RCC_CFGR_HPRE_M                 (uint32_t) (0xF << 4)                                   /* AHB prescaler mask */
-#define RCC_CFGR_HPRE_DIV1              (uint32_t) (0x0 << 4)                                   /* AHB prescaler - SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2              (uint32_t) (0x8 << 4)                                   /* AHB prescaler - SYSCLK/2 */
-#define RCC_CFGR_HPRE_DIV4              (uint32_t) (0x9 << 4)                                   /* AHB prescaler - SYSCLK/4 */
-#define RCC_CFGR_HPRE_DIV8              (uint32_t) (0xA << 4)                                   /* AHB prescaler - SYSCLK/8 */
-#define RCC_CFGR_HPRE_DIV16             (uint32_t) (0xB << 4)                                   /* AHB prescaler - SYSCLK/16 */
-#define RCC_CFGR_HPRE_DIV64             (uint32_t) (0xC << 4)                                   /* AHB prescaler - SYSCLK/64 */
-#define RCC_CFGR_HPRE_DIV128            (uint32_t) (0xD << 4)                                   /* AHB prescaler - SYSCLK/128 */
-#define RCC_CFGR_HPRE_DIV256            (uint32_t) (0xE << 4)                                   /* AHB prescaler - SYSCLK/256 */
-#define RCC_CFGR_HPRE_DIV512            (uint32_t) (0xF << 4)                                   /* AHB prescaler - SYSCLK/512 */
-#define RCC_CFGR_PPRE1_M                (uint32_t) (7 << 10)                                    /* APB low speed prescaler mask */
-#define RCC_CFGR_PPRE1_DIV1             (uint32_t) (0 << 10)                                    /* APB low speed prescaler - HCLK/1 */
-#define RCC_CFGR_PPRE1_DIV2             (uint32_t) (4 << 10)                                    /* APB low speed prescaler - HCLK/2 */
-#define RCC_CFGR_PPRE1_DIV4             (uint32_t) (5 << 10)                                    /* APB low speed prescaler - HCLK/4 */
-#define RCC_CFGR_PPRE1_DIV8             (uint32_t) (6 << 10)                                    /* APB low speed prescaler - HCLK/8 */
-#define RCC_CFGR_PPRE1_DIV16            (uint32_t) (7 << 10)                                    /* APB low speed prescaler - HCLK/16 */
-#define RCC_CFGR_PPRE2_M                (uint32_t) (7 << 13)                                    /* APB high speec prescaler mask */
-#define RCC_CFGR_PPRE2_DIV1             (uint32_t) (0 << 13)                                    /* APB high speed prescaler - HCLK/1 */
-#define RCC_CFGR_PPRE2_DIV2             (uint32_t) (4 << 13)                                    /* APB high speed prescaler - HCLK/2 */
-#define RCC_CFGR_PPRE2_DIV4             (uint32_t) (5 << 13)                                    /* APB high speed prescaler - HCLK/4 */
-#define RCC_CFGR_PPRE2_DIV8             (uint32_t) (6 << 13)                                    /* APB high speed prescaler - HCLK/8 */
-#define RCC_CFGR_PPRE2_DIV16            (uint32_t) (7 << 13)                                    /* APB high speed prescaler - HCLK/16 */
-#define RCC_CFGR_RTCPRE_M               (uint32_t) (0x1F << 16)                                 /* HSE division factor for RTC clock mask */
-#define RCC_CFGR_RTCPRE(n)              (uint32_t) (n << 16)                                    /* HSE division factor for RTC clock */
-
-#define RCC_AHB1RSTR_GPIOARST           (uint32_t) (1 << 0)                                     /* GPIOA reset */
-#define RCC_AHB1RSTR_GPIOBRST           (uint32_t) (1 << 1)                                     /* GPIOB reset */
-#define RCC_AHB1RSTR_GPIOCRST           (uint32_t) (1 << 2)                                     /* GPIOC reset */
-#define RCC_AHB1RSTR_GPIODRST           (uint32_t) (1 << 3)                                     /* GPIOD reset */
-#define RCC_AHB1RSTR_GPIOERST           (uint32_t) (1 << 4)                                     /* GPIOE reset */
-#define RCC_AHB1RSTR_GPIOFRST           (uint32_t) (1 << 5)                                     /* GPIOF reset */
-#define RCC_AHB1RSTR_GPIOGRST           (uint32_t) (1 << 6)                                     /* GPIOG reset */
-#define RCC_AHB1RSTR_GPIOHRST           (uint32_t) (1 << 7)                                     /* GPIOH reset */
-#define RCC_AHB1RSTR_GPIOIRST           (uint32_t) (1 << 8)                                     /* GPIOI reset */
-#define RCC_AHB1RSTR_CRCRST             (uint32_t) (1 << 12)                                    /* CRC reset */
-#define RCC_AHB1RSTR_DMA1RST            (uint32_t) (1 << 21)                                    /* DMA1 reset */
-#define RCC_AHB1RSTR_DMA2RST            (uint32_t) (1 << 22)                                    /* DMA2 reset */
-#define RCC_AHB1RSTR_ETHMACRST          (uint32_t) (1 << 25)                                    /* Ethernet MAC reset */
-#define RCC_AHB1RSTR_OTGHSRST           (uint32_t) (1 << 29)                                    /* USB OTG HS reset */
-
-#define RCC_AHB2RSTR_DCMIRST            (uint32_t) (1 << 0)                                     /* Camera interface reset */
-#define RCC_AHB2RSTR_CRYPRST            (uint32_t) (1 << 4)                                     /* Cyrpto modules reset */
-#define RCC_AHB2RSTR_HASHRST            (uint32_t) (1 << 5)                                     /* Hash modules reset */
-#define RCC_AHB2RSTR_RNGRST             (uint32_t) (1 << 6)                                     /* Random number generator reset */
-#define RCC_AHB2RSTR_OTGFSRST           (uint32_t) (1 << 7)                                     /* USB OTG FS reset */
-
-#define RCC_AHB3RSTR_FSMCRST            (uint32_t) (1 << 0)                                     /* Flexible static memeory controller reset */
-
-#define RCC_APB1RSTR_TIM2RST            (uint32_t) (1 << 0)                                     /* TIM2 reset */
-#define RCC_APB1RSTR_TIM3RST            (uint32_t) (1 << 1)                                     /* TIM3 reset */
-#define RCC_APB1RSTR_TIM4RST            (uint32_t) (1 << 2)                                     /* TIM4 reset */
-#define RCC_APB1RSTR_TIM5RST            (uint32_t) (1 << 3)                                     /* TIM5 reset */
-#define RCC_APB1RSTR_TIM6RST            (uint32_t) (1 << 4)                                     /* TIM6 reset */
-#define RCC_APB1RSTR_TIM7RST            (uint32_t) (1 << 5)                                     /* TIM7 reset */
-#define RCC_APB1RSTR_TIM12RST           (uint32_t) (1 << 6)                                     /* TIM12 reset */
-#define RCC_APB1RSTR_TIM13RST           (uint32_t) (1 << 7)                                     /* TIM13 reset */
-#define RCC_APB1RSTR_TIM14RST           (uint32_t) (1 << 8)                                     /* TIM14 reset */
-#define RCC_APB1RSTR_WWDGRST            (uint32_t) (1 << 11)                                    /* Window watchdog reset */
-#define RCC_APB1RSTR_SPI2RST            (uint32_t) (1 << 14)                                    /* SPI2 reset */
-#define RCC_APB1RSTR_SPI3RST            (uint32_t) (1 << 15)                                    /* SPI3 reset */
-#define RCC_APB1RSTR_USART2RST          (uint32_t) (1 << 17)                                    /* USART2 reset */
-#define RCC_APB1RSTR_USART3RST          (uint32_t) (1 << 18)                                    /* USART3 reset */
-#define RCC_APB1RSTR_USART4RST          (uint32_t) (1 << 19)                                    /* USART4 reset */
-#define RCC_APB1RSTR_USART5RST          (uint32_t) (1 << 20)                                    /* USART5 reset */
-#define RCC_APB1RSTR_I2C1RST            (uint32_t) (1 << 21)                                    /* I2C1 reset */
-#define RCC_APB1RSTR_I2C2RST            (uint32_t) (1 << 22)                                    /* I2C2 reset */
-#define RCC_APB1RSTR_I2C3RST            (uint32_t) (1 << 23)                                    /* I2C3 reset */
-#define RCC_APB1RSTR_CAN1RST            (uint32_t) (1 << 25)                                    /* CAN1 reset */
-#define RCC_APB1RSTR_CAN2RST            (uint32_t) (1 << 26)                                    /* CAN2 reset */
-#define RCC_APB1RSTR_PWRRST             (uint32_t) (1 << 28)                                    /* Power interface reset */
-#define RCC_APB1RSTR_DACRST             (uint32_t) (1 << 29)                                    /* DAC reset */
-
-#define RCC_APB2RSTR_TIM1RST            (uint32_t) (1 << 0)                                     /* TIM1 reset */
-#define RCC_APB2RSTR_TIM8RST            (uint32_t) (1 << 1)                                     /* TIM8 reset */
-#define RCC_APB2RSTR_USART1RST          (uint32_t) (1 << 4)                                     /* USART1 reset */
-#define RCC_APB2RSTR_USART6RST          (uint32_t) (1 << 5)                                     /* USART6 reset */
-#define RCC_APB2RSTR_ADCRST             (uint32_t) (1 << 8)                                     /* ADC1 reset */
-#define RCC_APB2RSTR_SDIORST            (uint32_t) (1 << 11)                                    /* SDIO reset */
-#define RCC_APB2RSTR_SPI1RST            (uint32_t) (1 << 12)                                    /* SPI1 reset */
-#define RCC_APB2RSTR_SYSCFGRST          (uint32_t) (1 << 14)                                    /* System configuration controller reset */
-#define RCC_APB2RSTR_TIM9RST            (uint32_t) (1 << 16)                                    /* TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST           (uint32_t) (1 << 17)                                    /* TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST           (uint32_t) (1 << 18)                                    /* TIM11 reset */
-
-#define RCC_AHB1ENR_GPIOAEN             (uint32_t) (1 << 0)                                     /* GPIOA clock enable */
-#define RCC_AHB1ENR_GPIOBEN             (uint32_t) (1 << 1)                                     /* GPIOB clock enable */
-#define RCC_AHB1ENR_GPIOCEN             (uint32_t) (1 << 2)                                     /* GPIOC clock enable */
-#define RCC_AHB1ENR_GPIODEN             (uint32_t) (1 << 3)                                     /* GPIOD clock enable */
-#define RCC_AHB1ENR_GPIOEEN             (uint32_t) (1 << 4)                                     /* GPIOE clock enable */
-#define RCC_AHB1ENR_GPIOFEN             (uint32_t) (1 << 5)                                     /* GPIOF clock enable */
-#define RCC_AHB1ENR_GPIOGEN             (uint32_t) (1 << 6)                                     /* GPIOG clock enable */
-#define RCC_AHB1ENR_GPIOHEN             (uint32_t) (1 << 7)                                     /* GPIOH clock enable */
-#define RCC_AHB1ENR_GPIOIEN             (uint32_t) (1 << 8)                                     /* GPIOI clock enable */
-#define RCC_AHB1ENR_CRCEN               (uint32_t) (1 << 12)                                    /* CRC clock enable */
-#define RCC_AHB1ENR_BKPSRAMEN           (uint32_t) (1 << 18)                                    /* Backup SRAM clock enable */
-#define RCC_AHB1ENR_CCMDATARAMEN        (uint32_t) (1 << 20)                                    /* CCM data RAM clock enable */
-#define RCC_AHB1ENR_DMA1EN              (uint32_t) (1 << 21)                                    /* DMA1 clock enable */
-#define RCC_AHB1ENR_DMA2EN              (uint32_t) (1 << 22)                                    /* DMA2 clock enable */
-#define RCC_AHB1ENR_ETHMACEN            (uint32_t) (1 << 25)                                    /* Ethernet MAC clock enable */
-#define RCC_AHB1ENR_ETHMACTXEN          (uint32_t) (1 << 26)                                    /* Ethernet MAC TX clock enable */
-#define RCC_AHB1ENR_ETHMACRXEN          (uint32_t) (1 << 27)                                    /* Ethernet MAC RX clock enable */
-#define RCC_AHB1ENR_ETHMACPTPEN         (uint32_t) (1 << 28)                                    /* Ethernet MAC PTP clock enable */
-#define RCC_AHB1ENR_OTGHSEN             (uint32_t) (1 << 29)                                    /* USB OTG HS clock enable */
-#define RCC_AHB1ENR_OTGHSULPIEN         (uint32_t) (1 << 30)                                    /* USB OTG HSULPI clock enable */
-
-#define RCC_AHB2ENR_DCMIEN              (uint32_t) (1 << 0)                                     /* Camera interface clock enable */
-#define RCC_AHB2ENR_CRYPEN              (uint32_t) (1 << 4)                                     /* Cyrpto modules clock enable */
-#define RCC_AHB2ENR_HASHEN              (uint32_t) (1 << 5)                                     /* Hash modules clock enable */
-#define RCC_AHB2ENR_RNGEN               (uint32_t) (1 << 6)                                     /* Random number generator clock enable */
-#define RCC_AHB2ENR_OTGFSEN             (uint32_t) (1 << 7)                                     /* USB OTG FS clock enable */
-
-#define RCC_AHB3ENR_FSMCEN              (uint32_t) (1 << 0)                                     /* Flexible static memeory controller clock enable */
-
-#define RCC_APB1ENR_TIM2EN              (uint32_t) (1 << 0)                                     /* TIM2 clock enable */
-#define RCC_APB1ENR_TIM3EN              (uint32_t) (1 << 1)                                     /* TIM3 clock enable */
-#define RCC_APB1ENR_TIM4EN              (uint32_t) (1 << 2)                                     /* TIM4 clock enable */
-#define RCC_APB1ENR_TIM5EN              (uint32_t) (1 << 3)                                     /* TIM5 clock enable */
-#define RCC_APB1ENR_TIM6EN              (uint32_t) (1 << 4)                                     /* TIM6 clock enable */
-#define RCC_APB1ENR_TIM7EN              (uint32_t) (1 << 5)                                     /* TIM7 clock enable */
-#define RCC_APB1ENR_TIM12EN             (uint32_t) (1 << 6)                                     /* TIM12 clock enable */
-#define RCC_APB1ENR_TIM13EN             (uint32_t) (1 << 7)                                     /* TIM13 clock enable */
-#define RCC_APB1ENR_TIM14EN             (uint32_t) (1 << 8)                                     /* TIM14 clock enable */
-#define RCC_APB1ENR_WWDGEN              (uint32_t) (1 << 11)                                    /* Window watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN              (uint32_t) (1 << 14)                                    /* SPI2 clock enable */
-#define RCC_APB1ENR_SPI3EN              (uint32_t) (1 << 15)                                    /* SPI3 clock enable */
-#define RCC_APB1ENR_USART2EN            (uint32_t) (1 << 17)                                    /* USART2 clock enable */
-#define RCC_APB1ENR_USART3EN            (uint32_t) (1 << 18)                                    /* USART3 clock enable */
-#define RCC_APB1ENR_USART4EN            (uint32_t) (1 << 19)                                    /* USART4 clock enable */
-#define RCC_APB1ENR_USART5EN            (uint32_t) (1 << 20)                                    /* USART5 clock enable */
-#define RCC_APB1ENR_I2C1EN              (uint32_t) (1 << 21)                                    /* I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN              (uint32_t) (1 << 22)                                    /* I2C2 clock enable */
-#define RCC_APB1ENR_I2C3EN              (uint32_t) (1 << 23)                                    /* I2C3 clock enable */
-#define RCC_APB1ENR_CAN1EN              (uint32_t) (1 << 25)                                    /* CAN1 clock enable */
-#define RCC_APB1ENR_CAN2EN              (uint32_t) (1 << 26)                                    /* CAN2 clock enable */
-#define RCC_APB1ENR_PWREN               (uint32_t) (1 << 28)                                    /* Power interface clock enable */
-#define RCC_APB1ENR_DACEN               (uint32_t) (1 << 29)                                    /* DAC clock enable */
-
-#define RCC_APB2ENR_TIM1EN              (uint32_t) (1 << 0)                                     /* TIM1 clock enable */
-#define RCC_APB2ENR_TIM8EN              (uint32_t) (1 << 1)                                     /* TIM8 clock enable */
-#define RCC_APB2ENR_USART1EN            (uint32_t) (1 << 4)                                     /* USART1 clock enable */
-#define RCC_APB2ENR_USART2EN            (uint32_t) (1 << 5)                                     /* USART2 clock enable */
-#define RCC_APB2ENR_ADC1EN              (uint32_t) (1 << 8)                                     /* ADC1 clock enable */
-#define RCC_APB2ENR_ADC2EN              (uint32_t) (1 << 9)                                     /* ADC2 clock enable */
-#define RCC_APB2ENR_ADC3EN              (uint32_t) (1 << 10)                                    /* ADC3 clock enable */
-#define RCC_APB2ENR_SDIOEN              (uint32_t) (1 << 11)                                    /* SDIO clock enable */
-#define RCC_APB2ENR_SPI1EN              (uint32_t) (1 << 12)                                    /* SPI1 clock enable */
-#define RCC_APB2ENR_SYSCFGEN            (uint32_t) (1 << 14)                                    /* System configuration controller clock enable */
-#define RCC_APB2ENR_TIM9EN              (uint32_t) (1 << 16)                                    /* TIM9 clock enable */
-#define RCC_APB2ENR_TIM10EN             (uint32_t) (1 << 17)                                    /* TIM10 clock enable */
-#define RCC_APB2ENR_TIM11EN             (uint32_t) (1 << 18)                                    /* TIM11 clock enable */
-
-#define FLASH_ACR_PRFTEN                (uint32_t) (1 << 8)                                     /* Prefetch enable */
-#define FLASH_ACR_ICEN                  (uint32_t) (1 << 9)                                     /* Instruction cache enable */
-#define FLASH_ACR_DCEN                  (uint32_t) (1 << 10)                                    /* Data cache enable */
-#define FLASH_ACR_ICRST                 (uint32_t) (1 << 11)                                    /* Instruction cache reset */
-#define FLASH_ACR_CCRST                 (uint32_t) (1 << 12)                                    /* Data cache reset */
-#define FLASH_ACR_LATENCY_M             (uint32_t) (7 << 0)                                     /* Latency mask */
-#define FLASH_ACR_LATENCY(n)            (uint32_t) (n << 0)                                     /* Latency - n wait states */
+#define PWR_CR_VOS \
+    (uint16_t) (1 << 14) /* Regulator voltage scaling output selection */
+
+#define HSI_VALUE (uint32_t) (16000000) /* HSI value in Hz */
+#define HSE_VALUE (uint32_t) (1 << 27)  /* HSE value in Hz */
+
+#define RCC_CR_HSION (uint32_t) (1 << 0)        /* HSI clock enable */
+#define RCC_CR_HSIRDY (uint32_t) (1 << 1)       /* HSI ready */
+#define RCC_CR_HSITRIM_M (uint32_t) (0x1F << 3) /* HSI trimming mask */
+#define RCC_CR_HSITRIM(n) (uint32_t) (n << 3)   /* HSI trimming */
+#define RCC_CR_HSICAL_M (uint32_t) (0xFF << 8)  /* HSI calibration mask */
+#define RCC_CR_HSEON (uint32_t) (1 << 16)       /* HSE clock enable */
+#define RCC_CR_HSERDY (uint32_t) (1 << 17)      /* HSE ready */
+#define RCC_CR_HSEBYP (uint32_t) (1 << 18)      /* HSE bypass */
+#define RCC_CR_CSSON (uint32_t) (1 << 19)     /* Clock security system enable */
+#define RCC_CR_PLLON (uint32_t) (1 << 24)     /* Main PLL enable */
+#define RCC_CR_PLLRDY (uint32_t) (1 << 25)    /* Main PLL clock ready */
+#define RCC_CR_PLLI2SON (uint32_t) (1 << 26)  /* PLLI2S enable */
+#define RCC_CR_PLLI2SRDY (uint32_t) (1 << 27) /* PLLI2S clock ready */
+
+#define RCC_PLLCFGR_RESET \
+    (uint32_t) (0x24003010) /* PLLCFGR register reset value */
+#define RCC_PLLCFGR_PLLSRC_HSE \
+    (uint32_t) (1 << 22) /* HSE oscillator selected as clock entry */
+#define RCC_PLLCFGR_PLLM (uint32_t) (0x003F)
+#define RCC_PLLCFGR_PLLN (uint32_t) (0x7FC0)
+#define RCC_PLLCFGR_PLLP (uint32_t) (0x00030000)
+
+#define RCC_CFGR_SW_M (uint32_t) (3 << 0) /* System clock switch mask */
+#define RCC_CFGR_SW_HSI                                                       \
+    (uint32_t) (0 << 0) /* System clock switch - HSI selected as system clock \
+                         */
+#define RCC_CFGR_SW_HSE                                                       \
+    (uint32_t) (1 << 0) /* System clock switch - HSE selected as system clock \
+                         */
+#define RCC_CFGR_SW_PLL                                                       \
+    (uint32_t) (2 << 0) /* System clock switch - PLL selected as system clock \
+                         */
+#define RCC_CFGR_SWS_M                                     \
+    (uint32_t) (3 << 2) /* System clock switch status mask \
+                         */
+#define RCC_CFGR_SWS_HSI                                                   \
+    (uint32_t) (0 << 2) /* System clock switch status - HSI used as system \
+                           clock */
+#define RCC_CFGR_SWS_HSE                                                   \
+    (uint32_t) (1 << 2) /* System clock switch status - HSE used as system \
+                           clock */
+#define RCC_CFGR_SWS_PLL                                                   \
+    (uint32_t) (2 << 2) /* System clock switch status - PLL used as system \
+                           clock */
+#define RCC_CFGR_HPRE_M (uint32_t) (0xF << 4) /* AHB prescaler mask */
+#define RCC_CFGR_HPRE_DIV1 \
+    (uint32_t) (0x0 << 4) /* AHB prescaler - SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2                            \
+    (uint32_t) (0x8 << 4) /* AHB prescaler - SYSCLK/2 \
+                           */
+#define RCC_CFGR_HPRE_DIV4                            \
+    (uint32_t) (0x9 << 4) /* AHB prescaler - SYSCLK/4 \
+                           */
+#define RCC_CFGR_HPRE_DIV8                            \
+    (uint32_t) (0xA << 4) /* AHB prescaler - SYSCLK/8 \
+                           */
+#define RCC_CFGR_HPRE_DIV16 \
+    (uint32_t) (0xB << 4) /* AHB prescaler - SYSCLK/16 */
+#define RCC_CFGR_HPRE_DIV64 \
+    (uint32_t) (0xC << 4) /* AHB prescaler - SYSCLK/64 */
+#define RCC_CFGR_HPRE_DIV128 \
+    (uint32_t) (0xD << 4) /* AHB prescaler - SYSCLK/128 */
+#define RCC_CFGR_HPRE_DIV256 \
+    (uint32_t) (0xE << 4) /* AHB prescaler - SYSCLK/256 */
+#define RCC_CFGR_HPRE_DIV512 \
+    (uint32_t) (0xF << 4) /* AHB prescaler - SYSCLK/512 */
+#define RCC_CFGR_PPRE1_M                                 \
+    (uint32_t) (7 << 10) /* APB low speed prescaler mask \
+                          */
+#define RCC_CFGR_PPRE1_DIV1 \
+    (uint32_t) (0 << 10) /* APB low speed prescaler - HCLK/1 */
+#define RCC_CFGR_PPRE1_DIV2 \
+    (uint32_t) (4 << 10) /* APB low speed prescaler - HCLK/2 */
+#define RCC_CFGR_PPRE1_DIV4 \
+    (uint32_t) (5 << 10) /* APB low speed prescaler - HCLK/4 */
+#define RCC_CFGR_PPRE1_DIV8 \
+    (uint32_t) (6 << 10) /* APB low speed prescaler - HCLK/8 */
+#define RCC_CFGR_PPRE1_DIV16 \
+    (uint32_t) (7 << 10) /* APB low speed prescaler - HCLK/16 */
+#define RCC_CFGR_PPRE2_M \
+    (uint32_t) (7 << 13) /* APB high speec prescaler mask */
+#define RCC_CFGR_PPRE2_DIV1 \
+    (uint32_t) (0 << 13) /* APB high speed prescaler - HCLK/1 */
+#define RCC_CFGR_PPRE2_DIV2 \
+    (uint32_t) (4 << 13) /* APB high speed prescaler - HCLK/2 */
+#define RCC_CFGR_PPRE2_DIV4 \
+    (uint32_t) (5 << 13) /* APB high speed prescaler - HCLK/4 */
+#define RCC_CFGR_PPRE2_DIV8 \
+    (uint32_t) (6 << 13) /* APB high speed prescaler - HCLK/8 */
+#define RCC_CFGR_PPRE2_DIV16 \
+    (uint32_t) (7 << 13) /* APB high speed prescaler - HCLK/16 */
+#define RCC_CFGR_RTCPRE_M \
+    (uint32_t) (0x1F << 16) /* HSE division factor for RTC clock mask */
+#define RCC_CFGR_RTCPRE(n) \
+    (uint32_t) (n << 16) /* HSE division factor for RTC clock */
+
+#define RCC_AHB1RSTR_GPIOARST (uint32_t) (1 << 0)   /* GPIOA reset */
+#define RCC_AHB1RSTR_GPIOBRST (uint32_t) (1 << 1)   /* GPIOB reset */
+#define RCC_AHB1RSTR_GPIOCRST (uint32_t) (1 << 2)   /* GPIOC reset */
+#define RCC_AHB1RSTR_GPIODRST (uint32_t) (1 << 3)   /* GPIOD reset */
+#define RCC_AHB1RSTR_GPIOERST (uint32_t) (1 << 4)   /* GPIOE reset */
+#define RCC_AHB1RSTR_GPIOFRST (uint32_t) (1 << 5)   /* GPIOF reset */
+#define RCC_AHB1RSTR_GPIOGRST (uint32_t) (1 << 6)   /* GPIOG reset */
+#define RCC_AHB1RSTR_GPIOHRST (uint32_t) (1 << 7)   /* GPIOH reset */
+#define RCC_AHB1RSTR_GPIOIRST (uint32_t) (1 << 8)   /* GPIOI reset */
+#define RCC_AHB1RSTR_CRCRST (uint32_t) (1 << 12)    /* CRC reset */
+#define RCC_AHB1RSTR_DMA1RST (uint32_t) (1 << 21)   /* DMA1 reset */
+#define RCC_AHB1RSTR_DMA2RST (uint32_t) (1 << 22)   /* DMA2 reset */
+#define RCC_AHB1RSTR_ETHMACRST (uint32_t) (1 << 25) /* Ethernet MAC reset */
+#define RCC_AHB1RSTR_OTGHSRST (uint32_t) (1 << 29)  /* USB OTG HS reset */
+
+#define RCC_AHB2RSTR_DCMIRST (uint32_t) (1 << 0) /* Camera interface reset */
+#define RCC_AHB2RSTR_CRYPRST (uint32_t) (1 << 4) /* Cyrpto modules reset */
+#define RCC_AHB2RSTR_HASHRST (uint32_t) (1 << 5) /* Hash modules reset */
+#define RCC_AHB2RSTR_RNGRST \
+    (uint32_t) (1 << 6) /* Random number generator reset */
+#define RCC_AHB2RSTR_OTGFSRST (uint32_t) (1 << 7) /* USB OTG FS reset */
+
+#define RCC_AHB3RSTR_FSMCRST \
+    (uint32_t) (1 << 0) /* Flexible static memeory controller reset */
+
+#define RCC_APB1RSTR_TIM2RST (uint32_t) (1 << 0)    /* TIM2 reset */
+#define RCC_APB1RSTR_TIM3RST (uint32_t) (1 << 1)    /* TIM3 reset */
+#define RCC_APB1RSTR_TIM4RST (uint32_t) (1 << 2)    /* TIM4 reset */
+#define RCC_APB1RSTR_TIM5RST (uint32_t) (1 << 3)    /* TIM5 reset */
+#define RCC_APB1RSTR_TIM6RST (uint32_t) (1 << 4)    /* TIM6 reset */
+#define RCC_APB1RSTR_TIM7RST (uint32_t) (1 << 5)    /* TIM7 reset */
+#define RCC_APB1RSTR_TIM12RST (uint32_t) (1 << 6)   /* TIM12 reset */
+#define RCC_APB1RSTR_TIM13RST (uint32_t) (1 << 7)   /* TIM13 reset */
+#define RCC_APB1RSTR_TIM14RST (uint32_t) (1 << 8)   /* TIM14 reset */
+#define RCC_APB1RSTR_WWDGRST (uint32_t) (1 << 11)   /* Window watchdog reset */
+#define RCC_APB1RSTR_SPI2RST (uint32_t) (1 << 14)   /* SPI2 reset */
+#define RCC_APB1RSTR_SPI3RST (uint32_t) (1 << 15)   /* SPI3 reset */
+#define RCC_APB1RSTR_USART2RST (uint32_t) (1 << 17) /* USART2 reset */
+#define RCC_APB1RSTR_USART3RST (uint32_t) (1 << 18) /* USART3 reset */
+#define RCC_APB1RSTR_USART4RST (uint32_t) (1 << 19) /* USART4 reset */
+#define RCC_APB1RSTR_USART5RST (uint32_t) (1 << 20) /* USART5 reset */
+#define RCC_APB1RSTR_I2C1RST (uint32_t) (1 << 21)   /* I2C1 reset */
+#define RCC_APB1RSTR_I2C2RST (uint32_t) (1 << 22)   /* I2C2 reset */
+#define RCC_APB1RSTR_I2C3RST (uint32_t) (1 << 23)   /* I2C3 reset */
+#define RCC_APB1RSTR_CAN1RST (uint32_t) (1 << 25)   /* CAN1 reset */
+#define RCC_APB1RSTR_CAN2RST (uint32_t) (1 << 26)   /* CAN2 reset */
+#define RCC_APB1RSTR_PWRRST (uint32_t) (1 << 28)    /* Power interface reset */
+#define RCC_APB1RSTR_DACRST (uint32_t) (1 << 29)    /* DAC reset */
+
+#define RCC_APB2RSTR_TIM1RST (uint32_t) (1 << 0)   /* TIM1 reset */
+#define RCC_APB2RSTR_TIM8RST (uint32_t) (1 << 1)   /* TIM8 reset */
+#define RCC_APB2RSTR_USART1RST (uint32_t) (1 << 4) /* USART1 reset */
+#define RCC_APB2RSTR_USART6RST (uint32_t) (1 << 5) /* USART6 reset */
+#define RCC_APB2RSTR_ADCRST (uint32_t) (1 << 8)    /* ADC1 reset */
+#define RCC_APB2RSTR_SDIORST (uint32_t) (1 << 11)  /* SDIO reset */
+#define RCC_APB2RSTR_SPI1RST (uint32_t) (1 << 12)  /* SPI1 reset */
+#define RCC_APB2RSTR_SYSCFGRST \
+    (uint32_t) (1 << 14) /* System configuration controller reset */
+#define RCC_APB2RSTR_TIM9RST (uint32_t) (1 << 16)  /* TIM9 reset */
+#define RCC_APB2RSTR_TIM10RST (uint32_t) (1 << 17) /* TIM10 reset */
+#define RCC_APB2RSTR_TIM11RST (uint32_t) (1 << 18) /* TIM11 reset */
+
+#define RCC_AHB1ENR_GPIOAEN (uint32_t) (1 << 0) /* GPIOA clock enable */
+#define RCC_AHB1ENR_GPIOBEN (uint32_t) (1 << 1) /* GPIOB clock enable */
+#define RCC_AHB1ENR_GPIOCEN (uint32_t) (1 << 2) /* GPIOC clock enable */
+#define RCC_AHB1ENR_GPIODEN (uint32_t) (1 << 3) /* GPIOD clock enable */
+#define RCC_AHB1ENR_GPIOEEN (uint32_t) (1 << 4) /* GPIOE clock enable */
+#define RCC_AHB1ENR_GPIOFEN (uint32_t) (1 << 5) /* GPIOF clock enable */
+#define RCC_AHB1ENR_GPIOGEN (uint32_t) (1 << 6) /* GPIOG clock enable */
+#define RCC_AHB1ENR_GPIOHEN (uint32_t) (1 << 7) /* GPIOH clock enable */
+#define RCC_AHB1ENR_GPIOIEN (uint32_t) (1 << 8) /* GPIOI clock enable */
+#define RCC_AHB1ENR_CRCEN (uint32_t) (1 << 12)  /* CRC clock enable */
+#define RCC_AHB1ENR_BKPSRAMEN \
+    (uint32_t) (1 << 18) /* Backup SRAM clock enable */
+#define RCC_AHB1ENR_CCMDATARAMEN \
+    (uint32_t) (1 << 20)                        /* CCM data RAM clock enable */
+#define RCC_AHB1ENR_DMA1EN (uint32_t) (1 << 21) /* DMA1 clock enable */
+#define RCC_AHB1ENR_DMA2EN (uint32_t) (1 << 22) /* DMA2 clock enable */
+#define RCC_AHB1ENR_ETHMACEN \
+    (uint32_t) (1 << 25) /* Ethernet MAC clock enable */
+#define RCC_AHB1ENR_ETHMACTXEN \
+    (uint32_t) (1 << 26) /* Ethernet MAC TX clock enable */
+#define RCC_AHB1ENR_ETHMACRXEN \
+    (uint32_t) (1 << 27) /* Ethernet MAC RX clock enable */
+#define RCC_AHB1ENR_ETHMACPTPEN \
+    (uint32_t) (1 << 28) /* Ethernet MAC PTP clock enable */
+#define RCC_AHB1ENR_OTGHSEN (uint32_t) (1 << 29) /* USB OTG HS clock enable */
+#define RCC_AHB1ENR_OTGHSULPIEN \
+    (uint32_t) (1 << 30) /* USB OTG HSULPI clock enable */
+
+#define RCC_AHB2ENR_DCMIEN \
+    (uint32_t) (1 << 0) /* Camera interface clock enable */
+#define RCC_AHB2ENR_CRYPEN                                                    \
+    (uint32_t) (1 << 4)                        /* Cyrpto modules clock enable \
+                                                */
+#define RCC_AHB2ENR_HASHEN (uint32_t) (1 << 5) /* Hash modules clock enable */
+#define RCC_AHB2ENR_RNGEN \
+    (uint32_t) (1 << 6) /* Random number generator clock enable */
+#define RCC_AHB2ENR_OTGFSEN (uint32_t) (1 << 7) /* USB OTG FS clock enable */
+
+#define RCC_AHB3ENR_FSMCEN \
+    (uint32_t) (1 << 0) /* Flexible static memeory controller clock enable */
+
+#define RCC_APB1ENR_TIM2EN (uint32_t) (1 << 0)  /* TIM2 clock enable */
+#define RCC_APB1ENR_TIM3EN (uint32_t) (1 << 1)  /* TIM3 clock enable */
+#define RCC_APB1ENR_TIM4EN (uint32_t) (1 << 2)  /* TIM4 clock enable */
+#define RCC_APB1ENR_TIM5EN (uint32_t) (1 << 3)  /* TIM5 clock enable */
+#define RCC_APB1ENR_TIM6EN (uint32_t) (1 << 4)  /* TIM6 clock enable */
+#define RCC_APB1ENR_TIM7EN (uint32_t) (1 << 5)  /* TIM7 clock enable */
+#define RCC_APB1ENR_TIM12EN (uint32_t) (1 << 6) /* TIM12 clock enable */
+#define RCC_APB1ENR_TIM13EN (uint32_t) (1 << 7) /* TIM13 clock enable */
+#define RCC_APB1ENR_TIM14EN (uint32_t) (1 << 8) /* TIM14 clock enable */
+#define RCC_APB1ENR_WWDGEN \
+    (uint32_t) (1 << 11) /* Window watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN (uint32_t) (1 << 14)   /* SPI2 clock enable */
+#define RCC_APB1ENR_SPI3EN (uint32_t) (1 << 15)   /* SPI3 clock enable */
+#define RCC_APB1ENR_USART2EN (uint32_t) (1 << 17) /* USART2 clock enable */
+#define RCC_APB1ENR_USART3EN (uint32_t) (1 << 18) /* USART3 clock enable */
+#define RCC_APB1ENR_USART4EN (uint32_t) (1 << 19) /* USART4 clock enable */
+#define RCC_APB1ENR_USART5EN (uint32_t) (1 << 20) /* USART5 clock enable */
+#define RCC_APB1ENR_I2C1EN (uint32_t) (1 << 21)   /* I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN (uint32_t) (1 << 22)   /* I2C2 clock enable */
+#define RCC_APB1ENR_I2C3EN (uint32_t) (1 << 23)   /* I2C3 clock enable */
+#define RCC_APB1ENR_CAN1EN (uint32_t) (1 << 25)   /* CAN1 clock enable */
+#define RCC_APB1ENR_CAN2EN (uint32_t) (1 << 26)   /* CAN2 clock enable */
+#define RCC_APB1ENR_PWREN \
+    (uint32_t) (1 << 28) /* Power interface clock enable */
+#define RCC_APB1ENR_DACEN (uint32_t) (1 << 29) /* DAC clock enable */
+
+#define RCC_APB2ENR_TIM1EN (uint32_t) (1 << 0)   /* TIM1 clock enable */
+#define RCC_APB2ENR_TIM8EN (uint32_t) (1 << 1)   /* TIM8 clock enable */
+#define RCC_APB2ENR_USART1EN (uint32_t) (1 << 4) /* USART1 clock enable */
+#define RCC_APB2ENR_USART2EN (uint32_t) (1 << 5) /* USART2 clock enable */
+#define RCC_APB2ENR_ADC1EN (uint32_t) (1 << 8)   /* ADC1 clock enable */
+#define RCC_APB2ENR_ADC2EN (uint32_t) (1 << 9)   /* ADC2 clock enable */
+#define RCC_APB2ENR_ADC3EN (uint32_t) (1 << 10)  /* ADC3 clock enable */
+#define RCC_APB2ENR_SDIOEN (uint32_t) (1 << 11)  /* SDIO clock enable */
+#define RCC_APB2ENR_SPI1EN (uint32_t) (1 << 12)  /* SPI1 clock enable */
+#define RCC_APB2ENR_SYSCFGEN \
+    (uint32_t) (1 << 14) /* System configuration controller clock enable */
+#define RCC_APB2ENR_TIM9EN (uint32_t) (1 << 16)  /* TIM9 clock enable */
+#define RCC_APB2ENR_TIM10EN (uint32_t) (1 << 17) /* TIM10 clock enable */
+#define RCC_APB2ENR_TIM11EN (uint32_t) (1 << 18) /* TIM11 clock enable */
+
+#define FLASH_ACR_PRFTEN (uint32_t) (1 << 8)     /* Prefetch enable */
+#define FLASH_ACR_ICEN (uint32_t) (1 << 9)       /* Instruction cache enable */
+#define FLASH_ACR_DCEN (uint32_t) (1 << 10)      /* Data cache enable */
+#define FLASH_ACR_ICRST (uint32_t) (1 << 11)     /* Instruction cache reset */
+#define FLASH_ACR_CCRST (uint32_t) (1 << 12)     /* Data cache reset */
+#define FLASH_ACR_LATENCY_M (uint32_t) (7 << 0)  /* Latency mask */
+#define FLASH_ACR_LATENCY(n) (uint32_t) (n << 0) /* Latency - n wait states */
 
 /* TIMx */
-#define TIMx_CR1_CEN                    (uint32_t) (1 << 0)                                     /* TIMx counter enable */
-#define TIMx_CR1_UDIS                   (uint32_t) (1 << 1)                                     /* TIMx update disable */
-#define TIMx_CR1_URS                    (uint32_t) (1 << 2)                                     /* TIMx update request source */
-#define TIMx_CR1_OPM                    (uint32_t) (1 << 3)                                     /* TIMx one-pulse mode */
-#define TIMx_CR1_DIR_DOWN               (uint32_t) (1 << 4)                                     /* TIMx downcounter */
-#define TIMx_CR1_CMS_EDGE               (uint32_t) (0 << 5)                                     /* TIMx center-aligned mode selection - counter up or down depending on DIR bit */
-#define TIMx_CR1_CMS_CM1                (uint32_t) (1 << 5)                                     /* TIMx center-aligned mode selection - up and down, compare flags set down */
-#define TIMx_CR1_CMS_CM2                (uint32_t) (2 << 5)                                     /* TIMx center-aligned mode selection - up and down, compare flags set up */
-#define TIMx_CR1_CMS_CM3                (uint32_t) (3 << 5)                                     /* TIMx center-aligned mode selection - up and down, compare flags set up/down */
-#define TIMx_CR1_ARPE                   (uint32_t) (1 << 7)                                     /* TIMx auto-reload preload enable */
-#define TIMx_CR1_CKD_1                  (uint32_t) (0 << 8)                                     /* TIMx clock division 1 */
-#define TIMx_CR1_CKD_2                  (uint32_t) (1 << 8)                                     /* TIMx clock division 2 */
-#define TIMx_CR1_CKD_4                  (uint32_t) (2 << 8)                                     /* TIMx clock division 4 */
-
-#define TIMx_CR2_CCDS                   (uint32_t) (1 << 3)                                     /* TIMx capture/compare DMA requests send when update event occurs */
-#define TIMx_CR2_MMS_RST                (uint32_t) (0 << 4)                                     /* TIMx master mode - reset */
-#define TIMx_CR2_MMS_EN                 (uint32_t) (1 << 4)                                     /* TIMx master mode - enable */
-#define TIMx_CR2_MMS_UP                 (uint32_t) (2 << 4)                                     /* TIMx master mode - update */
-#define TIMx_CR2_MMS_CMP_PUL            (uint32_t) (3 << 4)                                     /* TIMx master mode - compare pulse */
-#define TIMx_CR2_MMS_CMP_OC1            (uint32_t) (4 << 4)                                     /* TIMx master mode - compare OC1 */
-#define TIMx_CR2_MMS_CMP_OC2            (uint32_t) (5 << 4)                                     /* TIMx master mode - compare OC2 */
-#define TIMx_CR2_MMS_CMP_OC3            (uint32_t) (6 << 4)                                     /* TIMx master mode - compare OC3 */
-#define TIMx_CR2_MMS_CMP_OC4            (uint32_t) (7 << 4)                                     /* TIMx master mode - compare OC4 */
-#define TIMx_CR2_TI1_123                (uint32_t) (1 << 7)                                     /* TIMx CH1, CH2, CH3 pins connected to TI1 */
-
-#define TIMx_DIER_UIE                   (uint32_t) (1 << 0)                                     /* TIMx update interrupt enable */
-#define TIMx_DIER_CC1IE                 (uint32_t) (1 << 1)                                     /* TIMx CC1 interrupt enable */
-#define TIMx_DIER_CC2IE                 (uint32_t) (1 << 2)                                     /* TIMx CC2 interrupt enable */
-#define TIMx_DIER_CC3IE                 (uint32_t) (1 << 3)                                     /* TIMx CC3 interrupt enable */
-#define TIMx_DIER_CC4IE                 (uint32_t) (1 << 4)                                     /* TIMx CC4 interrupt enable */
-#define TIMx_DIER_TIE                   (uint32_t) (1 << 6)                                     /* TIMx trigger interrupt enable */
-#define TIMx_DIER_UDE                   (uint32_t) (1 << 8)                                     /* TIMx update DMA request enable */
-#define TIMx_DIER_CC1DE                 (uint32_t) (1 << 9)                                     /* TIMx CC1 DMA request enable */
-#define TIMx_DIER_CC2DE                 (uint32_t) (1 << 10)                                    /* TIMx CC2 DMA request enable */
-#define TIMx_DIER_CC3DE                 (uint32_t) (1 << 11)                                    /* TIMx CC3 DMA request enable */
-#define TIMx_DIER_CC4DE                 (uint32_t) (1 << 12)                                    /* TIMx CC4 DMA request enable */
-#define TIMx_DIER_TDE                   (uint32_t) (1 << 14)                                    /* TIMx trigger DMA request enable */
+#define TIMx_CR1_CEN (uint32_t) (1 << 0)      /* TIMx counter enable */
+#define TIMx_CR1_UDIS (uint32_t) (1 << 1)     /* TIMx update disable */
+#define TIMx_CR1_URS (uint32_t) (1 << 2)      /* TIMx update request source */
+#define TIMx_CR1_OPM (uint32_t) (1 << 3)      /* TIMx one-pulse mode */
+#define TIMx_CR1_DIR_DOWN (uint32_t) (1 << 4) /* TIMx downcounter */
+#define TIMx_CR1_CMS_EDGE                                                     \
+    (uint32_t) (0 << 5) /* TIMx center-aligned mode selection - counter up or \
+                           down depending on DIR bit */
+#define TIMx_CR1_CMS_CM1                                                     \
+    (uint32_t) (1 << 5) /* TIMx center-aligned mode selection - up and down, \
+                           compare flags set down */
+#define TIMx_CR1_CMS_CM2                                                     \
+    (uint32_t) (2 << 5) /* TIMx center-aligned mode selection - up and down, \
+                           compare flags set up */
+#define TIMx_CR1_CMS_CM3                                                     \
+    (uint32_t) (3 << 5) /* TIMx center-aligned mode selection - up and down, \
+                           compare flags set up/down */
+#define TIMx_CR1_ARPE                                                         \
+    (uint32_t) (1 << 7)                    /* TIMx auto-reload preload enable \
+                                            */
+#define TIMx_CR1_CKD_1 (uint32_t) (0 << 8) /* TIMx clock division 1 */
+#define TIMx_CR1_CKD_2 (uint32_t) (1 << 8) /* TIMx clock division 2 */
+#define TIMx_CR1_CKD_4 (uint32_t) (2 << 8) /* TIMx clock division 4 */
+
+#define TIMx_CR2_CCDS                                                         \
+    (uint32_t) (1 << 3) /* TIMx capture/compare DMA requests send when update \
+                           event occurs */
+#define TIMx_CR2_MMS_RST (uint32_t) (0 << 4) /* TIMx master mode - reset */
+#define TIMx_CR2_MMS_EN (uint32_t) (1 << 4)  /* TIMx master mode - enable */
+#define TIMx_CR2_MMS_UP (uint32_t) (2 << 4)  /* TIMx master mode - update */
+#define TIMx_CR2_MMS_CMP_PUL \
+    (uint32_t) (3 << 4) /* TIMx master mode - compare pulse */
+#define TIMx_CR2_MMS_CMP_OC1 \
+    (uint32_t) (4 << 4) /* TIMx master mode - compare OC1 */
+#define TIMx_CR2_MMS_CMP_OC2 \
+    (uint32_t) (5 << 4) /* TIMx master mode - compare OC2 */
+#define TIMx_CR2_MMS_CMP_OC3 \
+    (uint32_t) (6 << 4) /* TIMx master mode - compare OC3 */
+#define TIMx_CR2_MMS_CMP_OC4 \
+    (uint32_t) (7 << 4) /* TIMx master mode - compare OC4 */
+#define TIMx_CR2_TI1_123 \
+    (uint32_t) (1 << 7) /* TIMx CH1, CH2, CH3 pins connected to TI1 */
+
+#define TIMx_DIER_UIE (uint32_t) (1 << 0)   /* TIMx update interrupt enable */
+#define TIMx_DIER_CC1IE (uint32_t) (1 << 1) /* TIMx CC1 interrupt enable */
+#define TIMx_DIER_CC2IE (uint32_t) (1 << 2) /* TIMx CC2 interrupt enable */
+#define TIMx_DIER_CC3IE (uint32_t) (1 << 3) /* TIMx CC3 interrupt enable */
+#define TIMx_DIER_CC4IE (uint32_t) (1 << 4) /* TIMx CC4 interrupt enable */
+#define TIMx_DIER_TIE (uint32_t) (1 << 6)   /* TIMx trigger interrupt enable */
+#define TIMx_DIER_UDE (uint32_t) (1 << 8)   /* TIMx update DMA request enable */
+#define TIMx_DIER_CC1DE (uint32_t) (1 << 9) /* TIMx CC1 DMA request enable */
+#define TIMx_DIER_CC2DE (uint32_t) (1 << 10) /* TIMx CC2 DMA request enable */
+#define TIMx_DIER_CC3DE (uint32_t) (1 << 11) /* TIMx CC3 DMA request enable */
+#define TIMx_DIER_CC4DE (uint32_t) (1 << 12) /* TIMx CC4 DMA request enable */
+#define TIMx_DIER_TDE                                       \
+    (uint32_t) (1 << 14) /* TIMx trigger DMA request enable \
+                          */
 
 /* SPI */
-#define SPI_CR1_CPHA                    (uint32_t) (1 << 0)                                     /* SPI clock phase */
-#define SPI_CR1_CPOL                    (uint32_t) (1 << 1)                                     /* SPI clock polarity */
-#define SPI_CR1_MSTR                    (uint32_t) (1 << 2)                                     /* SPI master selection */
-#define SPI_CR1_BR_2                    (uint32_t) (0 << 3)                                     /* SPI baud rate = fPCLK/2 */
-#define SPI_CR1_BR_4                    (uint32_t) (1 << 3)                                     /* SPI baud rate = fPCLK/4 */
-#define SPI_CR1_BR_8                    (uint32_t) (2 << 3)                                     /* SPI baud rate = fPCLK/8 */
-#define SPI_CR1_BR_16                   (uint32_t) (3 << 3)                                     /* SPI baud rate = fPCLK/16 */
-#define SPI_CR1_BR_32                   (uint32_t) (4 << 3)                                     /* SPI baud rate = fPCLK/32 */
-#define SPI_CR1_BR_64                   (uint32_t) (5 << 3)                                     /* SPI baud rate = fPCLK/64 */
-#define SPI_CR1_BR_128                  (uint32_t) (6 << 3)                                     /* SPI baud rate = fPCLK/128 */
-#define SPI_CR1_BR_256                  (uint32_t) (7 << 3)                                     /* SPI baud rate = fPCLK/256 */
-#define SPI_CR1_SPE                     (uint32_t) (1 << 6)                                     /* SPI enable */
-#define SPI_CR1_LSBFIRST                (uint32_t) (1 << 7)                                     /* SPI LSB transmitted first */
-#define SPI_CR1_SSI                     (uint32_t) (1 << 8)                                     /* SPI internal slave select */
-#define SPI_CR1_SSM                     (uint32_t) (1 << 9)                                     /* SPI software slave management */
-#define SPI_CR1_DFF                     (uint32_t) (1 << 11)                                    /* SPI data frame format (0 = 8bit, 1 = 16bit) */
-#define SPI_SR_RXNE                     (uint32_t) (1 << 0)                                     /* SPI receive not empty */
-#define SPI_SR_TXNE                     (uint32_t) (1 << 1)                                     /* SPI transmit not empty */
-#define SPI_SR_CHSIDE                   (uint32_t) (1 << 2)                                     /* SPI channel side */
-#define SPI_SR_UDR                      (uint32_t) (1 << 3)                                     /* SPI underrun flag */
-#define SPI_SR_CRCERR                   (uint32_t) (1 << 4)                                     /* SPI CRC error flag */
-#define SPI_SR_MODF                     (uint32_t) (1 << 5)                                     /* SPI mode fault */
-#define SPI_SR_OVR                      (uint32_t) (1 << 6)                                     /* SPI overrun flag */
-#define SPI_SR_BSY                      (uint32_t) (1 << 7)                                     /* SPI busy flag */
-#define SPI_SR_TIRFE                    (uint32_t) (1 << 8)                                     /* SPI TI frame format error */
+#define SPI_CR1_CPHA (uint32_t) (1 << 0)     /* SPI clock phase */
+#define SPI_CR1_CPOL (uint32_t) (1 << 1)     /* SPI clock polarity */
+#define SPI_CR1_MSTR (uint32_t) (1 << 2)     /* SPI master selection */
+#define SPI_CR1_BR_2 (uint32_t) (0 << 3)     /* SPI baud rate = fPCLK/2 */
+#define SPI_CR1_BR_4 (uint32_t) (1 << 3)     /* SPI baud rate = fPCLK/4 */
+#define SPI_CR1_BR_8 (uint32_t) (2 << 3)     /* SPI baud rate = fPCLK/8 */
+#define SPI_CR1_BR_16 (uint32_t) (3 << 3)    /* SPI baud rate = fPCLK/16 */
+#define SPI_CR1_BR_32 (uint32_t) (4 << 3)    /* SPI baud rate = fPCLK/32 */
+#define SPI_CR1_BR_64 (uint32_t) (5 << 3)    /* SPI baud rate = fPCLK/64 */
+#define SPI_CR1_BR_128 (uint32_t) (6 << 3)   /* SPI baud rate = fPCLK/128 */
+#define SPI_CR1_BR_256 (uint32_t) (7 << 3)   /* SPI baud rate = fPCLK/256 */
+#define SPI_CR1_SPE (uint32_t) (1 << 6)      /* SPI enable */
+#define SPI_CR1_LSBFIRST (uint32_t) (1 << 7) /* SPI LSB transmitted first */
+#define SPI_CR1_SSI (uint32_t) (1 << 8)      /* SPI internal slave select */
+#define SPI_CR1_SSM (uint32_t) (1 << 9)      /* SPI software slave management */
+#define SPI_CR1_DFF \
+    (uint32_t) (1 << 11) /* SPI data frame format (0 = 8bit, 1 = 16bit) */
+#define SPI_SR_RXNE (uint32_t) (1 << 0)   /* SPI receive not empty */
+#define SPI_SR_TXNE (uint32_t) (1 << 1)   /* SPI transmit not empty */
+#define SPI_SR_CHSIDE (uint32_t) (1 << 2) /* SPI channel side */
+#define SPI_SR_UDR (uint32_t) (1 << 3)    /* SPI underrun flag */
+#define SPI_SR_CRCERR (uint32_t) (1 << 4) /* SPI CRC error flag */
+#define SPI_SR_MODF (uint32_t) (1 << 5)   /* SPI mode fault */
+#define SPI_SR_OVR (uint32_t) (1 << 6)    /* SPI overrun flag */
+#define SPI_SR_BSY (uint32_t) (1 << 7)    /* SPI busy flag */
+#define SPI_SR_TIRFE (uint32_t) (1 << 8)  /* SPI TI frame format error */
 
 /* I2C */
-#define I2C_CR1_PE                      (uint32_t) (1 << 0)                                     /* I2C peripheral enable */
-#define I2C_CR1_SMBUS                   (uint32_t) (1 << 1)                                     /* I2C SMBus mode */
-#define I2C_CR1_SMBTYPE                 (uint32_t) (1 << 3)                                     /* I2C SMBus type (0=Device, 1=Host) */
-#define I2C_CR1_ENARP                   (uint32_t) (1 << 4)                                     /* I2C enable ARP */
-#define I2C_CR1_ENPEC                   (uint32_t) (1 << 5)                                     /* I2C enable PEC */
-#define I2C_CR1_ENGC                    (uint32_t) (1 << 6)                                     /* I2C enable general call */
-#define I2C_CR1_NOSTRETCH               (uint32_t) (1 << 7)                                     /* I2C clock stretching disable */
-#define I2C_CR1_START                   (uint32_t) (1 << 8)                                     /* I2C START generation */
-#define I2C_CR1_STOP                    (uint32_t) (1 << 9)                                     /* I2C STOP generation */
-#define I2C_CR1_ACK                     (uint32_t) (1 << 10)                                    /* I2C ACK enable */
-#define I2C_CR1_POS                     (uint32_t) (1 << 11)                                    /* I2C ACK/PEC position */
-#define I2C_CR1_PEC                     (uint32_t) (1 << 12)                                    /* I2C packet error checking */
-#define I2C_CR1_ALERT                   (uint32_t) (1 << 13)                                    /* I2C SMBus alert */
-#define I2C_CR1_SWRST                   (uint32_t) (1 << 15)                                    /* I2C software reset */
-
-#define I2C_CR2_FREQ(n)                 (uint32_t) (n << 0)                                     /* I2C clock frequency */
-#define I2C_CR2_ITERREN                 (uint32_t) (1 << 8)                                     /* I2C error interrupt enable */
-#define I2C_CR2_ITEVTEN                 (uint32_t) (1 << 9)                                     /* I2C event interrupt enable */
-#define I2C_CR2_ITBUFEN                 (uint32_t) (1 << 10)                                    /* I2C buffer interrupt enable */
-#define I2C_CR2_DMAEN                   (uint32_t) (1 << 11)                                    /* I2C DMA requests enable */
-#define I2C_CR2_LAST                    (uint32_t) (1 << 12)                                    /* I2C DMA last transfer */
-
-#define I2C_OAR1_ADD10(n)               (uint32_t) (n << 0)                                     /* I2C interface address (10-bit) */
-#define I2C_OAR1_ADD7(n)                (uint32_t) (n << 1)                                     /* I2C interface address (7-bit) */
-#define I2C_OAR1_ADDMODE                (uint32_t) (1 << 15)                                    /* I2C interface address mode (1=10-bit) */
-
-#define I2C_OAR2_ENDUAL                 (uint32_t) (1 << 0)                                     /* I2C dual address mode enable */
-#define I2C_OAR2_ADD2(n)                (uint32_t) (n << 1)                                     /* I2C interface address 2 (7-bit) */
-
-#define I2C_SR1_SB                      (uint32_t) (1 << 0)                                     /* I2C start bit generated */
-#define I2C_SR1_ADDR                    (uint32_t) (1 << 1)                                     /* I2C address sent/matched */
-#define I2C_SR1_BTF                     (uint32_t) (1 << 2)                                     /* I2C byte transfer finished */
-#define I2C_SR1_ADD10                   (uint32_t) (1 << 3)                                     /* I2C 10-bit header sent */
-#define I2C_SR1_STOPF                   (uint32_t) (1 << 4)                                     /* I2C stop detection */
-#define I2C_SR1_RXNE                    (uint32_t) (1 << 6)                                     /* I2C DR not empty */
-#define I2C_SR1_TXE                     (uint32_t) (1 << 7)                                     /* I2C DR empty */
-#define I2C_SR1_BERR                    (uint32_t) (1 << 8)                                     /* I2C bus error */
-#define I2C_SR1_ARLO                    (uint32_t) (1 << 9)                                     /* I2C attribution lost */
-#define I2C_SR1_AF                      (uint32_t) (1 << 10)                                    /* I2C acknowledge failure */
-#define I2C_SR1_OVR                     (uint32_t) (1 << 11)                                    /* I2C overrun/underrun */
-#define I2C_SR1_PECERR                  (uint32_t) (1 << 12)                                    /* I2C PEC error in reception */
-#define I2C_SR1_TIMEOUT                 (uint32_t) (1 << 14)                                    /* I2C timeout or tlow error */
-#define I2C_SR1_SMBALERT                (uint32_t) (1 << 15)                                    /* I2C SMBus alert */
-
-#define I2C_SR2_MSL                     (uint32_t) (1 << 0)                                     /* I2C master/slave */
-#define I2C_SR2_BUSY                    (uint32_t) (1 << 1)                                     /* I2C bus busy */
-#define I2C_SR2_TRA                     (uint32_t) (1 << 2)                                     /* I2C transmitter/receiver */
-#define I2C_SR2_GENCALL                 (uint32_t) (1 << 4)                                     /* I2C general call address */
-#define I2C_SR2_SMBDEFAULT              (uint32_t) (1 << 5)                                     /* I2C SMBus device default address */
-#define I2C_SR2_SMBHOST                 (uint32_t) (1 << 6)                                     /* I2C SMBus host header */
-#define I2C_SR2_DUALF                   (uint32_t) (1 << 7)                                     /* I2C dual flag */
-#define I2C_SR2_PEC(r)                  (uint32_t) (r >> 8)                                     /* I2C packet error checking register */
-
-#define I2C_CCR_CCR(n)                  (uint32_t) (n & 0x0FFF)                                 /* I2C clock control register */
-#define I2C_CCR_DUTY                    (uint32_t) (1 << 14)                                    /* I2C fast mode duty cycle */
-#define I2C_CCR_FS                      (uint32_t) (1 << 15)                                    /* I2C master mode selection */
+#define I2C_CR1_PE (uint32_t) (1 << 0)    /* I2C peripheral enable */
+#define I2C_CR1_SMBUS (uint32_t) (1 << 1) /* I2C SMBus mode */
+#define I2C_CR1_SMBTYPE \
+    (uint32_t) (1 << 3) /* I2C SMBus type (0=Device, 1=Host) */
+#define I2C_CR1_ENARP (uint32_t) (1 << 4) /* I2C enable ARP */
+#define I2C_CR1_ENPEC (uint32_t) (1 << 5) /* I2C enable PEC */
+#define I2C_CR1_ENGC (uint32_t) (1 << 6)  /* I2C enable general call */
+#define I2C_CR1_NOSTRETCH                                                  \
+    (uint32_t) (1 << 7)                    /* I2C clock stretching disable \
+                                            */
+#define I2C_CR1_START (uint32_t) (1 << 8)  /* I2C START generation */
+#define I2C_CR1_STOP (uint32_t) (1 << 9)   /* I2C STOP generation */
+#define I2C_CR1_ACK (uint32_t) (1 << 10)   /* I2C ACK enable */
+#define I2C_CR1_POS (uint32_t) (1 << 11)   /* I2C ACK/PEC position */
+#define I2C_CR1_PEC (uint32_t) (1 << 12)   /* I2C packet error checking */
+#define I2C_CR1_ALERT (uint32_t) (1 << 13) /* I2C SMBus alert */
+#define I2C_CR1_SWRST (uint32_t) (1 << 15) /* I2C software reset */
+
+#define I2C_CR2_FREQ(n) (uint32_t) (n << 0)  /* I2C clock frequency */
+#define I2C_CR2_ITERREN (uint32_t) (1 << 8)  /* I2C error interrupt enable */
+#define I2C_CR2_ITEVTEN (uint32_t) (1 << 9)  /* I2C event interrupt enable */
+#define I2C_CR2_ITBUFEN (uint32_t) (1 << 10) /* I2C buffer interrupt enable */
+#define I2C_CR2_DMAEN (uint32_t) (1 << 11)   /* I2C DMA requests enable */
+#define I2C_CR2_LAST (uint32_t) (1 << 12)    /* I2C DMA last transfer */
+
+#define I2C_OAR1_ADD10(n) \
+    (uint32_t) (n << 0) /* I2C interface address (10-bit) */
+#define I2C_OAR1_ADD7(n)                                 \
+    (uint32_t) (n << 1) /* I2C interface address (7-bit) \
+                         */
+#define I2C_OAR1_ADDMODE \
+    (uint32_t) (1 << 15) /* I2C interface address mode (1=10-bit) */
+
+#define I2C_OAR2_ENDUAL (uint32_t) (1 << 0) /* I2C dual address mode enable */
+#define I2C_OAR2_ADD2(n) \
+    (uint32_t) (n << 1) /* I2C interface address 2 (7-bit) */
+
+#define I2C_SR1_SB (uint32_t) (1 << 0)        /* I2C start bit generated */
+#define I2C_SR1_ADDR (uint32_t) (1 << 1)      /* I2C address sent/matched */
+#define I2C_SR1_BTF (uint32_t) (1 << 2)       /* I2C byte transfer finished */
+#define I2C_SR1_ADD10 (uint32_t) (1 << 3)     /* I2C 10-bit header sent */
+#define I2C_SR1_STOPF (uint32_t) (1 << 4)     /* I2C stop detection */
+#define I2C_SR1_RXNE (uint32_t) (1 << 6)      /* I2C DR not empty */
+#define I2C_SR1_TXE (uint32_t) (1 << 7)       /* I2C DR empty */
+#define I2C_SR1_BERR (uint32_t) (1 << 8)      /* I2C bus error */
+#define I2C_SR1_ARLO (uint32_t) (1 << 9)      /* I2C attribution lost */
+#define I2C_SR1_AF (uint32_t) (1 << 10)       /* I2C acknowledge failure */
+#define I2C_SR1_OVR (uint32_t) (1 << 11)      /* I2C overrun/underrun */
+#define I2C_SR1_PECERR (uint32_t) (1 << 12)   /* I2C PEC error in reception */
+#define I2C_SR1_TIMEOUT (uint32_t) (1 << 14)  /* I2C timeout or tlow error */
+#define I2C_SR1_SMBALERT (uint32_t) (1 << 15) /* I2C SMBus alert */
+
+#define I2C_SR2_MSL (uint32_t) (1 << 0)     /* I2C master/slave */
+#define I2C_SR2_BUSY (uint32_t) (1 << 1)    /* I2C bus busy */
+#define I2C_SR2_TRA (uint32_t) (1 << 2)     /* I2C transmitter/receiver */
+#define I2C_SR2_GENCALL (uint32_t) (1 << 4) /* I2C general call address */
+#define I2C_SR2_SMBDEFAULT \
+    (uint32_t) (1 << 5) /* I2C SMBus device default address */
+#define I2C_SR2_SMBHOST (uint32_t) (1 << 6) /* I2C SMBus host header */
+#define I2C_SR2_DUALF (uint32_t) (1 << 7)   /* I2C dual flag */
+#define I2C_SR2_PEC(r) \
+    (uint32_t) (r >> 8) /* I2C packet error checking register */
+
+#define I2C_CCR_CCR(n)                                                  \
+    (uint32_t) (n & 0x0FFF)               /* I2C clock control register \
+                                           */
+#define I2C_CCR_DUTY (uint32_t) (1 << 14) /* I2C fast mode duty cycle */
+#define I2C_CCR_FS (uint32_t) (1 << 15)   /* I2C master mode selection */
 
 /* USART */
-#define USART_SR_TC                     (uint32_t) (1 << 6)                                     /* USART Transmission Complete */
-#define USART_SR_RXNE                   (uint32_t) (1 << 5)                                     /* USART Read data register not empty */
+#define USART_SR_TC (uint32_t) (1 << 6) /* USART Transmission Complete */
+#define USART_SR_RXNE \
+    (uint32_t) (1 << 5) /* USART Read data register not empty */
 
 /* USART_CR1 */
-#define USART_CR1_OVER8                 (uint32_t) (1 << 15)                                    /* Oversampling mode */
-#define USART_CR1_UE                    (uint32_t) (1 << 13)                                    /* USART Enable */
-#define USART_CR1_M9                    (uint32_t) (1 << 12)                                    /* World length 1: 9 bits, 0: 8bits */
-#define USART_CR1_WAKE                  (uint32_t) (1 << 11)                                    /* Wakeup method */
-#define USART_CR1_PCE                   (uint32_t) (1 << 10)                                    /* PCE Parity control enable */
-#define USART_CR1_PS                    (uint32_t) (1 << 9)                                     /* Parity selection */
-#define USART_CR1_PEIE                  (uint32_t) (1 << 8)                                     /* PE Interrupt enable */
-#define USART_CR1_TXEIE                 (uint32_t) (1 << 7)                                     /* TXE interrupt enable */
-#define USART_CR1_TCIE                  (uint32_t) (1 << 6)                                     /* Transmission complete interrupt enable */
-#define USART_CR1_RXNEIE                (uint32_t) (1 << 5)                                     /* RXNE Interrupt Enable */
-#define USART_CR1_IDLEIE                (uint32_t) (1 << 4)                                     /* IDEL INterrupt Enable */
-#define USART_CR1_TE                    (uint32_t) (1 << 3)                                     /* USART Transmit Enable */
-#define USART_CR1_RE                    (uint32_t) (1 << 2)                                     /* USART Receive Enable */
-#define USART_CR1_RWU                   (uint32_t) (1 << 1)
-#define USART_CR1_SBK                   (uint32_t) (1 << 0)                                     /* Send break characters */
-
-#define USART_CR3_DMAR_EN               (uint32_t) (1 << 6)                                     /* USART DMA Receive Enable */
-#define USART_CR3_DMAT_EN               (uint32_t) (1 << 7)                                     /* USART DMA Transmit Enable */
+#define USART_CR1_OVER8 (uint32_t) (1 << 15) /* Oversampling mode */
+#define USART_CR1_UE (uint32_t) (1 << 13)    /* USART Enable */
+#define USART_CR1_M9                                         \
+    (uint32_t) (1 << 12) /* World length 1: 9 bits, 0: 8bits \
+                          */
+#define USART_CR1_WAKE (uint32_t) (1 << 11) /* Wakeup method */
+#define USART_CR1_PCE (uint32_t) (1 << 10)  /* PCE Parity control enable */
+#define USART_CR1_PS (uint32_t) (1 << 9)    /* Parity selection */
+#define USART_CR1_PEIE (uint32_t) (1 << 8)  /* PE Interrupt enable */
+#define USART_CR1_TXEIE (uint32_t) (1 << 7) /* TXE interrupt enable */
+#define USART_CR1_TCIE \
+    (uint32_t) (1 << 6) /* Transmission complete interrupt enable */
+#define USART_CR1_RXNEIE (uint32_t) (1 << 5) /* RXNE Interrupt Enable */
+#define USART_CR1_IDLEIE (uint32_t) (1 << 4) /* IDEL INterrupt Enable */
+#define USART_CR1_TE (uint32_t) (1 << 3)     /* USART Transmit Enable */
+#define USART_CR1_RE (uint32_t) (1 << 2)     /* USART Receive Enable */
+#define USART_CR1_RWU (uint32_t) (1 << 1)
+#define USART_CR1_SBK (uint32_t) (1 << 0) /* Send break characters */
+
+#define USART_CR3_DMAR_EN (uint32_t) (1 << 6) /* USART DMA Receive Enable */
+#define USART_CR3_DMAT_EN (uint32_t) (1 << 7) /* USART DMA Transmit Enable */
 
 /* GPIO */
-#define GPIOA                           (uint8_t)  (0)                                          /* GPIO Port A */
-#define GPIOB                           (uint8_t)  (1)                                          /* GPIO Port B */
-#define GPIOC                           (uint8_t)  (2)                                          /* GPIO Port C */
-#define GPIOD                           (uint8_t)  (3)                                          /* GPIO Port D */
-#define GPIOE                           (uint8_t)  (4)                                          /* GPIO Port E */
-#define GPIOF                           (uint8_t)  (5)                                          /* GPIO Port F */
-#define GPIOG                           (uint8_t)  (6)                                          /* GPIO Port G */
-#define GPIOH                           (uint8_t)  (7)                                          /* GPIO Port H */
-#define GPIOI                           (uint8_t)  (8)                                          /* GPIO Port I */
-
-#define GPIO_MODER_PIN(n)               (uint32_t) (2*n)                                        /* Pin bitshift */
-#define GPIO_MODER_M(n)                 (uint32_t) (0x3 << 2*n)                                 /* Pin mask */
-#define GPIO_MODER_IN                   (uint32_t) (0x0)                                        /* Input mode */
-#define GPIO_MODER_OUT                  (uint32_t) (0x1)                                        /* Output mode */
-#define GPIO_MODER_ALT                  (uint32_t) (0x2)                                        /* Alternative function mode */
-#define GPIO_MODER_ANA                  (uint32_t) (0x3)                                        /* Analog mode */
-
-#define GPIO_OTYPER_PIN(n)              (uint32_t) (n)                                          /* Pin bitshift */
-#define GPIO_OTYPER_M(n)                (uint32_t) (1 << n)                                     /* Pin mask */
-#define GPIO_OTYPER_PP                  (uint32_t) (0x0)                                        /* Output push-pull */
-#define GPIO_OTYPER_OD                  (uint32_t) (0x1)                                        /* Output open drain */
-
-#define GPIO_OSPEEDR_PIN(n)             (uint32_t) (2*n)                                        /* Pin bitshift */
-#define GPIO_OSPEEDR_M(n)               (uint32_t) (0x3 << (2*n))                               /* Pin mask */
-#define GPIO_OSPEEDR_2M                 (uint32_t) (0x0)                                        /* Output speed 2MHz */
-#define GPIO_OSPEEDR_25M                (uint32_t) (0x1)                                        /* Output speed 25MHz */
-#define GPIO_OSPEEDR_50M                (uint32_t) (0x2)                                        /* Output speed 50MHz */
-#define GPIO_OSPEEDR_100M               (uint32_t) (0x3)                                        /* Output speed 100MHz */
-
-#define GPIO_PUPDR_PIN(n)               (uint32_t) (2*n)                                        /* Pin bitshift */
-#define GPIO_PUPDR_M(n)                 (uint32_t) (0x3 << (2*n))                               /* Pin mask */
-#define GPIO_PUPDR_NONE                 (uint32_t) (0x0)                                        /* Port no pull-up, pull-down */
-#define GPIO_PUPDR_UP                   (uint32_t) (0x1)                                        /* Port pull-up */
-#define GPIO_PUPDR_DOWN                 (uint32_t) (0x2)                                        /* Port pull-down */
-
-#define GPIO_IDR_PIN(n)                 (uint32_t) (1 << n)                                     /* Input for pin n */
-
-#define GPIO_ODR_PIN(n)                 (uint32_t) (1 << n)                                     /* Output for pin n */
-
-#define GPIO_BSRR_BS(n)                 (uint32_t) (1 << n)                                     /* Set pin n */
-#define GPIO_BSRR_BR(n)                 (uint32_t) (1 << (n+16))                                /* Reset pin n */
-
-#define GPIO_AFRL_PIN(n)                (uint32_t) (4*n)                                        /* Pin bitshift */
-#define GPIO_AFRL_M(n)                  (uint32_t) (0xF << (4*n))                               /* Pin mask */
-#define GPIO_AFRH_PIN(n)                (uint32_t) (4*(n-8))                                    /* Pin bitshift */
-#define GPIO_AFRH_M(n)                  (uint32_t) (0xF << (4*(n-8)))                           /* Pin mask */
+#define GPIOA (uint8_t) (0) /* GPIO Port A */
+#define GPIOB (uint8_t) (1) /* GPIO Port B */
+#define GPIOC (uint8_t) (2) /* GPIO Port C */
+#define GPIOD (uint8_t) (3) /* GPIO Port D */
+#define GPIOE (uint8_t) (4) /* GPIO Port E */
+#define GPIOF (uint8_t) (5) /* GPIO Port F */
+#define GPIOG (uint8_t) (6) /* GPIO Port G */
+#define GPIOH (uint8_t) (7) /* GPIO Port H */
+#define GPIOI (uint8_t) (8) /* GPIO Port I */
+
+#define GPIO_MODER_PIN(n) (uint32_t) (2 * n)      /* Pin bitshift */
+#define GPIO_MODER_M(n) (uint32_t) (0x3 << 2 * n) /* Pin mask */
+#define GPIO_MODER_IN (uint32_t) (0x0)            /* Input mode */
+#define GPIO_MODER_OUT (uint32_t) (0x1)           /* Output mode */
+#define GPIO_MODER_ALT (uint32_t) (0x2) /* Alternative function mode */
+#define GPIO_MODER_ANA (uint32_t) (0x3) /* Analog mode */
+
+#define GPIO_OTYPER_PIN(n) (uint32_t) (n)    /* Pin bitshift */
+#define GPIO_OTYPER_M(n) (uint32_t) (1 << n) /* Pin mask */
+#define GPIO_OTYPER_PP (uint32_t) (0x0)      /* Output push-pull */
+#define GPIO_OTYPER_OD (uint32_t) (0x1)      /* Output open drain */
+
+#define GPIO_OSPEEDR_PIN(n) (uint32_t) (2 * n)        /* Pin bitshift */
+#define GPIO_OSPEEDR_M(n) (uint32_t) (0x3 << (2 * n)) /* Pin mask */
+#define GPIO_OSPEEDR_2M (uint32_t) (0x0)              /* Output speed 2MHz */
+#define GPIO_OSPEEDR_25M (uint32_t) (0x1)             /* Output speed 25MHz */
+#define GPIO_OSPEEDR_50M (uint32_t) (0x2)             /* Output speed 50MHz */
+#define GPIO_OSPEEDR_100M (uint32_t) (0x3)            /* Output speed 100MHz */
+
+#define GPIO_PUPDR_PIN(n) (uint32_t) (2 * n)        /* Pin bitshift */
+#define GPIO_PUPDR_M(n) (uint32_t) (0x3 << (2 * n)) /* Pin mask */
+#define GPIO_PUPDR_NONE (uint32_t) (0x0) /* Port no pull-up, pull-down */
+#define GPIO_PUPDR_UP (uint32_t) (0x1)   /* Port pull-up */
+#define GPIO_PUPDR_DOWN (uint32_t) (0x2) /* Port pull-down */
+
+#define GPIO_IDR_PIN(n) (uint32_t) (1 << n) /* Input for pin n */
+
+#define GPIO_ODR_PIN(n) (uint32_t) (1 << n) /* Output for pin n */
+
+#define GPIO_BSRR_BS(n) (uint32_t) (1 << n)        /* Set pin n */
+#define GPIO_BSRR_BR(n) (uint32_t) (1 << (n + 16)) /* Reset pin n */
+
+#define GPIO_AFRL_PIN(n) (uint32_t) (4 * n)              /* Pin bitshift */
+#define GPIO_AFRL_M(n) (uint32_t) (0xF << (4 * n))       /* Pin mask */
+#define GPIO_AFRH_PIN(n) (uint32_t) (4 * (n - 8))        /* Pin bitshift */
+#define GPIO_AFRH_M(n) (uint32_t) (0xF << (4 * (n - 8))) /* Pin mask */
 
 /* DMA */
-#define DMA_LISR_TCIF2                  (uint32_t) (1 << 21)                                    /* DMA stream 2 transfer complete flag */
-#define DMA_HISR_TCIF7                  (uint32_t) (1 << 27)                                    /* DMA stream 7 transfer complete flag */
-#define DMA_LIFCR_CTCIF2                (uint32_t) (1 << 21)                                    /* DMA clear stream 2 transfer complete flag */
-#define DMA_HIFCR_CTCIF7                (uint32_t) (1 << 27)                                    /* DMA clear stream 7 transfer complete flag */
-
-#define DMA_SxCR_EN                     (uint32_t) (1 << 0)                                     /* DMA stream enable */
-#define DMA_SxCR_DMEIE                  (uint32_t) (1 << 1)                                     /* DMA stream direct mode error interrupt enable */
-#define DMA_SxCR_TEIE                   (uint32_t) (1 << 2)                                     /* DMA stream transmit error interrupt enable */
-#define DMA_SxCR_HTIE                   (uint32_t) (1 << 3)                                     /* DMA stream half transfer interrupt enable */
-#define DMA_SxCR_TCIE                   (uint32_t) (1 << 4)                                     /* DMA stream transfer complete interrupt enable */
-#define DMA_SxCR_PFCTRL                 (uint32_t) (1 << 5)                                     /* DMA stream peripheral flow control */
-#define DMA_SxCR_DIR_PM                 (uint32_t) (0 << 6)                                     /* DMA stream peripheral-to-memory data transfer */
-#define DMA_SxCR_DIR_MP                 (uint32_t) (1 << 6)                                     /* DMA stream memory-to-peripheral data transfer */
-#define DMA_SxCR_DIR_MM                 (uint32_t) (2 << 6)                                     /* DMA stream memory-to-memory data transfer */
-#define DMA_SxCR_CIRC                   (uint32_t) (1 << 8)                                     /* DMA stream circular mode enable */
-#define DMA_SxCR_PINC                   (uint32_t) (1 << 9)                                     /* DMA stream peripheral increment mode enable */
-#define DMA_SxCR_MINC                   (uint32_t) (1 << 10)                                    /* DMA stream memory increment mode enable */
-#define DMA_SxCR_PSIZE_BYTE             (uint32_t) (0 << 11)                                    /* DMA stream peripheral data size - Byte */
-#define DMA_SxCR_PSIZE_HW               (uint32_t) (1 << 11)                                    /* DMA stream peripheral data size - Half-word */
-#define DMA_SxCR_PSIZE_WORD             (uint32_t) (2 << 11)                                    /* DMA stream peripheral data size - Word */
-#define DMA_SxCR_MSIZE_BYTE             (uint32_t) (0 << 13)                                    /* DMA stream memory data size - Byte */
-#define DMA_SxCR_MSIZE_HW               (uint32_t) (1 << 13)                                    /* DMA stream memory data size - Half-word */
-#define DMA_SxCR_MSIZE_WORD             (uint32_t) (2 << 13)                                    /* DMA stream memory data size - Word */
-#define DMA_SxCR_PINCOS_LINKED          (uint32_t) (0 << 15)                                    /* DMA stream peripheral increment offset size linked to PSIZE */
-#define DMA_SxCR_PINCOS_FIXED           (uint32_t) (1 << 15)                                    /* DMA stream peripheral increment offset size fixed */
-#define DMA_SxCR_PL_LOW                 (uint32_t) (0 << 16)                                    /* DMA stream priority level low */
-#define DMA_SxCR_PL_MED                 (uint32_t) (1 << 16)                                    /* DMA stream priority level medium */
-#define DMA_SxCR_PL_HIGH                (uint32_t) (2 << 16)                                    /* DMA stream priority level high */
-#define DMA_SxCR_PL_VHIGH               (uint32_t) (3 << 16)                                    /* DMA stream priority level very high */
-#define DMA_SxCR_DBM                    (uint32_t) (1 << 18)                                    /* DMA stream double buffer mode */
-#define DMA_SxCR_CT                     (uint32_t) (1 << 19)                                    /* DMA stream current target (M0 or M1) */
-#define DMA_SxCR_PBURST_NO              (uint32_t) (0 << 21)                                    /* DMA stream peripheral burst disable */
-#define DMA_SxCR_PBURST_4               (uint32_t) (1 << 21)                                    /* DMA stream peripheral burst of 4 beats */
-#define DMA_SxCR_PBURST_8               (uint32_t) (2 << 21)                                    /* DMA stream peripheral burst of 8 beats */
-#define DMA_SxCR_PBURST_16              (uint32_t) (3 << 21)                                    /* DMA stream peripheral burst of 16 beats */
-#define DMA_SxCR_MBURST_NO              (uint32_t) (0 << 23)                                    /* DMA stream memory burst disable */
-#define DMA_SxCR_MBURST_4               (uint32_t) (1 << 23)                                    /* DMA stream memory burst of 4 beats */
-#define DMA_SxCR_MBURST_8               (uint32_t) (2 << 23)                                    /* DMA stream memory burst of 8 beats */
-#define DMA_SxCR_MBURST_16              (uint32_t) (3 << 23)                                    /* DMA stream memory burst of 16 beats */
-#define DMA_SxCR_CHSEL(x)               (uint32_t) (x << 25)                                    /* DMA stream channel select */
-
-#define DMA_SxFCR_FTH_1                 (uint32_t) (0 << 0)                                     /* DMA stream FIFO threshold 1/4 */
-#define DMA_SxFCR_FTH_2                 (uint32_t) (1 << 0)                                     /* DMA stream FIFO threshold 1/2 */
-#define DMA_SxFCR_FTH_3                 (uint32_t) (2 << 0)                                     /* DMA stream FIFO threshold 3/4 */
-#define DMA_SxFCR_FTH_4                 (uint32_t) (3 << 0)                                     /* DMA stream FIFO threshold full*/
-#define DMA_SxFCR_DMDIS                 (uint32_t) (1 << 2)                                     /* DMA stream direct mode disable */
-#define DMA_SxFCR_FS                    (uint32_t) (7 << 3)                                     /* DMA stream FIFO status */
-#define DMA_SxFCR_FEIE                  (uint32_t) (1 << 7)                                     /* DMA stream FIFO error interrupt enable */
+#define DMA_LISR_TCIF2 \
+    (uint32_t) (1 << 21) /* DMA stream 2 transfer complete flag */
+#define DMA_HISR_TCIF7 \
+    (uint32_t) (1 << 27) /* DMA stream 7 transfer complete flag */
+#define DMA_LIFCR_CTCIF2 \
+    (uint32_t) (1 << 21) /* DMA clear stream 2 transfer complete flag */
+#define DMA_HIFCR_CTCIF7 \
+    (uint32_t) (1 << 27) /* DMA clear stream 7 transfer complete flag */
+
+#define DMA_SxCR_EN (uint32_t) (1 << 0) /* DMA stream enable */
+#define DMA_SxCR_DMEIE \
+    (uint32_t) (1 << 1) /* DMA stream direct mode error interrupt enable */
+#define DMA_SxCR_TEIE \
+    (uint32_t) (1 << 2) /* DMA stream transmit error interrupt enable */
+#define DMA_SxCR_HTIE \
+    (uint32_t) (1 << 3) /* DMA stream half transfer interrupt enable */
+#define DMA_SxCR_TCIE \
+    (uint32_t) (1 << 4) /* DMA stream transfer complete interrupt enable */
+#define DMA_SxCR_PFCTRL \
+    (uint32_t) (1 << 5) /* DMA stream peripheral flow control */
+#define DMA_SxCR_DIR_PM \
+    (uint32_t) (0 << 6) /* DMA stream peripheral-to-memory data transfer */
+#define DMA_SxCR_DIR_MP \
+    (uint32_t) (1 << 6) /* DMA stream memory-to-peripheral data transfer */
+#define DMA_SxCR_DIR_MM \
+    (uint32_t) (2 << 6) /* DMA stream memory-to-memory data transfer */
+#define DMA_SxCR_CIRC                                      \
+    (uint32_t) (1 << 8) /* DMA stream circular mode enable \
+                         */
+#define DMA_SxCR_PINC \
+    (uint32_t) (1 << 9) /* DMA stream peripheral increment mode enable */
+#define DMA_SxCR_MINC \
+    (uint32_t) (1 << 10) /* DMA stream memory increment mode enable */
+#define DMA_SxCR_PSIZE_BYTE \
+    (uint32_t) (0 << 11) /* DMA stream peripheral data size - Byte */
+#define DMA_SxCR_PSIZE_HW \
+    (uint32_t) (1 << 11) /* DMA stream peripheral data size - Half-word */
+#define DMA_SxCR_PSIZE_WORD \
+    (uint32_t) (2 << 11) /* DMA stream peripheral data size - Word */
+#define DMA_SxCR_MSIZE_BYTE \
+    (uint32_t) (0 << 13) /* DMA stream memory data size - Byte */
+#define DMA_SxCR_MSIZE_HW \
+    (uint32_t) (1 << 13) /* DMA stream memory data size - Half-word */
+#define DMA_SxCR_MSIZE_WORD \
+    (uint32_t) (2 << 13) /* DMA stream memory data size - Word */
+#define DMA_SxCR_PINCOS_LINKED                                                 \
+    (uint32_t) (0 << 15) /* DMA stream peripheral increment offset size linked \
+                            to PSIZE */
+#define DMA_SxCR_PINCOS_FIXED                                                 \
+    (uint32_t) (1 << 15) /* DMA stream peripheral increment offset size fixed \
+                          */
+#define DMA_SxCR_PL_LOW                                   \
+    (uint32_t) (0 << 16) /* DMA stream priority level low \
+                          */
+#define DMA_SxCR_PL_MED \
+    (uint32_t) (1 << 16) /* DMA stream priority level medium */
+#define DMA_SxCR_PL_HIGH \
+    (uint32_t) (2 << 16) /* DMA stream priority level high */
+#define DMA_SxCR_PL_VHIGH \
+    (uint32_t) (3 << 16) /* DMA stream priority level very high */
+#define DMA_SxCR_DBM (uint32_t) (1 << 18) /* DMA stream double buffer mode */
+#define DMA_SxCR_CT \
+    (uint32_t) (1 << 19) /* DMA stream current target (M0 or M1) */
+#define DMA_SxCR_PBURST_NO \
+    (uint32_t) (0 << 21) /* DMA stream peripheral burst disable */
+#define DMA_SxCR_PBURST_4 \
+    (uint32_t) (1 << 21) /* DMA stream peripheral burst of 4 beats */
+#define DMA_SxCR_PBURST_8 \
+    (uint32_t) (2 << 21) /* DMA stream peripheral burst of 8 beats */
+#define DMA_SxCR_PBURST_16 \
+    (uint32_t) (3 << 21) /* DMA stream peripheral burst of 16 beats */
+#define DMA_SxCR_MBURST_NO \
+    (uint32_t) (0 << 23) /* DMA stream memory burst disable */
+#define DMA_SxCR_MBURST_4 \
+    (uint32_t) (1 << 23) /* DMA stream memory burst of 4 beats */
+#define DMA_SxCR_MBURST_8 \
+    (uint32_t) (2 << 23) /* DMA stream memory burst of 8 beats */
+#define DMA_SxCR_MBURST_16 \
+    (uint32_t) (3 << 23) /* DMA stream memory burst of 16 beats */
+#define DMA_SxCR_CHSEL(x) (uint32_t) (x << 25) /* DMA stream channel select */
+
+#define DMA_SxFCR_FTH_1                                  \
+    (uint32_t) (0 << 0) /* DMA stream FIFO threshold 1/4 \
+                         */
+#define DMA_SxFCR_FTH_2                                  \
+    (uint32_t) (1 << 0) /* DMA stream FIFO threshold 1/2 \
+                         */
+#define DMA_SxFCR_FTH_3                                  \
+    (uint32_t) (2 << 0) /* DMA stream FIFO threshold 3/4 \
+                         */
+#define DMA_SxFCR_FTH_4                              \
+    (uint32_t) (3 << 0) /* DMA stream FIFO threshold \
+                           full*/
+#define DMA_SxFCR_DMDIS                                                    \
+    (uint32_t) (1 << 2)                  /* DMA stream direct mode disable \
+                                          */
+#define DMA_SxFCR_FS (uint32_t) (7 << 3) /* DMA stream FIFO status */
+#define DMA_SxFCR_FEIE \
+    (uint32_t) (1 << 7) /* DMA stream FIFO error interrupt enable */
 
 /* USB FS */
 /* Global Registers */
-#define USB_FS_GOTGCTL_SRQSCS           (uint32_t) (1 << 0)                                     /* USB session request success */
-#define USB_FS_GOTGCTL_SRQ              (uint32_t) (1 << 1)                                     /* USB session request */
-#define USB_FS_GOTGCTL_HNGSCS           (uint32_t) (1 << 8)                                     /* USB host negotiation success */
-#define USB_FS_GOTGCTL_HNP              (uint32_t) (1 << 9)                                     /* USB HNP request */
-#define USB_FS_GOTGCTL_HSHNPEN          (uint32_t) (1 << 10)                                    /* USB host set HPN enable */
-#define USB_FS_GOTGCTL_DHNPEN           (uint32_t) (1 << 11)                                    /* USB device HPN enabled */
-#define USB_FS_GOTGCTL_CIDSTS           (uint32_t) (1 << 16)                                    /* USB connector ID status */
-#define USB_FS_GOTGCTL_DBCT             (uint32_t) (1 << 17)                                    /* USB debounce time */
-#define USB_FS_GOTGCTL_ASVLD            (uint32_t) (1 << 18)                                    /* USB A session valid */
-#define USB_FS_GOTGCTL_BSVLD            (uint32_t) (1 << 19)                                    /* USB B session valid */
-
-#define USB_FS_GOTGINT_SEDET            (uint32_t) (1 << 2)                                     /* USB session end detected */
-#define USB_FS_GOTGINT_SRSSCHG          (uint32_t) (1 << 8)                                     /* USB session request success status change */
-#define USB_FS_GOTGINT_HNSSCHG          (uint32_t) (1 << 9)                                     /* USB host negotiation success status change */
-#define USB_FS_GOTGINT_HNGDET           (uint32_t) (1 << 17)                                    /* USB host negotiation detected */
-#define USB_FS_GOTGINT_ADTOCHG          (uint32_t) (1 << 18)                                    /* USB A-device timeout change */
-#define USB_FS_GOTGINT_DBCDNE           (uint32_t) (1 << 19)                                    /* USB debounce done */
-
-#define USB_FS_GAHBCFG_GINTMSK          (uint32_t) (1 << 0)                                     /* USB global interrupt mask */
-#define USB_FS_GAHBCFG_TXFELVL          (uint32_t) (1 << 7)                                     /* USB TX FIFO empty level */
-#define USB_FS_GAHBCFG_PTXFELVL         (uint32_t) (1 << 8)                                     /* USB Periodic TX FIFO empty level */
-
-#define USB_FS_GUSBCFG_TOCAL(n)         (uint32_t) (n << 0)                                     /* USB FS timeout calibration */
-#define USB_FS_GUSBCFG_PHYSEL           (uint32_t) (1 << 7)                                     /* USB FS serial transceiver select */
-#define USB_FS_GUSBCFG_SRPCAP           (uint32_t) (1 << 8)                                     /* USB SRP capable */
-#define USB_FS_GUSBCFG_HNPCAP           (uint32_t) (1 << 9)                                     /* USB HNP capable */
-#define USB_FS_GUSBCFG_TRDT(n)          (uint32_t) (n << 10)                                    /* USB turnaround time (4 bits) */
-#define USB_FS_GUSBCFG_FHMOD            (uint32_t) (1 << 29)                                    /* USB force host mode */
-#define USB_FS_GUSBCFG_FDMOD            (uint32_t) (1 << 30)                                    /* USB force device mode */
-#define USB_FS_GUSBCFG_CTXPKT           (uint32_t) (1 << 31)                                    /* USB corrupt packet */
-
-#define USB_FS_GRSTCTL_CSRST            (uint32_t) (1 << 0)                                     /* USB core soft reset */
-#define USB_FS_GRSTCTL_HSRST            (uint32_t) (1 << 1)                                     /* USB HCLK soft reset */
-#define USB_FS_GRSTCTL_FCRST            (uint32_t) (1 << 2)                                     /* USB host frame counter reset */
-#define USB_FS_GRSTCTL_RXFFLSH          (uint32_t) (1 << 4)                                     /* USB RX FIFO flush */
-#define USB_FS_GRSTCTL_TXFFLSH          (uint32_t) (1 << 5)                                     /* USB TX FIFO flush */
-#define USB_FS_GRSTCTL_TXFNUM(n)        (uint32_t) (n << 6)                                     /* USB TX FIFO number */
-#define USB_FS_GRSTCTL_AHBIDL           (uint32_t) (1 << 31)                                    /* USB AHB master idle */
-
-#define USB_FS_GINTSTS_CMOD             (uint32_t) (1 << 0)                                     /* USB current mode of operation */
-#define USB_FS_GINTSTS_MMIS             (uint32_t) (1 << 1)                                     /* USB mode mismatch interrupt */
-#define USB_FS_GINTSTS_OTGINT           (uint32_t) (1 << 2)                                     /* USB OTG interrupt */
-#define USB_FS_GINTSTS_SOF              (uint32_t) (1 << 3)                                     /* USB start of frame */
-#define USB_FS_GINTSTS_RXFLVL           (uint32_t) (1 << 4)                                     /* USB RX FIFO non-empty */
-#define USB_FS_GINTSTS_NPTXFE           (uint32_t) (1 << 5)                                     /* USB non-periodic TX FIFO empty */
-#define USB_FS_GINTSTS_GINAKEFF         (uint32_t) (1 << 6)                                     /* USB global IN non-periodic NAK effective */
-#define USB_FS_GINTSTS_GONAKEFF         (uint32_t) (1 << 7)                                     /* USB global OUT NAK effective */
-#define USB_FS_GINTSTS_ESUSP            (uint32_t) (1 << 10)                                    /* USB early suspend */
-#define USB_FS_GINTSTS_USBSUSP          (uint32_t) (1 << 11)                                    /* USB suspend */
-#define USB_FS_GINTSTS_USBRST           (uint32_t) (1 << 12)                                    /* USB reset */
-#define USB_FS_GINTSTS_ENUMDNE          (uint32_t) (1 << 13)                                    /* USB enumeration done */
-#define USB_FS_GINTSTS_ISOODRP          (uint32_t) (1 << 14)                                    /* USB isochronous OUT packet dropped interrupt */
-#define USB_FS_GINTSTS_EOPF             (uint32_t) (1 << 15)                                    /* USB end of packet frame interrupt */
-#define USB_FS_GINTSTS_IEPINT           (uint32_t) (1 << 18)                                    /* USB IN endpoint interrupt */
-#define USB_FS_GINTSTS_OEPINT           (uint32_t) (1 << 19)                                    /* USB OUT endpoint interrupt */
-#define USB_FS_GINTSTS_IISOIXFR         (uint32_t) (1 << 20)                                    /* USB incomplete isochronous IN transfer */
-#define USB_FS_GINTSTS_IISOOXFR         (uint32_t) (1 << 21)                                    /* USB incomplete isochronous OUT transfer */
-#define USB_FS_GINTSTS_IPXFR            (uint32_t) (1 << 21)                                    /* USB incomplete periodic transfer */
-#define USB_FS_GINTSTS_HPRTINT          (uint32_t) (1 << 24)                                    /* USB host port interrupt */
-#define USB_FS_GINTSTS_HCINT            (uint32_t) (1 << 25)                                    /* USB host channels interrupt */
-#define USB_FS_GINTSTS_PTXFE            (uint32_t) (1 << 26)                                    /* USB periodic TX FIFO empty */
-#define USB_FS_GINTSTS_CIDSCHG          (uint32_t) (1 << 28)                                    /* USB connector ID status change */
-#define USB_FS_GINTSTS_DISCINT          (uint32_t) (1 << 29)                                    /* USB disconnect detected interrupt */
-#define USB_FS_GINTSTS_SRQINT           (uint32_t) (1 << 30)                                    /* USB session request/new session detected interrupt */
-#define USB_FS_GINTSTS_WKUPINT          (uint32_t) (1 << 31)                                    /* USB resume/remote wakeup detected interrupt */
-
-#define USB_FS_GINTMSK_MMISM            (uint32_t) (1 << 1)                                     /* USB mode mismatch interrupt mask */
-#define USB_FS_GINTMSK_OTGINT           (uint32_t) (1 << 2)                                     /* USB OTG interrupt mask */
-#define USB_FS_GINTMSK_SOFM             (uint32_t) (1 << 3)                                     /* USB start of frame mask */
-#define USB_FS_GINTMSK_RXFLVLM          (uint32_t) (1 << 4)                                     /* USB RX FIFO non-empty mask */
-#define USB_FS_GINTMSK_NPTXFEM          (uint32_t) (1 << 5)                                     /* USB non-periodic TX FIFO empty mask */
-#define USB_FS_GINTMSK_GINAKEFFM        (uint32_t) (1 << 6)                                     /* USB global IN non-periodic NAK effective mask */
-#define USB_FS_GINTMSK_GONAKEFFM        (uint32_t) (1 << 7)                                     /* USB global OUT NAK effective mask */
-#define USB_FS_GINTMSK_ESUSPM           (uint32_t) (1 << 10)                                    /* USB early suspend mask */
-#define USB_FS_GINTMSK_USBSUSPM         (uint32_t) (1 << 11)                                    /* USB suspend mask */
-#define USB_FS_GINTMSK_USBRSTM          (uint32_t) (1 << 12)                                    /* USB reset mask */
-#define USB_FS_GINTMSK_ENUMDNEM         (uint32_t) (1 << 13)                                    /* USB enumeration done mask */
-#define USB_FS_GINTMSK_ISOODRPM         (uint32_t) (1 << 14)                                    /* USB isochronous OUT packet dropped interrupt mask */
-#define USB_FS_GINTMSK_EOPFM            (uint32_t) (1 << 15)                                    /* USB end of packet frame interrupt mask */
-#define USB_FS_GINTMSK_EPMISM           (uint32_t) (1 << 17)                                    /* USB endpoint mismatch interrupt mask */
-#define USB_FS_GINTMSK_IEPINT           (uint32_t) (1 << 18)                                    /* USB IN endpoint interrupt mask */
-#define USB_FS_GINTMSK_OEPINT           (uint32_t) (1 << 19)                                    /* USB OUT endpoint interrupt mask */
-#define USB_FS_GINTMSK_IISOIXFRM        (uint32_t) (1 << 20)                                    /* USB incomplete isochronous IN transfer mask */
-#define USB_FS_GINTMSK_IISOOXFRM        (uint32_t) (1 << 21)                                    /* USB incomplete isochronous OUT transfer mask */
-#define USB_FS_GINTMSK_IPXFRM           (uint32_t) (1 << 21)                                    /* USB incomplete periodic transfer mask */
-#define USB_FS_GINTMSK_HPRTINT          (uint32_t) (1 << 24)                                    /* USB host port interrupt mask */
-#define USB_FS_GINTMSK_HCINT            (uint32_t) (1 << 25)                                    /* USB host channels interrupt mask */
-#define USB_FS_GINTMSK_PTXFEM           (uint32_t) (1 << 26)                                    /* USB periodic TX FIFO empty mask */
-#define USB_FS_GINTMSK_CIDSCHGM         (uint32_t) (1 << 28)                                    /* USB connector ID status change mask */
-#define USB_FS_GINTMSK_DISCINT          (uint32_t) (1 << 29)                                    /* USB disconnect detected interrupt mask */
-#define USB_FS_GINTMSK_SRQINT           (uint32_t) (1 << 30)                                    /* USB session request/new session detected interrupt mask */
-#define USB_FS_GINTMSK_WKUPINT          (uint32_t) (1 << 31)                                    /* USB resume/remote wakeup detected interrupt mask */
-
-#define USB_FS_GRXSTS_EPNUM(r)          (uint32_t) (r & 0xF)                                    /* USB RX FIFO endpoint number */
-#define USB_FS_GRXSTS_BCNT(r)           (uint32_t) ((r & 0x7FF0) >> 4)                          /* USB RX FIFO byte count */
-#define USB_FS_GRXSTS_DPID(r)           (uint32_t) ((r & 0x18000) >> 15)                        /* USB RX FIFO data PID */
-#define USB_FS_GRXSTS_PKTSTS(r)         (uint32_t) ((r & 0x1E0000) >> 17)                       /* USB RX FIFO packet status */
-#define USB_FS_GRXSTS_FRMNUM(r)         (uint32_t) ((r & 0x1E00000) >> 21)                      /* USB RX FIFO frame number */
-#define USB_FS_GRXSTS_PKTSTS_NAK        (uint8_t)  (1)                                          /* USB RX FIFO packet status = global OUT NAK */
-#define USB_FS_GRXSTS_PKTSTS_ORX        (uint8_t)  (2)                                          /* USB RX FIFO packet status = OUT data packet received */
-#define USB_FS_GRXSTS_PKTSTS_OCP        (uint8_t)  (3)                                          /* USB RX FIFO packet status = OUT transfer completed */
-#define USB_FS_GRXSTS_PKTSTS_STUPCP     (uint8_t)  (4)                                          /* USB RX FIFO packet status = SETUP transaction completed */
-#define USB_FS_GRXSTS_PKTSTS_STUPRX     (uint8_t)  (6)                                          /* USB RX FIFO packet status = SETUP data packet received */
-
-#define USB_FS_DIEPTXF0_TX0FSA(n)       (uint32_t) (n << 0)                                     /* USB endpoint 0 transmit RAM start address */
-#define USB_FS_DIEPTXF0_TX0FD(n)        (uint32_t) (n << 16)                                    /* USB endpoint 0 TX FIFO depth */
-
-#define USB_FS_GCCFG_PWRDWN             (uint32_t) (1 << 16)                                    /* USB power down */
-#define USB_FS_GCCFG_VBUSASEN           (uint32_t) (1 << 18)                                    /* USB VBUS "A" sensing enable */
-#define USB_FS_GCCFG_VBUSBSEN           (uint32_t) (1 << 19)                                    /* USB VBUS "B" sensing enable */
-#define USB_FS_GCCFG_SOFOUTEN           (uint32_t) (1 << 20)                                    /* USB SOF output enable */
-#define USB_FS_GCCFG_NOVBUSSSENS        (uint32_t) (1 << 21)                                    /* USB VBUS sensing disable */
-
-#define USB_FS_DIEPTXF_INEPTXSA(n)      (uint32_t) (n << 0)                                     /* USB IN endpoint FIFOx transmit RAM start address */
-#define USB_FS_DIEPTXF_INEPTXFD(n)      (uint32_t) (n << 16)                                    /* USB IN endpoint TX FIFOx depth */
+#define USB_FS_GOTGCTL_SRQSCS \
+    (uint32_t) (1 << 0)                        /* USB session request success */
+#define USB_FS_GOTGCTL_SRQ (uint32_t) (1 << 1) /* USB session request */
+#define USB_FS_GOTGCTL_HNGSCS \
+    (uint32_t) (1 << 8) /* USB host negotiation success */
+#define USB_FS_GOTGCTL_HNP (uint32_t) (1 << 9) /* USB HNP request */
+#define USB_FS_GOTGCTL_HSHNPEN \
+    (uint32_t) (1 << 10) /* USB host set HPN enable */
+#define USB_FS_GOTGCTL_DHNPEN                      \
+    (uint32_t) (1 << 11) /* USB device HPN enabled \
+                          */
+#define USB_FS_GOTGCTL_CIDSTS                                                \
+    (uint32_t) (1 << 16)                          /* USB connector ID status \
+                                                   */
+#define USB_FS_GOTGCTL_DBCT (uint32_t) (1 << 17)  /* USB debounce time */
+#define USB_FS_GOTGCTL_ASVLD (uint32_t) (1 << 18) /* USB A session valid */
+#define USB_FS_GOTGCTL_BSVLD (uint32_t) (1 << 19) /* USB B session valid */
+
+#define USB_FS_GOTGINT_SEDET                        \
+    (uint32_t) (1 << 2) /* USB session end detected \
+                         */
+#define USB_FS_GOTGINT_SRSSCHG \
+    (uint32_t) (1 << 8) /* USB session request success status change */
+#define USB_FS_GOTGINT_HNSSCHG \
+    (uint32_t) (1 << 9) /* USB host negotiation success status change */
+#define USB_FS_GOTGINT_HNGDET \
+    (uint32_t) (1 << 17) /* USB host negotiation detected */
+#define USB_FS_GOTGINT_ADTOCHG \
+    (uint32_t) (1 << 18) /* USB A-device timeout change */
+#define USB_FS_GOTGINT_DBCDNE (uint32_t) (1 << 19) /* USB debounce done */
+
+#define USB_FS_GAHBCFG_GINTMSK \
+    (uint32_t) (1 << 0) /* USB global interrupt mask */
+#define USB_FS_GAHBCFG_TXFELVL                     \
+    (uint32_t) (1 << 7) /* USB TX FIFO empty level \
+                         */
+#define USB_FS_GAHBCFG_PTXFELVL \
+    (uint32_t) (1 << 8) /* USB Periodic TX FIFO empty level */
+
+#define USB_FS_GUSBCFG_TOCAL(n) \
+    (uint32_t) (n << 0) /* USB FS timeout calibration */
+#define USB_FS_GUSBCFG_PHYSEL \
+    (uint32_t) (1 << 7) /* USB FS serial transceiver select */
+#define USB_FS_GUSBCFG_SRPCAP (uint32_t) (1 << 8) /* USB SRP capable */
+#define USB_FS_GUSBCFG_HNPCAP (uint32_t) (1 << 9) /* USB HNP capable */
+#define USB_FS_GUSBCFG_TRDT(n) \
+    (uint32_t) (n << 10) /* USB turnaround time (4 bits) */
+#define USB_FS_GUSBCFG_FHMOD (uint32_t) (1 << 29)  /* USB force host mode */
+#define USB_FS_GUSBCFG_FDMOD (uint32_t) (1 << 30)  /* USB force device mode */
+#define USB_FS_GUSBCFG_CTXPKT (uint32_t) (1 << 31) /* USB corrupt packet */
+
+#define USB_FS_GRSTCTL_CSRST (uint32_t) (1 << 0) /* USB core soft reset */
+#define USB_FS_GRSTCTL_HSRST (uint32_t) (1 << 1) /* USB HCLK soft reset */
+#define USB_FS_GRSTCTL_FCRST \
+    (uint32_t) (1 << 2) /* USB host frame counter reset */
+#define USB_FS_GRSTCTL_RXFFLSH (uint32_t) (1 << 4)   /* USB RX FIFO flush */
+#define USB_FS_GRSTCTL_TXFFLSH (uint32_t) (1 << 5)   /* USB TX FIFO flush */
+#define USB_FS_GRSTCTL_TXFNUM(n) (uint32_t) (n << 6) /* USB TX FIFO number */
+#define USB_FS_GRSTCTL_AHBIDL (uint32_t) (1 << 31)   /* USB AHB master idle */
+
+#define USB_FS_GINTSTS_CMOD \
+    (uint32_t) (1 << 0) /* USB current mode of operation */
+#define USB_FS_GINTSTS_MMIS \
+    (uint32_t) (1 << 1) /* USB mode mismatch interrupt */
+#define USB_FS_GINTSTS_OTGINT (uint32_t) (1 << 2) /* USB OTG interrupt */
+#define USB_FS_GINTSTS_SOF (uint32_t) (1 << 3)    /* USB start of frame */
+#define USB_FS_GINTSTS_RXFLVL (uint32_t) (1 << 4) /* USB RX FIFO non-empty */
+#define USB_FS_GINTSTS_NPTXFE \
+    (uint32_t) (1 << 5) /* USB non-periodic TX FIFO empty */
+#define USB_FS_GINTSTS_GINAKEFF \
+    (uint32_t) (1 << 6) /* USB global IN non-periodic NAK effective */
+#define USB_FS_GINTSTS_GONAKEFF \
+    (uint32_t) (1 << 7) /* USB global OUT NAK effective */
+#define USB_FS_GINTSTS_ESUSP (uint32_t) (1 << 10)   /* USB early suspend */
+#define USB_FS_GINTSTS_USBSUSP (uint32_t) (1 << 11) /* USB suspend */
+#define USB_FS_GINTSTS_USBRST (uint32_t) (1 << 12)  /* USB reset */
+#define USB_FS_GINTSTS_ENUMDNE (uint32_t) (1 << 13) /* USB enumeration done */
+#define USB_FS_GINTSTS_ISOODRP \
+    (uint32_t) (1 << 14) /* USB isochronous OUT packet dropped interrupt */
+#define USB_FS_GINTSTS_EOPF \
+    (uint32_t) (1 << 15) /* USB end of packet frame interrupt */
+#define USB_FS_GINTSTS_IEPINT \
+    (uint32_t) (1 << 18) /* USB IN endpoint interrupt */
+#define USB_FS_GINTSTS_OEPINT \
+    (uint32_t) (1 << 19) /* USB OUT endpoint interrupt */
+#define USB_FS_GINTSTS_IISOIXFR \
+    (uint32_t) (1 << 20) /* USB incomplete isochronous IN transfer */
+#define USB_FS_GINTSTS_IISOOXFR \
+    (uint32_t) (1 << 21) /* USB incomplete isochronous OUT transfer */
+#define USB_FS_GINTSTS_IPXFR \
+    (uint32_t) (1 << 21) /* USB incomplete periodic transfer */
+#define USB_FS_GINTSTS_HPRTINT \
+    (uint32_t) (1 << 24) /* USB host port interrupt */
+#define USB_FS_GINTSTS_HCINT \
+    (uint32_t) (1 << 25) /* USB host channels interrupt */
+#define USB_FS_GINTSTS_PTXFE \
+    (uint32_t) (1 << 26) /* USB periodic TX FIFO empty */
+#define USB_FS_GINTSTS_CIDSCHG \
+    (uint32_t) (1 << 28) /* USB connector ID status change */
+#define USB_FS_GINTSTS_DISCINT \
+    (uint32_t) (1 << 29) /* USB disconnect detected interrupt */
+#define USB_FS_GINTSTS_SRQINT                                                  \
+    (uint32_t) (1 << 30) /* USB session request/new session detected interrupt \
+                          */
+#define USB_FS_GINTSTS_WKUPINT \
+    (uint32_t) (1 << 31) /* USB resume/remote wakeup detected interrupt */
+
+#define USB_FS_GINTMSK_MMISM \
+    (uint32_t) (1 << 1) /* USB mode mismatch interrupt mask */
+#define USB_FS_GINTMSK_OTGINT (uint32_t) (1 << 2) /* USB OTG interrupt mask */
+#define USB_FS_GINTMSK_SOFM (uint32_t) (1 << 3)   /* USB start of frame mask */
+#define USB_FS_GINTMSK_RXFLVLM \
+    (uint32_t) (1 << 4) /* USB RX FIFO non-empty mask */
+#define USB_FS_GINTMSK_NPTXFEM \
+    (uint32_t) (1 << 5) /* USB non-periodic TX FIFO empty mask */
+#define USB_FS_GINTMSK_GINAKEFFM \
+    (uint32_t) (1 << 6) /* USB global IN non-periodic NAK effective mask */
+#define USB_FS_GINTMSK_GONAKEFFM \
+    (uint32_t) (1 << 7) /* USB global OUT NAK effective mask */
+#define USB_FS_GINTMSK_ESUSPM                                                  \
+    (uint32_t) (1 << 10)                             /* USB early suspend mask \
+                                                      */
+#define USB_FS_GINTMSK_USBSUSPM (uint32_t) (1 << 11) /* USB suspend mask */
+#define USB_FS_GINTMSK_USBRSTM (uint32_t) (1 << 12)  /* USB reset mask */
+#define USB_FS_GINTMSK_ENUMDNEM \
+    (uint32_t) (1 << 13) /* USB enumeration done mask */
+#define USB_FS_GINTMSK_ISOODRPM                                               \
+    (uint32_t) (1 << 14) /* USB isochronous OUT packet dropped interrupt mask \
+                          */
+#define USB_FS_GINTMSK_EOPFM \
+    (uint32_t) (1 << 15) /* USB end of packet frame interrupt mask */
+#define USB_FS_GINTMSK_EPMISM \
+    (uint32_t) (1 << 17) /* USB endpoint mismatch interrupt mask */
+#define USB_FS_GINTMSK_IEPINT \
+    (uint32_t) (1 << 18) /* USB IN endpoint interrupt mask */
+#define USB_FS_GINTMSK_OEPINT \
+    (uint32_t) (1 << 19) /* USB OUT endpoint interrupt mask */
+#define USB_FS_GINTMSK_IISOIXFRM \
+    (uint32_t) (1 << 20) /* USB incomplete isochronous IN transfer mask */
+#define USB_FS_GINTMSK_IISOOXFRM \
+    (uint32_t) (1 << 21) /* USB incomplete isochronous OUT transfer mask */
+#define USB_FS_GINTMSK_IPXFRM \
+    (uint32_t) (1 << 21) /* USB incomplete periodic transfer mask */
+#define USB_FS_GINTMSK_HPRTINT \
+    (uint32_t) (1 << 24) /* USB host port interrupt mask */
+#define USB_FS_GINTMSK_HCINT \
+    (uint32_t) (1 << 25) /* USB host channels interrupt mask */
+#define USB_FS_GINTMSK_PTXFEM \
+    (uint32_t) (1 << 26) /* USB periodic TX FIFO empty mask */
+#define USB_FS_GINTMSK_CIDSCHGM \
+    (uint32_t) (1 << 28) /* USB connector ID status change mask */
+#define USB_FS_GINTMSK_DISCINT \
+    (uint32_t) (1 << 29) /* USB disconnect detected interrupt mask */
+#define USB_FS_GINTMSK_SRQINT                                                  \
+    (uint32_t) (1 << 30) /* USB session request/new session detected interrupt \
+                            mask */
+#define USB_FS_GINTMSK_WKUPINT                                               \
+    (uint32_t) (1 << 31) /* USB resume/remote wakeup detected interrupt mask \
+                          */
+
+#define USB_FS_GRXSTS_EPNUM(r) \
+    (uint32_t) (r & 0xF) /* USB RX FIFO endpoint number */
+#define USB_FS_GRXSTS_BCNT(r) \
+    (uint32_t) ((r & 0x7FF0) >> 4) /* USB RX FIFO byte count */
+#define USB_FS_GRXSTS_DPID(r) \
+    (uint32_t) ((r & 0x18000) >> 15) /* USB RX FIFO data PID */
+#define USB_FS_GRXSTS_PKTSTS(r) \
+    (uint32_t) ((r & 0x1E0000) >> 17) /* USB RX FIFO packet status */
+#define USB_FS_GRXSTS_FRMNUM(r) \
+    (uint32_t) ((r & 0x1E00000) >> 21) /* USB RX FIFO frame number */
+#define USB_FS_GRXSTS_PKTSTS_NAK \
+    (uint8_t) (1) /* USB RX FIFO packet status = global OUT NAK */
+#define USB_FS_GRXSTS_PKTSTS_ORX \
+    (uint8_t) (2) /* USB RX FIFO packet status = OUT data packet received */
+#define USB_FS_GRXSTS_PKTSTS_OCP \
+    (uint8_t) (3) /* USB RX FIFO packet status = OUT transfer completed */
+#define USB_FS_GRXSTS_PKTSTS_STUPCP                                          \
+    (uint8_t) (4) /* USB RX FIFO packet status = SETUP transaction completed \
+                   */
+#define USB_FS_GRXSTS_PKTSTS_STUPRX \
+    (uint8_t) (6) /* USB RX FIFO packet status = SETUP data packet received */
+
+#define USB_FS_DIEPTXF0_TX0FSA(n) \
+    (uint32_t) (n << 0) /* USB endpoint 0 transmit RAM start address */
+#define USB_FS_DIEPTXF0_TX0FD(n) \
+    (uint32_t) (n << 16) /* USB endpoint 0 TX FIFO depth */
+
+#define USB_FS_GCCFG_PWRDWN (uint32_t) (1 << 16) /* USB power down */
+#define USB_FS_GCCFG_VBUSASEN \
+    (uint32_t) (1 << 18) /* USB VBUS "A" sensing enable */
+#define USB_FS_GCCFG_VBUSBSEN \
+    (uint32_t) (1 << 19) /* USB VBUS "B" sensing enable */
+#define USB_FS_GCCFG_SOFOUTEN (uint32_t) (1 << 20) /* USB SOF output enable */
+#define USB_FS_GCCFG_NOVBUSSSENS \
+    (uint32_t) (1 << 21) /* USB VBUS sensing disable */
+
+#define USB_FS_DIEPTXF_INEPTXSA(n) \
+    (uint32_t) (n << 0) /* USB IN endpoint FIFOx transmit RAM start address */
+#define USB_FS_DIEPTXF_INEPTXFD(n) \
+    (uint32_t) (n << 16) /* USB IN endpoint TX FIFOx depth */
 
 /* Device-mode Registers */
-#define USB_FS_DCFG_DSPD_FS             (uint32_t) (1 << 1 | 1 << 0)                            /* USB device speed: full speed (USB 1.1) */
-#define USB_FS_DCFG_NZLSOHSK            (uint32_t) (1 << 2)                                     /* USB device non-zero-length status OUT handshake */
-#define USB_FS_DCFG_DAD(x)              (uint32_t) (x << 4)                                     /* USB device address */
-#define USB_FS_DCFG_PFIVL_80            (uint32_t) (0 << 11)                                    /* USB device periodic frame interval: 80% */
-#define USB_FS_DCFG_PFIVL_85            (uint32_t) (1 << 11)                                    /* USB device periodic frame interval: 85% */
-#define USB_FS_DCFG_PFIVL_90            (uint32_t) (2 << 11)                                    /* USB device periodic frame interval: 90% */
-#define USB_FS_DCFG_PFIVL_95            (uint32_t) (3 << 11)                                    /* USB device periodic frame interval: 95% */
-
-#define USB_FS_DCTL_RWUSIG              (uint32_t) (1 << 0)                                     /* USB device remote wakeup signaling */
-#define USB_FS_DCTL_SDIS                (uint32_t) (1 << 1)                                     /* USB device soft disconnect */
-#define USB_FS_DCTL_GINSTS              (uint32_t) (1 << 2)                                     /* USB device global IN NAK status */
-#define USB_FS_DCTL_GONSTS              (uint32_t) (1 << 3)                                     /* USB device global OUT NAK status */
-#define USB_FS_DCTL_TCTL_J              (uint32_t) (1 << 4)                                     /* USB device Test_J mode */
-#define USB_FS_DCTL_TCTL_K              (uint32_t) (2 << 4)                                     /* USB device Test_K mode */
-#define USB_FS_DCTL_TCTL_SE0_NAK        (uint32_t) (3 << 4)                                     /* USB device Test_SE0_NAK mode */
-#define USB_FS_DCTL_TCTL_PKT            (uint32_t) (4 << 4)                                     /* USB device Test_Packet mode */
-#define USB_FS_DCTL_TCTL_FEN            (uint32_t) (5 << 4)                                     /* USB device Test_Force_Enable mode */
-#define USB_FS_DCTL_SGINAK              (uint32_t) (1 << 7)                                     /* USB device set global IN NAK */
-#define USB_FS_DCTL_CGINAK              (uint32_t) (1 << 8)                                     /* USB device clear global IN NAK */
-#define USB_FS_DCTL_SGONAK              (uint32_t) (1 << 9)                                     /* USB device set global OUT NAK */
-#define USB_FS_DCTL_CGONAK              (uint32_t) (1 << 10)                                    /* USB device clear global OUT NAK */
-#define USB_FS_DCTL_POPRGDNE            (uint32_t) (1 << 11)                                    /* USB device power-no programming done */
-
-#define USB_FS_DSTS_SUSPSTS             (uint32_t) (1 << 0)                                     /* USB device suspend status */
-#define USB_FS_DSTS_ENUMSPD             (uint32_t) (3 << 1)                                     /* USB device enumerated speed (Must == 3) */
-#define USB_FS_DSTS_ENUMSPD_FS          (uint32_t) (3 << 1)                                          /* USB device enumerated speed (Must == 3) */
-#define USB_FS_DSTS_EERR                (uint32_t) (1 << 3)                                     /* USB device erratic error */
-#define USB_FS_DSTS_FNSOF               (uint32_t) (0x3FFF00)                                   /* USB device frame number of received SOF (bits 21:8) */
-
-#define USB_FS_DIEPMSK_XFRCM            (uint32_t) (1 << 0)                                     /* USB device transfer completed interrupt mask */
-#define USB_FS_DIEPMSK_EPDM             (uint32_t) (1 << 1)                                     /* USB device endpoint disabled interrupt mask */
-#define USB_FS_DIEPMSK_TOM              (uint32_t) (1 << 3)                                     /* USB device timout condition mask */
-#define USB_FS_DIEPMSK_ITTXFEMSK        (uint32_t) (1 << 4)                                     /* USB device IN token received when TX FIFO empty mask */
-#define USB_FS_DIEPMSK_INEPNMM          (uint32_t) (1 << 5)                                     /* USB device IN token received with EP mismatch mask */
-#define USB_FS_DIEPMSK_INEPNEM          (uint32_t) (1 << 6)                                     /* USB device IN endpoint NAK effective mask */
-
-#define USB_FS_DOEPMSK_XFRCM            (uint32_t) (1 << 0)                                     /* USB device transfer completed interrupt mask */
-#define USB_FS_DOEPMSK_EPDM             (uint32_t) (1 << 1)                                     /* USB device endpoint disabled interrupt mask */
-#define USB_FS_DOEPMSK_STUPM            (uint32_t) (1 << 3)                                     /* USB device SETUP phase done mask */
-#define USB_FS_DOEPMSK_OTEPDM           (uint32_t) (1 << 4)                                     /* USB device OUT token received when endpoint disabled mask */
-
-#define USB_FS_DAINT_IEPINT(n)          (uint32_t) (1 << n)                                     /* USB device IN endpoint interrupt bits */
-#define USB_FS_DAINT_OEPINT(n)          (uint32_t) (1 << (n+16))                                /* USB device OUT endpoint interrupt bits */
-
-#define USB_FS_DAINT_IEPM(n)            (uint32_t) (1 << n)                                     /* USB device IN endpoint interrupt mask bits */
-#define USB_FS_DAINT_OEPM(n)            (uint32_t) (1 << (n+16))                                /* USB device OUT endpoint interrupt mask bits */
-
-#define USB_FS_DIEPEMPMSK_INEPTXFEM(n)  (uint32_t) (1 << n)                                     /* USB device IN EP TX FIFO empty interrupt mask bits */
-
-#define USB_FS_DIEPCTL0_MPSIZE          (uint32_t) (3 << 0)                                     /* USB device endpoint 0 IN maximum packet size */
-#define USB_FS_DIEPCTL0_MPSIZE_64       (uint32_t) (0 << 0)                                     /* USB device endpoint 0 IN maximum packet size 64 bytes */
-#define USB_FS_DIEPCTL0_MPSIZE_32       (uint32_t) (1 << 0)                                     /* USB device endpoint 0 IN maximum packet size 32 bytes */
-#define USB_FS_DIEPCTL0_MPSIZE_16       (uint32_t) (2 << 0)                                     /* USB device endpoint 0 IN maximum packet size 16 bytes */
-#define USB_FS_DIEPCTL0_MPSIZE_8        (uint32_t) (3 << 0)                                     /* USB device endpoint 0 IN maximum packet size 8 bytes */
-#define USB_FS_DIEPCTL0_USBAEP          (uint32_t) (1 << 15)                                    /* USB device endpoint 0 IN USB active endpoint (always 1) */
-#define USB_FS_DIEPCTL0_NAKSTS          (uint32_t) (1 << 17)                                    /* USB device endpoint 0 IN NAK status */
-#define USB_FS_DIEPCTL0_STALL           (uint32_t) (1 << 21)                                    /* USB device endpoint 0 IN STALL handshake */
-#define USB_FS_DIEPCTL0_TXFNUM(n)       (uint32_t) (n << 22)                                    /* USB device endpoint 0 IN TX FIFO number */
-#define USB_FS_DIEPCTL0_CNAK            (uint32_t) (1 << 26)                                    /* USB device endpoint 0 IN clear NAK */
-#define USB_FS_DIEPCTL0_SNAK            (uint32_t) (1 << 27)                                    /* USB device endpoint 0 IN set NAK */
-#define USB_FS_DIEPCTL0_EPDIS           (uint32_t) (1 << 30)                                    /* USB device endpoint 0 IN endpoint disable */
-#define USB_FS_DIEPCTL0_EPENA           (uint32_t) (1 << 31)                                    /* USB device endpoint 0 IN endpoint enable */
-
-#define USB_FS_DIEPCTLx_MPSIZE(n)       (uint32_t) (n << 0)                                     /* USB device endpoint x IN maximum packet size in bytes (11 bits) */
-#define USB_FS_DIEPCTLx_USBAEP          (uint32_t) (1 << 15)                                    /* USB device endpoint x IN USB active endpoint */
-#define USB_FS_DIEPCTLx_EONUM_EVEN      (uint32_t) (0 << 16)                                    /* USB device endpoint x IN Odd frame */
-#define USB_FS_DIEPCTLx_EONUM_ODD       (uint32_t) (1 << 16)                                    /* USB device endpoint x IN Odd frame */
-#define USB_FS_DIEPCTLx_DPID_0          (uint32_t) (0 << 16)                                    /* USB device endpoint x IN data PID 0 */
-#define USB_FS_DIEPCTLx_DPID_1          (uint32_t) (1 << 16)                                    /* USB device endpoint x IN data PID 1 */
-#define USB_FS_DIEPCTLx_NAKSTS          (uint32_t) (1 << 17)                                    /* USB device endpoint x IN NAK status */
-#define USB_FS_DIEPCTLx_EPTYP_CTL       (uint32_t) (0 << 18)                                    /* USB device endpoint x IN type: control */
-#define USB_FS_DIEPCTLx_EPTYP_ISO       (uint32_t) (1 << 18)                                    /* USB device endpoint x IN type: isochronous */
-#define USB_FS_DIEPCTLx_EPTYP_BLK       (uint32_t) (2 << 18)                                    /* USB device endpoint x IN type: bulk */
-#define USB_FS_DIEPCTLx_EPTYP_INT       (uint32_t) (3 << 18)                                    /* USB device endpoint x IN type: interrupt */
-#define USB_FS_DIEPCTLx_STALL           (uint32_t) (1 << 21)                                    /* USB device endpoint x IN STALL handshake */
-#define USB_FS_DIEPCTLx_TXFNUM(n)       (uint32_t) (n << 22)                                    /* USB device endpoint x IN TX FIFO number (4 bits) */
-#define USB_FS_DIEPCTLx_CNAK            (uint32_t) (1 << 26)                                    /* USB device endpoint x IN clear NAK */
-#define USB_FS_DIEPCTLx_SNAK            (uint32_t) (1 << 27)                                    /* USB device endpoint x IN set NAK */
-#define USB_FS_DIEPCTLx_SD0PID          (uint32_t) (1 << 28)                                    /* USB device endpoint x IN set DATA0 PID */
-#define USB_FS_DIEPCTLx_SEVNFRM         (uint32_t) (1 << 28)                                    /* USB device endpoint x IN set even frame */
-#define USB_FS_DIEPCTLx_SODDFRM         (uint32_t) (1 << 29)                                    /* USB device endpoint x IN set odd frame */
-#define USB_FS_DIEPCTLx_EPDIS           (uint32_t) (1 << 30)                                    /* USB device endpoint x IN endpoint disable */
-#define USB_FS_DIEPCTLx_EPENA           (uint32_t) (1 << 31)                                    /* USB device endpoint x IN endpoint enable */
-
-#define USB_FS_DOEPCTL0_MPSIZE          (uint32_t) (3 << 0)                                     /* USB device endpoint 0 OUT maximum packet size */
-#define USB_FS_DOEPCTL0_MPSIZE_64       (uint32_t) (0 << 0)                                     /* USB device endpoint 0 OUT maximum packet size 64 bytes */
-#define USB_FS_DOEPCTL0_MPSIZE_32       (uint32_t) (1 << 0)                                     /* USB device endpoint 0 OUT maximum packet size 32 bytes */
-#define USB_FS_DOEPCTL0_MPSIZE_16       (uint32_t) (2 << 0)                                     /* USB device endpoint 0 OUT maximum packet size 16 bytes */
-#define USB_FS_DOEPCTL0_MPSIZE_8        (uint32_t) (3 << 0)                                     /* USB device endpoint 0 OUT maximum packet size 8 bytes */
-#define USB_FS_DOEPCTL0_USBAEP          (uint32_t) (1 << 15)                                    /* USB device endpoint 0 OUT USB active endpoint (always 1) */
-#define USB_FS_DOEPCTL0_NAKSTS          (uint32_t) (1 << 17)                                    /* USB device endpoint 0 OUT NAK status */
-#define USB_FS_DOEPCTL0_SNPM            (uint32_t) (1 << 20)                                    /* USB device endpoint 0 OUT snoop mode */
-#define USB_FS_DOEPCTL0_STALL           (uint32_t) (1 << 21)                                    /* USB device endpoint 0 OUT STALL handshake */
-#define USB_FS_DOEPCTL0_CNAK            (uint32_t) (1 << 26)                                    /* USB device endpoint 0 OUT clear NAK */
-#define USB_FS_DOEPCTL0_SNAK            (uint32_t) (1 << 27)                                    /* USB device endpoint 0 OUT set NAK */
-#define USB_FS_DOEPCTL0_EPDIS           (uint32_t) (1 << 30)                                    /* USB device endpoint 0 OUT endpoint disable */
-#define USB_FS_DOEPCTL0_EPENA           (uint32_t) (1 << 31)                                    /* USB device endpoint 0 OUT endpoint enable */
-
-#define USB_FS_DOEPCTLx_MPSIZE(n)       (uint32_t) (n << 0)                                     /* USB device endpoint x OUT maximum packet size in bytes (11 bits) */
-#define USB_FS_DOEPCTLx_USBAEP          (uint32_t) (1 << 15)                                    /* USB device endpoint x OUT USB active endpoint */
-#define USB_FS_DOEPCTLx_EONUM_EVEN      (uint32_t) (0 << 16)                                    /* USB device endpoint x OUT Odd frame */
-#define USB_FS_DOEPCTLx_EONUM_ODD       (uint32_t) (1 << 16)                                    /* USB device endpoint x OUT Odd frame */
-#define USB_FS_DOEPCTLx_DPID_0          (uint32_t) (0 << 16)                                    /* USB device endpoint x OUT data PID 0 */
-#define USB_FS_DOEPCTLx_DPID_1          (uint32_t) (1 << 16)                                    /* USB device endpoint x OUT data PID 1 */
-#define USB_FS_DOEPCTLx_NAKSTS          (uint32_t) (1 << 17)                                    /* USB device endpoint x OUT NAK status */
-#define USB_FS_DOEPCTLx_EPTYP_CTL       (uint32_t) (0 << 18)                                    /* USB device endpoint x OUT type: control */
-#define USB_FS_DOEPCTLx_EPTYP_ISO       (uint32_t) (1 << 18)                                    /* USB device endpoint x OUT type: isochronous */
-#define USB_FS_DOEPCTLx_EPTYP_BLK       (uint32_t) (2 << 18)                                    /* USB device endpoint x OUT type: bulk */
-#define USB_FS_DOEPCTLx_EPTYP_INT       (uint32_t) (3 << 18)                                    /* USB device endpoint x OUT type: interrupt */
-#define USB_FS_DOEPCTLx_SNPMN           (uint32_t) (1 << 20)                                    /* USB device endpoint x OUT snoop mode */
-#define USB_FS_DOEPCTLx_STALL           (uint32_t) (1 << 21)                                    /* USB device endpoint x OUT STALL handshake */
-#define USB_FS_DOEPCTLx_CNAK            (uint32_t) (1 << 26)                                    /* USB device endpoint x OUT clear NAK */
-#define USB_FS_DOEPCTLx_SNAK            (uint32_t) (1 << 27)                                    /* USB device endpoint x OUT set NAK */
-#define USB_FS_DOEPCTLx_SD0PID          (uint32_t) (1 << 28)                                    /* USB device endpoint x OUT set DATA0 PID */
-#define USB_FS_DOEPCTLx_SEVNFRM         (uint32_t) (1 << 28)                                    /* USB device endpoint x OUT set even frame */
-#define USB_FS_DOEPCTLx_SODDFRM         (uint32_t) (1 << 29)                                    /* USB device endpoint x OUT set odd frame */
-#define USB_FS_DOEPCTLx_EPDIS           (uint32_t) (1 << 30)                                    /* USB device endpoint x OUT endpoint disable */
-#define USB_FS_DOEPCTLx_EPENA           (uint32_t) (1 << 31)                                    /* USB device endpoint x OUT endpoint enable */
-
-#define USB_FS_DIEPINTx_XFRC            (uint32_t) (1 << 0)                                     /* USB device endpoint x IN transfer complete interrupt */
-#define USB_FS_DIEPINTx_EPDISD          (uint32_t) (1 << 1)                                     /* USB device endpoint x IN endpoint disabled interrupt */
-#define USB_FS_DIEPINTx_TOC             (uint32_t) (1 << 3)                                     /* USB device endpoint x IN timeout condition */
-#define USB_FS_DIEPINTx_ITTXFE          (uint32_t) (1 << 4)                                     /* USB device endpoint x IN token received when TX FIFO is empty */
-#define USB_FS_DIEPINTx_INEPNE          (uint32_t) (1 << 6)                                     /* USB device endpoint x IN endpoint NAK effective */
-#define USB_FS_DIEPINTx_TXFE            (uint32_t) (1 << 7)                                     /* USB device endpoint x IN TX FIFO empty */
-
-#define USB_FS_DOEPINTx_XFRC            (uint32_t) (1 << 0)                                     /* USB device endpoint x OUT transfer complete interrupt */
-#define USB_FS_DOEPINTx_EPDISD          (uint32_t) (1 << 1)                                     /* USB device endpoint x OUT endpoint disabled interrupt */
-#define USB_FS_DOEPINTx_STUP            (uint32_t) (1 << 3)                                     /* USB device endpoint x OUT SETUP phase complete */
-#define USB_FS_DOEPINTx_OTEPDIS         (uint32_t) (1 << 4)                                     /* USB device endpoint x OUT token receieved when endpoint disabled */
-#define USB_FS_DOEPINTx_B2BSTUP         (uint32_t) (1 << 6)                                     /* USB device endpoint x OUT back-to-back SETUP packets received */
-
-#define USB_FS_DIEPTSIZ0_XFRSIZ(n)      (uint32_t) (n << 0)                                     /* USB device endpoint 0 IN transfer size (7 bits) */
-#define USB_FS_DIEPTSIZ0_PKTCNT(n)      (uint32_t) (n << 19)                                    /* USB device endpoint 0 IN packet count */
-
-#define USB_FS_DIEPTSIZx_XFRSIZ(n)      (uint32_t) (n << 0)                                     /* USB device endpoint x IN transfer size (19 bits) */
-#define USB_FS_DIEPTSIZx_PKTCNT(n)      (uint32_t) (n << 19)                                    /* USB device endpoint x IN packet count (10 bits) */
-#define USB_FS_DIEPTSIZx_MCNT_1         (uint32_t) (1 << 29)                                    /* USB device endpoint x IN multi count 1 */
-#define USB_FS_DIEPTSIZx_MCNT_2         (uint32_t) (2 << 29)                                    /* USB device endpoint x IN multi count 1 */
-#define USB_FS_DIEPTSIZx_MCNT_3         (uint32_t) (3 << 29)                                    /* USB device endpoint x IN multi count 1 */
-
-#define USB_FS_DOEPTSIZ0_XFRSIZ(n)      (uint32_t) (n << 0)                                     /* USB device endpoint 0 OUT transfer size (7 bits) */
-#define USB_FS_DOEPTSIZ0_PKTCNT(n)      (uint32_t) (n << 19)                                    /* USB device endpoint 0 OUT packet count */
-#define USB_FS_DOEPTSIZ0_STUPCNT(n)     (uint32_t) (n << 29)                                    /* USB device endpoint 0 OUT back-to-back SETUP packets allowed */
-
-#define USB_FS_DOEPTSIZx_XFRSIZ(n)      (uint32_t) (n << 0)                                     /* USB device endpoint x OUT transfer size (19 bits) */
-#define USB_FS_DOEPTSIZx_PKTCNT(n)      (uint32_t) (n << 19)                                    /* USB device endpoint x OUT packet count (10 bits) */
-#define USB_FS_DOEPTSIZx_STUPCNT(n)     (uint32_t) (n << 29)                                    /* USB device endpoint x OUT back-to-back SETUP packets allowed */
-#define USB_FS_DOEPTSIZx_RXDPID         (uint32_t) (1 << 29 | 1 << 30)                          /* USB device endpoint x OUT received data PID */
+#define USB_FS_DCFG_DSPD_FS \
+    (uint32_t) (1 << 1 | 1 << 0) /* USB device speed: full speed (USB 1.1) */
+#define USB_FS_DCFG_NZLSOHSK \
+    (uint32_t) (1 << 2) /* USB device non-zero-length status OUT handshake */
+#define USB_FS_DCFG_DAD(x) (uint32_t) (x << 4) /* USB device address */
+#define USB_FS_DCFG_PFIVL_80 \
+    (uint32_t) (0 << 11) /* USB device periodic frame interval: 80% */
+#define USB_FS_DCFG_PFIVL_85 \
+    (uint32_t) (1 << 11) /* USB device periodic frame interval: 85% */
+#define USB_FS_DCFG_PFIVL_90 \
+    (uint32_t) (2 << 11) /* USB device periodic frame interval: 90% */
+#define USB_FS_DCFG_PFIVL_95 \
+    (uint32_t) (3 << 11) /* USB device periodic frame interval: 95% */
+
+#define USB_FS_DCTL_RWUSIG \
+    (uint32_t) (1 << 0) /* USB device remote wakeup signaling */
+#define USB_FS_DCTL_SDIS (uint32_t) (1 << 1) /* USB device soft disconnect */
+#define USB_FS_DCTL_GINSTS \
+    (uint32_t) (1 << 2) /* USB device global IN NAK status */
+#define USB_FS_DCTL_GONSTS \
+    (uint32_t) (1 << 3) /* USB device global OUT NAK status */
+#define USB_FS_DCTL_TCTL_J (uint32_t) (1 << 4) /* USB device Test_J mode */
+#define USB_FS_DCTL_TCTL_K (uint32_t) (2 << 4) /* USB device Test_K mode */
+#define USB_FS_DCTL_TCTL_SE0_NAK \
+    (uint32_t) (3 << 4) /* USB device Test_SE0_NAK mode */
+#define USB_FS_DCTL_TCTL_PKT \
+    (uint32_t) (4 << 4) /* USB device Test_Packet mode */
+#define USB_FS_DCTL_TCTL_FEN \
+    (uint32_t) (5 << 4) /* USB device Test_Force_Enable mode */
+#define USB_FS_DCTL_SGINAK \
+    (uint32_t) (1 << 7) /* USB device set global IN NAK */
+#define USB_FS_DCTL_CGINAK \
+    (uint32_t) (1 << 8) /* USB device clear global IN NAK */
+#define USB_FS_DCTL_SGONAK \
+    (uint32_t) (1 << 9) /* USB device set global OUT NAK */
+#define USB_FS_DCTL_CGONAK \
+    (uint32_t) (1 << 10) /* USB device clear global OUT NAK */
+#define USB_FS_DCTL_POPRGDNE \
+    (uint32_t) (1 << 11) /* USB device power-no programming done */
+
+#define USB_FS_DSTS_SUSPSTS                          \
+    (uint32_t) (1 << 0) /* USB device suspend status \
+                         */
+#define USB_FS_DSTS_ENUMSPD \
+    (uint32_t) (3 << 1) /* USB device enumerated speed (Must == 3) */
+#define USB_FS_DSTS_ENUMSPD_FS \
+    (uint32_t) (3 << 1) /* USB device enumerated speed (Must == 3) */
+#define USB_FS_DSTS_EERR (uint32_t) (1 << 3) /* USB device erratic error */
+#define USB_FS_DSTS_FNSOF                                                  \
+    (uint32_t) (0x3FFF00) /* USB device frame number of received SOF (bits \
+                             21:8) */
+
+#define USB_FS_DIEPMSK_XFRCM \
+    (uint32_t) (1 << 0) /* USB device transfer completed interrupt mask */
+#define USB_FS_DIEPMSK_EPDM \
+    (uint32_t) (1 << 1) /* USB device endpoint disabled interrupt mask */
+#define USB_FS_DIEPMSK_TOM \
+    (uint32_t) (1 << 3) /* USB device timout condition mask */
+#define USB_FS_DIEPMSK_ITTXFEMSK                                           \
+    (uint32_t) (1 << 4) /* USB device IN token received when TX FIFO empty \
+                           mask */
+#define USB_FS_DIEPMSK_INEPNMM                                                \
+    (uint32_t) (1 << 5) /* USB device IN token received with EP mismatch mask \
+                         */
+#define USB_FS_DIEPMSK_INEPNEM \
+    (uint32_t) (1 << 6) /* USB device IN endpoint NAK effective mask */
+
+#define USB_FS_DOEPMSK_XFRCM \
+    (uint32_t) (1 << 0) /* USB device transfer completed interrupt mask */
+#define USB_FS_DOEPMSK_EPDM \
+    (uint32_t) (1 << 1) /* USB device endpoint disabled interrupt mask */
+#define USB_FS_DOEPMSK_STUPM \
+    (uint32_t) (1 << 3) /* USB device SETUP phase done mask */
+#define USB_FS_DOEPMSK_OTEPDM                                          \
+    (uint32_t) (1 << 4) /* USB device OUT token received when endpoint \
+                           disabled mask */
+
+#define USB_FS_DAINT_IEPINT(n) \
+    (uint32_t) (1 << n) /* USB device IN endpoint interrupt bits */
+#define USB_FS_DAINT_OEPINT(n) \
+    (uint32_t) (1 << (n + 16)) /* USB device OUT endpoint interrupt bits */
+
+#define USB_FS_DAINT_IEPM(n) \
+    (uint32_t) (1 << n) /* USB device IN endpoint interrupt mask bits */
+#define USB_FS_DAINT_OEPM(n)                                                  \
+    (uint32_t) (1 << (n + 16)) /* USB device OUT endpoint interrupt mask bits \
+                                */
+
+#define USB_FS_DIEPEMPMSK_INEPTXFEM(n)                                        \
+    (uint32_t) (1 << n) /* USB device IN EP TX FIFO empty interrupt mask bits \
+                         */
+
+#define USB_FS_DIEPCTL0_MPSIZE \
+    (uint32_t) (3 << 0) /* USB device endpoint 0 IN maximum packet size */
+#define USB_FS_DIEPCTL0_MPSIZE_64                                          \
+    (uint32_t) (0 << 0) /* USB device endpoint 0 IN maximum packet size 64 \
+                           bytes */
+#define USB_FS_DIEPCTL0_MPSIZE_32                                          \
+    (uint32_t) (1 << 0) /* USB device endpoint 0 IN maximum packet size 32 \
+                           bytes */
+#define USB_FS_DIEPCTL0_MPSIZE_16                                          \
+    (uint32_t) (2 << 0) /* USB device endpoint 0 IN maximum packet size 16 \
+                           bytes */
+#define USB_FS_DIEPCTL0_MPSIZE_8                                          \
+    (uint32_t) (3 << 0) /* USB device endpoint 0 IN maximum packet size 8 \
+                           bytes */
+#define USB_FS_DIEPCTL0_USBAEP                                           \
+    (uint32_t) (1 << 15) /* USB device endpoint 0 IN USB active endpoint \
+                            (always 1) */
+#define USB_FS_DIEPCTL0_NAKSTS \
+    (uint32_t) (1 << 17) /* USB device endpoint 0 IN NAK status */
+#define USB_FS_DIEPCTL0_STALL \
+    (uint32_t) (1 << 21) /* USB device endpoint 0 IN STALL handshake */
+#define USB_FS_DIEPCTL0_TXFNUM(n) \
+    (uint32_t) (n << 22) /* USB device endpoint 0 IN TX FIFO number */
+#define USB_FS_DIEPCTL0_CNAK \
+    (uint32_t) (1 << 26) /* USB device endpoint 0 IN clear NAK */
+#define USB_FS_DIEPCTL0_SNAK \
+    (uint32_t) (1 << 27) /* USB device endpoint 0 IN set NAK */
+#define USB_FS_DIEPCTL0_EPDIS \
+    (uint32_t) (1 << 30) /* USB device endpoint 0 IN endpoint disable */
+#define USB_FS_DIEPCTL0_EPENA \
+    (uint32_t) (1 << 31) /* USB device endpoint 0 IN endpoint enable */
+
+#define USB_FS_DIEPCTLx_MPSIZE(n)                                          \
+    (uint32_t) (n << 0) /* USB device endpoint x IN maximum packet size in \
+                           bytes (11 bits) */
+#define USB_FS_DIEPCTLx_USBAEP \
+    (uint32_t) (1 << 15) /* USB device endpoint x IN USB active endpoint */
+#define USB_FS_DIEPCTLx_EONUM_EVEN \
+    (uint32_t) (0 << 16) /* USB device endpoint x IN Odd frame */
+#define USB_FS_DIEPCTLx_EONUM_ODD \
+    (uint32_t) (1 << 16) /* USB device endpoint x IN Odd frame */
+#define USB_FS_DIEPCTLx_DPID_0 \
+    (uint32_t) (0 << 16) /* USB device endpoint x IN data PID 0 */
+#define USB_FS_DIEPCTLx_DPID_1 \
+    (uint32_t) (1 << 16) /* USB device endpoint x IN data PID 1 */
+#define USB_FS_DIEPCTLx_NAKSTS \
+    (uint32_t) (1 << 17) /* USB device endpoint x IN NAK status */
+#define USB_FS_DIEPCTLx_EPTYP_CTL \
+    (uint32_t) (0 << 18) /* USB device endpoint x IN type: control */
+#define USB_FS_DIEPCTLx_EPTYP_ISO \
+    (uint32_t) (1 << 18) /* USB device endpoint x IN type: isochronous */
+#define USB_FS_DIEPCTLx_EPTYP_BLK \
+    (uint32_t) (2 << 18) /* USB device endpoint x IN type: bulk */
+#define USB_FS_DIEPCTLx_EPTYP_INT \
+    (uint32_t) (3 << 18) /* USB device endpoint x IN type: interrupt */
+#define USB_FS_DIEPCTLx_STALL \
+    (uint32_t) (1 << 21) /* USB device endpoint x IN STALL handshake */
+#define USB_FS_DIEPCTLx_TXFNUM(n)                                            \
+    (uint32_t) (n << 22) /* USB device endpoint x IN TX FIFO number (4 bits) \
+                          */
+#define USB_FS_DIEPCTLx_CNAK \
+    (uint32_t) (1 << 26) /* USB device endpoint x IN clear NAK */
+#define USB_FS_DIEPCTLx_SNAK \
+    (uint32_t) (1 << 27) /* USB device endpoint x IN set NAK */
+#define USB_FS_DIEPCTLx_SD0PID \
+    (uint32_t) (1 << 28) /* USB device endpoint x IN set DATA0 PID */
+#define USB_FS_DIEPCTLx_SEVNFRM \
+    (uint32_t) (1 << 28) /* USB device endpoint x IN set even frame */
+#define USB_FS_DIEPCTLx_SODDFRM \
+    (uint32_t) (1 << 29) /* USB device endpoint x IN set odd frame */
+#define USB_FS_DIEPCTLx_EPDIS \
+    (uint32_t) (1 << 30) /* USB device endpoint x IN endpoint disable */
+#define USB_FS_DIEPCTLx_EPENA \
+    (uint32_t) (1 << 31) /* USB device endpoint x IN endpoint enable */
+
+#define USB_FS_DOEPCTL0_MPSIZE \
+    (uint32_t) (3 << 0) /* USB device endpoint 0 OUT maximum packet size */
+#define USB_FS_DOEPCTL0_MPSIZE_64                                           \
+    (uint32_t) (0 << 0) /* USB device endpoint 0 OUT maximum packet size 64 \
+                           bytes */
+#define USB_FS_DOEPCTL0_MPSIZE_32                                           \
+    (uint32_t) (1 << 0) /* USB device endpoint 0 OUT maximum packet size 32 \
+                           bytes */
+#define USB_FS_DOEPCTL0_MPSIZE_16                                           \
+    (uint32_t) (2 << 0) /* USB device endpoint 0 OUT maximum packet size 16 \
+                           bytes */
+#define USB_FS_DOEPCTL0_MPSIZE_8                                           \
+    (uint32_t) (3 << 0) /* USB device endpoint 0 OUT maximum packet size 8 \
+                           bytes */
+#define USB_FS_DOEPCTL0_USBAEP                                            \
+    (uint32_t) (1 << 15) /* USB device endpoint 0 OUT USB active endpoint \
+                            (always 1) */
+#define USB_FS_DOEPCTL0_NAKSTS \
+    (uint32_t) (1 << 17) /* USB device endpoint 0 OUT NAK status */
+#define USB_FS_DOEPCTL0_SNPM \
+    (uint32_t) (1 << 20) /* USB device endpoint 0 OUT snoop mode */
+#define USB_FS_DOEPCTL0_STALL \
+    (uint32_t) (1 << 21) /* USB device endpoint 0 OUT STALL handshake */
+#define USB_FS_DOEPCTL0_CNAK \
+    (uint32_t) (1 << 26) /* USB device endpoint 0 OUT clear NAK */
+#define USB_FS_DOEPCTL0_SNAK \
+    (uint32_t) (1 << 27) /* USB device endpoint 0 OUT set NAK */
+#define USB_FS_DOEPCTL0_EPDIS \
+    (uint32_t) (1 << 30) /* USB device endpoint 0 OUT endpoint disable */
+#define USB_FS_DOEPCTL0_EPENA \
+    (uint32_t) (1 << 31) /* USB device endpoint 0 OUT endpoint enable */
+
+#define USB_FS_DOEPCTLx_MPSIZE(n)                                           \
+    (uint32_t) (n << 0) /* USB device endpoint x OUT maximum packet size in \
+                           bytes (11 bits) */
+#define USB_FS_DOEPCTLx_USBAEP \
+    (uint32_t) (1 << 15) /* USB device endpoint x OUT USB active endpoint */
+#define USB_FS_DOEPCTLx_EONUM_EVEN \
+    (uint32_t) (0 << 16) /* USB device endpoint x OUT Odd frame */
+#define USB_FS_DOEPCTLx_EONUM_ODD \
+    (uint32_t) (1 << 16) /* USB device endpoint x OUT Odd frame */
+#define USB_FS_DOEPCTLx_DPID_0 \
+    (uint32_t) (0 << 16) /* USB device endpoint x OUT data PID 0 */
+#define USB_FS_DOEPCTLx_DPID_1 \
+    (uint32_t) (1 << 16) /* USB device endpoint x OUT data PID 1 */
+#define USB_FS_DOEPCTLx_NAKSTS \
+    (uint32_t) (1 << 17) /* USB device endpoint x OUT NAK status */
+#define USB_FS_DOEPCTLx_EPTYP_CTL \
+    (uint32_t) (0 << 18) /* USB device endpoint x OUT type: control */
+#define USB_FS_DOEPCTLx_EPTYP_ISO \
+    (uint32_t) (1 << 18) /* USB device endpoint x OUT type: isochronous */
+#define USB_FS_DOEPCTLx_EPTYP_BLK \
+    (uint32_t) (2 << 18) /* USB device endpoint x OUT type: bulk */
+#define USB_FS_DOEPCTLx_EPTYP_INT \
+    (uint32_t) (3 << 18) /* USB device endpoint x OUT type: interrupt */
+#define USB_FS_DOEPCTLx_SNPMN \
+    (uint32_t) (1 << 20) /* USB device endpoint x OUT snoop mode */
+#define USB_FS_DOEPCTLx_STALL \
+    (uint32_t) (1 << 21) /* USB device endpoint x OUT STALL handshake */
+#define USB_FS_DOEPCTLx_CNAK \
+    (uint32_t) (1 << 26) /* USB device endpoint x OUT clear NAK */
+#define USB_FS_DOEPCTLx_SNAK \
+    (uint32_t) (1 << 27) /* USB device endpoint x OUT set NAK */
+#define USB_FS_DOEPCTLx_SD0PID \
+    (uint32_t) (1 << 28) /* USB device endpoint x OUT set DATA0 PID */
+#define USB_FS_DOEPCTLx_SEVNFRM \
+    (uint32_t) (1 << 28) /* USB device endpoint x OUT set even frame */
+#define USB_FS_DOEPCTLx_SODDFRM \
+    (uint32_t) (1 << 29) /* USB device endpoint x OUT set odd frame */
+#define USB_FS_DOEPCTLx_EPDIS \
+    (uint32_t) (1 << 30) /* USB device endpoint x OUT endpoint disable */
+#define USB_FS_DOEPCTLx_EPENA \
+    (uint32_t) (1 << 31) /* USB device endpoint x OUT endpoint enable */
+
+#define USB_FS_DIEPINTx_XFRC                                          \
+    (uint32_t) (1 << 0) /* USB device endpoint x IN transfer complete \
+                           interrupt */
+#define USB_FS_DIEPINTx_EPDISD                                        \
+    (uint32_t) (1 << 1) /* USB device endpoint x IN endpoint disabled \
+                           interrupt */
+#define USB_FS_DIEPINTx_TOC \
+    (uint32_t) (1 << 3) /* USB device endpoint x IN timeout condition */
+#define USB_FS_DIEPINTx_ITTXFE                                             \
+    (uint32_t) (1 << 4) /* USB device endpoint x IN token received when TX \
+                           FIFO is empty */
+#define USB_FS_DIEPINTx_INEPNE \
+    (uint32_t) (1 << 6) /* USB device endpoint x IN endpoint NAK effective */
+#define USB_FS_DIEPINTx_TXFE \
+    (uint32_t) (1 << 7) /* USB device endpoint x IN TX FIFO empty */
+
+#define USB_FS_DOEPINTx_XFRC                                           \
+    (uint32_t) (1 << 0) /* USB device endpoint x OUT transfer complete \
+                           interrupt */
+#define USB_FS_DOEPINTx_EPDISD                                         \
+    (uint32_t) (1 << 1) /* USB device endpoint x OUT endpoint disabled \
+                           interrupt */
+#define USB_FS_DOEPINTx_STUP \
+    (uint32_t) (1 << 3) /* USB device endpoint x OUT SETUP phase complete */
+#define USB_FS_DOEPINTx_OTEPDIS                                           \
+    (uint32_t) (1 << 4) /* USB device endpoint x OUT token receieved when \
+                           endpoint disabled */
+#define USB_FS_DOEPINTx_B2BSTUP                                         \
+    (uint32_t) (1 << 6) /* USB device endpoint x OUT back-to-back SETUP \
+                           packets received */
+
+#define USB_FS_DIEPTSIZ0_XFRSIZ(n) \
+    (uint32_t) (n << 0) /* USB device endpoint 0 IN transfer size (7 bits) */
+#define USB_FS_DIEPTSIZ0_PKTCNT(n) \
+    (uint32_t) (n << 19) /* USB device endpoint 0 IN packet count */
+
+#define USB_FS_DIEPTSIZx_XFRSIZ(n) \
+    (uint32_t) (n << 0) /* USB device endpoint x IN transfer size (19 bits) */
+#define USB_FS_DIEPTSIZx_PKTCNT(n) \
+    (uint32_t) (n << 19) /* USB device endpoint x IN packet count (10 bits) */
+#define USB_FS_DIEPTSIZx_MCNT_1 \
+    (uint32_t) (1 << 29) /* USB device endpoint x IN multi count 1 */
+#define USB_FS_DIEPTSIZx_MCNT_2 \
+    (uint32_t) (2 << 29) /* USB device endpoint x IN multi count 1 */
+#define USB_FS_DIEPTSIZx_MCNT_3 \
+    (uint32_t) (3 << 29) /* USB device endpoint x IN multi count 1 */
+
+#define USB_FS_DOEPTSIZ0_XFRSIZ(n) \
+    (uint32_t) (n << 0) /* USB device endpoint 0 OUT transfer size (7 bits) */
+#define USB_FS_DOEPTSIZ0_PKTCNT(n) \
+    (uint32_t) (n << 19) /* USB device endpoint 0 OUT packet count */
+#define USB_FS_DOEPTSIZ0_STUPCNT(n)                                      \
+    (uint32_t) (n << 29) /* USB device endpoint 0 OUT back-to-back SETUP \
+                            packets allowed */
+
+#define USB_FS_DOEPTSIZx_XFRSIZ(n)                                           \
+    (uint32_t) (n << 0) /* USB device endpoint x OUT transfer size (19 bits) \
+                         */
+#define USB_FS_DOEPTSIZx_PKTCNT(n)                                           \
+    (uint32_t) (n << 19) /* USB device endpoint x OUT packet count (10 bits) \
+                          */
+#define USB_FS_DOEPTSIZx_STUPCNT(n)                                      \
+    (uint32_t) (n << 29) /* USB device endpoint x OUT back-to-back SETUP \
+                            packets allowed */
+#define USB_FS_DOEPTSIZx_RXDPID \
+    (uint32_t) (1 << 29 |       \
+                1 << 30) /* USB device endpoint x OUT received data PID */
 
 /* Powe and Clock Gating Control Register */
-#define USB_FS_PCGCCTL_STPPCLK          (uint32_t) (1 << 0)                                     /* USB stop PHY clock */
-#define USB_FS_PCGCCTL_GATEHCLK         (uint32_t) (1 << 1)                                     /* USB gate HCLK */
-#define USB_FS_PCGCCTL_PHYSUSP          (uint32_t) (1 << 4)                                     /* USB PHY suspended */
+#define USB_FS_PCGCCTL_STPPCLK (uint32_t) (1 << 0)  /* USB stop PHY clock */
+#define USB_FS_PCGCCTL_GATEHCLK (uint32_t) (1 << 1) /* USB gate HCLK */
+#define USB_FS_PCGCCTL_PHYSUSP (uint32_t) (1 << 4)  /* USB PHY suspended */
 
 #endif
diff --git a/include/platform/stm32f4/syscfg.h b/include/platform/stm32f4/syscfg.h
index e98e1c8f..e9c852c6 100644
--- a/include/platform/stm32f4/syscfg.h
+++ b/include/platform/stm32f4/syscfg.h
@@ -10,19 +10,18 @@
 
 static inline void memory_remap_flash(void)
 {
-	*SYSCFG_MEMRMP = 0x0;
+    *SYSCFG_MEMRMP = 0x0;
 }
 
 static inline void memory_remap_sysflash(void)
 {
-	*SYSCFG_MEMRMP = 0x1;
+    *SYSCFG_MEMRMP = 0x1;
 }
 
 
 static inline void memory_remap_sram(void)
 {
-	*SYSCFG_MEMRMP = 0x3;
+    *SYSCFG_MEMRMP = 0x3;
 }
 
 #endif
-
diff --git a/include/platform/stm32f4/systick.h b/include/platform/stm32f4/systick.h
index a80d6294..f15881ca 100644
--- a/include/platform/stm32f4/systick.h
+++ b/include/platform/stm32f4/systick.h
@@ -3,8 +3,8 @@
 
 #include <platform/stm32f4/registers.h>
 
-#define CORE_CLOCK		(0x0a037a00) /* 168MHz */
-#define SYSTICK_MAXRELOAD	(0x00ffffff)
+#define CORE_CLOCK (0x0a037a00) /* 168MHz */
+#define SYSTICK_MAXRELOAD (0x00ffffff)
 
 void init_systick(uint32_t tick_reload, uint32_t tick_next_reload);
 void systick_disable(void);
diff --git a/include/platform/stm32f4/usart.h b/include/platform/stm32f4/usart.h
index 5d10900e..e163ee4f 100644
--- a/include/platform/stm32f4/usart.h
+++ b/include/platform/stm32f4/usart.h
@@ -6,55 +6,57 @@
 #ifndef PLATFORM_STM32F4_USART_H_
 #define PLATFORM_STM32F4_USART_H_
 
-#include <platform/stm32f4/registers.h>
 #include <platform/stm32f4/gpio.h>
+#include <platform/stm32f4/registers.h>
 
 struct usart_dev {
-	uint32_t u_num;
-	uint32_t baud;
-	uint32_t base;
-	volatile uint32_t *rcc_apbenr;
-	uint32_t rcc_reset;
-	struct gpio_cfg tx;
-	struct gpio_cfg rx;
+    uint32_t u_num;
+    uint32_t baud;
+    uint32_t base;
+    volatile uint32_t *rcc_apbenr;
+    uint32_t rcc_reset;
+    struct gpio_cfg tx;
+    struct gpio_cfg rx;
 };
 
 #define USART_NUM 6
 
 /* status bit */
-#define USART_CTS	((uint16_t) (0x1 << 9))
-#define USART_LBD	((uint16_t) (0x1 << 8))
-#define USART_TXE	((uint16_t) (0x1 << 7))
-#define USART_TC	((uint16_t) (0x1 << 6))
-#define USART_RXNE	((uint16_t) (0x1 << 5))
-#define USART_IDLE	((uint16_t) (0x1 << 4))
-#define USART_ORE	((uint16_t) (0x1 << 3))
-#define USART_NF	((uint16_t) (0x1 << 2))
-#define USART_FE	((uint16_t) (0x1 << 1))
-#define USART_PE	((uint16_t) (0x1 << 0))
-
-
-#define USART_IT_CR1	(0xc << 8)
-#define USART_IT_CR2	(0x10 << 8)
-#define USART_IT_CR3	(0x14 << 8)
-
-#define USART_IT_PE	((uint16_t) USART_IT_CR1 | 0x8)
-#define USART_IT_TXE	((uint16_t) USART_IT_CR1 | 0x7)
-#define USART_IT_TC	((uint16_t) USART_IT_CR1 | 0x6)
-#define USART_IT_RXNE	((uint16_t) USART_IT_CR1 | 0x5)
-#define USART_IT_IDLE	((uint16_t) USART_IT_CR1 | 0x4)
-#define USART_IT_LBD	((uint16_t) USART_IT_CR2 | 0x6)
-#define USART_IT_CTS	((uint16_t) USART_IT_CR3 | 0xa)
-#define USART_IT_ERR	((uint16_t) USART_IT_CR3 | 0x0)
-
-#define USART_IT_ENB_REG_OFFSET(USART_IT)	((USART_IT >> 8) & 0xff)
-#define USART_IT_POSITION(USART_IT)		(USART_IT & 0xff)
+#define USART_CTS ((uint16_t) (0x1 << 9))
+#define USART_LBD ((uint16_t) (0x1 << 8))
+#define USART_TXE ((uint16_t) (0x1 << 7))
+#define USART_TC ((uint16_t) (0x1 << 6))
+#define USART_RXNE ((uint16_t) (0x1 << 5))
+#define USART_IDLE ((uint16_t) (0x1 << 4))
+#define USART_ORE ((uint16_t) (0x1 << 3))
+#define USART_NF ((uint16_t) (0x1 << 2))
+#define USART_FE ((uint16_t) (0x1 << 1))
+#define USART_PE ((uint16_t) (0x1 << 0))
+
+
+#define USART_IT_CR1 (0xc << 8)
+#define USART_IT_CR2 (0x10 << 8)
+#define USART_IT_CR3 (0x14 << 8)
+
+#define USART_IT_PE ((uint16_t) USART_IT_CR1 | 0x8)
+#define USART_IT_TXE ((uint16_t) USART_IT_CR1 | 0x7)
+#define USART_IT_TC ((uint16_t) USART_IT_CR1 | 0x6)
+#define USART_IT_RXNE ((uint16_t) USART_IT_CR1 | 0x5)
+#define USART_IT_IDLE ((uint16_t) USART_IT_CR1 | 0x4)
+#define USART_IT_LBD ((uint16_t) USART_IT_CR2 | 0x6)
+#define USART_IT_CTS ((uint16_t) USART_IT_CR3 | 0xa)
+#define USART_IT_ERR ((uint16_t) USART_IT_CR3 | 0x0)
+
+#define USART_IT_ENB_REG_OFFSET(USART_IT) ((USART_IT >> 8) & 0xff)
+#define USART_IT_POSITION(USART_IT) (USART_IT & 0xff)
 
 void usart_init(struct usart_dev *usart);
 void usart_putc(struct usart_dev *usart, uint8_t c);
 uint8_t usart_getc(struct usart_dev *usart);
 int usart_status(struct usart_dev *usart, uint16_t st);
 int usart_interrupt_status(struct usart_dev *usart, uint16_t it);
-void usart_config_interrupt(struct usart_dev *usart, uint16_t it, uint8_t state);
+void usart_config_interrupt(struct usart_dev *usart,
+                            uint16_t it,
+                            uint8_t state);
 
 #endif /* PLATFORM_STM32F4_USART_H_ */
diff --git a/include/platform/stm32f429/dma2d.h b/include/platform/stm32f429/dma2d.h
index 4b5db03c..2f81a4b2 100644
--- a/include/platform/stm32f429/dma2d.h
+++ b/include/platform/stm32f429/dma2d.h
@@ -1,61 +1,61 @@
 #ifndef PLATFORM_STM32F429_DMA2D_H__
 #define PLATFORM_STM32F429_DMA2D_H__
 
-#include <platform/stm32f429/registers.h>
 #include <platform/link.h>
+#include <platform/stm32f429/registers.h>
 
 /* CR Register */
-#define DMA2D_CR_START                     (uint32_t) (1 << 0)
-#define DMA2D_CR_SUSP                      (uint32_t) (1 << 1)
-#define DMA2D_CR_ABORT                     (uint32_t) (1 << 2)
-#define DMA2D_CR_TEIE                      (uint32_t) (1 << 8)
-#define DMA2D_CR_TCIE                      (uint32_t) (1 << 9)
-#define DMA2D_CR_TWIE                      (uint32_t) (1 << 10)
-#define DMA2D_CR_CAEIE                     (uint32_t) (1 << 11)
-#define DMA2D_CR_CTCIE                     (uint32_t) (1 << 12)
-#define DMA2D_CR_CEIE                      (uint32_t) (1 << 13)
-#define DMA2D_CR_MODE                      ((uint32_t)0x00030000)
+#define DMA2D_CR_START (uint32_t) (1 << 0)
+#define DMA2D_CR_SUSP (uint32_t) (1 << 1)
+#define DMA2D_CR_ABORT (uint32_t) (1 << 2)
+#define DMA2D_CR_TEIE (uint32_t) (1 << 8)
+#define DMA2D_CR_TCIE (uint32_t) (1 << 9)
+#define DMA2D_CR_TWIE (uint32_t) (1 << 10)
+#define DMA2D_CR_CAEIE (uint32_t) (1 << 11)
+#define DMA2D_CR_CTCIE (uint32_t) (1 << 12)
+#define DMA2D_CR_CEIE (uint32_t) (1 << 13)
+#define DMA2D_CR_MODE ((uint32_t) 0x00030000)
 /* Color Mode */
-#define DMA2D_OPFCCR_CM                    ((uint32_t)0x00000007)
+#define DMA2D_OPFCCR_CM ((uint32_t) 0x00000007)
 /* Line Offset */
-#define DMA2D_OOR_LO                       ((uint32_t)0x00003FFF)
+#define DMA2D_OOR_LO ((uint32_t) 0x00003FFF)
 /* Number of lines */
-#define DMA2D_NLR_NL                       ((uint32_t)0x0000FFFF)
+#define DMA2D_NLR_NL ((uint32_t) 0x0000FFFF)
 /* Pixel Per Lines */
-#define DMA2D_NLR_PL                       ((uint32_t)0x3FFF0000)
+#define DMA2D_NLR_PL ((uint32_t) 0x3FFF0000)
 
 
 /* MODE */
-#define DMA2D_M2M                          ((uint32_t)0x00000000)
-#define DMA2D_M2M_PFC                      ((uint32_t)0x00010000)
-#define DMA2D_M2M_BLEND                    ((uint32_t)0x00020000)
-#define DMA2D_R2M                          ((uint32_t)0x00030000)
+#define DMA2D_M2M ((uint32_t) 0x00000000)
+#define DMA2D_M2M_PFC ((uint32_t) 0x00010000)
+#define DMA2D_M2M_BLEND ((uint32_t) 0x00020000)
+#define DMA2D_R2M ((uint32_t) 0x00030000)
 /* CMODE */
-#define DMA2D_ARGB8888                     ((uint32_t)0x00000000)
-#define DMA2D_RGB888                       ((uint32_t)0x00000001)
-#define DMA2D_RGB565                       ((uint32_t)0x00000002)
-#define DMA2D_ARGB1555                     ((uint32_t)0x00000003)
-#define DMA2D_ARGB4444                     ((uint32_t)0x00000004)
+#define DMA2D_ARGB8888 ((uint32_t) 0x00000000)
+#define DMA2D_RGB888 ((uint32_t) 0x00000001)
+#define DMA2D_RGB565 ((uint32_t) 0x00000002)
+#define DMA2D_ARGB1555 ((uint32_t) 0x00000003)
+#define DMA2D_ARGB4444 ((uint32_t) 0x00000004)
 
 /* FLAG */
-#define DMA2D_FLAG_CE                      ((uint32_t) 1 << 5)
-#define DMA2D_FLAG_CTC                     ((uint32_t) 1 << 4)
-#define DMA2D_FLAG_CAE                     ((uint32_t) 1 << 3)
-#define DMA2D_FLAG_TW                      ((uint32_t) 1 << 2)
-#define DMA2D_FLAG_TC                      ((uint32_t) 1 << 1)
-#define DMA2D_FLAG_TE                      ((uint32_t) 1 << 0)
+#define DMA2D_FLAG_CE ((uint32_t) 1 << 5)
+#define DMA2D_FLAG_CTC ((uint32_t) 1 << 4)
+#define DMA2D_FLAG_CAE ((uint32_t) 1 << 3)
+#define DMA2D_FLAG_TW ((uint32_t) 1 << 2)
+#define DMA2D_FLAG_TC ((uint32_t) 1 << 1)
+#define DMA2D_FLAG_TE ((uint32_t) 1 << 0)
 
 struct dma2d_cfg {
-	uint32_t mode;
-	uint32_t cmode;
-	uint32_t output_blue;
-	uint32_t output_green;
-	uint32_t output_red;
-	uint32_t output_alpha;
-	uint32_t output_memory_address;
-	uint32_t output_offset;
-	uint32_t number_of_line;
-	uint32_t pixel_per_line;
+    uint32_t mode;
+    uint32_t cmode;
+    uint32_t output_blue;
+    uint32_t output_green;
+    uint32_t output_red;
+    uint32_t output_alpha;
+    uint32_t output_memory_address;
+    uint32_t output_offset;
+    uint32_t number_of_line;
+    uint32_t pixel_per_line;
 };
 
 void dma2d_reset(void);
diff --git a/include/platform/stm32f429/exti.h b/include/platform/stm32f429/exti.h
index 4342f603..765718ac 100644
--- a/include/platform/stm32f429/exti.h
+++ b/include/platform/stm32f429/exti.h
@@ -1,27 +1,27 @@
 #ifndef PLATFORM_STM32F429_EXTI_H_
 #define PLATFORM_STM32F429_EXTI_H_
 
-#include <platform/stm32f429/registers.h>
 #include <platform/stm32f429/gpio.h>
+#include <platform/stm32f429/registers.h>
 
 /* EXTI mode */
-#define EXTI_INTERRUPT_MODE				0x0
-#define EXTI_EVENT_MODE					0x4
+#define EXTI_INTERRUPT_MODE 0x0
+#define EXTI_EVENT_MODE 0x4
 
 /* EXTI trigger type */
-#define EXTI_RISING_TRIGGER				0x8
-#define EXTI_FALLING_TRIGGER			0xc
-#define EXTI_RISING_FALLING_TRIGGER		0x10
+#define EXTI_RISING_TRIGGER 0x8
+#define EXTI_FALLING_TRIGGER 0xc
+#define EXTI_RISING_FALLING_TRIGGER 0x10
 
-#define EXTI_LINE(x)	((uint32_t)0x1 << x)
+#define EXTI_LINE(x) ((uint32_t) 0x1 << x)
 
 struct exti_regs {
-	volatile uint32_t IMR;
-	volatile uint32_t EMR;
-	volatile uint32_t RTSR;
-	volatile uint32_t FTSR;
-	volatile uint32_t SWIER;
-	volatile uint32_t PR;
+    volatile uint32_t IMR;
+    volatile uint32_t EMR;
+    volatile uint32_t RTSR;
+    volatile uint32_t FTSR;
+    volatile uint32_t SWIER;
+    volatile uint32_t PR;
 };
 
 
diff --git a/include/platform/stm32f429/fmc.h b/include/platform/stm32f429/fmc.h
index c4dbcb41..b596b2c5 100644
--- a/include/platform/stm32f429/fmc.h
+++ b/include/platform/stm32f429/fmc.h
@@ -5,87 +5,87 @@
 #include <platform/stm32f429/registers.h>
 
 struct fmc_sdram_cfg {
-	uint32_t bank;
-	uint32_t column_bits_number;
-	uint32_t row_bits_number;
-	uint32_t sdmemory_data_width;
-	uint32_t internal_bank_number;
-	uint32_t cas_latency;
-	uint32_t write_protection;
-	uint32_t sd_clock_period;
-	uint32_t readburst;
-	uint32_t readpipe_delay;
-	struct fmc_sdram_timing_cfg* timing;
+    uint32_t bank;
+    uint32_t column_bits_number;
+    uint32_t row_bits_number;
+    uint32_t sdmemory_data_width;
+    uint32_t internal_bank_number;
+    uint32_t cas_latency;
+    uint32_t write_protection;
+    uint32_t sd_clock_period;
+    uint32_t readburst;
+    uint32_t readpipe_delay;
+    struct fmc_sdram_timing_cfg *timing;
 };
 
 struct fmc_sdram_timing_cfg {
-	uint32_t lta_delay;
-	uint32_t esr_delay;
-	uint32_t sr_time;
-	uint32_t rc_delay;
-	uint32_t wr_time;
-	uint32_t rp_delay;
-	uint32_t rcd_delay;
+    uint32_t lta_delay;
+    uint32_t esr_delay;
+    uint32_t sr_time;
+    uint32_t rc_delay;
+    uint32_t wr_time;
+    uint32_t rp_delay;
+    uint32_t rcd_delay;
 };
 
 struct fmc_sdram_cmd {
-	uint32_t mode;
-	uint32_t target;
-	uint32_t auto_refresh_number;
-	uint32_t mode_register_definition;
+    uint32_t mode;
+    uint32_t target;
+    uint32_t auto_refresh_number;
+    uint32_t mode_register_definition;
 };
 
-#define FMC_Bank1_SDRAM                    ((uint32_t)0x00000000)
-#define FMC_Bank2_SDRAM                    ((uint32_t)0x00000001)
+#define FMC_Bank1_SDRAM ((uint32_t) 0x00000000)
+#define FMC_Bank2_SDRAM ((uint32_t) 0x00000001)
 
-#define FMC_ColumnBits_Number_8b           ((uint32_t)0x00000000)
-#define FMC_ColumnBits_Number_9b           ((uint32_t)0x00000001)
-#define FMC_ColumnBits_Number_10b          ((uint32_t)0x00000002)
-#define FMC_ColumnBits_Number_11b          ((uint32_t)0x00000003)
+#define FMC_ColumnBits_Number_8b ((uint32_t) 0x00000000)
+#define FMC_ColumnBits_Number_9b ((uint32_t) 0x00000001)
+#define FMC_ColumnBits_Number_10b ((uint32_t) 0x00000002)
+#define FMC_ColumnBits_Number_11b ((uint32_t) 0x00000003)
 
-#define FMC_RowBits_Number_11b             ((uint32_t)0x00000000)
-#define FMC_RowBits_Number_12b             ((uint32_t)0x00000004)
-#define FMC_RowBits_Number_13b             ((uint32_t)0x00000008)
+#define FMC_RowBits_Number_11b ((uint32_t) 0x00000000)
+#define FMC_RowBits_Number_12b ((uint32_t) 0x00000004)
+#define FMC_RowBits_Number_13b ((uint32_t) 0x00000008)
 
-#define FMC_SDMemory_Width_8b                ((uint32_t)0x00000000)
-#define FMC_SDMemory_Width_16b               ((uint32_t)0x00000010)
-#define FMC_SDMemory_Width_32b               ((uint32_t)0x00000020)
+#define FMC_SDMemory_Width_8b ((uint32_t) 0x00000000)
+#define FMC_SDMemory_Width_16b ((uint32_t) 0x00000010)
+#define FMC_SDMemory_Width_32b ((uint32_t) 0x00000020)
 
-#define FMC_InternalBank_Number_2          ((uint32_t)0x00000000)
-#define FMC_InternalBank_Number_4          ((uint32_t)0x00000040)
+#define FMC_InternalBank_Number_2 ((uint32_t) 0x00000000)
+#define FMC_InternalBank_Number_4 ((uint32_t) 0x00000040)
 
-#define FMC_CAS_Latency_1                  ((uint32_t)0x00000080)
-#define FMC_CAS_Latency_2                  ((uint32_t)0x00000100)
-#define FMC_CAS_Latency_3                  ((uint32_t)0x00000180)
+#define FMC_CAS_Latency_1 ((uint32_t) 0x00000080)
+#define FMC_CAS_Latency_2 ((uint32_t) 0x00000100)
+#define FMC_CAS_Latency_3 ((uint32_t) 0x00000180)
 
-#define FMC_Write_Protection_Disable       ((uint32_t)0x00000000)
-#define FMC_Write_Protection_Enable        ((uint32_t)0x00000200)
+#define FMC_Write_Protection_Disable ((uint32_t) 0x00000000)
+#define FMC_Write_Protection_Enable ((uint32_t) 0x00000200)
 
-#define FMC_SDClock_Disable                ((uint32_t)0x00000000)
-#define FMC_SDClock_Period_2               ((uint32_t)0x00000800)
-#define FMC_SDClock_Period_3               ((uint32_t)0x00000C00)
+#define FMC_SDClock_Disable ((uint32_t) 0x00000000)
+#define FMC_SDClock_Period_2 ((uint32_t) 0x00000800)
+#define FMC_SDClock_Period_3 ((uint32_t) 0x00000C00)
 
-#define FMC_FLAG_REFRESH                   ((uint32_t)0x00000001)
-#define FMC_FLAG_BUSY                      ((uint32_t)0x00000020)
+#define FMC_FLAG_REFRESH ((uint32_t) 0x00000001)
+#define FMC_FLAG_BUSY ((uint32_t) 0x00000020)
 
-#define FMC_Read_Burst_Disable             ((uint32_t)0x00000000)
-#define FMC_Read_Burst_Enable              ((uint32_t)0x00001000)
+#define FMC_Read_Burst_Disable ((uint32_t) 0x00000000)
+#define FMC_Read_Burst_Enable ((uint32_t) 0x00001000)
 
-#define FMC_ReadPipe_Delay_0               ((uint32_t)0x00000000)
-#define FMC_ReadPipe_Delay_1               ((uint32_t)0x00002000)
-#define FMC_ReadPipe_Delay_2               ((uint32_t)0x00004000)
+#define FMC_ReadPipe_Delay_0 ((uint32_t) 0x00000000)
+#define FMC_ReadPipe_Delay_1 ((uint32_t) 0x00002000)
+#define FMC_ReadPipe_Delay_2 ((uint32_t) 0x00004000)
 
-#define FMC_Command_Mode_normal            ((uint32_t)0x00000000)
-#define FMC_Command_Mode_CLK_Enabled       ((uint32_t)0x00000001)
-#define FMC_Command_Mode_PALL              ((uint32_t)0x00000002)
-#define FMC_Command_Mode_AutoRefresh       ((uint32_t)0x00000003)
-#define FMC_Command_Mode_LoadMode          ((uint32_t)0x00000004)
-#define FMC_Command_Mode_Selfrefresh       ((uint32_t)0x00000005)
-#define FMC_Command_Mode_PowerDown         ((uint32_t)0x00000006)
+#define FMC_Command_Mode_normal ((uint32_t) 0x00000000)
+#define FMC_Command_Mode_CLK_Enabled ((uint32_t) 0x00000001)
+#define FMC_Command_Mode_PALL ((uint32_t) 0x00000002)
+#define FMC_Command_Mode_AutoRefresh ((uint32_t) 0x00000003)
+#define FMC_Command_Mode_LoadMode ((uint32_t) 0x00000004)
+#define FMC_Command_Mode_Selfrefresh ((uint32_t) 0x00000005)
+#define FMC_Command_Mode_PowerDown ((uint32_t) 0x00000006)
 
-#define FMC_Command_Target_bank2           ((uint32_t)0x00000008)
-#define FMC_Command_Target_bank1           ((uint32_t)0x00000010)
-#define FMC_Command_Target_bank1_2         ((uint32_t)0x00000018)
+#define FMC_Command_Target_bank2 ((uint32_t) 0x00000008)
+#define FMC_Command_Target_bank1 ((uint32_t) 0x00000010)
+#define FMC_Command_Target_bank1_2 ((uint32_t) 0x00000018)
 
 void fmc_sdram_config(struct fmc_sdram_cfg *cfg);
 uint8_t fmc_get_flag(uint32_t bank, uint32_t flag);
diff --git a/include/platform/stm32f429/gpio.h b/include/platform/stm32f429/gpio.h
index 8e88b4dd..d6c01cd5 100644
--- a/include/platform/stm32f429/gpio.h
+++ b/include/platform/stm32f429/gpio.h
@@ -9,72 +9,72 @@
 #include <platform/stm32f429/registers.h>
 
 enum {
-	AF0 = 0,
-	AF1,
-	AF2,
-	AF3,
-	AF4,
-	AF5,
-	AF6,
-	AF7,
-	AF8,
-	AF9,
-	AF10,
-	AF11,
-	AF12,
-	AF13,
-	AF14,
-	AF15,
+    AF0 = 0,
+    AF1,
+    AF2,
+    AF3,
+    AF4,
+    AF5,
+    AF6,
+    AF7,
+    AF8,
+    AF9,
+    AF10,
+    AF11,
+    AF12,
+    AF13,
+    AF14,
+    AF15,
 };
 
 struct gpio_cfg {
-	uint8_t port;
-	uint8_t pin;
-	uint8_t pupd;
-	uint8_t speed;
-	uint8_t type;
-	uint8_t func;
-	uint8_t o_type;
+    uint8_t port;
+    uint8_t pin;
+    uint8_t pupd;
+    uint8_t speed;
+    uint8_t type;
+    uint8_t func;
+    uint8_t o_type;
 };
 
 /* GPIO Alternative Function */
-#define     af_system           AF0
-#define     af_tim1             AF1
-#define     af_tim2             AF1
-#define     af_tim3             AF2
-#define     af_tim4             AF2
-#define     af_tim5             AF2
-#define     af_tim8             AF3
-#define     af_tim9             AF3
-#define     af_tim10            AF3
-#define     af_tim11            AF3
-#define     af_i2c1             AF4
-#define     af_i2c2             AF4
-#define     af_i2c3             AF4
-#define     af_spi1             AF5
-#define     af_spi2             AF5
-#define     af_spi5             AF5
-#define     af_spi3             AF6
-#define     af_usart1           AF7
-#define     af_usart2           AF7
-#define     af_usart3		AF7
-#define     af_uart4		AF8
-#define     af_uart5		AF8
-#define     af_usart6           AF8
-#define     af_can1             AF9
-#define     af_can2             AF9
-#define     af_tim12            AF9
-#define     af_tim13            AF9
-#define     af_tim14            AF9
-#define     af_otg_fs           AF10
-#define     af_otg_hs           AF10
-#define     af_eth              AF11
-#define     af_fsmc             AF12
-#define     af_fmc              AF12
-#define     af_sdio             AF12
-#define     af_dcmi             AF13
-#define     af_ltdc             AF14
-#define     af_eventout         AF15
+#define af_system AF0
+#define af_tim1 AF1
+#define af_tim2 AF1
+#define af_tim3 AF2
+#define af_tim4 AF2
+#define af_tim5 AF2
+#define af_tim8 AF3
+#define af_tim9 AF3
+#define af_tim10 AF3
+#define af_tim11 AF3
+#define af_i2c1 AF4
+#define af_i2c2 AF4
+#define af_i2c3 AF4
+#define af_spi1 AF5
+#define af_spi2 AF5
+#define af_spi5 AF5
+#define af_spi3 AF6
+#define af_usart1 AF7
+#define af_usart2 AF7
+#define af_usart3 AF7
+#define af_uart4 AF8
+#define af_uart5 AF8
+#define af_usart6 AF8
+#define af_can1 AF9
+#define af_can2 AF9
+#define af_tim12 AF9
+#define af_tim13 AF9
+#define af_tim14 AF9
+#define af_otg_fs AF10
+#define af_otg_hs AF10
+#define af_eth AF11
+#define af_fsmc AF12
+#define af_fmc AF12
+#define af_sdio AF12
+#define af_dcmi AF13
+#define af_ltdc AF14
+#define af_eventout AF15
 
 void gpio_config(struct gpio_cfg *cfg);
 void gpio_config_output(uint8_t port, uint8_t pin, uint8_t pupd, uint8_t speed);
diff --git a/include/platform/stm32f429/i2c.h b/include/platform/stm32f429/i2c.h
index a22da67f..08ce534b 100644
--- a/include/platform/stm32f429/i2c.h
+++ b/include/platform/stm32f429/i2c.h
@@ -1,61 +1,61 @@
 #ifndef PLATFORM_STM32F429_I2C_H__
 #define PLATFORM_STM32F429_I2C_H__
 
-#include <platform/stm32f429/registers.h>
 #include <platform/link.h>
+#include <platform/stm32f429/registers.h>
 
 struct i2c_cfg {
-	uint32_t clock_speed;
-	uint16_t mode;
-	uint16_t duty_cycle;
-	uint16_t own_address;
-	uint16_t ack;
-	uint16_t acknowledged_address;
+    uint32_t clock_speed;
+    uint16_t mode;
+    uint16_t duty_cycle;
+    uint16_t own_address;
+    uint16_t ack;
+    uint16_t acknowledged_address;
 };
 
-#define I2C_Mode_I2C                    ((uint16_t)0x0000)
-#define I2C_Mode_SMBusDevice            ((uint16_t)0x0002)
-#define I2C_Mode_SMBusHost              ((uint16_t)0x000A)
+#define I2C_Mode_I2C ((uint16_t) 0x0000)
+#define I2C_Mode_SMBusDevice ((uint16_t) 0x0002)
+#define I2C_Mode_SMBusHost ((uint16_t) 0x000A)
 
 /* duty cycle */
 /* Fast mode Tlow/Thigh = 16/9 */
-#define I2C_DutyCycle_16_9              ((uint16_t)0x4000)
+#define I2C_DutyCycle_16_9 ((uint16_t) 0x4000)
 /* Fast mode Tlow/Thigh = 2 */
-#define I2C_DutyCycle_2                 ((uint16_t)0xBFFF)
+#define I2C_DutyCycle_2 ((uint16_t) 0xBFFF)
 
 /* Ack */
-#define I2C_Ack_Enable                  ((uint16_t)0x0400)
-#define I2C_Ack_Disable                 ((uint16_t)0x0000)
+#define I2C_Ack_Enable ((uint16_t) 0x0400)
+#define I2C_Ack_Disable ((uint16_t) 0x0000)
 
 /* Acknowledged address */
-#define I2C_AcknowledgedAddress_7bit    ((uint16_t)0x4000)
-#define I2C_AcknowledgedAddress_10bit   ((uint16_t)0xC000)
+#define I2C_AcknowledgedAddress_7bit ((uint16_t) 0x4000)
+#define I2C_AcknowledgedAddress_10bit ((uint16_t) 0xC000)
 
 /* i2c speed */
-#define I2C_SPEED                       100000
+#define I2C_SPEED 100000
 
 /* direction */
-#define  I2C_Direction_Transmitter      ((uint8_t)0x00)
-#define  I2C_Direction_Receiver         ((uint8_t)0x01)
+#define I2C_Direction_Transmitter ((uint8_t) 0x00)
+#define I2C_Direction_Receiver ((uint8_t) 0x01)
 
 /* SR1 flag */
-#define I2C_FLAG_SMBALERT               ((uint32_t)0x10008000)
-#define I2C_FLAG_TIMEOUT                ((uint32_t)0x10004000)
-#define I2C_FLAG_PECERR                 ((uint32_t)0x10001000)
-#define I2C_FLAG_OVR                    ((uint32_t)0x10000800)
-#define I2C_FLAG_AF                     ((uint32_t)0x10000400)
-#define I2C_FLAG_ARLO                   ((uint32_t)0x10000200)
-#define I2C_FLAG_BERR                   ((uint32_t)0x10000100)
-#define I2C_FLAG_TXE                    ((uint32_t)0x10000080)
-#define I2C_FLAG_RXNE                   ((uint32_t)0x10000040)
-#define I2C_FLAG_STOPF                  ((uint32_t)0x10000010)
-#define I2C_FLAG_ADD10                  ((uint32_t)0x10000008)
-#define I2C_FLAG_BTF                    ((uint32_t)0x10000004)
-#define I2C_FLAG_ADDR                   ((uint32_t)0x10000002)
-#define I2C_FLAG_SB                     ((uint32_t)0x10000001)
+#define I2C_FLAG_SMBALERT ((uint32_t) 0x10008000)
+#define I2C_FLAG_TIMEOUT ((uint32_t) 0x10004000)
+#define I2C_FLAG_PECERR ((uint32_t) 0x10001000)
+#define I2C_FLAG_OVR ((uint32_t) 0x10000800)
+#define I2C_FLAG_AF ((uint32_t) 0x10000400)
+#define I2C_FLAG_ARLO ((uint32_t) 0x10000200)
+#define I2C_FLAG_BERR ((uint32_t) 0x10000100)
+#define I2C_FLAG_TXE ((uint32_t) 0x10000080)
+#define I2C_FLAG_RXNE ((uint32_t) 0x10000040)
+#define I2C_FLAG_STOPF ((uint32_t) 0x10000010)
+#define I2C_FLAG_ADD10 ((uint32_t) 0x10000008)
+#define I2C_FLAG_BTF ((uint32_t) 0x10000004)
+#define I2C_FLAG_ADDR ((uint32_t) 0x10000002)
+#define I2C_FLAG_SB ((uint32_t) 0x10000001)
 
 void i2c_reset(uint32_t i2cx);
-void i2c_config(uint32_t i2cx, struct i2c_cfg* cfg);
+void i2c_config(uint32_t i2cx, struct i2c_cfg *cfg);
 void i2c_cmd(uint32_t i2cx, uint8_t enable);
 void i2c_generate_start(uint32_t i2cx, uint8_t enable);
 uint8_t i2c_get_flag(uint32_t i2cx, uint32_t flag);
diff --git a/include/platform/stm32f429/ioe.h b/include/platform/stm32f429/ioe.h
index 56855cf6..54972144 100644
--- a/include/platform/stm32f429/ioe.h
+++ b/include/platform/stm32f429/ioe.h
@@ -1,102 +1,102 @@
 #ifndef PLATFORM_STM32F429_IOE_H__
 #define PLATFORM_STM32F429_IOE_H__
 
-#include <platform/stm32f429/registers.h>
 #include <platform/link.h>
+#include <platform/stm32f429/registers.h>
 
-#define IOE_I2C_CLK             RCC_APB1ENR_I2C3EN
-#define IOE_I2C_SCL_GPIO_CLK    RCC_AHB1ENR_GPIOAEN
-#define IOE_I2C_SDA_GPIO_CLK    RCC_AHB1ENR_GPIOCEN
-#define IOE_IT_GPIO_CLK         RCC_AHB1ENR_GPIOIEN
+#define IOE_I2C_CLK RCC_APB1ENR_I2C3EN
+#define IOE_I2C_SCL_GPIO_CLK RCC_AHB1ENR_GPIOAEN
+#define IOE_I2C_SDA_GPIO_CLK RCC_AHB1ENR_GPIOCEN
+#define IOE_IT_GPIO_CLK RCC_AHB1ENR_GPIOIEN
 
-#define IOE_I2C_SCL_GPIO_PORT   GPIOA
-#define IOE_I2C_SDA_GPIO_PORT   GPIOC
+#define IOE_I2C_SCL_GPIO_PORT GPIOA
+#define IOE_I2C_SDA_GPIO_PORT GPIOC
 
-#define IOE_ADDR                0x82
-#define STMPE811_ID             0x0811
+#define IOE_ADDR 0x82
+#define STMPE811_ID 0x0811
 
-#define IOE_OK                  0
-#define IOE_FAILURE             1
-#define IOE_TIMEOUT             2
-#define IOE_NOT_OPERATIONAL     4
+#define IOE_OK 0
+#define IOE_FAILURE 1
+#define IOE_TIMEOUT 2
+#define IOE_NOT_OPERATIONAL 4
 
 /* gpio register */
-#define IOE_REG_GPIO_SET_PIN    0x10
-#define IOE_REG_GPIO_CLR_PIN    0x11
-#define IOE_REG_GPIO_MP_STA     0x12
-#define IOE_REG_GPIO_DIR        0x13
-#define IOE_REG_GPIO_ED         0x14
-#define IOE_REG_GPIO_RE         0x15
-#define IOE_REG_GPIO_FE         0x16
-#define IOE_REG_GPIO_AF         0x17
+#define IOE_REG_GPIO_SET_PIN 0x10
+#define IOE_REG_GPIO_CLR_PIN 0x11
+#define IOE_REG_GPIO_MP_STA 0x12
+#define IOE_REG_GPIO_DIR 0x13
+#define IOE_REG_GPIO_ED 0x14
+#define IOE_REG_GPIO_RE 0x15
+#define IOE_REG_GPIO_FE 0x16
+#define IOE_REG_GPIO_AF 0x17
 
 /* general control registers */
-#define IOE_REG_SYS_CTRL1       0x03
-#define IOE_REG_SYS_CTRL2       0x04
-#define IOE_REG_SPI_CFG         0x08
+#define IOE_REG_SYS_CTRL1 0x03
+#define IOE_REG_SYS_CTRL2 0x04
+#define IOE_REG_SPI_CFG 0x08
 
 /* ADC registers */
-#define IOE_REG_ADC_INT_EN      0x0E
-#define IOE_REG_ADC_INT_STA     0x0F
-#define IOE_REG_ADC_CTRL1       0x20
-#define IOE_REG_ADC_CTRL2       0x21
-#define IOE_REG_ADC_CAPT        0x22
-#define IOE_REG_ADC_DATA_CH0    0x30
-#define IOE_REG_ADC_DATA_CH1    0x32
-#define IOE_REG_ADC_DATA_CH2    0x34
-#define IOE_REG_ADC_DATA_CH3    0x36
-#define IOE_REG_ADC_DATA_CH4    0x38
-#define IOE_REG_ADC_DATA_CH5    0x3A
-#define IOE_REG_ADC_DATA_CH6    0x3B
-#define IOE_REG_ADC_DATA_CH7    0x3C
+#define IOE_REG_ADC_INT_EN 0x0E
+#define IOE_REG_ADC_INT_STA 0x0F
+#define IOE_REG_ADC_CTRL1 0x20
+#define IOE_REG_ADC_CTRL2 0x21
+#define IOE_REG_ADC_CAPT 0x22
+#define IOE_REG_ADC_DATA_CH0 0x30
+#define IOE_REG_ADC_DATA_CH1 0x32
+#define IOE_REG_ADC_DATA_CH2 0x34
+#define IOE_REG_ADC_DATA_CH3 0x36
+#define IOE_REG_ADC_DATA_CH4 0x38
+#define IOE_REG_ADC_DATA_CH5 0x3A
+#define IOE_REG_ADC_DATA_CH6 0x3B
+#define IOE_REG_ADC_DATA_CH7 0x3C
 
 /* Touch Panel registers */
-#define IOE_REG_TP_CTRL         0x40
-#define IOE_REG_TP_CFG          0x41
-#define IOE_REG_WDM_TR_X        0x42
-#define IOE_REG_WDM_TR_Y        0x44
-#define IOE_REG_WDM_BL_X        0x46
-#define IOE_REG_WDM_BL_Y        0x48
-#define IOE_REG_FIFO_TH         0x4A
-#define IOE_REG_FIFO_STA        0x4B
-#define IOE_REG_FIFO_SIZE       0x4C
-#define IOE_REG_TP_DATA_X       0x4D
-#define IOE_REG_TP_DATA_Y       0x4F
-#define IOE_REG_TP_DATA_Z       0x51
-#define IOE_REG_TP_DATA_XYZ     0x52
-#define IOE_REG_TP_FRACT_XYZ    0x56
-#define IOE_REG_TP_DATA         0x57
-#define IOE_REG_TP_I_DRIVE      0x58
-#define IOE_REG_TP_SHIELD       0x59
+#define IOE_REG_TP_CTRL 0x40
+#define IOE_REG_TP_CFG 0x41
+#define IOE_REG_WDM_TR_X 0x42
+#define IOE_REG_WDM_TR_Y 0x44
+#define IOE_REG_WDM_BL_X 0x46
+#define IOE_REG_WDM_BL_Y 0x48
+#define IOE_REG_FIFO_TH 0x4A
+#define IOE_REG_FIFO_STA 0x4B
+#define IOE_REG_FIFO_SIZE 0x4C
+#define IOE_REG_TP_DATA_X 0x4D
+#define IOE_REG_TP_DATA_Y 0x4F
+#define IOE_REG_TP_DATA_Z 0x51
+#define IOE_REG_TP_DATA_XYZ 0x52
+#define IOE_REG_TP_FRACT_XYZ 0x56
+#define IOE_REG_TP_DATA 0x57
+#define IOE_REG_TP_I_DRIVE 0x58
+#define IOE_REG_TP_SHIELD 0x59
 
 /* Interrupt Control registers */
-#define IOE_REG_INT_CTRL        0x09
-#define IOE_REG_INT_EN          0x0A
-#define IOE_REG_INT_STA         0x0B
-#define IOE_REG_GPIO_INT_EN     0x0C
-#define IOE_REG_GPIO_INT_STA    0x0D
+#define IOE_REG_INT_CTRL 0x09
+#define IOE_REG_INT_EN 0x0A
+#define IOE_REG_INT_STA 0x0B
+#define IOE_REG_GPIO_INT_EN 0x0C
+#define IOE_REG_GPIO_INT_STA 0x0D
 
 /* functionalities definition */
-#define IOE_ADC_FCT             0x01
-#define IOE_TP_FCT              0x02
-#define IOE_IO_FCT              0x04
+#define IOE_ADC_FCT 0x01
+#define IOE_TP_FCT 0x02
+#define IOE_IO_FCT 0x04
 
 /* Touch Panel Pins definition */
-#define TOUCH_YD                   IO_Pin_1
-#define TOUCH_XD                   IO_Pin_2
-#define TOUCH_YU                   IO_Pin_3
-#define TOUCH_XU                   IO_Pin_4
-#define TOUCH_IO_ALL               (uint32_t)(IO_Pin_1 | IO_Pin_2 | IO_Pin_3 | IO_Pin_4)
+#define TOUCH_YD IO_Pin_1
+#define TOUCH_XD IO_Pin_2
+#define TOUCH_YU IO_Pin_3
+#define TOUCH_XU IO_Pin_4
+#define TOUCH_IO_ALL (uint32_t) (IO_Pin_1 | IO_Pin_2 | IO_Pin_3 | IO_Pin_4)
 /* IO pins */
-#define IO_Pin_0                   0x01
-#define IO_Pin_1                   0x02
-#define IO_Pin_2                   0x04
-#define IO_Pin_3                   0x08
-#define IO_Pin_4                   0x10
-#define IO_Pin_5                   0x20
-#define IO_Pin_6                   0x40
-#define IO_Pin_7                   0x80
-#define IO_Pin_ALL                 0xFF
+#define IO_Pin_0 0x01
+#define IO_Pin_1 0x02
+#define IO_Pin_2 0x04
+#define IO_Pin_3 0x08
+#define IO_Pin_4 0x10
+#define IO_Pin_5 0x20
+#define IO_Pin_6 0x40
+#define IO_Pin_7 0x80
+#define IO_Pin_ALL 0xFF
 
 uint8_t ioe_init(void);
 uint8_t ioe_reset(void);
diff --git a/include/platform/stm32f429/lcd.h b/include/platform/stm32f429/lcd.h
index 4848fe96..fc06fc30 100644
--- a/include/platform/stm32f429/lcd.h
+++ b/include/platform/stm32f429/lcd.h
@@ -4,51 +4,51 @@
 #include <platform/link.h>
 #include <platform/stm32f429/registers.h>
 
-#define LCD_PIXEL_WIDTH     ((uint16_t)240)
-#define LCD_PIXEL_HEIGHT    ((uint16_t)320)
+#define LCD_PIXEL_WIDTH ((uint16_t) 240)
+#define LCD_PIXEL_HEIGHT ((uint16_t) 320)
 
-#define LCD_FRAME_BUFFER	((uint32_t)0xD0000000)
-#define BUFFER_OFFSET		((uint32_t)0x50000)
+#define LCD_FRAME_BUFFER ((uint32_t) 0xD0000000)
+#define BUFFER_OFFSET ((uint32_t) 0x50000)
 
-#define LCD_BACKGROUND_LAYER     0x0000
-#define LCD_FOREGROUND_LAYER     0x0001
+#define LCD_BACKGROUND_LAYER 0x0000
+#define LCD_FOREGROUND_LAYER 0x0001
 
-#define LCD_NCS_PIN			2
-#define LCD_NCS_GPIO_PORT	GPIOC
-#define LCD_NCS_GPIO_CLK	RCC_AHB1ENR_GPIOCEN
-#define LCD_NCS_PIN			2
+#define LCD_NCS_PIN 2
+#define LCD_NCS_GPIO_PORT GPIOC
+#define LCD_NCS_GPIO_CLK RCC_AHB1ENR_GPIOCEN
+#define LCD_NCS_PIN 2
 
-#define LCD_WRX_GPIO_PORT	GPIOD
-#define LCD_WRX_GPIO_CLK	RCC_AHB1ENR_GPIODEN
-#define LCD_WRX_PIN			13
+#define LCD_WRX_GPIO_PORT GPIOD
+#define LCD_WRX_GPIO_CLK RCC_AHB1ENR_GPIODEN
+#define LCD_WRX_PIN 13
 
-#define LCD_SPI_SCK_PIN		7
-#define LCD_SPI_SCK_GPIO_PORT	GPIOF
-#define LCD_SPI_SCK_GPIO_CLK	RCC_AHB1ENR_GPIOFEN
-#define LCD_SPI_MISO_PIN	8
-#define LCD_SPI_MISO_GPIO_PORT	GPIOF
-#define LCD_SPI_MISO_GPIO_CLK	RCC_AHB1ENR_GPIOFEN
-#define LCD_SPI_MOSI_PIN	9
-#define LCD_SPI_MOSI_GPIO_PORT	GPIOF
-#define LCD_SPI_MOSI_GPIO_CLK	RCC_AHB1ENR_GPIOFEN
-#define LCD_SPI                 SPI5_BASE
-#define LCD_SPI_CLK             RCC_APB2ENR_SPI5EN
+#define LCD_SPI_SCK_PIN 7
+#define LCD_SPI_SCK_GPIO_PORT GPIOF
+#define LCD_SPI_SCK_GPIO_CLK RCC_AHB1ENR_GPIOFEN
+#define LCD_SPI_MISO_PIN 8
+#define LCD_SPI_MISO_GPIO_PORT GPIOF
+#define LCD_SPI_MISO_GPIO_CLK RCC_AHB1ENR_GPIOFEN
+#define LCD_SPI_MOSI_PIN 9
+#define LCD_SPI_MOSI_GPIO_PORT GPIOF
+#define LCD_SPI_MOSI_GPIO_CLK RCC_AHB1ENR_GPIOFEN
+#define LCD_SPI SPI5_BASE
+#define LCD_SPI_CLK RCC_APB2ENR_SPI5EN
 
 /* LCD COLOR */
-#define LCD_COLOR_WHITE          0xFFFF
-#define LCD_COLOR_BLACK          0x0000
-#define LCD_COLOR_GREY           0xF7DE
-#define LCD_COLOR_BLUE           0x001F
-#define LCD_COLOR_BLUE2          0x051F
-#define LCD_COLOR_RED            0xF800
-#define LCD_COLOR_MAGENTA        0xF81F
-#define LCD_COLOR_GREEN          0x07E0
-#define LCD_COLOR_CYAN           0x7FFF
-#define LCD_COLOR_YELLOW         0xFFE0
+#define LCD_COLOR_WHITE 0xFFFF
+#define LCD_COLOR_BLACK 0x0000
+#define LCD_COLOR_GREY 0xF7DE
+#define LCD_COLOR_BLUE 0x001F
+#define LCD_COLOR_BLUE2 0x051F
+#define LCD_COLOR_RED 0xF800
+#define LCD_COLOR_MAGENTA 0xF81F
+#define LCD_COLOR_GREEN 0x07E0
+#define LCD_COLOR_CYAN 0x7FFF
+#define LCD_COLOR_YELLOW 0xFFE0
 
 /* LCD Direction */
-#define LCD_DIR_HORIZONTAL       0x0000
-#define LCD_DIR_VERTICAL         0x0001
+#define LCD_DIR_HORIZONTAL 0x0000
+#define LCD_DIR_VERTICAL 0x0001
 
 void lcd_init(void);
 void lcd_write_cmd(uint8_t lcdreg);
@@ -70,4 +70,3 @@ void lcd_draw_line(uint16_t x, uint16_t y, uint16_t length, uint8_t direction);
 void lcd_draw_rect(uint16_t x, uint16_t y, uint16_t height, uint16_t width);
 void lcd_fill_rect(uint16_t x, uint16_t y, uint16_t height, uint16_t width);
 #endif
-
diff --git a/include/platform/stm32f429/ltdc.h b/include/platform/stm32f429/ltdc.h
index 1a4d3fee..8b6acd72 100644
--- a/include/platform/stm32f429/ltdc.h
+++ b/include/platform/stm32f429/ltdc.h
@@ -4,123 +4,130 @@
 #include <platform/link.h>
 #include <platform/stm32f429/registers.h>
 
-#define LTDC_HSPolarity_AL               ((uint32_t)0x00000000)                  /* Horizontal Synchronization is active low */
-#define LTDC_HSPolarity_AH               ((uint32_t)0x80000000)                  /* Horizontal Synchronization is active high */
+#define LTDC_HSPolarity_AL \
+    ((uint32_t) 0x00000000) /* Horizontal Synchronization is active low */
+#define LTDC_HSPolarity_AH \
+    ((uint32_t) 0x80000000) /* Horizontal Synchronization is active high */
 
-#define LTDC_VSPolarity_AL               ((uint32_t)0x00000000)                  /* Vertical Synchronization is active low */
-#define LTDC_VSPolarity_AH               ((uint32_t)0x40000000)                  /* Vertical Synchronization is active high */
+#define LTDC_VSPolarity_AL \
+    ((uint32_t) 0x00000000) /* Vertical Synchronization is active low */
+#define LTDC_VSPolarity_AH \
+    ((uint32_t) 0x40000000) /* Vertical Synchronization is active high */
 
-#define LTDC_DEPolarity_AL               ((uint32_t)0x00000000)                  /* Data Enable, is active low */
-#define LTDC_DEPolarity_AH               ((uint32_t)0x20000000)                  /* Data Enable, is active high */
+#define LTDC_DEPolarity_AL \
+    ((uint32_t) 0x00000000) /* Data Enable, is active low */
+#define LTDC_DEPolarity_AH \
+    ((uint32_t) 0x20000000) /* Data Enable, is active high */
 
-#define LTDC_PCPolarity_IPC              ((uint32_t)0x00000000)                  /* input pixel clock */
-#define LTDC_PCPolarity_IIPC             ((uint32_t)0x10000000)                  /* inverted input pixel clock */
+#define LTDC_PCPolarity_IPC ((uint32_t) 0x00000000) /* input pixel clock */
+#define LTDC_PCPolarity_IIPC \
+    ((uint32_t) 0x10000000) /* inverted input pixel clock */
 
 /* LTDC pixel format */
-#define LTDC_Pixelformat_ARGB8888        ((uint32_t)0x00000000)
-#define LTDC_Pixelformat_RGB888          ((uint32_t)0x00000001)
-#define LTDC_Pixelformat_RGB565          ((uint32_t)0x00000002)
-#define LTDC_Pixelformat_ARGB1555        ((uint32_t)0x00000003)
-#define LTDC_Pixelformat_ARGB4444        ((uint32_t)0x00000004)
-#define LTDC_Pixelformat_L8              ((uint32_t)0x00000005)
-#define LTDC_Pixelformat_AL44            ((uint32_t)0x00000006)
-#define LTDC_Pixelformat_AL88            ((uint32_t)0x00000007)
+#define LTDC_Pixelformat_ARGB8888 ((uint32_t) 0x00000000)
+#define LTDC_Pixelformat_RGB888 ((uint32_t) 0x00000001)
+#define LTDC_Pixelformat_RGB565 ((uint32_t) 0x00000002)
+#define LTDC_Pixelformat_ARGB1555 ((uint32_t) 0x00000003)
+#define LTDC_Pixelformat_ARGB4444 ((uint32_t) 0x00000004)
+#define LTDC_Pixelformat_L8 ((uint32_t) 0x00000005)
+#define LTDC_Pixelformat_AL44 ((uint32_t) 0x00000006)
+#define LTDC_Pixelformat_AL88 ((uint32_t) 0x00000007)
 
 /* LTDC blending factor1 */
-#define LTDC_BlendingFactor1_CA          ((uint32_t)0x00000400)
-#define LTDC_BlendingFactor1_PAxCA       ((uint32_t)0x00000600)
+#define LTDC_BlendingFactor1_CA ((uint32_t) 0x00000400)
+#define LTDC_BlendingFactor1_PAxCA ((uint32_t) 0x00000600)
 
 /* LTDC blending factor2 */
-#define LTDC_BlendingFactor2_CA          ((uint32_t)0x00000005)
-#define LTDC_BlendingFactor2_PAxCA       ((uint32_t)0x00000007)
+#define LTDC_BlendingFactor2_CA ((uint32_t) 0x00000005)
+#define LTDC_BlendingFactor2_PAxCA ((uint32_t) 0x00000007)
 
 /* Layer Enable */
-#define LTDC_LxCR_LEN                    ((uint32_t) 1 << 0)
+#define LTDC_LxCR_LEN ((uint32_t) 1 << 0)
 /* Color Keying Enable */
-#define LTDC_LxCR_COLKEN                 ((uint32_t) 1 << 1)
+#define LTDC_LxCR_COLKEN ((uint32_t) 1 << 1)
 /* Color Lockup Table Enable */
-#define LTDC_LxCR_CLUTEN                 ((uint32_t) 1 << 4)
+#define LTDC_LxCR_CLUTEN ((uint32_t) 1 << 4)
 
 /* Dither Enable */
-#define LTDC_GCR_DTEN                    ((uint32_t)0x00010000)
+#define LTDC_GCR_DTEN ((uint32_t) 0x00010000)
 
 /* Window Horizontal Start Position */
-#define LTDC_LxWHPCR_WHSPOS             ((uint32_t)0x00000FFF)
+#define LTDC_LxWHPCR_WHSPOS ((uint32_t) 0x00000FFF)
 /* Window Horizontal End Position */
-#define LTDC_LxWHPCR_WHEPOS             ((uint32_t)0xFFFF0000)
+#define LTDC_LxWHPCR_WHEPOS ((uint32_t) 0xFFFF0000)
 
 /* Window Vertical Start Position */
-#define LTDC_LxWVPCR_WVSPOS             ((uint32_t)0x00000FFF)
+#define LTDC_LxWVPCR_WVSPOS ((uint32_t) 0x00000FFF)
 /* Window Vertical End Position */
-#define LTDC_LxWVPCR_WVEPOS             ((uint32_t)0xFFFF0000)
+#define LTDC_LxWVPCR_WVEPOS ((uint32_t) 0xFFFF0000)
 
 /* Pixel Format */
-#define LTDC_LxPFCR_PF                  ((uint32_t)0x00000007)
+#define LTDC_LxPFCR_PF ((uint32_t) 0x00000007)
 
 /* Default Color Blue */
-#define LTDC_LxDCCR_DCBLUE              ((uint32_t)0x000000FF)
+#define LTDC_LxDCCR_DCBLUE ((uint32_t) 0x000000FF)
 /* Default Color Green */
-#define LTDC_LxDCCR_DCGREEN             ((uint32_t)0x0000FF00)
+#define LTDC_LxDCCR_DCGREEN ((uint32_t) 0x0000FF00)
 /* Default Color Red */
-#define LTDC_LxDCCR_DCRED               ((uint32_t)0x00FF0000)
+#define LTDC_LxDCCR_DCRED ((uint32_t) 0x00FF0000)
 /* Default Color Alpha */
-#define LTDC_LxDCCR_DCALPHA             ((uint32_t)0xFF000000)
+#define LTDC_LxDCCR_DCALPHA ((uint32_t) 0xFF000000)
 
 /* Constant Alpha */
-#define LTDC_LxCACR_CONSTA              ((uint32_t)0x000000FF)
+#define LTDC_LxCACR_CONSTA ((uint32_t) 0x000000FF)
 
 /* Blending Factor 2 */
-#define LTDC_LxBFCR_BF2                 ((uint32_t)0x00000007)
+#define LTDC_LxBFCR_BF2 ((uint32_t) 0x00000007)
 /* Blending Factor 1 */
-#define LTDC_LxBFCR_BF1                 ((uint32_t)0x00000700)
+#define LTDC_LxBFCR_BF1 ((uint32_t) 0x00000700)
 
 /* Color Frame Buffer Start Address */
-#define LTDC_LxCFBAR_CFBADD             ((uint32_t)0xFFFFFFFF)
+#define LTDC_LxCFBAR_CFBADD ((uint32_t) 0xFFFFFFFF)
 /* Color Frame Buffer Line Length */
-#define LTDC_LxCFBLR_CFBLL              ((uint32_t)0x00001FFF)
+#define LTDC_LxCFBLR_CFBLL ((uint32_t) 0x00001FFF)
 /* Color Frame Buffer Pitch in Bytes */
-#define LTDC_LxCFBLR_CFBP               ((uint32_t)0x1FFF0000)
+#define LTDC_LxCFBLR_CFBP ((uint32_t) 0x1FFF0000)
 /* Color Frame Buffer Line Number */
-#define LTDC_LxCFBLNR_CFBLNBR           ((uint32_t)0x000007FF)
+#define LTDC_LxCFBLNR_CFBLNBR ((uint32_t) 0x000007FF)
 
 /* Immediately Reload */
-#define LTDC_IMReload                   ((uint32_t) 1 << 0)
+#define LTDC_IMReload ((uint32_t) 1 << 0)
 
 struct ltdc_cfg {
-	uint32_t hs_polarity;
-	uint32_t vs_polarity;
-	uint32_t de_polarity;
-	uint32_t pc_polarity;
-	uint32_t horizontal_sync;
-	uint32_t vertical_sync;
-	uint32_t accumulated_hbp;
-	uint32_t accumulated_vbp;
-	uint32_t accumulated_active_w;
-	uint32_t accumulated_active_h;
-	uint32_t total_width;
-	uint32_t total_height;
-	uint32_t bg_red_value;
-	uint32_t bg_green_value;
-	uint32_t bg_blue_value;
+    uint32_t hs_polarity;
+    uint32_t vs_polarity;
+    uint32_t de_polarity;
+    uint32_t pc_polarity;
+    uint32_t horizontal_sync;
+    uint32_t vertical_sync;
+    uint32_t accumulated_hbp;
+    uint32_t accumulated_vbp;
+    uint32_t accumulated_active_w;
+    uint32_t accumulated_active_h;
+    uint32_t total_width;
+    uint32_t total_height;
+    uint32_t bg_red_value;
+    uint32_t bg_green_value;
+    uint32_t bg_blue_value;
 };
 
 struct ltdc_layer_cfg {
-	uint32_t horizontal_start;
-	uint32_t horizontal_end;
-	uint32_t vertical_start;
-	uint32_t vertical_end;
-	uint32_t pixel_format;
-	uint32_t constant_alpha;
-	uint32_t default_blue;
-	uint32_t default_green;
-	uint32_t default_red;
-	uint32_t default_alpha;
-	uint32_t blending_factor1;
-	uint32_t blending_factor2;
-	uint32_t cfb_start_address;
-	uint32_t cfb_line_length;
-	uint32_t cfb_pitch;
-	uint32_t cfb_line_number;
+    uint32_t horizontal_start;
+    uint32_t horizontal_end;
+    uint32_t vertical_start;
+    uint32_t vertical_end;
+    uint32_t pixel_format;
+    uint32_t constant_alpha;
+    uint32_t default_blue;
+    uint32_t default_green;
+    uint32_t default_red;
+    uint32_t default_alpha;
+    uint32_t blending_factor1;
+    uint32_t blending_factor2;
+    uint32_t cfb_start_address;
+    uint32_t cfb_line_length;
+    uint32_t cfb_pitch;
+    uint32_t cfb_line_number;
 };
 
 void ltdc_config(struct ltdc_cfg *cfg);
diff --git a/include/platform/stm32f429/nvic.h b/include/platform/stm32f429/nvic.h
index e9949fbb..617f9131 100644
--- a/include/platform/stm32f429/nvic.h
+++ b/include/platform/stm32f429/nvic.h
@@ -6,267 +6,291 @@
 #ifndef __PLATFORM_STM32F429_NVIC_H__
 #define __PLATFORM_STM32F429_NVIC_H__
 
-#include <platform/stm32f429/registers.h>
 #include <platform/cortex_m.h>
+#include <platform/stm32f429/registers.h>
 
-#define IRQ_ENABLE	1
-#define IRQ_DISABLE	0
+#define IRQ_ENABLE 1
+#define IRQ_DISABLE 0
 
 typedef enum IRQn {
-	/* Cortex-M4 Processor Exceptions Numbers */
-	NonMaskableInt_IRQn	= -14,	/*!< 2 Non Maskable Interrupt */
-	MemoryManagement_IRQn	= -12,	/*!< 4 Cortex-M4 Memory Management Interrupt */
-	BusFault_IRQn		= -11,	/*!< 5 Cortex-M4 Bus Fault Interrupt */
-	UsageFault_IRQn		= -10,	/*!< 6 Cortex-M4 Usage Fault Interrupt */
-	SVCall_IRQn		= -5,	/*!< 11 Cortex-M4 SV Call Interrupt */
-	DebugMonitor_IRQn	= -4,	/*!< 12 Cortex-M4 Debug Monitor Interrupt */
-	PendSV_IRQn		= -2,	/*!< 14 Cortex-M4 Pend SV Interrupt */
-	SysTick_IRQn		= -1,	/*!< 15 Cortex-M4 System Tick Interrupt */
+    /* Cortex-M4 Processor Exceptions Numbers */
+    NonMaskableInt_IRQn = -14,   /*!< 2 Non Maskable Interrupt */
+    MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+    BusFault_IRQn = -11,         /*!< 5 Cortex-M4 Bus Fault Interrupt */
+    UsageFault_IRQn = -10,       /*!< 6 Cortex-M4 Usage Fault Interrupt */
+    SVCall_IRQn = -5,            /*!< 11 Cortex-M4 SV Call Interrupt */
+    DebugMonitor_IRQn = -4,      /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+    PendSV_IRQn = -2,            /*!< 14 Cortex-M4 Pend SV Interrupt */
+    SysTick_IRQn = -1,           /*!< 15 Cortex-M4 System Tick Interrupt */
 
-	/* STM32 specific Interrupt Numbers */
-	WWDG_IRQn		= 0,	/*!< Window WatchDog Interrupt */
-	PVD_IRQn		= 1,	/*!< PVD through EXTI Line detection Interrupt */
-	TAMP_STAMP_IRQn		= 2,	/*!< Tamper and TimeStamp interrupts through the EXTI line */
-	RTC_WKUP_IRQn		= 3,	/*!< RTC Wakeup interrupt through the EXTI line */
-	FLASH_IRQn		= 4,	/*!< FLASH global Interrupt */
-	RCC_IRQn		= 5,	/*!< RCC global Interrupt */
-	EXTI0_IRQn		= 6,	/*!< EXTI Line0 Interrupt */
-	EXTI1_IRQn		= 7,	/*!< EXTI Line1 Interrupt */
-	EXTI2_IRQn		= 8,	/*!< EXTI Line2 Interrupt */
-	EXTI3_IRQn		= 9,	/*!< EXTI Line3 Interrupt */
-	EXTI4_IRQn		= 10,	/*!< EXTI Line4 Interrupt */
-	DMA1_Stream0_IRQn	= 11,	/*!< DMA1 Stream 0 global Interrupt */
-	DMA1_Stream1_IRQn	= 12,	/*!< DMA1 Stream 1 global Interrupt */
-	DMA1_Stream2_IRQn	= 13,	/*!< DMA1 Stream 2 global Interrupt */
-	DMA1_Stream3_IRQn	= 14,	/*!< DMA1 Stream 3 global Interrupt */
-	DMA1_Stream4_IRQn	= 15,	/*!< DMA1 Stream 4 global Interrupt */
-	DMA1_Stream5_IRQn	= 16,	/*!< DMA1 Stream 5 global Interrupt */
-	DMA1_Stream6_IRQn	= 17,	/*!< DMA1 Stream 6 global Interrupt */
-	ADC_IRQn		= 18,	/*!< ADC1, ADC2 and ADC3 global Interrupts */
-	CAN1_TX_IRQn		= 19,	/*!< CAN1 TX Interrupt */
-	CAN1_RX0_IRQn		= 20,	/*!< CAN1 RX0 Interrupt */
-	CAN1_RX1_IRQn		= 21,	/*!< CAN1 RX1 Interrupt */
-	CAN1_SCE_IRQn		= 22,	/*!< CAN1 SCE Interrupt */
-	EXTI9_5_IRQn		= 23,	/*!< External Line[9:5] Interrupts */
-	TIM1_BRK_TIM9_IRQn	= 24,	/*!< TIM1 Break interrupt and TIM9 global interrupt */
-	TIM1_UP_TIM10_IRQn	= 25,	/*!< TIM1 Update Interrupt and TIM10 global interrupt */
-	TIM1_TRG_COM_TIM11_IRQn	= 26,	/*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-	TIM1_CC_IRQn		= 27,	/*!< TIM1 Capture Compare Interrupt */
-	TIM2_IRQn		= 28,	/*!< TIM2 global Interrupt */
-	TIM3_IRQn		= 29,	/*!< TIM3 global Interrupt */
-	TIM4_IRQn		= 30,	/*!< TIM4 global Interrupt */
-	I2C1_EV_IRQn		= 31,	/*!< I2C1 Event Interrupt */
-	I2C1_ER_IRQn		= 32,	/*!< I2C1 Error Interrupt */
-	I2C2_EV_IRQn		= 33,	/*!< I2C2 Event Interrupt */
-	I2C2_ER_IRQn		= 34,	/*!< I2C2 Error Interrupt */
-	SPI1_IRQn		= 35,	/*!< SPI1 global Interrupt */
-	SPI2_IRQn		= 36,	/*!< SPI2 global Interrupt */
-	USART1_IRQn		= 37,	/*!< USART1 global Interrupt */
-	USART2_IRQn		= 38,	/*!< USART2 global Interrupt */
-	USART3_IRQn		= 39,	/*!< USART3 global Interrupt */
-	EXTI15_10_IRQn		= 40,	/*!< External Line[15:10] Interrupts */
-	RTC_Alarm_IRQn		= 41,	/*!< RTC Alarm (A and B) through EXTI Line Interrupt */
-	OTG_FS_WKUP_IRQn	= 42,	/*!< USB OTG FS Wakeup through EXTI line interrupt */
-	TIM8_BRK_TIM12_IRQn	= 43,	/*!< TIM8 Break Interrupt and TIM12 global interrupt */
-	TIM8_UP_TIM13_IRQn	= 44,	/*!< TIM8 Update Interrupt and TIM13 global interrupt */
-	TIM8_TRG_COM_TIM14_IRQn	= 45,	/*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-	TIM8_CC_IRQn		= 46,	/*!< TIM8 Capture Compare Interrupt */
-	DMA1_Stream7_IRQn	= 47,	/*!< DMA1 Stream7 Interrupt */
-	FSMC_IRQn		= 48,	/*!< FSMC global Interrupt */
-	SDIO_IRQn		= 49,	/*!< SDIO global Interrupt */
-	TIM5_IRQn		= 50,	/*!< TIM5 global Interrupt */
-	SPI3_IRQn		= 51,	/*!< SPI3 global Interrupt */
-	UART4_IRQn		= 52,	/*!< UART4 global Interrupt */
-	UART5_IRQn		= 53,	/*!< UART5 global Interrupt */
-	TIM6_DAC_IRQn		= 54,	/*!< TIM6 global and DAC1&2 underrun error interrupts */
-	TIM7_IRQn		= 55,	/*!< TIM7 global interrupt */
-	DMA2_Stream0_IRQn	= 56,	/*!< DMA2 Stream 0 global Interrupt */
-	DMA2_Stream1_IRQn	= 57,	/*!< DMA2 Stream 1 global Interrupt */
-	DMA2_Stream2_IRQn	= 58,	/*!< DMA2 Stream 2 global Interrupt */
-	DMA2_Stream3_IRQn	= 59,	/*!< DMA2 Stream 3 global Interrupt */
-	DMA2_Stream4_IRQn	= 60,	/*!< DMA2 Stream 4 global Interrupt */
-	ETH_IRQn		= 61,	/*!< Ethernet global Interrupt */
-	ETH_WKUP_IRQn		= 62,	/*!< Ethernet Wakeup through EXTI line Interrupt */
-	CAN2_TX_IRQn		= 63,	/*!< CAN2 TX Interrupt */
-	CAN2_RX0_IRQn		= 64,	/*!< CAN2 RX0 Interrupt */
-	CAN2_RX1_IRQn		= 65,	/*!< CAN2 RX1 Interrupt */
-	CAN2_SCE_IRQn		= 66,	/*!< CAN2 SCE Interrupt */
-	OTG_FS_IRQn		= 67,	/*!< USB OTG FS global Interrupt */
-	DMA2_Stream5_IRQn	= 68,	/*!< DMA2 Stream 5 global interrupt */
-	DMA2_Stream6_IRQn	= 69,	/*!< DMA2 Stream 6 global interrupt */
-	DMA2_Stream7_IRQn	= 70,	/*!< DMA2 Stream 7 global interrupt */
-	USART6_IRQn		= 71,	/*!< USART6 global interrupt */
-	I2C3_EV_IRQn		= 72,	/*!< I2C3 event interrupt */
-	I2C3_ER_IRQn		= 73,	/*!< I2C3 error interrupt */
-	OTG_HS_EP1_OUT_IRQn	= 74,	/*!< USB OTG HS End Point 1 Out global interrupt */
-	OTG_HS_EP1_IN_IRQn	= 75,	/*!< USB OTG HS End Point 1 In global interrupt */
-	OTG_HS_WKUP_IRQn	= 76,	/*!< USB OTG HS Wakeup through EXTI interrupt */
-	OTG_HS_IRQn		= 77,	/*!< USB OTG HS global interrupt */
-	DCMI_IRQn		= 78,	/*!< DCMI global interrupt */
-	CRYP_IRQn		= 79,	/*!< CRYP crypto global interrupt */
-	HASH_RNG_IRQn		= 80,	/*!< Hash and Rng global interrupt */
-	FPU_IRQn		= 81,	/*!< FPU global interrupt */
-	IRQn_NUM,
+    /* STM32 specific Interrupt Numbers */
+    WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+    PVD_IRQn = 1,  /*!< PVD through EXTI Line detection Interrupt */
+    TAMP_STAMP_IRQn =
+        2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+    RTC_WKUP_IRQn = 3,      /*!< RTC Wakeup interrupt through the EXTI line */
+    FLASH_IRQn = 4,         /*!< FLASH global Interrupt */
+    RCC_IRQn = 5,           /*!< RCC global Interrupt */
+    EXTI0_IRQn = 6,         /*!< EXTI Line0 Interrupt */
+    EXTI1_IRQn = 7,         /*!< EXTI Line1 Interrupt */
+    EXTI2_IRQn = 8,         /*!< EXTI Line2 Interrupt */
+    EXTI3_IRQn = 9,         /*!< EXTI Line3 Interrupt */
+    EXTI4_IRQn = 10,        /*!< EXTI Line4 Interrupt */
+    DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+    DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+    DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+    DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+    DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+    DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+    DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+    ADC_IRQn = 18,          /*!< ADC1, ADC2 and ADC3 global Interrupts */
+    CAN1_TX_IRQn = 19,      /*!< CAN1 TX Interrupt */
+    CAN1_RX0_IRQn = 20,     /*!< CAN1 RX0 Interrupt */
+    CAN1_RX1_IRQn = 21,     /*!< CAN1 RX1 Interrupt */
+    CAN1_SCE_IRQn = 22,     /*!< CAN1 SCE Interrupt */
+    EXTI9_5_IRQn = 23,      /*!< External Line[9:5] Interrupts */
+    TIM1_BRK_TIM9_IRQn =
+        24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+    TIM1_UP_TIM10_IRQn =
+        25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+    TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt
+                                     and TIM11 global interrupt */
+    TIM1_CC_IRQn = 27,            /*!< TIM1 Capture Compare Interrupt */
+    TIM2_IRQn = 28,               /*!< TIM2 global Interrupt */
+    TIM3_IRQn = 29,               /*!< TIM3 global Interrupt */
+    TIM4_IRQn = 30,               /*!< TIM4 global Interrupt */
+    I2C1_EV_IRQn = 31,            /*!< I2C1 Event Interrupt */
+    I2C1_ER_IRQn = 32,            /*!< I2C1 Error Interrupt */
+    I2C2_EV_IRQn = 33,            /*!< I2C2 Event Interrupt */
+    I2C2_ER_IRQn = 34,            /*!< I2C2 Error Interrupt */
+    SPI1_IRQn = 35,               /*!< SPI1 global Interrupt */
+    SPI2_IRQn = 36,               /*!< SPI2 global Interrupt */
+    USART1_IRQn = 37,             /*!< USART1 global Interrupt */
+    USART2_IRQn = 38,             /*!< USART2 global Interrupt */
+    USART3_IRQn = 39,             /*!< USART3 global Interrupt */
+    EXTI15_10_IRQn = 40,          /*!< External Line[15:10] Interrupts */
+    RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+    OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+    TIM8_BRK_TIM12_IRQn =
+        43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+    TIM8_UP_TIM13_IRQn =
+        44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+    TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt
+                                     and TIM14 global interrupt */
+    TIM8_CC_IRQn = 46,            /*!< TIM8 Capture Compare Interrupt */
+    DMA1_Stream7_IRQn = 47,       /*!< DMA1 Stream7 Interrupt */
+    FSMC_IRQn = 48,               /*!< FSMC global Interrupt */
+    SDIO_IRQn = 49,               /*!< SDIO global Interrupt */
+    TIM5_IRQn = 50,               /*!< TIM5 global Interrupt */
+    SPI3_IRQn = 51,               /*!< SPI3 global Interrupt */
+    UART4_IRQn = 52,              /*!< UART4 global Interrupt */
+    UART5_IRQn = 53,              /*!< UART5 global Interrupt */
+    TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+    TIM7_IRQn = 55,     /*!< TIM7 global interrupt */
+    DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+    DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+    DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+    DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+    DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+    ETH_IRQn = 61,          /*!< Ethernet global Interrupt */
+    ETH_WKUP_IRQn = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt */
+    CAN2_TX_IRQn = 63,      /*!< CAN2 TX Interrupt */
+    CAN2_RX0_IRQn = 64,     /*!< CAN2 RX0 Interrupt */
+    CAN2_RX1_IRQn = 65,     /*!< CAN2 RX1 Interrupt */
+    CAN2_SCE_IRQn = 66,     /*!< CAN2 SCE Interrupt */
+    OTG_FS_IRQn = 67,       /*!< USB OTG FS global Interrupt */
+    DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+    DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+    DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+    USART6_IRQn = 71,       /*!< USART6 global interrupt */
+    I2C3_EV_IRQn = 72,      /*!< I2C3 event interrupt */
+    I2C3_ER_IRQn = 73,      /*!< I2C3 error interrupt */
+    OTG_HS_EP1_OUT_IRQn =
+        74,                  /*!< USB OTG HS End Point 1 Out global interrupt */
+    OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+    OTG_HS_WKUP_IRQn = 76,   /*!< USB OTG HS Wakeup through EXTI interrupt */
+    OTG_HS_IRQn = 77,        /*!< USB OTG HS global interrupt */
+    DCMI_IRQn = 78,          /*!< DCMI global interrupt */
+    CRYP_IRQn = 79,          /*!< CRYP crypto global interrupt */
+    HASH_RNG_IRQn = 80,      /*!< Hash and Rng global interrupt */
+    FPU_IRQn = 81,           /*!< FPU global interrupt */
+    IRQn_NUM,
 } IRQn_Type;
 
 #define MAX_IRQn FPU_IRQn
 
 /* Define device IRQ handler name */
-#define WWDG_HANDLER                nvic_handler0
-#define PVD_HANDLER                 nvic_handler1
-#define TAMP_STAMP_HANDLER          nvic_handler2
-#define RTC_WKUP_HANDLER            nvic_handler3
-#define FLASH_HANDLER               nvic_handler4
-#define RCC_HANDLER                 nvic_handler5
-#define EXTI0_HANDLER               nvic_handler6
-#define EXTI1_HANDLER               nvic_handler7
-#define EXTI2_HANDLER               nvic_handler8
-#define EXTI3_HANDLER               nvic_handler9
-#define EXTI4_HANDLER               nvic_handler10
-#define DMA1_Stream0_HANDLER        nvic_handler11
-#define DMA1_Stream1_HANDLER        nvic_handler12
-#define DMA1_Stream2_HANDLER        nvic_handler13
-#define DMA1_Stream3_HANDLER        nvic_handler14
-#define DMA1_Stream4_HANDLER        nvic_handler15
-#define DMA1_Stream5_HANDLER        nvic_handler16
-#define DMA1_Stream6_HANDLER        nvic_handler17
-#define ADC_HANDLER                 nvic_handler18
-#define CAN1_TX_HANDLER             nvic_handler19
-#define CAN1_RX0_HANDLER            nvic_handler20
-#define CAN1_RX1_HANDLER            nvic_handler21
-#define CAN1_SCE_HANDLER            nvic_handler22
-#define EXTI9_5_HANDLER             nvic_handler23
-#define TIM1_BRK_TIM9_HANDLER       nvic_handler24
-#define TIM1_UP_TIM10_HANDLER       nvic_handler25
-#define TIM1_TRG_COM_TIM11_HANDLER  nvic_handler26
-#define TIM1_CC_HANDLER             nvic_handler27
-#define TIM2_HANDLER                nvic_handler28
-#define TIM3_HANDLER                nvic_handler29
-#define TIM4_HANDLER                nvic_handler30
-#define I2C1_EV_HANDLER             nvic_handler31
-#define I2C1_ER_HANDLER             nvic_handler32
-#define I2C2_EV_HANDLER             nvic_handler33
-#define I2C2_ER_HANDLER             nvic_handler34
-#define SPI1_HANDLER                nvic_handler35
-#define SPI2_HANDLER                nvic_handler36
-#define USART1_HANDLER              nvic_handler37
-#define USART2_HANDLER              nvic_handler38
-#define USART2_HANDLER              nvic_handler38
-#define USART3_HANDLER              nvic_handler39
-#define EXTI15_10_HANDLER           nvic_handler40
-#define RTC_Alarm_HANDLER           nvic_handler41
-#define OTG_FS_WKUP_HANDLER         nvic_handler42
-#define TIM8_BRK_TIM12_HANDLER      nvic_handler43
-#define TIM8_UP_TIM13_HANDLER       nvic_handler44
-#define TIM8_TRG_COM_TIM14_HANDLER  nvic_handler45
-#define TIM8_CC_HANDLER             nvic_handler46
-#define DMA1_Stream7_HANDLER        nvic_handler47
-#define FSMC_HANDLER                nvic_handler48
-#define SDIO_HANDLER                nvic_handler49
-#define TIM5_HANDLER                nvic_handler50
-#define SPI3_HANDLER                nvic_handler51
-#define UART4_HANDLER               nvic_handler52
-#define UART5_HANDLER               nvic_handler53
-#define TIM6_DAC_HANDLER            nvic_handler54
-#define TIM7_HANDLER                nvic_handler55
-#define DMA2_Stream0_HANDLER        nvic_handler56
-#define DMA2_Stream1_HANDLER        nvic_handler57
-#define DMA2_Stream2_HANDLER        nvic_handler58
-#define DMA2_Stream3_HANDLER        nvic_handler59
-#define DMA2_Stream4_HANDLER        nvic_handler60
-#define ETH_HANDLER                 nvic_handler61
-#define ETH_WKUP_HANDLER            nvic_handler62
-#define CAN2_TX_HANDLER             nvic_handler63
-#define CAN2_RX0_HANDLER            nvic_handler64
-#define CAN2_RX1_HANDLER            nvic_handler65
-#define CAN2_SCE_HANDLER            nvic_handler66
-#define OTG_FS_HANDLER              nvic_handler67
-#define DMA2_Stream5_HANDLER        nvic_handler68
-#define DMA2_Stream6_HANDLER        nvic_handler69
-#define DMA2_Stream7_HANDLER        nvic_handler70
-#define USART6_HANDLER              nvic_handler71
-#define I2C3_EV_HANDLER             nvic_handler72
-#define I2C3_ER_HANDLER             nvic_handler73
-#define OTG_HS_EP1_OUT_HANDLER      nvic_handler74
-#define OTG_HS_EP1_IN_HANDLER       nvic_handler75
-#define OTG_HS_WKUP_HANDLER         nvic_handler76
-#define OTG_HS_HANDLER              nvic_handler77
-#define DCMI_HANDLER                nvic_handler78
-#define CRYP_HANDLER                nvic_handler79
-#define HASH_RNG_HANDLER            nvic_handler80
-#define FPU_HANDLER                 nvic_handler81
+#define WWDG_HANDLER nvic_handler0
+#define PVD_HANDLER nvic_handler1
+#define TAMP_STAMP_HANDLER nvic_handler2
+#define RTC_WKUP_HANDLER nvic_handler3
+#define FLASH_HANDLER nvic_handler4
+#define RCC_HANDLER nvic_handler5
+#define EXTI0_HANDLER nvic_handler6
+#define EXTI1_HANDLER nvic_handler7
+#define EXTI2_HANDLER nvic_handler8
+#define EXTI3_HANDLER nvic_handler9
+#define EXTI4_HANDLER nvic_handler10
+#define DMA1_Stream0_HANDLER nvic_handler11
+#define DMA1_Stream1_HANDLER nvic_handler12
+#define DMA1_Stream2_HANDLER nvic_handler13
+#define DMA1_Stream3_HANDLER nvic_handler14
+#define DMA1_Stream4_HANDLER nvic_handler15
+#define DMA1_Stream5_HANDLER nvic_handler16
+#define DMA1_Stream6_HANDLER nvic_handler17
+#define ADC_HANDLER nvic_handler18
+#define CAN1_TX_HANDLER nvic_handler19
+#define CAN1_RX0_HANDLER nvic_handler20
+#define CAN1_RX1_HANDLER nvic_handler21
+#define CAN1_SCE_HANDLER nvic_handler22
+#define EXTI9_5_HANDLER nvic_handler23
+#define TIM1_BRK_TIM9_HANDLER nvic_handler24
+#define TIM1_UP_TIM10_HANDLER nvic_handler25
+#define TIM1_TRG_COM_TIM11_HANDLER nvic_handler26
+#define TIM1_CC_HANDLER nvic_handler27
+#define TIM2_HANDLER nvic_handler28
+#define TIM3_HANDLER nvic_handler29
+#define TIM4_HANDLER nvic_handler30
+#define I2C1_EV_HANDLER nvic_handler31
+#define I2C1_ER_HANDLER nvic_handler32
+#define I2C2_EV_HANDLER nvic_handler33
+#define I2C2_ER_HANDLER nvic_handler34
+#define SPI1_HANDLER nvic_handler35
+#define SPI2_HANDLER nvic_handler36
+#define USART1_HANDLER nvic_handler37
+#define USART2_HANDLER nvic_handler38
+#define USART2_HANDLER nvic_handler38
+#define USART3_HANDLER nvic_handler39
+#define EXTI15_10_HANDLER nvic_handler40
+#define RTC_Alarm_HANDLER nvic_handler41
+#define OTG_FS_WKUP_HANDLER nvic_handler42
+#define TIM8_BRK_TIM12_HANDLER nvic_handler43
+#define TIM8_UP_TIM13_HANDLER nvic_handler44
+#define TIM8_TRG_COM_TIM14_HANDLER nvic_handler45
+#define TIM8_CC_HANDLER nvic_handler46
+#define DMA1_Stream7_HANDLER nvic_handler47
+#define FSMC_HANDLER nvic_handler48
+#define SDIO_HANDLER nvic_handler49
+#define TIM5_HANDLER nvic_handler50
+#define SPI3_HANDLER nvic_handler51
+#define UART4_HANDLER nvic_handler52
+#define UART5_HANDLER nvic_handler53
+#define TIM6_DAC_HANDLER nvic_handler54
+#define TIM7_HANDLER nvic_handler55
+#define DMA2_Stream0_HANDLER nvic_handler56
+#define DMA2_Stream1_HANDLER nvic_handler57
+#define DMA2_Stream2_HANDLER nvic_handler58
+#define DMA2_Stream3_HANDLER nvic_handler59
+#define DMA2_Stream4_HANDLER nvic_handler60
+#define ETH_HANDLER nvic_handler61
+#define ETH_WKUP_HANDLER nvic_handler62
+#define CAN2_TX_HANDLER nvic_handler63
+#define CAN2_RX0_HANDLER nvic_handler64
+#define CAN2_RX1_HANDLER nvic_handler65
+#define CAN2_SCE_HANDLER nvic_handler66
+#define OTG_FS_HANDLER nvic_handler67
+#define DMA2_Stream5_HANDLER nvic_handler68
+#define DMA2_Stream6_HANDLER nvic_handler69
+#define DMA2_Stream7_HANDLER nvic_handler70
+#define USART6_HANDLER nvic_handler71
+#define I2C3_EV_HANDLER nvic_handler72
+#define I2C3_ER_HANDLER nvic_handler73
+#define OTG_HS_EP1_OUT_HANDLER nvic_handler74
+#define OTG_HS_EP1_IN_HANDLER nvic_handler75
+#define OTG_HS_WKUP_HANDLER nvic_handler76
+#define OTG_HS_HANDLER nvic_handler77
+#define DCMI_HANDLER nvic_handler78
+#define CRYP_HANDLER nvic_handler79
+#define HASH_RNG_HANDLER nvic_handler80
+#define FPU_HANDLER nvic_handler81
 
 
-#define IRQ_VEC_N_HANDLER_DECLARE(n) \
-	void nvic_handler##n (void);
+#define IRQ_VEC_N_HANDLER_DECLARE(n) void nvic_handler##n(void);
 
-#define IRQ_VEC_N_OP	IRQ_VEC_N_HANDLER_DECLARE
+#define IRQ_VEC_N_OP IRQ_VEC_N_HANDLER_DECLARE
 #include "platform/stm32f429/nvic_private.h"
 #undef IRQ_VEC_N_OP
 
 typedef struct {
-	volatile uint32_t ISER[8];	/*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-	uint32_t RESERVED0[24];
-	volatile uint32_t ICER[8];	/*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-	uint32_t RSERVED1[24];
-	volatile uint32_t ISPR[8];	/*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-	uint32_t RESERVED2[24];
-	volatile uint32_t ICPR[8];	/*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-	uint32_t RESERVED3[24];
-	volatile uint32_t IABR[8];	/*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-	uint32_t RESERVED4[56];
-	volatile uint8_t  IP[240];	/*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-	uint32_t RESERVED5[644];
-	volatile uint32_t STIR;		/*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+    volatile uint32_t
+        ISER[8]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[24];
+    volatile uint32_t
+        ICER[8]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[24];
+    volatile uint32_t
+        ISPR[8]; /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[24];
+    volatile uint32_t
+        ICPR[8]; /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[24];
+    volatile uint32_t
+        IABR[8]; /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+    uint32_t RESERVED4[56];
+    volatile uint8_t IP[240]; /*!< Offset: 0x300 (R/W)  Interrupt Priority
+                                 Register (8Bit wide) */
+    uint32_t RESERVED5[644];
+    volatile uint32_t
+        STIR; /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
 } NVIC_Type;
 
-#define NVIC_PriorityGroup_0         ((uint32_t) 0x700) /*!< 0 bits for pre-emption priority
+#define NVIC_PriorityGroup_0                                \
+    ((uint32_t) 0x700) /*!< 0 bits for pre-emption priority \
 4 bits for subpriority */
-#define NVIC_PriorityGroup_1         ((uint32_t) 0x600) /*!< 1 bits for pre-emption priority
+#define NVIC_PriorityGroup_1                                \
+    ((uint32_t) 0x600) /*!< 1 bits for pre-emption priority \
 3 bits for subpriority */
-#define NVIC_PriorityGroup_2         ((uint32_t) 0x500) /*!< 2 bits for pre-emption priority
-	2 bits for subpriority */
-#define NVIC_PriorityGroup_3         ((uint32_t) 0x400) /*!< 3 bits for pre-emption priority
-		1 bits for subpriority */
-#define NVIC_PriorityGroup_4         ((uint32_t) 0x300) /*!< 4 bits for pre-emption priority
-			0 bits for subpriority */
-#define NVIC \
-	((NVIC_Type *) NVIC_BASE)
+#define NVIC_PriorityGroup_2                                \
+    ((uint32_t) 0x500) /*!< 2 bits for pre-emption priority \
+2 bits for subpriority */
+#define NVIC_PriorityGroup_3                                \
+    ((uint32_t) 0x400) /*!< 3 bits for pre-emption priority \
+1 bits for subpriority */
+#define NVIC_PriorityGroup_4                                \
+    ((uint32_t) 0x300) /*!< 4 bits for pre-emption priority \
+0 bits for subpriority */
+#define NVIC ((NVIC_Type *) NVIC_BASE)
 
 
-				void NVIC_SetPriority(IRQn_Type IRQn, uint8_t group_priority, uint8_t sub_priority);
+void NVIC_SetPriority(IRQn_Type IRQn,
+                      uint8_t group_priority,
+                      uint8_t sub_priority);
 void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
 
-inline static void  NVIC_EnableIRQ(IRQn_Type IRQn)
+inline static void NVIC_EnableIRQ(IRQn_Type IRQn)
 {
-	NVIC->ISER[((uint32_t) IRQn >> 0x5)] = (1 << ((uint32_t)(IRQn) & 0x1f));
+    NVIC->ISER[((uint32_t) IRQn >> 0x5)] = (1 << ((uint32_t) (IRQn) & 0x1f));
 }
 
 inline static void NVIC_DisableIRQ(IRQn_Type IRQn)
 {
-	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+    NVIC->ICER[((uint32_t) (IRQn) >> 5)] = (1 << ((uint32_t) (IRQn) & 0x1F));
 }
 
 inline static uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
-	return (uint32_t)((NVIC->ISPR[(uint32_t)(IRQn) >> 5] &
-	                   (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0);
+    return (uint32_t) ((NVIC->ISPR[(uint32_t) (IRQn) >> 5] &
+                        (1 << ((uint32_t) (IRQn) & 0x1F)))
+                           ? 1
+                           : 0);
 }
 
 inline static void NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
-	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+    NVIC->ISPR[((uint32_t) (IRQn) >> 5)] = (1 << ((uint32_t) (IRQn) & 0x1F));
 }
 
 inline static void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
-	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+    NVIC->ICPR[((uint32_t) (IRQn) >> 5)] = (1 << ((uint32_t) (IRQn) & 0x1F));
 }
 
 inline static uint32_t NVIC_GetActive(IRQn_Type IRQn)
 {
-	return (uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] &
-	                   (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0);
+    return (uint32_t) ((NVIC->IABR[(uint32_t) (IRQn) >> 5] &
+                        (1 << ((uint32_t) (IRQn) & 0x1F)))
+                           ? 1
+                           : 0);
 }
 
 int nvic_is_setup(int irq);
diff --git a/include/platform/stm32f429/nvic_private.h b/include/platform/stm32f429/nvic_private.h
index 1f55ebbc..d459ba41 100644
--- a/include/platform/stm32f429/nvic_private.h
+++ b/include/platform/stm32f429/nvic_private.h
@@ -1,410 +1,410 @@
 /* This header is only included internally. */
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_WWDG_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_WWDG_USER_IRQ))
 IRQ_VEC_N_OP(0)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_PVD_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_PVD_USER_IRQ))
 IRQ_VEC_N_OP(1)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TAMP_STAMP_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TAMP_STAMP_USER_IRQ))
 IRQ_VEC_N_OP(2)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_RTC_WKUP_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_RTC_WKUP_USER_IRQ))
 IRQ_VEC_N_OP(3)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_FLASH_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_FLASH_USER_IRQ))
 IRQ_VEC_N_OP(4)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_RCC_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_RCC_USER_IRQ))
 IRQ_VEC_N_OP(5)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_EXTI0_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_EXTI0_USER_IRQ))
 IRQ_VEC_N_OP(6)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_EXTI1_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_EXTI1_USER_IRQ))
 IRQ_VEC_N_OP(7)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_EXTI2_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_EXTI2_USER_IRQ))
 IRQ_VEC_N_OP(8)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_EXTI3_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_EXTI3_USER_IRQ))
 IRQ_VEC_N_OP(9)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_EXTI4_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_EXTI4_USER_IRQ))
 IRQ_VEC_N_OP(10)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream0_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream0_USER_IRQ))
 IRQ_VEC_N_OP(11)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream1_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream1_USER_IRQ))
 IRQ_VEC_N_OP(12)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream2_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream2_USER_IRQ))
 IRQ_VEC_N_OP(13)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream3_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream3_USER_IRQ))
 IRQ_VEC_N_OP(14)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream4_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream4_USER_IRQ))
 IRQ_VEC_N_OP(15)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream5_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream5_USER_IRQ))
 IRQ_VEC_N_OP(16)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream6_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream6_USER_IRQ))
 IRQ_VEC_N_OP(17)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_ADC_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_ADC_USER_IRQ))
 IRQ_VEC_N_OP(18)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CAN1_TX_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CAN1_TX_USER_IRQ))
 IRQ_VEC_N_OP(19)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CAN1_RX_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CAN1_RX_USER_IRQ))
 IRQ_VEC_N_OP(20)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CAN1_RX1_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CAN1_RX1_USER_IRQ))
 IRQ_VEC_N_OP(21)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CAN1_SCE_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CAN1_SCE_USER_IRQ))
 IRQ_VEC_N_OP(22)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_EXTI9_5_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_EXTI9_5_USER_IRQ))
 IRQ_VEC_N_OP(23)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM1_BRK_TIM9_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM1_BRK_TIM9_USER_IRQ))
 IRQ_VEC_N_OP(24)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM1_UP_TIM10_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM1_UP_TIM10_USER_IRQ))
 IRQ_VEC_N_OP(25)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM1_TRG_COM_TIM11_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM1_TRG_COM_TIM11_USER_IRQ))
 IRQ_VEC_N_OP(26)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM1_CC_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM1_CC_USER_IRQ))
 IRQ_VEC_N_OP(27)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM2_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM2_USER_IRQ))
 IRQ_VEC_N_OP(28)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM3_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM3_USER_IRQ))
 IRQ_VEC_N_OP(29)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM4_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM4_USER_IRQ))
 IRQ_VEC_N_OP(30)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_I2C1_EV_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_I2C1_EV_USER_IRQ))
 IRQ_VEC_N_OP(31)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_I2C1_ER_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_I2C1_ER_USER_IRQ))
 IRQ_VEC_N_OP(32)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_I2C2_EV_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_I2C2_EV_USER_IRQ))
 IRQ_VEC_N_OP(33)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_I2C2_ER_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_I2C2_ER_USER_IRQ))
 IRQ_VEC_N_OP(34)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_SPI1_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_SPI1_USER_IRQ))
 IRQ_VEC_N_OP(35)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_SPI2_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_SPI2_USER_IRQ))
 IRQ_VEC_N_OP(36)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_USART1_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_USART1_USER_IRQ))
 IRQ_VEC_N_OP(37)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_USART2_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_USART2_USER_IRQ))
 IRQ_VEC_N_OP(38)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_USART3_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_USART3_USER_IRQ))
 IRQ_VEC_N_OP(39)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_EXTI15_10_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_EXTI15_10_USER_IRQ))
 IRQ_VEC_N_OP(40)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_RTC_Alarm_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_RTC_Alarm_USER_IRQ))
 IRQ_VEC_N_OP(41)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_OTG_FS_WKUP_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_OTG_FS_WKUP_USER_IRQ))
 IRQ_VEC_N_OP(42)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM8_BRK_TIM12_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM8_BRK_TIM12_USER_IRQ))
 IRQ_VEC_N_OP(43)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM8_UP_TIM13_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM8_UP_TIM13_USER_IRQ))
 IRQ_VEC_N_OP(44)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM8_TRG_COM_TIM14_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM8_TRG_COM_TIM14_USER_IRQ))
 IRQ_VEC_N_OP(45)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM8_CC_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM8_CC_USER_IRQ))
 IRQ_VEC_N_OP(46)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream7_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA1_Stream7_USER_IRQ))
 IRQ_VEC_N_OP(47)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_FSMC_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_FSMC_USER_IRQ))
 IRQ_VEC_N_OP(48)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_SDIO_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_SDIO_USER_IRQ))
 IRQ_VEC_N_OP(49)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM5_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM5_USER_IRQ))
 IRQ_VEC_N_OP(50)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_SPI3_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_SPI3_USER_IRQ))
 IRQ_VEC_N_OP(51)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_UART4_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_UART4_USER_IRQ))
 IRQ_VEC_N_OP(52)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_UART5_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_UART5_USER_IRQ))
 IRQ_VEC_N_OP(53)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM6_DAC_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM6_DAC_USER_IRQ))
 IRQ_VEC_N_OP(54)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_TIM7_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_TIM7_USER_IRQ))
 IRQ_VEC_N_OP(55)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream0_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream0_USER_IRQ))
 IRQ_VEC_N_OP(56)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream1_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream1_USER_IRQ))
 IRQ_VEC_N_OP(57)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream2_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream2_USER_IRQ))
 IRQ_VEC_N_OP(58)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream3_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream3_USER_IRQ))
 IRQ_VEC_N_OP(59)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream4_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream4_USER_IRQ))
 IRQ_VEC_N_OP(60)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_ETH_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_ETH_USER_IRQ))
 IRQ_VEC_N_OP(61)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_ETH_WKUP_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_ETH_WKUP_USER_IRQ))
 IRQ_VEC_N_OP(62)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CAN2_TX_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CAN2_TX_USER_IRQ))
 IRQ_VEC_N_OP(63)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CAN2_RX0_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CAN2_RX0_USER_IRQ))
 IRQ_VEC_N_OP(64)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CAN2_RX1_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CAN2_RX1_USER_IRQ))
 IRQ_VEC_N_OP(65)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CAN2_SCE_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CAN2_SCE_USER_IRQ))
 IRQ_VEC_N_OP(66)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_OTG_FS_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_OTG_FS_USER_IRQ))
 IRQ_VEC_N_OP(67)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream5_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream5_USER_IRQ))
 IRQ_VEC_N_OP(68)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream6_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream6_USER_IRQ))
 IRQ_VEC_N_OP(69)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream7_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DMA2_Stream7_USER_IRQ))
 IRQ_VEC_N_OP(70)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_USART6_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_USART6_USER_IRQ))
 IRQ_VEC_N_OP(71)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_I2C3_EV_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_I2C3_EV_USER_IRQ))
 IRQ_VEC_N_OP(72)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_I2C3_ER_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_I2C3_ER_USER_IRQ))
 IRQ_VEC_N_OP(73)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_OTG_HS_EP1_OUT_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_OTG_HS_EP1_OUT_USER_IRQ))
 IRQ_VEC_N_OP(74)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_OTG_HS_EP1_IN_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_OTG_HS_EP1_IN_USER_IRQ))
 IRQ_VEC_N_OP(75)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_OTG_HS_WKUP_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_OTG_HS_WKUP_USER_IRQ))
 IRQ_VEC_N_OP(76)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_OTG_HS_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_OTG_HS_USER_IRQ))
 IRQ_VEC_N_OP(77)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_DCMI_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_DCMI_USER_IRQ))
 IRQ_VEC_N_OP(78)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_CRYP_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_CRYP_USER_IRQ))
 IRQ_VEC_N_OP(79)
 #endif
 
 #if !defined(USER_INTERRUPT) || \
-	(defined(USER_INTERRUPT) && defined(CONFIG_HASH_RNG_USER_IRQ))
+    (defined(USER_INTERRUPT) && defined(CONFIG_HASH_RNG_USER_IRQ))
 IRQ_VEC_N_OP(80)
 #endif
 
-#if !defined(USER_INTERRUPT) || (\
-	defined(USER_INTERRUPT) && defined(CONFIG_FPU_USER_IRQ))
+#if !defined(USER_INTERRUPT) || \
+    (defined(USER_INTERRUPT) && defined(CONFIG_FPU_USER_IRQ))
 IRQ_VEC_N_OP(81)
 #endif
diff --git a/include/platform/stm32f429/nvic_table.h b/include/platform/stm32f429/nvic_table.h
index 37759efa..8da981e6 100644
--- a/include/platform/stm32f429/nvic_table.h
+++ b/include/platform/stm32f429/nvic_table.h
@@ -1,8 +1,7 @@
 /* NVIC platform-speific table generator */
 
-#define IRQ_HANDLER_FUNC(n) \
-        nvic_handler##n,
+#define IRQ_HANDLER_FUNC(n) nvic_handler##n,
 
-#define IRQ_VEC_N_OP    IRQ_HANDLER_FUNC
+#define IRQ_VEC_N_OP IRQ_HANDLER_FUNC
 #include "platform/stm32f429/nvic_private.h"
 #undef IRQ_VEC_N_OP
diff --git a/include/platform/stm32f429/rcc.h b/include/platform/stm32f429/rcc.h
index 2213f938..ee7cb32a 100644
--- a/include/platform/stm32f429/rcc.h
+++ b/include/platform/stm32f429/rcc.h
@@ -3,27 +3,27 @@
 
 #include <platform/stm32f429/registers.h>
 struct rcc_clocks {
-	uint32_t sysclk_freq;
-	uint32_t hclk_freq;
-	uint32_t pclk1_freq;
-	uint32_t pclk2_freq;
+    uint32_t sysclk_freq;
+    uint32_t hclk_freq;
+    uint32_t pclk1_freq;
+    uint32_t pclk2_freq;
 };
 
 /* RCC_FLAG definition */
-#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
-#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
-#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
-#define RCC_FLAG_PLLI2SRDY               ((uint8_t)0x3B)
-#define RCC_FLAG_PLLSAIRDY               ((uint8_t)0x3D)
-#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
-#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
-#define RCC_FLAG_BORRST                  ((uint8_t)0x79)
-#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
-#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
-#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
-#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
-#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
-#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
+#define RCC_FLAG_HSIRDY ((uint8_t) 0x21)
+#define RCC_FLAG_HSERDY ((uint8_t) 0x31)
+#define RCC_FLAG_PLLRDY ((uint8_t) 0x39)
+#define RCC_FLAG_PLLI2SRDY ((uint8_t) 0x3B)
+#define RCC_FLAG_PLLSAIRDY ((uint8_t) 0x3D)
+#define RCC_FLAG_LSERDY ((uint8_t) 0x41)
+#define RCC_FLAG_LSIRDY ((uint8_t) 0x61)
+#define RCC_FLAG_BORRST ((uint8_t) 0x79)
+#define RCC_FLAG_PINRST ((uint8_t) 0x7A)
+#define RCC_FLAG_PORRST ((uint8_t) 0x7B)
+#define RCC_FLAG_SFTRST ((uint8_t) 0x7C)
+#define RCC_FLAG_IWDGRST ((uint8_t) 0x7D)
+#define RCC_FLAG_WWDGRST ((uint8_t) 0x7E)
+#define RCC_FLAG_LPWRRST ((uint8_t) 0x7F)
 
 void sys_clock_init(void);
 void RCC_AHB1PeriphClockCmd(uint32_t rcc_AHB1, uint8_t enable);
@@ -37,6 +37,6 @@ void RCC_PLLSAIConfig(uint32_t pllsain, uint32_t pllsaiq, uint32_t pllsair);
 void RCC_LTDCCLKDivConfig(uint32_t div);
 void RCC_PLLSAICmd(uint32_t enable);
 uint8_t RCC_GetFlagStatus(uint8_t flag);
-void RCC_GetClocksFreq(struct rcc_clocks* clock);
+void RCC_GetClocksFreq(struct rcc_clocks *clock);
 
 #endif
diff --git a/include/platform/stm32f429/registers.h b/include/platform/stm32f429/registers.h
index 6d765700..f524a362 100644
--- a/include/platform/stm32f429/registers.h
+++ b/include/platform/stm32f429/registers.h
@@ -8,1178 +8,1994 @@
 #define STM32F4X
 
 /* Memory Map */
-#define MEMORY_BASE                     (uint32_t) (0x00000000)                                 /* Base of memory map */
-#define FLASH_BASE                      (uint32_t) (0x08000000)                                 /* Flash Memory Base Address */
-#define RAM_BASE                        (uint32_t) (0x20000000)                                 /* RAM Base Address */
-#define ETHRAM_BASE                     (uint32_t) (0x2001C000)                                 /* ETHRAM Base Address */
-#define CCMRAM_BASE                     (uint32_t) (0x10000000)                                 /* CCMRAM Base Address - Accessible only to CPU */
+#define MEMORY_BASE (uint32_t) (0x00000000) /* Base of memory map */
+#define FLASH_BASE (uint32_t) (0x08000000)  /* Flash Memory Base Address */
+#define RAM_BASE (uint32_t) (0x20000000)    /* RAM Base Address */
+#define ETHRAM_BASE (uint32_t) (0x2001C000) /* ETHRAM Base Address */
+#define CCMRAM_BASE \
+    (uint32_t) (0x10000000) /* CCMRAM Base Address - Accessible only to CPU */
 
 /* Peripheral Map */
-#define PERIPH_BASE                     (uint32_t) (0x40000000)                                 /* Peripheral base address */
-#define PRIV_PERIPH_BASE                (uint32_t) (0xED000000)                                 /* Private peripheral base address */
-#define APB1PERIPH_BASE                 (PERIPH_BASE)
-#define APB2PERIPH_BASE                 (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE                 (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE                 (PERIPH_BASE + 0x10000000)
-
-#define PERIPH_BB_BASE                  (PERIPH_BASE + 0x02000000)                                 /* Peripheral base address in bit-band region */
+#define PERIPH_BASE (uint32_t) (0x40000000) /* Peripheral base address */
+#define PRIV_PERIPH_BASE \
+    (uint32_t) (0xED000000) /* Private peripheral base address */
+#define APB1PERIPH_BASE (PERIPH_BASE)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
+
+#define PERIPH_BB_BASE                                                       \
+    (PERIPH_BASE + 0x02000000) /* Peripheral base address in bit-band region \
+                                */
 
 /* APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
 
 /* APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800)
-#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000)
-#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
+#define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
 
 /* AHB */
-#define GPIO_BASE(port)                 (AHB1PERIPH_BASE + (0x400*port))                        /* GPIO Port base address */
-#define RCC_BASE                        (AHB1PERIPH_BASE + 0x3800)                              /* Reset and Clock Control base address */
-#define FLASH_R_BASE                    (AHB1PERIPH_BASE + 0x3C00)                              /* Flash registers base address */
-#define DMA1_BASE                       (AHB1PERIPH_BASE + 0x6000)                              /* DMA1 base address */
-#define DMA2_BASE                       (AHB1PERIPH_BASE + 0x6400)                              /* DMA2 base address */
-#define DMA2D_BASE                      (AHB1PERIPH_BASE + 0xB000)                              /* DMA2D base address */
-#define USB_FS_BASE                     (AHB2PERIPH_BASE + 0x0000)                              /* USB OTG FS base address */
+#define GPIO_BASE(port) \
+    (AHB1PERIPH_BASE + (0x400 * port)) /* GPIO Port base address */
+#define RCC_BASE \
+    (AHB1PERIPH_BASE + 0x3800) /* Reset and Clock Control base address */
+#define FLASH_R_BASE \
+    (AHB1PERIPH_BASE + 0x3C00)                /* Flash registers base address */
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)  /* DMA1 base address */
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)  /* DMA2 base address */
+#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000) /* DMA2D base address */
+#define USB_FS_BASE (AHB2PERIPH_BASE + 0x0000) /* USB OTG FS base address */
 
 
 /* Timer 1 (TIM1) */
-#define TIM1_CR1                        (volatile uint32_t *) (TIM1_BASE + 0x00)                /* TIM1 control register 1 */
-#define TIM1_CR2                        (volatile uint32_t *) (TIM1_BASE + 0x04)                /* TIM1 control register 2 */
-#define TIM1_SMCR                       (volatile uint32_t *) (TIM1_BASE + 0x08)                /* TIM1 slave mode control register */
-#define TIM1_DIER                       (volatile uint32_t *) (TIM1_BASE + 0x0C)                /* TIM1 DMA/Interrupt enable register */
-#define TIM1_SR                         (volatile uint32_t *) (TIM1_BASE + 0x10)                /* TIM1 status register */
-#define TIM1_EGR                        (volatile uint32_t *) (TIM1_BASE + 0x14)                /* TIM1 event generation register */
-#define TIM1_CCMR1                      (volatile uint32_t *) (TIM1_BASE + 0x18)                /* TIM1 capture/compare mode register 1 */
-#define TIM1_CCMR2                      (volatile uint32_t *) (TIM1_BASE + 0x1C)                /* TIM1 capture/compare mode register 2 */
-#define TIM1_CCER                       (volatile uint32_t *) (TIM1_BASE + 0x20)                /* TIM1 capture/compare enable register */
-#define TIM1_CNT                        (volatile uint32_t *) (TIM1_BASE + 0x24)                /* TIM1 counter */
-#define TIM1_PSC                        (volatile uint32_t *) (TIM1_BASE + 0x28)                /* TIM1 prescaler */
-#define TIM1_ARR                        (volatile uint32_t *) (TIM1_BASE + 0x2C)                /* TIM1 auto-reload register */
-#define TIM1_CCR1                       (volatile uint32_t *) (TIM1_BASE + 0x34)                /* TIM1 capture/compare register 1 */
-#define TIM1_CCR2                       (volatile uint32_t *) (TIM1_BASE + 0x38)                /* TIM1 capture/compare register 2 */
-#define TIM1_CCR3                       (volatile uint32_t *) (TIM1_BASE + 0x3C)                /* TIM1 capture/compare register 3 */
-#define TIM1_CCR4                       (volatile uint32_t *) (TIM1_BASE + 0x40)                /* TIM1 capture/compare register 4 */
-#define TIM1_DCR                        (volatile uint32_t *) (TIM1_BASE + 0x48)                /* TIM1 DMA control register */
-#define TIM1_DMAR                       (volatile uint32_t *) (TIM1_BASE + 0x4C)                /* TIM1 DMA address for full transfer */
-#define TIM1_OR                         (volatile uint32_t *) (TIM1_BASE + 0x50)                /* TIM1 option register */
-
-#define TIM2_CR1                        (volatile uint32_t *) (TIM2_BASE + 0x00)                /* TIM2 control register 1 */
-#define TIM2_CR2                        (volatile uint32_t *) (TIM2_BASE + 0x04)                /* TIM2 control register 2 */
-#define TIM2_SMCR                       (volatile uint32_t *) (TIM2_BASE + 0x08)                /* TIM2 slave mode control register */
-#define TIM2_DIER                       (volatile uint32_t *) (TIM2_BASE + 0x0C)                /* TIM2 DMA/Interrupt enable register */
-#define TIM2_SR                         (volatile uint32_t *) (TIM2_BASE + 0x10)                /* TIM2 status register */
-#define TIM2_EGR                        (volatile uint32_t *) (TIM2_BASE + 0x14)                /* TIM2 event generation register */
-#define TIM2_CCMR1                      (volatile uint32_t *) (TIM2_BASE + 0x18)                /* TIM2 capture/compare mode register 1 */
-#define TIM2_CCMR2                      (volatile uint32_t *) (TIM2_BASE + 0x1C)                /* TIM2 capture/compare mode register 2 */
-#define TIM2_CCER                       (volatile uint32_t *) (TIM2_BASE + 0x20)                /* TIM2 capture/compare enable register */
-#define TIM2_CNT                        (volatile uint32_t *) (TIM2_BASE + 0x24)                /* TIM2 counter */
-#define TIM2_PSC                        (volatile uint32_t *) (TIM2_BASE + 0x28)                /* TIM2 prescaler */
-#define TIM2_ARR                        (volatile uint32_t *) (TIM2_BASE + 0x2C)                /* TIM2 auto-reload register */
-#define TIM2_CCR1                       (volatile uint32_t *) (TIM2_BASE + 0x34)                /* TIM2 capture/compare register 1 */
-#define TIM2_CCR2                       (volatile uint32_t *) (TIM2_BASE + 0x38)                /* TIM2 capture/compare register 2 */
-#define TIM2_CCR3                       (volatile uint32_t *) (TIM2_BASE + 0x3C)                /* TIM2 capture/compare register 3 */
-#define TIM2_CCR4                       (volatile uint32_t *) (TIM2_BASE + 0x40)                /* TIM2 capture/compare register 4 */
-#define TIM2_DCR                        (volatile uint32_t *) (TIM2_BASE + 0x48)                /* TIM2 DMA control register */
-#define TIM2_DMAR                       (volatile uint32_t *) (TIM2_BASE + 0x4C)                /* TIM2 DMA address for full transfer */
-#define TIM2_OR                         (volatile uint32_t *) (TIM2_BASE + 0x50)                /* TIM2 option register */
+#define TIM1_CR1 \
+    (volatile uint32_t *) (TIM1_BASE + 0x00) /* TIM1 control register 1 */
+#define TIM1_CR2 \
+    (volatile uint32_t *) (TIM1_BASE + 0x04) /* TIM1 control register 2 */
+#define TIM1_SMCR                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x08) /* TIM1 slave mode control register */
+#define TIM1_DIER                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x0C) /* TIM1 DMA/Interrupt enable register */
+#define TIM1_SR \
+    (volatile uint32_t *) (TIM1_BASE + 0x10) /* TIM1 status register */
+#define TIM1_EGR                       \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x14) /* TIM1 event generation register */
+#define TIM1_CCMR1                     \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x18) /* TIM1 capture/compare mode register 1 */
+#define TIM1_CCMR2                     \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x1C) /* TIM1 capture/compare mode register 2 */
+#define TIM1_CCER                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x20) /* TIM1 capture/compare enable register */
+#define TIM1_CNT (volatile uint32_t *) (TIM1_BASE + 0x24) /* TIM1 counter */
+#define TIM1_PSC (volatile uint32_t *) (TIM1_BASE + 0x28) /* TIM1 prescaler */
+#define TIM1_ARR \
+    (volatile uint32_t *) (TIM1_BASE + 0x2C) /* TIM1 auto-reload register */
+#define TIM1_CCR1                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x34) /* TIM1 capture/compare register 1 */
+#define TIM1_CCR2                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x38) /* TIM1 capture/compare register 2 */
+#define TIM1_CCR3                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x3C) /* TIM1 capture/compare register 3 */
+#define TIM1_CCR4                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x40) /* TIM1 capture/compare register 4 */
+#define TIM1_DCR \
+    (volatile uint32_t *) (TIM1_BASE + 0x48) /* TIM1 DMA control register */
+#define TIM1_DMAR                      \
+    (volatile uint32_t *) (TIM1_BASE + \
+                           0x4C) /* TIM1 DMA address for full transfer */
+#define TIM1_OR \
+    (volatile uint32_t *) (TIM1_BASE + 0x50) /* TIM1 option register */
+
+#define TIM2_CR1 \
+    (volatile uint32_t *) (TIM2_BASE + 0x00) /* TIM2 control register 1 */
+#define TIM2_CR2 \
+    (volatile uint32_t *) (TIM2_BASE + 0x04) /* TIM2 control register 2 */
+#define TIM2_SMCR                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x08) /* TIM2 slave mode control register */
+#define TIM2_DIER                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x0C) /* TIM2 DMA/Interrupt enable register */
+#define TIM2_SR \
+    (volatile uint32_t *) (TIM2_BASE + 0x10) /* TIM2 status register */
+#define TIM2_EGR                       \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x14) /* TIM2 event generation register */
+#define TIM2_CCMR1                     \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x18) /* TIM2 capture/compare mode register 1 */
+#define TIM2_CCMR2                     \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x1C) /* TIM2 capture/compare mode register 2 */
+#define TIM2_CCER                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x20) /* TIM2 capture/compare enable register */
+#define TIM2_CNT (volatile uint32_t *) (TIM2_BASE + 0x24) /* TIM2 counter */
+#define TIM2_PSC (volatile uint32_t *) (TIM2_BASE + 0x28) /* TIM2 prescaler */
+#define TIM2_ARR \
+    (volatile uint32_t *) (TIM2_BASE + 0x2C) /* TIM2 auto-reload register */
+#define TIM2_CCR1                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x34) /* TIM2 capture/compare register 1 */
+#define TIM2_CCR2                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x38) /* TIM2 capture/compare register 2 */
+#define TIM2_CCR3                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x3C) /* TIM2 capture/compare register 3 */
+#define TIM2_CCR4                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x40) /* TIM2 capture/compare register 4 */
+#define TIM2_DCR \
+    (volatile uint32_t *) (TIM2_BASE + 0x48) /* TIM2 DMA control register */
+#define TIM2_DMAR                      \
+    (volatile uint32_t *) (TIM2_BASE + \
+                           0x4C) /* TIM2 DMA address for full transfer */
+#define TIM2_OR \
+    (volatile uint32_t *) (TIM2_BASE + 0x50) /* TIM2 option register */
 /* Power Control (PWR) */
-#define PWR_CR                          (volatile uint32_t *) (PWR_BASE + 0x00)                 /* Power Control Register */
-#define PWR_CSR                         (volatile uint32_t *) (PWR_BASE + 0x04)                 /* Power Control/Status Register */
+#define PWR_CR \
+    (volatile uint32_t *) (PWR_BASE + 0x00) /* Power Control Register */
+#define PWR_CSR                                                              \
+    (volatile uint32_t *) (PWR_BASE + 0x04) /* Power Control/Status Register \
+                                             */
 
 /* SPI */
-#define SPI_BASE(port)                  (port)                              /* Temporary SPI base */
-#define SPI_CR1(port)                   (volatile uint32_t *) (SPI_BASE(port) + 0x00)           /* SPI control register 1 */
-#define SPI_CR2(port)                   (volatile uint32_t *) (SPI_BASE(port) + 0x04)           /* SPI control register 2 */
-#define SPI_SR(port)                    (volatile uint32_t *) (SPI_BASE(port) + 0x08)           /* SPI status register */
-#define SPI_DR(port)                    (volatile uint32_t *) (SPI_BASE(port) + 0x0c)           /* SPI data register */
-#define SPI_CRCPR(port)                 (volatile uint32_t *) (SPI_BASE(port) + 0x10)           /* SPI CRC polynomial register */
-#define SPI_RXCRCR(port)                (volatile uint32_t *) (SPI_BASE(port) + 0x14)           /* SPI RX CRC register */
-#define SPI_TXCRCR(port)                (volatile uint32_t *) (SPI_BASE(port) + 0x18)           /* SPI TX CRC register */
-#define SPI_I2SCFGR(port)               (volatile uint32_t *) (SPI_BASE(port) + 0x1c)           /* SPI I2C configuration register */
-#define SPI_I2SPR(port)                 (volatile uint32_t *) (SPI_BASE(port) + 0x20)           /* SPI I2C prescaler register */
+#define SPI_BASE(port) (port) /* Temporary SPI base */
+#define SPI_CR1(port) \
+    (volatile uint32_t *) (SPI_BASE(port) + 0x00) /* SPI control register 1 */
+#define SPI_CR2(port) \
+    (volatile uint32_t *) (SPI_BASE(port) + 0x04) /* SPI control register 2 */
+#define SPI_SR(port) \
+    (volatile uint32_t *) (SPI_BASE(port) + 0x08) /* SPI status register */
+#define SPI_DR(port) \
+    (volatile uint32_t *) (SPI_BASE(port) + 0x0c) /* SPI data register */
+#define SPI_CRCPR(port)                     \
+    (volatile uint32_t *) (SPI_BASE(port) + \
+                           0x10) /* SPI CRC polynomial register */
+#define SPI_RXCRCR(port) \
+    (volatile uint32_t *) (SPI_BASE(port) + 0x14) /* SPI RX CRC register */
+#define SPI_TXCRCR(port) \
+    (volatile uint32_t *) (SPI_BASE(port) + 0x18) /* SPI TX CRC register */
+#define SPI_I2SCFGR(port)                   \
+    (volatile uint32_t *) (SPI_BASE(port) + \
+                           0x1c) /* SPI I2C configuration register */
+#define SPI_I2SPR(port)                     \
+    (volatile uint32_t *) (SPI_BASE(port) + \
+                           0x20) /* SPI I2C prescaler register */
 
 /* I2C */
-#define I2C_BASE(port)                  (port)                                                  /* I2C Base */
-#define I2C_CR1(port)                   (volatile uint32_t *) (I2C_BASE(port) + 0x00)           /* I2C control register 1 */
-#define I2C_CR2(port)                   (volatile uint32_t *) (I2C_BASE(port) + 0x04)           /* I2C control register 2 */
-#define I2C_OAR1(port)                  (volatile uint32_t *) (I2C_BASE(port) + 0x08)           /* I2C own address register 1 */
-#define I2C_OAR2(port)                  (volatile uint32_t *) (I2C_BASE(port) + 0x0C)           /* I2C own address register 2 */
-#define I2C_DR(port)                    (volatile uint32_t *) (I2C_BASE(port) + 0x10)           /* I2C data register */
-#define I2C_SR1(port)                   (volatile uint32_t *) (I2C_BASE(port) + 0x14)           /* I2C status register 1 */
-#define I2C_SR2(port)                   (volatile uint32_t *) (I2C_BASE(port) + 0x18)           /* I2C status register 2 */
-#define I2C_CCR(port)                   (volatile uint32_t *) (I2C_BASE(port) + 0x1C)           /* I2C clock control register */
-#define I2C_TRISE(port)                 (volatile uint32_t *) (I2C_BASE(port) + 0x20)           /* I2C TRISE register */
+#define I2C_BASE(port) (port) /* I2C Base */
+#define I2C_CR1(port) \
+    (volatile uint32_t *) (I2C_BASE(port) + 0x00) /* I2C control register 1 */
+#define I2C_CR2(port) \
+    (volatile uint32_t *) (I2C_BASE(port) + 0x04) /* I2C control register 2 */
+#define I2C_OAR1(port)                      \
+    (volatile uint32_t *) (I2C_BASE(port) + \
+                           0x08) /* I2C own address register 1 */
+#define I2C_OAR2(port)                      \
+    (volatile uint32_t *) (I2C_BASE(port) + \
+                           0x0C) /* I2C own address register 2 */
+#define I2C_DR(port) \
+    (volatile uint32_t *) (I2C_BASE(port) + 0x10) /* I2C data register */
+#define I2C_SR1(port) \
+    (volatile uint32_t *) (I2C_BASE(port) + 0x14) /* I2C status register 1 */
+#define I2C_SR2(port) \
+    (volatile uint32_t *) (I2C_BASE(port) + 0x18) /* I2C status register 2 */
+#define I2C_CCR(port)                       \
+    (volatile uint32_t *) (I2C_BASE(port) + \
+                           0x1C) /* I2C clock control register */
+#define I2C_TRISE(port) \
+    (volatile uint32_t *) (I2C_BASE(port) + 0x20) /* I2C TRISE register */
 
 /* USART 1 */
-#define USART1_SR                       (volatile uint32_t *) (USART1_BASE + 0x00)              /* USART1 status register */
-#define USART1_DR                       (volatile uint32_t *) (USART1_BASE + 0x04)              /* USART1 data register */
-#define USART1_BRR                      (volatile uint32_t *) (USART1_BASE + 0x08)              /* USART1 baud rate register */
-#define USART1_CR1                      (volatile uint32_t *) (USART1_BASE + 0x0C)              /* USART1 control register 1 */
-#define USART1_CR2                      (volatile uint32_t *) (USART1_BASE + 0x10)              /* USART1 control register 2 */
-#define USART1_CR3                      (volatile uint32_t *) (USART1_BASE + 0x14)              /* USART1 control register 3 */
-#define USART1_GTPR                     (volatile uint32_t *) (USART1_BASE + 0x18)              /* USART1 gaurd time and prescale register */
+#define USART1_SR \
+    (volatile uint32_t *) (USART1_BASE + 0x00) /* USART1 status register */
+#define USART1_DR \
+    (volatile uint32_t *) (USART1_BASE + 0x04) /* USART1 data register */
+#define USART1_BRR \
+    (volatile uint32_t *) (USART1_BASE + 0x08) /* USART1 baud rate register */
+#define USART1_CR1 \
+    (volatile uint32_t *) (USART1_BASE + 0x0C) /* USART1 control register 1 */
+#define USART1_CR2 \
+    (volatile uint32_t *) (USART1_BASE + 0x10) /* USART1 control register 2 */
+#define USART1_CR3 \
+    (volatile uint32_t *) (USART1_BASE + 0x14) /* USART1 control register 3 */
+#define USART1_GTPR                      \
+    (volatile uint32_t *) (USART1_BASE + \
+                           0x18) /* USART1 gaurd time and prescale register */
 
 /* GPIO Port (GPIO) */
-#define GPIO_MODER(port)                (volatile uint32_t *) (GPIO_BASE(port) + 0x00)          /* Port mode register */
-#define GPIO_OTYPER(port)               (volatile uint32_t *) (GPIO_BASE(port) + 0x04)          /* Port output type register */
-#define GPIO_OSPEEDR(port)              (volatile uint32_t *) (GPIO_BASE(port) + 0x08)          /* Port output speed register */
-#define GPIO_PUPDR(port)                (volatile uint32_t *) (GPIO_BASE(port) + 0x0C)          /* Port pull up/down register */
-#define GPIO_IDR(port)                  (volatile uint32_t *) (GPIO_BASE(port) + 0x10)          /* Port input data register */
-#define GPIO_ODR(port)                  (volatile uint32_t *) (GPIO_BASE(port) + 0x14)          /* Port output data register */
-#define GPIO_BSRR(port)                 (volatile uint32_t *) (GPIO_BASE(port) + 0x18)          /* Port bit set/reset register */
-#define GPIO_LCKR(port)                 (volatile uint32_t *) (GPIO_BASE(port) + 0x1C)          /* Port configuration lock register */
-#define GPIO_AFRL(port)                 (volatile uint32_t *) (GPIO_BASE(port) + 0x20)          /* Port alternate function low register */
-#define GPIO_AFRH(port)                 (volatile uint32_t *) (GPIO_BASE(port) + 0x24)          /* Port alternate function high register */
+#define GPIO_MODER(port) \
+    (volatile uint32_t *) (GPIO_BASE(port) + 0x00) /* Port mode register */
+#define GPIO_OTYPER(port)                    \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x04) /* Port output type register */
+#define GPIO_OSPEEDR(port)                   \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x08) /* Port output speed register */
+#define GPIO_PUPDR(port)                     \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x0C) /* Port pull up/down register */
+#define GPIO_IDR(port)                       \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x10) /* Port input data register */
+#define GPIO_ODR(port)                       \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x14) /* Port output data register */
+#define GPIO_BSRR(port)                      \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x18) /* Port bit set/reset register */
+#define GPIO_LCKR(port)                      \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x1C) /* Port configuration lock register */
+#define GPIO_AFRL(port)                      \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x20) /* Port alternate function low register */
+#define GPIO_AFRH(port)                      \
+    (volatile uint32_t *) (GPIO_BASE(port) + \
+                           0x24) /* Port alternate function high register */
 
 /* Reset and Clock Control (RCC) */
-#define RCC_CR                          (volatile uint32_t *) (RCC_BASE + 0x00)                 /* Clock Control Register */
-#define RCC_PLLCFGR                     (volatile uint32_t *) (RCC_BASE + 0x04)                 /* PLL Configuration Register */
-#define RCC_CFGR                        (volatile uint32_t *) (RCC_BASE + 0x08)                 /* Clock Configuration Register */
-#define RCC_CIR                         (volatile uint32_t *) (RCC_BASE + 0x0C)                 /* Clock Interrupt Register */
-#define RCC_AHB1RSTR                    (volatile uint32_t *) (RCC_BASE + 0x10)                 /* AHB1 reset Register */
-#define RCC_APB1RSTR                    (volatile uint32_t *) (RCC_BASE + 0x20)                 /* APB1 reset Register */
-#define RCC_APB2RSTR                    (volatile uint32_t *) (RCC_BASE + 0x24)                 /* APB2 reset Register */
-#define RCC_AHB1ENR                     (volatile uint32_t *) (RCC_BASE + 0x30)                 /* AHB1 Enable Register */
-#define RCC_AHB2ENR                     (volatile uint32_t *) (RCC_BASE + 0x34)                 /* AHB2 Enable Register */
-#define RCC_AHB3ENR                     (volatile uint32_t *) (RCC_BASE + 0x38)                 /* AHB3 Enable Register */
-#define RCC_APB1ENR                     (volatile uint32_t *) (RCC_BASE + 0x40)                 /* APB1 Peripheral Clock Enable Register */
-#define RCC_APB2ENR                     (volatile uint32_t *) (RCC_BASE + 0x44)                 /* APB2 Peripheral Clock Enable Register */
-#define RCC_BDCR                        (volatile uint32_t *) (RCC_BASE + 0x70)                 /* RCC Backup Domain Control Register */
-#define RCC_CSR                         (volatile uint32_t *) (RCC_BASE + 0x74)                 /* RCC Clock Control & Status Register */
-#define RCC_PLLSAICFGR                  (volatile uint32_t *) (RCC_BASE + 0x88)                 /* RCC PLLSAI Configuration register */
-#define RCC_DCKCFGR                     (volatile uint32_t *) (RCC_BASE + 0x8C)                 /* RCC Dedicated Clocks Configuration register */
+#define RCC_CR \
+    (volatile uint32_t *) (RCC_BASE + 0x00) /* Clock Control Register */
+#define RCC_PLLCFGR \
+    (volatile uint32_t *) (RCC_BASE + 0x04) /* PLL Configuration Register */
+#define RCC_CFGR \
+    (volatile uint32_t *) (RCC_BASE + 0x08) /* Clock Configuration Register */
+#define RCC_CIR \
+    (volatile uint32_t *) (RCC_BASE + 0x0C) /* Clock Interrupt Register */
+#define RCC_AHB1RSTR \
+    (volatile uint32_t *) (RCC_BASE + 0x10) /* AHB1 reset Register */
+#define RCC_APB1RSTR \
+    (volatile uint32_t *) (RCC_BASE + 0x20) /* APB1 reset Register */
+#define RCC_APB2RSTR \
+    (volatile uint32_t *) (RCC_BASE + 0x24) /* APB2 reset Register */
+#define RCC_AHB1ENR \
+    (volatile uint32_t *) (RCC_BASE + 0x30) /* AHB1 Enable Register */
+#define RCC_AHB2ENR \
+    (volatile uint32_t *) (RCC_BASE + 0x34) /* AHB2 Enable Register */
+#define RCC_AHB3ENR \
+    (volatile uint32_t *) (RCC_BASE + 0x38) /* AHB3 Enable Register */
+#define RCC_APB1ENR                   \
+    (volatile uint32_t *) (RCC_BASE + \
+                           0x40) /* APB1 Peripheral Clock Enable Register */
+#define RCC_APB2ENR                   \
+    (volatile uint32_t *) (RCC_BASE + \
+                           0x44) /* APB2 Peripheral Clock Enable Register */
+#define RCC_BDCR                      \
+    (volatile uint32_t *) (RCC_BASE + \
+                           0x70) /* RCC Backup Domain Control Register */
+#define RCC_CSR                       \
+    (volatile uint32_t *) (RCC_BASE + \
+                           0x74) /* RCC Clock Control & Status Register */
+#define RCC_PLLSAICFGR                \
+    (volatile uint32_t *) (RCC_BASE + \
+                           0x88) /* RCC PLLSAI Configuration register */
+#define RCC_DCKCFGR                                                 \
+    (volatile uint32_t *) (RCC_BASE + 0x8C) /* RCC Dedicated Clocks \
+                                               Configuration register */
 
 /* SYSCFG */
-#define SYSCFG_MEMRMP					(volatile uint32_t *)(SYSCFG_BASE + 0x0)				/* Memory remap register */
-#define SYSCFG_PMC						(volatile uint32_t *)(SYSCFG_BASE + 0x4)				/* Peripheral mode config register */
-#define SYSCFG_EXTICR1					(volatile uint32_t *)(SYSCFG_BASE + 0x8)				/* External INT config register1 */
-#define SYSCFG_EXTICR2					(volatile uint32_t *)(SYSCFG_BASE + 0xc)				/* External INT config register2 */
-#define SYSCFG_EXTICR3					(volatile uint32_t *)(SYSCFG_BASE + 0x10)				/* External INT config register3 */
-#define SYSCFG_EXTICR4					(volatile uint32_t *)(SYSCFG_BASE + 0x14)				/* External INT config register4 */
-#define SYSCFG_CMPCR					(volatile uint32_t *)(SYSCFG_BASE + 0x20)				/* Compensation cell control register*/
+#define SYSCFG_MEMRMP \
+    (volatile uint32_t *) (SYSCFG_BASE + 0x0) /* Memory remap register */
+#define SYSCFG_PMC                       \
+    (volatile uint32_t *) (SYSCFG_BASE + \
+                           0x4) /* Peripheral mode config register */
+#define SYSCFG_EXTICR1                   \
+    (volatile uint32_t *) (SYSCFG_BASE + \
+                           0x8) /* External INT config register1 */
+#define SYSCFG_EXTICR2                   \
+    (volatile uint32_t *) (SYSCFG_BASE + \
+                           0xc) /* External INT config register2 */
+#define SYSCFG_EXTICR3                   \
+    (volatile uint32_t *) (SYSCFG_BASE + \
+                           0x10) /* External INT config register3 */
+#define SYSCFG_EXTICR4                   \
+    (volatile uint32_t *) (SYSCFG_BASE + \
+                           0x14) /* External INT config register4 */
+#define SYSCFG_CMPCR                     \
+    (volatile uint32_t *) (SYSCFG_BASE + \
+                           0x20) /* Compensation cell control register*/
 
 
 
 /* APB1 RCC ENR */
-#define RCC_TIM2_APBENR					RCC_APB1ENR
-#define RCC_TIM3_APBENR					RCC_APB1ENR
-#define RCC_TIM4_APBENR					RCC_APB1ENR
-#define RCC_TIM5_APBENR					RCC_APB1ENR
-#define RCC_TIM6_APBENR					RCC_APB1ENR
-#define RCC_TIM7_APBENR					RCC_APB1ENR
-#define RCC_TIM12_APBENR				RCC_APB1ENR
-#define RCC_TIM13_APBENR				RCC_APB1ENR
-#define RCC_TIM14_APBENR				RCC_APB1ENR
-#define RCC_WWDG_APBENR					RCC_APB1ENR
-#define RCC_SPI2_APBENR					RCC_APB1ENR
-#define RCC_SPI3_APBENR					RCC_APB1ENR
-#define RCC_USART2_APBENR				RCC_APB1ENR
-#define RCC_USART3_APBENR				RCC_APB1ENR
-#define RCC_UART4_APBENR				RCC_APB1ENR
-#define RCC_UART5_APBENR				RCC_APB1ENR
-#define RCC_I2C1_APBENR					RCC_APB1ENR
-#define RCC_I2C2_APBENR					RCC_APB1ENR
-#define RCC_I2C3_APBENR					RCC_APB1ENR
-#define RCC_CAN1_APBENR					RCC_APB1ENR
-#define RCC_CAN2_APBENR					RCC_APB1ENR
-#define RCC_PWR_APBENR					RCC_APB1ENR
-#define RCC_DAC_APBENR					RCC_APB1ENR
+#define RCC_TIM2_APBENR RCC_APB1ENR
+#define RCC_TIM3_APBENR RCC_APB1ENR
+#define RCC_TIM4_APBENR RCC_APB1ENR
+#define RCC_TIM5_APBENR RCC_APB1ENR
+#define RCC_TIM6_APBENR RCC_APB1ENR
+#define RCC_TIM7_APBENR RCC_APB1ENR
+#define RCC_TIM12_APBENR RCC_APB1ENR
+#define RCC_TIM13_APBENR RCC_APB1ENR
+#define RCC_TIM14_APBENR RCC_APB1ENR
+#define RCC_WWDG_APBENR RCC_APB1ENR
+#define RCC_SPI2_APBENR RCC_APB1ENR
+#define RCC_SPI3_APBENR RCC_APB1ENR
+#define RCC_USART2_APBENR RCC_APB1ENR
+#define RCC_USART3_APBENR RCC_APB1ENR
+#define RCC_UART4_APBENR RCC_APB1ENR
+#define RCC_UART5_APBENR RCC_APB1ENR
+#define RCC_I2C1_APBENR RCC_APB1ENR
+#define RCC_I2C2_APBENR RCC_APB1ENR
+#define RCC_I2C3_APBENR RCC_APB1ENR
+#define RCC_CAN1_APBENR RCC_APB1ENR
+#define RCC_CAN2_APBENR RCC_APB1ENR
+#define RCC_PWR_APBENR RCC_APB1ENR
+#define RCC_DAC_APBENR RCC_APB1ENR
 
 /* APB2 RCC ENR */
-#define RCC_TIM1_APBENR					RCC_APB2ENR
-#define RCC_TIM8_APBENR					RCC_APB2ENR
-#define RCC_USART1_APBENR				RCC_APB2ENR
-#define RCC_USART6_APBENR				RCC_APB2ENR
-#define RCC_ADC1_APBENR					RCC_APB2ENR
-#define RCC_ADC2_APBENR					RCC_APB2ENR
-#define RCC_ADC3_APBENR					RCC_APB2ENR
-#define RCC_SDIO_APBENR					RCC_APB2ENR
-#define RCC_SPI1_APBENR					RCC_APB2ENR
-#define RCC_SYSCFG_APBENR				RCC_APB2ENR
-#define RCC_TIM9_APBENR					RCC_APB2ENR
-#define RCC_TIM10_APBENR				RCC_APB2ENR
-#define RCC_TIM11_APBENR				RCC_APB2ENR
+#define RCC_TIM1_APBENR RCC_APB2ENR
+#define RCC_TIM8_APBENR RCC_APB2ENR
+#define RCC_USART1_APBENR RCC_APB2ENR
+#define RCC_USART6_APBENR RCC_APB2ENR
+#define RCC_ADC1_APBENR RCC_APB2ENR
+#define RCC_ADC2_APBENR RCC_APB2ENR
+#define RCC_ADC3_APBENR RCC_APB2ENR
+#define RCC_SDIO_APBENR RCC_APB2ENR
+#define RCC_SPI1_APBENR RCC_APB2ENR
+#define RCC_SYSCFG_APBENR RCC_APB2ENR
+#define RCC_TIM9_APBENR RCC_APB2ENR
+#define RCC_TIM10_APBENR RCC_APB2ENR
+#define RCC_TIM11_APBENR RCC_APB2ENR
 
 /* Flash Registers (FLASH) */
-#define FLASH_ACR                       (volatile uint32_t *) (FLASH_R_BASE + 0x00)             /* Flash Access Control Register */
+#define FLASH_ACR                         \
+    (volatile uint32_t *) (FLASH_R_BASE + \
+                           0x00) /* Flash Access Control Register */
 
 /* Direct Memory Access 1 (DMA) */
-#define DMA1_LISR                       (volatile uint32_t *) (DMA1_BASE + 0x00)                /* DMA1 low interrupt status register */
-#define DMA1_HISR                       (volatile uint32_t *) (DMA1_BASE + 0x04)                /* DMA1 high interrupt status register */
-#define DMA1_LIFCR                      (volatile uint32_t *) (DMA1_BASE + 0x08)                /* DMA1 low interrupt flag clear register */
-#define DMA1_HIFCR                      (volatile uint32_t *) (DMA1_BASE + 0x0C)                /* DMA1 high interrupt flag clear register */
+#define DMA1_LISR                      \
+    (volatile uint32_t *) (DMA1_BASE + \
+                           0x00) /* DMA1 low interrupt status register */
+#define DMA1_HISR                      \
+    (volatile uint32_t *) (DMA1_BASE + \
+                           0x04) /* DMA1 high interrupt status register */
+#define DMA1_LIFCR                     \
+    (volatile uint32_t *) (DMA1_BASE + \
+                           0x08) /* DMA1 low interrupt flag clear register */
+#define DMA1_HIFCR                     \
+    (volatile uint32_t *) (DMA1_BASE + \
+                           0x0C) /* DMA1 high interrupt flag clear register */
 /* Stream n */
-#define DMA1_CR_S(n)                    (volatile uint32_t *) (DMA1_BASE + 0x10 + (0x18*n))     /* DMA1 stream n configuration register */
-#define DMA1_NDTR_S(n)                  (volatile uint32_t *) (DMA1_BASE + 0x14 + (0x18*n))     /* DMA1 stream n number of data register */
-#define DMA1_PAR_S(n)                   (volatile uint32_t *) (DMA1_BASE + 0x18 + (0x18*n))     /* DMA1 stream n peripheral address register */
-#define DMA1_M0AR_S(n)                  (volatile uint32_t *) (DMA1_BASE + 0x1C + (0x18*n))     /* DMA1 stream n memory 0 address register */
-#define DMA1_M1AR_S(n)                  (volatile uint32_t *) (DMA1_BASE + 0x20 + (0x18*n))     /* DMA1 stream n memory 1 address register */
-#define DMA1_FCR_S(n)                   (volatile uint32_t *) (DMA1_BASE + 0x24 + (0x18*n))     /* DMA1 stream n FIFO control register */
+#define DMA1_CR_S(n)                          \
+    (volatile uint32_t *) (DMA1_BASE + 0x10 + \
+                           (0x18 *            \
+                            n)) /* DMA1 stream n configuration register */
+#define DMA1_NDTR_S(n)                        \
+    (volatile uint32_t *) (DMA1_BASE + 0x14 + \
+                           (0x18 *            \
+                            n)) /* DMA1 stream n number of data register */
+#define DMA1_PAR_S(n)           \
+    (volatile uint32_t          \
+         *) (DMA1_BASE + 0x18 + \
+             (0x18 * n)) /* DMA1 stream n peripheral address register */
+#define DMA1_M0AR_S(n)                        \
+    (volatile uint32_t *) (DMA1_BASE + 0x1C + \
+                           (0x18 *            \
+                            n)) /* DMA1 stream n memory 0 address register */
+#define DMA1_M1AR_S(n)                        \
+    (volatile uint32_t *) (DMA1_BASE + 0x20 + \
+                           (0x18 *            \
+                            n)) /* DMA1 stream n memory 1 address register */
+#define DMA1_FCR_S(n)                         \
+    (volatile uint32_t *) (DMA1_BASE + 0x24 + \
+                           (0x18 *            \
+                            n)) /* DMA1 stream n FIFO control register */
 
 /* Direct Memory Access 2 (DMA) */
-#define DMA2_LISR                       (volatile uint32_t *) (DMA2_BASE + 0x00)                /* DMA2 low interrupt status register */
-#define DMA2_HISR                       (volatile uint32_t *) (DMA2_BASE + 0x04)                /* DMA2 high interrupt status register */
-#define DMA2_LIFCR                      (volatile uint32_t *) (DMA2_BASE + 0x08)                /* DMA2 low interrupt flag clear register */
-#define DMA2_HIFCR                      (volatile uint32_t *) (DMA2_BASE + 0x0C)                /* DMA2 high interrupt flag clear register */
+#define DMA2_LISR                      \
+    (volatile uint32_t *) (DMA2_BASE + \
+                           0x00) /* DMA2 low interrupt status register */
+#define DMA2_HISR                      \
+    (volatile uint32_t *) (DMA2_BASE + \
+                           0x04) /* DMA2 high interrupt status register */
+#define DMA2_LIFCR                     \
+    (volatile uint32_t *) (DMA2_BASE + \
+                           0x08) /* DMA2 low interrupt flag clear register */
+#define DMA2_HIFCR                     \
+    (volatile uint32_t *) (DMA2_BASE + \
+                           0x0C) /* DMA2 high interrupt flag clear register */
 /* Stream n */
-#define DMA2_CR_S(n)                    (volatile uint32_t *) (DMA2_BASE + 0x10 + (0x18*n))     /* DMA2 stream n configuration register */
-#define DMA2_NDTR_S(n)                  (volatile uint32_t *) (DMA2_BASE + 0x14 + (0x18*n))     /* DMA2 stream n number of data register */
-#define DMA2_PAR_S(n)                   (volatile uint32_t *) (DMA2_BASE + 0x18 + (0x18*n))     /* DMA2 stream n peripheral address register */
-#define DMA2_M0AR_S(n)                  (volatile uint32_t *) (DMA2_BASE + 0x1C + (0x18*n))     /* DMA2 stream n memory 0 address register */
-#define DMA2_M1AR_S(n)                  (volatile uint32_t *) (DMA2_BASE + 0x20 + (0x18*n))     /* DMA2 stream n memory 1 address register */
-#define DMA2_FCR_S(n)                   (volatile uint32_t *) (DMA2_BASE + 0x24 + (0x18*n))     /* DMA2 stream n FIFO control register */
+#define DMA2_CR_S(n)                          \
+    (volatile uint32_t *) (DMA2_BASE + 0x10 + \
+                           (0x18 *            \
+                            n)) /* DMA2 stream n configuration register */
+#define DMA2_NDTR_S(n)                        \
+    (volatile uint32_t *) (DMA2_BASE + 0x14 + \
+                           (0x18 *            \
+                            n)) /* DMA2 stream n number of data register */
+#define DMA2_PAR_S(n)           \
+    (volatile uint32_t          \
+         *) (DMA2_BASE + 0x18 + \
+             (0x18 * n)) /* DMA2 stream n peripheral address register */
+#define DMA2_M0AR_S(n)                        \
+    (volatile uint32_t *) (DMA2_BASE + 0x1C + \
+                           (0x18 *            \
+                            n)) /* DMA2 stream n memory 0 address register */
+#define DMA2_M1AR_S(n)                        \
+    (volatile uint32_t *) (DMA2_BASE + 0x20 + \
+                           (0x18 *            \
+                            n)) /* DMA2 stream n memory 1 address register */
+#define DMA2_FCR_S(n)                         \
+    (volatile uint32_t *) (DMA2_BASE + 0x24 + \
+                           (0x18 *            \
+                            n)) /* DMA2 stream n FIFO control register */
 
 /* DMA2D Registers */
-#define DMA2D_CR                        (volatile uint32_t *) (DMA2D_BASE + 0x00)               /* DMA2D Control Register */
-#define DMA2D_ISR                       (volatile uint32_t *) (DMA2D_BASE + 0x04)               /* DMA2D Interrupt Status Register */
-#define DMA2D_IFCR                      (volatile uint32_t *) (DMA2D_BASE + 0x08)               /* DMA2D Interrupt Flag Clear Register */
-#define DMA2D_FGMAR                     (volatile uint32_t *) (DMA2D_BASE + 0x0C)               /* DMA2D Foreground Memory Address Register */
-#define DMA2D_FGOR                      (volatile uint32_t *) (DMA2D_BASE + 0x10)               /* DMA2D Foreground Offset Register */
-#define DMA2D_BGMAR                     (volatile uint32_t *) (DMA2D_BASE + 0x14)               /* DMA2D Background Memory Address Register */
-#define DMA2D_BGOR                      (volatile uint32_t *) (DMA2D_BASE + 0x18)               /* DMA2D Background Offset Register */
-#define DMA2D_FGPFCCR                   (volatile uint32_t *) (DMA2D_BASE + 0x1C)               /* DMA2D Foreground PFC Control Register */
-#define DMA2D_FGCOLR                    (volatile uint32_t *) (DMA2D_BASE + 0x20)               /* DMA2D Foreground Color Control Register */
-#define DMA2D_BGPFCCR                   (volatile uint32_t *) (DMA2D_BASE + 0x24)               /* DMA2D Background PFC Control Register */
-#define DMA2D_BGCOLR                    (volatile uint32_t *) (DMA2D_BASE + 0x28)               /* DMA2D Background Color Control Register */
-#define DMA2D_FGCMAR                    (volatile uint32_t *) (DMA2D_BASE + 0x2C)               /* DMA2D Foreground CLUT Memory Address Register */
-#define DMA2D_BGCMAR                    (volatile uint32_t *) (DMA2D_BASE + 0x30)               /* DMA2D Background CLUT Memory Address Register */
-#define DMA2D_OPFCCR                    (volatile uint32_t *) (DMA2D_BASE + 0x34)               /* DMA2D Output PFC Control Register */
-#define DMA2D_OCOLR                     (volatile uint32_t *) (DMA2D_BASE + 0x38)               /* DMA2D Output Color Register */
-#define DMA2D_OMAR                      (volatile uint32_t *) (DMA2D_BASE + 0x3C)               /* DMA2D Output Memory Address Register */
-#define DMA2D_OOR                       (volatile uint32_t *) (DMA2D_BASE + 0x40)               /* DMA2D Output Offset Register */
-#define DMA2D_NLR                       (volatile uint32_t *) (DMA2D_BASE + 0x44)               /* DMA2D Number of Line Register */
-#define DMA2D_LWR                       (volatile uint32_t *) (DMA2D_BASE + 0x48)               /* DMA2D Line Watermark Register */
-#define DMA2D_AMTCR                     (volatile uint32_t *) (DMA2D_BASE + 0x4C)               /* DMA2D AHB Master Timer Configuration Register */
+#define DMA2D_CR \
+    (volatile uint32_t *) (DMA2D_BASE + 0x00) /* DMA2D Control Register */
+#define DMA2D_ISR                       \
+    (volatile uint32_t *) (DMA2D_BASE + \
+                           0x04) /* DMA2D Interrupt Status Register */
+#define DMA2D_IFCR                      \
+    (volatile uint32_t *) (DMA2D_BASE + \
+                           0x08) /* DMA2D Interrupt Flag Clear Register */
+#define DMA2D_FGMAR    \
+    (volatile uint32_t \
+         *) (DMA2D_BASE + 0x0C) /* DMA2D Foreground Memory Address Register */
+#define DMA2D_FGOR                      \
+    (volatile uint32_t *) (DMA2D_BASE + \
+                           0x10) /* DMA2D Foreground Offset Register */
+#define DMA2D_BGMAR    \
+    (volatile uint32_t \
+         *) (DMA2D_BASE + 0x14) /* DMA2D Background Memory Address Register */
+#define DMA2D_BGOR                      \
+    (volatile uint32_t *) (DMA2D_BASE + \
+                           0x18) /* DMA2D Background Offset Register */
+#define DMA2D_FGPFCCR                   \
+    (volatile uint32_t *) (DMA2D_BASE + \
+                           0x1C) /* DMA2D Foreground PFC Control Register */
+#define DMA2D_FGCOLR                    \
+    (volatile uint32_t *) (DMA2D_BASE + \
+                           0x20) /* DMA2D Foreground Color Control Register */
+#define DMA2D_BGPFCCR                   \
+    (volatile uint32_t *) (DMA2D_BASE + \
+                           0x24) /* DMA2D Background PFC Control Register */
+#define DMA2D_BGCOLR                    \
+    (volatile uint32_t *) (DMA2D_BASE + \
+                           0x28) /* DMA2D Background Color Control Register */
+#define DMA2D_FGCMAR                                                          \
+    (volatile uint32_t *) (DMA2D_BASE + 0x2C) /* DMA2D Foreground CLUT Memory \
+                                                 Address Register */
+#define DMA2D_BGCMAR                                                          \
+    (volatile uint32_t *) (DMA2D_BASE + 0x30) /* DMA2D Background CLUT Memory \
+                                                 Address Register */
+#define DMA2D_OPFCCR                    \
+    (volatile uint32_t *) (DMA2D_BASE + \
+                           0x34) /* DMA2D Output PFC Control Register */
+#define DMA2D_OCOLR                                                          \
+    (volatile uint32_t *) (DMA2D_BASE + 0x38) /* DMA2D Output Color Register \
+                                               */
+#define DMA2D_OMAR                      \
+    (volatile uint32_t *) (DMA2D_BASE + \
+                           0x3C) /* DMA2D Output Memory Address Register */
+#define DMA2D_OOR                                                             \
+    (volatile uint32_t *) (DMA2D_BASE + 0x40) /* DMA2D Output Offset Register \
+                                               */
+#define DMA2D_NLR                       \
+    (volatile uint32_t *) (DMA2D_BASE + \
+                           0x44) /* DMA2D Number of Line Register */
+#define DMA2D_LWR                       \
+    (volatile uint32_t *) (DMA2D_BASE + \
+                           0x48) /* DMA2D Line Watermark Register */
+#define DMA2D_AMTCR                                                     \
+    (volatile uint32_t *) (DMA2D_BASE + 0x4C) /* DMA2D AHB Master Timer \
+                                                 Configuration Register */
 
 /* USB OTG Full-Speed */
 /* Global Control and Status Registers */
-#define USB_FS_GOTGCTL                  (volatile uint32_t *) (USB_FS_BASE + 0x0000)            /* USB control and status register */
-#define USB_FS_GOTGINT                  (volatile uint32_t *) (USB_FS_BASE + 0x0004)            /* USB interrupt register */
-#define USB_FS_GAHBCFG                  (volatile uint32_t *) (USB_FS_BASE + 0x0008)            /* USB AHB configuration register */
-#define USB_FS_GUSBCFG                  (volatile uint32_t *) (USB_FS_BASE + 0x000C)            /* USB USB configuration register */
-#define USB_FS_GRSTCTL                  (volatile uint32_t *) (USB_FS_BASE + 0x0010)            /* USB reset control register */
-#define USB_FS_GINTSTS                  (volatile uint32_t *) (USB_FS_BASE + 0x0014)            /* USB core interrupt register */
-#define USB_FS_GINTMSK                  (volatile uint32_t *) (USB_FS_BASE + 0x0018)            /* USB interrupt mask register */
-#define USB_FS_GRXSTSR                  (volatile uint32_t *) (USB_FS_BASE + 0x001C)            /* USB receive status debug read register */
-#define USB_FS_GRXSTSP                  (volatile uint32_t *) (USB_FS_BASE + 0x0020)            /* USB receive status debug read and pop register */
-#define USB_FS_GRXFSIZ                  (volatile uint32_t *) (USB_FS_BASE + 0x0024)            /* USB receive FIFO size register */
-#define USB_FS_DIEPTXF0                 (volatile uint32_t *) (USB_FS_BASE + 0x0028)            /* USB endpoint 0 transmit FIFO size register */
-#define USB_FS_HNPTXFSIZ                (volatile uint32_t *) (USB_FS_BASE + 0x0028)            /* USB host non-periodic transmit FIFO size register */
-#define USB_FS_HNPTXSTS                 (volatile uint32_t *) (USB_FS_BASE + 0x002C)            /* USB host non-periodic transmit FIFO/queue status register */
-#define USB_FS_GCCFG                    (volatile uint32_t *) (USB_FS_BASE + 0x0038)            /* USB general core configuration register */
-#define USB_FS_CID                      (volatile uint32_t *) (USB_FS_BASE + 0x003C)            /* USB core ID register */
-#define USB_FS_HPTXFSIZ                 (volatile uint32_t *) (USB_FS_BASE + 0x0100)            /* USB host periodic transmit FIFO size register */
-#define USB_FS_DIEPTXF1                 (volatile uint32_t *) (USB_FS_BASE + 0x0104)            /* USB device IN endpoint transmit FIFO size register 1 */
-#define USB_FS_DIEPTXF2                 (volatile uint32_t *) (USB_FS_BASE + 0x0108)            /* USB device IN endpoint transmit FIFO size register 2 */
-#define USB_FS_DIEPTXF3                 (volatile uint32_t *) (USB_FS_BASE + 0x010C)            /* USB device IN endpoint transmit FIFO size register 3 */
+#define USB_FS_GOTGCTL                   \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x0000) /* USB control and status register */
+#define USB_FS_GOTGINT \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0004) /* USB interrupt register */
+#define USB_FS_GAHBCFG                   \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x0008) /* USB AHB configuration register */
+#define USB_FS_GUSBCFG                   \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x000C) /* USB USB configuration register */
+#define USB_FS_GRSTCTL                   \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x0010) /* USB reset control register */
+#define USB_FS_GINTSTS                   \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x0014) /* USB core interrupt register */
+#define USB_FS_GINTMSK                   \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x0018) /* USB interrupt mask register */
+#define USB_FS_GRXSTSR                                                       \
+    (volatile uint32_t *) (USB_FS_BASE + 0x001C) /* USB receive status debug \
+                                                    read register */
+#define USB_FS_GRXSTSP                                                       \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0020) /* USB receive status debug \
+                                                    read and pop register */
+#define USB_FS_GRXFSIZ                   \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x0024) /* USB receive FIFO size register */
+#define USB_FS_DIEPTXF0                                                     \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0028) /* USB endpoint 0 transmit \
+                                                    FIFO size register */
+#define USB_FS_HNPTXFSIZ   \
+    (volatile uint32_t     \
+         *) (USB_FS_BASE + \
+             0x0028) /* USB host non-periodic transmit FIFO size register */
+#define USB_FS_HNPTXSTS                                              \
+    (volatile uint32_t *) (USB_FS_BASE +                             \
+                           0x002C) /* USB host non-periodic transmit \
+                                      FIFO/queue status register */
+#define USB_FS_GCCFG                                                 \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0038) /* USB general core \
+                                                    configuration register */
+#define USB_FS_CID \
+    (volatile uint32_t *) (USB_FS_BASE + 0x003C) /* USB core ID register */
+#define USB_FS_HPTXFSIZ                                                        \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0100) /* USB host periodic transmit \
+                                                    FIFO size register */
+#define USB_FS_DIEPTXF1                                                    \
+    (volatile uint32_t *) (USB_FS_BASE +                                   \
+                           0x0104) /* USB device IN endpoint transmit FIFO \
+                                      size register 1 */
+#define USB_FS_DIEPTXF2                                                    \
+    (volatile uint32_t *) (USB_FS_BASE +                                   \
+                           0x0108) /* USB device IN endpoint transmit FIFO \
+                                      size register 2 */
+#define USB_FS_DIEPTXF3                                                    \
+    (volatile uint32_t *) (USB_FS_BASE +                                   \
+                           0x010C) /* USB device IN endpoint transmit FIFO \
+                                      size register 3 */
 
 /* Host-mode Registers */
 /* ... */
 
 /* Device-mode Registers */
-#define USB_FS_DCFG                     (volatile uint32_t *) (USB_FS_BASE + 0x0800)            /* USB device configuration register */
-#define USB_FS_DCTL                     (volatile uint32_t *) (USB_FS_BASE + 0x0804)            /* USB device control register */
-#define USB_FS_DSTS                     (volatile uint32_t *) (USB_FS_BASE + 0x0808)            /* USB device status register */
-#define USB_FS_DSTS                     (volatile uint32_t *) (USB_FS_BASE + 0x0808)            /* USB device status register */
-#define USB_FS_DIEPMSK                  (volatile uint32_t *) (USB_FS_BASE + 0x0810)            /* USB device IN endpoint common interrupt mask register */
-#define USB_FS_DOEPMSK                  (volatile uint32_t *) (USB_FS_BASE + 0x0814)            /* USB device OUT endpoint common interrupt mask register */
-#define USB_FS_DAINT                    (volatile uint32_t *) (USB_FS_BASE + 0x0818)            /* USB device all endpoints interrupt register */
-#define USB_FS_DAINTMSK                 (volatile uint32_t *) (USB_FS_BASE + 0x081C)            /* USB device all endpoints interrupt mask register */
-#define USB_FS_DVBUSDIS                 (volatile uint32_t *) (USB_FS_BASE + 0x0828)            /* USB device VBUS discharge time register */
-#define USB_FS_DVBUSPULSE               (volatile uint32_t *) (USB_FS_BASE + 0x082C)            /* USB device VBUS pulse time register */
-#define USB_FS_DIEPEMPMSK               (volatile uint32_t *) (USB_FS_BASE + 0x0834)            /* USB device IN endpoint FIFO empty interrupt mask register */
-#define USB_FS_DIEPCTL0                 (volatile uint32_t *) (USB_FS_BASE + 0x0900)            /* USB device IN endpoint 0 control register */
-#define USB_FS_DIEPCTL(n)               (volatile uint32_t *) (USB_FS_BASE + 0x0900 + n*0x20)   /* USB device endpoint n control register */
-#define USB_FS_DIEPINT(n)               (volatile uint32_t *) (USB_FS_BASE + 0x0908 + n*0x20)   /* USB device endpoint n interrupt register */
-#define USB_FS_DIEPTSIZ0                (volatile uint32_t *) (USB_FS_BASE + 0x0910)            /* USB device IN endpoint 0 transfer size register */
-#define USB_FS_DIEPTSIZ(n)              (volatile uint32_t *) (USB_FS_BASE + 0x0910 + n*0x20)   /* USB device OUT endpoint n transfer size register */
-#define USB_FS_DTXFSTS(n)               (volatile uint32_t *) (USB_FS_BASE + 0x0918 + n*0x20)   /* USB device IN endpoint n FIFO status register */
-#define USB_FS_DOEPCTL0                 (volatile uint32_t *) (USB_FS_BASE + 0x0B00)            /* USB device OUT endpoint 0 control register */
-#define USB_FS_DOEPCTL(n)               (volatile uint32_t *) (USB_FS_BASE + 0x0B00 + n*0x20)   /* USB device endpoint n control register */
-#define USB_FS_DOEPINT(n)               (volatile uint32_t *) (USB_FS_BASE + 0x0B08 + n*0x20)   /* USB device endpoint 1 interrupt register */
-#define USB_FS_DOEPTSIZ0                (volatile uint32_t *) (USB_FS_BASE + 0x0B10)            /* USB device OUT endpoint 0 transfer size register */
-#define USB_FS_DOEPTSIZ(n)              (volatile uint32_t *) (USB_FS_BASE + 0x0B10 + n*0x20)   /* USB device OUT endpoint n transfer size register */
+#define USB_FS_DCFG                      \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x0800) /* USB device configuration register */
+#define USB_FS_DCTL                      \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x0804) /* USB device control register */
+#define USB_FS_DSTS                      \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x0808) /* USB device status register */
+#define USB_FS_DSTS                      \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x0808) /* USB device status register */
+#define USB_FS_DIEPMSK                                                        \
+    (volatile uint32_t *) (USB_FS_BASE +                                      \
+                           0x0810) /* USB device IN endpoint common interrupt \
+                                      mask register */
+#define USB_FS_DOEPMSK                                                         \
+    (volatile uint32_t *) (USB_FS_BASE +                                       \
+                           0x0814) /* USB device OUT endpoint common interrupt \
+                                      mask register */
+#define USB_FS_DAINT                                                         \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0818) /* USB device all endpoints \
+                                                    interrupt register */
+#define USB_FS_DAINTMSK                                                      \
+    (volatile uint32_t *) (USB_FS_BASE + 0x081C) /* USB device all endpoints \
+                                                    interrupt mask register */
+#define USB_FS_DVBUSDIS                                                       \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0828) /* USB device VBUS discharge \
+                                                    time register */
+#define USB_FS_DVBUSPULSE                \
+    (volatile uint32_t *) (USB_FS_BASE + \
+                           0x082C) /* USB device VBUS pulse time register */
+#define USB_FS_DIEPEMPMSK                                               \
+    (volatile uint32_t *) (USB_FS_BASE +                                \
+                           0x0834) /* USB device IN endpoint FIFO empty \
+                                      interrupt mask register */
+#define USB_FS_DIEPCTL0                                                      \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0900) /* USB device IN endpoint 0 \
+                                                    control register */
+#define USB_FS_DIEPCTL(n)           \
+    (volatile uint32_t              \
+         *) (USB_FS_BASE + 0x0900 + \
+             n * 0x20) /* USB device endpoint n control register */
+#define USB_FS_DIEPINT(n)           \
+    (volatile uint32_t              \
+         *) (USB_FS_BASE + 0x0908 + \
+             n * 0x20) /* USB device endpoint n interrupt register */
+#define USB_FS_DIEPTSIZ0                                                     \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0910) /* USB device IN endpoint 0 \
+                                                    transfer size register */
+#define USB_FS_DIEPTSIZ(n)          \
+    (volatile uint32_t              \
+         *) (USB_FS_BASE + 0x0910 + \
+             n * 0x20) /* USB device OUT endpoint n transfer size register */
+#define USB_FS_DTXFSTS(n)           \
+    (volatile uint32_t              \
+         *) (USB_FS_BASE + 0x0918 + \
+             n * 0x20) /* USB device IN endpoint n FIFO status register */
+#define USB_FS_DOEPCTL0                                                       \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0B00) /* USB device OUT endpoint 0 \
+                                                    control register */
+#define USB_FS_DOEPCTL(n)           \
+    (volatile uint32_t              \
+         *) (USB_FS_BASE + 0x0B00 + \
+             n * 0x20) /* USB device endpoint n control register */
+#define USB_FS_DOEPINT(n)           \
+    (volatile uint32_t              \
+         *) (USB_FS_BASE + 0x0B08 + \
+             n * 0x20) /* USB device endpoint 1 interrupt register */
+#define USB_FS_DOEPTSIZ0                                                      \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0B10) /* USB device OUT endpoint 0 \
+                                                    transfer size register */
+#define USB_FS_DOEPTSIZ(n)          \
+    (volatile uint32_t              \
+         *) (USB_FS_BASE + 0x0B10 + \
+             n * 0x20) /* USB device OUT endpoint n transfer size register */
 
 /* Data FIFO Registers */
-#define USB_FS_DFIFO_EP(n)              (volatile uint32_t *) (USB_FS_BASE + 0x1000 + n*0x1000) /* USB endpoint n data FIFO base address */
+#define USB_FS_DFIFO_EP(n)          \
+    (volatile uint32_t              \
+         *) (USB_FS_BASE + 0x1000 + \
+             n * 0x1000) /* USB endpoint n data FIFO base address */
 
 /* Power and Clock Gating Registers */
-#define USB_FS_PCGCR                    (volatile uint32_t *) (USB_FS_BASE + 0x0E00)            /* USB power and clock gating control register */
+#define USB_FS_PCGCR                                                           \
+    (volatile uint32_t *) (USB_FS_BASE + 0x0E00) /* USB power and clock gating \
+                                                    control register */
 
 
 /**********************************************************************************************************************************************/
 
 /* Bit Masks - See RM0090 Reference Manual for STM32F4 for details */
-#define PWR_CR_VOS                      (uint16_t) (1 << 14)                                    /* Regulator voltage scaling output selection */
-
-#define HSI_VALUE                       (uint32_t) (16000000)                                   /* HSI value in Hz */
-#define HSE_VALUE                       (uint32_t) (1 << 27)                                    /* HSE value in Hz */
-
-#define RCC_CR_HSION                    (uint32_t) (1 << 0)                                     /* HSI clock enable */
-#define RCC_CR_HSIRDY                   (uint32_t) (1 << 1)                                     /* HSI ready */
-#define RCC_CR_HSITRIM_M                (uint32_t) (0x1F << 3)                                  /* HSI trimming mask */
-#define RCC_CR_HSITRIM(n)               (uint32_t) (n << 3)                                     /* HSI trimming */
-#define RCC_CR_HSICAL_M                 (uint32_t) (0xFF << 8)                                  /* HSI calibration mask */
-#define RCC_CR_HSEON                    (uint32_t) (1 << 16)                                    /* HSE clock enable */
-#define RCC_CR_HSERDY                   (uint32_t) (1 << 17)                                    /* HSE ready */
-#define RCC_CR_HSEBYP                   (uint32_t) (1 << 18)                                    /* HSE bypass */
-#define RCC_CR_CSSON                    (uint32_t) (1 << 19)                                    /* Clock security system enable */
-#define RCC_CR_PLLON                    (uint32_t) (1 << 24)                                    /* Main PLL enable */
-#define RCC_CR_PLLRDY                   (uint32_t) (1 << 25)                                    /* Main PLL clock ready */
-#define RCC_CR_PLLI2SON                 (uint32_t) (1 << 26)                                    /* PLLI2S enable */
-#define RCC_CR_PLLI2SRDY                (uint32_t) (1 << 27)                                    /* PLLI2S clock ready */
-
-#define RCC_PLLCFGR_RESET               (uint32_t) (0x24003010)                                 /* PLLCFGR register reset value */
-#define RCC_PLLCFGR_PLLSRC_HSE          (uint32_t) (1 << 22)                                    /* HSE oscillator selected as clock entry */
-#define RCC_PLLCFGR_PLLM                (uint32_t) (0x003F)
-#define RCC_PLLCFGR_PLLN                (uint32_t) (0x7FC0)
-#define RCC_PLLCFGR_PLLP                (uint32_t) (0x00030000)
-
-#define RCC_CFGR_SW_M                   (uint32_t) (3 << 0)                                     /* System clock switch mask */
-#define RCC_CFGR_SW_HSI                 (uint32_t) (0 << 0)                                     /* System clock switch - HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                 (uint32_t) (1 << 0)                                     /* System clock switch - HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                 (uint32_t) (2 << 0)                                     /* System clock switch - PLL selected as system clock */
-#define RCC_CFGR_SWS_M                  (uint32_t) (3 << 2)                                     /* System clock switch status mask */
-#define RCC_CFGR_SWS_HSI                (uint32_t) (0 << 2)                                     /* System clock switch status - HSI used as system clock */
-#define RCC_CFGR_SWS_HSE                (uint32_t) (1 << 2)                                     /* System clock switch status - HSE used as system clock */
-#define RCC_CFGR_SWS_PLL                (uint32_t) (2 << 2)                                     /* System clock switch status - PLL used as system clock */
-#define RCC_CFGR_HPRE_M                 (uint32_t) (0xF << 4)                                   /* AHB prescaler mask */
-#define RCC_CFGR_HPRE_DIV1              (uint32_t) (0x0 << 4)                                   /* AHB prescaler - SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2              (uint32_t) (0x8 << 4)                                   /* AHB prescaler - SYSCLK/2 */
-#define RCC_CFGR_HPRE_DIV4              (uint32_t) (0x9 << 4)                                   /* AHB prescaler - SYSCLK/4 */
-#define RCC_CFGR_HPRE_DIV8              (uint32_t) (0xA << 4)                                   /* AHB prescaler - SYSCLK/8 */
-#define RCC_CFGR_HPRE_DIV16             (uint32_t) (0xB << 4)                                   /* AHB prescaler - SYSCLK/16 */
-#define RCC_CFGR_HPRE_DIV64             (uint32_t) (0xC << 4)                                   /* AHB prescaler - SYSCLK/64 */
-#define RCC_CFGR_HPRE_DIV128            (uint32_t) (0xD << 4)                                   /* AHB prescaler - SYSCLK/128 */
-#define RCC_CFGR_HPRE_DIV256            (uint32_t) (0xE << 4)                                   /* AHB prescaler - SYSCLK/256 */
-#define RCC_CFGR_HPRE_DIV512            (uint32_t) (0xF << 4)                                   /* AHB prescaler - SYSCLK/512 */
-#define RCC_CFGR_PPRE1_M                (uint32_t) (7 << 10)                                    /* APB low speed prescaler mask */
-#define RCC_CFGR_PPRE1_DIV1             (uint32_t) (0 << 10)                                    /* APB low speed prescaler - HCLK/1 */
-#define RCC_CFGR_PPRE1_DIV2             (uint32_t) (4 << 10)                                    /* APB low speed prescaler - HCLK/2 */
-#define RCC_CFGR_PPRE1_DIV4             (uint32_t) (5 << 10)                                    /* APB low speed prescaler - HCLK/4 */
-#define RCC_CFGR_PPRE1_DIV8             (uint32_t) (6 << 10)                                    /* APB low speed prescaler - HCLK/8 */
-#define RCC_CFGR_PPRE1_DIV16            (uint32_t) (7 << 10)                                    /* APB low speed prescaler - HCLK/16 */
-#define RCC_CFGR_PPRE2_M                (uint32_t) (7 << 13)                                    /* APB high speec prescaler mask */
-#define RCC_CFGR_PPRE2_DIV1             (uint32_t) (0 << 13)                                    /* APB high speed prescaler - HCLK/1 */
-#define RCC_CFGR_PPRE2_DIV2             (uint32_t) (4 << 13)                                    /* APB high speed prescaler - HCLK/2 */
-#define RCC_CFGR_PPRE2_DIV4             (uint32_t) (5 << 13)                                    /* APB high speed prescaler - HCLK/4 */
-#define RCC_CFGR_PPRE2_DIV8             (uint32_t) (6 << 13)                                    /* APB high speed prescaler - HCLK/8 */
-#define RCC_CFGR_PPRE2_DIV16            (uint32_t) (7 << 13)                                    /* APB high speed prescaler - HCLK/16 */
-#define RCC_CFGR_RTCPRE_M               (uint32_t) (0x1F << 16)                                 /* HSE division factor for RTC clock mask */
-#define RCC_CFGR_RTCPRE(n)              (uint32_t) (n << 16)                                    /* HSE division factor for RTC clock */
-
-#define RCC_AHB1RSTR_GPIOARST           (uint32_t) (1 << 0)                                     /* GPIOA reset */
-#define RCC_AHB1RSTR_GPIOBRST           (uint32_t) (1 << 1)                                     /* GPIOB reset */
-#define RCC_AHB1RSTR_GPIOCRST           (uint32_t) (1 << 2)                                     /* GPIOC reset */
-#define RCC_AHB1RSTR_GPIODRST           (uint32_t) (1 << 3)                                     /* GPIOD reset */
-#define RCC_AHB1RSTR_GPIOERST           (uint32_t) (1 << 4)                                     /* GPIOE reset */
-#define RCC_AHB1RSTR_GPIOFRST           (uint32_t) (1 << 5)                                     /* GPIOF reset */
-#define RCC_AHB1RSTR_GPIOGRST           (uint32_t) (1 << 6)                                     /* GPIOG reset */
-#define RCC_AHB1RSTR_GPIOHRST           (uint32_t) (1 << 7)                                     /* GPIOH reset */
-#define RCC_AHB1RSTR_GPIOIRST           (uint32_t) (1 << 8)                                     /* GPIOI reset */
-#define RCC_AHB1RSTR_CRCRST             (uint32_t) (1 << 12)                                    /* CRC reset */
-#define RCC_AHB1RSTR_DMA1RST            (uint32_t) (1 << 21)                                    /* DMA1 reset */
-#define RCC_AHB1RSTR_DMA2RST            (uint32_t) (1 << 22)                                    /* DMA2 reset */
-#define RCC_AHB1RSTR_ETHMACRST          (uint32_t) (1 << 25)                                    /* Ethernet MAC reset */
-#define RCC_AHB1RSTR_OTGHSRST           (uint32_t) (1 << 29)                                    /* USB OTG HS reset */
-
-#define RCC_AHB2RSTR_DCMIRST            (uint32_t) (1 << 0)                                     /* Camera interface reset */
-#define RCC_AHB2RSTR_CRYPRST            (uint32_t) (1 << 4)                                     /* Cyrpto modules reset */
-#define RCC_AHB2RSTR_HASHRST            (uint32_t) (1 << 5)                                     /* Hash modules reset */
-#define RCC_AHB2RSTR_RNGRST             (uint32_t) (1 << 6)                                     /* Random number generator reset */
-#define RCC_AHB2RSTR_OTGFSRST           (uint32_t) (1 << 7)                                     /* USB OTG FS reset */
-
-#define RCC_AHB3RSTR_FSMCRST            (uint32_t) (1 << 0)                                     /* Flexible static memeory controller reset */
-
-#define RCC_APB1RSTR_TIM2RST            (uint32_t) (1 << 0)                                     /* TIM2 reset */
-#define RCC_APB1RSTR_TIM3RST            (uint32_t) (1 << 1)                                     /* TIM3 reset */
-#define RCC_APB1RSTR_TIM4RST            (uint32_t) (1 << 2)                                     /* TIM4 reset */
-#define RCC_APB1RSTR_TIM5RST            (uint32_t) (1 << 3)                                     /* TIM5 reset */
-#define RCC_APB1RSTR_TIM6RST            (uint32_t) (1 << 4)                                     /* TIM6 reset */
-#define RCC_APB1RSTR_TIM7RST            (uint32_t) (1 << 5)                                     /* TIM7 reset */
-#define RCC_APB1RSTR_TIM12RST           (uint32_t) (1 << 6)                                     /* TIM12 reset */
-#define RCC_APB1RSTR_TIM13RST           (uint32_t) (1 << 7)                                     /* TIM13 reset */
-#define RCC_APB1RSTR_TIM14RST           (uint32_t) (1 << 8)                                     /* TIM14 reset */
-#define RCC_APB1RSTR_WWDGRST            (uint32_t) (1 << 11)                                    /* Window watchdog reset */
-#define RCC_APB1RSTR_SPI2RST            (uint32_t) (1 << 14)                                    /* SPI2 reset */
-#define RCC_APB1RSTR_SPI3RST            (uint32_t) (1 << 15)                                    /* SPI3 reset */
-#define RCC_APB1RSTR_USART2RST          (uint32_t) (1 << 17)                                    /* USART2 reset */
-#define RCC_APB1RSTR_USART3RST          (uint32_t) (1 << 18)                                    /* USART3 reset */
-#define RCC_APB1RSTR_USART4RST          (uint32_t) (1 << 19)                                    /* USART4 reset */
-#define RCC_APB1RSTR_USART5RST          (uint32_t) (1 << 20)                                    /* USART5 reset */
-#define RCC_APB1RSTR_I2C1RST            (uint32_t) (1 << 21)                                    /* I2C1 reset */
-#define RCC_APB1RSTR_I2C2RST            (uint32_t) (1 << 22)                                    /* I2C2 reset */
-#define RCC_APB1RSTR_I2C3RST            (uint32_t) (1 << 23)                                    /* I2C3 reset */
-#define RCC_APB1RSTR_CAN1RST            (uint32_t) (1 << 25)                                    /* CAN1 reset */
-#define RCC_APB1RSTR_CAN2RST            (uint32_t) (1 << 26)                                    /* CAN2 reset */
-#define RCC_APB1RSTR_PWRRST             (uint32_t) (1 << 28)                                    /* Power interface reset */
-#define RCC_APB1RSTR_DACRST             (uint32_t) (1 << 29)                                    /* DAC reset */
-
-#define RCC_APB2RSTR_TIM1RST            (uint32_t) (1 << 0)                                     /* TIM1 reset */
-#define RCC_APB2RSTR_TIM8RST            (uint32_t) (1 << 1)                                     /* TIM8 reset */
-#define RCC_APB2RSTR_USART1RST          (uint32_t) (1 << 4)                                     /* USART1 reset */
-#define RCC_APB2RSTR_USART6RST          (uint32_t) (1 << 5)                                     /* USART6 reset */
-#define RCC_APB2RSTR_ADCRST             (uint32_t) (1 << 8)                                     /* ADC1 reset */
-#define RCC_APB2RSTR_SDIORST            (uint32_t) (1 << 11)                                    /* SDIO reset */
-#define RCC_APB2RSTR_SPI1RST            (uint32_t) (1 << 12)                                    /* SPI1 reset */
-#define RCC_APB2RSTR_SPI5RST            (uint32_t) (1 << 20)                                    /* SPI5 reset */
-#define RCC_APB2RSTR_SYSCFGRST          (uint32_t) (1 << 14)                                    /* System configuration controller reset */
-#define RCC_APB2RSTR_TIM9RST            (uint32_t) (1 << 16)                                    /* TIM9 reset */
-#define RCC_APB2RSTR_TIM10RST           (uint32_t) (1 << 17)                                    /* TIM10 reset */
-#define RCC_APB2RSTR_TIM11RST           (uint32_t) (1 << 18)                                    /* TIM11 reset */
-#define RCC_APB2RSTR_LTDC               (uint32_t) (1 << 26)                                    /* LTDC reset */
-
-#define RCC_AHB1ENR_GPIOAEN             (uint32_t) (1 << 0)                                     /* GPIOA clock enable */
-#define RCC_AHB1ENR_GPIOBEN             (uint32_t) (1 << 1)                                     /* GPIOB clock enable */
-#define RCC_AHB1ENR_GPIOCEN             (uint32_t) (1 << 2)                                     /* GPIOC clock enable */
-#define RCC_AHB1ENR_GPIODEN             (uint32_t) (1 << 3)                                     /* GPIOD clock enable */
-#define RCC_AHB1ENR_GPIOEEN             (uint32_t) (1 << 4)                                     /* GPIOE clock enable */
-#define RCC_AHB1ENR_GPIOFEN             (uint32_t) (1 << 5)                                     /* GPIOF clock enable */
-#define RCC_AHB1ENR_GPIOGEN             (uint32_t) (1 << 6)                                     /* GPIOG clock enable */
-#define RCC_AHB1ENR_GPIOHEN             (uint32_t) (1 << 7)                                     /* GPIOH clock enable */
-#define RCC_AHB1ENR_GPIOIEN             (uint32_t) (1 << 8)                                     /* GPIOI clock enable */
-#define RCC_AHB1ENR_CRCEN               (uint32_t) (1 << 12)                                    /* CRC clock enable */
-#define RCC_AHB1ENR_BKPSRAMEN           (uint32_t) (1 << 18)                                    /* Backup SRAM clock enable */
-#define RCC_AHB1ENR_CCMDATARAMEN        (uint32_t) (1 << 20)                                    /* CCM data RAM clock enable */
-#define RCC_AHB1ENR_DMA1EN              (uint32_t) (1 << 21)                                    /* DMA1 clock enable */
-#define RCC_AHB1ENR_DMA2EN              (uint32_t) (1 << 22)                                    /* DMA2 clock enable */
-#define RCC_AHB1ENR_DMA2DEN             (uint32_t) (1 << 23)                                    /* DMA2D clock enable */
-#define RCC_AHB1ENR_ETHMACEN            (uint32_t) (1 << 25)                                    /* Ethernet MAC clock enable */
-#define RCC_AHB1ENR_ETHMACTXEN          (uint32_t) (1 << 26)                                    /* Ethernet MAC TX clock enable */
-#define RCC_AHB1ENR_ETHMACRXEN          (uint32_t) (1 << 27)                                    /* Ethernet MAC RX clock enable */
-#define RCC_AHB1ENR_ETHMACPTPEN         (uint32_t) (1 << 28)                                    /* Ethernet MAC PTP clock enable */
-#define RCC_AHB1ENR_OTGHSEN             (uint32_t) (1 << 29)                                    /* USB OTG HS clock enable */
-#define RCC_AHB1ENR_OTGHSULPIEN         (uint32_t) (1 << 30)                                    /* USB OTG HSULPI clock enable */
-
-#define RCC_AHB2ENR_DCMIEN              (uint32_t) (1 << 0)                                     /* Camera interface clock enable */
-#define RCC_AHB2ENR_CRYPEN              (uint32_t) (1 << 4)                                     /* Cyrpto modules clock enable */
-#define RCC_AHB2ENR_HASHEN              (uint32_t) (1 << 5)                                     /* Hash modules clock enable */
-#define RCC_AHB2ENR_RNGEN               (uint32_t) (1 << 6)                                     /* Random number generator clock enable */
-#define RCC_AHB2ENR_OTGFSEN             (uint32_t) (1 << 7)                                     /* USB OTG FS clock enable */
-
-#define RCC_AHB3ENR_FSMCEN              (uint32_t) (1 << 0)                                     /* Flexible static memeory controller clock enable */
-#define RCC_AHB3ENR_FMCEN               (uint32_t) (1 << 0)                                     /* FMC clock enable */
-
-#define RCC_APB1ENR_TIM2EN              (uint32_t) (1 << 0)                                     /* TIM2 clock enable */
-#define RCC_APB1ENR_TIM3EN              (uint32_t) (1 << 1)                                     /* TIM3 clock enable */
-#define RCC_APB1ENR_TIM4EN              (uint32_t) (1 << 2)                                     /* TIM4 clock enable */
-#define RCC_APB1ENR_TIM5EN              (uint32_t) (1 << 3)                                     /* TIM5 clock enable */
-#define RCC_APB1ENR_TIM6EN              (uint32_t) (1 << 4)                                     /* TIM6 clock enable */
-#define RCC_APB1ENR_TIM7EN              (uint32_t) (1 << 5)                                     /* TIM7 clock enable */
-#define RCC_APB1ENR_TIM12EN             (uint32_t) (1 << 6)                                     /* TIM12 clock enable */
-#define RCC_APB1ENR_TIM13EN             (uint32_t) (1 << 7)                                     /* TIM13 clock enable */
-#define RCC_APB1ENR_TIM14EN             (uint32_t) (1 << 8)                                     /* TIM14 clock enable */
-#define RCC_APB1ENR_WWDGEN              (uint32_t) (1 << 11)                                    /* Window watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN              (uint32_t) (1 << 14)                                    /* SPI2 clock enable */
-#define RCC_APB1ENR_SPI3EN              (uint32_t) (1 << 15)                                    /* SPI3 clock enable */
-#define RCC_APB1ENR_USART2EN            (uint32_t) (1 << 17)                                    /* USART2 clock enable */
-#define RCC_APB1ENR_USART3EN            (uint32_t) (1 << 18)                                    /* USART3 clock enable */
-#define RCC_APB1ENR_USART4EN            (uint32_t) (1 << 19)                                    /* USART4 clock enable */
-#define RCC_APB1ENR_USART5EN            (uint32_t) (1 << 20)                                    /* USART5 clock enable */
-#define RCC_APB1ENR_I2C1EN              (uint32_t) (1 << 21)                                    /* I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN              (uint32_t) (1 << 22)                                    /* I2C2 clock enable */
-#define RCC_APB1ENR_I2C3EN              (uint32_t) (1 << 23)                                    /* I2C3 clock enable */
-#define RCC_APB1ENR_CAN1EN              (uint32_t) (1 << 25)                                    /* CAN1 clock enable */
-#define RCC_APB1ENR_CAN2EN              (uint32_t) (1 << 26)                                    /* CAN2 clock enable */
-#define RCC_APB1ENR_PWREN               (uint32_t) (1 << 28)                                    /* Power interface clock enable */
-#define RCC_APB1ENR_DACEN               (uint32_t) (1 << 29)                                    /* DAC clock enable */
-
-#define RCC_APB2ENR_TIM1EN              (uint32_t) (1 << 0)                                     /* TIM1 clock enable */
-#define RCC_APB2ENR_TIM8EN              (uint32_t) (1 << 1)                                     /* TIM8 clock enable */
-#define RCC_APB2ENR_USART1EN            (uint32_t) (1 << 4)                                     /* USART1 clock enable */
-#define RCC_APB2ENR_USART2EN            (uint32_t) (1 << 5)                                     /* USART2 clock enable */
-#define RCC_APB2ENR_ADC1EN              (uint32_t) (1 << 8)                                     /* ADC1 clock enable */
-#define RCC_APB2ENR_ADC2EN              (uint32_t) (1 << 9)                                     /* ADC2 clock enable */
-#define RCC_APB2ENR_ADC3EN              (uint32_t) (1 << 10)                                    /* ADC3 clock enable */
-#define RCC_APB2ENR_SDIOEN              (uint32_t) (1 << 11)                                    /* SDIO clock enable */
-#define RCC_APB2ENR_SPI1EN              (uint32_t) (1 << 12)                                    /* SPI1 clock enable */
-#define RCC_APB2ENR_SYSCFGEN            (uint32_t) (1 << 14)                                    /* System configuration controller clock enable */
-#define RCC_APB2ENR_TIM9EN              (uint32_t) (1 << 16)                                    /* TIM9 clock enable */
-#define RCC_APB2ENR_TIM10EN             (uint32_t) (1 << 17)                                    /* TIM10 clock enable */
-#define RCC_APB2ENR_TIM11EN             (uint32_t) (1 << 18)                                    /* TIM11 clock enable */
-#define RCC_APB2ENR_SPI5EN              (uint32_t) (1 << 20)                                    /* SPI5 clock enable */
-#define RCC_APB2ENR_LTDCEN              (uint32_t) (1 << 26)                                    /* LTDC clock enable */
-
-#define FLASH_ACR_PRFTEN                (uint32_t) (1 << 8)                                     /* Prefetch enable */
-#define FLASH_ACR_ICEN                  (uint32_t) (1 << 9)                                     /* Instruction cache enable */
-#define FLASH_ACR_DCEN                  (uint32_t) (1 << 10)                                    /* Data cache enable */
-#define FLASH_ACR_ICRST                 (uint32_t) (1 << 11)                                    /* Instruction cache reset */
-#define FLASH_ACR_CCRST                 (uint32_t) (1 << 12)                                    /* Data cache reset */
-#define FLASH_ACR_LATENCY_M             (uint32_t) (7 << 0)                                     /* Latency mask */
-#define FLASH_ACR_LATENCY(n)            (uint32_t) (n << 0)                                     /* Latency - n wait states */
+#define PWR_CR_VOS \
+    (uint16_t) (1 << 14) /* Regulator voltage scaling output selection */
+
+#define HSI_VALUE (uint32_t) (16000000) /* HSI value in Hz */
+#define HSE_VALUE (uint32_t) (1 << 27)  /* HSE value in Hz */
+
+#define RCC_CR_HSION (uint32_t) (1 << 0)        /* HSI clock enable */
+#define RCC_CR_HSIRDY (uint32_t) (1 << 1)       /* HSI ready */
+#define RCC_CR_HSITRIM_M (uint32_t) (0x1F << 3) /* HSI trimming mask */
+#define RCC_CR_HSITRIM(n) (uint32_t) (n << 3)   /* HSI trimming */
+#define RCC_CR_HSICAL_M (uint32_t) (0xFF << 8)  /* HSI calibration mask */
+#define RCC_CR_HSEON (uint32_t) (1 << 16)       /* HSE clock enable */
+#define RCC_CR_HSERDY (uint32_t) (1 << 17)      /* HSE ready */
+#define RCC_CR_HSEBYP (uint32_t) (1 << 18)      /* HSE bypass */
+#define RCC_CR_CSSON (uint32_t) (1 << 19)     /* Clock security system enable */
+#define RCC_CR_PLLON (uint32_t) (1 << 24)     /* Main PLL enable */
+#define RCC_CR_PLLRDY (uint32_t) (1 << 25)    /* Main PLL clock ready */
+#define RCC_CR_PLLI2SON (uint32_t) (1 << 26)  /* PLLI2S enable */
+#define RCC_CR_PLLI2SRDY (uint32_t) (1 << 27) /* PLLI2S clock ready */
+
+#define RCC_PLLCFGR_RESET \
+    (uint32_t) (0x24003010) /* PLLCFGR register reset value */
+#define RCC_PLLCFGR_PLLSRC_HSE \
+    (uint32_t) (1 << 22) /* HSE oscillator selected as clock entry */
+#define RCC_PLLCFGR_PLLM (uint32_t) (0x003F)
+#define RCC_PLLCFGR_PLLN (uint32_t) (0x7FC0)
+#define RCC_PLLCFGR_PLLP (uint32_t) (0x00030000)
+
+#define RCC_CFGR_SW_M (uint32_t) (3 << 0) /* System clock switch mask */
+#define RCC_CFGR_SW_HSI                                                       \
+    (uint32_t) (0 << 0) /* System clock switch - HSI selected as system clock \
+                         */
+#define RCC_CFGR_SW_HSE                                                       \
+    (uint32_t) (1 << 0) /* System clock switch - HSE selected as system clock \
+                         */
+#define RCC_CFGR_SW_PLL                                                       \
+    (uint32_t) (2 << 0) /* System clock switch - PLL selected as system clock \
+                         */
+#define RCC_CFGR_SWS_M                                     \
+    (uint32_t) (3 << 2) /* System clock switch status mask \
+                         */
+#define RCC_CFGR_SWS_HSI                                                   \
+    (uint32_t) (0 << 2) /* System clock switch status - HSI used as system \
+                           clock */
+#define RCC_CFGR_SWS_HSE                                                   \
+    (uint32_t) (1 << 2) /* System clock switch status - HSE used as system \
+                           clock */
+#define RCC_CFGR_SWS_PLL                                                   \
+    (uint32_t) (2 << 2) /* System clock switch status - PLL used as system \
+                           clock */
+#define RCC_CFGR_HPRE_M (uint32_t) (0xF << 4) /* AHB prescaler mask */
+#define RCC_CFGR_HPRE_DIV1 \
+    (uint32_t) (0x0 << 4) /* AHB prescaler - SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2                            \
+    (uint32_t) (0x8 << 4) /* AHB prescaler - SYSCLK/2 \
+                           */
+#define RCC_CFGR_HPRE_DIV4                            \
+    (uint32_t) (0x9 << 4) /* AHB prescaler - SYSCLK/4 \
+                           */
+#define RCC_CFGR_HPRE_DIV8                            \
+    (uint32_t) (0xA << 4) /* AHB prescaler - SYSCLK/8 \
+                           */
+#define RCC_CFGR_HPRE_DIV16 \
+    (uint32_t) (0xB << 4) /* AHB prescaler - SYSCLK/16 */
+#define RCC_CFGR_HPRE_DIV64 \
+    (uint32_t) (0xC << 4) /* AHB prescaler - SYSCLK/64 */
+#define RCC_CFGR_HPRE_DIV128 \
+    (uint32_t) (0xD << 4) /* AHB prescaler - SYSCLK/128 */
+#define RCC_CFGR_HPRE_DIV256 \
+    (uint32_t) (0xE << 4) /* AHB prescaler - SYSCLK/256 */
+#define RCC_CFGR_HPRE_DIV512 \
+    (uint32_t) (0xF << 4) /* AHB prescaler - SYSCLK/512 */
+#define RCC_CFGR_PPRE1_M                                 \
+    (uint32_t) (7 << 10) /* APB low speed prescaler mask \
+                          */
+#define RCC_CFGR_PPRE1_DIV1 \
+    (uint32_t) (0 << 10) /* APB low speed prescaler - HCLK/1 */
+#define RCC_CFGR_PPRE1_DIV2 \
+    (uint32_t) (4 << 10) /* APB low speed prescaler - HCLK/2 */
+#define RCC_CFGR_PPRE1_DIV4 \
+    (uint32_t) (5 << 10) /* APB low speed prescaler - HCLK/4 */
+#define RCC_CFGR_PPRE1_DIV8 \
+    (uint32_t) (6 << 10) /* APB low speed prescaler - HCLK/8 */
+#define RCC_CFGR_PPRE1_DIV16 \
+    (uint32_t) (7 << 10) /* APB low speed prescaler - HCLK/16 */
+#define RCC_CFGR_PPRE2_M \
+    (uint32_t) (7 << 13) /* APB high speec prescaler mask */
+#define RCC_CFGR_PPRE2_DIV1 \
+    (uint32_t) (0 << 13) /* APB high speed prescaler - HCLK/1 */
+#define RCC_CFGR_PPRE2_DIV2 \
+    (uint32_t) (4 << 13) /* APB high speed prescaler - HCLK/2 */
+#define RCC_CFGR_PPRE2_DIV4 \
+    (uint32_t) (5 << 13) /* APB high speed prescaler - HCLK/4 */
+#define RCC_CFGR_PPRE2_DIV8 \
+    (uint32_t) (6 << 13) /* APB high speed prescaler - HCLK/8 */
+#define RCC_CFGR_PPRE2_DIV16 \
+    (uint32_t) (7 << 13) /* APB high speed prescaler - HCLK/16 */
+#define RCC_CFGR_RTCPRE_M \
+    (uint32_t) (0x1F << 16) /* HSE division factor for RTC clock mask */
+#define RCC_CFGR_RTCPRE(n) \
+    (uint32_t) (n << 16) /* HSE division factor for RTC clock */
+
+#define RCC_AHB1RSTR_GPIOARST (uint32_t) (1 << 0)   /* GPIOA reset */
+#define RCC_AHB1RSTR_GPIOBRST (uint32_t) (1 << 1)   /* GPIOB reset */
+#define RCC_AHB1RSTR_GPIOCRST (uint32_t) (1 << 2)   /* GPIOC reset */
+#define RCC_AHB1RSTR_GPIODRST (uint32_t) (1 << 3)   /* GPIOD reset */
+#define RCC_AHB1RSTR_GPIOERST (uint32_t) (1 << 4)   /* GPIOE reset */
+#define RCC_AHB1RSTR_GPIOFRST (uint32_t) (1 << 5)   /* GPIOF reset */
+#define RCC_AHB1RSTR_GPIOGRST (uint32_t) (1 << 6)   /* GPIOG reset */
+#define RCC_AHB1RSTR_GPIOHRST (uint32_t) (1 << 7)   /* GPIOH reset */
+#define RCC_AHB1RSTR_GPIOIRST (uint32_t) (1 << 8)   /* GPIOI reset */
+#define RCC_AHB1RSTR_CRCRST (uint32_t) (1 << 12)    /* CRC reset */
+#define RCC_AHB1RSTR_DMA1RST (uint32_t) (1 << 21)   /* DMA1 reset */
+#define RCC_AHB1RSTR_DMA2RST (uint32_t) (1 << 22)   /* DMA2 reset */
+#define RCC_AHB1RSTR_ETHMACRST (uint32_t) (1 << 25) /* Ethernet MAC reset */
+#define RCC_AHB1RSTR_OTGHSRST (uint32_t) (1 << 29)  /* USB OTG HS reset */
+
+#define RCC_AHB2RSTR_DCMIRST (uint32_t) (1 << 0) /* Camera interface reset */
+#define RCC_AHB2RSTR_CRYPRST (uint32_t) (1 << 4) /* Cyrpto modules reset */
+#define RCC_AHB2RSTR_HASHRST (uint32_t) (1 << 5) /* Hash modules reset */
+#define RCC_AHB2RSTR_RNGRST \
+    (uint32_t) (1 << 6) /* Random number generator reset */
+#define RCC_AHB2RSTR_OTGFSRST (uint32_t) (1 << 7) /* USB OTG FS reset */
+
+#define RCC_AHB3RSTR_FSMCRST \
+    (uint32_t) (1 << 0) /* Flexible static memeory controller reset */
+
+#define RCC_APB1RSTR_TIM2RST (uint32_t) (1 << 0)    /* TIM2 reset */
+#define RCC_APB1RSTR_TIM3RST (uint32_t) (1 << 1)    /* TIM3 reset */
+#define RCC_APB1RSTR_TIM4RST (uint32_t) (1 << 2)    /* TIM4 reset */
+#define RCC_APB1RSTR_TIM5RST (uint32_t) (1 << 3)    /* TIM5 reset */
+#define RCC_APB1RSTR_TIM6RST (uint32_t) (1 << 4)    /* TIM6 reset */
+#define RCC_APB1RSTR_TIM7RST (uint32_t) (1 << 5)    /* TIM7 reset */
+#define RCC_APB1RSTR_TIM12RST (uint32_t) (1 << 6)   /* TIM12 reset */
+#define RCC_APB1RSTR_TIM13RST (uint32_t) (1 << 7)   /* TIM13 reset */
+#define RCC_APB1RSTR_TIM14RST (uint32_t) (1 << 8)   /* TIM14 reset */
+#define RCC_APB1RSTR_WWDGRST (uint32_t) (1 << 11)   /* Window watchdog reset */
+#define RCC_APB1RSTR_SPI2RST (uint32_t) (1 << 14)   /* SPI2 reset */
+#define RCC_APB1RSTR_SPI3RST (uint32_t) (1 << 15)   /* SPI3 reset */
+#define RCC_APB1RSTR_USART2RST (uint32_t) (1 << 17) /* USART2 reset */
+#define RCC_APB1RSTR_USART3RST (uint32_t) (1 << 18) /* USART3 reset */
+#define RCC_APB1RSTR_USART4RST (uint32_t) (1 << 19) /* USART4 reset */
+#define RCC_APB1RSTR_USART5RST (uint32_t) (1 << 20) /* USART5 reset */
+#define RCC_APB1RSTR_I2C1RST (uint32_t) (1 << 21)   /* I2C1 reset */
+#define RCC_APB1RSTR_I2C2RST (uint32_t) (1 << 22)   /* I2C2 reset */
+#define RCC_APB1RSTR_I2C3RST (uint32_t) (1 << 23)   /* I2C3 reset */
+#define RCC_APB1RSTR_CAN1RST (uint32_t) (1 << 25)   /* CAN1 reset */
+#define RCC_APB1RSTR_CAN2RST (uint32_t) (1 << 26)   /* CAN2 reset */
+#define RCC_APB1RSTR_PWRRST (uint32_t) (1 << 28)    /* Power interface reset */
+#define RCC_APB1RSTR_DACRST (uint32_t) (1 << 29)    /* DAC reset */
+
+#define RCC_APB2RSTR_TIM1RST (uint32_t) (1 << 0)   /* TIM1 reset */
+#define RCC_APB2RSTR_TIM8RST (uint32_t) (1 << 1)   /* TIM8 reset */
+#define RCC_APB2RSTR_USART1RST (uint32_t) (1 << 4) /* USART1 reset */
+#define RCC_APB2RSTR_USART6RST (uint32_t) (1 << 5) /* USART6 reset */
+#define RCC_APB2RSTR_ADCRST (uint32_t) (1 << 8)    /* ADC1 reset */
+#define RCC_APB2RSTR_SDIORST (uint32_t) (1 << 11)  /* SDIO reset */
+#define RCC_APB2RSTR_SPI1RST (uint32_t) (1 << 12)  /* SPI1 reset */
+#define RCC_APB2RSTR_SPI5RST (uint32_t) (1 << 20)  /* SPI5 reset */
+#define RCC_APB2RSTR_SYSCFGRST \
+    (uint32_t) (1 << 14) /* System configuration controller reset */
+#define RCC_APB2RSTR_TIM9RST (uint32_t) (1 << 16)  /* TIM9 reset */
+#define RCC_APB2RSTR_TIM10RST (uint32_t) (1 << 17) /* TIM10 reset */
+#define RCC_APB2RSTR_TIM11RST (uint32_t) (1 << 18) /* TIM11 reset */
+#define RCC_APB2RSTR_LTDC (uint32_t) (1 << 26)     /* LTDC reset */
+
+#define RCC_AHB1ENR_GPIOAEN (uint32_t) (1 << 0) /* GPIOA clock enable */
+#define RCC_AHB1ENR_GPIOBEN (uint32_t) (1 << 1) /* GPIOB clock enable */
+#define RCC_AHB1ENR_GPIOCEN (uint32_t) (1 << 2) /* GPIOC clock enable */
+#define RCC_AHB1ENR_GPIODEN (uint32_t) (1 << 3) /* GPIOD clock enable */
+#define RCC_AHB1ENR_GPIOEEN (uint32_t) (1 << 4) /* GPIOE clock enable */
+#define RCC_AHB1ENR_GPIOFEN (uint32_t) (1 << 5) /* GPIOF clock enable */
+#define RCC_AHB1ENR_GPIOGEN (uint32_t) (1 << 6) /* GPIOG clock enable */
+#define RCC_AHB1ENR_GPIOHEN (uint32_t) (1 << 7) /* GPIOH clock enable */
+#define RCC_AHB1ENR_GPIOIEN (uint32_t) (1 << 8) /* GPIOI clock enable */
+#define RCC_AHB1ENR_CRCEN (uint32_t) (1 << 12)  /* CRC clock enable */
+#define RCC_AHB1ENR_BKPSRAMEN \
+    (uint32_t) (1 << 18) /* Backup SRAM clock enable */
+#define RCC_AHB1ENR_CCMDATARAMEN \
+    (uint32_t) (1 << 20)                         /* CCM data RAM clock enable */
+#define RCC_AHB1ENR_DMA1EN (uint32_t) (1 << 21)  /* DMA1 clock enable */
+#define RCC_AHB1ENR_DMA2EN (uint32_t) (1 << 22)  /* DMA2 clock enable */
+#define RCC_AHB1ENR_DMA2DEN (uint32_t) (1 << 23) /* DMA2D clock enable */
+#define RCC_AHB1ENR_ETHMACEN \
+    (uint32_t) (1 << 25) /* Ethernet MAC clock enable */
+#define RCC_AHB1ENR_ETHMACTXEN \
+    (uint32_t) (1 << 26) /* Ethernet MAC TX clock enable */
+#define RCC_AHB1ENR_ETHMACRXEN \
+    (uint32_t) (1 << 27) /* Ethernet MAC RX clock enable */
+#define RCC_AHB1ENR_ETHMACPTPEN \
+    (uint32_t) (1 << 28) /* Ethernet MAC PTP clock enable */
+#define RCC_AHB1ENR_OTGHSEN (uint32_t) (1 << 29) /* USB OTG HS clock enable */
+#define RCC_AHB1ENR_OTGHSULPIEN \
+    (uint32_t) (1 << 30) /* USB OTG HSULPI clock enable */
+
+#define RCC_AHB2ENR_DCMIEN \
+    (uint32_t) (1 << 0) /* Camera interface clock enable */
+#define RCC_AHB2ENR_CRYPEN                                                    \
+    (uint32_t) (1 << 4)                        /* Cyrpto modules clock enable \
+                                                */
+#define RCC_AHB2ENR_HASHEN (uint32_t) (1 << 5) /* Hash modules clock enable */
+#define RCC_AHB2ENR_RNGEN \
+    (uint32_t) (1 << 6) /* Random number generator clock enable */
+#define RCC_AHB2ENR_OTGFSEN (uint32_t) (1 << 7) /* USB OTG FS clock enable */
+
+#define RCC_AHB3ENR_FSMCEN \
+    (uint32_t) (1 << 0) /* Flexible static memeory controller clock enable */
+#define RCC_AHB3ENR_FMCEN (uint32_t) (1 << 0) /* FMC clock enable */
+
+#define RCC_APB1ENR_TIM2EN (uint32_t) (1 << 0)  /* TIM2 clock enable */
+#define RCC_APB1ENR_TIM3EN (uint32_t) (1 << 1)  /* TIM3 clock enable */
+#define RCC_APB1ENR_TIM4EN (uint32_t) (1 << 2)  /* TIM4 clock enable */
+#define RCC_APB1ENR_TIM5EN (uint32_t) (1 << 3)  /* TIM5 clock enable */
+#define RCC_APB1ENR_TIM6EN (uint32_t) (1 << 4)  /* TIM6 clock enable */
+#define RCC_APB1ENR_TIM7EN (uint32_t) (1 << 5)  /* TIM7 clock enable */
+#define RCC_APB1ENR_TIM12EN (uint32_t) (1 << 6) /* TIM12 clock enable */
+#define RCC_APB1ENR_TIM13EN (uint32_t) (1 << 7) /* TIM13 clock enable */
+#define RCC_APB1ENR_TIM14EN (uint32_t) (1 << 8) /* TIM14 clock enable */
+#define RCC_APB1ENR_WWDGEN \
+    (uint32_t) (1 << 11) /* Window watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN (uint32_t) (1 << 14)   /* SPI2 clock enable */
+#define RCC_APB1ENR_SPI3EN (uint32_t) (1 << 15)   /* SPI3 clock enable */
+#define RCC_APB1ENR_USART2EN (uint32_t) (1 << 17) /* USART2 clock enable */
+#define RCC_APB1ENR_USART3EN (uint32_t) (1 << 18) /* USART3 clock enable */
+#define RCC_APB1ENR_USART4EN (uint32_t) (1 << 19) /* USART4 clock enable */
+#define RCC_APB1ENR_USART5EN (uint32_t) (1 << 20) /* USART5 clock enable */
+#define RCC_APB1ENR_I2C1EN (uint32_t) (1 << 21)   /* I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN (uint32_t) (1 << 22)   /* I2C2 clock enable */
+#define RCC_APB1ENR_I2C3EN (uint32_t) (1 << 23)   /* I2C3 clock enable */
+#define RCC_APB1ENR_CAN1EN (uint32_t) (1 << 25)   /* CAN1 clock enable */
+#define RCC_APB1ENR_CAN2EN (uint32_t) (1 << 26)   /* CAN2 clock enable */
+#define RCC_APB1ENR_PWREN \
+    (uint32_t) (1 << 28) /* Power interface clock enable */
+#define RCC_APB1ENR_DACEN (uint32_t) (1 << 29) /* DAC clock enable */
+
+#define RCC_APB2ENR_TIM1EN (uint32_t) (1 << 0)   /* TIM1 clock enable */
+#define RCC_APB2ENR_TIM8EN (uint32_t) (1 << 1)   /* TIM8 clock enable */
+#define RCC_APB2ENR_USART1EN (uint32_t) (1 << 4) /* USART1 clock enable */
+#define RCC_APB2ENR_USART2EN (uint32_t) (1 << 5) /* USART2 clock enable */
+#define RCC_APB2ENR_ADC1EN (uint32_t) (1 << 8)   /* ADC1 clock enable */
+#define RCC_APB2ENR_ADC2EN (uint32_t) (1 << 9)   /* ADC2 clock enable */
+#define RCC_APB2ENR_ADC3EN (uint32_t) (1 << 10)  /* ADC3 clock enable */
+#define RCC_APB2ENR_SDIOEN (uint32_t) (1 << 11)  /* SDIO clock enable */
+#define RCC_APB2ENR_SPI1EN (uint32_t) (1 << 12)  /* SPI1 clock enable */
+#define RCC_APB2ENR_SYSCFGEN \
+    (uint32_t) (1 << 14) /* System configuration controller clock enable */
+#define RCC_APB2ENR_TIM9EN (uint32_t) (1 << 16)  /* TIM9 clock enable */
+#define RCC_APB2ENR_TIM10EN (uint32_t) (1 << 17) /* TIM10 clock enable */
+#define RCC_APB2ENR_TIM11EN (uint32_t) (1 << 18) /* TIM11 clock enable */
+#define RCC_APB2ENR_SPI5EN (uint32_t) (1 << 20)  /* SPI5 clock enable */
+#define RCC_APB2ENR_LTDCEN (uint32_t) (1 << 26)  /* LTDC clock enable */
+
+#define FLASH_ACR_PRFTEN (uint32_t) (1 << 8)     /* Prefetch enable */
+#define FLASH_ACR_ICEN (uint32_t) (1 << 9)       /* Instruction cache enable */
+#define FLASH_ACR_DCEN (uint32_t) (1 << 10)      /* Data cache enable */
+#define FLASH_ACR_ICRST (uint32_t) (1 << 11)     /* Instruction cache reset */
+#define FLASH_ACR_CCRST (uint32_t) (1 << 12)     /* Data cache reset */
+#define FLASH_ACR_LATENCY_M (uint32_t) (7 << 0)  /* Latency mask */
+#define FLASH_ACR_LATENCY(n) (uint32_t) (n << 0) /* Latency - n wait states */
 
 /* TIMx */
-#define TIMx_CR1_CEN                    (uint32_t) (1 << 0)                                     /* TIMx counter enable */
-#define TIMx_CR1_UDIS                   (uint32_t) (1 << 1)                                     /* TIMx update disable */
-#define TIMx_CR1_URS                    (uint32_t) (1 << 2)                                     /* TIMx update request source */
-#define TIMx_CR1_OPM                    (uint32_t) (1 << 3)                                     /* TIMx one-pulse mode */
-#define TIMx_CR1_DIR_DOWN               (uint32_t) (1 << 4)                                     /* TIMx downcounter */
-#define TIMx_CR1_CMS_EDGE               (uint32_t) (0 << 5)                                     /* TIMx center-aligned mode selection - counter up or down depending on DIR bit */
-#define TIMx_CR1_CMS_CM1                (uint32_t) (1 << 5)                                     /* TIMx center-aligned mode selection - up and down, compare flags set down */
-#define TIMx_CR1_CMS_CM2                (uint32_t) (2 << 5)                                     /* TIMx center-aligned mode selection - up and down, compare flags set up */
-#define TIMx_CR1_CMS_CM3                (uint32_t) (3 << 5)                                     /* TIMx center-aligned mode selection - up and down, compare flags set up/down */
-#define TIMx_CR1_ARPE                   (uint32_t) (1 << 7)                                     /* TIMx auto-reload preload enable */
-#define TIMx_CR1_CKD_1                  (uint32_t) (0 << 8)                                     /* TIMx clock division 1 */
-#define TIMx_CR1_CKD_2                  (uint32_t) (1 << 8)                                     /* TIMx clock division 2 */
-#define TIMx_CR1_CKD_4                  (uint32_t) (2 << 8)                                     /* TIMx clock division 4 */
-
-#define TIMx_CR2_CCDS                   (uint32_t) (1 << 3)                                     /* TIMx capture/compare DMA requests send when update event occurs */
-#define TIMx_CR2_MMS_RST                (uint32_t) (0 << 4)                                     /* TIMx master mode - reset */
-#define TIMx_CR2_MMS_EN                 (uint32_t) (1 << 4)                                     /* TIMx master mode - enable */
-#define TIMx_CR2_MMS_UP                 (uint32_t) (2 << 4)                                     /* TIMx master mode - update */
-#define TIMx_CR2_MMS_CMP_PUL            (uint32_t) (3 << 4)                                     /* TIMx master mode - compare pulse */
-#define TIMx_CR2_MMS_CMP_OC1            (uint32_t) (4 << 4)                                     /* TIMx master mode - compare OC1 */
-#define TIMx_CR2_MMS_CMP_OC2            (uint32_t) (5 << 4)                                     /* TIMx master mode - compare OC2 */
-#define TIMx_CR2_MMS_CMP_OC3            (uint32_t) (6 << 4)                                     /* TIMx master mode - compare OC3 */
-#define TIMx_CR2_MMS_CMP_OC4            (uint32_t) (7 << 4)                                     /* TIMx master mode - compare OC4 */
-#define TIMx_CR2_TI1_123                (uint32_t) (1 << 7)                                     /* TIMx CH1, CH2, CH3 pins connected to TI1 */
-
-#define TIMx_DIER_UIE                   (uint32_t) (1 << 0)                                     /* TIMx update interrupt enable */
-#define TIMx_DIER_CC1IE                 (uint32_t) (1 << 1)                                     /* TIMx CC1 interrupt enable */
-#define TIMx_DIER_CC2IE                 (uint32_t) (1 << 2)                                     /* TIMx CC2 interrupt enable */
-#define TIMx_DIER_CC3IE                 (uint32_t) (1 << 3)                                     /* TIMx CC3 interrupt enable */
-#define TIMx_DIER_CC4IE                 (uint32_t) (1 << 4)                                     /* TIMx CC4 interrupt enable */
-#define TIMx_DIER_TIE                   (uint32_t) (1 << 6)                                     /* TIMx trigger interrupt enable */
-#define TIMx_DIER_UDE                   (uint32_t) (1 << 8)                                     /* TIMx update DMA request enable */
-#define TIMx_DIER_CC1DE                 (uint32_t) (1 << 9)                                     /* TIMx CC1 DMA request enable */
-#define TIMx_DIER_CC2DE                 (uint32_t) (1 << 10)                                    /* TIMx CC2 DMA request enable */
-#define TIMx_DIER_CC3DE                 (uint32_t) (1 << 11)                                    /* TIMx CC3 DMA request enable */
-#define TIMx_DIER_CC4DE                 (uint32_t) (1 << 12)                                    /* TIMx CC4 DMA request enable */
-#define TIMx_DIER_TDE                   (uint32_t) (1 << 14)                                    /* TIMx trigger DMA request enable */
+#define TIMx_CR1_CEN (uint32_t) (1 << 0)      /* TIMx counter enable */
+#define TIMx_CR1_UDIS (uint32_t) (1 << 1)     /* TIMx update disable */
+#define TIMx_CR1_URS (uint32_t) (1 << 2)      /* TIMx update request source */
+#define TIMx_CR1_OPM (uint32_t) (1 << 3)      /* TIMx one-pulse mode */
+#define TIMx_CR1_DIR_DOWN (uint32_t) (1 << 4) /* TIMx downcounter */
+#define TIMx_CR1_CMS_EDGE                                                     \
+    (uint32_t) (0 << 5) /* TIMx center-aligned mode selection - counter up or \
+                           down depending on DIR bit */
+#define TIMx_CR1_CMS_CM1                                                     \
+    (uint32_t) (1 << 5) /* TIMx center-aligned mode selection - up and down, \
+                           compare flags set down */
+#define TIMx_CR1_CMS_CM2                                                     \
+    (uint32_t) (2 << 5) /* TIMx center-aligned mode selection - up and down, \
+                           compare flags set up */
+#define TIMx_CR1_CMS_CM3                                                     \
+    (uint32_t) (3 << 5) /* TIMx center-aligned mode selection - up and down, \
+                           compare flags set up/down */
+#define TIMx_CR1_ARPE                                                         \
+    (uint32_t) (1 << 7)                    /* TIMx auto-reload preload enable \
+                                            */
+#define TIMx_CR1_CKD_1 (uint32_t) (0 << 8) /* TIMx clock division 1 */
+#define TIMx_CR1_CKD_2 (uint32_t) (1 << 8) /* TIMx clock division 2 */
+#define TIMx_CR1_CKD_4 (uint32_t) (2 << 8) /* TIMx clock division 4 */
+
+#define TIMx_CR2_CCDS                                                         \
+    (uint32_t) (1 << 3) /* TIMx capture/compare DMA requests send when update \
+                           event occurs */
+#define TIMx_CR2_MMS_RST (uint32_t) (0 << 4) /* TIMx master mode - reset */
+#define TIMx_CR2_MMS_EN (uint32_t) (1 << 4)  /* TIMx master mode - enable */
+#define TIMx_CR2_MMS_UP (uint32_t) (2 << 4)  /* TIMx master mode - update */
+#define TIMx_CR2_MMS_CMP_PUL \
+    (uint32_t) (3 << 4) /* TIMx master mode - compare pulse */
+#define TIMx_CR2_MMS_CMP_OC1 \
+    (uint32_t) (4 << 4) /* TIMx master mode - compare OC1 */
+#define TIMx_CR2_MMS_CMP_OC2 \
+    (uint32_t) (5 << 4) /* TIMx master mode - compare OC2 */
+#define TIMx_CR2_MMS_CMP_OC3 \
+    (uint32_t) (6 << 4) /* TIMx master mode - compare OC3 */
+#define TIMx_CR2_MMS_CMP_OC4 \
+    (uint32_t) (7 << 4) /* TIMx master mode - compare OC4 */
+#define TIMx_CR2_TI1_123 \
+    (uint32_t) (1 << 7) /* TIMx CH1, CH2, CH3 pins connected to TI1 */
+
+#define TIMx_DIER_UIE (uint32_t) (1 << 0)   /* TIMx update interrupt enable */
+#define TIMx_DIER_CC1IE (uint32_t) (1 << 1) /* TIMx CC1 interrupt enable */
+#define TIMx_DIER_CC2IE (uint32_t) (1 << 2) /* TIMx CC2 interrupt enable */
+#define TIMx_DIER_CC3IE (uint32_t) (1 << 3) /* TIMx CC3 interrupt enable */
+#define TIMx_DIER_CC4IE (uint32_t) (1 << 4) /* TIMx CC4 interrupt enable */
+#define TIMx_DIER_TIE (uint32_t) (1 << 6)   /* TIMx trigger interrupt enable */
+#define TIMx_DIER_UDE (uint32_t) (1 << 8)   /* TIMx update DMA request enable */
+#define TIMx_DIER_CC1DE (uint32_t) (1 << 9) /* TIMx CC1 DMA request enable */
+#define TIMx_DIER_CC2DE (uint32_t) (1 << 10) /* TIMx CC2 DMA request enable */
+#define TIMx_DIER_CC3DE (uint32_t) (1 << 11) /* TIMx CC3 DMA request enable */
+#define TIMx_DIER_CC4DE (uint32_t) (1 << 12) /* TIMx CC4 DMA request enable */
+#define TIMx_DIER_TDE                                       \
+    (uint32_t) (1 << 14) /* TIMx trigger DMA request enable \
+                          */
 
 /* SPI */
-#define SPI_CR1_CPHA                    (uint32_t) (1 << 0)                                     /* SPI clock phase */
-#define SPI_CR1_CPOL                    (uint32_t) (1 << 1)                                     /* SPI clock polarity */
-#define SPI_CR1_MSTR                    (uint32_t) (1 << 2)                                     /* SPI master selection */
-#define SPI_CR1_BR_2                    (uint32_t) (0 << 3)                                     /* SPI baud rate = fPCLK/2 */
-#define SPI_CR1_BR_4                    (uint32_t) (1 << 3)                                     /* SPI baud rate = fPCLK/4 */
-#define SPI_CR1_BR_8                    (uint32_t) (2 << 3)                                     /* SPI baud rate = fPCLK/8 */
-#define SPI_CR1_BR_16                   (uint32_t) (3 << 3)                                     /* SPI baud rate = fPCLK/16 */
-#define SPI_CR1_BR_32                   (uint32_t) (4 << 3)                                     /* SPI baud rate = fPCLK/32 */
-#define SPI_CR1_BR_64                   (uint32_t) (5 << 3)                                     /* SPI baud rate = fPCLK/64 */
-#define SPI_CR1_BR_128                  (uint32_t) (6 << 3)                                     /* SPI baud rate = fPCLK/128 */
-#define SPI_CR1_BR_256                  (uint32_t) (7 << 3)                                     /* SPI baud rate = fPCLK/256 */
-#define SPI_CR1_SPE                     (uint32_t) (1 << 6)                                     /* SPI enable */
-#define SPI_CR1_LSBFIRST                (uint32_t) (1 << 7)                                     /* SPI LSB transmitted first */
-#define SPI_CR1_SSI                     (uint32_t) (1 << 8)                                     /* SPI internal slave select */
-#define SPI_CR1_SSM                     (uint32_t) (1 << 9)                                     /* SPI software slave management */
-#define SPI_CR1_DFF                     (uint32_t) (1 << 11)                                    /* SPI data frame format (0 = 8bit, 1 = 16bit) */
-#define SPI_SR_RXNE                     (uint32_t) (1 << 0)                                     /* SPI receive not empty */
-#define SPI_SR_TXNE                     (uint32_t) (1 << 1)                                     /* SPI transmit not empty */
-#define SPI_SR_CHSIDE                   (uint32_t) (1 << 2)                                     /* SPI channel side */
-#define SPI_SR_UDR                      (uint32_t) (1 << 3)                                     /* SPI underrun flag */
-#define SPI_SR_CRCERR                   (uint32_t) (1 << 4)                                     /* SPI CRC error flag */
-#define SPI_SR_MODF                     (uint32_t) (1 << 5)                                     /* SPI mode fault */
-#define SPI_SR_OVR                      (uint32_t) (1 << 6)                                     /* SPI overrun flag */
-#define SPI_SR_BSY                      (uint32_t) (1 << 7)                                     /* SPI busy flag */
-#define SPI_SR_TIRFE                    (uint32_t) (1 << 8)                                     /* SPI TI frame format error */
+#define SPI_CR1_CPHA (uint32_t) (1 << 0)     /* SPI clock phase */
+#define SPI_CR1_CPOL (uint32_t) (1 << 1)     /* SPI clock polarity */
+#define SPI_CR1_MSTR (uint32_t) (1 << 2)     /* SPI master selection */
+#define SPI_CR1_BR_2 (uint32_t) (0 << 3)     /* SPI baud rate = fPCLK/2 */
+#define SPI_CR1_BR_4 (uint32_t) (1 << 3)     /* SPI baud rate = fPCLK/4 */
+#define SPI_CR1_BR_8 (uint32_t) (2 << 3)     /* SPI baud rate = fPCLK/8 */
+#define SPI_CR1_BR_16 (uint32_t) (3 << 3)    /* SPI baud rate = fPCLK/16 */
+#define SPI_CR1_BR_32 (uint32_t) (4 << 3)    /* SPI baud rate = fPCLK/32 */
+#define SPI_CR1_BR_64 (uint32_t) (5 << 3)    /* SPI baud rate = fPCLK/64 */
+#define SPI_CR1_BR_128 (uint32_t) (6 << 3)   /* SPI baud rate = fPCLK/128 */
+#define SPI_CR1_BR_256 (uint32_t) (7 << 3)   /* SPI baud rate = fPCLK/256 */
+#define SPI_CR1_SPE (uint32_t) (1 << 6)      /* SPI enable */
+#define SPI_CR1_LSBFIRST (uint32_t) (1 << 7) /* SPI LSB transmitted first */
+#define SPI_CR1_SSI (uint32_t) (1 << 8)      /* SPI internal slave select */
+#define SPI_CR1_SSM (uint32_t) (1 << 9)      /* SPI software slave management */
+#define SPI_CR1_DFF \
+    (uint32_t) (1 << 11) /* SPI data frame format (0 = 8bit, 1 = 16bit) */
+#define SPI_SR_RXNE (uint32_t) (1 << 0)   /* SPI receive not empty */
+#define SPI_SR_TXNE (uint32_t) (1 << 1)   /* SPI transmit not empty */
+#define SPI_SR_CHSIDE (uint32_t) (1 << 2) /* SPI channel side */
+#define SPI_SR_UDR (uint32_t) (1 << 3)    /* SPI underrun flag */
+#define SPI_SR_CRCERR (uint32_t) (1 << 4) /* SPI CRC error flag */
+#define SPI_SR_MODF (uint32_t) (1 << 5)   /* SPI mode fault */
+#define SPI_SR_OVR (uint32_t) (1 << 6)    /* SPI overrun flag */
+#define SPI_SR_BSY (uint32_t) (1 << 7)    /* SPI busy flag */
+#define SPI_SR_TIRFE (uint32_t) (1 << 8)  /* SPI TI frame format error */
 
 /* I2C */
-#define I2C_CR1_PE                      (uint32_t) (1 << 0)                                     /* I2C peripheral enable */
-#define I2C_CR1_SMBUS                   (uint32_t) (1 << 1)                                     /* I2C SMBus mode */
-#define I2C_CR1_SMBTYPE                 (uint32_t) (1 << 3)                                     /* I2C SMBus type (0=Device, 1=Host) */
-#define I2C_CR1_ENARP                   (uint32_t) (1 << 4)                                     /* I2C enable ARP */
-#define I2C_CR1_ENPEC                   (uint32_t) (1 << 5)                                     /* I2C enable PEC */
-#define I2C_CR1_ENGC                    (uint32_t) (1 << 6)                                     /* I2C enable general call */
-#define I2C_CR1_NOSTRETCH               (uint32_t) (1 << 7)                                     /* I2C clock stretching disable */
-#define I2C_CR1_START                   (uint32_t) (1 << 8)                                     /* I2C START generation */
-#define I2C_CR1_STOP                    (uint32_t) (1 << 9)                                     /* I2C STOP generation */
-#define I2C_CR1_ACK                     (uint32_t) (1 << 10)                                    /* I2C ACK enable */
-#define I2C_CR1_POS                     (uint32_t) (1 << 11)                                    /* I2C ACK/PEC position */
-#define I2C_CR1_PEC                     (uint32_t) (1 << 12)                                    /* I2C packet error checking */
-#define I2C_CR1_ALERT                   (uint32_t) (1 << 13)                                    /* I2C SMBus alert */
-#define I2C_CR1_SWRST                   (uint32_t) (1 << 15)                                    /* I2C software reset */
-
-#define I2C_CR2_FREQ_ALL                (uint32_t) (0x003F)                                     /* FREQ[5:0] bits */
-#define I2C_CR2_FREQ(n)                 (uint32_t) (n << 0)                                     /* I2C clock frequency */
-#define I2C_CR2_ITERREN                 (uint32_t) (1 << 8)                                     /* I2C error interrupt enable */
-#define I2C_CR2_ITEVTEN                 (uint32_t) (1 << 9)                                     /* I2C event interrupt enable */
-#define I2C_CR2_ITBUFEN                 (uint32_t) (1 << 10)                                    /* I2C buffer interrupt enable */
-#define I2C_CR2_DMAEN                   (uint32_t) (1 << 11)                                    /* I2C DMA requests enable */
-#define I2C_CR2_LAST                    (uint32_t) (1 << 12)                                    /* I2C DMA last transfer */
-
-#define I2C_OAR1_ADD(n)                 (uint16_t) (1 << n)                                     /* I2C interface address */
-#define I2C_OAR1_ADD10(n)               (uint32_t) (n << 0)                                     /* I2C interface address (10-bit) */
-#define I2C_OAR1_ADD7(n)                (uint32_t) (n << 1)                                     /* I2C interface address (7-bit) */
-#define I2C_OAR1_ADDMODE                (uint32_t) (1 << 15)                                    /* I2C interface address mode (1=10-bit) */
-
-#define I2C_OAR2_ENDUAL                 (uint32_t) (1 << 0)                                     /* I2C dual address mode enable */
-#define I2C_OAR2_ADD2(n)                (uint32_t) (n << 1)                                     /* I2C interface address 2 (7-bit) */
-
-#define I2C_SR1_SB                      (uint32_t) (1 << 0)                                     /* I2C start bit generated */
-#define I2C_SR1_ADDR                    (uint32_t) (1 << 1)                                     /* I2C address sent/matched */
-#define I2C_SR1_BTF                     (uint32_t) (1 << 2)                                     /* I2C byte transfer finished */
-#define I2C_SR1_ADD10                   (uint32_t) (1 << 3)                                     /* I2C 10-bit header sent */
-#define I2C_SR1_STOPF                   (uint32_t) (1 << 4)                                     /* I2C stop detection */
-#define I2C_SR1_RXNE                    (uint32_t) (1 << 6)                                     /* I2C DR not empty */
-#define I2C_SR1_TXE                     (uint32_t) (1 << 7)                                     /* I2C DR empty */
-#define I2C_SR1_BERR                    (uint32_t) (1 << 8)                                     /* I2C bus error */
-#define I2C_SR1_ARLO                    (uint32_t) (1 << 9)                                     /* I2C attribution lost */
-#define I2C_SR1_AF                      (uint32_t) (1 << 10)                                    /* I2C acknowledge failure */
-#define I2C_SR1_OVR                     (uint32_t) (1 << 11)                                    /* I2C overrun/underrun */
-#define I2C_SR1_PECERR                  (uint32_t) (1 << 12)                                    /* I2C PEC error in reception */
-#define I2C_SR1_TIMEOUT                 (uint32_t) (1 << 14)                                    /* I2C timeout or tlow error */
-#define I2C_SR1_SMBALERT                (uint32_t) (1 << 15)                                    /* I2C SMBus alert */
-
-#define I2C_SR2_MSL                     (uint32_t) (1 << 0)                                     /* I2C master/slave */
-#define I2C_SR2_BUSY                    (uint32_t) (1 << 1)                                     /* I2C bus busy */
-#define I2C_SR2_TRA                     (uint32_t) (1 << 2)                                     /* I2C transmitter/receiver */
-#define I2C_SR2_GENCALL                 (uint32_t) (1 << 4)                                     /* I2C general call address */
-#define I2C_SR2_SMBDEFAULT              (uint32_t) (1 << 5)                                     /* I2C SMBus device default address */
-#define I2C_SR2_SMBHOST                 (uint32_t) (1 << 6)                                     /* I2C SMBus host header */
-#define I2C_SR2_DUALF                   (uint32_t) (1 << 7)                                     /* I2C dual flag */
-#define I2C_SR2_PEC(r)                  (uint32_t) (r >> 8)                                     /* I2C packet error checking register */
-
-#define I2C_CCR_CCR(n)                  (uint32_t) (n & 0x0FFF)                                 /* I2C clock control register */
-#define I2C_CCR_DUTY                    (uint32_t) (1 << 14)                                    /* I2C fast mode duty cycle */
-#define I2C_CCR_FS                      (uint32_t) (1 << 15)                                    /* I2C master mode selection */
+#define I2C_CR1_PE (uint32_t) (1 << 0)    /* I2C peripheral enable */
+#define I2C_CR1_SMBUS (uint32_t) (1 << 1) /* I2C SMBus mode */
+#define I2C_CR1_SMBTYPE \
+    (uint32_t) (1 << 3) /* I2C SMBus type (0=Device, 1=Host) */
+#define I2C_CR1_ENARP (uint32_t) (1 << 4) /* I2C enable ARP */
+#define I2C_CR1_ENPEC (uint32_t) (1 << 5) /* I2C enable PEC */
+#define I2C_CR1_ENGC (uint32_t) (1 << 6)  /* I2C enable general call */
+#define I2C_CR1_NOSTRETCH                                                  \
+    (uint32_t) (1 << 7)                    /* I2C clock stretching disable \
+                                            */
+#define I2C_CR1_START (uint32_t) (1 << 8)  /* I2C START generation */
+#define I2C_CR1_STOP (uint32_t) (1 << 9)   /* I2C STOP generation */
+#define I2C_CR1_ACK (uint32_t) (1 << 10)   /* I2C ACK enable */
+#define I2C_CR1_POS (uint32_t) (1 << 11)   /* I2C ACK/PEC position */
+#define I2C_CR1_PEC (uint32_t) (1 << 12)   /* I2C packet error checking */
+#define I2C_CR1_ALERT (uint32_t) (1 << 13) /* I2C SMBus alert */
+#define I2C_CR1_SWRST (uint32_t) (1 << 15) /* I2C software reset */
+
+#define I2C_CR2_FREQ_ALL (uint32_t) (0x003F) /* FREQ[5:0] bits */
+#define I2C_CR2_FREQ(n) (uint32_t) (n << 0)  /* I2C clock frequency */
+#define I2C_CR2_ITERREN (uint32_t) (1 << 8)  /* I2C error interrupt enable */
+#define I2C_CR2_ITEVTEN (uint32_t) (1 << 9)  /* I2C event interrupt enable */
+#define I2C_CR2_ITBUFEN (uint32_t) (1 << 10) /* I2C buffer interrupt enable */
+#define I2C_CR2_DMAEN (uint32_t) (1 << 11)   /* I2C DMA requests enable */
+#define I2C_CR2_LAST (uint32_t) (1 << 12)    /* I2C DMA last transfer */
+
+#define I2C_OAR1_ADD(n) (uint16_t) (1 << n) /* I2C interface address */
+#define I2C_OAR1_ADD10(n) \
+    (uint32_t) (n << 0) /* I2C interface address (10-bit) */
+#define I2C_OAR1_ADD7(n)                                 \
+    (uint32_t) (n << 1) /* I2C interface address (7-bit) \
+                         */
+#define I2C_OAR1_ADDMODE \
+    (uint32_t) (1 << 15) /* I2C interface address mode (1=10-bit) */
+
+#define I2C_OAR2_ENDUAL (uint32_t) (1 << 0) /* I2C dual address mode enable */
+#define I2C_OAR2_ADD2(n) \
+    (uint32_t) (n << 1) /* I2C interface address 2 (7-bit) */
+
+#define I2C_SR1_SB (uint32_t) (1 << 0)        /* I2C start bit generated */
+#define I2C_SR1_ADDR (uint32_t) (1 << 1)      /* I2C address sent/matched */
+#define I2C_SR1_BTF (uint32_t) (1 << 2)       /* I2C byte transfer finished */
+#define I2C_SR1_ADD10 (uint32_t) (1 << 3)     /* I2C 10-bit header sent */
+#define I2C_SR1_STOPF (uint32_t) (1 << 4)     /* I2C stop detection */
+#define I2C_SR1_RXNE (uint32_t) (1 << 6)      /* I2C DR not empty */
+#define I2C_SR1_TXE (uint32_t) (1 << 7)       /* I2C DR empty */
+#define I2C_SR1_BERR (uint32_t) (1 << 8)      /* I2C bus error */
+#define I2C_SR1_ARLO (uint32_t) (1 << 9)      /* I2C attribution lost */
+#define I2C_SR1_AF (uint32_t) (1 << 10)       /* I2C acknowledge failure */
+#define I2C_SR1_OVR (uint32_t) (1 << 11)      /* I2C overrun/underrun */
+#define I2C_SR1_PECERR (uint32_t) (1 << 12)   /* I2C PEC error in reception */
+#define I2C_SR1_TIMEOUT (uint32_t) (1 << 14)  /* I2C timeout or tlow error */
+#define I2C_SR1_SMBALERT (uint32_t) (1 << 15) /* I2C SMBus alert */
+
+#define I2C_SR2_MSL (uint32_t) (1 << 0)     /* I2C master/slave */
+#define I2C_SR2_BUSY (uint32_t) (1 << 1)    /* I2C bus busy */
+#define I2C_SR2_TRA (uint32_t) (1 << 2)     /* I2C transmitter/receiver */
+#define I2C_SR2_GENCALL (uint32_t) (1 << 4) /* I2C general call address */
+#define I2C_SR2_SMBDEFAULT \
+    (uint32_t) (1 << 5) /* I2C SMBus device default address */
+#define I2C_SR2_SMBHOST (uint32_t) (1 << 6) /* I2C SMBus host header */
+#define I2C_SR2_DUALF (uint32_t) (1 << 7)   /* I2C dual flag */
+#define I2C_SR2_PEC(r) \
+    (uint32_t) (r >> 8) /* I2C packet error checking register */
+
+#define I2C_CCR_CCR(n)                                                  \
+    (uint32_t) (n & 0x0FFF)               /* I2C clock control register \
+                                           */
+#define I2C_CCR_DUTY (uint32_t) (1 << 14) /* I2C fast mode duty cycle */
+#define I2C_CCR_FS (uint32_t) (1 << 15)   /* I2C master mode selection */
 
 /* USART */
-#define USART_SR_TC                     (uint32_t) (1 << 6)                                     /* USART Transmission Complete */
-#define USART_SR_RXNE                   (uint32_t) (1 << 5)                                     /* USART Read data register not empty */
+#define USART_SR_TC (uint32_t) (1 << 6) /* USART Transmission Complete */
+#define USART_SR_RXNE \
+    (uint32_t) (1 << 5) /* USART Read data register not empty */
 
 /* USART_CR1 */
-#define USART_CR1_OVER8                 (uint32_t) (1 << 15)                                    /* Oversampling mode */
-#define USART_CR1_UE                    (uint32_t) (1 << 13)                                    /* USART Enable */
-#define USART_CR1_M9                    (uint32_t) (1 << 12)                                    /* World length 1: 9 bits, 0: 8bits */
-#define USART_CR1_WAKE                  (uint32_t) (1 << 11)                                    /* Wakeup method */
-#define USART_CR1_PCE                   (uint32_t) (1 << 10)                                    /* PCE Parity control enable */
-#define USART_CR1_PS                    (uint32_t) (1 << 9)                                     /* Parity selection */
-#define USART_CR1_PEIE                  (uint32_t) (1 << 8)                                     /* PE Interrupt enable */
-#define USART_CR1_TXEIE                 (uint32_t) (1 << 7)                                     /* TXE interrupt enable */
-#define USART_CR1_TCIE                  (uint32_t) (1 << 6)                                     /* Transmission complete interrupt enable */
-#define USART_CR1_RXNEIE                (uint32_t) (1 << 5)                                     /* RXNE Interrupt Enable */
-#define USART_CR1_IDLEIE                (uint32_t) (1 << 4)                                     /* IDEL INterrupt Enable */
-#define USART_CR1_TE                    (uint32_t) (1 << 3)                                     /* USART Transmit Enable */
-#define USART_CR1_RE                    (uint32_t) (1 << 2)                                     /* USART Receive Enable */
-#define USART_CR1_RWU                   (uint32_t) (1 << 1)
-#define USART_CR1_SBK                   (uint32_t) (1 << 0)                                     /* Send break characters */
-
-#define USART_CR3_DMAR_EN               (uint32_t) (1 << 6)                                     /* USART DMA Receive Enable */
-#define USART_CR3_DMAT_EN               (uint32_t) (1 << 7)                                     /* USART DMA Transmit Enable */
+#define USART_CR1_OVER8 (uint32_t) (1 << 15) /* Oversampling mode */
+#define USART_CR1_UE (uint32_t) (1 << 13)    /* USART Enable */
+#define USART_CR1_M9                                         \
+    (uint32_t) (1 << 12) /* World length 1: 9 bits, 0: 8bits \
+                          */
+#define USART_CR1_WAKE (uint32_t) (1 << 11) /* Wakeup method */
+#define USART_CR1_PCE (uint32_t) (1 << 10)  /* PCE Parity control enable */
+#define USART_CR1_PS (uint32_t) (1 << 9)    /* Parity selection */
+#define USART_CR1_PEIE (uint32_t) (1 << 8)  /* PE Interrupt enable */
+#define USART_CR1_TXEIE (uint32_t) (1 << 7) /* TXE interrupt enable */
+#define USART_CR1_TCIE \
+    (uint32_t) (1 << 6) /* Transmission complete interrupt enable */
+#define USART_CR1_RXNEIE (uint32_t) (1 << 5) /* RXNE Interrupt Enable */
+#define USART_CR1_IDLEIE (uint32_t) (1 << 4) /* IDEL INterrupt Enable */
+#define USART_CR1_TE (uint32_t) (1 << 3)     /* USART Transmit Enable */
+#define USART_CR1_RE (uint32_t) (1 << 2)     /* USART Receive Enable */
+#define USART_CR1_RWU (uint32_t) (1 << 1)
+#define USART_CR1_SBK (uint32_t) (1 << 0) /* Send break characters */
+
+#define USART_CR3_DMAR_EN (uint32_t) (1 << 6) /* USART DMA Receive Enable */
+#define USART_CR3_DMAT_EN (uint32_t) (1 << 7) /* USART DMA Transmit Enable */
 
 /* GPIO */
-#define GPIOA                           (uint8_t)  (0)                                          /* GPIO Port A */
-#define GPIOB                           (uint8_t)  (1)                                          /* GPIO Port B */
-#define GPIOC                           (uint8_t)  (2)                                          /* GPIO Port C */
-#define GPIOD                           (uint8_t)  (3)                                          /* GPIO Port D */
-#define GPIOE                           (uint8_t)  (4)                                          /* GPIO Port E */
-#define GPIOF                           (uint8_t)  (5)                                          /* GPIO Port F */
-#define GPIOG                           (uint8_t)  (6)                                          /* GPIO Port G */
-#define GPIOH                           (uint8_t)  (7)                                          /* GPIO Port H */
-#define GPIOI                           (uint8_t)  (8)                                          /* GPIO Port I */
-
-#define GPIO_MODER_PIN(n)               (uint32_t) (2*n)                                        /* Pin bitshift */
-#define GPIO_MODER_M(n)                 (uint32_t) (0x3 << 2*n)                                 /* Pin mask */
-#define GPIO_MODER_IN                   (uint32_t) (0x0)                                        /* Input mode */
-#define GPIO_MODER_OUT                  (uint32_t) (0x1)                                        /* Output mode */
-#define GPIO_MODER_ALT                  (uint32_t) (0x2)                                        /* Alternative function mode */
-#define GPIO_MODER_ANA                  (uint32_t) (0x3)                                        /* Analog mode */
-
-#define GPIO_OTYPER_PIN(n)              (uint32_t) (n)                                          /* Pin bitshift */
-#define GPIO_OTYPER_M(n)                (uint32_t) (1 << n)                                     /* Pin mask */
-#define GPIO_OTYPER_PP                  (uint32_t) (0x0)                                        /* Output push-pull */
-#define GPIO_OTYPER_OD                  (uint32_t) (0x1)                                        /* Output open drain */
-
-#define GPIO_OSPEEDR_PIN(n)             (uint32_t) (2*n)                                        /* Pin bitshift */
-#define GPIO_OSPEEDR_M(n)               (uint32_t) (0x3 << (2*n))                               /* Pin mask */
-#define GPIO_OSPEEDR_2M                 (uint32_t) (0x0)                                        /* Output speed 2MHz */
-#define GPIO_OSPEEDR_25M                (uint32_t) (0x1)                                        /* Output speed 25MHz */
-#define GPIO_OSPEEDR_50M                (uint32_t) (0x2)                                        /* Output speed 50MHz */
-#define GPIO_OSPEEDR_100M               (uint32_t) (0x3)                                        /* Output speed 100MHz */
-
-#define GPIO_PUPDR_PIN(n)               (uint32_t) (2*n)                                        /* Pin bitshift */
-#define GPIO_PUPDR_M(n)                 (uint32_t) (0x3 << (2*n))                               /* Pin mask */
-#define GPIO_PUPDR_NONE                 (uint32_t) (0x0)                                        /* Port no pull-up, pull-down */
-#define GPIO_PUPDR_UP                   (uint32_t) (0x1)                                        /* Port pull-up */
-#define GPIO_PUPDR_DOWN                 (uint32_t) (0x2)                                        /* Port pull-down */
-
-#define GPIO_IDR_PIN(n)                 (uint32_t) (1 << n)                                     /* Input for pin n */
-
-#define GPIO_ODR_PIN(n)                 (uint32_t) (1 << n)                                     /* Output for pin n */
-
-#define GPIO_BSRR_BS(n)                 (uint32_t) (1 << n)                                     /* Set pin n */
-#define GPIO_BSRR_BR(n)                 (uint32_t) (1 << (n+16))                                /* Reset pin n */
-
-#define GPIO_AFRL_PIN(n)                (uint32_t) (4*n)                                        /* Pin bitshift */
-#define GPIO_AFRL_M(n)                  (uint32_t) (0xF << (4*n))                               /* Pin mask */
-#define GPIO_AFRH_PIN(n)                (uint32_t) (4*(n-8))                                    /* Pin bitshift */
-#define GPIO_AFRH_M(n)                  (uint32_t) (0xF << (4*(n-8)))                           /* Pin mask */
+#define GPIOA (uint8_t) (0) /* GPIO Port A */
+#define GPIOB (uint8_t) (1) /* GPIO Port B */
+#define GPIOC (uint8_t) (2) /* GPIO Port C */
+#define GPIOD (uint8_t) (3) /* GPIO Port D */
+#define GPIOE (uint8_t) (4) /* GPIO Port E */
+#define GPIOF (uint8_t) (5) /* GPIO Port F */
+#define GPIOG (uint8_t) (6) /* GPIO Port G */
+#define GPIOH (uint8_t) (7) /* GPIO Port H */
+#define GPIOI (uint8_t) (8) /* GPIO Port I */
+
+#define GPIO_MODER_PIN(n) (uint32_t) (2 * n)      /* Pin bitshift */
+#define GPIO_MODER_M(n) (uint32_t) (0x3 << 2 * n) /* Pin mask */
+#define GPIO_MODER_IN (uint32_t) (0x0)            /* Input mode */
+#define GPIO_MODER_OUT (uint32_t) (0x1)           /* Output mode */
+#define GPIO_MODER_ALT (uint32_t) (0x2) /* Alternative function mode */
+#define GPIO_MODER_ANA (uint32_t) (0x3) /* Analog mode */
+
+#define GPIO_OTYPER_PIN(n) (uint32_t) (n)    /* Pin bitshift */
+#define GPIO_OTYPER_M(n) (uint32_t) (1 << n) /* Pin mask */
+#define GPIO_OTYPER_PP (uint32_t) (0x0)      /* Output push-pull */
+#define GPIO_OTYPER_OD (uint32_t) (0x1)      /* Output open drain */
+
+#define GPIO_OSPEEDR_PIN(n) (uint32_t) (2 * n)        /* Pin bitshift */
+#define GPIO_OSPEEDR_M(n) (uint32_t) (0x3 << (2 * n)) /* Pin mask */
+#define GPIO_OSPEEDR_2M (uint32_t) (0x0)              /* Output speed 2MHz */
+#define GPIO_OSPEEDR_25M (uint32_t) (0x1)             /* Output speed 25MHz */
+#define GPIO_OSPEEDR_50M (uint32_t) (0x2)             /* Output speed 50MHz */
+#define GPIO_OSPEEDR_100M (uint32_t) (0x3)            /* Output speed 100MHz */
+
+#define GPIO_PUPDR_PIN(n) (uint32_t) (2 * n)        /* Pin bitshift */
+#define GPIO_PUPDR_M(n) (uint32_t) (0x3 << (2 * n)) /* Pin mask */
+#define GPIO_PUPDR_NONE (uint32_t) (0x0) /* Port no pull-up, pull-down */
+#define GPIO_PUPDR_UP (uint32_t) (0x1)   /* Port pull-up */
+#define GPIO_PUPDR_DOWN (uint32_t) (0x2) /* Port pull-down */
+
+#define GPIO_IDR_PIN(n) (uint32_t) (1 << n) /* Input for pin n */
+
+#define GPIO_ODR_PIN(n) (uint32_t) (1 << n) /* Output for pin n */
+
+#define GPIO_BSRR_BS(n) (uint32_t) (1 << n)        /* Set pin n */
+#define GPIO_BSRR_BR(n) (uint32_t) (1 << (n + 16)) /* Reset pin n */
+
+#define GPIO_AFRL_PIN(n) (uint32_t) (4 * n)              /* Pin bitshift */
+#define GPIO_AFRL_M(n) (uint32_t) (0xF << (4 * n))       /* Pin mask */
+#define GPIO_AFRH_PIN(n) (uint32_t) (4 * (n - 8))        /* Pin bitshift */
+#define GPIO_AFRH_M(n) (uint32_t) (0xF << (4 * (n - 8))) /* Pin mask */
 
 /* DMA */
-#define DMA_LISR_TCIF2                  (uint32_t) (1 << 21)                                    /* DMA stream 2 transfer complete flag */
-#define DMA_HISR_TCIF7                  (uint32_t) (1 << 27)                                    /* DMA stream 7 transfer complete flag */
-#define DMA_LIFCR_CTCIF2                (uint32_t) (1 << 21)                                    /* DMA clear stream 2 transfer complete flag */
-#define DMA_HIFCR_CTCIF7                (uint32_t) (1 << 27)                                    /* DMA clear stream 7 transfer complete flag */
-
-#define DMA_SxCR_EN                     (uint32_t) (1 << 0)                                     /* DMA stream enable */
-#define DMA_SxCR_DMEIE                  (uint32_t) (1 << 1)                                     /* DMA stream direct mode error interrupt enable */
-#define DMA_SxCR_TEIE                   (uint32_t) (1 << 2)                                     /* DMA stream transmit error interrupt enable */
-#define DMA_SxCR_HTIE                   (uint32_t) (1 << 3)                                     /* DMA stream half transfer interrupt enable */
-#define DMA_SxCR_TCIE                   (uint32_t) (1 << 4)                                     /* DMA stream transfer complete interrupt enable */
-#define DMA_SxCR_PFCTRL                 (uint32_t) (1 << 5)                                     /* DMA stream peripheral flow control */
-#define DMA_SxCR_DIR_PM                 (uint32_t) (0 << 6)                                     /* DMA stream peripheral-to-memory data transfer */
-#define DMA_SxCR_DIR_MP                 (uint32_t) (1 << 6)                                     /* DMA stream memory-to-peripheral data transfer */
-#define DMA_SxCR_DIR_MM                 (uint32_t) (2 << 6)                                     /* DMA stream memory-to-memory data transfer */
-#define DMA_SxCR_CIRC                   (uint32_t) (1 << 8)                                     /* DMA stream circular mode enable */
-#define DMA_SxCR_PINC                   (uint32_t) (1 << 9)                                     /* DMA stream peripheral increment mode enable */
-#define DMA_SxCR_MINC                   (uint32_t) (1 << 10)                                    /* DMA stream memory increment mode enable */
-#define DMA_SxCR_PSIZE_BYTE             (uint32_t) (0 << 11)                                    /* DMA stream peripheral data size - Byte */
-#define DMA_SxCR_PSIZE_HW               (uint32_t) (1 << 11)                                    /* DMA stream peripheral data size - Half-word */
-#define DMA_SxCR_PSIZE_WORD             (uint32_t) (2 << 11)                                    /* DMA stream peripheral data size - Word */
-#define DMA_SxCR_MSIZE_BYTE             (uint32_t) (0 << 13)                                    /* DMA stream memory data size - Byte */
-#define DMA_SxCR_MSIZE_HW               (uint32_t) (1 << 13)                                    /* DMA stream memory data size - Half-word */
-#define DMA_SxCR_MSIZE_WORD             (uint32_t) (2 << 13)                                    /* DMA stream memory data size - Word */
-#define DMA_SxCR_PINCOS_LINKED          (uint32_t) (0 << 15)                                    /* DMA stream peripheral increment offset size linked to PSIZE */
-#define DMA_SxCR_PINCOS_FIXED           (uint32_t) (1 << 15)                                    /* DMA stream peripheral increment offset size fixed */
-#define DMA_SxCR_PL_LOW                 (uint32_t) (0 << 16)                                    /* DMA stream priority level low */
-#define DMA_SxCR_PL_MED                 (uint32_t) (1 << 16)                                    /* DMA stream priority level medium */
-#define DMA_SxCR_PL_HIGH                (uint32_t) (2 << 16)                                    /* DMA stream priority level high */
-#define DMA_SxCR_PL_VHIGH               (uint32_t) (3 << 16)                                    /* DMA stream priority level very high */
-#define DMA_SxCR_DBM                    (uint32_t) (1 << 18)                                    /* DMA stream double buffer mode */
-#define DMA_SxCR_CT                     (uint32_t) (1 << 19)                                    /* DMA stream current target (M0 or M1) */
-#define DMA_SxCR_PBURST_NO              (uint32_t) (0 << 21)                                    /* DMA stream peripheral burst disable */
-#define DMA_SxCR_PBURST_4               (uint32_t) (1 << 21)                                    /* DMA stream peripheral burst of 4 beats */
-#define DMA_SxCR_PBURST_8               (uint32_t) (2 << 21)                                    /* DMA stream peripheral burst of 8 beats */
-#define DMA_SxCR_PBURST_16              (uint32_t) (3 << 21)                                    /* DMA stream peripheral burst of 16 beats */
-#define DMA_SxCR_MBURST_NO              (uint32_t) (0 << 23)                                    /* DMA stream memory burst disable */
-#define DMA_SxCR_MBURST_4               (uint32_t) (1 << 23)                                    /* DMA stream memory burst of 4 beats */
-#define DMA_SxCR_MBURST_8               (uint32_t) (2 << 23)                                    /* DMA stream memory burst of 8 beats */
-#define DMA_SxCR_MBURST_16              (uint32_t) (3 << 23)                                    /* DMA stream memory burst of 16 beats */
-#define DMA_SxCR_CHSEL(x)               (uint32_t) (x << 25)                                    /* DMA stream channel select */
-
-#define DMA_SxFCR_FTH_1                 (uint32_t) (0 << 0)                                     /* DMA stream FIFO threshold 1/4 */
-#define DMA_SxFCR_FTH_2                 (uint32_t) (1 << 0)                                     /* DMA stream FIFO threshold 1/2 */
-#define DMA_SxFCR_FTH_3                 (uint32_t) (2 << 0)                                     /* DMA stream FIFO threshold 3/4 */
-#define DMA_SxFCR_FTH_4                 (uint32_t) (3 << 0)                                     /* DMA stream FIFO threshold full*/
-#define DMA_SxFCR_DMDIS                 (uint32_t) (1 << 2)                                     /* DMA stream direct mode disable */
-#define DMA_SxFCR_FS                    (uint32_t) (7 << 3)                                     /* DMA stream FIFO status */
-#define DMA_SxFCR_FEIE                  (uint32_t) (1 << 7)                                     /* DMA stream FIFO error interrupt enable */
+#define DMA_LISR_TCIF2 \
+    (uint32_t) (1 << 21) /* DMA stream 2 transfer complete flag */
+#define DMA_HISR_TCIF7 \
+    (uint32_t) (1 << 27) /* DMA stream 7 transfer complete flag */
+#define DMA_LIFCR_CTCIF2 \
+    (uint32_t) (1 << 21) /* DMA clear stream 2 transfer complete flag */
+#define DMA_HIFCR_CTCIF7 \
+    (uint32_t) (1 << 27) /* DMA clear stream 7 transfer complete flag */
+
+#define DMA_SxCR_EN (uint32_t) (1 << 0) /* DMA stream enable */
+#define DMA_SxCR_DMEIE \
+    (uint32_t) (1 << 1) /* DMA stream direct mode error interrupt enable */
+#define DMA_SxCR_TEIE \
+    (uint32_t) (1 << 2) /* DMA stream transmit error interrupt enable */
+#define DMA_SxCR_HTIE \
+    (uint32_t) (1 << 3) /* DMA stream half transfer interrupt enable */
+#define DMA_SxCR_TCIE \
+    (uint32_t) (1 << 4) /* DMA stream transfer complete interrupt enable */
+#define DMA_SxCR_PFCTRL \
+    (uint32_t) (1 << 5) /* DMA stream peripheral flow control */
+#define DMA_SxCR_DIR_PM \
+    (uint32_t) (0 << 6) /* DMA stream peripheral-to-memory data transfer */
+#define DMA_SxCR_DIR_MP \
+    (uint32_t) (1 << 6) /* DMA stream memory-to-peripheral data transfer */
+#define DMA_SxCR_DIR_MM \
+    (uint32_t) (2 << 6) /* DMA stream memory-to-memory data transfer */
+#define DMA_SxCR_CIRC                                      \
+    (uint32_t) (1 << 8) /* DMA stream circular mode enable \
+                         */
+#define DMA_SxCR_PINC \
+    (uint32_t) (1 << 9) /* DMA stream peripheral increment mode enable */
+#define DMA_SxCR_MINC \
+    (uint32_t) (1 << 10) /* DMA stream memory increment mode enable */
+#define DMA_SxCR_PSIZE_BYTE \
+    (uint32_t) (0 << 11) /* DMA stream peripheral data size - Byte */
+#define DMA_SxCR_PSIZE_HW \
+    (uint32_t) (1 << 11) /* DMA stream peripheral data size - Half-word */
+#define DMA_SxCR_PSIZE_WORD \
+    (uint32_t) (2 << 11) /* DMA stream peripheral data size - Word */
+#define DMA_SxCR_MSIZE_BYTE \
+    (uint32_t) (0 << 13) /* DMA stream memory data size - Byte */
+#define DMA_SxCR_MSIZE_HW \
+    (uint32_t) (1 << 13) /* DMA stream memory data size - Half-word */
+#define DMA_SxCR_MSIZE_WORD \
+    (uint32_t) (2 << 13) /* DMA stream memory data size - Word */
+#define DMA_SxCR_PINCOS_LINKED                                                 \
+    (uint32_t) (0 << 15) /* DMA stream peripheral increment offset size linked \
+                            to PSIZE */
+#define DMA_SxCR_PINCOS_FIXED                                                 \
+    (uint32_t) (1 << 15) /* DMA stream peripheral increment offset size fixed \
+                          */
+#define DMA_SxCR_PL_LOW                                   \
+    (uint32_t) (0 << 16) /* DMA stream priority level low \
+                          */
+#define DMA_SxCR_PL_MED \
+    (uint32_t) (1 << 16) /* DMA stream priority level medium */
+#define DMA_SxCR_PL_HIGH \
+    (uint32_t) (2 << 16) /* DMA stream priority level high */
+#define DMA_SxCR_PL_VHIGH \
+    (uint32_t) (3 << 16) /* DMA stream priority level very high */
+#define DMA_SxCR_DBM (uint32_t) (1 << 18) /* DMA stream double buffer mode */
+#define DMA_SxCR_CT \
+    (uint32_t) (1 << 19) /* DMA stream current target (M0 or M1) */
+#define DMA_SxCR_PBURST_NO \
+    (uint32_t) (0 << 21) /* DMA stream peripheral burst disable */
+#define DMA_SxCR_PBURST_4 \
+    (uint32_t) (1 << 21) /* DMA stream peripheral burst of 4 beats */
+#define DMA_SxCR_PBURST_8 \
+    (uint32_t) (2 << 21) /* DMA stream peripheral burst of 8 beats */
+#define DMA_SxCR_PBURST_16 \
+    (uint32_t) (3 << 21) /* DMA stream peripheral burst of 16 beats */
+#define DMA_SxCR_MBURST_NO \
+    (uint32_t) (0 << 23) /* DMA stream memory burst disable */
+#define DMA_SxCR_MBURST_4 \
+    (uint32_t) (1 << 23) /* DMA stream memory burst of 4 beats */
+#define DMA_SxCR_MBURST_8 \
+    (uint32_t) (2 << 23) /* DMA stream memory burst of 8 beats */
+#define DMA_SxCR_MBURST_16 \
+    (uint32_t) (3 << 23) /* DMA stream memory burst of 16 beats */
+#define DMA_SxCR_CHSEL(x) (uint32_t) (x << 25) /* DMA stream channel select */
+
+#define DMA_SxFCR_FTH_1                                  \
+    (uint32_t) (0 << 0) /* DMA stream FIFO threshold 1/4 \
+                         */
+#define DMA_SxFCR_FTH_2                                  \
+    (uint32_t) (1 << 0) /* DMA stream FIFO threshold 1/2 \
+                         */
+#define DMA_SxFCR_FTH_3                                  \
+    (uint32_t) (2 << 0) /* DMA stream FIFO threshold 3/4 \
+                         */
+#define DMA_SxFCR_FTH_4                              \
+    (uint32_t) (3 << 0) /* DMA stream FIFO threshold \
+                           full*/
+#define DMA_SxFCR_DMDIS                                                    \
+    (uint32_t) (1 << 2)                  /* DMA stream direct mode disable \
+                                          */
+#define DMA_SxFCR_FS (uint32_t) (7 << 3) /* DMA stream FIFO status */
+#define DMA_SxFCR_FEIE \
+    (uint32_t) (1 << 7) /* DMA stream FIFO error interrupt enable */
 
 /* USB FS */
 /* Global Registers */
-#define USB_FS_GOTGCTL_SRQSCS           (uint32_t) (1 << 0)                                     /* USB session request success */
-#define USB_FS_GOTGCTL_SRQ              (uint32_t) (1 << 1)                                     /* USB session request */
-#define USB_FS_GOTGCTL_HNGSCS           (uint32_t) (1 << 8)                                     /* USB host negotiation success */
-#define USB_FS_GOTGCTL_HNP              (uint32_t) (1 << 9)                                     /* USB HNP request */
-#define USB_FS_GOTGCTL_HSHNPEN          (uint32_t) (1 << 10)                                    /* USB host set HPN enable */
-#define USB_FS_GOTGCTL_DHNPEN           (uint32_t) (1 << 11)                                    /* USB device HPN enabled */
-#define USB_FS_GOTGCTL_CIDSTS           (uint32_t) (1 << 16)                                    /* USB connector ID status */
-#define USB_FS_GOTGCTL_DBCT             (uint32_t) (1 << 17)                                    /* USB debounce time */
-#define USB_FS_GOTGCTL_ASVLD            (uint32_t) (1 << 18)                                    /* USB A session valid */
-#define USB_FS_GOTGCTL_BSVLD            (uint32_t) (1 << 19)                                    /* USB B session valid */
-
-#define USB_FS_GOTGINT_SEDET            (uint32_t) (1 << 2)                                     /* USB session end detected */
-#define USB_FS_GOTGINT_SRSSCHG          (uint32_t) (1 << 8)                                     /* USB session request success status change */
-#define USB_FS_GOTGINT_HNSSCHG          (uint32_t) (1 << 9)                                     /* USB host negotiation success status change */
-#define USB_FS_GOTGINT_HNGDET           (uint32_t) (1 << 17)                                    /* USB host negotiation detected */
-#define USB_FS_GOTGINT_ADTOCHG          (uint32_t) (1 << 18)                                    /* USB A-device timeout change */
-#define USB_FS_GOTGINT_DBCDNE           (uint32_t) (1 << 19)                                    /* USB debounce done */
-
-#define USB_FS_GAHBCFG_GINTMSK          (uint32_t) (1 << 0)                                     /* USB global interrupt mask */
-#define USB_FS_GAHBCFG_TXFELVL          (uint32_t) (1 << 7)                                     /* USB TX FIFO empty level */
-#define USB_FS_GAHBCFG_PTXFELVL         (uint32_t) (1 << 8)                                     /* USB Periodic TX FIFO empty level */
-
-#define USB_FS_GUSBCFG_TOCAL(n)         (uint32_t) (n << 0)                                     /* USB FS timeout calibration */
-#define USB_FS_GUSBCFG_PHYSEL           (uint32_t) (1 << 7)                                     /* USB FS serial transceiver select */
-#define USB_FS_GUSBCFG_SRPCAP           (uint32_t) (1 << 8)                                     /* USB SRP capable */
-#define USB_FS_GUSBCFG_HNPCAP           (uint32_t) (1 << 9)                                     /* USB HNP capable */
-#define USB_FS_GUSBCFG_TRDT(n)          (uint32_t) (n << 10)                                    /* USB turnaround time (4 bits) */
-#define USB_FS_GUSBCFG_FHMOD            (uint32_t) (1 << 29)                                    /* USB force host mode */
-#define USB_FS_GUSBCFG_FDMOD            (uint32_t) (1 << 30)                                    /* USB force device mode */
-#define USB_FS_GUSBCFG_CTXPKT           (uint32_t) (1 << 31)                                    /* USB corrupt packet */
-
-#define USB_FS_GRSTCTL_CSRST            (uint32_t) (1 << 0)                                     /* USB core soft reset */
-#define USB_FS_GRSTCTL_HSRST            (uint32_t) (1 << 1)                                     /* USB HCLK soft reset */
-#define USB_FS_GRSTCTL_FCRST            (uint32_t) (1 << 2)                                     /* USB host frame counter reset */
-#define USB_FS_GRSTCTL_RXFFLSH          (uint32_t) (1 << 4)                                     /* USB RX FIFO flush */
-#define USB_FS_GRSTCTL_TXFFLSH          (uint32_t) (1 << 5)                                     /* USB TX FIFO flush */
-#define USB_FS_GRSTCTL_TXFNUM(n)        (uint32_t) (n << 6)                                     /* USB TX FIFO number */
-#define USB_FS_GRSTCTL_AHBIDL           (uint32_t) (1 << 31)                                    /* USB AHB master idle */
-
-#define USB_FS_GINTSTS_CMOD             (uint32_t) (1 << 0)                                     /* USB current mode of operation */
-#define USB_FS_GINTSTS_MMIS             (uint32_t) (1 << 1)                                     /* USB mode mismatch interrupt */
-#define USB_FS_GINTSTS_OTGINT           (uint32_t) (1 << 2)                                     /* USB OTG interrupt */
-#define USB_FS_GINTSTS_SOF              (uint32_t) (1 << 3)                                     /* USB start of frame */
-#define USB_FS_GINTSTS_RXFLVL           (uint32_t) (1 << 4)                                     /* USB RX FIFO non-empty */
-#define USB_FS_GINTSTS_NPTXFE           (uint32_t) (1 << 5)                                     /* USB non-periodic TX FIFO empty */
-#define USB_FS_GINTSTS_GINAKEFF         (uint32_t) (1 << 6)                                     /* USB global IN non-periodic NAK effective */
-#define USB_FS_GINTSTS_GONAKEFF         (uint32_t) (1 << 7)                                     /* USB global OUT NAK effective */
-#define USB_FS_GINTSTS_ESUSP            (uint32_t) (1 << 10)                                    /* USB early suspend */
-#define USB_FS_GINTSTS_USBSUSP          (uint32_t) (1 << 11)                                    /* USB suspend */
-#define USB_FS_GINTSTS_USBRST           (uint32_t) (1 << 12)                                    /* USB reset */
-#define USB_FS_GINTSTS_ENUMDNE          (uint32_t) (1 << 13)                                    /* USB enumeration done */
-#define USB_FS_GINTSTS_ISOODRP          (uint32_t) (1 << 14)                                    /* USB isochronous OUT packet dropped interrupt */
-#define USB_FS_GINTSTS_EOPF             (uint32_t) (1 << 15)                                    /* USB end of packet frame interrupt */
-#define USB_FS_GINTSTS_IEPINT           (uint32_t) (1 << 18)                                    /* USB IN endpoint interrupt */
-#define USB_FS_GINTSTS_OEPINT           (uint32_t) (1 << 19)                                    /* USB OUT endpoint interrupt */
-#define USB_FS_GINTSTS_IISOIXFR         (uint32_t) (1 << 20)                                    /* USB incomplete isochronous IN transfer */
-#define USB_FS_GINTSTS_IISOOXFR         (uint32_t) (1 << 21)                                    /* USB incomplete isochronous OUT transfer */
-#define USB_FS_GINTSTS_IPXFR            (uint32_t) (1 << 21)                                    /* USB incomplete periodic transfer */
-#define USB_FS_GINTSTS_HPRTINT          (uint32_t) (1 << 24)                                    /* USB host port interrupt */
-#define USB_FS_GINTSTS_HCINT            (uint32_t) (1 << 25)                                    /* USB host channels interrupt */
-#define USB_FS_GINTSTS_PTXFE            (uint32_t) (1 << 26)                                    /* USB periodic TX FIFO empty */
-#define USB_FS_GINTSTS_CIDSCHG          (uint32_t) (1 << 28)                                    /* USB connector ID status change */
-#define USB_FS_GINTSTS_DISCINT          (uint32_t) (1 << 29)                                    /* USB disconnect detected interrupt */
-#define USB_FS_GINTSTS_SRQINT           (uint32_t) (1 << 30)                                    /* USB session request/new session detected interrupt */
-#define USB_FS_GINTSTS_WKUPINT          (uint32_t) (1 << 31)                                    /* USB resume/remote wakeup detected interrupt */
-
-#define USB_FS_GINTMSK_MMISM            (uint32_t) (1 << 1)                                     /* USB mode mismatch interrupt mask */
-#define USB_FS_GINTMSK_OTGINT           (uint32_t) (1 << 2)                                     /* USB OTG interrupt mask */
-#define USB_FS_GINTMSK_SOFM             (uint32_t) (1 << 3)                                     /* USB start of frame mask */
-#define USB_FS_GINTMSK_RXFLVLM          (uint32_t) (1 << 4)                                     /* USB RX FIFO non-empty mask */
-#define USB_FS_GINTMSK_NPTXFEM          (uint32_t) (1 << 5)                                     /* USB non-periodic TX FIFO empty mask */
-#define USB_FS_GINTMSK_GINAKEFFM        (uint32_t) (1 << 6)                                     /* USB global IN non-periodic NAK effective mask */
-#define USB_FS_GINTMSK_GONAKEFFM        (uint32_t) (1 << 7)                                     /* USB global OUT NAK effective mask */
-#define USB_FS_GINTMSK_ESUSPM           (uint32_t) (1 << 10)                                    /* USB early suspend mask */
-#define USB_FS_GINTMSK_USBSUSPM         (uint32_t) (1 << 11)                                    /* USB suspend mask */
-#define USB_FS_GINTMSK_USBRSTM          (uint32_t) (1 << 12)                                    /* USB reset mask */
-#define USB_FS_GINTMSK_ENUMDNEM         (uint32_t) (1 << 13)                                    /* USB enumeration done mask */
-#define USB_FS_GINTMSK_ISOODRPM         (uint32_t) (1 << 14)                                    /* USB isochronous OUT packet dropped interrupt mask */
-#define USB_FS_GINTMSK_EOPFM            (uint32_t) (1 << 15)                                    /* USB end of packet frame interrupt mask */
-#define USB_FS_GINTMSK_EPMISM           (uint32_t) (1 << 17)                                    /* USB endpoint mismatch interrupt mask */
-#define USB_FS_GINTMSK_IEPINT           (uint32_t) (1 << 18)                                    /* USB IN endpoint interrupt mask */
-#define USB_FS_GINTMSK_OEPINT           (uint32_t) (1 << 19)                                    /* USB OUT endpoint interrupt mask */
-#define USB_FS_GINTMSK_IISOIXFRM        (uint32_t) (1 << 20)                                    /* USB incomplete isochronous IN transfer mask */
-#define USB_FS_GINTMSK_IISOOXFRM        (uint32_t) (1 << 21)                                    /* USB incomplete isochronous OUT transfer mask */
-#define USB_FS_GINTMSK_IPXFRM           (uint32_t) (1 << 21)                                    /* USB incomplete periodic transfer mask */
-#define USB_FS_GINTMSK_HPRTINT          (uint32_t) (1 << 24)                                    /* USB host port interrupt mask */
-#define USB_FS_GINTMSK_HCINT            (uint32_t) (1 << 25)                                    /* USB host channels interrupt mask */
-#define USB_FS_GINTMSK_PTXFEM           (uint32_t) (1 << 26)                                    /* USB periodic TX FIFO empty mask */
-#define USB_FS_GINTMSK_CIDSCHGM         (uint32_t) (1 << 28)                                    /* USB connector ID status change mask */
-#define USB_FS_GINTMSK_DISCINT          (uint32_t) (1 << 29)                                    /* USB disconnect detected interrupt mask */
-#define USB_FS_GINTMSK_SRQINT           (uint32_t) (1 << 30)                                    /* USB session request/new session detected interrupt mask */
-#define USB_FS_GINTMSK_WKUPINT          (uint32_t) (1 << 31)                                    /* USB resume/remote wakeup detected interrupt mask */
-
-#define USB_FS_GRXSTS_EPNUM(r)          (uint32_t) (r & 0xF)                                    /* USB RX FIFO endpoint number */
-#define USB_FS_GRXSTS_BCNT(r)           (uint32_t) ((r & 0x7FF0) >> 4)                          /* USB RX FIFO byte count */
-#define USB_FS_GRXSTS_DPID(r)           (uint32_t) ((r & 0x18000) >> 15)                        /* USB RX FIFO data PID */
-#define USB_FS_GRXSTS_PKTSTS(r)         (uint32_t) ((r & 0x1E0000) >> 17)                       /* USB RX FIFO packet status */
-#define USB_FS_GRXSTS_FRMNUM(r)         (uint32_t) ((r & 0x1E00000) >> 21)                      /* USB RX FIFO frame number */
-#define USB_FS_GRXSTS_PKTSTS_NAK        (uint8_t)  (1)                                          /* USB RX FIFO packet status = global OUT NAK */
-#define USB_FS_GRXSTS_PKTSTS_ORX        (uint8_t)  (2)                                          /* USB RX FIFO packet status = OUT data packet received */
-#define USB_FS_GRXSTS_PKTSTS_OCP        (uint8_t)  (3)                                          /* USB RX FIFO packet status = OUT transfer completed */
-#define USB_FS_GRXSTS_PKTSTS_STUPCP     (uint8_t)  (4)                                          /* USB RX FIFO packet status = SETUP transaction completed */
-#define USB_FS_GRXSTS_PKTSTS_STUPRX     (uint8_t)  (6)                                          /* USB RX FIFO packet status = SETUP data packet received */
-
-#define USB_FS_DIEPTXF0_TX0FSA(n)       (uint32_t) (n << 0)                                     /* USB endpoint 0 transmit RAM start address */
-#define USB_FS_DIEPTXF0_TX0FD(n)        (uint32_t) (n << 16)                                    /* USB endpoint 0 TX FIFO depth */
-
-#define USB_FS_GCCFG_PWRDWN             (uint32_t) (1 << 16)                                    /* USB power down */
-#define USB_FS_GCCFG_VBUSASEN           (uint32_t) (1 << 18)                                    /* USB VBUS "A" sensing enable */
-#define USB_FS_GCCFG_VBUSBSEN           (uint32_t) (1 << 19)                                    /* USB VBUS "B" sensing enable */
-#define USB_FS_GCCFG_SOFOUTEN           (uint32_t) (1 << 20)                                    /* USB SOF output enable */
-#define USB_FS_GCCFG_NOVBUSSSENS        (uint32_t) (1 << 21)                                    /* USB VBUS sensing disable */
-
-#define USB_FS_DIEPTXF_INEPTXSA(n)      (uint32_t) (n << 0)                                     /* USB IN endpoint FIFOx transmit RAM start address */
-#define USB_FS_DIEPTXF_INEPTXFD(n)      (uint32_t) (n << 16)                                    /* USB IN endpoint TX FIFOx depth */
+#define USB_FS_GOTGCTL_SRQSCS \
+    (uint32_t) (1 << 0)                        /* USB session request success */
+#define USB_FS_GOTGCTL_SRQ (uint32_t) (1 << 1) /* USB session request */
+#define USB_FS_GOTGCTL_HNGSCS \
+    (uint32_t) (1 << 8) /* USB host negotiation success */
+#define USB_FS_GOTGCTL_HNP (uint32_t) (1 << 9) /* USB HNP request */
+#define USB_FS_GOTGCTL_HSHNPEN \
+    (uint32_t) (1 << 10) /* USB host set HPN enable */
+#define USB_FS_GOTGCTL_DHNPEN                      \
+    (uint32_t) (1 << 11) /* USB device HPN enabled \
+                          */
+#define USB_FS_GOTGCTL_CIDSTS                                                \
+    (uint32_t) (1 << 16)                          /* USB connector ID status \
+                                                   */
+#define USB_FS_GOTGCTL_DBCT (uint32_t) (1 << 17)  /* USB debounce time */
+#define USB_FS_GOTGCTL_ASVLD (uint32_t) (1 << 18) /* USB A session valid */
+#define USB_FS_GOTGCTL_BSVLD (uint32_t) (1 << 19) /* USB B session valid */
+
+#define USB_FS_GOTGINT_SEDET                        \
+    (uint32_t) (1 << 2) /* USB session end detected \
+                         */
+#define USB_FS_GOTGINT_SRSSCHG \
+    (uint32_t) (1 << 8) /* USB session request success status change */
+#define USB_FS_GOTGINT_HNSSCHG \
+    (uint32_t) (1 << 9) /* USB host negotiation success status change */
+#define USB_FS_GOTGINT_HNGDET \
+    (uint32_t) (1 << 17) /* USB host negotiation detected */
+#define USB_FS_GOTGINT_ADTOCHG \
+    (uint32_t) (1 << 18) /* USB A-device timeout change */
+#define USB_FS_GOTGINT_DBCDNE (uint32_t) (1 << 19) /* USB debounce done */
+
+#define USB_FS_GAHBCFG_GINTMSK \
+    (uint32_t) (1 << 0) /* USB global interrupt mask */
+#define USB_FS_GAHBCFG_TXFELVL                     \
+    (uint32_t) (1 << 7) /* USB TX FIFO empty level \
+                         */
+#define USB_FS_GAHBCFG_PTXFELVL \
+    (uint32_t) (1 << 8) /* USB Periodic TX FIFO empty level */
+
+#define USB_FS_GUSBCFG_TOCAL(n) \
+    (uint32_t) (n << 0) /* USB FS timeout calibration */
+#define USB_FS_GUSBCFG_PHYSEL \
+    (uint32_t) (1 << 7) /* USB FS serial transceiver select */
+#define USB_FS_GUSBCFG_SRPCAP (uint32_t) (1 << 8) /* USB SRP capable */
+#define USB_FS_GUSBCFG_HNPCAP (uint32_t) (1 << 9) /* USB HNP capable */
+#define USB_FS_GUSBCFG_TRDT(n) \
+    (uint32_t) (n << 10) /* USB turnaround time (4 bits) */
+#define USB_FS_GUSBCFG_FHMOD (uint32_t) (1 << 29)  /* USB force host mode */
+#define USB_FS_GUSBCFG_FDMOD (uint32_t) (1 << 30)  /* USB force device mode */
+#define USB_FS_GUSBCFG_CTXPKT (uint32_t) (1 << 31) /* USB corrupt packet */
+
+#define USB_FS_GRSTCTL_CSRST (uint32_t) (1 << 0) /* USB core soft reset */
+#define USB_FS_GRSTCTL_HSRST (uint32_t) (1 << 1) /* USB HCLK soft reset */
+#define USB_FS_GRSTCTL_FCRST \
+    (uint32_t) (1 << 2) /* USB host frame counter reset */
+#define USB_FS_GRSTCTL_RXFFLSH (uint32_t) (1 << 4)   /* USB RX FIFO flush */
+#define USB_FS_GRSTCTL_TXFFLSH (uint32_t) (1 << 5)   /* USB TX FIFO flush */
+#define USB_FS_GRSTCTL_TXFNUM(n) (uint32_t) (n << 6) /* USB TX FIFO number */
+#define USB_FS_GRSTCTL_AHBIDL (uint32_t) (1 << 31)   /* USB AHB master idle */
+
+#define USB_FS_GINTSTS_CMOD \
+    (uint32_t) (1 << 0) /* USB current mode of operation */
+#define USB_FS_GINTSTS_MMIS \
+    (uint32_t) (1 << 1) /* USB mode mismatch interrupt */
+#define USB_FS_GINTSTS_OTGINT (uint32_t) (1 << 2) /* USB OTG interrupt */
+#define USB_FS_GINTSTS_SOF (uint32_t) (1 << 3)    /* USB start of frame */
+#define USB_FS_GINTSTS_RXFLVL (uint32_t) (1 << 4) /* USB RX FIFO non-empty */
+#define USB_FS_GINTSTS_NPTXFE \
+    (uint32_t) (1 << 5) /* USB non-periodic TX FIFO empty */
+#define USB_FS_GINTSTS_GINAKEFF \
+    (uint32_t) (1 << 6) /* USB global IN non-periodic NAK effective */
+#define USB_FS_GINTSTS_GONAKEFF \
+    (uint32_t) (1 << 7) /* USB global OUT NAK effective */
+#define USB_FS_GINTSTS_ESUSP (uint32_t) (1 << 10)   /* USB early suspend */
+#define USB_FS_GINTSTS_USBSUSP (uint32_t) (1 << 11) /* USB suspend */
+#define USB_FS_GINTSTS_USBRST (uint32_t) (1 << 12)  /* USB reset */
+#define USB_FS_GINTSTS_ENUMDNE (uint32_t) (1 << 13) /* USB enumeration done */
+#define USB_FS_GINTSTS_ISOODRP \
+    (uint32_t) (1 << 14) /* USB isochronous OUT packet dropped interrupt */
+#define USB_FS_GINTSTS_EOPF \
+    (uint32_t) (1 << 15) /* USB end of packet frame interrupt */
+#define USB_FS_GINTSTS_IEPINT \
+    (uint32_t) (1 << 18) /* USB IN endpoint interrupt */
+#define USB_FS_GINTSTS_OEPINT \
+    (uint32_t) (1 << 19) /* USB OUT endpoint interrupt */
+#define USB_FS_GINTSTS_IISOIXFR \
+    (uint32_t) (1 << 20) /* USB incomplete isochronous IN transfer */
+#define USB_FS_GINTSTS_IISOOXFR \
+    (uint32_t) (1 << 21) /* USB incomplete isochronous OUT transfer */
+#define USB_FS_GINTSTS_IPXFR \
+    (uint32_t) (1 << 21) /* USB incomplete periodic transfer */
+#define USB_FS_GINTSTS_HPRTINT \
+    (uint32_t) (1 << 24) /* USB host port interrupt */
+#define USB_FS_GINTSTS_HCINT \
+    (uint32_t) (1 << 25) /* USB host channels interrupt */
+#define USB_FS_GINTSTS_PTXFE \
+    (uint32_t) (1 << 26) /* USB periodic TX FIFO empty */
+#define USB_FS_GINTSTS_CIDSCHG \
+    (uint32_t) (1 << 28) /* USB connector ID status change */
+#define USB_FS_GINTSTS_DISCINT \
+    (uint32_t) (1 << 29) /* USB disconnect detected interrupt */
+#define USB_FS_GINTSTS_SRQINT                                                  \
+    (uint32_t) (1 << 30) /* USB session request/new session detected interrupt \
+                          */
+#define USB_FS_GINTSTS_WKUPINT \
+    (uint32_t) (1 << 31) /* USB resume/remote wakeup detected interrupt */
+
+#define USB_FS_GINTMSK_MMISM \
+    (uint32_t) (1 << 1) /* USB mode mismatch interrupt mask */
+#define USB_FS_GINTMSK_OTGINT (uint32_t) (1 << 2) /* USB OTG interrupt mask */
+#define USB_FS_GINTMSK_SOFM (uint32_t) (1 << 3)   /* USB start of frame mask */
+#define USB_FS_GINTMSK_RXFLVLM \
+    (uint32_t) (1 << 4) /* USB RX FIFO non-empty mask */
+#define USB_FS_GINTMSK_NPTXFEM \
+    (uint32_t) (1 << 5) /* USB non-periodic TX FIFO empty mask */
+#define USB_FS_GINTMSK_GINAKEFFM \
+    (uint32_t) (1 << 6) /* USB global IN non-periodic NAK effective mask */
+#define USB_FS_GINTMSK_GONAKEFFM \
+    (uint32_t) (1 << 7) /* USB global OUT NAK effective mask */
+#define USB_FS_GINTMSK_ESUSPM                                                  \
+    (uint32_t) (1 << 10)                             /* USB early suspend mask \
+                                                      */
+#define USB_FS_GINTMSK_USBSUSPM (uint32_t) (1 << 11) /* USB suspend mask */
+#define USB_FS_GINTMSK_USBRSTM (uint32_t) (1 << 12)  /* USB reset mask */
+#define USB_FS_GINTMSK_ENUMDNEM \
+    (uint32_t) (1 << 13) /* USB enumeration done mask */
+#define USB_FS_GINTMSK_ISOODRPM                                               \
+    (uint32_t) (1 << 14) /* USB isochronous OUT packet dropped interrupt mask \
+                          */
+#define USB_FS_GINTMSK_EOPFM \
+    (uint32_t) (1 << 15) /* USB end of packet frame interrupt mask */
+#define USB_FS_GINTMSK_EPMISM \
+    (uint32_t) (1 << 17) /* USB endpoint mismatch interrupt mask */
+#define USB_FS_GINTMSK_IEPINT \
+    (uint32_t) (1 << 18) /* USB IN endpoint interrupt mask */
+#define USB_FS_GINTMSK_OEPINT \
+    (uint32_t) (1 << 19) /* USB OUT endpoint interrupt mask */
+#define USB_FS_GINTMSK_IISOIXFRM \
+    (uint32_t) (1 << 20) /* USB incomplete isochronous IN transfer mask */
+#define USB_FS_GINTMSK_IISOOXFRM \
+    (uint32_t) (1 << 21) /* USB incomplete isochronous OUT transfer mask */
+#define USB_FS_GINTMSK_IPXFRM \
+    (uint32_t) (1 << 21) /* USB incomplete periodic transfer mask */
+#define USB_FS_GINTMSK_HPRTINT \
+    (uint32_t) (1 << 24) /* USB host port interrupt mask */
+#define USB_FS_GINTMSK_HCINT \
+    (uint32_t) (1 << 25) /* USB host channels interrupt mask */
+#define USB_FS_GINTMSK_PTXFEM \
+    (uint32_t) (1 << 26) /* USB periodic TX FIFO empty mask */
+#define USB_FS_GINTMSK_CIDSCHGM \
+    (uint32_t) (1 << 28) /* USB connector ID status change mask */
+#define USB_FS_GINTMSK_DISCINT \
+    (uint32_t) (1 << 29) /* USB disconnect detected interrupt mask */
+#define USB_FS_GINTMSK_SRQINT                                                  \
+    (uint32_t) (1 << 30) /* USB session request/new session detected interrupt \
+                            mask */
+#define USB_FS_GINTMSK_WKUPINT                                               \
+    (uint32_t) (1 << 31) /* USB resume/remote wakeup detected interrupt mask \
+                          */
+
+#define USB_FS_GRXSTS_EPNUM(r) \
+    (uint32_t) (r & 0xF) /* USB RX FIFO endpoint number */
+#define USB_FS_GRXSTS_BCNT(r) \
+    (uint32_t) ((r & 0x7FF0) >> 4) /* USB RX FIFO byte count */
+#define USB_FS_GRXSTS_DPID(r) \
+    (uint32_t) ((r & 0x18000) >> 15) /* USB RX FIFO data PID */
+#define USB_FS_GRXSTS_PKTSTS(r) \
+    (uint32_t) ((r & 0x1E0000) >> 17) /* USB RX FIFO packet status */
+#define USB_FS_GRXSTS_FRMNUM(r) \
+    (uint32_t) ((r & 0x1E00000) >> 21) /* USB RX FIFO frame number */
+#define USB_FS_GRXSTS_PKTSTS_NAK \
+    (uint8_t) (1) /* USB RX FIFO packet status = global OUT NAK */
+#define USB_FS_GRXSTS_PKTSTS_ORX \
+    (uint8_t) (2) /* USB RX FIFO packet status = OUT data packet received */
+#define USB_FS_GRXSTS_PKTSTS_OCP \
+    (uint8_t) (3) /* USB RX FIFO packet status = OUT transfer completed */
+#define USB_FS_GRXSTS_PKTSTS_STUPCP                                          \
+    (uint8_t) (4) /* USB RX FIFO packet status = SETUP transaction completed \
+                   */
+#define USB_FS_GRXSTS_PKTSTS_STUPRX \
+    (uint8_t) (6) /* USB RX FIFO packet status = SETUP data packet received */
+
+#define USB_FS_DIEPTXF0_TX0FSA(n) \
+    (uint32_t) (n << 0) /* USB endpoint 0 transmit RAM start address */
+#define USB_FS_DIEPTXF0_TX0FD(n) \
+    (uint32_t) (n << 16) /* USB endpoint 0 TX FIFO depth */
+
+#define USB_FS_GCCFG_PWRDWN (uint32_t) (1 << 16) /* USB power down */
+#define USB_FS_GCCFG_VBUSASEN \
+    (uint32_t) (1 << 18) /* USB VBUS "A" sensing enable */
+#define USB_FS_GCCFG_VBUSBSEN \
+    (uint32_t) (1 << 19) /* USB VBUS "B" sensing enable */
+#define USB_FS_GCCFG_SOFOUTEN (uint32_t) (1 << 20) /* USB SOF output enable */
+#define USB_FS_GCCFG_NOVBUSSSENS \
+    (uint32_t) (1 << 21) /* USB VBUS sensing disable */
+
+#define USB_FS_DIEPTXF_INEPTXSA(n) \
+    (uint32_t) (n << 0) /* USB IN endpoint FIFOx transmit RAM start address */
+#define USB_FS_DIEPTXF_INEPTXFD(n) \
+    (uint32_t) (n << 16) /* USB IN endpoint TX FIFOx depth */
 
 /* Device-mode Registers */
-#define USB_FS_DCFG_DSPD_FS             (uint32_t) (1 << 1 | 1 << 0)                            /* USB device speed: full speed (USB 1.1) */
-#define USB_FS_DCFG_NZLSOHSK            (uint32_t) (1 << 2)                                     /* USB device non-zero-length status OUT handshake */
-#define USB_FS_DCFG_DAD(x)              (uint32_t) (x << 4)                                     /* USB device address */
-#define USB_FS_DCFG_PFIVL_80            (uint32_t) (0 << 11)                                    /* USB device periodic frame interval: 80% */
-#define USB_FS_DCFG_PFIVL_85            (uint32_t) (1 << 11)                                    /* USB device periodic frame interval: 85% */
-#define USB_FS_DCFG_PFIVL_90            (uint32_t) (2 << 11)                                    /* USB device periodic frame interval: 90% */
-#define USB_FS_DCFG_PFIVL_95            (uint32_t) (3 << 11)                                    /* USB device periodic frame interval: 95% */
-
-#define USB_FS_DCTL_RWUSIG              (uint32_t) (1 << 0)                                     /* USB device remote wakeup signaling */
-#define USB_FS_DCTL_SDIS                (uint32_t) (1 << 1)                                     /* USB device soft disconnect */
-#define USB_FS_DCTL_GINSTS              (uint32_t) (1 << 2)                                     /* USB device global IN NAK status */
-#define USB_FS_DCTL_GONSTS              (uint32_t) (1 << 3)                                     /* USB device global OUT NAK status */
-#define USB_FS_DCTL_TCTL_J              (uint32_t) (1 << 4)                                     /* USB device Test_J mode */
-#define USB_FS_DCTL_TCTL_K              (uint32_t) (2 << 4)                                     /* USB device Test_K mode */
-#define USB_FS_DCTL_TCTL_SE0_NAK        (uint32_t) (3 << 4)                                     /* USB device Test_SE0_NAK mode */
-#define USB_FS_DCTL_TCTL_PKT            (uint32_t) (4 << 4)                                     /* USB device Test_Packet mode */
-#define USB_FS_DCTL_TCTL_FEN            (uint32_t) (5 << 4)                                     /* USB device Test_Force_Enable mode */
-#define USB_FS_DCTL_SGINAK              (uint32_t) (1 << 7)                                     /* USB device set global IN NAK */
-#define USB_FS_DCTL_CGINAK              (uint32_t) (1 << 8)                                     /* USB device clear global IN NAK */
-#define USB_FS_DCTL_SGONAK              (uint32_t) (1 << 9)                                     /* USB device set global OUT NAK */
-#define USB_FS_DCTL_CGONAK              (uint32_t) (1 << 10)                                    /* USB device clear global OUT NAK */
-#define USB_FS_DCTL_POPRGDNE            (uint32_t) (1 << 11)                                    /* USB device power-no programming done */
-
-#define USB_FS_DSTS_SUSPSTS             (uint32_t) (1 << 0)                                     /* USB device suspend status */
-#define USB_FS_DSTS_ENUMSPD             (uint32_t) (3 << 1)                                     /* USB device enumerated speed (Must == 3) */
-#define USB_FS_DSTS_ENUMSPD_FS          (uint32_t) (3 << 1)                                          /* USB device enumerated speed (Must == 3) */
-#define USB_FS_DSTS_EERR                (uint32_t) (1 << 3)                                     /* USB device erratic error */
-#define USB_FS_DSTS_FNSOF               (uint32_t) (0x3FFF00)                                   /* USB device frame number of received SOF (bits 21:8) */
-
-#define USB_FS_DIEPMSK_XFRCM            (uint32_t) (1 << 0)                                     /* USB device transfer completed interrupt mask */
-#define USB_FS_DIEPMSK_EPDM             (uint32_t) (1 << 1)                                     /* USB device endpoint disabled interrupt mask */
-#define USB_FS_DIEPMSK_TOM              (uint32_t) (1 << 3)                                     /* USB device timout condition mask */
-#define USB_FS_DIEPMSK_ITTXFEMSK        (uint32_t) (1 << 4)                                     /* USB device IN token received when TX FIFO empty mask */
-#define USB_FS_DIEPMSK_INEPNMM          (uint32_t) (1 << 5)                                     /* USB device IN token received with EP mismatch mask */
-#define USB_FS_DIEPMSK_INEPNEM          (uint32_t) (1 << 6)                                     /* USB device IN endpoint NAK effective mask */
-
-#define USB_FS_DOEPMSK_XFRCM            (uint32_t) (1 << 0)                                     /* USB device transfer completed interrupt mask */
-#define USB_FS_DOEPMSK_EPDM             (uint32_t) (1 << 1)                                     /* USB device endpoint disabled interrupt mask */
-#define USB_FS_DOEPMSK_STUPM            (uint32_t) (1 << 3)                                     /* USB device SETUP phase done mask */
-#define USB_FS_DOEPMSK_OTEPDM           (uint32_t) (1 << 4)                                     /* USB device OUT token received when endpoint disabled mask */
-
-#define USB_FS_DAINT_IEPINT(n)          (uint32_t) (1 << n)                                     /* USB device IN endpoint interrupt bits */
-#define USB_FS_DAINT_OEPINT(n)          (uint32_t) (1 << (n+16))                                /* USB device OUT endpoint interrupt bits */
-
-#define USB_FS_DAINT_IEPM(n)            (uint32_t) (1 << n)                                     /* USB device IN endpoint interrupt mask bits */
-#define USB_FS_DAINT_OEPM(n)            (uint32_t) (1 << (n+16))                                /* USB device OUT endpoint interrupt mask bits */
-
-#define USB_FS_DIEPEMPMSK_INEPTXFEM(n)  (uint32_t) (1 << n)                                     /* USB device IN EP TX FIFO empty interrupt mask bits */
-
-#define USB_FS_DIEPCTL0_MPSIZE          (uint32_t) (3 << 0)                                     /* USB device endpoint 0 IN maximum packet size */
-#define USB_FS_DIEPCTL0_MPSIZE_64       (uint32_t) (0 << 0)                                     /* USB device endpoint 0 IN maximum packet size 64 bytes */
-#define USB_FS_DIEPCTL0_MPSIZE_32       (uint32_t) (1 << 0)                                     /* USB device endpoint 0 IN maximum packet size 32 bytes */
-#define USB_FS_DIEPCTL0_MPSIZE_16       (uint32_t) (2 << 0)                                     /* USB device endpoint 0 IN maximum packet size 16 bytes */
-#define USB_FS_DIEPCTL0_MPSIZE_8        (uint32_t) (3 << 0)                                     /* USB device endpoint 0 IN maximum packet size 8 bytes */
-#define USB_FS_DIEPCTL0_USBAEP          (uint32_t) (1 << 15)                                    /* USB device endpoint 0 IN USB active endpoint (always 1) */
-#define USB_FS_DIEPCTL0_NAKSTS          (uint32_t) (1 << 17)                                    /* USB device endpoint 0 IN NAK status */
-#define USB_FS_DIEPCTL0_STALL           (uint32_t) (1 << 21)                                    /* USB device endpoint 0 IN STALL handshake */
-#define USB_FS_DIEPCTL0_TXFNUM(n)       (uint32_t) (n << 22)                                    /* USB device endpoint 0 IN TX FIFO number */
-#define USB_FS_DIEPCTL0_CNAK            (uint32_t) (1 << 26)                                    /* USB device endpoint 0 IN clear NAK */
-#define USB_FS_DIEPCTL0_SNAK            (uint32_t) (1 << 27)                                    /* USB device endpoint 0 IN set NAK */
-#define USB_FS_DIEPCTL0_EPDIS           (uint32_t) (1 << 30)                                    /* USB device endpoint 0 IN endpoint disable */
-#define USB_FS_DIEPCTL0_EPENA           (uint32_t) (1 << 31)                                    /* USB device endpoint 0 IN endpoint enable */
-
-#define USB_FS_DIEPCTLx_MPSIZE(n)       (uint32_t) (n << 0)                                     /* USB device endpoint x IN maximum packet size in bytes (11 bits) */
-#define USB_FS_DIEPCTLx_USBAEP          (uint32_t) (1 << 15)                                    /* USB device endpoint x IN USB active endpoint */
-#define USB_FS_DIEPCTLx_EONUM_EVEN      (uint32_t) (0 << 16)                                    /* USB device endpoint x IN Odd frame */
-#define USB_FS_DIEPCTLx_EONUM_ODD       (uint32_t) (1 << 16)                                    /* USB device endpoint x IN Odd frame */
-#define USB_FS_DIEPCTLx_DPID_0          (uint32_t) (0 << 16)                                    /* USB device endpoint x IN data PID 0 */
-#define USB_FS_DIEPCTLx_DPID_1          (uint32_t) (1 << 16)                                    /* USB device endpoint x IN data PID 1 */
-#define USB_FS_DIEPCTLx_NAKSTS          (uint32_t) (1 << 17)                                    /* USB device endpoint x IN NAK status */
-#define USB_FS_DIEPCTLx_EPTYP_CTL       (uint32_t) (0 << 18)                                    /* USB device endpoint x IN type: control */
-#define USB_FS_DIEPCTLx_EPTYP_ISO       (uint32_t) (1 << 18)                                    /* USB device endpoint x IN type: isochronous */
-#define USB_FS_DIEPCTLx_EPTYP_BLK       (uint32_t) (2 << 18)                                    /* USB device endpoint x IN type: bulk */
-#define USB_FS_DIEPCTLx_EPTYP_INT       (uint32_t) (3 << 18)                                    /* USB device endpoint x IN type: interrupt */
-#define USB_FS_DIEPCTLx_STALL           (uint32_t) (1 << 21)                                    /* USB device endpoint x IN STALL handshake */
-#define USB_FS_DIEPCTLx_TXFNUM(n)       (uint32_t) (n << 22)                                    /* USB device endpoint x IN TX FIFO number (4 bits) */
-#define USB_FS_DIEPCTLx_CNAK            (uint32_t) (1 << 26)                                    /* USB device endpoint x IN clear NAK */
-#define USB_FS_DIEPCTLx_SNAK            (uint32_t) (1 << 27)                                    /* USB device endpoint x IN set NAK */
-#define USB_FS_DIEPCTLx_SD0PID          (uint32_t) (1 << 28)                                    /* USB device endpoint x IN set DATA0 PID */
-#define USB_FS_DIEPCTLx_SEVNFRM         (uint32_t) (1 << 28)                                    /* USB device endpoint x IN set even frame */
-#define USB_FS_DIEPCTLx_SODDFRM         (uint32_t) (1 << 29)                                    /* USB device endpoint x IN set odd frame */
-#define USB_FS_DIEPCTLx_EPDIS           (uint32_t) (1 << 30)                                    /* USB device endpoint x IN endpoint disable */
-#define USB_FS_DIEPCTLx_EPENA           (uint32_t) (1 << 31)                                    /* USB device endpoint x IN endpoint enable */
-
-#define USB_FS_DOEPCTL0_MPSIZE          (uint32_t) (3 << 0)                                     /* USB device endpoint 0 OUT maximum packet size */
-#define USB_FS_DOEPCTL0_MPSIZE_64       (uint32_t) (0 << 0)                                     /* USB device endpoint 0 OUT maximum packet size 64 bytes */
-#define USB_FS_DOEPCTL0_MPSIZE_32       (uint32_t) (1 << 0)                                     /* USB device endpoint 0 OUT maximum packet size 32 bytes */
-#define USB_FS_DOEPCTL0_MPSIZE_16       (uint32_t) (2 << 0)                                     /* USB device endpoint 0 OUT maximum packet size 16 bytes */
-#define USB_FS_DOEPCTL0_MPSIZE_8        (uint32_t) (3 << 0)                                     /* USB device endpoint 0 OUT maximum packet size 8 bytes */
-#define USB_FS_DOEPCTL0_USBAEP          (uint32_t) (1 << 15)                                    /* USB device endpoint 0 OUT USB active endpoint (always 1) */
-#define USB_FS_DOEPCTL0_NAKSTS          (uint32_t) (1 << 17)                                    /* USB device endpoint 0 OUT NAK status */
-#define USB_FS_DOEPCTL0_SNPM            (uint32_t) (1 << 20)                                    /* USB device endpoint 0 OUT snoop mode */
-#define USB_FS_DOEPCTL0_STALL           (uint32_t) (1 << 21)                                    /* USB device endpoint 0 OUT STALL handshake */
-#define USB_FS_DOEPCTL0_CNAK            (uint32_t) (1 << 26)                                    /* USB device endpoint 0 OUT clear NAK */
-#define USB_FS_DOEPCTL0_SNAK            (uint32_t) (1 << 27)                                    /* USB device endpoint 0 OUT set NAK */
-#define USB_FS_DOEPCTL0_EPDIS           (uint32_t) (1 << 30)                                    /* USB device endpoint 0 OUT endpoint disable */
-#define USB_FS_DOEPCTL0_EPENA           (uint32_t) (1 << 31)                                    /* USB device endpoint 0 OUT endpoint enable */
-
-#define USB_FS_DOEPCTLx_MPSIZE(n)       (uint32_t) (n << 0)                                     /* USB device endpoint x OUT maximum packet size in bytes (11 bits) */
-#define USB_FS_DOEPCTLx_USBAEP          (uint32_t) (1 << 15)                                    /* USB device endpoint x OUT USB active endpoint */
-#define USB_FS_DOEPCTLx_EONUM_EVEN      (uint32_t) (0 << 16)                                    /* USB device endpoint x OUT Odd frame */
-#define USB_FS_DOEPCTLx_EONUM_ODD       (uint32_t) (1 << 16)                                    /* USB device endpoint x OUT Odd frame */
-#define USB_FS_DOEPCTLx_DPID_0          (uint32_t) (0 << 16)                                    /* USB device endpoint x OUT data PID 0 */
-#define USB_FS_DOEPCTLx_DPID_1          (uint32_t) (1 << 16)                                    /* USB device endpoint x OUT data PID 1 */
-#define USB_FS_DOEPCTLx_NAKSTS          (uint32_t) (1 << 17)                                    /* USB device endpoint x OUT NAK status */
-#define USB_FS_DOEPCTLx_EPTYP_CTL       (uint32_t) (0 << 18)                                    /* USB device endpoint x OUT type: control */
-#define USB_FS_DOEPCTLx_EPTYP_ISO       (uint32_t) (1 << 18)                                    /* USB device endpoint x OUT type: isochronous */
-#define USB_FS_DOEPCTLx_EPTYP_BLK       (uint32_t) (2 << 18)                                    /* USB device endpoint x OUT type: bulk */
-#define USB_FS_DOEPCTLx_EPTYP_INT       (uint32_t) (3 << 18)                                    /* USB device endpoint x OUT type: interrupt */
-#define USB_FS_DOEPCTLx_SNPMN           (uint32_t) (1 << 20)                                    /* USB device endpoint x OUT snoop mode */
-#define USB_FS_DOEPCTLx_STALL           (uint32_t) (1 << 21)                                    /* USB device endpoint x OUT STALL handshake */
-#define USB_FS_DOEPCTLx_CNAK            (uint32_t) (1 << 26)                                    /* USB device endpoint x OUT clear NAK */
-#define USB_FS_DOEPCTLx_SNAK            (uint32_t) (1 << 27)                                    /* USB device endpoint x OUT set NAK */
-#define USB_FS_DOEPCTLx_SD0PID          (uint32_t) (1 << 28)                                    /* USB device endpoint x OUT set DATA0 PID */
-#define USB_FS_DOEPCTLx_SEVNFRM         (uint32_t) (1 << 28)                                    /* USB device endpoint x OUT set even frame */
-#define USB_FS_DOEPCTLx_SODDFRM         (uint32_t) (1 << 29)                                    /* USB device endpoint x OUT set odd frame */
-#define USB_FS_DOEPCTLx_EPDIS           (uint32_t) (1 << 30)                                    /* USB device endpoint x OUT endpoint disable */
-#define USB_FS_DOEPCTLx_EPENA           (uint32_t) (1 << 31)                                    /* USB device endpoint x OUT endpoint enable */
-
-#define USB_FS_DIEPINTx_XFRC            (uint32_t) (1 << 0)                                     /* USB device endpoint x IN transfer complete interrupt */
-#define USB_FS_DIEPINTx_EPDISD          (uint32_t) (1 << 1)                                     /* USB device endpoint x IN endpoint disabled interrupt */
-#define USB_FS_DIEPINTx_TOC             (uint32_t) (1 << 3)                                     /* USB device endpoint x IN timeout condition */
-#define USB_FS_DIEPINTx_ITTXFE          (uint32_t) (1 << 4)                                     /* USB device endpoint x IN token received when TX FIFO is empty */
-#define USB_FS_DIEPINTx_INEPNE          (uint32_t) (1 << 6)                                     /* USB device endpoint x IN endpoint NAK effective */
-#define USB_FS_DIEPINTx_TXFE            (uint32_t) (1 << 7)                                     /* USB device endpoint x IN TX FIFO empty */
-
-#define USB_FS_DOEPINTx_XFRC            (uint32_t) (1 << 0)                                     /* USB device endpoint x OUT transfer complete interrupt */
-#define USB_FS_DOEPINTx_EPDISD          (uint32_t) (1 << 1)                                     /* USB device endpoint x OUT endpoint disabled interrupt */
-#define USB_FS_DOEPINTx_STUP            (uint32_t) (1 << 3)                                     /* USB device endpoint x OUT SETUP phase complete */
-#define USB_FS_DOEPINTx_OTEPDIS         (uint32_t) (1 << 4)                                     /* USB device endpoint x OUT token receieved when endpoint disabled */
-#define USB_FS_DOEPINTx_B2BSTUP         (uint32_t) (1 << 6)                                     /* USB device endpoint x OUT back-to-back SETUP packets received */
-
-#define USB_FS_DIEPTSIZ0_XFRSIZ(n)      (uint32_t) (n << 0)                                     /* USB device endpoint 0 IN transfer size (7 bits) */
-#define USB_FS_DIEPTSIZ0_PKTCNT(n)      (uint32_t) (n << 19)                                    /* USB device endpoint 0 IN packet count */
-
-#define USB_FS_DIEPTSIZx_XFRSIZ(n)      (uint32_t) (n << 0)                                     /* USB device endpoint x IN transfer size (19 bits) */
-#define USB_FS_DIEPTSIZx_PKTCNT(n)      (uint32_t) (n << 19)                                    /* USB device endpoint x IN packet count (10 bits) */
-#define USB_FS_DIEPTSIZx_MCNT_1         (uint32_t) (1 << 29)                                    /* USB device endpoint x IN multi count 1 */
-#define USB_FS_DIEPTSIZx_MCNT_2         (uint32_t) (2 << 29)                                    /* USB device endpoint x IN multi count 1 */
-#define USB_FS_DIEPTSIZx_MCNT_3         (uint32_t) (3 << 29)                                    /* USB device endpoint x IN multi count 1 */
-
-#define USB_FS_DOEPTSIZ0_XFRSIZ(n)      (uint32_t) (n << 0)                                     /* USB device endpoint 0 OUT transfer size (7 bits) */
-#define USB_FS_DOEPTSIZ0_PKTCNT(n)      (uint32_t) (n << 19)                                    /* USB device endpoint 0 OUT packet count */
-#define USB_FS_DOEPTSIZ0_STUPCNT(n)     (uint32_t) (n << 29)                                    /* USB device endpoint 0 OUT back-to-back SETUP packets allowed */
-
-#define USB_FS_DOEPTSIZx_XFRSIZ(n)      (uint32_t) (n << 0)                                     /* USB device endpoint x OUT transfer size (19 bits) */
-#define USB_FS_DOEPTSIZx_PKTCNT(n)      (uint32_t) (n << 19)                                    /* USB device endpoint x OUT packet count (10 bits) */
-#define USB_FS_DOEPTSIZx_STUPCNT(n)     (uint32_t) (n << 29)                                    /* USB device endpoint x OUT back-to-back SETUP packets allowed */
-#define USB_FS_DOEPTSIZx_RXDPID         (uint32_t) (1 << 29 | 1 << 30)                          /* USB device endpoint x OUT received data PID */
+#define USB_FS_DCFG_DSPD_FS \
+    (uint32_t) (1 << 1 | 1 << 0) /* USB device speed: full speed (USB 1.1) */
+#define USB_FS_DCFG_NZLSOHSK \
+    (uint32_t) (1 << 2) /* USB device non-zero-length status OUT handshake */
+#define USB_FS_DCFG_DAD(x) (uint32_t) (x << 4) /* USB device address */
+#define USB_FS_DCFG_PFIVL_80 \
+    (uint32_t) (0 << 11) /* USB device periodic frame interval: 80% */
+#define USB_FS_DCFG_PFIVL_85 \
+    (uint32_t) (1 << 11) /* USB device periodic frame interval: 85% */
+#define USB_FS_DCFG_PFIVL_90 \
+    (uint32_t) (2 << 11) /* USB device periodic frame interval: 90% */
+#define USB_FS_DCFG_PFIVL_95 \
+    (uint32_t) (3 << 11) /* USB device periodic frame interval: 95% */
+
+#define USB_FS_DCTL_RWUSIG \
+    (uint32_t) (1 << 0) /* USB device remote wakeup signaling */
+#define USB_FS_DCTL_SDIS (uint32_t) (1 << 1) /* USB device soft disconnect */
+#define USB_FS_DCTL_GINSTS \
+    (uint32_t) (1 << 2) /* USB device global IN NAK status */
+#define USB_FS_DCTL_GONSTS \
+    (uint32_t) (1 << 3) /* USB device global OUT NAK status */
+#define USB_FS_DCTL_TCTL_J (uint32_t) (1 << 4) /* USB device Test_J mode */
+#define USB_FS_DCTL_TCTL_K (uint32_t) (2 << 4) /* USB device Test_K mode */
+#define USB_FS_DCTL_TCTL_SE0_NAK \
+    (uint32_t) (3 << 4) /* USB device Test_SE0_NAK mode */
+#define USB_FS_DCTL_TCTL_PKT \
+    (uint32_t) (4 << 4) /* USB device Test_Packet mode */
+#define USB_FS_DCTL_TCTL_FEN \
+    (uint32_t) (5 << 4) /* USB device Test_Force_Enable mode */
+#define USB_FS_DCTL_SGINAK \
+    (uint32_t) (1 << 7) /* USB device set global IN NAK */
+#define USB_FS_DCTL_CGINAK \
+    (uint32_t) (1 << 8) /* USB device clear global IN NAK */
+#define USB_FS_DCTL_SGONAK \
+    (uint32_t) (1 << 9) /* USB device set global OUT NAK */
+#define USB_FS_DCTL_CGONAK \
+    (uint32_t) (1 << 10) /* USB device clear global OUT NAK */
+#define USB_FS_DCTL_POPRGDNE \
+    (uint32_t) (1 << 11) /* USB device power-no programming done */
+
+#define USB_FS_DSTS_SUSPSTS                          \
+    (uint32_t) (1 << 0) /* USB device suspend status \
+                         */
+#define USB_FS_DSTS_ENUMSPD \
+    (uint32_t) (3 << 1) /* USB device enumerated speed (Must == 3) */
+#define USB_FS_DSTS_ENUMSPD_FS \
+    (uint32_t) (3 << 1) /* USB device enumerated speed (Must == 3) */
+#define USB_FS_DSTS_EERR (uint32_t) (1 << 3) /* USB device erratic error */
+#define USB_FS_DSTS_FNSOF                                                  \
+    (uint32_t) (0x3FFF00) /* USB device frame number of received SOF (bits \
+                             21:8) */
+
+#define USB_FS_DIEPMSK_XFRCM \
+    (uint32_t) (1 << 0) /* USB device transfer completed interrupt mask */
+#define USB_FS_DIEPMSK_EPDM \
+    (uint32_t) (1 << 1) /* USB device endpoint disabled interrupt mask */
+#define USB_FS_DIEPMSK_TOM \
+    (uint32_t) (1 << 3) /* USB device timout condition mask */
+#define USB_FS_DIEPMSK_ITTXFEMSK                                           \
+    (uint32_t) (1 << 4) /* USB device IN token received when TX FIFO empty \
+                           mask */
+#define USB_FS_DIEPMSK_INEPNMM                                                \
+    (uint32_t) (1 << 5) /* USB device IN token received with EP mismatch mask \
+                         */
+#define USB_FS_DIEPMSK_INEPNEM \
+    (uint32_t) (1 << 6) /* USB device IN endpoint NAK effective mask */
+
+#define USB_FS_DOEPMSK_XFRCM \
+    (uint32_t) (1 << 0) /* USB device transfer completed interrupt mask */
+#define USB_FS_DOEPMSK_EPDM \
+    (uint32_t) (1 << 1) /* USB device endpoint disabled interrupt mask */
+#define USB_FS_DOEPMSK_STUPM \
+    (uint32_t) (1 << 3) /* USB device SETUP phase done mask */
+#define USB_FS_DOEPMSK_OTEPDM                                          \
+    (uint32_t) (1 << 4) /* USB device OUT token received when endpoint \
+                           disabled mask */
+
+#define USB_FS_DAINT_IEPINT(n) \
+    (uint32_t) (1 << n) /* USB device IN endpoint interrupt bits */
+#define USB_FS_DAINT_OEPINT(n) \
+    (uint32_t) (1 << (n + 16)) /* USB device OUT endpoint interrupt bits */
+
+#define USB_FS_DAINT_IEPM(n) \
+    (uint32_t) (1 << n) /* USB device IN endpoint interrupt mask bits */
+#define USB_FS_DAINT_OEPM(n)                                                  \
+    (uint32_t) (1 << (n + 16)) /* USB device OUT endpoint interrupt mask bits \
+                                */
+
+#define USB_FS_DIEPEMPMSK_INEPTXFEM(n)                                        \
+    (uint32_t) (1 << n) /* USB device IN EP TX FIFO empty interrupt mask bits \
+                         */
+
+#define USB_FS_DIEPCTL0_MPSIZE \
+    (uint32_t) (3 << 0) /* USB device endpoint 0 IN maximum packet size */
+#define USB_FS_DIEPCTL0_MPSIZE_64                                          \
+    (uint32_t) (0 << 0) /* USB device endpoint 0 IN maximum packet size 64 \
+                           bytes */
+#define USB_FS_DIEPCTL0_MPSIZE_32                                          \
+    (uint32_t) (1 << 0) /* USB device endpoint 0 IN maximum packet size 32 \
+                           bytes */
+#define USB_FS_DIEPCTL0_MPSIZE_16                                          \
+    (uint32_t) (2 << 0) /* USB device endpoint 0 IN maximum packet size 16 \
+                           bytes */
+#define USB_FS_DIEPCTL0_MPSIZE_8                                          \
+    (uint32_t) (3 << 0) /* USB device endpoint 0 IN maximum packet size 8 \
+                           bytes */
+#define USB_FS_DIEPCTL0_USBAEP                                           \
+    (uint32_t) (1 << 15) /* USB device endpoint 0 IN USB active endpoint \
+                            (always 1) */
+#define USB_FS_DIEPCTL0_NAKSTS \
+    (uint32_t) (1 << 17) /* USB device endpoint 0 IN NAK status */
+#define USB_FS_DIEPCTL0_STALL \
+    (uint32_t) (1 << 21) /* USB device endpoint 0 IN STALL handshake */
+#define USB_FS_DIEPCTL0_TXFNUM(n) \
+    (uint32_t) (n << 22) /* USB device endpoint 0 IN TX FIFO number */
+#define USB_FS_DIEPCTL0_CNAK \
+    (uint32_t) (1 << 26) /* USB device endpoint 0 IN clear NAK */
+#define USB_FS_DIEPCTL0_SNAK \
+    (uint32_t) (1 << 27) /* USB device endpoint 0 IN set NAK */
+#define USB_FS_DIEPCTL0_EPDIS \
+    (uint32_t) (1 << 30) /* USB device endpoint 0 IN endpoint disable */
+#define USB_FS_DIEPCTL0_EPENA \
+    (uint32_t) (1 << 31) /* USB device endpoint 0 IN endpoint enable */
+
+#define USB_FS_DIEPCTLx_MPSIZE(n)                                          \
+    (uint32_t) (n << 0) /* USB device endpoint x IN maximum packet size in \
+                           bytes (11 bits) */
+#define USB_FS_DIEPCTLx_USBAEP \
+    (uint32_t) (1 << 15) /* USB device endpoint x IN USB active endpoint */
+#define USB_FS_DIEPCTLx_EONUM_EVEN \
+    (uint32_t) (0 << 16) /* USB device endpoint x IN Odd frame */
+#define USB_FS_DIEPCTLx_EONUM_ODD \
+    (uint32_t) (1 << 16) /* USB device endpoint x IN Odd frame */
+#define USB_FS_DIEPCTLx_DPID_0 \
+    (uint32_t) (0 << 16) /* USB device endpoint x IN data PID 0 */
+#define USB_FS_DIEPCTLx_DPID_1 \
+    (uint32_t) (1 << 16) /* USB device endpoint x IN data PID 1 */
+#define USB_FS_DIEPCTLx_NAKSTS \
+    (uint32_t) (1 << 17) /* USB device endpoint x IN NAK status */
+#define USB_FS_DIEPCTLx_EPTYP_CTL \
+    (uint32_t) (0 << 18) /* USB device endpoint x IN type: control */
+#define USB_FS_DIEPCTLx_EPTYP_ISO \
+    (uint32_t) (1 << 18) /* USB device endpoint x IN type: isochronous */
+#define USB_FS_DIEPCTLx_EPTYP_BLK \
+    (uint32_t) (2 << 18) /* USB device endpoint x IN type: bulk */
+#define USB_FS_DIEPCTLx_EPTYP_INT \
+    (uint32_t) (3 << 18) /* USB device endpoint x IN type: interrupt */
+#define USB_FS_DIEPCTLx_STALL \
+    (uint32_t) (1 << 21) /* USB device endpoint x IN STALL handshake */
+#define USB_FS_DIEPCTLx_TXFNUM(n)                                            \
+    (uint32_t) (n << 22) /* USB device endpoint x IN TX FIFO number (4 bits) \
+                          */
+#define USB_FS_DIEPCTLx_CNAK \
+    (uint32_t) (1 << 26) /* USB device endpoint x IN clear NAK */
+#define USB_FS_DIEPCTLx_SNAK \
+    (uint32_t) (1 << 27) /* USB device endpoint x IN set NAK */
+#define USB_FS_DIEPCTLx_SD0PID \
+    (uint32_t) (1 << 28) /* USB device endpoint x IN set DATA0 PID */
+#define USB_FS_DIEPCTLx_SEVNFRM \
+    (uint32_t) (1 << 28) /* USB device endpoint x IN set even frame */
+#define USB_FS_DIEPCTLx_SODDFRM \
+    (uint32_t) (1 << 29) /* USB device endpoint x IN set odd frame */
+#define USB_FS_DIEPCTLx_EPDIS \
+    (uint32_t) (1 << 30) /* USB device endpoint x IN endpoint disable */
+#define USB_FS_DIEPCTLx_EPENA \
+    (uint32_t) (1 << 31) /* USB device endpoint x IN endpoint enable */
+
+#define USB_FS_DOEPCTL0_MPSIZE \
+    (uint32_t) (3 << 0) /* USB device endpoint 0 OUT maximum packet size */
+#define USB_FS_DOEPCTL0_MPSIZE_64                                           \
+    (uint32_t) (0 << 0) /* USB device endpoint 0 OUT maximum packet size 64 \
+                           bytes */
+#define USB_FS_DOEPCTL0_MPSIZE_32                                           \
+    (uint32_t) (1 << 0) /* USB device endpoint 0 OUT maximum packet size 32 \
+                           bytes */
+#define USB_FS_DOEPCTL0_MPSIZE_16                                           \
+    (uint32_t) (2 << 0) /* USB device endpoint 0 OUT maximum packet size 16 \
+                           bytes */
+#define USB_FS_DOEPCTL0_MPSIZE_8                                           \
+    (uint32_t) (3 << 0) /* USB device endpoint 0 OUT maximum packet size 8 \
+                           bytes */
+#define USB_FS_DOEPCTL0_USBAEP                                            \
+    (uint32_t) (1 << 15) /* USB device endpoint 0 OUT USB active endpoint \
+                            (always 1) */
+#define USB_FS_DOEPCTL0_NAKSTS \
+    (uint32_t) (1 << 17) /* USB device endpoint 0 OUT NAK status */
+#define USB_FS_DOEPCTL0_SNPM \
+    (uint32_t) (1 << 20) /* USB device endpoint 0 OUT snoop mode */
+#define USB_FS_DOEPCTL0_STALL \
+    (uint32_t) (1 << 21) /* USB device endpoint 0 OUT STALL handshake */
+#define USB_FS_DOEPCTL0_CNAK \
+    (uint32_t) (1 << 26) /* USB device endpoint 0 OUT clear NAK */
+#define USB_FS_DOEPCTL0_SNAK \
+    (uint32_t) (1 << 27) /* USB device endpoint 0 OUT set NAK */
+#define USB_FS_DOEPCTL0_EPDIS \
+    (uint32_t) (1 << 30) /* USB device endpoint 0 OUT endpoint disable */
+#define USB_FS_DOEPCTL0_EPENA \
+    (uint32_t) (1 << 31) /* USB device endpoint 0 OUT endpoint enable */
+
+#define USB_FS_DOEPCTLx_MPSIZE(n)                                           \
+    (uint32_t) (n << 0) /* USB device endpoint x OUT maximum packet size in \
+                           bytes (11 bits) */
+#define USB_FS_DOEPCTLx_USBAEP \
+    (uint32_t) (1 << 15) /* USB device endpoint x OUT USB active endpoint */
+#define USB_FS_DOEPCTLx_EONUM_EVEN \
+    (uint32_t) (0 << 16) /* USB device endpoint x OUT Odd frame */
+#define USB_FS_DOEPCTLx_EONUM_ODD \
+    (uint32_t) (1 << 16) /* USB device endpoint x OUT Odd frame */
+#define USB_FS_DOEPCTLx_DPID_0 \
+    (uint32_t) (0 << 16) /* USB device endpoint x OUT data PID 0 */
+#define USB_FS_DOEPCTLx_DPID_1 \
+    (uint32_t) (1 << 16) /* USB device endpoint x OUT data PID 1 */
+#define USB_FS_DOEPCTLx_NAKSTS \
+    (uint32_t) (1 << 17) /* USB device endpoint x OUT NAK status */
+#define USB_FS_DOEPCTLx_EPTYP_CTL \
+    (uint32_t) (0 << 18) /* USB device endpoint x OUT type: control */
+#define USB_FS_DOEPCTLx_EPTYP_ISO \
+    (uint32_t) (1 << 18) /* USB device endpoint x OUT type: isochronous */
+#define USB_FS_DOEPCTLx_EPTYP_BLK \
+    (uint32_t) (2 << 18) /* USB device endpoint x OUT type: bulk */
+#define USB_FS_DOEPCTLx_EPTYP_INT \
+    (uint32_t) (3 << 18) /* USB device endpoint x OUT type: interrupt */
+#define USB_FS_DOEPCTLx_SNPMN \
+    (uint32_t) (1 << 20) /* USB device endpoint x OUT snoop mode */
+#define USB_FS_DOEPCTLx_STALL \
+    (uint32_t) (1 << 21) /* USB device endpoint x OUT STALL handshake */
+#define USB_FS_DOEPCTLx_CNAK \
+    (uint32_t) (1 << 26) /* USB device endpoint x OUT clear NAK */
+#define USB_FS_DOEPCTLx_SNAK \
+    (uint32_t) (1 << 27) /* USB device endpoint x OUT set NAK */
+#define USB_FS_DOEPCTLx_SD0PID \
+    (uint32_t) (1 << 28) /* USB device endpoint x OUT set DATA0 PID */
+#define USB_FS_DOEPCTLx_SEVNFRM \
+    (uint32_t) (1 << 28) /* USB device endpoint x OUT set even frame */
+#define USB_FS_DOEPCTLx_SODDFRM \
+    (uint32_t) (1 << 29) /* USB device endpoint x OUT set odd frame */
+#define USB_FS_DOEPCTLx_EPDIS \
+    (uint32_t) (1 << 30) /* USB device endpoint x OUT endpoint disable */
+#define USB_FS_DOEPCTLx_EPENA \
+    (uint32_t) (1 << 31) /* USB device endpoint x OUT endpoint enable */
+
+#define USB_FS_DIEPINTx_XFRC                                          \
+    (uint32_t) (1 << 0) /* USB device endpoint x IN transfer complete \
+                           interrupt */
+#define USB_FS_DIEPINTx_EPDISD                                        \
+    (uint32_t) (1 << 1) /* USB device endpoint x IN endpoint disabled \
+                           interrupt */
+#define USB_FS_DIEPINTx_TOC \
+    (uint32_t) (1 << 3) /* USB device endpoint x IN timeout condition */
+#define USB_FS_DIEPINTx_ITTXFE                                             \
+    (uint32_t) (1 << 4) /* USB device endpoint x IN token received when TX \
+                           FIFO is empty */
+#define USB_FS_DIEPINTx_INEPNE \
+    (uint32_t) (1 << 6) /* USB device endpoint x IN endpoint NAK effective */
+#define USB_FS_DIEPINTx_TXFE \
+    (uint32_t) (1 << 7) /* USB device endpoint x IN TX FIFO empty */
+
+#define USB_FS_DOEPINTx_XFRC                                           \
+    (uint32_t) (1 << 0) /* USB device endpoint x OUT transfer complete \
+                           interrupt */
+#define USB_FS_DOEPINTx_EPDISD                                         \
+    (uint32_t) (1 << 1) /* USB device endpoint x OUT endpoint disabled \
+                           interrupt */
+#define USB_FS_DOEPINTx_STUP \
+    (uint32_t) (1 << 3) /* USB device endpoint x OUT SETUP phase complete */
+#define USB_FS_DOEPINTx_OTEPDIS                                           \
+    (uint32_t) (1 << 4) /* USB device endpoint x OUT token receieved when \
+                           endpoint disabled */
+#define USB_FS_DOEPINTx_B2BSTUP                                         \
+    (uint32_t) (1 << 6) /* USB device endpoint x OUT back-to-back SETUP \
+                           packets received */
+
+#define USB_FS_DIEPTSIZ0_XFRSIZ(n) \
+    (uint32_t) (n << 0) /* USB device endpoint 0 IN transfer size (7 bits) */
+#define USB_FS_DIEPTSIZ0_PKTCNT(n) \
+    (uint32_t) (n << 19) /* USB device endpoint 0 IN packet count */
+
+#define USB_FS_DIEPTSIZx_XFRSIZ(n) \
+    (uint32_t) (n << 0) /* USB device endpoint x IN transfer size (19 bits) */
+#define USB_FS_DIEPTSIZx_PKTCNT(n) \
+    (uint32_t) (n << 19) /* USB device endpoint x IN packet count (10 bits) */
+#define USB_FS_DIEPTSIZx_MCNT_1 \
+    (uint32_t) (1 << 29) /* USB device endpoint x IN multi count 1 */
+#define USB_FS_DIEPTSIZx_MCNT_2 \
+    (uint32_t) (2 << 29) /* USB device endpoint x IN multi count 1 */
+#define USB_FS_DIEPTSIZx_MCNT_3 \
+    (uint32_t) (3 << 29) /* USB device endpoint x IN multi count 1 */
+
+#define USB_FS_DOEPTSIZ0_XFRSIZ(n) \
+    (uint32_t) (n << 0) /* USB device endpoint 0 OUT transfer size (7 bits) */
+#define USB_FS_DOEPTSIZ0_PKTCNT(n) \
+    (uint32_t) (n << 19) /* USB device endpoint 0 OUT packet count */
+#define USB_FS_DOEPTSIZ0_STUPCNT(n)                                      \
+    (uint32_t) (n << 29) /* USB device endpoint 0 OUT back-to-back SETUP \
+                            packets allowed */
+
+#define USB_FS_DOEPTSIZx_XFRSIZ(n)                                           \
+    (uint32_t) (n << 0) /* USB device endpoint x OUT transfer size (19 bits) \
+                         */
+#define USB_FS_DOEPTSIZx_PKTCNT(n)                                           \
+    (uint32_t) (n << 19) /* USB device endpoint x OUT packet count (10 bits) \
+                          */
+#define USB_FS_DOEPTSIZx_STUPCNT(n)                                      \
+    (uint32_t) (n << 29) /* USB device endpoint x OUT back-to-back SETUP \
+                            packets allowed */
+#define USB_FS_DOEPTSIZx_RXDPID \
+    (uint32_t) (1 << 29 |       \
+                1 << 30) /* USB device endpoint x OUT received data PID */
 
 /* Powe and Clock Gating Control Register */
-#define USB_FS_PCGCCTL_STPPCLK          (uint32_t) (1 << 0)                                     /* USB stop PHY clock */
-#define USB_FS_PCGCCTL_GATEHCLK         (uint32_t) (1 << 1)                                     /* USB gate HCLK */
-#define USB_FS_PCGCCTL_PHYSUSP          (uint32_t) (1 << 4)                                     /* USB PHY suspended */
+#define USB_FS_PCGCCTL_STPPCLK (uint32_t) (1 << 0)  /* USB stop PHY clock */
+#define USB_FS_PCGCCTL_GATEHCLK (uint32_t) (1 << 1) /* USB gate HCLK */
+#define USB_FS_PCGCCTL_PHYSUSP (uint32_t) (1 << 4)  /* USB PHY suspended */
 
 /* FMC definition */
-#define FMC_R_BASE                      ((uint32_t) 0xA0000000)                                 /* FMC registers base address */
-
-#define FMC_Bank5_6_R_BASE              (FMC_R_BASE + 0x0140)
-
-#define FMC_Bank5_6_SDCR(n)             (volatile uint32_t *) (FMC_Bank5_6_R_BASE + 0x00 + (4*n))      /* SDRAM Control Register */
-#define FMC_Bank5_6_SDTR(n)             (volatile uint32_t *) (FMC_Bank5_6_R_BASE + 0x08 + (4*n))      /* SDRAM Timing Register */
-#define FMC_Bank5_6_SDCMR               (volatile uint32_t *) (FMC_Bank5_6_R_BASE + 0x10)      /* SDRAM Command Mode Register */
-#define FMC_Bank5_6_SDRTR               (volatile uint32_t *) (FMC_Bank5_6_R_BASE + 0x14)      /* SDRAM Refresh Timer Register */
-#define FMC_Bank5_6_SDSR                (volatile uint32_t *) (FMC_Bank5_6_R_BASE + 0x18)      /* SDRAM Status Register */
+#define FMC_R_BASE ((uint32_t) 0xA0000000) /* FMC registers base address */
+
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
+
+#define FMC_Bank5_6_SDCR(n)                            \
+    (volatile uint32_t *) (FMC_Bank5_6_R_BASE + 0x00 + \
+                           (4 * n)) /* SDRAM Control Register */
+#define FMC_Bank5_6_SDTR(n)                            \
+    (volatile uint32_t *) (FMC_Bank5_6_R_BASE + 0x08 + \
+                           (4 * n)) /* SDRAM Timing Register */
+#define FMC_Bank5_6_SDCMR                       \
+    (volatile uint32_t *) (FMC_Bank5_6_R_BASE + \
+                           0x10) /* SDRAM Command Mode Register */
+#define FMC_Bank5_6_SDRTR                       \
+    (volatile uint32_t *) (FMC_Bank5_6_R_BASE + \
+                           0x14) /* SDRAM Refresh Timer Register */
+#define FMC_Bank5_6_SDSR                        \
+    (volatile uint32_t *) (FMC_Bank5_6_R_BASE + \
+                           0x18) /* SDRAM Status Register */
 
 /* RCC_PLL_Clock definition */
-#define RCC_PLLSAIDivR_Div2             ((uint32_t)0x00000000)
-#define RCC_PLLSAIDivR_Div4             ((uint32_t)0x00010000)
-#define RCC_PLLSAIDivR_Div8             ((uint32_t)0x00020000)
-#define RCC_PLLSAIDivR_Div16            ((uint32_t)0x00030000)
+#define RCC_PLLSAIDivR_Div2 ((uint32_t) 0x00000000)
+#define RCC_PLLSAIDivR_Div4 ((uint32_t) 0x00010000)
+#define RCC_PLLSAIDivR_Div8 ((uint32_t) 0x00020000)
+#define RCC_PLLSAIDivR_Div16 ((uint32_t) 0x00030000)
 
 /* RCC_DCKCFGR definition */
-#define  RCC_DCKCFGR_PLLI2SDIVQ         ((uint32_t)0x0000001F)
-#define  RCC_DCKCFGR_PLLSAIDIVQ         ((uint32_t)0x00001F00)
-#define  RCC_DCKCFGR_PLLSAIDIVR         ((uint32_t)0x00030000)
-#define  RCC_DCKCFGR_SAI1ASRC           ((uint32_t)0x00300000)
-#define  RCC_DCKCFGR_SAI1BSRC           ((uint32_t)0x00C00000)
-#define  RCC_DCKCFGR_TIMPRE             ((uint32_t)0x01000000)
+#define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t) 0x0000001F)
+#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t) 0x00001F00)
+#define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t) 0x00030000)
+#define RCC_DCKCFGR_SAI1ASRC ((uint32_t) 0x00300000)
+#define RCC_DCKCFGR_SAI1BSRC ((uint32_t) 0x00C00000)
+#define RCC_DCKCFGR_TIMPRE ((uint32_t) 0x01000000)
 
 /* LTDC definition */
-#define LTDC_Layer_BASE(layer)          (LTDC_BASE + 0x84 + ((layer - 1) * 0x80))
-#define LTDC_Layer1                     1
-#define LTDC_Layer2                     2
-#define LTDC_Layer1_BASE                LTDC_Layer_BASE(LTDC_Layer1)
-#define LTDC_Layer2_BASE                LTDC_Layer_BASE(LTDC_Layer2)
-
-#define LTDC_SSCR                       (volatile uint32_t *) (LTDC_BASE + 0x08)                /* LTDC Synchronization Size Configuration Register */
-#define LTDC_BPCR                       (volatile uint32_t *) (LTDC_BASE + 0x0C)                /* LTDC Back Porch Configuration Register */
-#define LTDC_AWCR                       (volatile uint32_t *) (LTDC_BASE + 0x10)                /* LTDC Active Width Configuration Register */
-#define LTDC_TWCR                       (volatile uint32_t *) (LTDC_BASE + 0x14)                /* LTDC Total Width Configuration Register */
-#define LTDC_GCR                        (volatile uint32_t *) (LTDC_BASE + 0x18)                /* LTDC Global Control Register */
-#define LTDC_SRCR                       (volatile uint32_t *) (LTDC_BASE + 0x24)                /* LTDC Shadow Reload Configuration Register */
-#define LTDC_BCCR                       (volatile uint32_t *) (LTDC_BASE + 0x2C)                /* LTDC Background Color Configuration Register */
-#define LTDC_IER                        (volatile uint32_t *) (LTDC_BASE + 0x34)                /* LTDC Interrupt Enable Register */
-#define LTDC_ISR                        (volatile uint32_t *) (LTDC_BASE + 0x38)                /* LTDC Interrupt Status Register */
-#define LTDC_ICR                        (volatile uint32_t *) (LTDC_BASE + 0x3C)                /* LTDC Interrupt Clear Register */
-#define LTDC_LIPCR                      (volatile uint32_t *) (LTDC_BASE + 0x40)                /* LTDC Line Interrupt Position Configuration Register */
-#define LTDC_CPSR                       (volatile uint32_t *) (LTDC_BASE + 0x44)                /* LTDC Current Position Status Register */
-#define LTDC_CDSR                       (volatile uint32_t *) (LTDC_BASE + 0x48)                /* LTDC Current Display Status Register */
-
-#define LTDC_SSCR_VSH                   ((uint32_t)0x000007FF)                                  /* Vertical Synchronization Height */
-#define LTDC_SSCR_HSW                   ((uint32_t)0x0FFF0000)                                  /* Horizontal Synchronization Width */
-
-#define LTDC_BPCR_AVBP                  ((uint32_t)0x000007FF)                                  /* Accumulated Vertical Back Porch */
-#define LTDC_BPCR_AHBP                  ((uint32_t)0x0FFF0000)                                  /* Accumulated Horizontal Back Porch */
-
-#define LTDC_AWCR_AAH                   ((uint32_t)0x000007FF)                                  /* Accumulated Active heigh */
-#define LTDC_AWCR_AAW                   ((uint32_t)0x0FFF0000)                                  /* Accumulated Active Width */
-
-#define LTDC_TWCR_TOTALH                ((uint32_t)0x000007FF)                                  /* Total Heigh */
-#define LTDC_TWCR_TOTALW                ((uint32_t)0x0FFF0000)                                  /* Total Width */
-
-#define LTDC_GCR_LTDCEN                 ((uint32_t)0x00000001)                                  /* LCD-TFT controller enable bit */
-#define LTDC_GCR_DBW                    ((uint32_t)0x00000070)                                  /* Dither Blue Width */
-#define LTDC_GCR_DGW                    ((uint32_t)0x00000700)                                  /* Dither Green Width */
-#define LTDC_GCR_DRW                    ((uint32_t)0x00007000)                                  /* Dither Red Width */
-#define LTDC_GCR_DTEN                   ((uint32_t)0x00010000)                                  /* Dither Enable */
-#define LTDC_GCR_PCPOL                  ((uint32_t)0x10000000)                                  /* Pixel Clock Polarity */
-#define LTDC_GCR_DEPOL                  ((uint32_t)0x20000000)                                  /* Data Enable Polarity */
-#define LTDC_GCR_VSPOL                  ((uint32_t)0x40000000)                                  /* Vertical Synchronization Polarity */
-#define LTDC_GCR_HSPOL                  ((uint32_t)0x80000000)                                  /* Horizontal Synchronization Polarity */
-
-#define LTDC_SRCR_IMR                   ((uint32_t) 1 << 0)                                     /* Immediate Reload */
-#define LTDC_SRCR_VBR                   ((uint32_t) 1 << 1)                                     /* Vertical Blanking Reload */
-
-#define LTDC_BCCR_BCBLUE                ((uint32_t)0x000000FF)                                  /* Background Blue value */
-#define LTDC_BCCR_BCGREEN               ((uint32_t)0x0000FF00)                                  /* Background Green value */
-#define LTDC_BCCR_BCRED                 ((uint32_t)0x00FF0000)                                  /* Background Red value */
-
-#define LTDC_IER_LIE                    ((uint32_t) 1 << 0)                                    /* Line Interrupt Enable */
-#define LTDC_IER_FUIE                   ((uint32_t) 1 << 1)                                    /* FIFO Underrun Interrupt Enable */
-#define LTDC_IER_TERRIE                 ((uint32_t) 1 << 2)                                    /* Transfer Error Interrupt Enable */
-#define LTDC_IER_RRIE                   ((uint32_t) 1 << 3)                                    /* Register Reload interrupt enable */
-
-#define LTDC_ISR_LIF                    ((uint32_t) 1 << 0)                                    /* Line Interrupt Flag */
-#define LTDC_ISR_FUIF                   ((uint32_t) 1 << 1)                                    /* FIFO Underrun Interrupt Flag */
-#define LTDC_ISR_TERRIF                 ((uint32_t) 1 << 2)                                    /* Transfer Error Interrupt Flag */
-#define LTDC_ISR_RRIF                   ((uint32_t) 1 << 3)                                    /* Register Reload interrupt Flag */
-
-#define LTDC_ICR_CLIF                   ((uint32_t) 1 << 0)                                    /* Clears the Line Interrupt Flag */
-#define LTDC_ICR_CFUIF                  ((uint32_t) 1 << 1)                                    /* Clears the FIFO Underrun Interrupt Flag */
-#define LTDC_ICR_CTERRIF                ((uint32_t) 1 << 2)                                    /* Clears the Transfer Error Interrupt Flag */
-#define LTDC_ICR_CRRIF                  ((uint32_t) 1 << 3)                                    /* Clears Register Reload interrupt Flag */
-
-#define LTDC_LIPCR_LIPOS                ((uint32_t)0x000007FF)                                 /* Line Interrupt Position */
-
-#define LTDC_CPSR_CYPOS                 ((uint32_t)0x0000FFFF)                                 /* Current Y Position */
-#define LTDC_CPSR_CXPOS                 ((uint32_t)0xFFFF0000)                                 /* Current X Position */
-
-#define LTDC_CDSR_VDES                  ((uint32_t) 1 << 0)                                    /* Vertical Data Enable Status */
-#define LTDC_CDSR_HDES                  ((uint32_t) 1 << 1)                                    /* Horizontal Data Enable Status */
-#define LTDC_CDSR_VSYNCS                ((uint32_t) 1 << 2)                                    /* Vertical Synchronization Status */
-#define LTDC_CDSR_HSYNCS                ((uint32_t) 1 << 3)                                    /* Horizontal Synchronization Status */
-
-#define LTDC_Layer_CR(layer)            (volatile uint32_t *) (LTDC_Layer_BASE(layer) + 0x00)      /* Control Register */
-#define LTDC_Layer_WHPCR(layer)         (volatile uint32_t *) (LTDC_Layer_BASE(layer) + 0x04)      /* Window Horizontal Position Configuration Register */
-#define LTDC_Layer_WVPCR(layer)         (volatile uint32_t *) (LTDC_Layer_BASE(layer) + 0x08)      /* Window Vertical Position Configuration Register */
-#define LTDC_Layer_CKCR(layer)          (volatile uint32_t *) (LTDC_Layer_BASE(layer) + 0x0C)      /* Color Keying Configuration Register */
-#define LTDC_Layer_PFCR(layer)          (volatile uint32_t *) (LTDC_Layer_BASE(layer) + 0x10)      /* Pixel Format Configuration Register */
-#define LTDC_Layer_CACR(layer)          (volatile uint32_t *) (LTDC_Layer_BASE(layer) + 0x14)      /* Constant Alpha Configuration Register */
-#define LTDC_Layer_DCCR(layer)          (volatile uint32_t *) (LTDC_Layer_BASE(layer) + 0x18)      /* Default Color Configuration Register */
-#define LTDC_Layer_BFCR(layer)          (volatile uint32_t *) (LTDC_Layer_BASE(layer) + 0x1C)      /* Blending Factors Configuration Register */
-#define LTDC_Layer_CFBAR(layer)         (volatile uint32_t *) (LTDC_Layer_BASE(layer) + 0x28)      /* Color Frame Buffer Address Register */
-#define LTDC_Layer_CFBLR(layer)         (volatile uint32_t *) (LTDC_Layer_BASE(layer) + 0x2C)      /* Color Frame Buffer Length Register */
-#define LTDC_Layer_CFBLNR(layer)        (volatile uint32_t *) (LTDC_Layer_BASE(layer) + 0x30)      /* Color Frame Buffer Line Number Register */
+#define LTDC_Layer_BASE(layer) (LTDC_BASE + 0x84 + ((layer - 1) * 0x80))
+#define LTDC_Layer1 1
+#define LTDC_Layer2 2
+#define LTDC_Layer1_BASE LTDC_Layer_BASE(LTDC_Layer1)
+#define LTDC_Layer2_BASE LTDC_Layer_BASE(LTDC_Layer2)
+
+#define LTDC_SSCR                                                         \
+    (volatile uint32_t *) (LTDC_BASE + 0x08) /* LTDC Synchronization Size \
+                                                Configuration Register */
+#define LTDC_BPCR                      \
+    (volatile uint32_t *) (LTDC_BASE + \
+                           0x0C) /* LTDC Back Porch Configuration Register */
+#define LTDC_AWCR      \
+    (volatile uint32_t \
+         *) (LTDC_BASE + 0x10) /* LTDC Active Width Configuration Register */
+#define LTDC_TWCR                      \
+    (volatile uint32_t *) (LTDC_BASE + \
+                           0x14) /* LTDC Total Width Configuration Register */
+#define LTDC_GCR                                                             \
+    (volatile uint32_t *) (LTDC_BASE + 0x18) /* LTDC Global Control Register \
+                                              */
+#define LTDC_SRCR      \
+    (volatile uint32_t \
+         *) (LTDC_BASE + 0x24) /* LTDC Shadow Reload Configuration Register */
+#define LTDC_BCCR                                                     \
+    (volatile uint32_t *) (LTDC_BASE + 0x2C) /* LTDC Background Color \
+                                                Configuration Register */
+#define LTDC_IER                       \
+    (volatile uint32_t *) (LTDC_BASE + \
+                           0x34) /* LTDC Interrupt Enable Register */
+#define LTDC_ISR                       \
+    (volatile uint32_t *) (LTDC_BASE + \
+                           0x38) /* LTDC Interrupt Status Register */
+#define LTDC_ICR                                                              \
+    (volatile uint32_t *) (LTDC_BASE + 0x3C) /* LTDC Interrupt Clear Register \
+                                              */
+#define LTDC_LIPCR                                                           \
+    (volatile uint32_t *) (LTDC_BASE + 0x40) /* LTDC Line Interrupt Position \
+                                                Configuration Register */
+#define LTDC_CPSR                      \
+    (volatile uint32_t *) (LTDC_BASE + \
+                           0x44) /* LTDC Current Position Status Register */
+#define LTDC_CDSR                      \
+    (volatile uint32_t *) (LTDC_BASE + \
+                           0x48) /* LTDC Current Display Status Register */
+
+#define LTDC_SSCR_VSH \
+    ((uint32_t) 0x000007FF) /* Vertical Synchronization Height */
+#define LTDC_SSCR_HSW \
+    ((uint32_t) 0x0FFF0000) /* Horizontal Synchronization Width */
+
+#define LTDC_BPCR_AVBP \
+    ((uint32_t) 0x000007FF) /* Accumulated Vertical Back Porch */
+#define LTDC_BPCR_AHBP \
+    ((uint32_t) 0x0FFF0000) /* Accumulated Horizontal Back Porch */
+
+#define LTDC_AWCR_AAH ((uint32_t) 0x000007FF) /* Accumulated Active heigh */
+#define LTDC_AWCR_AAW ((uint32_t) 0x0FFF0000) /* Accumulated Active Width */
+
+#define LTDC_TWCR_TOTALH ((uint32_t) 0x000007FF) /* Total Heigh */
+#define LTDC_TWCR_TOTALW ((uint32_t) 0x0FFF0000) /* Total Width */
+
+#define LTDC_GCR_LTDCEN \
+    ((uint32_t) 0x00000001)                  /* LCD-TFT controller enable bit */
+#define LTDC_GCR_DBW ((uint32_t) 0x00000070) /* Dither Blue Width */
+#define LTDC_GCR_DGW ((uint32_t) 0x00000700) /* Dither Green Width */
+#define LTDC_GCR_DRW ((uint32_t) 0x00007000) /* Dither Red Width */
+#define LTDC_GCR_DTEN ((uint32_t) 0x00010000)  /* Dither Enable */
+#define LTDC_GCR_PCPOL ((uint32_t) 0x10000000) /* Pixel Clock Polarity */
+#define LTDC_GCR_DEPOL ((uint32_t) 0x20000000) /* Data Enable Polarity */
+#define LTDC_GCR_VSPOL \
+    ((uint32_t) 0x40000000) /* Vertical Synchronization Polarity */
+#define LTDC_GCR_HSPOL \
+    ((uint32_t) 0x80000000) /* Horizontal Synchronization Polarity */
+
+#define LTDC_SRCR_IMR ((uint32_t) 1 << 0) /* Immediate Reload */
+#define LTDC_SRCR_VBR ((uint32_t) 1 << 1) /* Vertical Blanking Reload */
+
+#define LTDC_BCCR_BCBLUE ((uint32_t) 0x000000FF)  /* Background Blue value */
+#define LTDC_BCCR_BCGREEN ((uint32_t) 0x0000FF00) /* Background Green value */
+#define LTDC_BCCR_BCRED ((uint32_t) 0x00FF0000)   /* Background Red value */
+
+#define LTDC_IER_LIE ((uint32_t) 1 << 0)  /* Line Interrupt Enable */
+#define LTDC_IER_FUIE ((uint32_t) 1 << 1) /* FIFO Underrun Interrupt Enable */
+#define LTDC_IER_TERRIE \
+    ((uint32_t) 1 << 2) /* Transfer Error Interrupt Enable */
+#define LTDC_IER_RRIE                                       \
+    ((uint32_t) 1 << 3) /* Register Reload interrupt enable \
+                         */
+
+#define LTDC_ISR_LIF ((uint32_t) 1 << 0)  /* Line Interrupt Flag */
+#define LTDC_ISR_FUIF ((uint32_t) 1 << 1) /* FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF                                                    \
+    ((uint32_t) 1 << 2)                   /* Transfer Error Interrupt Flag \
+                                           */
+#define LTDC_ISR_RRIF ((uint32_t) 1 << 3) /* Register Reload interrupt Flag */
+
+#define LTDC_ICR_CLIF ((uint32_t) 1 << 0) /* Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF \
+    ((uint32_t) 1 << 1) /* Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF \
+    ((uint32_t) 1 << 2) /* Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF \
+    ((uint32_t) 1 << 3) /* Clears Register Reload interrupt Flag */
+
+#define LTDC_LIPCR_LIPOS ((uint32_t) 0x000007FF) /* Line Interrupt Position */
+
+#define LTDC_CPSR_CYPOS ((uint32_t) 0x0000FFFF) /* Current Y Position */
+#define LTDC_CPSR_CXPOS ((uint32_t) 0xFFFF0000) /* Current X Position */
+
+#define LTDC_CDSR_VDES ((uint32_t) 1 << 0) /* Vertical Data Enable Status */
+#define LTDC_CDSR_HDES ((uint32_t) 1 << 1) /* Horizontal Data Enable Status */
+#define LTDC_CDSR_VSYNCS \
+    ((uint32_t) 1 << 2) /* Vertical Synchronization Status */
+#define LTDC_CDSR_HSYNCS \
+    ((uint32_t) 1 << 3) /* Horizontal Synchronization Status */
+
+#define LTDC_Layer_CR(layer)                                                  \
+    (volatile uint32_t *) (LTDC_Layer_BASE(layer) + 0x00) /* Control Register \
+                                                           */
+#define LTDC_Layer_WHPCR(layer)       \
+    (volatile uint32_t                \
+         *) (LTDC_Layer_BASE(layer) + \
+             0x04) /* Window Horizontal Position Configuration Register */
+#define LTDC_Layer_WVPCR(layer)       \
+    (volatile uint32_t                \
+         *) (LTDC_Layer_BASE(layer) + \
+             0x08) /* Window Vertical Position Configuration Register */
+#define LTDC_Layer_CKCR(layer)                      \
+    (volatile uint32_t *) (LTDC_Layer_BASE(layer) + \
+                           0x0C) /* Color Keying Configuration Register */
+#define LTDC_Layer_PFCR(layer)                      \
+    (volatile uint32_t *) (LTDC_Layer_BASE(layer) + \
+                           0x10) /* Pixel Format Configuration Register */
+#define LTDC_Layer_CACR(layer)                      \
+    (volatile uint32_t *) (LTDC_Layer_BASE(layer) + \
+                           0x14) /* Constant Alpha Configuration Register */
+#define LTDC_Layer_DCCR(layer)                      \
+    (volatile uint32_t *) (LTDC_Layer_BASE(layer) + \
+                           0x18) /* Default Color Configuration Register */
+#define LTDC_Layer_BFCR(layer)                      \
+    (volatile uint32_t *) (LTDC_Layer_BASE(layer) + \
+                           0x1C) /* Blending Factors Configuration Register */
+#define LTDC_Layer_CFBAR(layer)                     \
+    (volatile uint32_t *) (LTDC_Layer_BASE(layer) + \
+                           0x28) /* Color Frame Buffer Address Register */
+#define LTDC_Layer_CFBLR(layer)                     \
+    (volatile uint32_t *) (LTDC_Layer_BASE(layer) + \
+                           0x2C) /* Color Frame Buffer Length Register */
+#define LTDC_Layer_CFBLNR(layer)                    \
+    (volatile uint32_t *) (LTDC_Layer_BASE(layer) + \
+                           0x30) /* Color Frame Buffer Line Number Register */
 
 #endif
diff --git a/include/platform/stm32f429/sdram.h b/include/platform/stm32f429/sdram.h
index abdb63ab..63717f15 100644
--- a/include/platform/stm32f429/sdram.h
+++ b/include/platform/stm32f429/sdram.h
@@ -4,22 +4,22 @@
 #include <platform/link.h>
 #include <platform/stm32f429/registers.h>
 
-#define SDRAM_MEMORY_WIDTH    FMC_SDMemory_Width_16b
-#define SDRAM_CAS_LATENCY    FMC_CAS_Latency_3
-#define SDCLOCK_PERIOD    FMC_SDClock_Period_2
-#define SDRAM_READBURST    FMC_Read_Burst_Disable
+#define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_16b
+#define SDRAM_CAS_LATENCY FMC_CAS_Latency_3
+#define SDCLOCK_PERIOD FMC_SDClock_Period_2
+#define SDRAM_READBURST FMC_Read_Burst_Disable
 
-#define SDRAM_MODEREG_BURST_LENGTH_1             ((uint16_t)0x0000)
-#define SDRAM_MODEREG_BURST_LENGTH_2             ((uint16_t)0x0001)
-#define SDRAM_MODEREG_BURST_LENGTH_4             ((uint16_t)0x0002)
-#define SDRAM_MODEREG_BURST_LENGTH_8             ((uint16_t)0x0004)
-#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL      ((uint16_t)0x0000)
-#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED     ((uint16_t)0x0008)
-#define SDRAM_MODEREG_CAS_LATENCY_2              ((uint16_t)0x0020)
-#define SDRAM_MODEREG_CAS_LATENCY_3              ((uint16_t)0x0030)
-#define SDRAM_MODEREG_OPERATING_MODE_STANDARD    ((uint16_t)0x0000)
-#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
-#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200)
+#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t) 0x0000)
+#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t) 0x0001)
+#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t) 0x0002)
+#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t) 0x0004)
+#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t) 0x0000)
+#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t) 0x0008)
+#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t) 0x0020)
+#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t) 0x0030)
+#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t) 0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t) 0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t) 0x0200)
 
 void sdram_init(void);
 
diff --git a/include/platform/stm32f429/spi.h b/include/platform/stm32f429/spi.h
index 1d55c665..ecce69ef 100644
--- a/include/platform/stm32f429/spi.h
+++ b/include/platform/stm32f429/spi.h
@@ -4,27 +4,27 @@
 #include <platform/link.h>
 #include <platform/stm32f429/registers.h>
 
-#define SPI_I2S_FLAG_RXNE               (uint16_t) (1 << 0)
-#define SPI_I2S_FLAG_TXE                (uint16_t) (1 << 1)
-#define I2S_FLAG_CHSIDE                 (uint16_t) (1 << 2)
-#define I2S_FLAG_UDR                    (uint16_t) (1 << 3)
-#define SPI_FLAG_CRCERR                 (uint16_t) (1 << 4)
-#define SPI_FLAG_MODF                   (uint16_t) (1 << 5)
-#define SPI_I2S_FLAG_OVR                (uint16_t) (1 << 6)
-#define SPI_I2S_FLAG_BSY                (uint16_t) (1 << 7)
-#define SPI_I2S_FLAG_TIFRFE             (uint16_t) (1 << 8)
+#define SPI_I2S_FLAG_RXNE (uint16_t) (1 << 0)
+#define SPI_I2S_FLAG_TXE (uint16_t) (1 << 1)
+#define I2S_FLAG_CHSIDE (uint16_t) (1 << 2)
+#define I2S_FLAG_UDR (uint16_t) (1 << 3)
+#define SPI_FLAG_CRCERR (uint16_t) (1 << 4)
+#define SPI_FLAG_MODF (uint16_t) (1 << 5)
+#define SPI_I2S_FLAG_OVR (uint16_t) (1 << 6)
+#define SPI_I2S_FLAG_BSY (uint16_t) (1 << 7)
+#define SPI_I2S_FLAG_TIFRFE (uint16_t) (1 << 8)
 
 
 struct spi_cfg {
-	uint16_t direction;
-	uint16_t mode;
-	uint16_t size;
-	uint16_t cpol;
-	uint16_t cpha;
-	uint16_t nss;
-	uint16_t baudrate;
-	uint16_t firstbit;
-	uint16_t crcpolynomial;
+    uint16_t direction;
+    uint16_t mode;
+    uint16_t size;
+    uint16_t cpol;
+    uint16_t cpha;
+    uint16_t nss;
+    uint16_t baudrate;
+    uint16_t firstbit;
+    uint16_t crcpolynomial;
 };
 
 void spi_config(uint32_t spix, struct spi_cfg *spi_init);
diff --git a/include/platform/stm32f429/syscfg.h b/include/platform/stm32f429/syscfg.h
index 171fc0cd..49b588c9 100644
--- a/include/platform/stm32f429/syscfg.h
+++ b/include/platform/stm32f429/syscfg.h
@@ -10,19 +10,18 @@
 
 static inline void memory_remap_flash(void)
 {
-	*SYSCFG_MEMRMP = 0x0;
+    *SYSCFG_MEMRMP = 0x0;
 }
 
 static inline void memory_remap_sysflash(void)
 {
-	*SYSCFG_MEMRMP = 0x1;
+    *SYSCFG_MEMRMP = 0x1;
 }
 
 
 static inline void memory_remap_sram(void)
 {
-	*SYSCFG_MEMRMP = 0x3;
+    *SYSCFG_MEMRMP = 0x3;
 }
 
 #endif
-
diff --git a/include/platform/stm32f429/systick.h b/include/platform/stm32f429/systick.h
index 0cf25f31..40eb3e9b 100644
--- a/include/platform/stm32f429/systick.h
+++ b/include/platform/stm32f429/systick.h
@@ -3,8 +3,8 @@
 
 #include <platform/stm32f429/registers.h>
 
-#define CORE_CLOCK		(0x0a037a00) /* 168MHz */
-#define SYSTICK_MAXRELOAD	(0x00ffffff)
+#define CORE_CLOCK (0x0a037a00) /* 168MHz */
+#define SYSTICK_MAXRELOAD (0x00ffffff)
 
 void init_systick(uint32_t tick_reload, uint32_t tick_next_reload);
 void systick_disable(void);
diff --git a/include/platform/stm32f429/usart.h b/include/platform/stm32f429/usart.h
index ced3b47f..ff9ef3eb 100644
--- a/include/platform/stm32f429/usart.h
+++ b/include/platform/stm32f429/usart.h
@@ -6,55 +6,57 @@
 #ifndef PLATFORM_STM32F429_USART_H_
 #define PLATFORM_STM32F429_USART_H_
 
-#include <platform/stm32f429/registers.h>
 #include <platform/stm32f429/gpio.h>
+#include <platform/stm32f429/registers.h>
 
 struct usart_dev {
-	uint32_t u_num;
-	uint32_t baud;
-	uint32_t base;
-	volatile uint32_t *rcc_apbenr;
-	uint32_t rcc_reset;
-	struct gpio_cfg tx;
-	struct gpio_cfg rx;
+    uint32_t u_num;
+    uint32_t baud;
+    uint32_t base;
+    volatile uint32_t *rcc_apbenr;
+    uint32_t rcc_reset;
+    struct gpio_cfg tx;
+    struct gpio_cfg rx;
 };
 
 #define USART_NUM 4
 
 /* status bit */
-#define USART_CTS	((uint16_t) (0x1 << 9))
-#define USART_LBD	((uint16_t) (0x1 << 8))
-#define USART_TXE	((uint16_t) (0x1 << 7))
-#define USART_TC	((uint16_t) (0x1 << 6))
-#define USART_RXNE	((uint16_t) (0x1 << 5))
-#define USART_IDLE	((uint16_t) (0x1 << 4))
-#define USART_ORE	((uint16_t) (0x1 << 3))
-#define USART_NF	((uint16_t) (0x1 << 2))
-#define USART_FE	((uint16_t) (0x1 << 1))
-#define USART_PE	((uint16_t) (0x1 << 0))
-
-
-#define USART_IT_CR1	(0xc << 8)
-#define USART_IT_CR2	(0x10 << 8)
-#define USART_IT_CR3	(0x14 << 8)
-
-#define USART_IT_PE	((uint16_t) USART_IT_CR1 | 0x8)
-#define USART_IT_TXE	((uint16_t) USART_IT_CR1 | 0x7)
-#define USART_IT_TC	((uint16_t) USART_IT_CR1 | 0x6)
-#define USART_IT_RXNE	((uint16_t) USART_IT_CR1 | 0x5)
-#define USART_IT_IDLE	((uint16_t) USART_IT_CR1 | 0x4)
-#define USART_IT_LBD	((uint16_t) USART_IT_CR2 | 0x6)
-#define USART_IT_CTS	((uint16_t) USART_IT_CR3 | 0xa)
-#define USART_IT_ERR	((uint16_t) USART_IT_CR3 | 0x0)
-
-#define USART_IT_ENB_REG_OFFSET(USART_IT)	((USART_IT >> 8) & 0xff)
-#define USART_IT_POSITION(USART_IT)		(USART_IT & 0xff)
+#define USART_CTS ((uint16_t) (0x1 << 9))
+#define USART_LBD ((uint16_t) (0x1 << 8))
+#define USART_TXE ((uint16_t) (0x1 << 7))
+#define USART_TC ((uint16_t) (0x1 << 6))
+#define USART_RXNE ((uint16_t) (0x1 << 5))
+#define USART_IDLE ((uint16_t) (0x1 << 4))
+#define USART_ORE ((uint16_t) (0x1 << 3))
+#define USART_NF ((uint16_t) (0x1 << 2))
+#define USART_FE ((uint16_t) (0x1 << 1))
+#define USART_PE ((uint16_t) (0x1 << 0))
+
+
+#define USART_IT_CR1 (0xc << 8)
+#define USART_IT_CR2 (0x10 << 8)
+#define USART_IT_CR3 (0x14 << 8)
+
+#define USART_IT_PE ((uint16_t) USART_IT_CR1 | 0x8)
+#define USART_IT_TXE ((uint16_t) USART_IT_CR1 | 0x7)
+#define USART_IT_TC ((uint16_t) USART_IT_CR1 | 0x6)
+#define USART_IT_RXNE ((uint16_t) USART_IT_CR1 | 0x5)
+#define USART_IT_IDLE ((uint16_t) USART_IT_CR1 | 0x4)
+#define USART_IT_LBD ((uint16_t) USART_IT_CR2 | 0x6)
+#define USART_IT_CTS ((uint16_t) USART_IT_CR3 | 0xa)
+#define USART_IT_ERR ((uint16_t) USART_IT_CR3 | 0x0)
+
+#define USART_IT_ENB_REG_OFFSET(USART_IT) ((USART_IT >> 8) & 0xff)
+#define USART_IT_POSITION(USART_IT) (USART_IT & 0xff)
 
 void usart_init(struct usart_dev *usart);
 void usart_putc(struct usart_dev *usart, uint8_t c);
 uint8_t usart_getc(struct usart_dev *usart);
 int usart_status(struct usart_dev *usart, uint16_t st);
 int usart_interrupt_status(struct usart_dev *usart, uint16_t it);
-void usart_config_interrupt(struct usart_dev *usart, uint16_t it, uint8_t state);
+void usart_config_interrupt(struct usart_dev *usart,
+                            uint16_t it,
+                            uint8_t state);
 
 #endif /* PLATFORM_STM32F429_USART_H_ */
diff --git a/include/sched.h b/include/sched.h
index 5cb50191..7505a87e 100644
--- a/include/sched.h
+++ b/include/sched.h
@@ -23,26 +23,26 @@ struct tcb;
  */
 
 /* Number of priority levels (0 = highest, 31 = lowest) */
-#define SCHED_PRIORITY_LEVELS	32
+#define SCHED_PRIORITY_LEVELS 32
 
 /* Priority assignments for system threads */
-#define SCHED_PRIO_SOFTIRQ	0	/* Kernel softirq thread */
-#define SCHED_PRIO_INTR		1	/* Interrupt handler threads */
-#define SCHED_PRIO_ROOT		2	/* Root thread */
-#define SCHED_PRIO_IPC		3	/* IPC fast path */
-#define SCHED_PRIO_NORMAL_MIN	4	/* Normal threads start here */
-#define SCHED_PRIO_NORMAL_MAX	30	/* Normal threads end here */
-#define SCHED_PRIO_IDLE		31	/* Idle thread (always lowest) */
+#define SCHED_PRIO_SOFTIRQ 0     /* Kernel softirq thread */
+#define SCHED_PRIO_INTR 1        /* Interrupt handler threads */
+#define SCHED_PRIO_ROOT 2        /* Root thread */
+#define SCHED_PRIO_IPC 3         /* IPC fast path */
+#define SCHED_PRIO_NORMAL_MIN 4  /* Normal threads start here */
+#define SCHED_PRIO_NORMAL_MAX 30 /* Normal threads end here */
+#define SCHED_PRIO_IDLE 31       /* Idle thread (always lowest) */
 
 /* Default priority for user threads */
-#define SCHED_PRIO_DEFAULT	16
+#define SCHED_PRIO_DEFAULT 16
 
 /**
  * Linked list node for ready queue.
  * Embedded in TCB for zero-allocation enqueueing.
  */
 typedef struct sched_link {
-	struct sched_link *prev, *next;
+    struct sched_link *prev, *next;
 } sched_link_t;
 
 /* Scheduler initialization */
diff --git a/include/softirq.h b/include/softirq.h
index dbd378d3..755ab246 100644
--- a/include/softirq.h
+++ b/include/softirq.h
@@ -9,22 +9,22 @@
 #include <types.h>
 
 typedef enum {
-	KTE_SOFTIRQ,		/* Kernel timer event */
-	ASYNC_SOFTIRQ,		/* Asynchronius event */
-	SYSCALL_SOFTIRQ,
+    KTE_SOFTIRQ,   /* Kernel timer event */
+    ASYNC_SOFTIRQ, /* Asynchronius event */
+    SYSCALL_SOFTIRQ,
 
 #ifdef CONFIG_KDB
-	KDB_SOFTIRQ,		/* KDB should have least priority */
+    KDB_SOFTIRQ, /* KDB should have least priority */
 #endif
 
-	NR_SOFTIRQ
+    NR_SOFTIRQ
 } softirq_type_t;
 
 typedef void (*softirq_handler_t)(void);
 
 typedef struct {
-	uint32_t 		  schedule;
-	softirq_handler_t handler;
+    uint32_t schedule;
+    softirq_handler_t handler;
 } softirq_t;
 
 void softirq_register(softirq_type_t type, softirq_handler_t handler);
diff --git a/include/syscall.h b/include/syscall.h
index 6abbee53..df00d334 100644
--- a/include/syscall.h
+++ b/include/syscall.h
@@ -7,18 +7,18 @@
 #define SYSCALL_H_
 
 typedef enum {
-	SYS_KERNEL_INTERFACE,		/* Not used, KIP is mapped */
-	SYS_EXCHANGE_REGISTERS,
-	SYS_THREAD_CONTROL,
-	SYS_SYSTEM_CLOCK,
-	SYS_THREAD_SWITCH,
-	SYS_SCHEDULE,
-	SYS_IPC,
-	SYS_LIPC,
-	SYS_UNMAP,
-	SYS_SPACE_CONTROL,
-	SYS_PROCESSOR_CONTROL,
-	SYS_MEMORY_CONTROL,
+    SYS_KERNEL_INTERFACE, /* Not used, KIP is mapped */
+    SYS_EXCHANGE_REGISTERS,
+    SYS_THREAD_CONTROL,
+    SYS_SYSTEM_CLOCK,
+    SYS_THREAD_SWITCH,
+    SYS_SCHEDULE,
+    SYS_IPC,
+    SYS_LIPC,
+    SYS_UNMAP,
+    SYS_SPACE_CONTROL,
+    SYS_PROCESSOR_CONTROL,
+    SYS_MEMORY_CONTROL,
 } syscall_t;
 
 void svc_handler(void);
diff --git a/include/thread.h b/include/thread.h
index 278d8e4a..f223ae3d 100644
--- a/include/thread.h
+++ b/include/thread.h
@@ -6,10 +6,10 @@
 #ifndef THREAD_H_
 #define THREAD_H_
 
-#include <types.h>
+#include <kip.h>
 #include <lib/ktable.h>
 #include <memory.h>
-#include <kip.h>
+#include <types.h>
 
 #include <l4/utcb.h>
 
@@ -34,47 +34,47 @@
  *   - L4_ANYTHREAD  - anythread
  */
 
-#define L4_NILTHREAD		0
-#define L4_ANYLOCALTHREAD	0xFFFFFFC0
-#define L4_ANYTHREAD		0xFFFFFFFF
+#define L4_NILTHREAD 0
+#define L4_ANYLOCALTHREAD 0xFFFFFFC0
+#define L4_ANYTHREAD 0xFFFFFFFF
 
-#define GLOBALID_TO_TID(id)	(id >> 14)
-#define TID_TO_GLOBALID(id)	(id << 14)
+#define GLOBALID_TO_TID(id) (id >> 14)
+#define TID_TO_GLOBALID(id) (id << 14)
 
-#define THREAD_BY_TID(id)	 thread_by_globalid(TID_TO_GLOBALID(id))
+#define THREAD_BY_TID(id) thread_by_globalid(TID_TO_GLOBALID(id))
 
 /* Stack canary for overflow detection.
  * Placed at stack_base (lowest address). Checked on context switch.
  */
-#define STACK_CANARY		0xDEADBEEF
+#define STACK_CANARY 0xDEADBEEF
 
 typedef enum {
-	THREAD_IDLE,
-	THREAD_KERNEL,
-	THREAD_ROOT,
-	THREAD_INTERRUPT,
-	THREAD_IRQ_REQUEST,
-	THREAD_LOG,
-	THREAD_SYS	= 16,				/* Systembase */
-	THREAD_USER	= CONFIG_INTR_THREAD_MAX	/* Userbase */
+    THREAD_IDLE,
+    THREAD_KERNEL,
+    THREAD_ROOT,
+    THREAD_INTERRUPT,
+    THREAD_IRQ_REQUEST,
+    THREAD_LOG,
+    THREAD_SYS = 16,                     /* Systembase */
+    THREAD_USER = CONFIG_INTR_THREAD_MAX /* Userbase */
 } thread_tag_t;
 
 typedef enum {
-	T_INACTIVE,
-	T_RUNNABLE,
-	T_SVC_BLOCKED,
-	T_RECV_BLOCKED,
-	T_SEND_BLOCKED
+    T_INACTIVE,
+    T_RUNNABLE,
+    T_SVC_BLOCKED,
+    T_RECV_BLOCKED,
+    T_SEND_BLOCKED
 } thread_state_t;
 
 typedef struct {
-	uint32_t sp;
-	uint32_t ret;
-	uint32_t ctl;
-	uint32_t regs[8];
+    uint32_t sp;
+    uint32_t ret;
+    uint32_t ctl;
+    uint32_t regs[8];
 #ifdef CONFIG_FPU
-	uint64_t fp_regs[8];
-	uint32_t fp_flag;
+    uint64_t fp_regs[8];
+    uint32_t fp_flag;
 #endif
 } context_t;
 
@@ -85,35 +85,35 @@ typedef struct {
  * Contains pointers to thread's UTCB (User TCB) and address space
  */
 struct tcb {
-	/* Hot scheduler fields - Cache Line 0 */
-	struct {
-		struct tcb *prev, *next;
-	} sched_link;			/* 8 bytes (0-7) */
+    /* Hot scheduler fields - Cache Line 0 */
+    struct {
+        struct tcb *prev, *next;
+    } sched_link; /* 8 bytes (0-7) */
 
-	thread_state_t state;		/* 4 bytes (8-11) */
-	uint8_t priority;		/* 1 byte  (12) - effective priority */
-	uint8_t base_priority;		/* 1 byte  (13) - natural priority */
-	uint8_t _sched_pad[2];		/* 2 bytes (14-15) - Alignment */
+    thread_state_t state;  /* 4 bytes (8-11) */
+    uint8_t priority;      /* 1 byte  (12) - effective priority */
+    uint8_t base_priority; /* 1 byte  (13) - natural priority */
+    uint8_t _sched_pad[2]; /* 2 bytes (14-15) - Alignment */
 
-	l4_thread_t t_globalid;		/* 4 bytes (16-19) */
-	l4_thread_t t_localid;		/* 4 bytes (20-23) */
+    l4_thread_t t_globalid; /* 4 bytes (16-19) */
+    l4_thread_t t_localid;  /* 4 bytes (20-23) */
 
-	memptr_t stack_base;		/* 4 bytes (24-27) */
-	size_t stack_size;		/* 4 bytes (28-31) */
-	/* End of Cache Line 0 (32 bytes) */
+    memptr_t stack_base; /* 4 bytes (24-27) */
+    size_t stack_size;   /* 4 bytes (28-31) */
+    /* End of Cache Line 0 (32 bytes) */
 
-	context_t ctx;
+    context_t ctx;
 
-	as_t *as;
-	struct utcb *utcb;
+    as_t *as;
+    struct utcb *utcb;
 
-	l4_thread_t ipc_from;
+    l4_thread_t ipc_from;
 
-	struct tcb *t_sibling;
-	struct tcb *t_parent;
-	struct tcb *t_child;
+    struct tcb *t_sibling;
+    struct tcb *t_parent;
+    struct tcb *t_child;
 
-	uint32_t timeout_event;
+    uint32_t timeout_event;
 };
 typedef struct tcb tcb_t;
 
@@ -122,16 +122,16 @@ typedef struct tcb tcb_t;
  */
 static inline void thread_init_canary(tcb_t *thr)
 {
-	if (thr->stack_base)
-		*((uint32_t *) thr->stack_base) = STACK_CANARY;
+    if (thr->stack_base)
+        *((uint32_t *) thr->stack_base) = STACK_CANARY;
 }
 
 /* Check stack canary. Returns 1 if valid, 0 if corrupted. */
 static inline int thread_check_canary(tcb_t *thr)
 {
-	if (!thr->stack_base)
-		return 1;  /* No stack tracking, skip check */
-	return *((uint32_t *) thr->stack_base) == STACK_CANARY;
+    if (!thr->stack_base)
+        return 1; /* No stack tracking, skip check */
+    return *((uint32_t *) thr->stack_base) == STACK_CANARY;
 }
 
 void thread_init_subsys(void);
diff --git a/include/types.h b/include/types.h
index 18a21a5d..99c56c7e 100644
--- a/include/types.h
+++ b/include/types.h
@@ -15,8 +15,8 @@ typedef uint32_t l4_thread_t;
 
 #if !defined(__cplusplus) && !defined(c_plusplus)
 typedef uint32_t bool;
-#define true	1
-#define false	0
+#define true 1
+#define false 0
 #endif
 
 #ifndef _SIZE_T_
@@ -24,10 +24,8 @@ typedef uint32_t bool;
 typedef uint32_t size_t;
 #endif
 
-#define NULL \
-	((ptr_t) 0x0)
+#define NULL ((ptr_t) 0x0)
 
-#define ALIGNED(size, align) \
-	(size / align) + ((size & (align - 1)) != 0)
+#define ALIGNED(size, align) (size / align) + ((size & (align - 1)) != 0)
 
 #endif /* TYPES_H_ */
diff --git a/kernel/debug.c b/kernel/debug.c
index a448db63..da9c2f42 100644
--- a/kernel/debug.c
+++ b/kernel/debug.c
@@ -3,28 +3,28 @@
  * found in the LICENSE file.
  */
 
+#include <debug.h>
 #include <lib/stdarg.h>
 #include <lib/stdio.h>
-#include <debug.h>
 
 #ifdef CONFIG_DEBUG
 
 dbg_layer_t dbg_layer;
 
-void dbg_printf(dbg_layer_t layer, char* fmt, ...)
+void dbg_printf(dbg_layer_t layer, char *fmt, ...)
 {
-	va_list va;
-	va_start(va, fmt);
-	dbg_vprintf(layer, fmt, va);
-	va_end(va);
+    va_list va;
+    va_start(va, fmt);
+    dbg_vprintf(layer, fmt, va);
+    va_end(va);
 }
 
 void dbg_vprintf(dbg_layer_t layer, char *fmt, va_list va)
 {
-	if (layer != DL_EMERG && !(dbg_layer & layer))
-		return;
+    if (layer != DL_EMERG && !(dbg_layer & layer))
+        return;
 
-	__l4_vprintf(fmt, va);
+    __l4_vprintf(fmt, va);
 }
 
-#endif	/* CONFIG_DEBUG */
+#endif /* CONFIG_DEBUG */
diff --git a/kernel/error.c b/kernel/error.c
index 813f6e9d..8b8ff1d4 100644
--- a/kernel/error.c
+++ b/kernel/error.c
@@ -3,15 +3,15 @@
  * found in the LICENSE file.
  */
 
-#include <error.h>
-#include <thread.h>
 #include <debug.h>
+#include <error.h>
 #include <kdb.h>
-#include <platform/irq.h>
+#include <lib/stdarg.h>
 #include <platform/armv7m.h>
-#include <platform/link.h>
 #include <platform/debug_device.h>
-#include <lib/stdarg.h>
+#include <platform/irq.h>
+#include <platform/link.h>
+#include <thread.h>
 
 #ifdef LOADER
 extern uint32_t stack_end;
@@ -22,71 +22,71 @@ extern volatile tcb_t *caller;
 
 void set_user_error(tcb_t *thread, enum user_error_t error)
 {
-	assert(thread && thread->utcb);
+    assert(thread && thread->utcb);
 
-	thread->utcb->error_code = error;
+    thread->utcb->error_code = error;
 }
 
 void set_caller_error(enum user_error_t error)
 {
-	if (caller)
-		set_user_error((tcb_t *) caller, error);
-	else
-		panic("User-level error %d during in-kernel call!", error);
+    if (caller)
+        set_user_error((tcb_t *) caller, error);
+    else
+        panic("User-level error %d during in-kernel call!", error);
 }
 #endif
 
 #ifdef CONFIG_PANIC_DUMP_STACK
 static void panic_dump_stack(void)
 {
-	uint32_t *current_sp = (uint32_t *) read_msp();
-	int word = 0;
+    uint32_t *current_sp = (uint32_t *) read_msp();
+    int word = 0;
 
-	dbg_puts("\n\nStack dump:\n");
+    dbg_puts("\n\nStack dump:\n");
 
 #ifdef LOADER
-	while (current_sp < &stack_end) {
+    while (current_sp < &stack_end) {
 #else
-	while (current_sp < &kernel_stack_end) {
+    while (current_sp < &kernel_stack_end) {
 #endif
-		dbg_printf(DL_EMERG, "%p ", *(++current_sp));
+        dbg_printf(DL_EMERG, "%p ", *(++current_sp));
 
-		if (++word % 8 == 0)
-			dbg_putchar('\n');
-	}
+        if (++word % 8 == 0)
+            dbg_putchar('\n');
+    }
 }
-#endif	/* CONFIG_PANIC_DUMP_STACK */
+#endif /* CONFIG_PANIC_DUMP_STACK */
 
 void panic_impl(char *fmt, ...)
 {
-	va_list va;
-	va_start(va, fmt);
+    va_list va;
+    va_start(va, fmt);
 
-	dbg_start_panic();
+    dbg_start_panic();
 
-	irq_disable();
-	dbg_vprintf(DL_EMERG, fmt, va);
+    irq_disable();
+    dbg_vprintf(DL_EMERG, fmt, va);
 
 #ifndef LOADER
 #ifdef CONFIG_KDB
-	kdb_dump_error();
+    kdb_dump_error();
 #endif
 #endif
 
 #ifdef CONFIG_PANIC_DUMP_STACK
-	panic_dump_stack();
+    panic_dump_stack();
 #endif
 
-	va_end(va);
+    va_end(va);
 
-	while (1)
-		/* */ ;
+    while (1)
+        /* */;
 }
 
 void assert_impl(int cond, const char *condstr, const char *funcname)
 {
-	if (!cond) {
-		/* Write to buffer */
-		panic("Assertion %s failed @%s\n", condstr, funcname);
-	}
+    if (!cond) {
+        /* Write to buffer */
+        panic("Assertion %s failed @%s\n", condstr, funcname);
+    }
 }
diff --git a/kernel/fpage.c b/kernel/fpage.c
index 92b6aa2a..2dc721e8 100644
--- a/kernel/fpage.c
+++ b/kernel/fpage.c
@@ -7,13 +7,13 @@
  * Fpage chain functions
  */
 
-#include <types.h>
-#include <memory.h>
 #include <fpage.h>
 #include <fpage_impl.h>
+#include <memory.h>
+#include <types.h>
 
-#include <error.h>
 #include <debug.h>
+#include <error.h>
 
 DECLARE_KTABLE(fpage_t, fpage_table, CONFIG_MAX_FPAGES);
 
@@ -34,17 +34,17 @@ DECLARE_KTABLE(fpage_t, fpage_table, CONFIG_MAX_FPAGES);
  */
 static int fp_addr_log2(memptr_t addr)
 {
-	int shift = 0;
+    int shift = 0;
 
-	if (addr == 0)
-		return CONFIG_LARGEST_FPAGE_SHIFT;
+    if (addr == 0)
+        return CONFIG_LARGEST_FPAGE_SHIFT;
 
-	while ((addr & 1) == 0) {
-		++shift;
-		addr >>= 1;
-	}
+    while ((addr & 1) == 0) {
+        ++shift;
+        addr >>= 1;
+    }
 
-	return shift;
+    return shift;
 }
 
 /*
@@ -54,22 +54,22 @@ static int fp_addr_log2(memptr_t addr)
  */
 static int fp_size_log2(size_t size)
 {
-	int shift = 0;
+    int shift = 0;
 
-	if (size == 0)
-		return 0;
+    if (size == 0)
+        return 0;
 
-	while (size > 1) {
-		++shift;
-		size >>= 1;
-	}
+    while (size > 1) {
+        ++shift;
+        size >>= 1;
+    }
 
-	return shift;
+    return shift;
 }
 
 void fpages_init(void)
 {
-	ktable_init(&fpage_table);
+    ktable_init(&fpage_table);
 }
 
 /**
@@ -81,36 +81,35 @@ void fpages_init(void)
  */
 static void insert_fpage_chain_to_as(as_t *as, fpage_t *first, fpage_t *last)
 {
-	fpage_t *fp;
-
-	/* NULL chain is a no-op */
-	if (!first || !last)
-		return;
-
-	fp = as->first;
-
-	if (!fp) {
-		/* First chain in AS */
-		as->first = first;
-		return;
-	}
-
-	if (last->fpage.base < fp->fpage.base) {
-		/* Add chain into beginning */
-		last->as_next = as->first;
-		as->first = first;
-	} else {
-		/* Search for chain in the middle */
-		while (fp->as_next) {
-			if (FPAGE_BASE(last) < FPAGE_BASE(fp->as_next)) {
-				last->as_next = fp->as_next;
-				break;
-			}
-			fp = fp->as_next;
-		}
-		fp->as_next = first;
-	}
-
+    fpage_t *fp;
+
+    /* NULL chain is a no-op */
+    if (!first || !last)
+        return;
+
+    fp = as->first;
+
+    if (!fp) {
+        /* First chain in AS */
+        as->first = first;
+        return;
+    }
+
+    if (last->fpage.base < fp->fpage.base) {
+        /* Add chain into beginning */
+        last->as_next = as->first;
+        as->first = first;
+    } else {
+        /* Search for chain in the middle */
+        while (fp->as_next) {
+            if (FPAGE_BASE(last) < FPAGE_BASE(fp->as_next)) {
+                last->as_next = fp->as_next;
+                break;
+            }
+            fp = fp->as_next;
+        }
+        fp->as_next = first;
+    }
 }
 
 /**
@@ -122,7 +121,7 @@ static void insert_fpage_chain_to_as(as_t *as, fpage_t *first, fpage_t *last)
  */
 static void insert_fpage_to_as(as_t *as, fpage_t *fpage)
 {
-	insert_fpage_chain_to_as(as, fpage, fpage);
+    insert_fpage_chain_to_as(as, fpage, fpage);
 }
 
 /**
@@ -134,8 +133,8 @@ static void insert_fpage_to_as(as_t *as, fpage_t *fpage)
  */
 static void remove_fpage_from_as(as_t *as, fpage_t *fp)
 {
-	remove_fpage_from_list(as, fp, first, as_next);
-	remove_fpage_from_list(as, fp, mpu_first, mpu_next);
+    remove_fpage_from_list(as, fp, first, as_next);
+    remove_fpage_from_list(as, fp, mpu_first, mpu_next);
 }
 
 /* FIXME: Support for bit-bang regions. */
@@ -149,39 +148,38 @@ static int fpage_alloc_count = 0;
 
 static fpage_t *create_fpage(memptr_t base, size_t shift, int mpid)
 {
-	fpage_t *fpage = (fpage_t *) ktable_alloc(&fpage_table);
-
-	if (!fpage) {
-		dbg_printf(DL_KDB,
-		           "FPAGE: alloc failed! count=%d base=%p shift=%d mpid=%d\n",
-		           fpage_alloc_count, base, shift, mpid);
-		return NULL;
-	}
-
-	fpage_alloc_count++;
-	if ((fpage_alloc_count % 50) == 0)
-		dbg_printf(DL_KDB, "FPAGE: allocated %d fpages\n",
-		           fpage_alloc_count);
-
-	fpage->as_next = NULL;
-	fpage->map_next = fpage; 	/* That is first fpage in mapping */
-	fpage->mpu_next = NULL;
-	fpage->fpage.mpid = mpid;
-	fpage->fpage.flags = 0;
-	fpage->fpage.rwx = MP_USER_PERM(mempool_getbyid(mpid)->flags);
-
-	fpage->fpage.base = base;
-	fpage->fpage.shift = shift;
-
-	if (mempool_getbyid(mpid)->flags & MP_MAP_ALWAYS)
-		fpage->fpage.flags |= FPAGE_ALWAYS;
-
-	return fpage;
+    fpage_t *fpage = (fpage_t *) ktable_alloc(&fpage_table);
+
+    if (!fpage) {
+        dbg_printf(DL_KDB,
+                   "FPAGE: alloc failed! count=%d base=%p shift=%d mpid=%d\n",
+                   fpage_alloc_count, base, shift, mpid);
+        return NULL;
+    }
+
+    fpage_alloc_count++;
+    if ((fpage_alloc_count % 50) == 0)
+        dbg_printf(DL_KDB, "FPAGE: allocated %d fpages\n", fpage_alloc_count);
+
+    fpage->as_next = NULL;
+    fpage->map_next = fpage; /* That is first fpage in mapping */
+    fpage->mpu_next = NULL;
+    fpage->fpage.mpid = mpid;
+    fpage->fpage.flags = 0;
+    fpage->fpage.rwx = MP_USER_PERM(mempool_getbyid(mpid)->flags);
+
+    fpage->fpage.base = base;
+    fpage->fpage.shift = shift;
+
+    if (mempool_getbyid(mpid)->flags & MP_MAP_ALWAYS)
+        fpage->fpage.flags |= FPAGE_ALWAYS;
+
+    return fpage;
 }
 
 void destroy_fpage(fpage_t *fpage)
 {
-	ktable_free(&fpage_table, fpage);
+    ktable_free(&fpage_table, fpage);
 }
 
 /**
@@ -190,357 +188,360 @@ void destroy_fpage(fpage_t *fpage)
  */
 static void free_fpage_chain(fpage_t *first)
 {
-	fpage_t *fp, *next;
+    fpage_t *fp, *next;
 
-	for (fp = first; fp; fp = next) {
-		next = fp->as_next;
-		ktable_free(&fpage_table, fp);
-	}
+    for (fp = first; fp; fp = next) {
+        next = fp->as_next;
+        ktable_free(&fpage_table, fp);
+    }
 }
 
-static void create_fpage_chain(memptr_t base, size_t size, int mpid,
-                               fpage_t **pfirst, fpage_t **plast)
+static void create_fpage_chain(memptr_t base,
+                               size_t size,
+                               int mpid,
+                               fpage_t **pfirst,
+                               fpage_t **plast)
 {
-	int shift, sshift, bshift;
-	fpage_t *fpage = NULL;
-	fpage_t *newfp;
-
-	while (size) {
-		/* Select minimum of base alignment and largest fitting size.
-		 * bshift: base alignment (trailing zeros) ensures MPU alignment
-		 * sshift: floor(log2(size)) gives largest power-of-2 that fits
-		 */
-		bshift = fp_addr_log2(base);
-		sshift = fp_size_log2(size);
-
-		shift = (bshift < sshift) ? bshift : sshift;
-
-		newfp = create_fpage(base, shift, mpid);
-		if (!newfp) {
-			/* Allocation failed - leave chain incomplete */
-			dbg_printf(DL_KDB,
-			           "FPAGE: chain alloc failed at base=%p\n", base);
-			return;
-		}
-
-		if (!*pfirst) {
-			/* Create first page */
-			fpage = newfp;
-			*pfirst = fpage;
-			*plast = fpage;
-		} else {
-			/* Build chain */
-			fpage->as_next = newfp;
-			fpage = fpage->as_next;
-			*plast = fpage;
-		}
-
-		size -= ((memptr_t)1 << shift);
-		base += ((memptr_t)1 << shift);
-	}
+    int shift, sshift, bshift;
+    fpage_t *fpage = NULL;
+    fpage_t *newfp;
+
+    while (size) {
+        /* Select minimum of base alignment and largest fitting size.
+         * bshift: base alignment (trailing zeros) ensures MPU alignment
+         * sshift: floor(log2(size)) gives largest power-of-2 that fits
+         */
+        bshift = fp_addr_log2(base);
+        sshift = fp_size_log2(size);
+
+        shift = (bshift < sshift) ? bshift : sshift;
+
+        newfp = create_fpage(base, shift, mpid);
+        if (!newfp) {
+            /* Allocation failed - leave chain incomplete */
+            dbg_printf(DL_KDB, "FPAGE: chain alloc failed at base=%p\n", base);
+            return;
+        }
+
+        if (!*pfirst) {
+            /* Create first page */
+            fpage = newfp;
+            *pfirst = fpage;
+            *plast = fpage;
+        } else {
+            /* Build chain */
+            fpage->as_next = newfp;
+            fpage = fpage->as_next;
+            *plast = fpage;
+        }
+
+        size -= ((memptr_t) 1 << shift);
+        base += ((memptr_t) 1 << shift);
+    }
 }
 
 fpage_t *split_fpage(as_t *as, fpage_t *fpage, memptr_t split, int rl)
 {
-	memptr_t base = fpage->fpage.base,
-	         end = fpage->fpage.base + ((memptr_t)1 << fpage->fpage.shift);
-	fpage_t *lfirst = NULL, *llast = NULL, *rfirst = NULL, *rlast = NULL;
-
-	if (!as || !fpage)
-		return NULL;
-
-	/* For rl=1 (right side), round DOWN to include the split point.
-	 * For rl=0 (left side), round UP to exclude past the split point.
-	 */
-	if (rl)
-		split = mempool_align_base(fpage->fpage.mpid, split);
-	else
-		split = mempool_align(fpage->fpage.mpid, split);
-
-	/* Check if split point is valid after alignment.
-	 * Must be strictly between base and end.
-	 */
-	if (split <= base || split >= end) {
-		return fpage;
-	}
-
-	if (fpage->map_next != fpage) {
-		/* Splitting not supported for mapped pages */
-		/* UNIMPLIMENTED */
-		return NULL;
-	}
-
-	/* Split fpage into two chains of fpages */
-	create_fpage_chain(base, (split - base),
-	                   fpage->fpage.mpid, &lfirst, &llast);
-	create_fpage_chain(split, (end - split),
-	                   fpage->fpage.mpid, &rfirst, &rlast);
-
-	/* Check if both chains were created successfully.
-	 * If either failed, keep the original fpage intact.
-	 */
-	if (!lfirst || !llast || !rfirst || !rlast) {
-		/* Free any partially created chains */
-		fpage_t *fp, *next;
-		for (fp = lfirst; fp; fp = next) {
-			next = fp->as_next;
-			ktable_free(&fpage_table, fp);
-		}
-		for (fp = rfirst; fp; fp = next) {
-			next = fp->as_next;
-			ktable_free(&fpage_table, fp);
-		}
-		dbg_printf(DL_KDB,
-		           "FPAGE: split failed, keeping original (base=%p split=%p)\n",
-		           base, split);
-		return NULL;
-	}
-
-	remove_fpage_from_as(as, fpage);
-	ktable_free(&fpage_table, fpage);
-
-	insert_fpage_chain_to_as(as, lfirst, llast);
-	insert_fpage_chain_to_as(as, rfirst, rlast);
-
-	if (rl == 0)
-		return llast;
-	return rfirst;
+    memptr_t base = fpage->fpage.base,
+             end = fpage->fpage.base + ((memptr_t) 1 << fpage->fpage.shift);
+    fpage_t *lfirst = NULL, *llast = NULL, *rfirst = NULL, *rlast = NULL;
+
+    if (!as || !fpage)
+        return NULL;
+
+    /* For rl=1 (right side), round DOWN to include the split point.
+     * For rl=0 (left side), round UP to exclude past the split point.
+     */
+    if (rl)
+        split = mempool_align_base(fpage->fpage.mpid, split);
+    else
+        split = mempool_align(fpage->fpage.mpid, split);
+
+    /* Check if split point is valid after alignment.
+     * Must be strictly between base and end.
+     */
+    if (split <= base || split >= end) {
+        return fpage;
+    }
+
+    if (fpage->map_next != fpage) {
+        /* Splitting not supported for mapped pages */
+        /* UNIMPLIMENTED */
+        return NULL;
+    }
+
+    /* Split fpage into two chains of fpages */
+    create_fpage_chain(base, (split - base), fpage->fpage.mpid, &lfirst,
+                       &llast);
+    create_fpage_chain(split, (end - split), fpage->fpage.mpid, &rfirst,
+                       &rlast);
+
+    /* Check if both chains were created successfully.
+     * If either failed, keep the original fpage intact.
+     */
+    if (!lfirst || !llast || !rfirst || !rlast) {
+        /* Free any partially created chains */
+        fpage_t *fp, *next;
+        for (fp = lfirst; fp; fp = next) {
+            next = fp->as_next;
+            ktable_free(&fpage_table, fp);
+        }
+        for (fp = rfirst; fp; fp = next) {
+            next = fp->as_next;
+            ktable_free(&fpage_table, fp);
+        }
+        dbg_printf(DL_KDB,
+                   "FPAGE: split failed, keeping original (base=%p split=%p)\n",
+                   base, split);
+        return NULL;
+    }
+
+    remove_fpage_from_as(as, fpage);
+    ktable_free(&fpage_table, fpage);
+
+    insert_fpage_chain_to_as(as, lfirst, llast);
+    insert_fpage_chain_to_as(as, rfirst, rlast);
+
+    if (rl == 0)
+        return llast;
+    return rfirst;
 }
 
 
-int assign_fpages_ext(int mpid, as_t *as, memptr_t base, size_t size,
-                      fpage_t **pfirst, fpage_t **plast)
+int assign_fpages_ext(int mpid,
+                      as_t *as,
+                      memptr_t base,
+                      size_t size,
+                      fpage_t **pfirst,
+                      fpage_t **plast)
 {
-	fpage_t **fp;
-	memptr_t  end;
-
-	if (size <= 0)
-		return -1;
-
-	/* if mpid is unknown, search using base addr */
-	if (mpid == -1) {
-		if ((mpid = mempool_search(base, size)) == -1) {
-			/* Cannot find appropriate mempool, return error */
-			return -1;
-		}
-	}
-
-	/* Check if mempool supports fpage creation */
-	if (!(mempool_getbyid(mpid)->flags & MP_FPAGE_MASK)) {
-		/* Mempool does not support fpages (e.g., kernel text/data/bss) */
-		return -1;
-	}
-
-	end = base + size;
-
-	/* Overflow check: end must be greater than base */
-	if (end < base) {
-		dbg_printf(DL_KDB,
-		           "FPAGE: overflow in assign_fpages_ext base=%p size=%p\n",
-		           base, size);
-		return -1;
-	}
-
-	if (as) {
-		/* find unmapped space */
-		fp = &as->first;
-		while (base < end && *fp) {
-			if (base < FPAGE_BASE(*fp)) {
-				fpage_t *first = NULL, *last = NULL;
-				size = (end < FPAGE_BASE(*fp) ? end : FPAGE_BASE(*fp)) - base;
-
-				dbg_printf(DL_MEMORY,
-				           "MEM: fpage chain %s [b:%p, sz:%p] as %p\n",
-				           mempool_getbyid(mpid)->name, base, size, as);
-
-				{
-					/* Round UP base to prevent over-mapping.
-					 * S1 fix: mempool_align_base rounds DOWN,
-					 * granting access below requested address.
-					 */
-					memptr_t abase = mempool_align(mpid, base);
-					memptr_t aend = mempool_align(mpid, base + size);
-
-					/* Empty region after alignment: skip */
-					if (abase >= aend) {
-						base = FPAGE_BASE(*fp);
-						fp = &(*fp)->as_next;
-						continue;
-					}
-
-					create_fpage_chain(abase, aend - abase, mpid,
-					                   &first, &last);
-				}
-
-				/* NULL guard: create_fpage_chain may fail */
-				if (!first || !last) {
-					free_fpage_chain(first);
-					return -1;
-				}
-
-				last->as_next = *fp;
-				*fp = first;
-				fp = &last->as_next;
-
-				if (!*pfirst)
-					*pfirst = first;
-				*plast = last;
-
-				base = FPAGE_END(*fp);
-			} else if (base < FPAGE_END(*fp)) {
-				if (!*pfirst)
-					*pfirst = *fp;
-				*plast = *fp;
-
-				base = FPAGE_END(*fp);
-			}
-
-			fp = &(*fp)->as_next;
-		}
-
-		if (base < end) {
-			fpage_t *first = NULL, *last = NULL;
-			size = end - base;
-
-			dbg_printf(DL_MEMORY,
-			           "MEM: fpage chain %s [b:%p, sz:%p] as %p\n",
-			           mempool_getbyid(mpid)->name, base, size, as);
-
-			{
-				/* S1 fix: round UP base to prevent over-mapping */
-				memptr_t abase = mempool_align(mpid, base);
-				memptr_t aend = mempool_align(mpid, base + size);
-
-				/* Empty region check */
-				if (abase < aend) {
-					create_fpage_chain(abase, aend - abase, mpid,
-					                   &first, &last);
-				}
-			}
-
-			/* Only link if chain was created */
-			if (first && last) {
-				*fp = first;
-
-				if (!*pfirst)
-					*pfirst = first;
-				*plast = last;
-			}
-		}
-	} else {
-		dbg_printf(DL_MEMORY,
-		           "MEM: fpage chain %s [b:%p, sz:%p] as %p\n",
-		           mempool_getbyid(mpid)->name, base, size, as);
-
-		{
-			/* S1 fix: round UP base to prevent over-mapping */
-			memptr_t abase = mempool_align(mpid, base);
-			memptr_t aend = mempool_align(mpid, base + size);
-
-			/* Empty region check: return error if nothing to map */
-			if (abase >= aend)
-				return -1;
-
-			create_fpage_chain(abase, aend - abase, mpid, pfirst, plast);
-
-			/* Check if chain creation failed */
-			if (!*pfirst || !*plast) {
-				free_fpage_chain(*pfirst);
-				*pfirst = NULL;
-				*plast = NULL;
-				return -1;
-			}
-		}
-	}
-
-	return 0;
+    fpage_t **fp;
+    memptr_t end;
+
+    if (size <= 0)
+        return -1;
+
+    /* if mpid is unknown, search using base addr */
+    if (mpid == -1) {
+        if ((mpid = mempool_search(base, size)) == -1) {
+            /* Cannot find appropriate mempool, return error */
+            return -1;
+        }
+    }
+
+    /* Check if mempool supports fpage creation */
+    if (!(mempool_getbyid(mpid)->flags & MP_FPAGE_MASK)) {
+        /* Mempool does not support fpages (e.g., kernel text/data/bss) */
+        return -1;
+    }
+
+    end = base + size;
+
+    /* Overflow check: end must be greater than base */
+    if (end < base) {
+        dbg_printf(DL_KDB,
+                   "FPAGE: overflow in assign_fpages_ext base=%p size=%p\n",
+                   base, size);
+        return -1;
+    }
+
+    if (as) {
+        /* find unmapped space */
+        fp = &as->first;
+        while (base < end && *fp) {
+            if (base < FPAGE_BASE(*fp)) {
+                fpage_t *first = NULL, *last = NULL;
+                size = (end < FPAGE_BASE(*fp) ? end : FPAGE_BASE(*fp)) - base;
+
+                dbg_printf(DL_MEMORY,
+                           "MEM: fpage chain %s [b:%p, sz:%p] as %p\n",
+                           mempool_getbyid(mpid)->name, base, size, as);
+
+                {
+                    /* Round UP base to prevent over-mapping.
+                     * S1 fix: mempool_align_base rounds DOWN,
+                     * granting access below requested address.
+                     */
+                    memptr_t abase = mempool_align(mpid, base);
+                    memptr_t aend = mempool_align(mpid, base + size);
+
+                    /* Empty region after alignment: skip */
+                    if (abase >= aend) {
+                        base = FPAGE_BASE(*fp);
+                        fp = &(*fp)->as_next;
+                        continue;
+                    }
+
+                    create_fpage_chain(abase, aend - abase, mpid, &first,
+                                       &last);
+                }
+
+                /* NULL guard: create_fpage_chain may fail */
+                if (!first || !last) {
+                    free_fpage_chain(first);
+                    return -1;
+                }
+
+                last->as_next = *fp;
+                *fp = first;
+                fp = &last->as_next;
+
+                if (!*pfirst)
+                    *pfirst = first;
+                *plast = last;
+
+                base = FPAGE_END(*fp);
+            } else if (base < FPAGE_END(*fp)) {
+                if (!*pfirst)
+                    *pfirst = *fp;
+                *plast = *fp;
+
+                base = FPAGE_END(*fp);
+            }
+
+            fp = &(*fp)->as_next;
+        }
+
+        if (base < end) {
+            fpage_t *first = NULL, *last = NULL;
+            size = end - base;
+
+            dbg_printf(DL_MEMORY, "MEM: fpage chain %s [b:%p, sz:%p] as %p\n",
+                       mempool_getbyid(mpid)->name, base, size, as);
+
+            {
+                /* S1 fix: round UP base to prevent over-mapping */
+                memptr_t abase = mempool_align(mpid, base);
+                memptr_t aend = mempool_align(mpid, base + size);
+
+                /* Empty region check */
+                if (abase < aend) {
+                    create_fpage_chain(abase, aend - abase, mpid, &first,
+                                       &last);
+                }
+            }
+
+            /* Only link if chain was created */
+            if (first && last) {
+                *fp = first;
+
+                if (!*pfirst)
+                    *pfirst = first;
+                *plast = last;
+            }
+        }
+    } else {
+        dbg_printf(DL_MEMORY, "MEM: fpage chain %s [b:%p, sz:%p] as %p\n",
+                   mempool_getbyid(mpid)->name, base, size, as);
+
+        {
+            /* S1 fix: round UP base to prevent over-mapping */
+            memptr_t abase = mempool_align(mpid, base);
+            memptr_t aend = mempool_align(mpid, base + size);
+
+            /* Empty region check: return error if nothing to map */
+            if (abase >= aend)
+                return -1;
+
+            create_fpage_chain(abase, aend - abase, mpid, pfirst, plast);
+
+            /* Check if chain creation failed */
+            if (!*pfirst || !*plast) {
+                free_fpage_chain(*pfirst);
+                *pfirst = NULL;
+                *plast = NULL;
+                return -1;
+            }
+        }
+    }
+
+    return 0;
 }
 
 int assign_fpages(as_t *as, memptr_t base, size_t size)
 {
-	fpage_t *first = NULL, *last = NULL;
-	return assign_fpages_ext(-1, as, base, size, &first, &last);
+    fpage_t *first = NULL, *last = NULL;
+    return assign_fpages_ext(-1, as, base, size, &first, &last);
 }
 
 
 int map_fpage(as_t *src, as_t *dst, fpage_t *fpage, map_action_t action)
 {
-	fpage_t *fpmap;
+    fpage_t *fpmap;
 
-	/* NULL fpage or dst is a programming error - fail gracefully */
-	if (!fpage || !dst) {
-		dbg_printf(DL_KDB,
-		           "FPAGE: map_fpage NULL arg! fpage=%p dst=%p\n",
-		           fpage, dst);
-		return -1;
-	}
+    /* NULL fpage or dst is a programming error - fail gracefully */
+    if (!fpage || !dst) {
+        dbg_printf(DL_KDB, "FPAGE: map_fpage NULL arg! fpage=%p dst=%p\n",
+                   fpage, dst);
+        return -1;
+    }
 
-	fpmap = (fpage_t *) ktable_alloc(&fpage_table);
+    fpmap = (fpage_t *) ktable_alloc(&fpage_table);
 
-	if (!fpmap) {
-		dbg_printf(DL_KDB,
-		           "FPAGE: map alloc failed! src=%p dst=%p\n", src, dst);
-		return -1;
-	}
+    if (!fpmap) {
+        dbg_printf(DL_KDB, "FPAGE: map alloc failed! src=%p dst=%p\n", src,
+                   dst);
+        return -1;
+    }
 
-	fpmap->as_next = NULL;
-	fpmap->mpu_next = NULL;
+    fpmap->as_next = NULL;
+    fpmap->mpu_next = NULL;
 
-	/* Copy fpage description */
-	fpmap->raw[0] = fpage->raw[0];
-	fpmap->raw[1] = fpage->raw[1];
+    /* Copy fpage description */
+    fpmap->raw[0] = fpage->raw[0];
+    fpmap->raw[1] = fpage->raw[1];
 
-	/* Set flags correctly: preserve FPAGE_ALWAYS for MPU prioritization */
-	if (action == MAP)
-		fpage->fpage.flags |= FPAGE_MAPPED;
-	fpmap->fpage.flags = FPAGE_CLONE | (fpage->fpage.flags & FPAGE_ALWAYS);
+    /* Set flags correctly: preserve FPAGE_ALWAYS for MPU prioritization */
+    if (action == MAP)
+        fpage->fpage.flags |= FPAGE_MAPPED;
+    fpmap->fpage.flags = FPAGE_CLONE | (fpage->fpage.flags & FPAGE_ALWAYS);
 
-	/* Insert into mapee list */
-	fpmap->map_next = fpage->map_next;
-	fpage->map_next = fpmap;
+    /* Insert into mapee list */
+    fpmap->map_next = fpage->map_next;
+    fpage->map_next = fpmap;
 
-	/* Insert into AS */
-	insert_fpage_to_as(dst, fpmap);
+    /* Insert into AS */
+    insert_fpage_to_as(dst, fpmap);
 
-	dbg_printf(DL_MEMORY, "MEM: %s fpage %p [b:%p sz:2**%d] from %p to %p\n",
-	           (action == MAP) ? "mapped" : "granted", fpmap,
-	           FPAGE_BASE(fpmap), fpmap->fpage.shift, src, dst);
+    dbg_printf(DL_MEMORY, "MEM: %s fpage %p [b:%p sz:2**%d] from %p to %p\n",
+               (action == MAP) ? "mapped" : "granted", fpmap, FPAGE_BASE(fpmap),
+               fpmap->fpage.shift, src, dst);
 
-	return 0;
+    return 0;
 }
 
 int unmap_fpage(as_t *as, fpage_t *fpage)
 {
-	fpage_t *fpprev = fpage;
+    fpage_t *fpprev = fpage;
 
-	dbg_printf(DL_MEMORY, "MEM: unmapped fpage %p from %p\n", fpage, as);
+    dbg_printf(DL_MEMORY, "MEM: unmapped fpage %p from %p\n", fpage, as);
 
-	/* Fpages that are not mapped or granted
-	 * are destroyed with its AS
-	 */
-	if (!(fpage->fpage.flags & FPAGE_CLONE))
-		return -1;
+    /* Fpages that are not mapped or granted
+     * are destroyed with its AS
+     */
+    if (!(fpage->fpage.flags & FPAGE_CLONE))
+        return -1;
 
-	/* Find previous fpage in circular map list with cycle guard */
-	{
-		int guard = CONFIG_MAX_FPAGES;
-		while (fpprev->map_next != fpage && --guard > 0)
-			fpprev = fpprev->map_next;
+    /* Find previous fpage in circular map list with cycle guard */
+    {
+        int guard = CONFIG_MAX_FPAGES;
+        while (fpprev->map_next != fpage && --guard > 0)
+            fpprev = fpprev->map_next;
 
-		if (guard <= 0) {
-			dbg_printf(DL_KDB,
-			           "FPAGE: cycle detected in unmap_fpage %p\n", fpage);
-			return -1;
-		}
-	}
+        if (guard <= 0) {
+            dbg_printf(DL_KDB, "FPAGE: cycle detected in unmap_fpage %p\n",
+                       fpage);
+            return -1;
+        }
+    }
 
-	/* Clear flags */
-	fpprev->fpage.flags &= ~FPAGE_MAPPED;
+    /* Clear flags */
+    fpprev->fpage.flags &= ~FPAGE_MAPPED;
 
-	fpprev->map_next = fpage->map_next;
-	remove_fpage_from_as(as, fpage);
+    fpprev->map_next = fpage->map_next;
+    remove_fpage_from_as(as, fpage);
 
-	ktable_free(&fpage_table, fpage);
+    ktable_free(&fpage_table, fpage);
 
-	return 0;
+    return 0;
 }
diff --git a/kernel/init.c b/kernel/init.c
index b28aaa26..8d8e6af7 100644
--- a/kernel/init.c
+++ b/kernel/init.c
@@ -6,9 +6,9 @@
 #include <debug.h>
 #include <error.h>
 
-#include <syscall.h>
-#include <ktimer.h>
 #include <init_hook.h>
+#include <ktimer.h>
+#include <syscall.h>
 
 extern void __l4_start(void);
 extern void memmanage_handler(void);
@@ -17,71 +17,70 @@ extern void pendsv_handler(void);
 
 void busfault(void)
 {
-	while (1)
-		/* wait */ ;
+    while (1)
+        /* wait */;
 }
 
 void nointerrupt(void)
 {
-	while (1)
-		/* wait */ ;
+    while (1)
+        /* wait */;
 }
 
 void hard_fault_handler(void)
 {
-	/*
-	 * If we are here, it may mean currently executing priority is higher
-	 * than or equal to the priority of fault exception, inhibiting normal
-	 * preemption, then processor escalates the exception priority to
-	 * HardFault.
-	 */
-	panic("Kernel panic: Hard fault. Restarting\n");
+    /*
+     * If we are here, it may mean currently executing priority is higher
+     * than or equal to the priority of fault exception, inhibiting normal
+     * preemption, then processor escalates the exception priority to
+     * HardFault.
+     */
+    panic("Kernel panic: Hard fault. Restarting\n");
 }
 
 void nmi_handler(void)
 {
-	panic("Kernel panic: NMI. Restarting\n");
+    panic("Kernel panic: NMI. Restarting\n");
 }
 
 /*
  * Declare NVIC table
  */
 
-extern void (* const g_pfnVectors[])(void);
+extern void (*const g_pfnVectors[])(void);
 
 #include INC_PLAT(nvic.h)
 
 __ISR_VECTOR
-void (* const g_pfnVectors[])(void) = {
-	/* Core Level - ARM Cortex-M */
-	(void *) &kernel_stack_end,	/* initial stack pointer */
-	__l4_start,			/* reset handler */
-	nmi_handler,			/* NMI handler */
-	hard_fault_handler,		/* hard fault handler */
-	memmanage_handler,		/* MPU fault handler */
-	busfault,			/* bus fault handler */
-	nointerrupt,			/* usage fault handler */
-	0,				/* Reserved */
-	0,				/* Reserved */
-	0,				/* Reserved */
-	0,				/* Reserved */
-	svc_handler,			/* SVCall handler */
+void (*const g_pfnVectors[])(void) = {
+    /* Core Level - ARM Cortex-M */
+    (void *) &kernel_stack_end, /* initial stack pointer */
+    __l4_start,                 /* reset handler */
+    nmi_handler,                /* NMI handler */
+    hard_fault_handler,         /* hard fault handler */
+    memmanage_handler,          /* MPU fault handler */
+    busfault,                   /* bus fault handler */
+    nointerrupt,                /* usage fault handler */
+    0,                          /* Reserved */
+    0,                          /* Reserved */
+    0,                          /* Reserved */
+    0,                          /* Reserved */
+    svc_handler,                /* SVCall handler */
 #ifdef CONFIG_KPROBES
-	debugmon_handler,		/* Debug monitor handler */
+    debugmon_handler, /* Debug monitor handler */
 #else
-	nointerrupt,
+    nointerrupt,
 #endif
-	0,				/* Reserved */
-	pendsv_handler,			/* PendSV handler */
-	ktimer_handler, 		/* SysTick handler */
+    0,              /* Reserved */
+    pendsv_handler, /* PendSV handler */
+    ktimer_handler, /* SysTick handler */
 
-	/* Chip Level: vendor specific */
-	/* FIXME: use better IRQ vector generator */
+/* Chip Level: vendor specific */
+/* FIXME: use better IRQ vector generator */
 #include INC_PLAT(nvic_table.h)
 };
 
-#define MAX(a, b)			\
-	((a) > (b) ? (a) : (b))
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
 
 extern const init_struct init_hook_start[];
 extern const init_struct init_hook_end[];
@@ -89,17 +88,15 @@ static unsigned int last_level = 0;
 
 int run_init_hook(unsigned int level)
 {
-	unsigned int max_called_level = last_level;
+    unsigned int max_called_level = last_level;
 
-	for (const init_struct *ptr = init_hook_start;
-	     ptr != init_hook_end; ++ptr)
-		if ((ptr->level > last_level) &&
-		    (ptr->level <= level)) {
-			max_called_level = MAX(max_called_level, ptr->level);
-			ptr->hook();
-		}
+    for (const init_struct *ptr = init_hook_start; ptr != init_hook_end; ++ptr)
+        if ((ptr->level > last_level) && (ptr->level <= level)) {
+            max_called_level = MAX(max_called_level, ptr->level);
+            ptr->hook();
+        }
 
-	last_level = max_called_level;
+    last_level = max_called_level;
 
-	return last_level;
+    return last_level;
 }
diff --git a/kernel/interrupt.c b/kernel/interrupt.c
index 0b8d1125..478da05c 100644
--- a/kernel/interrupt.c
+++ b/kernel/interrupt.c
@@ -1,50 +1,50 @@
-#include <thread.h>
-#include <ipc.h>
-#include <sched.h>
-#include <platform/irq.h>
-#include <interrupt.h>
-#include <interrupt_ipc.h>
 #include <debug.h>
-#include <init_hook.h>
 #include <error.h>
+#include <init_hook.h>
+#include <interrupt.h>
+#include <interrupt_ipc.h>
+#include <ipc.h>
 #include <lib/ktable.h>
+#include <platform/irq.h>
+#include <sched.h>
+#include <thread.h>
 
 #include INC_PLAT(nvic.h)
 
 void __interrupt_handler(int n);
 
 /* user interrupt vector */
-#define USER_IRQ_VEC(n)						\
-	void nvic_handler##n(void) __NAKED;			\
-	void nvic_handler##n(void)				\
-	{							\
-		irq_enter();					\
-		__interrupt_handler(n);				\
-		request_schedule();				\
-		irq_return();					\
-	}
+#define USER_IRQ_VEC(n)                 \
+    void nvic_handler##n(void) __NAKED; \
+    void nvic_handler##n(void)          \
+    {                                   \
+        irq_enter();                    \
+        __interrupt_handler(n);         \
+        request_schedule();             \
+        irq_return();                   \
+    }
 
 #undef USER_INTERRUPT_USED
 #define USER_INTERRUPT
-#define IRQ_VEC_N_OP	USER_IRQ_VEC
+#define IRQ_VEC_N_OP USER_IRQ_VEC
 #include INC_PLAT(nvic_private.h)
 #undef IRQ_VEC_N_OP
 #undef USER_INTERRUPT
 
 typedef void (*irq_handler_t)(void);
 
-#define INVALID_IDX		IRQn_NUM
-#define INVALID_IRQ_NUM	IRQn_NUM
+#define INVALID_IDX IRQn_NUM
+#define INVALID_IRQ_NUM IRQn_NUM
 
 #define IS_VALID_IRQ_NUM(irq) ((irq) < INVALID_IRQ_NUM)
 
 struct user_irq {
-	tcb_t *thr;
-	int irq;
-	uint16_t action;
-	uint16_t priority;
-	irq_handler_t handler;
-	struct user_irq *next;
+    tcb_t *thr;
+    int irq;
+    uint16_t action;
+    uint16_t priority;
+    irq_handler_t handler;
+    struct user_irq *next;
 };
 
 static struct user_irq *user_irqs[IRQn_NUM];
@@ -52,262 +52,259 @@ static struct user_irq *user_irqs[IRQn_NUM];
 DECLARE_KTABLE(struct user_irq, user_irq_table, IRQn_NUM);
 
 struct user_irq_queue {
-	struct user_irq *head;
-	struct user_irq *tail;
+    struct user_irq *head;
+    struct user_irq *tail;
 };
 
 static struct user_irq_queue user_irq_queue;
 
 static int user_irq_queue_is_empty(void)
 {
-	return (!user_irq_queue.head);
+    return (!user_irq_queue.head);
 }
 
 static void user_irq_queue_push(struct user_irq *uirq)
 {
-	if (user_irq_queue_is_empty()) {
-		user_irq_queue.head = user_irq_queue.tail = uirq;
-	} else {
-		user_irq_queue.tail->next = uirq;
-		user_irq_queue.tail = uirq;
-	}
+    if (user_irq_queue_is_empty()) {
+        user_irq_queue.head = user_irq_queue.tail = uirq;
+    } else {
+        user_irq_queue.tail->next = uirq;
+        user_irq_queue.tail = uirq;
+    }
 }
 
 static void user_irq_queue_delete(int irq)
 {
-	struct user_irq *uirq = user_irqs[irq];
-	for (struct user_irq **iter = &user_irq_queue.head ; *iter;
-	     iter = &(*iter)->next) {
-		if (*iter == uirq) {
-			*iter = uirq->next;
-			break;
-		}
-	}
+    struct user_irq *uirq = user_irqs[irq];
+    for (struct user_irq **iter = &user_irq_queue.head; *iter;
+         iter = &(*iter)->next) {
+        if (*iter == uirq) {
+            *iter = uirq->next;
+            break;
+        }
+    }
 }
 
 static inline void user_irq_reset_all(void)
 {
-	for (int i = 0 ; i < IRQn_NUM ; i++)
-		user_irqs[i] = NULL;
+    for (int i = 0; i < IRQn_NUM; i++)
+        user_irqs[i] = NULL;
 }
 
 static struct user_irq *user_irq_create_default(int irq)
 {
-	if (IS_VALID_IRQ_NUM(irq)) {
-		struct user_irq *uirq = ktable_alloc(&user_irq_table);
-		uirq->thr = NULL;
-		uirq->irq = irq;
-		uirq->action = 0;
-		uirq->priority = 0;
-		uirq->handler = NULL;
-		uirq->next = NULL;
-
-		return uirq;
-	}
-	return NULL;
+    if (IS_VALID_IRQ_NUM(irq)) {
+        struct user_irq *uirq = ktable_alloc(&user_irq_table);
+        uirq->thr = NULL;
+        uirq->irq = irq;
+        uirq->action = 0;
+        uirq->priority = 0;
+        uirq->handler = NULL;
+        uirq->next = NULL;
+
+        return uirq;
+    }
+    return NULL;
 }
 
 static inline struct user_irq *user_irq_fetch(int irq)
 {
-	if (!user_irqs[irq])
-		user_irqs[irq] =  user_irq_create_default(irq);
-	return user_irqs[irq];
+    if (!user_irqs[irq])
+        user_irqs[irq] = user_irq_create_default(irq);
+    return user_irqs[irq];
 }
 
 static void user_irq_release(int irq)
 {
-	if (IS_VALID_IRQ_NUM(irq)) {
-		struct user_irq *uirq = user_irqs[irq];
-
-		if (uirq) {
-			ktable_free(&user_irq_table, uirq);
-			user_irqs[irq] = NULL;
-		}
-	}
+    if (IS_VALID_IRQ_NUM(irq)) {
+        struct user_irq *uirq = user_irqs[irq];
+
+        if (uirq) {
+            ktable_free(&user_irq_table, uirq);
+            user_irqs[irq] = NULL;
+        }
+    }
 }
 
 static void irq_handler_ipc(struct user_irq *uirq)
 {
-	if (!uirq| !uirq->thr)
-		return;
-
-	/* Prepare ipc for user interrupt thread */
-	tcb_t *thr = uirq->thr;
-	ipc_msg_tag_t tag = {
-		.s.label = USER_INTERRUPT_LABEL,
-		.s.n_untyped = IRQ_IPC_MSG_NUM,
-	};
-
-	ipc_write_mr(thr, 0, tag.raw);
-	ipc_write_mr(thr, IRQ_IPC_IRQN + 1, (uint32_t) uirq->irq);
-	ipc_write_mr(thr, IRQ_IPC_HANDLER + 1, (uint32_t) uirq->handler);
-	ipc_write_mr(thr, IRQ_IPC_ACTION + 1, (uint32_t) uirq->action);
-	thr->utcb->sender = TID_TO_GLOBALID(THREAD_INTERRUPT);
-	thr->ipc_from = L4_NILTHREAD;
+    if (!uirq | !uirq->thr)
+        return;
+
+    /* Prepare ipc for user interrupt thread */
+    tcb_t *thr = uirq->thr;
+    ipc_msg_tag_t tag = {
+        .s.label = USER_INTERRUPT_LABEL,
+        .s.n_untyped = IRQ_IPC_MSG_NUM,
+    };
+
+    ipc_write_mr(thr, 0, tag.raw);
+    ipc_write_mr(thr, IRQ_IPC_IRQN + 1, (uint32_t) uirq->irq);
+    ipc_write_mr(thr, IRQ_IPC_HANDLER + 1, (uint32_t) uirq->handler);
+    ipc_write_mr(thr, IRQ_IPC_ACTION + 1, (uint32_t) uirq->action);
+    thr->utcb->sender = TID_TO_GLOBALID(THREAD_INTERRUPT);
+    thr->ipc_from = L4_NILTHREAD;
 }
 
 static int irq_handler_enable(int irq)
 {
-	struct user_irq *uirq = user_irqs[irq];
+    struct user_irq *uirq = user_irqs[irq];
 
-	assert((intptr_t) uirq);
+    assert((intptr_t) uirq);
 
-	if (!uirq->thr)
-		return -1;
+    if (!uirq->thr)
+        return -1;
 
-	tcb_t *thr = uirq->thr;
+    tcb_t *thr = uirq->thr;
 
-	if (thr->state != T_RECV_BLOCKED)
-		return -1;
+    if (thr->state != T_RECV_BLOCKED)
+        return -1;
 
-	irq_handler_ipc(uirq);
+    irq_handler_ipc(uirq);
 
-	/* Wake up the interrupt thread directly */
-	thr->priority = SCHED_PRIO_INTR;
-	thr->state = T_RUNNABLE;
-	sched_enqueue(thr);
+    /* Wake up the interrupt thread directly */
+    thr->priority = SCHED_PRIO_INTR;
+    thr->state = T_RUNNABLE;
+    sched_enqueue(thr);
 
-	return 0;
+    return 0;
 }
 
 /*
-* Push n to irq queue.
-* Select the first one in queue to run.
-*/
+ * Push n to irq queue.
+ * Select the first one in queue to run.
+ */
 static void irq_schedule(int irq)
 {
-	struct user_irq *uirq = user_irq_fetch(irq);
+    struct user_irq *uirq = user_irq_fetch(irq);
 
-	irq_disable();
-	user_irq_queue_push(uirq);
-	irq_enable();
+    irq_disable();
+    user_irq_queue_push(uirq);
+    irq_enable();
 
-	irq_handler_enable(irq);
+    irq_handler_enable(irq);
 }
 
 void __interrupt_handler(int irq)
 {
-	struct user_irq *uirq = user_irq_fetch(irq);
+    struct user_irq *uirq = user_irq_fetch(irq);
 
-	if (!uirq ||
-	    !uirq->thr ||
-	    !uirq->handler ||
-	    uirq->action != USER_IRQ_ENABLE) {
-		return;
-	}
+    if (!uirq || !uirq->thr || !uirq->handler ||
+        uirq->action != USER_IRQ_ENABLE) {
+        return;
+    }
 
-	user_irq_disable(irq); /* No re-entry interrupt */
-	irq_schedule(irq);
+    user_irq_disable(irq); /* No re-entry interrupt */
+    irq_schedule(irq);
 }
 
 void interrupt_init(void)
 {
-	user_irq_reset_all();
+    user_irq_reset_all();
 }
 
 INIT_HOOK(interrupt_init, INIT_LEVEL_KERNEL_EARLY);
 
 void user_interrupt_config(tcb_t *from)
 {
-	ipc_msg_tag_t tag = { .raw = ipc_read_mr(from, 0) };
-	if (tag.s.label != USER_INTERRUPT_LABEL)
-		return;
+    ipc_msg_tag_t tag = {.raw = ipc_read_mr(from, 0)};
+    if (tag.s.label != USER_INTERRUPT_LABEL)
+        return;
 
-	int irq = (uint16_t) from->ctx.regs[IRQ_IPC_IRQN + 1];
-	l4_thread_t tid = (l4_thread_t) from->ctx.regs[IRQ_IPC_TID + 1];
-	int action = (uint16_t) from->ctx.regs[IRQ_IPC_ACTION + 1];
-	irq_handler_t handler = (irq_handler_t)
-	                        from->ctx.regs[IRQ_IPC_HANDLER + 1];
-	int priority = (uint16_t) from->ctx.regs[IRQ_IPC_PRIORITY + 1];
+    int irq = (uint16_t) from->ctx.regs[IRQ_IPC_IRQN + 1];
+    l4_thread_t tid = (l4_thread_t) from->ctx.regs[IRQ_IPC_TID + 1];
+    int action = (uint16_t) from->ctx.regs[IRQ_IPC_ACTION + 1];
+    irq_handler_t handler = (irq_handler_t) from->ctx.regs[IRQ_IPC_HANDLER + 1];
+    int priority = (uint16_t) from->ctx.regs[IRQ_IPC_PRIORITY + 1];
 
-	user_irq_disable(irq);
+    user_irq_disable(irq);
 
-	if (!IS_VALID_IRQ_NUM(irq))
-		return;
+    if (!IS_VALID_IRQ_NUM(irq))
+        return;
 
-	struct user_irq *uirq = user_irq_fetch(irq);
+    struct user_irq *uirq = user_irq_fetch(irq);
 
-	if (!uirq)
-		return;
+    if (!uirq)
+        return;
 
-	/* update user irq config */
-	if (tid != L4_NILTHREAD)
-		uirq->thr = thread_by_globalid(tid);
+    /* update user irq config */
+    if (tid != L4_NILTHREAD)
+        uirq->thr = thread_by_globalid(tid);
 
-	uirq->action = (uint16_t) action;
+    uirq->action = (uint16_t) action;
 
-	if (handler)
-		uirq->handler = handler;
+    if (handler)
+        uirq->handler = handler;
 
-	if (priority > 0)
-		uirq->priority = (uint16_t)priority;
+    if (priority > 0)
+        uirq->priority = (uint16_t) priority;
 }
 
 void user_interrupt_handler_update(tcb_t *thr)
 {
-	if (!thr)
-		return;
-
-	for (int irq = 0 ; irq < IRQn_NUM ; irq++) {
-		struct user_irq *uirq = user_irq_fetch(irq);
-		if (!uirq)
-			continue;
-
-		if (uirq->thr == thr) {
-			/* make sure irq is cleared */
-			/* clear pending bit */
-			user_irq_clear_pending(irq);
-			switch (uirq->action) {
-			case USER_IRQ_ENABLE:
-				user_irq_enable(irq);
-				break;
-			case USER_IRQ_DISABLE:
-				irq_disable();
-				user_irq_queue_delete(irq);
-				irq_enable();
-				user_irq_disable(irq);
-				break;
-			case USER_IRQ_FREE:
-				irq_disable();
-				user_irq_queue_delete(irq);
-				user_irq_release(irq);
-				irq_enable();
-				/* reply ipc immediately */
-				irq_handler_ipc(uirq);
-				thr->state = T_RUNNABLE;
-				sched_enqueue(thr);
-				break;
-			}
-			break;
-		}
-	}
+    if (!thr)
+        return;
+
+    for (int irq = 0; irq < IRQn_NUM; irq++) {
+        struct user_irq *uirq = user_irq_fetch(irq);
+        if (!uirq)
+            continue;
+
+        if (uirq->thr == thr) {
+            /* make sure irq is cleared */
+            /* clear pending bit */
+            user_irq_clear_pending(irq);
+            switch (uirq->action) {
+            case USER_IRQ_ENABLE:
+                user_irq_enable(irq);
+                break;
+            case USER_IRQ_DISABLE:
+                irq_disable();
+                user_irq_queue_delete(irq);
+                irq_enable();
+                user_irq_disable(irq);
+                break;
+            case USER_IRQ_FREE:
+                irq_disable();
+                user_irq_queue_delete(irq);
+                user_irq_release(irq);
+                irq_enable();
+                /* reply ipc immediately */
+                irq_handler_ipc(uirq);
+                thr->state = T_RUNNABLE;
+                sched_enqueue(thr);
+                break;
+            }
+            break;
+        }
+    }
 }
 
 void user_irq_enable(int irq)
 {
-	if (nvic_is_setup(irq)) {
-		NVIC_EnableIRQ(irq);
-	}
+    if (nvic_is_setup(irq)) {
+        NVIC_EnableIRQ(irq);
+    }
 }
 
 void user_irq_disable(int irq)
 {
-	if (nvic_is_setup(irq)) {
-		NVIC_ClearPendingIRQ(irq);
-		NVIC_DisableIRQ(irq);
-	}
+    if (nvic_is_setup(irq)) {
+        NVIC_ClearPendingIRQ(irq);
+        NVIC_DisableIRQ(irq);
+    }
 }
 
 void user_irq_set_pending(int irq)
 {
-	if (nvic_is_setup(irq)) {
-		NVIC_SetPendingIRQ(irq);
-	}
+    if (nvic_is_setup(irq)) {
+        NVIC_SetPendingIRQ(irq);
+    }
 }
 
 void user_irq_clear_pending(int irq)
 {
-	if (nvic_is_setup(irq)) {
-		NVIC_ClearPendingIRQ(irq);
-	}
+    if (nvic_is_setup(irq)) {
+        NVIC_ClearPendingIRQ(irq);
+    }
 }
diff --git a/kernel/ipc.c b/kernel/ipc.c
index 151304fd..23a9ca83 100644
--- a/kernel/ipc.c
+++ b/kernel/ipc.c
@@ -5,17 +5,17 @@
 
 #include INC_PLAT(systick.h)
 
-#include <platform/armv7m.h>
 #include <debug.h>
 #include <error.h>
-#include <types.h>
-#include <thread.h>
-#include <memory.h>
+#include <interrupt.h>
 #include <ipc.h>
+#include <ktimer.h>
+#include <memory.h>
+#include <platform/armv7m.h>
 #include <sched.h>
+#include <thread.h>
+#include <types.h>
 #include <user-log.h>
-#include <ktimer.h>
-#include <interrupt.h>
 
 extern tcb_t *caller;
 
@@ -29,509 +29,482 @@ extern int thread_count;
  */
 static inline void thread_make_runnable(tcb_t *thr)
 {
-	thr->state = T_RUNNABLE;
-	sched_enqueue(thr);
+    thr->state = T_RUNNABLE;
+    sched_enqueue(thr);
 }
 
 uint32_t ipc_read_mr(tcb_t *from, int i)
 {
-	if (i >= 8)
-		return from->utcb->mr[i - 8];
-	return from->ctx.regs[i];
+    if (i >= 8)
+        return from->utcb->mr[i - 8];
+    return from->ctx.regs[i];
 }
 
 void ipc_write_mr(tcb_t *to, int i, uint32_t data)
 {
-	if (i >= 8)
-		to->utcb->mr[i - 8] = data;
-	else
-		to->ctx.regs[i] = data;
+    if (i >= 8)
+        to->utcb->mr[i - 8] = data;
+    else
+        to->ctx.regs[i] = data;
 }
 
 static void user_ipc_error(tcb_t *thr, enum user_error_t error)
 {
-	ipc_msg_tag_t tag;
+    ipc_msg_tag_t tag;
 
-	/* Set ipc unsuccessful */
-	tag.raw = ipc_read_mr(thr, 0);
-	tag.s.flags |= 0x8;
-	ipc_write_mr(thr, 0, tag.raw);
+    /* Set ipc unsuccessful */
+    tag.raw = ipc_read_mr(thr, 0);
+    tag.s.flags |= 0x8;
+    ipc_write_mr(thr, 0, tag.raw);
 
-	set_user_error(thr, error);
+    set_user_error(thr, error);
 }
 
-static inline void do_ipc_error(tcb_t *from, tcb_t *to,
+static inline void do_ipc_error(tcb_t *from,
+                                tcb_t *to,
                                 enum user_error_t from_err,
                                 enum user_error_t to_err,
                                 thread_state_t from_state,
                                 thread_state_t to_state)
 {
-	user_ipc_error(from, from_err);
-	user_ipc_error(to, to_err);
-	from->state = from_state;
-	to->state = to_state;
+    user_ipc_error(from, from_err);
+    user_ipc_error(to, to_err);
+    from->state = from_state;
+    to->state = to_state;
 }
 
 
 static void do_ipc(tcb_t *from, tcb_t *to)
 {
-	ipc_typed_item	typed_item;
-	int untyped_idx, typed_idx, typed_item_idx;
-	uint32_t typed_data;		/* typed item extra word */
-	l4_thread_t from_recv_tid;
-
-	/* Clear timeout event when ipc is established. */
-	from->timeout_event = 0;
-	to->timeout_event = 0;
-
-	/* Copy tag of message */
-	ipc_msg_tag_t tag = { .raw = ipc_read_mr(from, 0) };
-	int untyped_last = tag.s.n_untyped + 1;
-	int typed_last = untyped_last + tag.s.n_typed;
-
-	dbg_printf(DL_IPC,
-	           "IPC: do_ipc tag:%p n_untyped:%d n_typed:%d MR1:%p MR2:%p\n",
-	           tag.raw, tag.s.n_untyped, tag.s.n_typed,
-	           ipc_read_mr(from, 1), ipc_read_mr(from, 2));
-
-	if (typed_last > IPC_MR_COUNT) {
-		do_ipc_error(from, to,
-		             UE_IPC_MSG_OVERFLOW | UE_IPC_PHASE_SEND,
-		             UE_IPC_MSG_OVERFLOW | UE_IPC_PHASE_RECV,
-		             T_RUNNABLE,
-		             T_RUNNABLE);
-		return;
-	}
-
-	ipc_write_mr(to, 0, tag.raw);
-
-	/* Copy untyped words */
-	for (untyped_idx = 1; untyped_idx < untyped_last; ++untyped_idx) {
-		ipc_write_mr(to, untyped_idx, ipc_read_mr(from, untyped_idx));
-	}
-
-	typed_item_idx = -1;
-	/* Copy typed words
-	 * FSM: j - number of byte */
-	for (typed_idx = untyped_idx; typed_idx < typed_last; ++typed_idx) {
-		uint32_t mr_data = ipc_read_mr(from, typed_idx);
-
-		/* Write typed mr data to 'to' thread */
-		ipc_write_mr(to, typed_idx, mr_data);
-
-		if (typed_item_idx == -1) {
-			/* If typed_item_idx == -1 - read typed item's tag */
-			typed_item.raw = mr_data;
-			++typed_item_idx;
-		} else if (typed_item.s.header & IPC_TI_MAP_GRANT) {
-			/* MapItem / GrantItem have 1xxx in header */
-			int ret;
-			memptr_t map_base, map_size;
-			typed_data = mr_data;
-
-			map_base = typed_item.raw & 0xFFFFFFC0;
-			map_size = typed_data & 0xFFFFFFC0;
-
-			/* S1 security fix: REJECT unaligned map base addresses.
-			 * L4 spec uses 64-byte alignment (0xFFFFFFC0 mask), but
-			 * kernel requires CONFIG_SMALLEST_FPAGE_SIZE (256-byte).
-			 * Unaligned addresses cannot be safely mapped - kernel
-			 * must not silently adjust boundaries.
-			 */
-			if (!addr_is_fpage_aligned(map_base)) {
-				dbg_printf(DL_IPC,
-				           "IPC: REJECT unaligned map base %p\n",
-				           map_base);
-				do_ipc_error(from, to,
-				             UE_IPC_ABORTED | UE_IPC_PHASE_SEND,
-				             UE_IPC_ABORTED | UE_IPC_PHASE_RECV,
-				             T_RUNNABLE,
-				             T_RUNNABLE);
-				return;
-			}
-
-			dbg_printf(DL_IPC,
-			           "IPC: map_area from %t to %t base:%p size:%p priv:%d\n",
-			           from->t_globalid, to->t_globalid,
-			           map_base, map_size,
-			           thread_ispriviliged(from));
-
-			ret = map_area(from->as, to->as,
-			               map_base, map_size,
-			               (typed_item.s.header & IPC_TI_GRANT) ?
-			                   GRANT : MAP,
-			               thread_ispriviliged(from));
-			typed_item_idx = -1;
-
-			dbg_printf(DL_IPC, "IPC: map_area returned %d\n", ret);
-
-			if (ret < 0) {
-				do_ipc_error(from, to,
-				             UE_IPC_ABORTED | UE_IPC_PHASE_SEND,
-				             UE_IPC_ABORTED | UE_IPC_PHASE_RECV,
-				             T_RUNNABLE,
-				             T_RUNNABLE);
-				return;
-			}
-		}
-
-		/* TODO: StringItem support */
-	}
-
-	if (!to->ctx.sp || !from->ctx.sp) {
-		do_ipc_error(from, to,
-		             UE_IPC_ABORTED | UE_IPC_PHASE_SEND,
-		             UE_IPC_ABORTED | UE_IPC_PHASE_RECV,
-		             T_RUNNABLE,
-		             T_RUNNABLE);
-		return;
-	}
-
-	to->utcb->sender = from->t_globalid;
-
-	/* Temporarily boost receiver priority for IPC fast path.
-	 * base_priority is preserved; effective priority restored
-	 * when thread is descheduled (in thread_switch).
-	 */
-	sched_set_priority(to, SCHED_PRIO_IPC);
-	thread_make_runnable(to);
-	to->ipc_from = L4_NILTHREAD;
-	((uint32_t *) to->ctx.sp)[REG_R0] = from->t_globalid;
-
-	/* If from has receive phases, lock myself */
-	from_recv_tid = ((uint32_t *) from->ctx.sp)[REG_R1];
-	if (from_recv_tid == L4_NILTHREAD) {
-		thread_make_runnable(from);
-	} else {
-		from->state = T_RECV_BLOCKED;
-		from->ipc_from = from_recv_tid;
-
-		dbg_printf(DL_IPC, "IPC: %t receiving\n", from->t_globalid);
-	}
-
-	dbg_printf(DL_IPC,
-	           "IPC: %t→%t done\n", from->t_globalid, to->t_globalid);
+    ipc_typed_item typed_item;
+    int untyped_idx, typed_idx, typed_item_idx;
+    uint32_t typed_data; /* typed item extra word */
+    l4_thread_t from_recv_tid;
+
+    /* Clear timeout event when ipc is established. */
+    from->timeout_event = 0;
+    to->timeout_event = 0;
+
+    /* Copy tag of message */
+    ipc_msg_tag_t tag = {.raw = ipc_read_mr(from, 0)};
+    int untyped_last = tag.s.n_untyped + 1;
+    int typed_last = untyped_last + tag.s.n_typed;
+
+    dbg_printf(DL_IPC,
+               "IPC: do_ipc tag:%p n_untyped:%d n_typed:%d MR1:%p MR2:%p\n",
+               tag.raw, tag.s.n_untyped, tag.s.n_typed, ipc_read_mr(from, 1),
+               ipc_read_mr(from, 2));
+
+    if (typed_last > IPC_MR_COUNT) {
+        do_ipc_error(from, to, UE_IPC_MSG_OVERFLOW | UE_IPC_PHASE_SEND,
+                     UE_IPC_MSG_OVERFLOW | UE_IPC_PHASE_RECV, T_RUNNABLE,
+                     T_RUNNABLE);
+        return;
+    }
+
+    ipc_write_mr(to, 0, tag.raw);
+
+    /* Copy untyped words */
+    for (untyped_idx = 1; untyped_idx < untyped_last; ++untyped_idx) {
+        ipc_write_mr(to, untyped_idx, ipc_read_mr(from, untyped_idx));
+    }
+
+    typed_item_idx = -1;
+    /* Copy typed words
+     * FSM: j - number of byte */
+    for (typed_idx = untyped_idx; typed_idx < typed_last; ++typed_idx) {
+        uint32_t mr_data = ipc_read_mr(from, typed_idx);
+
+        /* Write typed mr data to 'to' thread */
+        ipc_write_mr(to, typed_idx, mr_data);
+
+        if (typed_item_idx == -1) {
+            /* If typed_item_idx == -1 - read typed item's tag */
+            typed_item.raw = mr_data;
+            ++typed_item_idx;
+        } else if (typed_item.s.header & IPC_TI_MAP_GRANT) {
+            /* MapItem / GrantItem have 1xxx in header */
+            int ret;
+            memptr_t map_base, map_size;
+            typed_data = mr_data;
+
+            map_base = typed_item.raw & 0xFFFFFFC0;
+            map_size = typed_data & 0xFFFFFFC0;
+
+            /* S1 security fix: REJECT unaligned map base addresses.
+             * L4 spec uses 64-byte alignment (0xFFFFFFC0 mask), but
+             * kernel requires CONFIG_SMALLEST_FPAGE_SIZE (256-byte).
+             * Unaligned addresses cannot be safely mapped - kernel
+             * must not silently adjust boundaries.
+             */
+            if (!addr_is_fpage_aligned(map_base)) {
+                dbg_printf(DL_IPC, "IPC: REJECT unaligned map base %p\n",
+                           map_base);
+                do_ipc_error(from, to, UE_IPC_ABORTED | UE_IPC_PHASE_SEND,
+                             UE_IPC_ABORTED | UE_IPC_PHASE_RECV, T_RUNNABLE,
+                             T_RUNNABLE);
+                return;
+            }
+
+            dbg_printf(DL_IPC,
+                       "IPC: map_area from %t to %t base:%p size:%p priv:%d\n",
+                       from->t_globalid, to->t_globalid, map_base, map_size,
+                       thread_ispriviliged(from));
+
+            ret = map_area(from->as, to->as, map_base, map_size,
+                           (typed_item.s.header & IPC_TI_GRANT) ? GRANT : MAP,
+                           thread_ispriviliged(from));
+            typed_item_idx = -1;
+
+            dbg_printf(DL_IPC, "IPC: map_area returned %d\n", ret);
+
+            if (ret < 0) {
+                do_ipc_error(from, to, UE_IPC_ABORTED | UE_IPC_PHASE_SEND,
+                             UE_IPC_ABORTED | UE_IPC_PHASE_RECV, T_RUNNABLE,
+                             T_RUNNABLE);
+                return;
+            }
+        }
+
+        /* TODO: StringItem support */
+    }
+
+    if (!to->ctx.sp || !from->ctx.sp) {
+        do_ipc_error(from, to, UE_IPC_ABORTED | UE_IPC_PHASE_SEND,
+                     UE_IPC_ABORTED | UE_IPC_PHASE_RECV, T_RUNNABLE,
+                     T_RUNNABLE);
+        return;
+    }
+
+    to->utcb->sender = from->t_globalid;
+
+    /* Temporarily boost receiver priority for IPC fast path.
+     * base_priority is preserved; effective priority restored
+     * when thread is descheduled (in thread_switch).
+     */
+    sched_set_priority(to, SCHED_PRIO_IPC);
+    thread_make_runnable(to);
+    to->ipc_from = L4_NILTHREAD;
+    ((uint32_t *) to->ctx.sp)[REG_R0] = from->t_globalid;
+
+    /* If from has receive phases, lock myself */
+    from_recv_tid = ((uint32_t *) from->ctx.sp)[REG_R1];
+    if (from_recv_tid == L4_NILTHREAD) {
+        thread_make_runnable(from);
+    } else {
+        from->state = T_RECV_BLOCKED;
+        from->ipc_from = from_recv_tid;
+
+        dbg_printf(DL_IPC, "IPC: %t receiving\n", from->t_globalid);
+    }
+
+    dbg_printf(DL_IPC, "IPC: %t→%t done\n", from->t_globalid, to->t_globalid);
 }
 
 uint32_t ipc_timeout(void *data)
 {
-	ktimer_event_t *event = (ktimer_event_t *) data;
-	tcb_t *thr = (tcb_t *) event->data;
-
-	dbg_printf(DL_KDB, "IPC: timeout tid=%t st=%d\n",
-	           thr->t_globalid, thr->state);
+    ktimer_event_t *event = (ktimer_event_t *) data;
+    tcb_t *thr = (tcb_t *) event->data;
 
-	if (thr->timeout_event == (uint32_t)data) {
+    dbg_printf(DL_KDB, "IPC: timeout tid=%t st=%d\n", thr->t_globalid,
+               thr->state);
 
-		if (thr->state == T_RECV_BLOCKED)
-			user_ipc_error(thr, UE_IPC_TIMEOUT | UE_IPC_PHASE_RECV);
+    if (thr->timeout_event == (uint32_t) data) {
+        if (thr->state == T_RECV_BLOCKED)
+            user_ipc_error(thr, UE_IPC_TIMEOUT | UE_IPC_PHASE_RECV);
 
-		if (thr->state == T_SEND_BLOCKED)
-			user_ipc_error(thr, UE_IPC_TIMEOUT | UE_IPC_PHASE_SEND);
+        if (thr->state == T_SEND_BLOCKED)
+            user_ipc_error(thr, UE_IPC_TIMEOUT | UE_IPC_PHASE_SEND);
 
-		thread_make_runnable(thr);
-		thr->timeout_event = 0;
-	}
+        thread_make_runnable(thr);
+        thr->timeout_event = 0;
+    }
 
-	return 0;
+    return 0;
 }
 
 static void sys_ipc_timeout(uint32_t timeout)
 {
-	ktimer_event_t *kevent;
-	ipc_time_t t = { .raw = timeout };
+    ktimer_event_t *kevent;
+    ipc_time_t t = {.raw = timeout};
 
-	/* millisec to ticks */
-	uint32_t ticks = (t.period.m << t.period.e) /
-	                 ((1000000) / (CORE_CLOCK/CONFIG_KTIMER_HEARTBEAT));
+    /* millisec to ticks */
+    uint32_t ticks = (t.period.m << t.period.e) /
+                     ((1000000) / (CORE_CLOCK / CONFIG_KTIMER_HEARTBEAT));
 
-	kevent = ktimer_event_create(ticks, ipc_timeout, caller);
+    kevent = ktimer_event_create(ticks, ipc_timeout, caller);
 
-	dbg_printf(DL_KDB, "IPC: sched timeout ticks=%d ev=%p\n",
-	           ticks, kevent);
+    dbg_printf(DL_KDB, "IPC: sched timeout ticks=%d ev=%p\n", ticks, kevent);
 
-	caller->timeout_event = (uint32_t) kevent;
+    caller->timeout_event = (uint32_t) kevent;
 }
 
 void sys_ipc(uint32_t *param1)
 {
-	/* TODO: Checking of recv-mask */
-	tcb_t *to_thr = NULL;
-	l4_thread_t to_tid = param1[REG_R0], from_tid = param1[REG_R1];
-	uint32_t timeout = param1[REG_R2];
-
-
-
-	if (to_tid == L4_NILTHREAD &&
-		from_tid == L4_NILTHREAD) {
-		dbg_printf(DL_KDB, "IPC: sleep tid=%t timeout=%p\n",
-		           caller->t_globalid, timeout);
-		caller->state = T_INACTIVE;
-		if (timeout)
-			sys_ipc_timeout(timeout);
-		return;
-	}
-
-	if (to_tid != L4_NILTHREAD) {
-		to_thr = thread_by_globalid(to_tid);
-
-		if (to_tid == TID_TO_GLOBALID(THREAD_LOG)) {
-			user_log(caller);
-			thread_make_runnable(caller);
-			return;
-		} else if (to_tid == TID_TO_GLOBALID(THREAD_IRQ_REQUEST)) {
-			user_interrupt_config(caller);
-			thread_make_runnable(caller);
-			return;
-		} else if (to_thr &&
-		           (to_thr->state == T_RECV_BLOCKED ||
-		            to_tid == caller->t_globalid)) {
-			/* To thread who is waiting for us or sends to myself */
-			do_ipc(caller, to_thr);
-			return;
-		} else if (to_thr && to_thr->state == T_INACTIVE &&
-		           GLOBALID_TO_TID(to_thr->utcb->t_pager) ==
-		           GLOBALID_TO_TID(caller->t_globalid)) {
-			if (ipc_read_mr(caller, 0) == 0x00000005) {
-				/* mr1: thread func, mr2: stack addr,
-				 * mr3: stack size
-			         * mr4: thread entry, mr5: thread args
-			         * thread start protocol */
-
-				memptr_t sp = ipc_read_mr(caller, 2);
-				size_t stack_size = ipc_read_mr(caller, 3);
-				uint32_t regs[4];	/* r0, r1, r2, r3 */
-
-				dbg_printf(DL_IPC,
-				           "IPC: %t thread start sp:%p stack_size:%p\n",
-				           to_tid, sp, stack_size);
-
-				/* Security check: Ensure stack is in user-writable memory */
-				int pid = mempool_search(sp - stack_size, stack_size);
-				mempool_t *mp = mempool_getbyid(pid);
-
-				if (!mp || !(mp->flags & MP_UW)) {
-					dbg_printf(DL_IPC,
-					           "IPC: REJECT invalid stack for %t: %p (pool %s)\n",
-					           to_tid, sp - stack_size, mp ? mp->name : "N/A");
-					user_ipc_error(caller,
-					               UE_IPC_ABORTED | UE_IPC_PHASE_SEND);
-					thread_make_runnable(caller);
-					return;
-				}
-
-				to_thr->stack_base = sp - stack_size;
-				to_thr->stack_size = stack_size;
-				thread_init_canary(to_thr);
-
-				dbg_printf(DL_IPC,
-				           "IPC: %t stack_base:%p stack_size:%p\n",
-				           to_tid, to_thr->stack_base, to_thr->stack_size);
-
-				regs[REG_R0] = (uint32_t)&kip;
-				regs[REG_R1] = (uint32_t)to_thr->utcb;
-				regs[REG_R2] = ipc_read_mr(caller, 4);
-				regs[REG_R3] = ipc_read_mr(caller, 5);
-				thread_init_ctx((void *) sp,
-				                (void *) ipc_read_mr(caller, 1),
-				                regs, to_thr);
-
-				thread_make_runnable(caller);
-
-				/* Start thread */
-				thread_make_runnable(to_thr);
-
-				return;
-			} else {
-				/* Non-start IPC to INACTIVE thread: process
-				 * typed items (MapItems) only, without full
-				 * do_ipc() which requires valid ctx.sp.
-				 * This allows mapping memory to thread before
-				 * it's started.
-				 */
-				ipc_msg_tag_t tag = { .raw = ipc_read_mr(caller, 0) };
-				int untyped_last = tag.s.n_untyped + 1;
-				int typed_last = untyped_last + tag.s.n_typed;
-				ipc_typed_item typed_item;
-				int typed_item_idx = -1;
-
-				/* Bounds check to prevent OOB MR access */
-				if (typed_last > IPC_MR_COUNT) {
-					user_ipc_error(caller,
-					               UE_IPC_MSG_OVERFLOW | UE_IPC_PHASE_SEND);
-					thread_make_runnable(caller);
-					return;
-				}
-
-				dbg_printf(DL_IPC,
-				           "IPC: %t to INACTIVE %t (non-start)\n",
-				           caller->t_globalid, to_thr->t_globalid);
-
-				/* Process typed items (MapItems only) */
-				for (int typed_idx = untyped_last; typed_idx < typed_last; ++typed_idx) {
-					uint32_t mr_data = ipc_read_mr(caller, typed_idx);
-
-					if (typed_item_idx == -1) {
-						typed_item.raw = mr_data;
-						++typed_item_idx;
-					} else if (typed_item.s.header & IPC_TI_MAP_GRANT) {
-						memptr_t map_base = typed_item.raw & 0xFFFFFFC0;
-						memptr_t map_size = mr_data & 0xFFFFFFC0;
-						int ret;
-
-						/* S1 fix: reject unaligned addresses */
-						if (!addr_is_fpage_aligned(map_base)) {
-							dbg_printf(DL_IPC,
-							           "IPC: REJECT unaligned map to INACTIVE %p\n",
-							           map_base);
-							thread_make_runnable(caller);
-							return;
-						}
-
-						ret = map_area(caller->as, to_thr->as,
-						               map_base, map_size,
-						               (typed_item.s.header & IPC_TI_GRANT) ?
-						                   GRANT : MAP,
-						               thread_ispriviliged(caller));
-						typed_item_idx = -1;
-
-						if (ret < 0) {
-							dbg_printf(DL_IPC,
-							           "IPC: map to INACTIVE failed: %d\n",
-							           ret);
-						}
-					}
-				}
-
-				/* Keep thread INACTIVE, sender continues */
-				thread_make_runnable(caller);
-				return;
-			}
-		} else  {
-			/* Check if we should block or return error.
-			 * Blocking on non-existent threads or T_INACTIVE
-			 * threads without timeout leads to infinite stalls.
-			 */
-			if (!to_thr) {
-				/* Thread doesn't exist - return error */
-				dbg_printf(DL_IPC,
-				           "IPC: %t send to non-existent %t\n",
-				           caller->t_globalid, to_tid);
-				user_ipc_error(caller,
-				               UE_IPC_ABORTED | UE_IPC_PHASE_SEND);
-				thread_make_runnable(caller);
-				return;
-			}
-
-			if (to_thr->state == T_INACTIVE && !timeout) {
-				/* T_INACTIVE thread with no timeout.
-				 * Would block forever - return error.
-				 * With timeout, we can safely block and wait.
-				 */
-				dbg_printf(DL_IPC,
-				           "IPC: %t send to INACTIVE %t (no timeout)\n",
-				           caller->t_globalid, to_tid);
-				user_ipc_error(caller,
-				               UE_IPC_ABORTED | UE_IPC_PHASE_SEND);
-				thread_make_runnable(caller);
-				return;
-			}
-
-			/* Block and wait for receiver */
-			dbg_printf(DL_IPC,
-			           "IPC: %t SEND_BLOCKED to %t (state=%d)\n",
-			           caller->t_globalid, to_tid, to_thr->state);
-			caller->state = T_SEND_BLOCKED;
-			caller->utcb->intended_receiver = to_tid;
-
-			if (timeout)
-				sys_ipc_timeout(timeout);
-
-			return;
-		}
-	}
-
-	if (from_tid != L4_NILTHREAD) {
-		tcb_t *thr = NULL;
-
-		if (from_tid == L4_ANYTHREAD) {
-			/* Find out if there is any sending thread waiting
-			 * for caller
-			 */
-			for (int i = 1; i < thread_count; ++i) {
-				thr = thread_map[i];
-				if (thr && thr->state == T_SEND_BLOCKED &&
-				    thr->utcb->intended_receiver ==
-				    caller->t_globalid) {
-					do_ipc(thr, caller);
-					return;
-				}
-			}
-		} else if (from_tid != TID_TO_GLOBALID(THREAD_INTERRUPT)) {
-			thr = thread_by_globalid(from_tid);
-
-			if (thr && thr->state == T_SEND_BLOCKED &&
-			    thr->utcb->intended_receiver ==
-			    caller->t_globalid) {
-				do_ipc(thr, caller);
-				return;
-			}
-		}
-
-		/* Only receive phases, simply lock myself */
-		caller->state = T_RECV_BLOCKED;
-		caller->ipc_from = from_tid;
-
-		if (from_tid == TID_TO_GLOBALID(THREAD_INTERRUPT)) {
-			/* Threaded interrupt is ready */
-			user_interrupt_handler_update(caller);
-		}
-
-		if (timeout)
-			sys_ipc_timeout(timeout);
-
-		dbg_printf(DL_IPC, "IPC: %t receiving\n", caller->t_globalid);
-
-		return;
-	}
-
-	caller->state = T_SEND_BLOCKED;
+    /* TODO: Checking of recv-mask */
+    tcb_t *to_thr = NULL;
+    l4_thread_t to_tid = param1[REG_R0], from_tid = param1[REG_R1];
+    uint32_t timeout = param1[REG_R2];
+
+
+
+    if (to_tid == L4_NILTHREAD && from_tid == L4_NILTHREAD) {
+        dbg_printf(DL_KDB, "IPC: sleep tid=%t timeout=%p\n", caller->t_globalid,
+                   timeout);
+        caller->state = T_INACTIVE;
+        if (timeout)
+            sys_ipc_timeout(timeout);
+        return;
+    }
+
+    if (to_tid != L4_NILTHREAD) {
+        to_thr = thread_by_globalid(to_tid);
+
+        if (to_tid == TID_TO_GLOBALID(THREAD_LOG)) {
+            user_log(caller);
+            thread_make_runnable(caller);
+            return;
+        } else if (to_tid == TID_TO_GLOBALID(THREAD_IRQ_REQUEST)) {
+            user_interrupt_config(caller);
+            thread_make_runnable(caller);
+            return;
+        } else if (to_thr && (to_thr->state == T_RECV_BLOCKED ||
+                              to_tid == caller->t_globalid)) {
+            /* To thread who is waiting for us or sends to myself */
+            do_ipc(caller, to_thr);
+            return;
+        } else if (to_thr && to_thr->state == T_INACTIVE &&
+                   GLOBALID_TO_TID(to_thr->utcb->t_pager) ==
+                       GLOBALID_TO_TID(caller->t_globalid)) {
+            if (ipc_read_mr(caller, 0) == 0x00000005) {
+                /* mr1: thread func, mr2: stack addr,
+                 * mr3: stack size
+                 * mr4: thread entry, mr5: thread args
+                 * thread start protocol */
+
+                memptr_t sp = ipc_read_mr(caller, 2);
+                size_t stack_size = ipc_read_mr(caller, 3);
+                uint32_t regs[4]; /* r0, r1, r2, r3 */
+
+                dbg_printf(DL_IPC, "IPC: %t thread start sp:%p stack_size:%p\n",
+                           to_tid, sp, stack_size);
+
+                /* Security check: Ensure stack is in user-writable memory */
+                int pid = mempool_search(sp - stack_size, stack_size);
+                mempool_t *mp = mempool_getbyid(pid);
+
+                if (!mp || !(mp->flags & MP_UW)) {
+                    dbg_printf(
+                        DL_IPC,
+                        "IPC: REJECT invalid stack for %t: %p (pool %s)\n",
+                        to_tid, sp - stack_size, mp ? mp->name : "N/A");
+                    user_ipc_error(caller, UE_IPC_ABORTED | UE_IPC_PHASE_SEND);
+                    thread_make_runnable(caller);
+                    return;
+                }
+
+                to_thr->stack_base = sp - stack_size;
+                to_thr->stack_size = stack_size;
+                thread_init_canary(to_thr);
+
+                dbg_printf(DL_IPC, "IPC: %t stack_base:%p stack_size:%p\n",
+                           to_tid, to_thr->stack_base, to_thr->stack_size);
+
+                regs[REG_R0] = (uint32_t) &kip;
+                regs[REG_R1] = (uint32_t) to_thr->utcb;
+                regs[REG_R2] = ipc_read_mr(caller, 4);
+                regs[REG_R3] = ipc_read_mr(caller, 5);
+                thread_init_ctx((void *) sp, (void *) ipc_read_mr(caller, 1),
+                                regs, to_thr);
+
+                thread_make_runnable(caller);
+
+                /* Start thread */
+                thread_make_runnable(to_thr);
+
+                return;
+            } else {
+                /* Non-start IPC to INACTIVE thread: process
+                 * typed items (MapItems) only, without full
+                 * do_ipc() which requires valid ctx.sp.
+                 * This allows mapping memory to thread before
+                 * it's started.
+                 */
+                ipc_msg_tag_t tag = {.raw = ipc_read_mr(caller, 0)};
+                int untyped_last = tag.s.n_untyped + 1;
+                int typed_last = untyped_last + tag.s.n_typed;
+                ipc_typed_item typed_item;
+                int typed_item_idx = -1;
+
+                /* Bounds check to prevent OOB MR access */
+                if (typed_last > IPC_MR_COUNT) {
+                    user_ipc_error(caller,
+                                   UE_IPC_MSG_OVERFLOW | UE_IPC_PHASE_SEND);
+                    thread_make_runnable(caller);
+                    return;
+                }
+
+                dbg_printf(DL_IPC, "IPC: %t to INACTIVE %t (non-start)\n",
+                           caller->t_globalid, to_thr->t_globalid);
+
+                /* Process typed items (MapItems only) */
+                for (int typed_idx = untyped_last; typed_idx < typed_last;
+                     ++typed_idx) {
+                    uint32_t mr_data = ipc_read_mr(caller, typed_idx);
+
+                    if (typed_item_idx == -1) {
+                        typed_item.raw = mr_data;
+                        ++typed_item_idx;
+                    } else if (typed_item.s.header & IPC_TI_MAP_GRANT) {
+                        memptr_t map_base = typed_item.raw & 0xFFFFFFC0;
+                        memptr_t map_size = mr_data & 0xFFFFFFC0;
+                        int ret;
+
+                        /* S1 fix: reject unaligned addresses */
+                        if (!addr_is_fpage_aligned(map_base)) {
+                            dbg_printf(
+                                DL_IPC,
+                                "IPC: REJECT unaligned map to INACTIVE %p\n",
+                                map_base);
+                            thread_make_runnable(caller);
+                            return;
+                        }
+
+                        ret = map_area(
+                            caller->as, to_thr->as, map_base, map_size,
+                            (typed_item.s.header & IPC_TI_GRANT) ? GRANT : MAP,
+                            thread_ispriviliged(caller));
+                        typed_item_idx = -1;
+
+                        if (ret < 0) {
+                            dbg_printf(DL_IPC,
+                                       "IPC: map to INACTIVE failed: %d\n",
+                                       ret);
+                        }
+                    }
+                }
+
+                /* Keep thread INACTIVE, sender continues */
+                thread_make_runnable(caller);
+                return;
+            }
+        } else {
+            /* Check if we should block or return error.
+             * Blocking on non-existent threads or T_INACTIVE
+             * threads without timeout leads to infinite stalls.
+             */
+            if (!to_thr) {
+                /* Thread doesn't exist - return error */
+                dbg_printf(DL_IPC, "IPC: %t send to non-existent %t\n",
+                           caller->t_globalid, to_tid);
+                user_ipc_error(caller, UE_IPC_ABORTED | UE_IPC_PHASE_SEND);
+                thread_make_runnable(caller);
+                return;
+            }
+
+            if (to_thr->state == T_INACTIVE && !timeout) {
+                /* T_INACTIVE thread with no timeout.
+                 * Would block forever - return error.
+                 * With timeout, we can safely block and wait.
+                 */
+                dbg_printf(DL_IPC, "IPC: %t send to INACTIVE %t (no timeout)\n",
+                           caller->t_globalid, to_tid);
+                user_ipc_error(caller, UE_IPC_ABORTED | UE_IPC_PHASE_SEND);
+                thread_make_runnable(caller);
+                return;
+            }
+
+            /* Block and wait for receiver */
+            dbg_printf(DL_IPC, "IPC: %t SEND_BLOCKED to %t (state=%d)\n",
+                       caller->t_globalid, to_tid, to_thr->state);
+            caller->state = T_SEND_BLOCKED;
+            caller->utcb->intended_receiver = to_tid;
+
+            if (timeout)
+                sys_ipc_timeout(timeout);
+
+            return;
+        }
+    }
+
+    if (from_tid != L4_NILTHREAD) {
+        tcb_t *thr = NULL;
+
+        if (from_tid == L4_ANYTHREAD) {
+            /* Find out if there is any sending thread waiting
+             * for caller
+             */
+            for (int i = 1; i < thread_count; ++i) {
+                thr = thread_map[i];
+                if (thr && thr->state == T_SEND_BLOCKED &&
+                    thr->utcb->intended_receiver == caller->t_globalid) {
+                    do_ipc(thr, caller);
+                    return;
+                }
+            }
+        } else if (from_tid != TID_TO_GLOBALID(THREAD_INTERRUPT)) {
+            thr = thread_by_globalid(from_tid);
+
+            if (thr && thr->state == T_SEND_BLOCKED &&
+                thr->utcb->intended_receiver == caller->t_globalid) {
+                do_ipc(thr, caller);
+                return;
+            }
+        }
+
+        /* Only receive phases, simply lock myself */
+        caller->state = T_RECV_BLOCKED;
+        caller->ipc_from = from_tid;
+
+        if (from_tid == TID_TO_GLOBALID(THREAD_INTERRUPT)) {
+            /* Threaded interrupt is ready */
+            user_interrupt_handler_update(caller);
+        }
+
+        if (timeout)
+            sys_ipc_timeout(timeout);
+
+        dbg_printf(DL_IPC, "IPC: %t receiving\n", caller->t_globalid);
+
+        return;
+    }
+
+    caller->state = T_SEND_BLOCKED;
 }
 
 uint32_t ipc_deliver(void *data)
 {
-	l4_thread_t receiver;
-	tcb_t *from_thr = NULL, *to_thr = NULL;
-
-	for (int i = 1; i < thread_count; ++i) {
-		tcb_t *thr = thread_map[i];
-		if (!thr)
-			continue;
-		switch (thr->state) {
-		case T_RECV_BLOCKED:
-			if (thr->ipc_from != L4_NILTHREAD &&
-				thr->ipc_from != L4_ANYTHREAD &&
-				thr->ipc_from != TID_TO_GLOBALID(THREAD_INTERRUPT)) {
-				from_thr = thread_by_globalid(thr->ipc_from);
-				/* NOTE: Must check from_thr intend to send*/
-				if (from_thr && from_thr->state == T_SEND_BLOCKED &&
-				    from_thr->utcb->intended_receiver == thr->t_globalid)
-					do_ipc(from_thr, thr);
-			}
-			break;
-		case T_SEND_BLOCKED:
-			receiver = thr->utcb->intended_receiver;
-			if (receiver != L4_NILTHREAD &&
-			    receiver != L4_ANYTHREAD) {
-				to_thr = thread_by_globalid(receiver);
-				if (to_thr && to_thr->state == T_RECV_BLOCKED)
-					do_ipc(thr, to_thr);
-			}
-			break;
-		default:
-			break;
-		}
-	}
-
-	return 4096;
+    l4_thread_t receiver;
+    tcb_t *from_thr = NULL, *to_thr = NULL;
+
+    for (int i = 1; i < thread_count; ++i) {
+        tcb_t *thr = thread_map[i];
+        if (!thr)
+            continue;
+        switch (thr->state) {
+        case T_RECV_BLOCKED:
+            if (thr->ipc_from != L4_NILTHREAD &&
+                thr->ipc_from != L4_ANYTHREAD &&
+                thr->ipc_from != TID_TO_GLOBALID(THREAD_INTERRUPT)) {
+                from_thr = thread_by_globalid(thr->ipc_from);
+                /* NOTE: Must check from_thr intend to send*/
+                if (from_thr && from_thr->state == T_SEND_BLOCKED &&
+                    from_thr->utcb->intended_receiver == thr->t_globalid)
+                    do_ipc(from_thr, thr);
+            }
+            break;
+        case T_SEND_BLOCKED:
+            receiver = thr->utcb->intended_receiver;
+            if (receiver != L4_NILTHREAD && receiver != L4_ANYTHREAD) {
+                to_thr = thread_by_globalid(receiver);
+                if (to_thr && to_thr->state == T_RECV_BLOCKED)
+                    do_ipc(thr, to_thr);
+            }
+            break;
+        default:
+            break;
+        }
+    }
+
+    return 4096;
 }
diff --git a/kernel/kdb.c b/kernel/kdb.c
index 3c3664a0..84b16295 100644
--- a/kernel/kdb.c
+++ b/kernel/kdb.c
@@ -3,19 +3,19 @@
  * found in the LICENSE file.
  */
 
-#include <types.h>
-#include <kdb.h>
 #include <debug.h>
 #include <init_hook.h>
+#include <kdb.h>
 #include <softirq.h>
+#include <types.h>
 
 typedef void (*kdb_function_t)(void);
 
 struct kdb_t {
-	char option;
-	char *name;
-	char *menuentry;
-	kdb_function_t function;
+    char option;
+    char *name;
+    char *menuentry;
+    kdb_function_t function;
 };
 
 extern void kdb_dump_events(void);
@@ -31,131 +31,109 @@ extern void kdb_show_sampling(void);
 extern void kdb_show_tickless_verify(void);
 
 struct kdb_t kdb_functions[] = {
-	{
-		.option = 'K',
-		.name = "KTABLES",
-		.menuentry = "print kernel tables",
-		.function = kdb_dump_ktable
-	},
-	{
-		.option = 'e',
-		.name = "KTIMER",
-		.menuentry = "dump ktimer events",
-		.function = kdb_dump_events
-	},
-	{
-		.option = 'n',
-		.name = "NOW",
-		.menuentry = "show timer (now)",
-		.function = kdb_show_ktimer
-	},
-	{
-		.option = 's',
-		.name = "SOFTIRQ",
-		.menuentry = "show softirqs",
-		.function = kdb_dump_softirq
-	},
-	{
-		.option = 't',
-		.name = "THREADS",
-		.menuentry = "dump threads",
-		.function = kdb_dump_threads
-	},
-	{
-		.option = 'S',
-		.name = "STACKS",
-		.menuentry = "dump stack usage",
-		.function = kdb_dump_stacks
-	},
-	{
-		.option = 'M',
-		.name = "MPU",
-		.menuentry = "dump MPU status",
-		.function = kdb_dump_mpu
-	},
-	{
-		.option = 'm',
-		.name = "MEMPOOLS",
-		.menuentry = "dump memory pools",
-		.function = kdb_dump_mempool
-	},
-	{
-		.option = 'a',
-		.name = "AS",
-		.menuentry = "dump address spaces",
-		.function = kdb_dump_as
-	},
+    {.option = 'K',
+     .name = "KTABLES",
+     .menuentry = "print kernel tables",
+     .function = kdb_dump_ktable},
+    {.option = 'e',
+     .name = "KTIMER",
+     .menuentry = "dump ktimer events",
+     .function = kdb_dump_events},
+    {.option = 'n',
+     .name = "NOW",
+     .menuentry = "show timer (now)",
+     .function = kdb_show_ktimer},
+    {.option = 's',
+     .name = "SOFTIRQ",
+     .menuentry = "show softirqs",
+     .function = kdb_dump_softirq},
+    {.option = 't',
+     .name = "THREADS",
+     .menuentry = "dump threads",
+     .function = kdb_dump_threads},
+    {.option = 'S',
+     .name = "STACKS",
+     .menuentry = "dump stack usage",
+     .function = kdb_dump_stacks},
+    {.option = 'M',
+     .name = "MPU",
+     .menuentry = "dump MPU status",
+     .function = kdb_dump_mpu},
+    {.option = 'm',
+     .name = "MEMPOOLS",
+     .menuentry = "dump memory pools",
+     .function = kdb_dump_mempool},
+    {.option = 'a',
+     .name = "AS",
+     .menuentry = "dump address spaces",
+     .function = kdb_dump_as},
 #ifdef CONFIG_SYMMAP
-	{
-		.option = 'p',
-		.name = "TOP",
-		.menuentry = "show sampling",
-		.function = kdb_show_sampling
-	},
+    {.option = 'p',
+     .name = "TOP",
+     .menuentry = "show sampling",
+     .function = kdb_show_sampling},
 #endif
 #if defined(CONFIG_KTIMER_TICKLESS) && defined(CONFIG_KTIMER_TICKLESS_VERIFY)
-	{
-		.option = 'v',
-		.name = "TICKLESS VERIFY",
-		.menuentry = "show tickless scheduling stat",
-		.function = kdb_show_tickless_verify
-	},
+    {.option = 'v',
+     .name = "TICKLESS VERIFY",
+     .menuentry = "show tickless scheduling stat",
+     .function = kdb_show_tickless_verify},
 #endif
-	/* Insert KDB functions here */
+    /* Insert KDB functions here */
 };
 
 static void kdb_print_menu(void)
 {
-	dbg_printf(DL_KDB, "commands: \n");
-	for (int i = 0; i < (sizeof(kdb_functions) / sizeof(struct kdb_t)); ++i) {
-		dbg_printf(DL_KDB, "%c: %s\n",
-		           kdb_functions[i].option, kdb_functions[i].menuentry);
-	}
+    dbg_printf(DL_KDB, "commands: \n");
+    for (int i = 0; i < (sizeof(kdb_functions) / sizeof(struct kdb_t)); ++i) {
+        dbg_printf(DL_KDB, "%c: %s\n", kdb_functions[i].option,
+                   kdb_functions[i].menuentry);
+    }
 }
 
 
 int kdb_handler(char c)
 {
-	dbg_printf(DL_KDB, "\n\n## KDB ##\n");
-	for (int i = 0; i < (sizeof(kdb_functions) / sizeof(struct kdb_t)); ++i) {
-		if (c == kdb_functions[i].option) {
-			dbg_printf(DL_KDB, "-------%s------\n", kdb_functions[i].name);
-			kdb_functions[i].function();
-			goto ok;
-		}
-	}
-
-	if (c == '?') {
-		kdb_print_menu();
-		goto ok;
-	}
-
-	return 1;
+    dbg_printf(DL_KDB, "\n\n## KDB ##\n");
+    for (int i = 0; i < (sizeof(kdb_functions) / sizeof(struct kdb_t)); ++i) {
+        if (c == kdb_functions[i].option) {
+            dbg_printf(DL_KDB, "-------%s------\n", kdb_functions[i].name);
+            kdb_functions[i].function();
+            goto ok;
+        }
+    }
+
+    if (c == '?') {
+        kdb_print_menu();
+        goto ok;
+    }
+
+    return 1;
 
 ok:
-	dbg_printf(DL_KDB, "----------------\n");
-	return 0;
+    dbg_printf(DL_KDB, "----------------\n");
+    return 0;
 }
 
 int kdb_dump_error()
 {
-	for (int i = 0; i < (sizeof(kdb_functions) / sizeof(struct kdb_t)); ++i) {
-		dbg_printf(DL_KDB, "-------%s------\n", kdb_functions[i].name);
-		kdb_functions[i].function();
-	}
+    for (int i = 0; i < (sizeof(kdb_functions) / sizeof(struct kdb_t)); ++i) {
+        dbg_printf(DL_KDB, "-------%s------\n", kdb_functions[i].name);
+        kdb_functions[i].function();
+    }
 
-	return 0;
+    return 0;
 }
 
 void debug_kdb_handler(void)
 {
-	kdb_handler(dbg_getchar());
+    kdb_handler(dbg_getchar());
 }
 
 void kdb_init(void)
 {
-	softirq_register(KDB_SOFTIRQ, debug_kdb_handler);
-	dbg_puts("Press '?' to print KDB menu\n");
+    softirq_register(KDB_SOFTIRQ, debug_kdb_handler);
+    dbg_puts("Press '?' to print KDB menu\n");
 }
 
 INIT_HOOK(kdb_init, INIT_LEVEL_KERNEL);
diff --git a/kernel/kip.c b/kernel/kip.c
index 10985615..cfaa5a86 100644
--- a/kernel/kip.c
+++ b/kernel/kip.c
@@ -2,10 +2,10 @@
 #include <platform/link.h>
 
 kip_t kip __KIP = {
-	.kernel_id = 0x00000000,
+    .kernel_id = 0x00000000,
 
-	.api_version.raw = 0x84 << 24 | 7 << 16,	/* L4 X.2, rev 7 */
-	.api_flags.raw	= 0x00000000,		/* Little endian 32-bit */
+    .api_version.raw = 0x84 << 24 | 7 << 16, /* L4 X.2, rev 7 */
+    .api_flags.raw = 0x00000000,             /* Little endian 32-bit */
 };
 
 /* Extra information on KIP */
diff --git a/kernel/kprobes.c b/kernel/kprobes.c
index 66d5629d..33ca5a5b 100644
--- a/kernel/kprobes.c
+++ b/kernel/kprobes.c
@@ -3,155 +3,156 @@
  * found in the LICENSE file.
  */
 
+#include <debug.h>
+#include <init_hook.h>
 #include <kprobes.h>
 #include <platform/armv7m.h>
 #include <platform/breakpoint.h>
-#include <init_hook.h>
-#include <debug.h>
 
 static struct kprobe *kp_list;
 
 void kprobe_init()
 {
-	kp_list = NULL;
-	kprobe_arch_init();
+    kp_list = NULL;
+    kprobe_arch_init();
 }
 
 INIT_HOOK(kprobe_init, INIT_LEVEL_KERNEL);
 
 struct kprobe *kplist_search(void *addr)
 {
-	struct kprobe *cur = kp_list;
-	while (cur) {
-		if (cur->addr == addr)
-			return cur;
-		cur = cur->next;
-	}
-	return NULL;
+    struct kprobe *cur = kp_list;
+    while (cur) {
+        if (cur->addr == addr)
+            return cur;
+        cur = cur->next;
+    }
+    return NULL;
 }
 
 void kplist_add(struct kprobe *kp)
 {
-	kp->next = kp_list;
-	kp_list = kp;
+    kp->next = kp_list;
+    kp_list = kp;
 }
 
 void kplist_del(struct kprobe *kp)
 {
-	struct kprobe *cur = kp_list;
-	if (kp_list == kp) {
-		kp_list = kp->next;
-		return;
-	}
-	while (cur) {
-		if (cur->next == kp) {
-			cur->next = kp->next;
-			break;
-		}
-		cur = cur->next;
-	}
+    struct kprobe *cur = kp_list;
+    if (kp_list == kp) {
+        kp_list = kp->next;
+        return;
+    }
+    while (cur) {
+        if (cur->next == kp) {
+            cur->next = kp->next;
+            break;
+        }
+        cur = cur->next;
+    }
 }
 
 int kprobe_register(struct kprobe *kp)
 {
-	kp->addr = (void *) ((uint32_t) kp->addr & ~(1UL));
-	if (is_thumb32(*(uint16_t *) kp->addr))
-		kp->step_addr = kp->addr + 4;
-	else
-		kp->step_addr = kp->addr + 2;
+    kp->addr = (void *) ((uint32_t) kp->addr & ~(1UL));
+    if (is_thumb32(*(uint16_t *) kp->addr))
+        kp->step_addr = kp->addr + 4;
+    else
+        kp->step_addr = kp->addr + 2;
 
-	if (kprobe_arch_add(kp) < 0)
-		return -1;
+    if (kprobe_arch_add(kp) < 0)
+        return -1;
 
-	kplist_add(kp);
-	return 0;
+    kplist_add(kp);
+    return 0;
 }
 
 int kprobe_unregister(struct kprobe *kp)
 {
-	kplist_del(kp);
-	kprobe_arch_del(kp);
-	return 0;
+    kplist_del(kp);
+    kprobe_arch_del(kp);
+    return 0;
 }
 
-static int __kretprobe_post_handler(struct kprobe *kp, uint32_t *stack,
+static int __kretprobe_post_handler(struct kprobe *kp,
+                                    uint32_t *stack,
                                     uint32_t *kp_regs)
 {
-	struct kretprobe * rp = (struct kretprobe *) kp;
+    struct kretprobe *rp = (struct kretprobe *) kp;
 
-	kprobe_unregister(kp);
+    kprobe_unregister(kp);
 
-	kp->addr = rp->backup_addr;
+    kp->addr = rp->backup_addr;
 
-	kretprobe_register(rp);
-	return 0;
+    kretprobe_register(rp);
+    return 0;
 }
 
-static int __kretprobe_pre_handler(struct kprobe *kp, uint32_t *stack,
+static int __kretprobe_pre_handler(struct kprobe *kp,
+                                   uint32_t *stack,
                                    uint32_t *kp_regs)
 {
-	struct kretprobe * rp = (struct kretprobe *) kp;
+    struct kretprobe *rp = (struct kretprobe *) kp;
 
-	kprobe_unregister(kp);
+    kprobe_unregister(kp);
 
-	rp->backup_addr = kp->addr;
-	kp->addr = (void *) stack[REG_LR];
-	kp->pre_handler = rp->handler;
-	kp->post_handler = __kretprobe_post_handler;
+    rp->backup_addr = kp->addr;
+    kp->addr = (void *) stack[REG_LR];
+    kp->pre_handler = rp->handler;
+    kp->post_handler = __kretprobe_post_handler;
 
-	kprobe_register(kp);
-	return 0;
+    kprobe_register(kp);
+    return 0;
 }
 
 int kretprobe_register(struct kretprobe *rp)
 {
-	rp->kp.pre_handler = __kretprobe_pre_handler;
-	rp->kp.post_handler = NULL;
-	return kprobe_register((struct kprobe *) rp);
+    rp->kp.pre_handler = __kretprobe_pre_handler;
+    rp->kp.post_handler = NULL;
+    return kprobe_register((struct kprobe *) rp);
 }
 
 int kretprobe_unregister(struct kretprobe *rp)
 {
-	return kprobe_unregister(&rp->kp);
+    return kprobe_unregister(&rp->kp);
 }
 
 void kprobe_prebreak(uint32_t *stack, uint32_t *kp_regs)
 {
-	struct kprobe *kp = kp_list;
-	while (kp) {
-		if ((uint32_t) kp->addr == stack[REG_PC] && kp->pre_handler)
-			kp->pre_handler(kp, stack, kp_regs);
-		kp = kp->next;
-	}
+    struct kprobe *kp = kp_list;
+    while (kp) {
+        if ((uint32_t) kp->addr == stack[REG_PC] && kp->pre_handler)
+            kp->pre_handler(kp, stack, kp_regs);
+        kp = kp->next;
+    }
 }
 
 void kprobe_postbreak(uint32_t *stack, uint32_t *kp_regs)
 {
-	struct kprobe *kp = kp_list;
-	while (kp) {
-		if ((uint32_t) kp->step_addr == stack[REG_PC] &&
-		    kp->post_handler)
-			kp->post_handler(kp, stack, kp_regs);
-		kp = kp->next;
-	}
+    struct kprobe *kp = kp_list;
+    while (kp) {
+        if ((uint32_t) kp->step_addr == stack[REG_PC] && kp->post_handler)
+            kp->post_handler(kp, stack, kp_regs);
+        kp = kp->next;
+    }
 }
 
 void kprobe_breakpoint_enable(uint32_t *stack)
 {
-	struct kprobe *kp = kp_list;
-	while (kp) {
-		if ((uint32_t) kp->step_addr == stack[REG_PC])
-			enable_breakpoint(kp->bkpt);
-		kp = kp->next;
-	}
+    struct kprobe *kp = kp_list;
+    while (kp) {
+        if ((uint32_t) kp->step_addr == stack[REG_PC])
+            enable_breakpoint(kp->bkpt);
+        kp = kp->next;
+    }
 }
 
 void kprobe_breakpoint_disable(uint32_t *stack)
 {
-	struct kprobe *kp = kp_list;
-	while (kp) {
-		if ((uint32_t) kp->addr == stack[REG_PC])
-			disable_breakpoint(kp->bkpt);
-		kp = kp->next;
-	}
+    struct kprobe *kp = kp_list;
+    while (kp) {
+        if ((uint32_t) kp->addr == stack[REG_PC])
+            disable_breakpoint(kp->bkpt);
+        kp = kp->next;
+    }
 }
diff --git a/kernel/ksym.c b/kernel/ksym.c
index 46d5528e..8bf1ace5 100644
--- a/kernel/ksym.c
+++ b/kernel/ksym.c
@@ -3,11 +3,11 @@
  * found in the LICENSE file.
  */
 
+#include <init_hook.h>
 #include <ksym.h>
-#include <types.h>
 #include <lib/stdlib.h>
-#include <init_hook.h>
 #include <platform/link.h>
+#include <types.h>
 
 static int __ksym_count;
 static const ksym_t *__ksym_tbl;
@@ -15,66 +15,65 @@ static const char *__ksym_strings;
 
 void ksym_init()
 {
-	void *ksym_addr = (void *) &symtab_start;
+    void *ksym_addr = (void *) &symtab_start;
 
-	if (*((int *) ksym_addr) == KSYM_MAGIC) {
-		__ksym_count = *((int *) ksym_addr + 1);
-		__ksym_tbl = (void *) ksym_addr + 8;
-		__ksym_strings = (void *) __ksym_tbl +
-		                 __ksym_count * sizeof(ksym_t);
-	} else {
-		static ksym_t _sym_tbl[] = { { 0, 0 } };
-		static char _sym_strings [] = "No symbol\0";
-		__ksym_count = 1;
-		__ksym_tbl = _sym_tbl;
-		__ksym_strings = _sym_strings;
-	}
+    if (*((int *) ksym_addr) == KSYM_MAGIC) {
+        __ksym_count = *((int *) ksym_addr + 1);
+        __ksym_tbl = (void *) ksym_addr + 8;
+        __ksym_strings = (void *) __ksym_tbl + __ksym_count * sizeof(ksym_t);
+    } else {
+        static ksym_t _sym_tbl[] = {{0, 0}};
+        static char _sym_strings[] = "No symbol\0";
+        __ksym_count = 1;
+        __ksym_tbl = _sym_tbl;
+        __ksym_strings = _sym_strings;
+    }
 }
 
 INIT_HOOK(ksym_init, INIT_LEVEL_KERNEL_EARLY);
 
 int ksym_total()
 {
-	return __ksym_count;
+    return __ksym_count;
 }
 
 static int cmp_key(const void *addr, const void *p1)
 {
-	ksym_t * sym = (ksym_t *)p1;
-	if (sym == (__ksym_tbl + ksym_total() - 1)) {
-		return 0;
-	} else if ((addr >= sym->addr) && (addr < (sym + 1)->addr)) {
-		return 0;
-	} else {
-		return addr - ((ksym_t *) sym)->addr;
-	}
+    ksym_t *sym = (ksym_t *) p1;
+    if (sym == (__ksym_tbl + ksym_total() - 1)) {
+        return 0;
+    } else if ((addr >= sym->addr) && (addr < (sym + 1)->addr)) {
+        return 0;
+    } else {
+        return addr - ((ksym_t *) sym)->addr;
+    }
 }
 
 int ksym_lookup(void *addr)
 {
-	static int prev_index = 0;
-	ksym_t *found;
+    static int prev_index = 0;
+    ksym_t *found;
 
-	if (__ksym_tbl[prev_index].addr < addr) {
-		found = (ksym_t *) bsearch(addr, __ksym_tbl + prev_index,
-		                           __ksym_count - prev_index,
-		                           sizeof(__ksym_tbl[0]), cmp_key);
-	} else {
-		found = (ksym_t *) bsearch(addr, __ksym_tbl, __ksym_count,
-		                           sizeof(__ksym_tbl[0]), cmp_key);
-	}
+    if (__ksym_tbl[prev_index].addr < addr) {
+        found = (ksym_t *) bsearch(addr, __ksym_tbl + prev_index,
+                                   __ksym_count - prev_index,
+                                   sizeof(__ksym_tbl[0]), cmp_key);
+    } else {
+        found = (ksym_t *) bsearch(addr, __ksym_tbl, __ksym_count,
+                                   sizeof(__ksym_tbl[0]), cmp_key);
+    }
 
-	if (!found)
-		return -1;
-	return prev_index = (found - __ksym_tbl);
+    if (!found)
+        return -1;
+    return prev_index = (found - __ksym_tbl);
 }
 
 char *ksym_id2name(int symid)
 {
-	return (char *) &__ksym_strings[__ksym_tbl[symid].strid];
+    return (char *) &__ksym_strings[__ksym_tbl[symid].strid];
 }
 
 void *ksym_id2addr(int symid)
 {
-	return __ksym_tbl[symid].addr;
+    return __ksym_tbl[symid].addr;
 }
diff --git a/kernel/ktimer.c b/kernel/ktimer.c
index e30ec58d..b489d2ce 100644
--- a/kernel/ktimer.c
+++ b/kernel/ktimer.c
@@ -6,13 +6,13 @@
 #include INC_PLAT(systick.h)
 
 #include <debug.h>
+#include <init_hook.h>
 #include <ktimer.h>
 #include <lib/ktable.h>
-#include <softirq.h>
 #include <platform/armv7m.h>
 #include <platform/bitops.h>
 #include <platform/irq.h>
-#include <init_hook.h>
+#include <softirq.h>
 #if defined(CONFIG_KTIMER_TICKLESS) && defined(CONFIG_KTIMER_TICKLESS_VERIFY)
 #include <tickless-verify.h>
 #endif
@@ -35,52 +35,52 @@ extern uint32_t SystemCoreClock;
 
 static void ktimer_init(void)
 {
-	init_systick(CONFIG_KTIMER_HEARTBEAT, 0);
+    init_systick(CONFIG_KTIMER_HEARTBEAT, 0);
 }
 
 static void ktimer_disable(void)
 {
-	if (ktimer_enabled) {
-		ktimer_enabled = 0;
-	}
+    if (ktimer_enabled) {
+        ktimer_enabled = 0;
+    }
 }
 
 static void ktimer_enable(uint32_t delta)
 {
-	/* Always update delta and reset time counter.
-	 * This is called both for initial enable and to reschedule
-	 * when an earlier event is inserted at queue head.
-	 */
-	ktimer_delta = delta;
-	ktimer_time = 0;
-	ktimer_enabled = 1;
-
-#if defined(CONFIG_KDB) && \
-    defined(CONFIG_KTIMER_TICKLESS) && defined(CONFIG_KTIMER_TICKLESS_VERIFY)
-	tickless_verify_start(ktimer_now, ktimer_delta);
-#endif	/* CONFIG_KDB */
+    /* Always update delta and reset time counter.
+     * This is called both for initial enable and to reschedule
+     * when an earlier event is inserted at queue head.
+     */
+    ktimer_delta = delta;
+    ktimer_time = 0;
+    ktimer_enabled = 1;
+
+#if defined(CONFIG_KDB) && defined(CONFIG_KTIMER_TICKLESS) && \
+    defined(CONFIG_KTIMER_TICKLESS_VERIFY)
+    tickless_verify_start(ktimer_now, ktimer_delta);
+#endif /* CONFIG_KDB */
 }
 
 void __ktimer_handler(void)
 {
-	++ktimer_now;
+    ++ktimer_now;
 
-	if (ktimer_enabled && ktimer_delta > 0) {
-		++ktimer_time;
-		--ktimer_delta;
+    if (ktimer_enabled && ktimer_delta > 0) {
+        ++ktimer_time;
+        --ktimer_delta;
 
-		if (ktimer_delta == 0) {
-			ktimer_enabled = 0;
-			ktimer_time = ktimer_delta = 0;
+        if (ktimer_delta == 0) {
+            ktimer_enabled = 0;
+            ktimer_time = ktimer_delta = 0;
 
-#if defined(CONFIG_KDB) && \
-    defined(CONFIG_KTIMER_TICKLESS) && defined(CONFIG_KTIMER_TICKLESS_VERIFY)
-			tickless_verify_stop(ktimer_now);
-#endif	/* CONFIG_KDB */
+#if defined(CONFIG_KDB) && defined(CONFIG_KTIMER_TICKLESS) && \
+    defined(CONFIG_KTIMER_TICKLESS_VERIFY)
+            tickless_verify_stop(ktimer_now);
+#endif /* CONFIG_KDB */
 
-			softirq_schedule(KTE_SOFTIRQ);
-		}
-	}
+            softirq_schedule(KTE_SOFTIRQ);
+        }
+    }
 }
 
 IRQ_HANDLER(ktimer_handler, __ktimer_handler);
@@ -88,226 +88,219 @@ IRQ_HANDLER(ktimer_handler, __ktimer_handler);
 #ifdef CONFIG_KDB
 void kdb_show_ktimer(void)
 {
-	dbg_printf(DL_KDB, "Now is %ld\n", ktimer_now);
+    dbg_printf(DL_KDB, "Now is %ld\n", ktimer_now);
 
-	if (ktimer_enabled) {
-		dbg_printf(DL_KDB,
-		           "Ktimer T=%d D=%d\n", ktimer_time, ktimer_delta);
-	}
+    if (ktimer_enabled) {
+        dbg_printf(DL_KDB, "Ktimer T=%d D=%d\n", ktimer_time, ktimer_delta);
+    }
 }
 
 #if defined(CONFIG_KTIMER_TICKLESS) && defined(CONFIG_KTIMER_TICKLESS_VERIFY)
 void kdb_show_tickless_verify(void)
 {
-	static int init = 0;
-	int32_t avg;
-	int times;
-
-	if (init == 0) {
-		dbg_printf(DL_KDB, "Init tickless verification...\n");
-		tickless_verify_init();
-		init++;
-	} else {
-		avg = tickless_verify_stat(&times);
-		dbg_printf(DL_KDB, "Times: %d\nAverage: %d\n", times, avg);
-	}
+    static int init = 0;
+    int32_t avg;
+    int times;
+
+    if (init == 0) {
+        dbg_printf(DL_KDB, "Init tickless verification...\n");
+        tickless_verify_init();
+        init++;
+    } else {
+        avg = tickless_verify_stat(&times);
+        dbg_printf(DL_KDB, "Times: %d\nAverage: %d\n", times, avg);
+    }
 }
 #endif
-#endif	/* CONFIG_KDB */
+#endif /* CONFIG_KDB */
 
-static void ktimer_event_recalc(ktimer_event_t* event, uint32_t new_delta)
+static void ktimer_event_recalc(ktimer_event_t *event, uint32_t new_delta)
 {
-	if (event) {
-		dbg_printf(DL_KTIMER,
-		           "KTE: Recalculated event %p D=%d -> %d\n",
-		           event, event->delta, event->delta - new_delta);
-		event->delta -= new_delta;
-	}
-
+    if (event) {
+        dbg_printf(DL_KTIMER, "KTE: Recalculated event %p D=%d -> %d\n", event,
+                   event->delta, event->delta - new_delta);
+        event->delta -= new_delta;
+    }
 }
 
 int ktimer_event_schedule(uint32_t ticks, ktimer_event_t *kte)
 {
-	long etime = 0, delta = 0;
-	ktimer_event_t *event = NULL, *next_event = NULL;
-
-	if (!ticks)
-		return -1;
-	dbg_printf(DL_KDB, "KTE: sched ev=%p ticks=%d kt=%d q=%p\n",
-	           kte, ticks, ktimer_time, event_queue);
-
-	/* Adjust for elapsed time. If timeout has already passed
-	 * (ticks <= ktimer_time), schedule for next tick (ticks=1)
-	 * to avoid unsigned underflow.
-	 */
-	if (ticks <= (uint32_t)ktimer_time)
-		ticks = 1;
-	else
-		ticks -= ktimer_time;
-	kte->next = NULL;
-
-	if (!event_queue) {
-		/* All other events are already handled, so simply schedule
-		 * and enable timer
-		 */
-		dbg_printf(DL_KDB,
-		           "KTE: Scheduled event %p on %d (head)\n",
-		           kte, ticks);
-
-		kte->delta = ticks;
-		event_queue = kte;
-
-		ktimer_enable(ticks);
-	} else {
-		/* etime is total delta for event from now (-ktimer_value())
-		 * on each iteration we add delta between events.
-		 *
-		 * Search for event chain until etime is larger than ticks
-		 * e.g ticks = 80
-		 *
-		 * 0---17------------60----------------60---...
-		 *                   ^                 ^
-		 *                   |           (etime + next_event->delta) =
-		 *                   |           = 120 - 17 = 103
-		 *                               etime = 60 - 17 =  43
-		 *
-		 * kte is between event(60) and event(120),
-		 * delta = 80 - 43 = 37
-		 * insert and recalculate:
-		 *
-		 * 0---17------------60-------37-------23---...
-		 *
-		 * */
-		next_event = event_queue;
-
-		if (ticks >= event_queue->delta) {
-			do {
-				event = next_event;
-				etime += event->delta;
-				delta = ticks - etime;
-				next_event = event->next;
-			} while (next_event &&
-			         ticks > (etime + next_event->delta));
-
-			dbg_printf(DL_KTIMER,
-			           "KTE: Scheduled event %p [%p:%p] with "
-			           "D=%d and T=%d\n",
-			           kte, event, next_event, delta, ticks);
-
-			/* Insert into chain and recalculate */
-			event->next = kte;
-		} else {
-			/* Event should be scheduled before earlier event */
-			dbg_printf(DL_KTIMER,
-			           "KTE: Scheduled early event %p with T=%d\n",
-			           kte, ticks);
-
-			event_queue = kte;
-			delta = ticks;
-
-			/* Reset timer */
-			ktimer_enable(ticks);
-		}
-
-		/* Chaining events */
-		if (delta < CONFIG_KTIMER_MINTICKS)
-			delta = 0;
-
-		kte->next = next_event;
-		kte->delta = delta;
-
-		ktimer_event_recalc(next_event, delta);
-	}
-
-	return 0;
+    long etime = 0, delta = 0;
+    ktimer_event_t *event = NULL, *next_event = NULL;
+
+    if (!ticks)
+        return -1;
+    dbg_printf(DL_KDB, "KTE: sched ev=%p ticks=%d kt=%d q=%p\n", kte, ticks,
+               ktimer_time, event_queue);
+
+    /* Adjust for elapsed time. If timeout has already passed
+     * (ticks <= ktimer_time), schedule for next tick (ticks=1)
+     * to avoid unsigned underflow.
+     */
+    if (ticks <= (uint32_t) ktimer_time)
+        ticks = 1;
+    else
+        ticks -= ktimer_time;
+    kte->next = NULL;
+
+    if (!event_queue) {
+        /* All other events are already handled, so simply schedule
+         * and enable timer
+         */
+        dbg_printf(DL_KDB, "KTE: Scheduled event %p on %d (head)\n", kte,
+                   ticks);
+
+        kte->delta = ticks;
+        event_queue = kte;
+
+        ktimer_enable(ticks);
+    } else {
+        /* etime is total delta for event from now (-ktimer_value())
+         * on each iteration we add delta between events.
+         *
+         * Search for event chain until etime is larger than ticks
+         * e.g ticks = 80
+         *
+         * 0---17------------60----------------60---...
+         *                   ^                 ^
+         *                   |           (etime + next_event->delta) =
+         *                   |           = 120 - 17 = 103
+         *                               etime = 60 - 17 =  43
+         *
+         * kte is between event(60) and event(120),
+         * delta = 80 - 43 = 37
+         * insert and recalculate:
+         *
+         * 0---17------------60-------37-------23---...
+         *
+         * */
+        next_event = event_queue;
+
+        if (ticks >= event_queue->delta) {
+            do {
+                event = next_event;
+                etime += event->delta;
+                delta = ticks - etime;
+                next_event = event->next;
+            } while (next_event && ticks > (etime + next_event->delta));
+
+            dbg_printf(DL_KTIMER,
+                       "KTE: Scheduled event %p [%p:%p] with "
+                       "D=%d and T=%d\n",
+                       kte, event, next_event, delta, ticks);
+
+            /* Insert into chain and recalculate */
+            event->next = kte;
+        } else {
+            /* Event should be scheduled before earlier event */
+            dbg_printf(DL_KTIMER, "KTE: Scheduled early event %p with T=%d\n",
+                       kte, ticks);
+
+            event_queue = kte;
+            delta = ticks;
+
+            /* Reset timer */
+            ktimer_enable(ticks);
+        }
+
+        /* Chaining events */
+        if (delta < CONFIG_KTIMER_MINTICKS)
+            delta = 0;
+
+        kte->next = next_event;
+        kte->delta = delta;
+
+        ktimer_event_recalc(next_event, delta);
+    }
+
+    return 0;
 }
 
 ktimer_event_t *ktimer_event_create(uint32_t ticks,
-	                                ktimer_event_handler_t handler,
-	                                void *data)
+                                    ktimer_event_handler_t handler,
+                                    void *data)
 {
-	ktimer_event_t *kte = NULL;
+    ktimer_event_t *kte = NULL;
 
-	if (!handler)
-		goto ret;
+    if (!handler)
+        goto ret;
 
-	kte = (ktimer_event_t *) ktable_alloc(&ktimer_event_table);
+    kte = (ktimer_event_t *) ktable_alloc(&ktimer_event_table);
 
-	/* No available slots */
-	if (!kte)
-		goto ret;
+    /* No available slots */
+    if (!kte)
+        goto ret;
 
-	kte->next = NULL;
-	kte->handler = handler;
-	kte->data = data;
+    kte->next = NULL;
+    kte->handler = handler;
+    kte->data = data;
 
-	if (ktimer_event_schedule(ticks, kte) == -1) {
-		ktable_free(&ktimer_event_table, kte);
-		kte = NULL;
-	}
+    if (ktimer_event_schedule(ticks, kte) == -1) {
+        ktable_free(&ktimer_event_table, kte);
+        kte = NULL;
+    }
 
 ret:
-	return kte;
+    return kte;
 }
 
 void ktimer_event_handler()
 {
-	ktimer_event_t *event = event_queue;
-	ktimer_event_t *last_event = NULL;
-	ktimer_event_t *next_event = NULL;
-	uint32_t h_retvalue  = 0;
-
-	if (!event_queue) {
-		/* That is bug if we are here */
-		dbg_printf(DL_KTIMER, "KTE: OOPS! handler found no events\n");
-
-		ktimer_disable();
-		return;
-	}
-
-	/* Search last event in event chain */
-	do {
-		event = event->next;
-	} while (event && event->delta == 0);
-
-	last_event = event;
-
-	/* All rescheduled events will be scheduled after last event */
-	event = event_queue;
-	event_queue = last_event;
-
-	/* walk chain */
-	do {
-		h_retvalue = event->handler(event);
-		next_event = event->next;
-
-		if (h_retvalue != 0x0) {
-			dbg_printf(DL_KTIMER,
-			           "KTE: Handled and rescheduled event %p @%ld\n",
-			           event, ktimer_now);
-			ktimer_event_schedule(h_retvalue, event);
-		} else {
-			dbg_printf(DL_KTIMER,
-			           "KTE: Handled event %p @%ld\n",
-			           event, ktimer_now);
-			ktable_free(&ktimer_event_table, event);
-		}
-
-		event = next_event;	/* Guaranteed to be next
-					   regardless of re-scheduling */
-	} while (next_event && next_event != last_event);
-
-	if (event_queue) {
-		/* Reset ktimer */
-		ktimer_enable(event_queue->delta);
-	}
+    ktimer_event_t *event = event_queue;
+    ktimer_event_t *last_event = NULL;
+    ktimer_event_t *next_event = NULL;
+    uint32_t h_retvalue = 0;
+
+    if (!event_queue) {
+        /* That is bug if we are here */
+        dbg_printf(DL_KTIMER, "KTE: OOPS! handler found no events\n");
+
+        ktimer_disable();
+        return;
+    }
+
+    /* Search last event in event chain */
+    do {
+        event = event->next;
+    } while (event && event->delta == 0);
+
+    last_event = event;
+
+    /* All rescheduled events will be scheduled after last event */
+    event = event_queue;
+    event_queue = last_event;
+
+    /* walk chain */
+    do {
+        h_retvalue = event->handler(event);
+        next_event = event->next;
+
+        if (h_retvalue != 0x0) {
+            dbg_printf(DL_KTIMER,
+                       "KTE: Handled and rescheduled event %p @%ld\n", event,
+                       ktimer_now);
+            ktimer_event_schedule(h_retvalue, event);
+        } else {
+            dbg_printf(DL_KTIMER, "KTE: Handled event %p @%ld\n", event,
+                       ktimer_now);
+            ktable_free(&ktimer_event_table, event);
+        }
+
+        event = next_event; /* Guaranteed to be next
+                       regardless of re-scheduling */
+    } while (next_event && next_event != last_event);
+
+    if (event_queue) {
+        /* Reset ktimer */
+        ktimer_enable(event_queue->delta);
+    }
 }
 
 void ktimer_event_init()
 {
-	ktable_init(&ktimer_event_table);
-	ktimer_init();
-	softirq_register(KTE_SOFTIRQ, ktimer_event_handler);
+    ktable_init(&ktimer_event_table);
+    ktimer_init();
+    softirq_register(KTE_SOFTIRQ, ktimer_event_handler);
 }
 
 INIT_HOOK(ktimer_event_init, INIT_LEVEL_KERNEL);
@@ -315,16 +308,16 @@ INIT_HOOK(ktimer_event_init, INIT_LEVEL_KERNEL);
 #ifdef CONFIG_KDB
 void kdb_dump_events(void)
 {
-	ktimer_event_t *event = event_queue;
+    ktimer_event_t *event = event_queue;
 
-	dbg_puts("\nktimer events: \n");
-	dbg_printf(DL_KDB, "%8s %12s\n", "EVENT", "DELTA");
+    dbg_puts("\nktimer events: \n");
+    dbg_printf(DL_KDB, "%8s %12s\n", "EVENT", "DELTA");
 
-	while (event) {
-		dbg_printf(DL_KDB, "%p %12d\n", event, event->delta);
+    while (event) {
+        dbg_printf(DL_KDB, "%p %12d\n", event, event->delta);
 
-		event = event->next;
-	}
+        event = event->next;
+    }
 }
 #endif
 
@@ -332,69 +325,72 @@ void kdb_dump_events(void)
 
 #define KTIMER_MAXTICKS (SYSTICK_MAXRELOAD / CONFIG_KTIMER_HEARTBEAT)
 
-static uint32_t volatile ktimer_tickless_compensation = CONFIG_KTIMER_TICKLESS_COMPENSATION;
-static uint32_t volatile ktimer_tickless_int_compensation = CONFIG_KTIMER_TICKLESS_INT_COMPENSATION;
+static uint32_t volatile ktimer_tickless_compensation =
+    CONFIG_KTIMER_TICKLESS_COMPENSATION;
+static uint32_t volatile ktimer_tickless_int_compensation =
+    CONFIG_KTIMER_TICKLESS_INT_COMPENSATION;
 
 void ktimer_enter_tickless()
 {
-	uint32_t tickless_delta;
-	uint32_t reload;
+    uint32_t tickless_delta;
+    uint32_t reload;
 
-	irq_disable();
+    irq_disable();
 
-	if (ktimer_enabled && ktimer_delta <= KTIMER_MAXTICKS) {
-		tickless_delta = ktimer_delta;
-	} else {
-		tickless_delta = KTIMER_MAXTICKS;
-	}
+    if (ktimer_enabled && ktimer_delta <= KTIMER_MAXTICKS) {
+        tickless_delta = ktimer_delta;
+    } else {
+        tickless_delta = KTIMER_MAXTICKS;
+    }
 
-	/* Minus 1 for current value */
-	tickless_delta -= 1;
+    /* Minus 1 for current value */
+    tickless_delta -= 1;
 
-	reload = CONFIG_KTIMER_HEARTBEAT * tickless_delta;
+    reload = CONFIG_KTIMER_HEARTBEAT * tickless_delta;
 
-	reload += systick_now() - ktimer_tickless_compensation;
+    reload += systick_now() - ktimer_tickless_compensation;
 
-	if (reload > 2) {
-		init_systick(reload, CONFIG_KTIMER_HEARTBEAT);
+    if (reload > 2) {
+        init_systick(reload, CONFIG_KTIMER_HEARTBEAT);
 
-#if defined(CONFIG_KDB) && \
-    defined(CONFIG_KTIMER_TICKLESS) && defined(CONFIG_KTIMER_TICKLESS_VERIFY)
-		tickless_verify_count();
+#if defined(CONFIG_KDB) && defined(CONFIG_KTIMER_TICKLESS) && \
+    defined(CONFIG_KTIMER_TICKLESS_VERIFY)
+        tickless_verify_count();
 #endif
-	}
+    }
 
-	wait_for_interrupt();
+    wait_for_interrupt();
 
-	if (!systick_flag_count()) {
-		uint32_t tickless_rest = (systick_now() / CONFIG_KTIMER_HEARTBEAT);
+    if (!systick_flag_count()) {
+        uint32_t tickless_rest = (systick_now() / CONFIG_KTIMER_HEARTBEAT);
 
-		if (tickless_rest > 0) {
-			int reload_overflow;
+        if (tickless_rest > 0) {
+            int reload_overflow;
 
-			tickless_delta = tickless_delta - tickless_rest;
+            tickless_delta = tickless_delta - tickless_rest;
 
-			reload = systick_now() % CONFIG_KTIMER_HEARTBEAT - ktimer_tickless_int_compensation;
-			reload_overflow = reload < 0;
-			reload += reload_overflow * CONFIG_KTIMER_HEARTBEAT;
+            reload = systick_now() % CONFIG_KTIMER_HEARTBEAT -
+                     ktimer_tickless_int_compensation;
+            reload_overflow = reload < 0;
+            reload += reload_overflow * CONFIG_KTIMER_HEARTBEAT;
 
-			init_systick(reload, CONFIG_KTIMER_HEARTBEAT);
+            init_systick(reload, CONFIG_KTIMER_HEARTBEAT);
 
-			if (reload_overflow) {
-				tickless_delta++;
-			}
+            if (reload_overflow) {
+                tickless_delta++;
+            }
 
-#if defined(CONFIG_KDB) && \
-    defined(CONFIG_KTIMER_TICKLESS) && defined(CONFIG_KTIMER_TICKLESS_VERIFY)
-			tickless_verify_count_int();
+#if defined(CONFIG_KDB) && defined(CONFIG_KTIMER_TICKLESS) && \
+    defined(CONFIG_KTIMER_TICKLESS_VERIFY)
+            tickless_verify_count_int();
 #endif
-		}
-	}
+        }
+    }
 
-	ktimer_time += tickless_delta;
-	ktimer_delta -= tickless_delta;
-	ktimer_now += tickless_delta;
+    ktimer_time += tickless_delta;
+    ktimer_delta -= tickless_delta;
+    ktimer_now += tickless_delta;
 
-	irq_enable();
+    irq_enable();
 }
 #endif /* CONFIG_KTIMER_TICKLESS */
diff --git a/kernel/lib/bsearch.c b/kernel/lib/bsearch.c
index df6a2d48..eb989eaa 100644
--- a/kernel/lib/bsearch.c
+++ b/kernel/lib/bsearch.c
@@ -6,8 +6,8 @@
  * found in the LICENSE file.
  */
 
-#include <types.h>
 #include <error.h>
+#include <types.h>
 
 /*
  * Perform a binary search.
@@ -25,23 +25,26 @@
  * have to make lim 3, then halve, obtaining 1, so that we will only
  * look at item 3.
  */
-void *bsearch(const void *key, const void *base0, size_t nmemb, size_t size,
+void *bsearch(const void *key,
+              const void *base0,
+              size_t nmemb,
+              size_t size,
               int (*compar)(const void *, const void *))
 {
-	const char *base = base0;
-	size_t lim;
-	int cmp;
-	const void *p;
+    const char *base = base0;
+    size_t lim;
+    int cmp;
+    const void *p;
 
-	for (lim = nmemb; lim != 0; lim >>= 1) {
-		p = base + (lim >> 1) * size;
-		cmp = (*compar)(key, p);
-		if (cmp == 0)
-			return (void *) p;
-		if (cmp > 0) {	/* key > p: move right */
-			base = (const char *) p + size;
-			lim--;
-		}		/* else move left */
-	}
-	return NULL;
+    for (lim = nmemb; lim != 0; lim >>= 1) {
+        p = base + (lim >> 1) * size;
+        cmp = (*compar)(key, p);
+        if (cmp == 0)
+            return (void *) p;
+        if (cmp > 0) { /* key > p: move right */
+            base = (const char *) p + size;
+            lim--;
+        } /* else move left */
+    }
+    return NULL;
 }
diff --git a/kernel/lib/ktable.c b/kernel/lib/ktable.c
index d8442bb6..8be26fe1 100644
--- a/kernel/lib/ktable.c
+++ b/kernel/lib/ktable.c
@@ -3,8 +3,8 @@
  * found in the LICENSE file.
  */
 
-#include <lib/ktable.h>
 #include <debug.h>
+#include <lib/ktable.h>
 
 #ifdef CONFIG_KDB
 #include <kdb.h>
@@ -15,42 +15,42 @@ static uint8_t kdb_ktable_cnt;
 
 static void kdb_register_ktable(ktable_t *kt)
 {
-	if (kdb_ktable_cnt < (KTABLE_NUM - 1)) {
-		kdb_ktables[kdb_ktable_cnt++] = kt;
-	}
+    if (kdb_ktable_cnt < (KTABLE_NUM - 1)) {
+        kdb_ktables[kdb_ktable_cnt++] = kt;
+    }
 }
 
 void kdb_dump_ktable(void)
 {
-	int i = 0, j;
-	ktable_t *kt;
-
-	for (; i < kdb_ktable_cnt; ++i) {
-		kt = kdb_ktables[i];
-
-		/* Validate ktable before dumping to avoid crash on corruption */
-		if (!kt || !kt->bitmap || !kt->data || kt->num == 0) {
-			dbg_printf(DL_KDB,
-			           "\nKT: [%d] INVALID kt=%p\n", i, kt);
-			continue;
-		}
-
-		dbg_printf(DL_KDB, "\nKT: %s\nbitmap:%p, data:%p, num: %d size: %d\n",
-		           kt->tname, kt->bitmap, kt->data, kt->num, kt->size);
-		/* Dump bitmap */
-		for (j = 0; j < kt->num; ++j) {
-			if (j % 64 == 0)
-				dbg_printf(DL_KDB, "%5d: ", j);
-
-			dbg_putchar((bitmap_get_bit(bitmap_cursor(kt->bitmap, j))) ? 'X' : '-');
-
-			if ((j + 1) % 64 == 0)
-				dbg_puts("\n");
-		}
-	}
+    int i = 0, j;
+    ktable_t *kt;
+
+    for (; i < kdb_ktable_cnt; ++i) {
+        kt = kdb_ktables[i];
+
+        /* Validate ktable before dumping to avoid crash on corruption */
+        if (!kt || !kt->bitmap || !kt->data || kt->num == 0) {
+            dbg_printf(DL_KDB, "\nKT: [%d] INVALID kt=%p\n", i, kt);
+            continue;
+        }
+
+        dbg_printf(DL_KDB, "\nKT: %s\nbitmap:%p, data:%p, num: %d size: %d\n",
+                   kt->tname, kt->bitmap, kt->data, kt->num, kt->size);
+        /* Dump bitmap */
+        for (j = 0; j < kt->num; ++j) {
+            if (j % 64 == 0)
+                dbg_printf(DL_KDB, "%5d: ", j);
+
+            dbg_putchar((bitmap_get_bit(bitmap_cursor(kt->bitmap, j))) ? 'X'
+                                                                       : '-');
+
+            if ((j + 1) % 64 == 0)
+                dbg_puts("\n");
+        }
+    }
 }
 
-#endif	/* CONFIG_KDB */
+#endif /* CONFIG_KDB */
 
 /**
  * Initialize kernel table kt
@@ -59,14 +59,14 @@ void kdb_dump_ktable(void)
  * */
 void ktable_init(ktable_t *kt)
 {
-	char *kt_ptr = (char *) kt->bitmap;
-	char *kt_end = (char *) kt->bitmap + kt->num / 8;
+    char *kt_ptr = (char *) kt->bitmap;
+    char *kt_end = (char *) kt->bitmap + kt->num / 8;
 
-	while (kt_ptr != kt_end)
-		*(kt_ptr++) = 0x0;
+    while (kt_ptr != kt_end)
+        *(kt_ptr++) = 0x0;
 
 #ifdef CONFIG_KDB
-	kdb_register_ktable(kt);
+    kdb_register_ktable(kt);
 #endif
 }
 
@@ -83,10 +83,10 @@ void ktable_init(ktable_t *kt)
  * */
 int ktable_is_allocated(ktable_t *kt, int i)
 {
-	if (i > kt->num)
-		return -1;
+    if (i > kt->num)
+        return -1;
 
-	return bitmap_get_bit(bitmap_cursor(kt->bitmap, i));
+    return bitmap_get_bit(bitmap_cursor(kt->bitmap, i));
 }
 
 /**
@@ -101,20 +101,19 @@ int ktable_is_allocated(ktable_t *kt, int i)
  */
 void *ktable_alloc_id(ktable_t *kt, int i)
 {
-	bitmap_cursor_t	cursor = bitmap_cursor(kt->bitmap, i);
+    bitmap_cursor_t cursor = bitmap_cursor(kt->bitmap, i);
 
-	if (i > kt->num)
-		return NULL;
+    if (i > kt->num)
+        return NULL;
 
-	if (bitmap_test_and_set_bit(cursor)) {
-		dbg_printf(DL_KTABLE,
-		           "KT: %s allocated %d [%p]\n", kt->tname, i,
-		           kt->data + (i * kt->size));
+    if (bitmap_test_and_set_bit(cursor)) {
+        dbg_printf(DL_KTABLE, "KT: %s allocated %d [%p]\n", kt->tname, i,
+                   kt->data + (i * kt->size));
 
-		return (void *) kt->data + (i * kt->size);
-	}
+        return (void *) kt->data + (i * kt->size);
+    }
 
-	return NULL;
+    return NULL;
 }
 
 /**
@@ -129,42 +128,37 @@ void *ktable_alloc_id(ktable_t *kt, int i)
  */
 void *ktable_alloc(ktable_t *kt)
 {
-	bitmap_cursor_t	cursor;
-	int checked = 0;
-
-	/* Validate ktable pointer and fields to detect corruption early.
-	 * A corrupted ktable can cause undefined behavior in bitmap ops.
-	 */
-	if (!kt || !kt->bitmap || !kt->data || kt->num == 0 || kt->size == 0) {
-		dbg_printf(DL_KDB,
-		           "KT: INVALID kt=%p bitmap=%p data=%p num=%d size=%d\n",
-		           kt,
-		           kt ? kt->bitmap : (bitmap_ptr_t)0,
-		           kt ? kt->data : (ptr_t)0,
-		           kt ? (int)kt->num : 0,
-		           kt ? (int)kt->size : 0);
-		return NULL;
-	}
-
-	/* Search for free element */
-	for_each_in_bitmap(cursor, kt->bitmap, kt->num, 0) {
-		checked++;
-		if (bitmap_test_and_set_bit(cursor)) {
-			int i = bitmap_cursor_id(cursor);
-
-			dbg_printf(DL_KTABLE,
-			           "KT: %s allocated %d [%p]\n", kt->tname, i,
-			           kt->data + (i * kt->size));
-
-			return (void *) kt->data + (i * kt->size);
-		}
-	}
-
-	dbg_printf(DL_KDB,
-	           "KT: %s FULL checked=%d num=%d\n",
-	           kt->tname, checked, kt->num);
-
-	return NULL;
+    bitmap_cursor_t cursor;
+    int checked = 0;
+
+    /* Validate ktable pointer and fields to detect corruption early.
+     * A corrupted ktable can cause undefined behavior in bitmap ops.
+     */
+    if (!kt || !kt->bitmap || !kt->data || kt->num == 0 || kt->size == 0) {
+        dbg_printf(
+            DL_KDB, "KT: INVALID kt=%p bitmap=%p data=%p num=%d size=%d\n", kt,
+            kt ? kt->bitmap : (bitmap_ptr_t) 0, kt ? kt->data : (ptr_t) 0,
+            kt ? (int) kt->num : 0, kt ? (int) kt->size : 0);
+        return NULL;
+    }
+
+    /* Search for free element */
+    for_each_in_bitmap (cursor, kt->bitmap, kt->num, 0) {
+        checked++;
+        if (bitmap_test_and_set_bit(cursor)) {
+            int i = bitmap_cursor_id(cursor);
+
+            dbg_printf(DL_KTABLE, "KT: %s allocated %d [%p]\n", kt->tname, i,
+                       kt->data + (i * kt->size));
+
+            return (void *) kt->data + (i * kt->size);
+        }
+    }
+
+    dbg_printf(DL_KDB, "KT: %s FULL checked=%d num=%d\n", kt->tname, checked,
+               kt->num);
+
+    return NULL;
 }
 
 /**
@@ -179,13 +173,13 @@ void *ktable_alloc(ktable_t *kt)
  */
 uint32_t ktable_getid(ktable_t *kt, void *element)
 {
-	int i = ((ptr_t) element - kt->data) / kt->size;
+    int i = ((ptr_t) element - kt->data) / kt->size;
 
-	/* Element does not belong to this ktable */
-	if (i > kt->num || i < 0)
-		return -1;
+    /* Element does not belong to this ktable */
+    if (i > kt->num || i < 0)
+        return -1;
 
-	return i;
+    return i;
 }
 
 /**
@@ -197,14 +191,13 @@ uint32_t ktable_getid(ktable_t *kt, void *element)
  * */
 void ktable_free(ktable_t *kt, void *element)
 {
-	size_t i = ktable_getid(kt, element);
+    size_t i = ktable_getid(kt, element);
 
-	if (i != -1) {
-		bitmap_cursor_t	cursor = bitmap_cursor(kt->bitmap, i);
+    if (i != -1) {
+        bitmap_cursor_t cursor = bitmap_cursor(kt->bitmap, i);
 
-		dbg_printf(DL_KTABLE,
-		           "KT: %s free %d [%p]\n", kt->tname, i, element);
+        dbg_printf(DL_KTABLE, "KT: %s free %d [%p]\n", kt->tname, i, element);
 
-		bitmap_clear_bit(cursor);
-	}
+        bitmap_clear_bit(cursor);
+    }
 }
diff --git a/kernel/lib/memcpy.c b/kernel/lib/memcpy.c
index 8c5dfbb5..dfe601d4 100644
--- a/kernel/lib/memcpy.c
+++ b/kernel/lib/memcpy.c
@@ -4,13 +4,13 @@
  * in the LICENSE file.
  */
 
-#include <types.h>
 #include <lib/string.h>
+#include <types.h>
 
 void *memcpy(void *restrict dest, const void *restrict src, size_t n)
 {
-	unsigned char *d = dest;
-	const unsigned char *s = src;
+    unsigned char *d = dest;
+    const unsigned char *s = src;
 
 #ifdef __GNUC__
 
@@ -22,137 +22,137 @@ void *memcpy(void *restrict dest, const void *restrict src, size_t n)
 #define RS >>
 #endif
 
-	typedef uint32_t __attribute__((__may_alias__)) u32;
-	uint32_t w, x;
+    typedef uint32_t __attribute__((__may_alias__)) u32;
+    uint32_t w, x;
 
-	for (; (uintptr_t) s % 4 && n; n--)
-		*d++ = *s++;
+    for (; (uintptr_t) s % 4 && n; n--)
+        *d++ = *s++;
 
-	if ((uintptr_t) d % 4 == 0) {
-		for (; n >= 16; s += 16, d += 16, n -= 16) {
-			*(u32 *)(d + 0) = *(u32 *)(s + 0);
-			*(u32 *)(d + 4) = *(u32 *)(s + 4);
-			*(u32 *)(d + 8) = *(u32 *)(s + 8);
-			*(u32 *)(d + 12) = *(u32 *)(s + 12);
-		}
-		if (n & 8) {
-			*(u32 *)(d + 0) = *(u32 *)(s + 0);
-			*(u32 *)(d + 4) = *(u32 *)(s + 4);
-			d += 8;
-			s += 8;
-		}
-		if (n & 4) {
-			*(u32 *)(d + 0) = *(u32 *)(s + 0);
-			d += 4;
-			s += 4;
-		}
-		if (n & 2) {
-			*d++ = *s++;
-			*d++ = *s++;
-		}
-		if (n & 1) {
-			*d = *s;
-		}
-		return dest;
-	}
+    if ((uintptr_t) d % 4 == 0) {
+        for (; n >= 16; s += 16, d += 16, n -= 16) {
+            *(u32 *) (d + 0) = *(u32 *) (s + 0);
+            *(u32 *) (d + 4) = *(u32 *) (s + 4);
+            *(u32 *) (d + 8) = *(u32 *) (s + 8);
+            *(u32 *) (d + 12) = *(u32 *) (s + 12);
+        }
+        if (n & 8) {
+            *(u32 *) (d + 0) = *(u32 *) (s + 0);
+            *(u32 *) (d + 4) = *(u32 *) (s + 4);
+            d += 8;
+            s += 8;
+        }
+        if (n & 4) {
+            *(u32 *) (d + 0) = *(u32 *) (s + 0);
+            d += 4;
+            s += 4;
+        }
+        if (n & 2) {
+            *d++ = *s++;
+            *d++ = *s++;
+        }
+        if (n & 1) {
+            *d = *s;
+        }
+        return dest;
+    }
 
-	if (n >= 32)
-		switch ((uintptr_t) d % 4) {
-		case 1:
-			w = *(u32 *) s;
-			*d++ = *s++;
-			*d++ = *s++;
-			*d++ = *s++;
-			n -= 3;
-			for (; n >= 17; s += 16, d += 16, n -= 16) {
-				x = *(u32 *)(s + 1);
-				*(u32 *)(d + 0) = (w LS 24) | (x RS 8);
-				w = *(u32 *)(s + 5);
-				*(u32 *)(d + 4) = (x LS 24) | (w RS 8);
-				x = *(u32 *)(s + 9);
-				*(u32 *)(d + 8) = (w LS 24) | (x RS 8);
-				w = *(u32 *)(s + 13);
-				*(u32 *)(d + 12) = (x LS 24) | (w RS 8);
-			}
-			break;
-		case 2:
-			w = *(u32 *) s;
-			*d++ = *s++;
-			*d++ = *s++;
-			n -= 2;
-			for (; n >= 18; s += 16, d += 16, n -= 16) {
-				x = *(u32 *)(s + 2);
-				*(u32 *)(d + 0) = (w LS 16) | (x RS 16);
-				w = *(u32 *)(s + 6);
-				*(u32 *)(d + 4) = (x LS 16) | (w RS 16);
-				x = *(u32 *)(s + 10);
-				*(u32 *)(d + 8) = (w LS 16) | (x RS 16);
-				w = *(u32 *)(s + 14);
-				*(u32 *)(d + 12) = (x LS 16) | (w RS 16);
-			}
-			break;
-		case 3:
-			w = *(u32 *) s;
-			*d++ = *s++;
-			n -= 1;
-			for (; n >= 19; s += 16, d += 16, n -= 16) {
-				x = *(u32 *)(s + 3);
-				*(u32 *)(d + 0) = (w LS 8) | (x RS 24);
-				w = *(u32 *)(s + 7);
-				*(u32 *)(d + 4) = (x LS 8) | (w RS 24);
-				x = *(u32 *)(s + 11);
-				*(u32 *)(d + 8) = (w LS 8) | (x RS 24);
-				w = *(u32 *)(s + 15);
-				*(u32 *)(d + 12) = (x LS 8) | (w RS 24);
-			}
-			break;
-		}
-	if (n & 16) {
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-	}
-	if (n & 8) {
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-	}
-	if (n & 4) {
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-		*d++ = *s++;
-	}
-	if (n & 2) {
-		*d++ = *s++;
-		*d++ = *s++;
-	}
-	if (n & 1) {
-		*d = *s;
-	}
-	return dest;
+    if (n >= 32)
+        switch ((uintptr_t) d % 4) {
+        case 1:
+            w = *(u32 *) s;
+            *d++ = *s++;
+            *d++ = *s++;
+            *d++ = *s++;
+            n -= 3;
+            for (; n >= 17; s += 16, d += 16, n -= 16) {
+                x = *(u32 *) (s + 1);
+                *(u32 *) (d + 0) = (w LS 24) | (x RS 8);
+                w = *(u32 *) (s + 5);
+                *(u32 *) (d + 4) = (x LS 24) | (w RS 8);
+                x = *(u32 *) (s + 9);
+                *(u32 *) (d + 8) = (w LS 24) | (x RS 8);
+                w = *(u32 *) (s + 13);
+                *(u32 *) (d + 12) = (x LS 24) | (w RS 8);
+            }
+            break;
+        case 2:
+            w = *(u32 *) s;
+            *d++ = *s++;
+            *d++ = *s++;
+            n -= 2;
+            for (; n >= 18; s += 16, d += 16, n -= 16) {
+                x = *(u32 *) (s + 2);
+                *(u32 *) (d + 0) = (w LS 16) | (x RS 16);
+                w = *(u32 *) (s + 6);
+                *(u32 *) (d + 4) = (x LS 16) | (w RS 16);
+                x = *(u32 *) (s + 10);
+                *(u32 *) (d + 8) = (w LS 16) | (x RS 16);
+                w = *(u32 *) (s + 14);
+                *(u32 *) (d + 12) = (x LS 16) | (w RS 16);
+            }
+            break;
+        case 3:
+            w = *(u32 *) s;
+            *d++ = *s++;
+            n -= 1;
+            for (; n >= 19; s += 16, d += 16, n -= 16) {
+                x = *(u32 *) (s + 3);
+                *(u32 *) (d + 0) = (w LS 8) | (x RS 24);
+                w = *(u32 *) (s + 7);
+                *(u32 *) (d + 4) = (x LS 8) | (w RS 24);
+                x = *(u32 *) (s + 11);
+                *(u32 *) (d + 8) = (w LS 8) | (x RS 24);
+                w = *(u32 *) (s + 15);
+                *(u32 *) (d + 12) = (x LS 8) | (w RS 24);
+            }
+            break;
+        }
+    if (n & 16) {
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+    }
+    if (n & 8) {
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+    }
+    if (n & 4) {
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+        *d++ = *s++;
+    }
+    if (n & 2) {
+        *d++ = *s++;
+        *d++ = *s++;
+    }
+    if (n & 1) {
+        *d = *s;
+    }
+    return dest;
 #endif
 
-	for (; n; n--)
-		*d++ = *s++;
+    for (; n; n--)
+        *d++ = *s++;
 
-	return dest;
+    return dest;
 }
diff --git a/kernel/lib/memset.c b/kernel/lib/memset.c
index 0d7d9da5..37b53e3d 100644
--- a/kernel/lib/memset.c
+++ b/kernel/lib/memset.c
@@ -4,103 +4,103 @@
  * in the LICENSE file.
  */
 
-#include <types.h>
 #include <lib/string.h>
+#include <types.h>
 
 void *memset(void *dest, int c, size_t n)
 {
-	unsigned char *s = dest;
-	size_t k;
+    unsigned char *s = dest;
+    size_t k;
 #ifdef __GNUC__
-	typedef uint32_t __attribute__((__may_alias__)) u32;
-	typedef uint64_t __attribute__((__may_alias__)) u64;
-	u32 c32;
-	u64 c64;
+    typedef uint32_t __attribute__((__may_alias__)) u32;
+    typedef uint64_t __attribute__((__may_alias__)) u64;
+    u32 c32;
+    u64 c64;
 #endif
 
-	/* Fill head and tail with minimal branching. Each
-	 * conditional ensures that all the subsequently used
-	 * offsets are well-defined and in the dest region.
-	 */
+    /* Fill head and tail with minimal branching. Each
+     * conditional ensures that all the subsequently used
+     * offsets are well-defined and in the dest region.
+     */
 
-	if (!n)
-		return dest;
-	s[0] = s[n - 1] = c;
-	if (n <= 2)
-		return dest;
-	s[1] = s[n - 2] = c;
-	s[2] = s[n - 3] = c;
-	if (n <= 6)
-		return dest;
-	s[3] = s[n - 4] = c;
-	if (n <= 8)
-		return dest;
+    if (!n)
+        return dest;
+    s[0] = s[n - 1] = c;
+    if (n <= 2)
+        return dest;
+    s[1] = s[n - 2] = c;
+    s[2] = s[n - 3] = c;
+    if (n <= 6)
+        return dest;
+    s[3] = s[n - 4] = c;
+    if (n <= 8)
+        return dest;
 
-	/* Advance pointer to align it at a 4-byte boundary,
-	 * and truncate n to a multiple of 4. The previous code
-	 * already took care of any head/tail that get cut off
-	 * by the alignment.
-	 */
+    /* Advance pointer to align it at a 4-byte boundary,
+     * and truncate n to a multiple of 4. The previous code
+     * already took care of any head/tail that get cut off
+     * by the alignment.
+     */
 
-	k = - (uintptr_t) s & 3;
-	s += k;
-	n -= k;
-	n &= -4;
+    k = -(uintptr_t) s & 3;
+    s += k;
+    n -= k;
+    n &= -4;
 
 #ifdef __GNUC__
-	c32 = ((u32) - 1) / 255 * (unsigned char) c;
-	/* In preparation to copy 32 bytes at a time, aligned on
-	 * an 8-byte bounary, fill head/tail up to 28 bytes each.
-	 * As in the initial byte-based head/tail fill, each
-	 * conditional below ensures that the subsequent offsets
-	 * are valid (e.g. !(n<=24) implies n>=28).
-	 */
+    c32 = ((u32) -1) / 255 * (unsigned char) c;
+    /* In preparation to copy 32 bytes at a time, aligned on
+     * an 8-byte bounary, fill head/tail up to 28 bytes each.
+     * As in the initial byte-based head/tail fill, each
+     * conditional below ensures that the subsequent offsets
+     * are valid (e.g. !(n<=24) implies n>=28).
+     */
 
-	*(u32 *)(s + 0) = c32;
-	*(u32 *)(s + n - 4) = c32;
-	if (n <= 8)
-		return dest;
-	*(u32 *)(s + 4) = c32;
-	*(u32 *)(s + 8) = c32;
-	*(u32 *)(s + n - 12) = c32;
-	*(u32 *)(s + n - 8) = c32;
-	if (n <= 24)
-		return dest;
-	*(u32 *)(s + 12) = c32;
-	*(u32 *)(s + 16) = c32;
-	*(u32 *)(s + 20) = c32;
-	*(u32 *)(s + 24) = c32;
-	*(u32 *)(s + n - 28) = c32;
-	*(u32 *)(s + n - 24) = c32;
-	*(u32 *)(s + n - 20) = c32;
-	*(u32 *)(s + n - 16) = c32;
+    *(u32 *) (s + 0) = c32;
+    *(u32 *) (s + n - 4) = c32;
+    if (n <= 8)
+        return dest;
+    *(u32 *) (s + 4) = c32;
+    *(u32 *) (s + 8) = c32;
+    *(u32 *) (s + n - 12) = c32;
+    *(u32 *) (s + n - 8) = c32;
+    if (n <= 24)
+        return dest;
+    *(u32 *) (s + 12) = c32;
+    *(u32 *) (s + 16) = c32;
+    *(u32 *) (s + 20) = c32;
+    *(u32 *) (s + 24) = c32;
+    *(u32 *) (s + n - 28) = c32;
+    *(u32 *) (s + n - 24) = c32;
+    *(u32 *) (s + n - 20) = c32;
+    *(u32 *) (s + n - 16) = c32;
 
-	/* Align to a multiple of 8 so we can fill 64 bits at a time,
-	 * and avoid writing the same bytes twice as much as is
-	 * practical without introducing additional branching.
-	 */
+    /* Align to a multiple of 8 so we can fill 64 bits at a time,
+     * and avoid writing the same bytes twice as much as is
+     * practical without introducing additional branching.
+     */
 
-	k = 24 + ((uintptr_t) s & 4);
-	s += k;
-	n -= k;
+    k = 24 + ((uintptr_t) s & 4);
+    s += k;
+    n -= k;
 
-	/* If this loop is reached, 28 tail bytes have already been
-	 * filled, so any remainder when n drops below 32 can be
-	 * safely ignored.
-	 */
+    /* If this loop is reached, 28 tail bytes have already been
+     * filled, so any remainder when n drops below 32 can be
+     * safely ignored.
+     */
 
-	c64 = c32 | ((u64)c32 << 32);
-	for (; n >= 32; n -= 32, s += 32) {
-		*(u64 *)(s + 0) = c64;
-		*(u64 *)(s + 8) = c64;
-		*(u64 *)(s + 16) = c64;
-		*(u64 *)(s + 24) = c64;
-	}
+    c64 = c32 | ((u64) c32 << 32);
+    for (; n >= 32; n -= 32, s += 32) {
+        *(u64 *) (s + 0) = c64;
+        *(u64 *) (s + 8) = c64;
+        *(u64 *) (s + 16) = c64;
+        *(u64 *) (s + 24) = c64;
+    }
 #else
-	/* Pure C fallback with no aliasing violations. */
-	for (; n; n--, s++)
-		*s = c;
+    /* Pure C fallback with no aliasing violations. */
+    for (; n; n--, s++)
+        *s = c;
 #endif
 
-	return dest;
+    return dest;
 }
diff --git a/kernel/lib/queue.c b/kernel/lib/queue.c
index 92c4f62c..5077a09c 100644
--- a/kernel/lib/queue.c
+++ b/kernel/lib/queue.c
@@ -7,52 +7,51 @@
 
 static uint32_t queue_length(struct queue_t *queue)
 {
-	return (queue->end >= queue->top) ?
-	       (queue->end - queue->top) :
-	       (queue->size + queue->top - queue->end);
+    return (queue->end >= queue->top) ? (queue->end - queue->top)
+                                      : (queue->size + queue->top - queue->end);
 }
 
 uint32_t queue_init(struct queue_t *queue, uint8_t *addr, size_t size)
 {
-	queue->top = 0;
-	queue->end = 0;
-	queue->size = size;
-	queue->data = addr;
+    queue->top = 0;
+    queue->end = 0;
+    queue->size = size;
+    queue->data = addr;
 
-	return QUEUE_OK;
+    return QUEUE_OK;
 }
 
 uint32_t queue_push(struct queue_t *queue, uint8_t element)
 {
-	if (queue_length(queue) == queue->size)
-		return QUEUE_OVERFLOW;
+    if (queue_length(queue) == queue->size)
+        return QUEUE_OVERFLOW;
 
-	++queue->end;
+    ++queue->end;
 
-	if (queue->end == (queue->size - 1))
-		queue->end = 0;
+    if (queue->end == (queue->size - 1))
+        queue->end = 0;
 
-	queue->data[queue->end] = element;
+    queue->data[queue->end] = element;
 
-	return QUEUE_OK;
+    return QUEUE_OK;
 }
 
 int queue_is_empty(struct queue_t *queue)
 {
-	return queue_length(queue) == 0;
+    return queue_length(queue) == 0;
 }
 
 uint32_t queue_pop(struct queue_t *queue, uint8_t *element)
 {
-	if (queue_length(queue) == 0)
-		return QUEUE_EMPTY;
+    if (queue_length(queue) == 0)
+        return QUEUE_EMPTY;
 
-	++queue->top;
+    ++queue->top;
 
-	if (queue->top == (queue->size - 1))
-		queue->top = 0;
+    if (queue->top == (queue->size - 1))
+        queue->top = 0;
 
-	*element = queue->data[queue->top];
+    *element = queue->data[queue->top];
 
-	return QUEUE_OK;
+    return QUEUE_OK;
 }
diff --git a/kernel/lib/sort.c b/kernel/lib/sort.c
index de5296b6..c155fd66 100644
--- a/kernel/lib/sort.c
+++ b/kernel/lib/sort.c
@@ -13,35 +13,33 @@
 #include <types.h>
 
 /* Qsort routine from Bentley & McIlroy's "Engineering a Sort Function" */
-#define swapcode(TYPE, parmi, parmj, n)			\
-	{						\
-		long i = (n) / sizeof (TYPE);		\
-		TYPE *pi = (TYPE *) (parmi);		\
-		TYPE *pj = (TYPE *) (parmj);		\
-		do {					\
-			TYPE t = *pi;			\
-			*pi++ = *pj;			\
-			*pj++ = t;			\
-		} while (--i > 0);			\
-	}
+#define swapcode(TYPE, parmi, parmj, n) \
+    {                                   \
+        long i = (n) / sizeof(TYPE);    \
+        TYPE *pi = (TYPE *) (parmi);    \
+        TYPE *pj = (TYPE *) (parmj);    \
+        do {                            \
+            TYPE t = *pi;               \
+            *pi++ = *pj;                \
+            *pj++ = t;                  \
+        } while (--i > 0);              \
+    }
 
-#define SWAPINIT(a, es)						\
-	swaptype = ((char *) a - (char *) 0) % sizeof(long) ||	\
-		es % sizeof(long) ?				\
-			2 : es == sizeof(long) ?		\
-				0 : 1;
+#define SWAPINIT(a, es)                                                      \
+    swaptype = ((char *) a - (char *) 0) % sizeof(long) || es % sizeof(long) \
+                   ? 2                                                       \
+               : es == sizeof(long) ? 0                                      \
+                                    : 1;
 
 static inline void swapfunc(char *a, char *b, int n, int swaptype)
 {
-	if (swaptype <= 1)
-		swapcode(long, a, b, n)
-	else
-		swapcode(char, a, b, n)
+    if (swaptype <= 1)
+        swapcode(long, a, b, n) else swapcode(char, a, b, n)
 }
 
-#define vecswap(a, b, n)			\
-	if ((n) > 0)				\
-		swapfunc(a, b, n, swaptype)
+#define vecswap(a, b, n) \
+    if ((n) > 0)         \
+    swapfunc(a, b, n, swaptype)
 
 /**
  * sorting time is O(n log n) both on average and worst-case.
@@ -50,41 +48,41 @@ static inline void swapfunc(char *a, char *b, int n, int swaptype)
  * O(n*n) worst-case behavior and extra memory requirements that make it
  * less suitable for kernel use.
  */
-void sort(void *base, size_t num, size_t size,
+void sort(void *base,
+          size_t num,
+          size_t size,
           int (*cmp_func)(const void *, const void *))
 {
-	int i = (num / 2 - 1) * size;
-	int n = num * size;
-	int c, r;
+    int i = (num / 2 - 1) * size;
+    int n = num * size;
+    int c, r;
 
-	int swaptype;
+    int swaptype;
 
-	SWAPINIT(base, size);
+    SWAPINIT(base, size);
 
-	/* perform a heapsort on the given array */
-	for (; i >= 0; i -= size) {
-		for (r = i; r * 2 + size < n; r  = c) {
-			c = r * 2 + size;
-			if (c < n - size &&
-			    cmp_func(base + c, base + c + size) < 0)
-				c += size;
-			if (cmp_func(base + r, base + c) >= 0)
-				break;
-			vecswap(base + r, base + c, size);
-		}
-	}
+    /* perform a heapsort on the given array */
+    for (; i >= 0; i -= size) {
+        for (r = i; r * 2 + size < n; r = c) {
+            c = r * 2 + size;
+            if (c < n - size && cmp_func(base + c, base + c + size) < 0)
+                c += size;
+            if (cmp_func(base + r, base + c) >= 0)
+                break;
+            vecswap(base + r, base + c, size);
+        }
+    }
 
-	/* sort */
-	for (i = n - size; i > 0; i -= size) {
-		vecswap(base, base + i, size);
-		for (r = 0; r * 2 + size < i; r = c) {
-			c = r * 2 + size;
-			if (c < i - size &&
-			    cmp_func(base + c, base + c + size) < 0)
-				c += size;
-			if (cmp_func(base + r, base + c) >= 0)
-				break;
-			vecswap(base + r, base + c, size);
-		}
-	}
+    /* sort */
+    for (i = n - size; i > 0; i -= size) {
+        vecswap(base, base + i, size);
+        for (r = 0; r * 2 + size < i; r = c) {
+            c = r * 2 + size;
+            if (c < i - size && cmp_func(base + c, base + c + size) < 0)
+                c += size;
+            if (cmp_func(base + r, base + c) >= 0)
+                break;
+            vecswap(base + r, base + c, size);
+        }
+    }
 }
diff --git a/kernel/lib/stdio.c b/kernel/lib/stdio.c
index f2283316..07610473 100644
--- a/kernel/lib/stdio.c
+++ b/kernel/lib/stdio.c
@@ -8,159 +8,154 @@
 
 void __l4_puts(char *str)
 {
-	while (*str) {
-		if (*str == '\n')
-			__l4_putchar('\r');
-		__l4_putchar(*(str++));
-	}
+    while (*str) {
+        if (*str == '\n')
+            __l4_putchar('\r');
+        __l4_putchar(*(str++));
+    }
 }
 
 static void __l4_puts_x(char *str, int width, const char pad)
 {
-	while (*str) {
-		if (*str == '\n')
-			__l4_putchar('\r');
-		__l4_putchar(*(str++));
-		--width;
-	}
-
-	while (width > 0) {
-		__l4_putchar(pad);
-		--width;
-	}
+    while (*str) {
+        if (*str == '\n')
+            __l4_putchar('\r');
+        __l4_putchar(*(str++));
+        --width;
+    }
+
+    while (width > 0) {
+        __l4_putchar(pad);
+        --width;
+    }
 }
 
-#define hexchars(x)			\
-	(((x) < 10) ?			\
-		('0' + (x)) :		\
-	 	('a' + ((x) - 10)))
+#define hexchars(x) (((x) < 10) ? ('0' + (x)) : ('a' + ((x) - 10)))
 
 static int __l4_put_hex(const uint32_t val, int width, const char pad)
 {
-	int i, n = 0;
-	int nwidth = 0;
-
-	/* Find width of hexnumber */
-	while ((val >> (4 * nwidth)) && ((unsigned) nwidth <  2 * sizeof(val)))
-		nwidth++;
-	if (nwidth == 0)
-		nwidth = 1;
-
-	/* May need to increase number of printed characters */
-	if (width == 0 && width < nwidth)
-		width = nwidth;
-
-	/* Print number with padding */
-	for (i = width - nwidth; i > 0; i--, n++)
-		__l4_putchar(pad);
-	for (i = 4 * (nwidth - 1); i >= 0; i -= 4, n++)
-		__l4_putchar(hexchars((val >> i) & 0xF));
-
-	return n;
+    int i, n = 0;
+    int nwidth = 0;
+
+    /* Find width of hexnumber */
+    while ((val >> (4 * nwidth)) && ((unsigned) nwidth < 2 * sizeof(val)))
+        nwidth++;
+    if (nwidth == 0)
+        nwidth = 1;
+
+    /* May need to increase number of printed characters */
+    if (width == 0 && width < nwidth)
+        width = nwidth;
+
+    /* Print number with padding */
+    for (i = width - nwidth; i > 0; i--, n++)
+        __l4_putchar(pad);
+    for (i = 4 * (nwidth - 1); i >= 0; i -= 4, n++)
+        __l4_putchar(hexchars((val >> i) & 0xF));
+
+    return n;
 }
 
 static void __l4_put_dec(const uint32_t val, const int width, const char pad)
 {
-	uint32_t divisor;
-	int digits;
+    uint32_t divisor;
+    int digits;
 
-	/* estimate number of spaces and digits */
-	for (divisor = 1, digits = 1; val / divisor >= 10; divisor *= 10, digits++)
-		/* */ ;
+    /* estimate number of spaces and digits */
+    for (divisor = 1, digits = 1; val / divisor >= 10; divisor *= 10, digits++)
+        /* */;
 
-	/* print spaces */
-	for (; digits < width; digits++)
-		__l4_putchar(pad);
+    /* print spaces */
+    for (; digits < width; digits++)
+        __l4_putchar(pad);
 
-	/* print digits */
-	do {
-		__l4_putchar(((val / divisor) % 10) + '0');
-	} while (divisor /= 10);
+    /* print digits */
+    do {
+        __l4_putchar(((val / divisor) % 10) + '0');
+    } while (divisor /= 10);
 }
 
 
 void __l4_printf(char *fmt, ...)
 {
-	va_list va;
-	va_start(va, fmt);
-	__l4_vprintf(fmt, va);
-	va_end(va);
+    va_list va;
+    va_start(va, fmt);
+    __l4_vprintf(fmt, va);
+    va_end(va);
 }
 
 void __l4_vprintf(char *fmt, va_list va)
 {
-	int mode = 0;	/* 0: usual char; 1: specifiers */
-	int width = 0;
-	char pad = ' ';
-	int size = 16;
-
-	while (*fmt) {
-		if (*fmt == '%') {
-			mode = 1;
-			pad = ' ';
-			width = 0;
-			size = 32;
-
-			fmt++;
-			continue;
-		}
-
-		if (!mode) {
-			if (*fmt == '\n')
-				__l4_putchar('\r');
-			__l4_putchar(*fmt);
-		} else {
-			switch (*fmt) {
-			case 'c':
-				__l4_putchar(va_arg(va, uint32_t));
-				mode = 0;
-				break;
-			case 's':
-				__l4_puts_x(va_arg(va, char *), width, pad);
-				mode = 0;
-				break;
-			case 'l':
-			case 'L':
-				size = 64;
-				break;
-			case 'd':
-			case 'D':
-				__l4_put_dec((size == 32) ?
-				             va_arg(va, uint32_t) :
-				             va_arg(va, uint64_t),
-				             width, pad);
-				mode = 0;
-				break;
-			case 'p':
-			case 't':
-				size = 32;
-				width = 8;
-				pad = '0';
-			case 'x':
-			case 'X':
-				__l4_put_hex((size == 32) ?
-				             va_arg(va, uint32_t) :
-				             va_arg(va, uint64_t),
-				             width, pad);
-				mode = 0;
-				break;
-			case '%':
-				__l4_putchar('%');
-				mode = 0;
-				break;
-			case '0':
-				if (!width)
-					pad = '0';
-				break;
-			case ' ':
-				pad = ' ';
-			}
-
-			if (*fmt >= '0' && *fmt <= '9') {
-				width = width * 10 + (*fmt - '0');
-			}
-		}
-
-		fmt++;
-	}
+    int mode = 0; /* 0: usual char; 1: specifiers */
+    int width = 0;
+    char pad = ' ';
+    int size = 16;
+
+    while (*fmt) {
+        if (*fmt == '%') {
+            mode = 1;
+            pad = ' ';
+            width = 0;
+            size = 32;
+
+            fmt++;
+            continue;
+        }
+
+        if (!mode) {
+            if (*fmt == '\n')
+                __l4_putchar('\r');
+            __l4_putchar(*fmt);
+        } else {
+            switch (*fmt) {
+            case 'c':
+                __l4_putchar(va_arg(va, uint32_t));
+                mode = 0;
+                break;
+            case 's':
+                __l4_puts_x(va_arg(va, char *), width, pad);
+                mode = 0;
+                break;
+            case 'l':
+            case 'L':
+                size = 64;
+                break;
+            case 'd':
+            case 'D':
+                __l4_put_dec(
+                    (size == 32) ? va_arg(va, uint32_t) : va_arg(va, uint64_t),
+                    width, pad);
+                mode = 0;
+                break;
+            case 'p':
+            case 't':
+                size = 32;
+                width = 8;
+                pad = '0';
+            case 'x':
+            case 'X':
+                __l4_put_hex(
+                    (size == 32) ? va_arg(va, uint32_t) : va_arg(va, uint64_t),
+                    width, pad);
+                mode = 0;
+                break;
+            case '%':
+                __l4_putchar('%');
+                mode = 0;
+                break;
+            case '0':
+                if (!width)
+                    pad = '0';
+                break;
+            case ' ':
+                pad = ' ';
+            }
+
+            if (*fmt >= '0' && *fmt <= '9') {
+                width = width * 10 + (*fmt - '0');
+            }
+        }
+
+        fmt++;
+    }
 }
diff --git a/kernel/lib/strcmp.c b/kernel/lib/strcmp.c
index 880009ac..3a1a03f3 100644
--- a/kernel/lib/strcmp.c
+++ b/kernel/lib/strcmp.c
@@ -9,6 +9,7 @@
 
 int strcmp(const char *l, const char *r)
 {
-	for (; *l == *r && *l && *r; l++, r++);
-	return *(unsigned char *) l - *(unsigned char *) r;
+    for (; *l == *r && *l && *r; l++, r++)
+        ;
+    return *(unsigned char *) l - *(unsigned char *) r;
 }
diff --git a/kernel/memory.c b/kernel/memory.c
index a2cf803d..544b8373 100644
--- a/kernel/memory.c
+++ b/kernel/memory.c
@@ -3,16 +3,16 @@
  * found in the LICENSE file.
  */
 
-#include <memory.h>
-#include <error.h>
 #include <debug.h>
-#include <thread.h>
-#include <lib/ktable.h>
+#include <error.h>
 #include <fpage_impl.h>
 #include <init_hook.h>
 #include <kip.h>
+#include <lib/ktable.h>
+#include <memory.h>
 #include <platform/cortex_m.h>
 #include <platform/irq.h>
+#include <thread.h>
 
 /**
  * @file    memory.c
@@ -47,64 +47,136 @@
  * Translated into memdesc array in KIP by memory_init
  */
 static mempool_t memmap[] = {
-	DECLARE_MEMPOOL_2("KTEXT", kernel_text,
-		MP_KR | MP_KX | MP_NO_FPAGE, MPT_KERNEL_TEXT),
-	DECLARE_MEMPOOL_2("UTEXT", user_text,
-		MP_UR | MP_UX | MP_MEMPOOL | MP_MAP_ALWAYS, MPT_USER_TEXT),
-	DECLARE_MEMPOOL_2("KIP", kip,
-		MP_KR | MP_KW | MP_UR | MP_SRAM, MPT_KERNEL_DATA),
-	DECLARE_MEMPOOL("KDATA", &kip_end, &kernel_data_end,
-		MP_KR | MP_KW | MP_NO_FPAGE, MPT_KERNEL_DATA),
-	DECLARE_MEMPOOL_2("KBSS",  kernel_bss,
-		MP_KR | MP_KW | MP_NO_FPAGE, MPT_KERNEL_DATA),
-	DECLARE_MEMPOOL_2("UDATA", user_data,
-		MP_UR | MP_UW | MP_MEMPOOL | MP_MAP_ALWAYS, MPT_USER_DATA),
-	DECLARE_MEMPOOL_2("UBSS",  user_bss,
-		MP_UR | MP_UW | MP_MEMPOOL  | MP_MAP_ALWAYS, MPT_USER_DATA),
-	DECLARE_MEMPOOL("MEM0",  &mem0_start, 0x2001c000,
-		MP_UR | MP_UW | MP_SRAM, MPT_AVAILABLE),
+    DECLARE_MEMPOOL_2("KTEXT",
+                      kernel_text,
+                      MP_KR | MP_KX | MP_NO_FPAGE,
+                      MPT_KERNEL_TEXT),
+    DECLARE_MEMPOOL_2("UTEXT",
+                      user_text,
+                      MP_UR | MP_UX | MP_MEMPOOL | MP_MAP_ALWAYS,
+                      MPT_USER_TEXT),
+    DECLARE_MEMPOOL_2("KIP",
+                      kip,
+                      MP_KR | MP_KW | MP_UR | MP_SRAM,
+                      MPT_KERNEL_DATA),
+    DECLARE_MEMPOOL("KDATA",
+                    &kip_end,
+                    &kernel_data_end,
+                    MP_KR | MP_KW | MP_NO_FPAGE,
+                    MPT_KERNEL_DATA),
+    DECLARE_MEMPOOL_2("KBSS",
+                      kernel_bss,
+                      MP_KR | MP_KW | MP_NO_FPAGE,
+                      MPT_KERNEL_DATA),
+    DECLARE_MEMPOOL_2("UDATA",
+                      user_data,
+                      MP_UR | MP_UW | MP_MEMPOOL | MP_MAP_ALWAYS,
+                      MPT_USER_DATA),
+    DECLARE_MEMPOOL_2("UBSS",
+                      user_bss,
+                      MP_UR | MP_UW | MP_MEMPOOL | MP_MAP_ALWAYS,
+                      MPT_USER_DATA),
+    DECLARE_MEMPOOL("MEM0",
+                    &mem0_start,
+                    0x2001c000,
+                    MP_UR | MP_UW | MP_SRAM,
+                    MPT_AVAILABLE),
 #ifdef CONFIG_BITMAP_BITBAND
-	DECLARE_MEMPOOL("KBITMAP",  &bitmap_bitband_start, &bitmap_bitband_end,
-		MP_KR | MP_KW | MP_NO_FPAGE, MPT_KERNEL_DATA),
+    DECLARE_MEMPOOL("KBITMAP",
+                    &bitmap_bitband_start,
+                    &bitmap_bitband_end,
+                    MP_KR | MP_KW | MP_NO_FPAGE,
+                    MPT_KERNEL_DATA),
 #else
-	DECLARE_MEMPOOL("KBITMAP",  &bitmap_start, &bitmap_end,
-		MP_KR | MP_KW | MP_NO_FPAGE, MPT_KERNEL_DATA),
+    DECLARE_MEMPOOL("KBITMAP",
+                    &bitmap_start,
+                    &bitmap_end,
+                    MP_KR | MP_KW | MP_NO_FPAGE,
+                    MPT_KERNEL_DATA),
 #endif
-	DECLARE_MEMPOOL("MEM1",   &mem1_start, 0x10010000,
-		MP_UR | MP_UW | MP_AHB_RAM, MPT_AVAILABLE),
-	DECLARE_MEMPOOL("APB1DEV", 0x40000000, 0x40007800,
-		MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES),
-	DECLARE_MEMPOOL("APB2_1DEV", 0x40010000, 0x40014c00,
-		MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES),
-	DECLARE_MEMPOOL("APB2_2DEV", 0x40014000, 0x40014c00,
-		MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES),
-	DECLARE_MEMPOOL("AHB1_1DEV", 0x40020000, 0x40023c00,
-		MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES),
-	DECLARE_MEMPOOL("AHB1_2DEV", 0x40023c00, 0x40040000,
-		MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES),
-	DECLARE_MEMPOOL("AHB2DEV", 0x50000000, 0x50061000,
-		MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES),
-	DECLARE_MEMPOOL("AHB3DEV", 0x60000000, 0xA0001000,
-		MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES),
+    DECLARE_MEMPOOL("MEM1",
+                    &mem1_start,
+                    0x10010000,
+                    MP_UR | MP_UW | MP_AHB_RAM,
+                    MPT_AVAILABLE),
+    DECLARE_MEMPOOL("APB1DEV",
+                    0x40000000,
+                    0x40007800,
+                    MP_UR | MP_UW | MP_DEVICES,
+                    MPT_DEVICES),
+    DECLARE_MEMPOOL("APB2_1DEV",
+                    0x40010000,
+                    0x40014c00,
+                    MP_UR | MP_UW | MP_DEVICES,
+                    MPT_DEVICES),
+    DECLARE_MEMPOOL("APB2_2DEV",
+                    0x40014000,
+                    0x40014c00,
+                    MP_UR | MP_UW | MP_DEVICES,
+                    MPT_DEVICES),
+    DECLARE_MEMPOOL("AHB1_1DEV",
+                    0x40020000,
+                    0x40023c00,
+                    MP_UR | MP_UW | MP_DEVICES,
+                    MPT_DEVICES),
+    DECLARE_MEMPOOL("AHB1_2DEV",
+                    0x40023c00,
+                    0x40040000,
+                    MP_UR | MP_UW | MP_DEVICES,
+                    MPT_DEVICES),
+    DECLARE_MEMPOOL("AHB2DEV",
+                    0x50000000,
+                    0x50061000,
+                    MP_UR | MP_UW | MP_DEVICES,
+                    MPT_DEVICES),
+    DECLARE_MEMPOOL("AHB3DEV",
+                    0x60000000,
+                    0xA0001000,
+                    MP_UR | MP_UW | MP_DEVICES,
+                    MPT_DEVICES),
 #ifdef CONFIG_BOARD_STM32F429DISCOVERY
-	DECLARE_MEMPOOL("APB2_3DEV", 0x40015000, 0x40015c00,
-		MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES),
-	DECLARE_MEMPOOL("APB2_4DEV", 0x40016800, 0x40017900,
-		MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES),
-	DECLARE_MEMPOOL("CR_PLLSAION_BB", 0x42470000, 0x42470c00,
-		MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES),
-	DECLARE_MEMPOOL("LCD_FRAME_BUFFER_1", 0xD0000000, 0xD00A0000,
-		MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES),
-	DECLARE_MEMPOOL("LCD_FRAME_BUFFER_2", 0xD00A0000, 0xD0140000,
-		MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES),
+    DECLARE_MEMPOOL("APB2_3DEV",
+                    0x40015000,
+                    0x40015c00,
+                    MP_UR | MP_UW | MP_DEVICES,
+                    MPT_DEVICES),
+    DECLARE_MEMPOOL("APB2_4DEV",
+                    0x40016800,
+                    0x40017900,
+                    MP_UR | MP_UW | MP_DEVICES,
+                    MPT_DEVICES),
+    DECLARE_MEMPOOL("CR_PLLSAION_BB",
+                    0x42470000,
+                    0x42470c00,
+                    MP_UR | MP_UW | MP_DEVICES,
+                    MPT_DEVICES),
+    DECLARE_MEMPOOL("LCD_FRAME_BUFFER_1",
+                    0xD0000000,
+                    0xD00A0000,
+                    MP_UR | MP_UW | MP_DEVICES,
+                    MPT_DEVICES),
+    DECLARE_MEMPOOL("LCD_FRAME_BUFFER_2",
+                    0xD00A0000,
+                    0xD0140000,
+                    MP_UR | MP_UW | MP_DEVICES,
+                    MPT_DEVICES),
 #endif
 #ifdef CONFIG_BOARD_STM32F429NUCLEO
-	DECLARE_MEMPOOL("APB2_3DEV", 0x40015000, 0x40015c00,
-		MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES),
-	DECLARE_MEMPOOL("APB2_4DEV", 0x40016800, 0x40017900,
-		MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES),
-	DECLARE_MEMPOOL("CR_PLLSAION_BB", 0x42470000, 0x42470c00,
-		MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES),
+    DECLARE_MEMPOOL("APB2_3DEV",
+                    0x40015000,
+                    0x40015c00,
+                    MP_UR | MP_UW | MP_DEVICES,
+                    MPT_DEVICES),
+    DECLARE_MEMPOOL("APB2_4DEV",
+                    0x40016800,
+                    0x40017900,
+                    MP_UR | MP_UW | MP_DEVICES,
+                    MPT_DEVICES),
+    DECLARE_MEMPOOL("CR_PLLSAION_BB",
+                    0x42470000,
+                    0x42470c00,
+                    MP_UR | MP_UW | MP_DEVICES,
+                    MPT_DEVICES),
 #endif
 };
 
@@ -117,37 +189,37 @@ extern char *kip_extra;
 /* size value must be 2^k */
 static memptr_t addr_align_up(memptr_t addr, size_t size)
 {
-	memptr_t mask = ~(size - 1);
-	memptr_t aligned = (addr + (size - 1)) & mask;
-	/* Check for overflow: if aligned < addr, return max aligned value */
-	if (aligned < addr)
-		return mask;
-	return aligned;
+    memptr_t mask = ~(size - 1);
+    memptr_t aligned = (addr + (size - 1)) & mask;
+    /* Check for overflow: if aligned < addr, return max aligned value */
+    if (aligned < addr)
+        return mask;
+    return aligned;
 }
 
 static memptr_t addr_align_down(memptr_t addr, size_t size)
 {
-	return addr & ~(size - 1);
+    return addr & ~(size - 1);
 }
 
-#define CONFIG_SMALLEST_FPAGE_SIZE	(1 << CONFIG_SMALLEST_FPAGE_SHIFT)
+#define CONFIG_SMALLEST_FPAGE_SIZE (1 << CONFIG_SMALLEST_FPAGE_SHIFT)
 
 /* Align size up to fpage boundary (for determining region end) */
 memptr_t mempool_align(int mpid, memptr_t addr)
 {
-	if (memmap[mpid].flags & MP_FPAGE_MASK)
-		return addr_align_up(addr, CONFIG_SMALLEST_FPAGE_SIZE);
+    if (memmap[mpid].flags & MP_FPAGE_MASK)
+        return addr_align_up(addr, CONFIG_SMALLEST_FPAGE_SIZE);
 
-	return INVALID_FPAGE_REGION;
+    return INVALID_FPAGE_REGION;
 }
 
 /* Align base address down to fpage boundary (for region start) */
 memptr_t mempool_align_base(int mpid, memptr_t addr)
 {
-	if (memmap[mpid].flags & MP_FPAGE_MASK)
-		return addr_align_down(addr, CONFIG_SMALLEST_FPAGE_SIZE);
+    if (memmap[mpid].flags & MP_FPAGE_MASK)
+        return addr_align_down(addr, CONFIG_SMALLEST_FPAGE_SIZE);
 
-	return INVALID_FPAGE_REGION;
+    return INVALID_FPAGE_REGION;
 }
 
 /*
@@ -156,79 +228,77 @@ memptr_t mempool_align_base(int mpid, memptr_t addr)
  */
 int addr_is_fpage_aligned(memptr_t addr)
 {
-	return (addr & (CONFIG_SMALLEST_FPAGE_SIZE - 1)) == 0;
+    return (addr & (CONFIG_SMALLEST_FPAGE_SIZE - 1)) == 0;
 }
 
 int mempool_search(memptr_t base, size_t size)
 {
-	memptr_t end;
+    memptr_t end;
 
-	/* Check for overflow in base + size */
-	if (size > 0 && base > (memptr_t)-1 - size + 1)
-		return -1;  /* Overflow would occur */
+    /* Check for overflow in base + size */
+    if (size > 0 && base > (memptr_t) -1 - size + 1)
+        return -1; /* Overflow would occur */
 
-	end = base + size;
+    end = base + size;
 
-	for (int i = 0; i < sizeof(memmap) / sizeof(mempool_t); ++i) {
-		if ((memmap[i].start <= base) &&
-		    (memmap[i].end >= end)) {
-			return i;
-		}
-	}
-	return -1;
+    for (int i = 0; i < sizeof(memmap) / sizeof(mempool_t); ++i) {
+        if ((memmap[i].start <= base) && (memmap[i].end >= end)) {
+            return i;
+        }
+    }
+    return -1;
 }
 
 mempool_t *mempool_getbyid(int mpid)
 {
-	if (mpid == -1)
-		return NULL;
+    if (mpid == -1)
+        return NULL;
 
-	return memmap + mpid;
+    return memmap + mpid;
 }
 
 void memory_init()
 {
-	int j = 0;
-	uint32_t *shcsr = (uint32_t *) 0xE000ED24;
-
-	/* Verify and set STKALIGN for 8-byte stack alignment on exceptions.
-	 * This is critical for Cortex-M: misaligned stacks cause HardFault.
-	 * STKALIGN (bit 9 of CCR) ensures automatic 8-byte alignment.
-	 */
-	if (!(*SCB_CCR & SCB_CCR_STKALIGN)) {
-		*SCB_CCR |= SCB_CCR_STKALIGN;
-		__ISB();
-	}
-
-	fpages_init();
-
-	ktable_init(&as_table);
-
-	mem_desc = (kip_mem_desc_t *) kip_extra;
-
-	/* Initialize mempool table in KIP */
-	for (int i = 0; i < sizeof(memmap) / sizeof(mempool_t); ++i) {
-		switch (memmap[i].tag) {
-		case MPT_USER_DATA:
-		case MPT_USER_TEXT:
-		case MPT_DEVICES:
-		case MPT_AVAILABLE:
-			mem_desc[j].base = addr_align_up(
-					(memmap[i].start),
-			                CONFIG_SMALLEST_FPAGE_SIZE) | i;
-			mem_desc[j].size = addr_align_up(
-					(memmap[i].end - memmap[i].start),
-					CONFIG_SMALLEST_FPAGE_SIZE) | memmap[i].tag;
-			j++;
-			break;
-		}
-	}
-
-	kip.memory_info.s.memory_desc_ptr =
-	    ((void *) mem_desc) - ((void *) &kip);
-	kip.memory_info.s.n = j;
-
-	*shcsr |= 1 << 16;	/* Enable memfault */
+    int j = 0;
+    uint32_t *shcsr = (uint32_t *) 0xE000ED24;
+
+    /* Verify and set STKALIGN for 8-byte stack alignment on exceptions.
+     * This is critical for Cortex-M: misaligned stacks cause HardFault.
+     * STKALIGN (bit 9 of CCR) ensures automatic 8-byte alignment.
+     */
+    if (!(*SCB_CCR & SCB_CCR_STKALIGN)) {
+        *SCB_CCR |= SCB_CCR_STKALIGN;
+        __ISB();
+    }
+
+    fpages_init();
+
+    ktable_init(&as_table);
+
+    mem_desc = (kip_mem_desc_t *) kip_extra;
+
+    /* Initialize mempool table in KIP */
+    for (int i = 0; i < sizeof(memmap) / sizeof(mempool_t); ++i) {
+        switch (memmap[i].tag) {
+        case MPT_USER_DATA:
+        case MPT_USER_TEXT:
+        case MPT_DEVICES:
+        case MPT_AVAILABLE:
+            mem_desc[j].base =
+                addr_align_up((memmap[i].start), CONFIG_SMALLEST_FPAGE_SIZE) |
+                i;
+            mem_desc[j].size = addr_align_up((memmap[i].end - memmap[i].start),
+                                             CONFIG_SMALLEST_FPAGE_SIZE) |
+                               memmap[i].tag;
+            j++;
+            break;
+        }
+    }
+
+    kip.memory_info.s.memory_desc_ptr = ((void *) mem_desc) - ((void *) &kip);
+    kip.memory_info.s.n = j;
+
+    *shcsr |= 1 << 16; /* Enable memfault */
 }
 
 INIT_HOOK(memory_init, INIT_LEVEL_KERNEL_EARLY);
@@ -237,161 +307,163 @@ INIT_HOOK(memory_init, INIT_LEVEL_KERNEL_EARLY);
  * AS functions
  */
 
-void as_setup_mpu(as_t *as, memptr_t sp, memptr_t pc,
-                  memptr_t stack_base, size_t stack_size)
+void as_setup_mpu(as_t *as,
+                  memptr_t sp,
+                  memptr_t pc,
+                  memptr_t stack_base,
+                  size_t stack_size)
 {
-	fpage_t *mpu[8] = { NULL };
-	fpage_t *fp;
-	int mpu_first_i;
-	int i, j;
-
-	fpage_t *mpu_stack_first = NULL;
-	memptr_t start = stack_base;
-	memptr_t end = stack_base + stack_size;
-
-	/* Find stack fpages */
-	fp = as->first;
-	i = 0;
-	while (i < 8 && fp && start < end) {
-		if (addr_in_fpage(start, fp, 0)) {
-			if (!mpu_stack_first)
-				mpu_stack_first = fp;
-
-			mpu[i++] = fp;
-			start = FPAGE_END(fp);
-		}
-		fp = fp->as_next;
-	}
-
-	as->mpu_stack_first = mpu_stack_first;
-	mpu_first_i = i;
-
-	/*
-	 * We walk through fpage list
-	 * mpu_fp[0] are pc
-	 * mpu_fp[1] are always-mapped fpages
-	 * mpu_fp[2] are others
-	 */
-	fp = as->mpu_first;
-	if (!fp) {
-		fpage_t *mpu_first[3] = {NULL};
-		fpage_t *mpu_fp[3] = {NULL};
-
-		fp = as->first;
-		while (fp) {
-			int priv = 2;
-
-			if (addr_in_fpage(pc, fp, 0)) {
-				priv = 0;
-			} else if (fp->fpage.flags & FPAGE_ALWAYS) {
-				priv = 1;
-			}
-
-			if (!mpu_first[priv]) {
-				mpu_first[priv] = fp;
-				mpu_fp[priv] = fp;
-			} else {
-				mpu_fp[priv]->mpu_next = fp;
-				mpu_fp[priv] = fp;
-			}
-
-			fp = fp->as_next;
-		}
-
-		if (mpu_first[1]) {
-			mpu_fp[1]->mpu_next = mpu_first[2];
-		} else {
-			mpu_first[1] = mpu_first[2];
-		}
-		if (mpu_first[0]) {
-			mpu_fp[0]->mpu_next = mpu_first[1];
-		} else {
-			mpu_first[0] = mpu_first[1];
-		}
-		as->mpu_first = mpu_first[0];
-	}
-
-	/* Prevent link to stack pages */
-	for (fp = as->mpu_first; i < 8 && fp; fp = fp->mpu_next) {
-		for (j = 0; j < mpu_first_i; j++) {
-			if (fp == mpu[j]) {
-				break;
-			}
-		}
-
-		if (j == mpu_first_i) {
-			mpu[i++] = fp;
-		}
-	}
-
-	as->mpu_first = mpu[mpu_first_i];
-
-	/* Setup MPU stack regions */
-	for (j = 0; j < mpu_first_i; ++j) {
-		mpu_setup_region(j, mpu[j]);
-
-		if (j < mpu_first_i - 1)
-			mpu[j]->mpu_next = mpu[j + 1];
-		else
-			mpu[j]->mpu_next = NULL;
-	}
-
-	/* Setup MPU fifo regions */
-	for (; j < i; ++j) {
-		mpu_setup_region(j, mpu[j]);
-
-		if (j < i - 1)
-			mpu[j]->mpu_next = mpu[j + 1];
-	}
-
-	/* Clean unused MPU regions */
-	for (; j < 8; ++j) {
-		mpu_setup_region(j, NULL);
-	}
+    fpage_t *mpu[8] = {NULL};
+    fpage_t *fp;
+    int mpu_first_i;
+    int i, j;
+
+    fpage_t *mpu_stack_first = NULL;
+    memptr_t start = stack_base;
+    memptr_t end = stack_base + stack_size;
+
+    /* Find stack fpages */
+    fp = as->first;
+    i = 0;
+    while (i < 8 && fp && start < end) {
+        if (addr_in_fpage(start, fp, 0)) {
+            if (!mpu_stack_first)
+                mpu_stack_first = fp;
+
+            mpu[i++] = fp;
+            start = FPAGE_END(fp);
+        }
+        fp = fp->as_next;
+    }
+
+    as->mpu_stack_first = mpu_stack_first;
+    mpu_first_i = i;
+
+    /*
+     * We walk through fpage list
+     * mpu_fp[0] are pc
+     * mpu_fp[1] are always-mapped fpages
+     * mpu_fp[2] are others
+     */
+    fp = as->mpu_first;
+    if (!fp) {
+        fpage_t *mpu_first[3] = {NULL};
+        fpage_t *mpu_fp[3] = {NULL};
+
+        fp = as->first;
+        while (fp) {
+            int priv = 2;
+
+            if (addr_in_fpage(pc, fp, 0)) {
+                priv = 0;
+            } else if (fp->fpage.flags & FPAGE_ALWAYS) {
+                priv = 1;
+            }
+
+            if (!mpu_first[priv]) {
+                mpu_first[priv] = fp;
+                mpu_fp[priv] = fp;
+            } else {
+                mpu_fp[priv]->mpu_next = fp;
+                mpu_fp[priv] = fp;
+            }
+
+            fp = fp->as_next;
+        }
+
+        if (mpu_first[1]) {
+            mpu_fp[1]->mpu_next = mpu_first[2];
+        } else {
+            mpu_first[1] = mpu_first[2];
+        }
+        if (mpu_first[0]) {
+            mpu_fp[0]->mpu_next = mpu_first[1];
+        } else {
+            mpu_first[0] = mpu_first[1];
+        }
+        as->mpu_first = mpu_first[0];
+    }
+
+    /* Prevent link to stack pages */
+    for (fp = as->mpu_first; i < 8 && fp; fp = fp->mpu_next) {
+        for (j = 0; j < mpu_first_i; j++) {
+            if (fp == mpu[j]) {
+                break;
+            }
+        }
+
+        if (j == mpu_first_i) {
+            mpu[i++] = fp;
+        }
+    }
+
+    as->mpu_first = mpu[mpu_first_i];
+
+    /* Setup MPU stack regions */
+    for (j = 0; j < mpu_first_i; ++j) {
+        mpu_setup_region(j, mpu[j]);
+
+        if (j < mpu_first_i - 1)
+            mpu[j]->mpu_next = mpu[j + 1];
+        else
+            mpu[j]->mpu_next = NULL;
+    }
+
+    /* Setup MPU fifo regions */
+    for (; j < i; ++j) {
+        mpu_setup_region(j, mpu[j]);
+
+        if (j < i - 1)
+            mpu[j]->mpu_next = mpu[j + 1];
+    }
+
+    /* Clean unused MPU regions */
+    for (; j < 8; ++j) {
+        mpu_setup_region(j, NULL);
+    }
 }
 
 void as_map_user(as_t *as)
 {
-	for (int i = 0; i < sizeof(memmap) / sizeof(mempool_t); ++i) {
-		switch (memmap[i].tag) {
-		case MPT_USER_DATA:
-		case MPT_USER_TEXT:
-		case MPT_DEVICES:
-			/* Map user text, data and hardware device memory */
-			assign_fpages(as, memmap[i].start,
-			              (memmap[i].end - memmap[i].start));
-		}
-	}
+    for (int i = 0; i < sizeof(memmap) / sizeof(mempool_t); ++i) {
+        switch (memmap[i].tag) {
+        case MPT_USER_DATA:
+        case MPT_USER_TEXT:
+        case MPT_DEVICES:
+            /* Map user text, data and hardware device memory */
+            assign_fpages(as, memmap[i].start,
+                          (memmap[i].end - memmap[i].start));
+        }
+    }
 }
 
 void as_map_ktext(as_t *as)
 {
-	for (int i = 0; i < sizeof(memmap) / sizeof(mempool_t); ++i) {
-		if (memmap[i].tag == MPT_KERNEL_TEXT) {
-			assign_fpages(as, memmap[i].start,
-			              (memmap[i].end - memmap[i].start));
-		}
-	}
+    for (int i = 0; i < sizeof(memmap) / sizeof(mempool_t); ++i) {
+        if (memmap[i].tag == MPT_KERNEL_TEXT) {
+            assign_fpages(as, memmap[i].start,
+                          (memmap[i].end - memmap[i].start));
+        }
+    }
 }
 
 as_t *as_create(uint32_t as_spaceid)
 {
-	as_t *as = (as_t *) ktable_alloc(&as_table);
-
-	if (!as) {
-		dbg_printf(DL_KDB,
-		           "AS: Failed to allocate address space for %p\n",
-		           as_spaceid);
-		return NULL;
-	}
-
-	as->as_spaceid = as_spaceid;
-	as->first = NULL;
-	as->mpu_first = NULL;
-	as->mpu_stack_first = NULL;
-	as->shared = 1;  /* Creator holds initial reference */
-
-	return as;
+    as_t *as = (as_t *) ktable_alloc(&as_table);
+
+    if (!as) {
+        dbg_printf(DL_KDB, "AS: Failed to allocate address space for %p\n",
+                   as_spaceid);
+        return NULL;
+    }
+
+    as->as_spaceid = as_spaceid;
+    as->first = NULL;
+    as->mpu_first = NULL;
+    as->mpu_stack_first = NULL;
+    as->shared = 1; /* Creator holds initial reference */
+
+    return as;
 }
 
 /*
@@ -400,14 +472,14 @@ as_t *as_create(uint32_t as_spaceid)
  */
 void as_get(as_t *as)
 {
-	uint32_t flags;
+    uint32_t flags;
 
-	if (!as)
-		return;
+    if (!as)
+        return;
 
-	flags = irq_save_flags();
-	as->shared++;
-	irq_restore_flags(flags);
+    flags = irq_save_flags();
+    as->shared++;
+    irq_restore_flags(flags);
 }
 
 /*
@@ -417,26 +489,25 @@ void as_get(as_t *as)
  */
 void as_put(as_t *as)
 {
-	uint32_t flags;
-
-	if (!as)
-		return;
-
-	flags = irq_save_flags();
-
-	/* Guard against refcount underflow (double-put bug) */
-	if (as->shared == 0) {
-		irq_restore_flags(flags);
-		dbg_printf(DL_KDB, "AS: refcount underflow for %p\n",
-		           as->as_spaceid);
-		return;
-	}
-
-	if (--as->shared == 0) {
-		/* Keep IRQs disabled through destroy */
-		as_destroy(as);
-	}
-	irq_restore_flags(flags);
+    uint32_t flags;
+
+    if (!as)
+        return;
+
+    flags = irq_save_flags();
+
+    /* Guard against refcount underflow (double-put bug) */
+    if (as->shared == 0) {
+        irq_restore_flags(flags);
+        dbg_printf(DL_KDB, "AS: refcount underflow for %p\n", as->as_spaceid);
+        return;
+    }
+
+    if (--as->shared == 0) {
+        /* Keep IRQs disabled through destroy */
+        as_destroy(as);
+    }
+    irq_restore_flags(flags);
 }
 
 /*
@@ -446,252 +517,244 @@ void as_put(as_t *as)
  */
 void as_destroy(as_t *as)
 {
-	fpage_t *fp, *fpnext;
-	fp = as->first;
+    fpage_t *fp, *fpnext;
+    fp = as->first;
 
-	/*
-	 * FIXME: What if a CLONED fpage which is MAPPED is to be deleted
-	 */
-	while (fp) {
-		fpnext = fp->as_next;
+    /*
+     * FIXME: What if a CLONED fpage which is MAPPED is to be deleted
+     */
+    while (fp) {
+        fpnext = fp->as_next;
 
-		if (fp->fpage.flags & FPAGE_CLONE)
-			unmap_fpage(as, fp);
-		else
-			destroy_fpage(fp);
+        if (fp->fpage.flags & FPAGE_CLONE)
+            unmap_fpage(as, fp);
+        else
+            destroy_fpage(fp);
 
-		fp = fpnext;
-	}
+        fp = fpnext;
+    }
 
-	ktable_free(&as_table, (void *) as);
+    ktable_free(&as_table, (void *) as);
 }
 
-int map_area(as_t *src, as_t *dst, memptr_t base, size_t size,
-             map_action_t action, int is_privileged)
+int map_area(as_t *src,
+             as_t *dst,
+             memptr_t base,
+             size_t size,
+             map_action_t action,
+             int is_privileged)
 {
-	/* Most complicated part of mapping subsystem */
-	memptr_t end, probe = base;
-
-	/* Check for overflow in base + size */
-	if (size > 0 && base > (memptr_t)-1 - size + 1)
-		return -1;  /* Overflow would occur */
-
-	end = base + size;
-	fpage_t *fp = src->first, *first = NULL, *last = NULL;
-	int last_invalid = 0;
-
-	dbg_printf(DL_MEMORY,
-	           "MEM: map_area base:%p, size:%p, priv:%d\n",
-	           base, size, is_privileged);
-
-	/* FIXME: reverse mappings (i.e. thread 1 maps 0x1000 to thread 2,
-	 * than thread 2 does the same to thread 1).
-	 */
-
-	/* For priviliged thread (ROOT), we use shadowed mapping,
-	 * so first we will check if that fpages exist and then
-	 * create them.
-	 */
-
-	/* FIXME: checking existence of fpages */
-
-	if (is_privileged) {
-		if (assign_fpages_ext(-1, src, base, size, &first, &last) < 0) {
-			/* Cannot create fpages for this region */
-			return -1;
-		}
-		if (src == dst) {
-			/* Maps to itself, ignore other actions */
-			return 0;
-		}
-	} else {
-		if (src == dst) {
-			/* Maps to itself, ignore other actions */
-			return 0;
-		}
-		/* We should determine first and last fpage we will map to:
-		 *
-		 * +----------+    +----------+    +----------+
-		 * |   first  | -> |          | -> |  last    |
-		 * +----------+    +----------+    +----------+
-		 *     ^base            ^    +size      =    ^end
-		 *                      | probe
-		 *
-		 * probe checks that addresses in fpage are sequental
-		 */
-		while (fp) {
-			if (!first && addr_in_fpage(base, fp, 0)) {
-				first = fp;
-			}
-
-			if (!last && addr_in_fpage(end, fp, 1)) {
-				last = fp;
-				break;
-			}
-
-			if (first) {
-				/* Check weather if addresses in fpage list
-				 * are sequental
-				 */
-				if (!addr_in_fpage(probe, fp, 1))
-					return -1;
-
-				probe += (1 << fp->fpage.shift);
-			}
-
-			fp = fp->as_next;
-		}
-	}
-
-	if (!last || !first) {
-		/* Not in address space or error */
-		return -1;
-	}
-
-	if (first == last)
-		last_invalid = 1;
-
-	/* That is a problem because we should split
-	 * fpages into two (and split all mappings too)
-	 */
-
-	first = split_fpage(src, first, base, 1);
-
-	/* If first and last were same pages, after first split,
-	 * last fpage will be invalidated, so we search it again
-	 */
-	if (last_invalid) {
-		fp = first;
-		while (fp) {
-			if (addr_in_fpage(end, fp, 1)) {
-				last = fp;
-				break;
-			}
-			fp = fp->as_next;
-		}
-	}
-
-	last  = split_fpage(src, last, end, 0);
-
-	if (!last || !first) {
-		/* Splitting not supported for mapped pages */
-		/* UNIMPLIMENTED */
-		dbg_printf(DL_KDB,
-		           "MEM: map_area split failed: first=%p last=%p base=%p\n",
-		           first, last, base);
-		return -1;
-	}
-
-	/* Map chain of fpages */
-
-	fp = first;
-	while (fp != last) {
-		if (map_fpage(src, dst, fp, action) < 0) {
-			dbg_printf(DL_KDB,
-			           "MEM: map_area fpage map failed: fp=%p\n", fp);
-			return -1;
-		}
-		fp = fp->as_next;
-	}
-	if (map_fpage(src, dst, fp, action) < 0) {
-		dbg_printf(DL_KDB,
-		           "MEM: map_area final fpage map failed: fp=%p\n", fp);
-		return -1;
-	}
-
-	return 0;
+    /* Most complicated part of mapping subsystem */
+    memptr_t end, probe = base;
+
+    /* Check for overflow in base + size */
+    if (size > 0 && base > (memptr_t) -1 - size + 1)
+        return -1; /* Overflow would occur */
+
+    end = base + size;
+    fpage_t *fp = src->first, *first = NULL, *last = NULL;
+    int last_invalid = 0;
+
+    dbg_printf(DL_MEMORY, "MEM: map_area base:%p, size:%p, priv:%d\n", base,
+               size, is_privileged);
+
+    /* FIXME: reverse mappings (i.e. thread 1 maps 0x1000 to thread 2,
+     * than thread 2 does the same to thread 1).
+     */
+
+    /* For priviliged thread (ROOT), we use shadowed mapping,
+     * so first we will check if that fpages exist and then
+     * create them.
+     */
+
+    /* FIXME: checking existence of fpages */
+
+    if (is_privileged) {
+        if (assign_fpages_ext(-1, src, base, size, &first, &last) < 0) {
+            /* Cannot create fpages for this region */
+            return -1;
+        }
+        if (src == dst) {
+            /* Maps to itself, ignore other actions */
+            return 0;
+        }
+    } else {
+        if (src == dst) {
+            /* Maps to itself, ignore other actions */
+            return 0;
+        }
+        /* We should determine first and last fpage we will map to:
+         *
+         * +----------+    +----------+    +----------+
+         * |   first  | -> |          | -> |  last    |
+         * +----------+    +----------+    +----------+
+         *     ^base            ^    +size      =    ^end
+         *                      | probe
+         *
+         * probe checks that addresses in fpage are sequental
+         */
+        while (fp) {
+            if (!first && addr_in_fpage(base, fp, 0)) {
+                first = fp;
+            }
+
+            if (!last && addr_in_fpage(end, fp, 1)) {
+                last = fp;
+                break;
+            }
+
+            if (first) {
+                /* Check weather if addresses in fpage list
+                 * are sequental
+                 */
+                if (!addr_in_fpage(probe, fp, 1))
+                    return -1;
+
+                probe += (1 << fp->fpage.shift);
+            }
+
+            fp = fp->as_next;
+        }
+    }
+
+    if (!last || !first) {
+        /* Not in address space or error */
+        return -1;
+    }
+
+    if (first == last)
+        last_invalid = 1;
+
+    /* That is a problem because we should split
+     * fpages into two (and split all mappings too)
+     */
+
+    first = split_fpage(src, first, base, 1);
+
+    /* If first and last were same pages, after first split,
+     * last fpage will be invalidated, so we search it again
+     */
+    if (last_invalid) {
+        fp = first;
+        while (fp) {
+            if (addr_in_fpage(end, fp, 1)) {
+                last = fp;
+                break;
+            }
+            fp = fp->as_next;
+        }
+    }
+
+    last = split_fpage(src, last, end, 0);
+
+    if (!last || !first) {
+        /* Splitting not supported for mapped pages */
+        /* UNIMPLIMENTED */
+        dbg_printf(DL_KDB,
+                   "MEM: map_area split failed: first=%p last=%p base=%p\n",
+                   first, last, base);
+        return -1;
+    }
+
+    /* Map chain of fpages */
+
+    fp = first;
+    while (fp != last) {
+        if (map_fpage(src, dst, fp, action) < 0) {
+            dbg_printf(DL_KDB, "MEM: map_area fpage map failed: fp=%p\n", fp);
+            return -1;
+        }
+        fp = fp->as_next;
+    }
+    if (map_fpage(src, dst, fp, action) < 0) {
+        dbg_printf(DL_KDB, "MEM: map_area final fpage map failed: fp=%p\n", fp);
+        return -1;
+    }
+
+    return 0;
 }
 
 #ifdef CONFIG_KDB
 
 static char *kdb_mempool_prop(mempool_t *mp)
 {
-	static char mempool[10] = "--- --- -";
-	mempool[0] = (mp->flags & MP_KR) ? 'r' : '-';
-	mempool[1] = (mp->flags & MP_KW) ? 'w' : '-';
-	mempool[2] = (mp->flags & MP_KX) ? 'x' : '-';
-
-	mempool[4] = (mp->flags & MP_UR) ? 'r' : '-';
-	mempool[5] = (mp->flags & MP_UW) ? 'w' : '-';
-	mempool[6] = (mp->flags & MP_UX) ? 'x' : '-';
-
-	mempool[8] = (mp->flags & MP_DEVICES) ?
-	             'D' : (mp->flags & MP_MEMPOOL) ?
-	             'M' : (mp->flags & MP_AHB_RAM) ?
-	             'A' : (mp->flags & MP_SRAM) ?
-	             'S' : 'N';
-	return mempool;
+    static char mempool[10] = "--- --- -";
+    mempool[0] = (mp->flags & MP_KR) ? 'r' : '-';
+    mempool[1] = (mp->flags & MP_KW) ? 'w' : '-';
+    mempool[2] = (mp->flags & MP_KX) ? 'x' : '-';
+
+    mempool[4] = (mp->flags & MP_UR) ? 'r' : '-';
+    mempool[5] = (mp->flags & MP_UW) ? 'w' : '-';
+    mempool[6] = (mp->flags & MP_UX) ? 'x' : '-';
+
+    mempool[8] = (mp->flags & MP_DEVICES)   ? 'D'
+                 : (mp->flags & MP_MEMPOOL) ? 'M'
+                 : (mp->flags & MP_AHB_RAM) ? 'A'
+                 : (mp->flags & MP_SRAM)    ? 'S'
+                                            : 'N';
+    return mempool;
 }
 
 void kdb_dump_mempool(void)
 {
-	dbg_printf(DL_KDB,
-	           "%2s %20s %10s [%8s:%8s] %10s\n",
-	           "ID", "NAME", "SIZE", "START", "END", "FLAGS");
-
-	for (int i = 0; i < sizeof(memmap) / sizeof(mempool_t); ++i) {
-		dbg_printf(DL_KDB,
-		           "%2d %20s %10d [%p:%p] %10s\n",
-		           i,
-		           memmap[i].name, (memmap[i].end - memmap[i].start),
-		           memmap[i].start, memmap[i].end,
-		           kdb_mempool_prop(&(memmap[i])));
-	}
+    dbg_printf(DL_KDB, "%2s %20s %10s [%8s:%8s] %10s\n", "ID", "NAME", "SIZE",
+               "START", "END", "FLAGS");
+
+    for (int i = 0; i < sizeof(memmap) / sizeof(mempool_t); ++i) {
+        dbg_printf(DL_KDB, "%2d %20s %10d [%p:%p] %10s\n", i, memmap[i].name,
+                   (memmap[i].end - memmap[i].start), memmap[i].start,
+                   memmap[i].end, kdb_mempool_prop(&(memmap[i])));
+    }
 }
 
 void kdb_dump_as(void)
 {
-	extern enum {
-		DBG_ASYNC, DBG_PANIC
-	}
-	dbg_state;
-	int idx = 0, nl = 0, i;
-	as_t *as = NULL;
-	fpage_t *fpage = NULL;
-
-	for_each_in_ktable(as, idx, &as_table) {
-		fpage = as->first;
-		dbg_printf(DL_KDB, "Address Space %p\n", as->as_spaceid);
-
-		while (fpage) {
-			fpage->used = 0;
-			fpage = fpage->as_next;
-		}
-
-		i = 0;
-		fpage = as->mpu_stack_first;
-		while (i < 8 && fpage) {
-			fpage->used = 1;
-			fpage = fpage->mpu_next;
-			++i;
-		}
-
-		fpage = as->mpu_first;
-		while (i < 8 && fpage) {
-			fpage->used = 1;
-			fpage = fpage->mpu_next;
-			++i;
-		}
-
-		nl = 0;
-		fpage = as->first;
-		while (fpage) {
-			dbg_printf(DL_KDB,
-			           "MEM: %c fpage %5s [b:%p, sz:2**%d]\n",
-			           fpage->used ? 'o' : ' ',
-			           memmap[fpage->fpage.mpid].name,
-			           fpage->fpage.base, fpage->fpage.shift);
-			fpage = fpage->as_next;
-			++nl;
-
-			if (dbg_state != DBG_PANIC && nl == 12) {
-				dbg_puts("Press any key...\n");
-				while (dbg_getchar() == 0)
-					/* */ ;
-				nl = 0;
-			}
-		}
-	}
+    extern enum { DBG_ASYNC, DBG_PANIC } dbg_state;
+    int idx = 0, nl = 0, i;
+    as_t *as = NULL;
+    fpage_t *fpage = NULL;
+
+    for_each_in_ktable (as, idx, &as_table) {
+        fpage = as->first;
+        dbg_printf(DL_KDB, "Address Space %p\n", as->as_spaceid);
+
+        while (fpage) {
+            fpage->used = 0;
+            fpage = fpage->as_next;
+        }
+
+        i = 0;
+        fpage = as->mpu_stack_first;
+        while (i < 8 && fpage) {
+            fpage->used = 1;
+            fpage = fpage->mpu_next;
+            ++i;
+        }
+
+        fpage = as->mpu_first;
+        while (i < 8 && fpage) {
+            fpage->used = 1;
+            fpage = fpage->mpu_next;
+            ++i;
+        }
+
+        nl = 0;
+        fpage = as->first;
+        while (fpage) {
+            dbg_printf(DL_KDB, "MEM: %c fpage %5s [b:%p, sz:2**%d]\n",
+                       fpage->used ? 'o' : ' ', memmap[fpage->fpage.mpid].name,
+                       fpage->fpage.base, fpage->fpage.shift);
+            fpage = fpage->as_next;
+            ++nl;
+
+            if (dbg_state != DBG_PANIC && nl == 12) {
+                dbg_puts("Press any key...\n");
+                while (dbg_getchar() == 0)
+                    /* */;
+                nl = 0;
+            }
+        }
+    }
 }
 
-#endif	/* CONFIG_KDB */
+#endif /* CONFIG_KDB */
diff --git a/kernel/sampling-kdb.c b/kernel/sampling-kdb.c
index f9d9b7fa..c9563dd5 100644
--- a/kernel/sampling-kdb.c
+++ b/kernel/sampling-kdb.c
@@ -7,76 +7,77 @@
 #error __FILE__ " depends on CONFIG_KPROBES"
 #endif
 
-#include <ksym.h>
-#include <sampling.h>
-#include <types.h>
-#include <thread.h>
 #include <debug.h>
-#include <lib/stdlib.h>
 #include <kprobes.h>
+#include <ksym.h>
+#include <lib/stdlib.h>
 #include <platform/cortex_m.h>
+#include <sampling.h>
+#include <thread.h>
+#include <types.h>
 
 #ifdef CONFIG_KDB
-static int sampling_handler(struct kprobe *kp, uint32_t *stack,
+static int sampling_handler(struct kprobe *kp,
+                            uint32_t *stack,
                             uint32_t *kp_regs)
 {
-	uint32_t *target_stack;
+    uint32_t *target_stack;
 
-	/* examine KTIMER LR */
-	if (stack[REG_LR] & 0x4)
-		target_stack = PSP();
-	else
-		target_stack = stack + 8;
+    /* examine KTIMER LR */
+    if (stack[REG_LR] & 0x4)
+        target_stack = PSP();
+    else
+        target_stack = stack + 8;
 
-	sampled_pcpush((void *) target_stack[REG_PC]);
-	return 0;
+    sampled_pcpush((void *) target_stack[REG_PC]);
+    return 0;
 }
 
 extern void ktimer_handler(void);
 void kdb_show_sampling(void)
 {
-	int *hitcount, *symid_list;
-	static int init = 0;
-	static int init_failed = 0;
-	static struct kprobe k;
+    int *hitcount, *symid_list;
+    static int init = 0;
+    static int init_failed = 0;
+    static struct kprobe k;
 
-	if (init_failed) {
-		dbg_printf(DL_KDB,
-		           "Sampling unavailable (kprobe on Flash requires FPB)\n");
-		return;
-	}
+    if (init_failed) {
+        dbg_printf(DL_KDB,
+                   "Sampling unavailable (kprobe on Flash requires FPB)\n");
+        return;
+    }
 
-	if (init == 0) {
-		sampling_init();
-		sampling_enable();
+    if (init == 0) {
+        sampling_init();
+        sampling_enable();
 
-		k.addr = ktimer_handler;
-		k.pre_handler = sampling_handler;
-		k.post_handler = NULL;
+        k.addr = ktimer_handler;
+        k.pre_handler = sampling_handler;
+        k.post_handler = NULL;
 
-		if (kprobe_register(&k) < 0) {
-			dbg_printf(DL_KDB,
-			           "FAILED: kprobe on Flash requires FPB hardware\n");
-			sampling_disable();
-			init_failed = 1;
-			return;
-		}
+        if (kprobe_register(&k) < 0) {
+            dbg_printf(DL_KDB,
+                       "FAILED: kprobe on Flash requires FPB hardware\n");
+            sampling_disable();
+            init_failed = 1;
+            return;
+        }
 
-		init++;
-		return;
-	}
+        init++;
+        return;
+    }
 
-	sampling_disable();
-	sampling_stats(&hitcount, &symid_list);
+    sampling_disable();
+    sampling_stats(&hitcount, &symid_list);
 
-	for (int i = 0; i < ksym_total(); i++) {
-		int symid = symid_list[i];
-		if (hitcount[symid] == 0)
-			break;
-		dbg_printf(DL_KDB, "%5d [ %24s ]\n", hitcount[symid],
-		           ksym_id2name(symid));
-	}
+    for (int i = 0; i < ksym_total(); i++) {
+        int symid = symid_list[i];
+        if (hitcount[symid] == 0)
+            break;
+        dbg_printf(DL_KDB, "%5d [ %24s ]\n", hitcount[symid],
+                   ksym_id2name(symid));
+    }
 
-	sampling_enable();
+    sampling_enable();
 }
 #endif /* CONFIG_KDB */
diff --git a/kernel/sampling.c b/kernel/sampling.c
index 176d4ae5..d238fb0d 100644
--- a/kernel/sampling.c
+++ b/kernel/sampling.c
@@ -3,10 +3,10 @@
  * found in the LICENSE file.
  */
 
-#include <ksym.h>
-#include <sampling.h>
 #include <debug.h>
+#include <ksym.h>
 #include <lib/stdlib.h>
+#include <sampling.h>
 
 static void *sampled_pc[MAX_SAMPLING_COUNT];
 static int sampled_count;
@@ -17,71 +17,71 @@ static int ksymid_sortedlist[MAX_KSYM];
 
 void sampling_enable()
 {
-	__sampling_enabled = 1;
+    __sampling_enabled = 1;
 }
 
 void sampling_disable()
 {
-	__sampling_enabled = 0;
+    __sampling_enabled = 0;
 }
 
 void sampling_init()
 {
-	if (ksym_total() > MAX_KSYM) {
-		dbg_printf(DL_KDB, "ksym %d > MAX_KSYM\n", ksym_total());
-		return;
-	}
-	for (int i = 0; i < MAX_SAMPLING_COUNT; i++) {
-		sampled_pc[i] = 0;
-	}
-	sampled_count = 0;
+    if (ksym_total() > MAX_KSYM) {
+        dbg_printf(DL_KDB, "ksym %d > MAX_KSYM\n", ksym_total());
+        return;
+    }
+    for (int i = 0; i < MAX_SAMPLING_COUNT; i++) {
+        sampled_pc[i] = 0;
+    }
+    sampled_count = 0;
 }
 
 void sampled_pcpush(void *pc)
 {
-	if (__sampling_enabled == 0)
-		return;
+    if (__sampling_enabled == 0)
+        return;
 
-	if (sampled_count == MAX_SAMPLING_COUNT)
-		sampled_count = 0;
-	sampled_pc[sampled_count++] = pc;
+    if (sampled_count == MAX_SAMPLING_COUNT)
+        sampled_count = 0;
+    sampled_pc[sampled_count++] = pc;
 }
 
 static int cmp_addr(const void *p1, const void *p2)
 {
-	return *(int *) p1 - *(int *) p2;
+    return *(int *) p1 - *(int *) p2;
 }
 
 static int cmp_symhit(const void *p1, const void *p2)
 {
-	int *symid1 = (int *) p1;
-	int *symid2 = (int *) p2;
-	return ksym_hitcount[*symid2] - ksym_hitcount[*symid1];
+    int *symid1 = (int *) p1;
+    int *symid2 = (int *) p2;
+    return ksym_hitcount[*symid2] - ksym_hitcount[*symid1];
 }
 
 void sampling_stats(int **hitcountp, int **symid_list)
 {
-	/* init data */
-	sort(sampled_pc, MAX_SAMPLING_COUNT, sizeof(sampled_pc[0]), cmp_addr);
+    /* init data */
+    sort(sampled_pc, MAX_SAMPLING_COUNT, sizeof(sampled_pc[0]), cmp_addr);
 
-	for (int i = 0; i < MAX_KSYM; i++) {
-		ksym_hitcount[i] = 0;
-		ksymid_sortedlist[i] = i;
-	}
+    for (int i = 0; i < MAX_KSYM; i++) {
+        ksym_hitcount[i] = 0;
+        ksymid_sortedlist[i] = i;
+    }
 
-	/* calculation total hit for each ksym */
-	for (int i = 0; i < MAX_SAMPLING_COUNT; i++) {
-		int symid = ksym_lookup(sampled_pc[i]);
-		if (symid < 0)
-			continue;
-		ksym_hitcount[symid]++;
-	}
+    /* calculation total hit for each ksym */
+    for (int i = 0; i < MAX_SAMPLING_COUNT; i++) {
+        int symid = ksym_lookup(sampled_pc[i]);
+        if (symid < 0)
+            continue;
+        ksym_hitcount[symid]++;
+    }
 
-	/* create a list from highest hit to lowest hit */
-	sort(ksymid_sortedlist, ksym_total(),
-	     sizeof(ksymid_sortedlist[0]), cmp_symhit);
+    /* create a list from highest hit to lowest hit */
+    sort(ksymid_sortedlist, ksym_total(), sizeof(ksymid_sortedlist[0]),
+         cmp_symhit);
 
-	/* output the result */
-	*hitcountp = ksym_hitcount;
-	*symid_list = ksymid_sortedlist;
+    /* output the result */
+    *hitcountp = ksym_hitcount;
+    *symid_list = ksymid_sortedlist;
 }
diff --git a/kernel/sched.c b/kernel/sched.c
index 0d5830cb..8754a25c 100644
--- a/kernel/sched.c
+++ b/kernel/sched.c
@@ -3,12 +3,12 @@
  * found in the LICENSE file.
  */
 
-#include <sched.h>
-#include <thread.h>
+#include <debug.h>
 #include <error.h>
 #include <init_hook.h>
 #include <platform/irq.h>
-#include <debug.h>
+#include <sched.h>
+#include <thread.h>
 
 /**
  * @file sched.c
@@ -25,7 +25,8 @@
  *   - Conditional rotation: only rotate on timeslice expiry (yield)
  *
  * Data structures:
- *   - ready_bitmap: One bit per priority level (bit 31 = prio 0, bit 0 = prio 31)
+ *   - ready_bitmap: One bit per priority level (bit 31 = prio 0, bit 0 = prio
+ * 31)
  *   - ready_queue[]: Circular doubly-linked list per priority level
  */
 
@@ -44,9 +45,9 @@ static tcb_t *ready_queue[SCHED_PRIORITY_LEVELS];
  */
 static inline uint32_t clz32(uint32_t x)
 {
-	uint32_t result;
-	__asm__ __volatile__ ("clz %0, %1" : "=r"(result) : "r"(x));
-	return result;
+    uint32_t result;
+    __asm__ __volatile__("clz %0, %1" : "=r"(result) : "r"(x));
+    return result;
 }
 
 /**
@@ -54,10 +55,10 @@ static inline uint32_t clz32(uint32_t x)
  */
 void sched_init(void)
 {
-	ready_bitmap = 0;
+    ready_bitmap = 0;
 
-	for (int i = 0; i < SCHED_PRIORITY_LEVELS; ++i)
-		ready_queue[i] = NULL;
+    for (int i = 0; i < SCHED_PRIORITY_LEVELS; ++i)
+        ready_queue[i] = NULL;
 }
 
 INIT_HOOK(sched_init, INIT_LEVEL_KERNEL_EARLY);
@@ -68,7 +69,7 @@ INIT_HOOK(sched_init, INIT_LEVEL_KERNEL_EARLY);
  */
 int sched_is_queued(tcb_t *thread)
 {
-	return thread->sched_link.prev != (void *)0;
+    return thread->sched_link.prev != (void *) 0;
 }
 
 /**
@@ -77,8 +78,8 @@ int sched_is_queued(tcb_t *thread)
  */
 static inline void sched_link_init(tcb_t *thread)
 {
-	thread->sched_link.prev = NULL;
-	thread->sched_link.next = NULL;
+    thread->sched_link.prev = NULL;
+    thread->sched_link.next = NULL;
 }
 
 /**
@@ -90,56 +91,56 @@ static inline void sched_link_init(tcb_t *thread)
  */
 void sched_enqueue(tcb_t *thread)
 {
-	uint8_t prio;
-	tcb_t *head;
-	uint32_t flags;
-
-	if (!thread)
-		return;
-
-	flags = irq_save_flags();
-
-	/* Strict invariant: only runnable threads in ready queues
-	 * Check inside critical section to prevent race with state changes
-	 */
-	if (thread->state != T_RUNNABLE) {
-		irq_restore_flags(flags);
-		panic("SCHED: Enqueueing non-runnable thread %t (state %d)\n",
-		      thread->t_globalid, thread->state);
-	}
-
-	/* Don't double-enqueue */
-	if (sched_is_queued(thread)) {
-		irq_restore_flags(flags);
-		return;
-	}
-
-	prio = thread->priority;
-	if (prio >= SCHED_PRIORITY_LEVELS)
-		prio = SCHED_PRIO_IDLE;
-
-	head = ready_queue[prio];
-
-	if (!head) {
-		/* Empty queue: thread becomes sole element */
-		ready_queue[prio] = thread;
-		thread->sched_link.prev = thread;
-		thread->sched_link.next = thread;
-
-		/* Optimization: Only set bitmap when queue was empty */
-		ready_bitmap |= (1UL << (31 - prio));
-	} else {
-		/* Insert at tail (before head in circular list) */
-		tcb_t *tail = head->sched_link.prev;
-
-		thread->sched_link.next = head;
-		thread->sched_link.prev = tail;
-		tail->sched_link.next = thread;
-		head->sched_link.prev = thread;
-		/* Bitmap already set - no update needed */
-	}
-
-	irq_restore_flags(flags);
+    uint8_t prio;
+    tcb_t *head;
+    uint32_t flags;
+
+    if (!thread)
+        return;
+
+    flags = irq_save_flags();
+
+    /* Strict invariant: only runnable threads in ready queues
+     * Check inside critical section to prevent race with state changes
+     */
+    if (thread->state != T_RUNNABLE) {
+        irq_restore_flags(flags);
+        panic("SCHED: Enqueueing non-runnable thread %t (state %d)\n",
+              thread->t_globalid, thread->state);
+    }
+
+    /* Don't double-enqueue */
+    if (sched_is_queued(thread)) {
+        irq_restore_flags(flags);
+        return;
+    }
+
+    prio = thread->priority;
+    if (prio >= SCHED_PRIORITY_LEVELS)
+        prio = SCHED_PRIO_IDLE;
+
+    head = ready_queue[prio];
+
+    if (!head) {
+        /* Empty queue: thread becomes sole element */
+        ready_queue[prio] = thread;
+        thread->sched_link.prev = thread;
+        thread->sched_link.next = thread;
+
+        /* Optimization: Only set bitmap when queue was empty */
+        ready_bitmap |= (1UL << (31 - prio));
+    } else {
+        /* Insert at tail (before head in circular list) */
+        tcb_t *tail = head->sched_link.prev;
+
+        thread->sched_link.next = head;
+        thread->sched_link.prev = tail;
+        tail->sched_link.next = thread;
+        head->sched_link.prev = thread;
+        /* Bitmap already set - no update needed */
+    }
+
+    irq_restore_flags(flags);
 }
 
 /**
@@ -149,47 +150,47 @@ void sched_enqueue(tcb_t *thread)
  */
 void sched_dequeue(tcb_t *thread)
 {
-	uint8_t prio;
-	tcb_t *prev, *next;
-	uint32_t flags;
-
-	if (!thread)
-		return;
-
-	flags = irq_save_flags();
-
-	/* Not in queue */
-	if (!sched_is_queued(thread)) {
-		irq_restore_flags(flags);
-		return;
-	}
-
-	prio = thread->priority;
-	if (prio >= SCHED_PRIORITY_LEVELS)
-		prio = SCHED_PRIO_IDLE;
-
-	prev = thread->sched_link.prev;
-	next = thread->sched_link.next;
-
-	if (thread == next) {
-		/* Only element in queue */
-		ready_queue[prio] = NULL;
-		ready_bitmap &= ~(1UL << (31 - prio));
-	} else {
-		/* Unlink from list */
-		prev->sched_link.next = next;
-		next->sched_link.prev = prev;
-
-		/* Update head if we removed it */
-		if (ready_queue[prio] == thread)
-			ready_queue[prio] = next;
-		/* Bitmap stays set - queue still has threads */
-	}
-
-	/* Mark as not queued */
-	sched_link_init(thread);
-
-	irq_restore_flags(flags);
+    uint8_t prio;
+    tcb_t *prev, *next;
+    uint32_t flags;
+
+    if (!thread)
+        return;
+
+    flags = irq_save_flags();
+
+    /* Not in queue */
+    if (!sched_is_queued(thread)) {
+        irq_restore_flags(flags);
+        return;
+    }
+
+    prio = thread->priority;
+    if (prio >= SCHED_PRIORITY_LEVELS)
+        prio = SCHED_PRIO_IDLE;
+
+    prev = thread->sched_link.prev;
+    next = thread->sched_link.next;
+
+    if (thread == next) {
+        /* Only element in queue */
+        ready_queue[prio] = NULL;
+        ready_bitmap &= ~(1UL << (31 - prio));
+    } else {
+        /* Unlink from list */
+        prev->sched_link.next = next;
+        next->sched_link.prev = prev;
+
+        /* Update head if we removed it */
+        if (ready_queue[prio] == thread)
+            ready_queue[prio] = next;
+        /* Bitmap stays set - queue still has threads */
+    }
+
+    /* Mark as not queued */
+    sched_link_init(thread);
+
+    irq_restore_flags(flags);
 }
 
 /**
@@ -199,45 +200,45 @@ void sched_dequeue(tcb_t *thread)
  */
 void sched_yield(void)
 {
-	tcb_t *curr = thread_current();
-	uint8_t prio;
-	tcb_t *head;
-	uint32_t flags;
-
-	if (!curr)
-		return;
-
-	flags = irq_save_flags();
-
-	if (!sched_is_queued(curr)) {
-		irq_restore_flags(flags);
-		return;
-	}
-
-	prio = curr->priority;
-	if (prio >= SCHED_PRIORITY_LEVELS)
-		prio = SCHED_PRIO_IDLE;
-
-	head = ready_queue[prio];
-
-	/* Only rotate if more than one thread at this priority */
-	if (head && head->sched_link.next != head) {
-		/* Invariant: running thread must be queue head for fair rotation.
-		 * If curr != head, priority was changed while running - still safe
-		 * because we rotate whatever is at head, maintaining FIFO order.
-		 */
-		if (head != curr) {
-			/* Current thread not at head - it was re-prioritized.
-			 * Still rotate head for other waiters at this priority.
-			 */
-			dbg_printf(DL_SCHEDULE,
-				   "SCHED: yield curr %t != head %t at prio %d\n",
-				   curr->t_globalid, head->t_globalid, prio);
-		}
-		ready_queue[prio] = head->sched_link.next;
-	}
-
-	irq_restore_flags(flags);
+    tcb_t *curr = thread_current();
+    uint8_t prio;
+    tcb_t *head;
+    uint32_t flags;
+
+    if (!curr)
+        return;
+
+    flags = irq_save_flags();
+
+    if (!sched_is_queued(curr)) {
+        irq_restore_flags(flags);
+        return;
+    }
+
+    prio = curr->priority;
+    if (prio >= SCHED_PRIORITY_LEVELS)
+        prio = SCHED_PRIO_IDLE;
+
+    head = ready_queue[prio];
+
+    /* Only rotate if more than one thread at this priority */
+    if (head && head->sched_link.next != head) {
+        /* Invariant: running thread must be queue head for fair rotation.
+         * If curr != head, priority was changed while running - still safe
+         * because we rotate whatever is at head, maintaining FIFO order.
+         */
+        if (head != curr) {
+            /* Current thread not at head - it was re-prioritized.
+             * Still rotate head for other waiters at this priority.
+             */
+            dbg_printf(DL_SCHEDULE,
+                       "SCHED: yield curr %t != head %t at prio %d\n",
+                       curr->t_globalid, head->t_globalid, prio);
+        }
+        ready_queue[prio] = head->sched_link.next;
+    }
+
+    irq_restore_flags(flags);
 }
 
 /**
@@ -251,33 +252,33 @@ void sched_yield(void)
  */
 tcb_t *schedule_select(void)
 {
-	uint32_t prio;
-	tcb_t *thread;
-	uint32_t flags;
+    uint32_t prio;
+    tcb_t *thread;
+    uint32_t flags;
 
-	flags = irq_save_flags();
+    flags = irq_save_flags();
 
-	/* CLZ returns 32 if bitmap is 0 (no branches needed) */
-	prio = clz32(ready_bitmap);
+    /* CLZ returns 32 if bitmap is 0 (no branches needed) */
+    prio = clz32(ready_bitmap);
 
-	if (prio < SCHED_PRIORITY_LEVELS) {
-		thread = ready_queue[prio];
+    if (prio < SCHED_PRIORITY_LEVELS) {
+        thread = ready_queue[prio];
 
-		/* Safety check for consistency */
-		if (!thread) {
-			irq_restore_flags(flags);
-			panic("SCHED: Inconsistent bitmap/queue at prio %d\n", prio);
-		}
+        /* Safety check for consistency */
+        if (!thread) {
+            irq_restore_flags(flags);
+            panic("SCHED: Inconsistent bitmap/queue at prio %d\n", prio);
+        }
 
-		irq_restore_flags(flags);
-		/* Strict invariant: queued threads are always runnable */
-		return thread;
-	}
+        irq_restore_flags(flags);
+        /* Strict invariant: queued threads are always runnable */
+        return thread;
+    }
 
-	irq_restore_flags(flags);
-	/* Not reached: idle thread should always be runnable */
-	panic("Reached end of schedule_select()\n");
-	return NULL;
+    irq_restore_flags(flags);
+    /* Not reached: idle thread should always be runnable */
+    panic("Reached end of schedule_select()\n");
+    return NULL;
 }
 
 /**
@@ -290,36 +291,36 @@ tcb_t *schedule_select(void)
  */
 void sched_set_priority(tcb_t *thread, uint8_t new_prio)
 {
-	uint32_t flags;
-	int was_queued;
+    uint32_t flags;
+    int was_queued;
 
-	if (!thread)
-		return;
+    if (!thread)
+        return;
 
-	if (new_prio >= SCHED_PRIORITY_LEVELS)
-		new_prio = SCHED_PRIO_IDLE;
+    if (new_prio >= SCHED_PRIORITY_LEVELS)
+        new_prio = SCHED_PRIO_IDLE;
 
-	flags = irq_save_flags();
+    flags = irq_save_flags();
 
-	/* Check if priority actually changes */
-	if (thread->priority == new_prio) {
-		irq_restore_flags(flags);
-		return;
-	}
+    /* Check if priority actually changes */
+    if (thread->priority == new_prio) {
+        irq_restore_flags(flags);
+        return;
+    }
 
-	/* Remove from old queue if queued */
-	was_queued = sched_is_queued(thread);
-	if (was_queued)
-		sched_dequeue(thread);
+    /* Remove from old queue if queued */
+    was_queued = sched_is_queued(thread);
+    if (was_queued)
+        sched_dequeue(thread);
 
-	/* Update priority */
-	thread->priority = new_prio;
+    /* Update priority */
+    thread->priority = new_prio;
 
-	/* Re-add to new queue if was queued */
-	if (was_queued)
-		sched_enqueue(thread);
+    /* Re-add to new queue if was queued */
+    if (was_queued)
+        sched_enqueue(thread);
 
-	irq_restore_flags(flags);
+    irq_restore_flags(flags);
 }
 
 /**
@@ -328,7 +329,7 @@ void sched_set_priority(tcb_t *thread, uint8_t new_prio)
  */
 int schedule(void)
 {
-	tcb_t *scheduled = schedule_select();
-	thread_switch(scheduled);
-	return 1;
+    tcb_t *scheduled = schedule_select();
+    thread_switch(scheduled);
+    return 1;
 }
diff --git a/kernel/softirq.c b/kernel/softirq.c
index b6773c85..29ee0033 100644
--- a/kernel/softirq.c
+++ b/kernel/softirq.c
@@ -3,77 +3,75 @@
  * found in the LICENSE file.
  */
 
-#include <types.h>
-#include <platform/irq.h>
+#include <debug.h>
 #include <platform/bitops.h>
+#include <platform/irq.h>
 #include <softirq.h>
-#include <debug.h>
 #include <systhread.h>
+#include <types.h>
 
 static softirq_t softirq[NR_SOFTIRQ];
 
 void softirq_register(softirq_type_t type, softirq_handler_t handler)
 {
-	softirq[type].handler = handler;
-	softirq[type].schedule = 0;
+    softirq[type].handler = handler;
+    softirq[type].schedule = 0;
 }
 
 void softirq_schedule(softirq_type_t type)
 {
-	atomic_set(&(softirq[type].schedule), 1);
-	set_kernel_state(T_RUNNABLE);
+    atomic_set(&(softirq[type].schedule), 1);
+    set_kernel_state(T_RUNNABLE);
 }
 
 static char *softirq_names[NR_SOFTIRQ] __attribute__((used)) = {
-	"Kernel timer events",
-	"Asynchronous events",
-	"System calls",
+    "Kernel timer events",
+    "Asynchronous events",
+    "System calls",
 #ifdef CONFIG_KDB
-	"KDB enters",
+    "KDB enters",
 #endif
 };
 
 int softirq_execute()
 {
-	uint32_t softirq_schedule = 0, executed = 0;
+    uint32_t softirq_schedule = 0, executed = 0;
 retry:
-	for (int i = 0; i < NR_SOFTIRQ; ++i) {
-		if (atomic_get(&(softirq[i].schedule)) != 0 &&
-		    softirq[i].handler) {
-			softirq[i].handler();
+    for (int i = 0; i < NR_SOFTIRQ; ++i) {
+        if (atomic_get(&(softirq[i].schedule)) != 0 && softirq[i].handler) {
+            softirq[i].handler();
 
-			executed = 1;
-			atomic_set(&(softirq[i].schedule), 0);
+            executed = 1;
+            atomic_set(&(softirq[i].schedule), 0);
 
-			dbg_printf(DL_SOFTIRQ,
-			           "SOFTIRQ: executing %s\n", softirq_names[i]);
-		}
-	}
+            dbg_printf(DL_SOFTIRQ, "SOFTIRQ: executing %s\n", softirq_names[i]);
+        }
+    }
 
-	/* Must ensure that no interrupt reschedule its softirq */
-	irq_disable();
+    /* Must ensure that no interrupt reschedule its softirq */
+    irq_disable();
 
-	softirq_schedule = 0;
-	for (int i = 0; i < NR_SOFTIRQ; ++i) {
-		softirq_schedule |= softirq[i].schedule;
-	}
+    softirq_schedule = 0;
+    for (int i = 0; i < NR_SOFTIRQ; ++i) {
+        softirq_schedule |= softirq[i].schedule;
+    }
 
-	set_kernel_state((softirq_schedule) ? T_RUNNABLE : T_INACTIVE);
-	irq_enable();
+    set_kernel_state((softirq_schedule) ? T_RUNNABLE : T_INACTIVE);
+    irq_enable();
 
-	if (softirq_schedule)
-		goto retry;
+    if (softirq_schedule)
+        goto retry;
 
-	return executed;
+    return executed;
 }
 
 #ifdef CONFIG_KDB
 void kdb_dump_softirq(void)
 {
-	for (int i = 0; i < NR_SOFTIRQ; ++i) {
-		dbg_printf(DL_KDB, "%32s %s\n", softirq_names[i],
-		           atomic_get(&(softirq[i].schedule)) ?
-		           "scheduled" : "not scheduled");
-	}
+    for (int i = 0; i < NR_SOFTIRQ; ++i) {
+        dbg_printf(
+            DL_KDB, "%32s %s\n", softirq_names[i],
+            atomic_get(&(softirq[i].schedule)) ? "scheduled" : "not scheduled");
+    }
 }
 #endif
diff --git a/kernel/start.c b/kernel/start.c
index 48819ed6..5fdad2a5 100644
--- a/kernel/start.c
+++ b/kernel/start.c
@@ -10,95 +10,97 @@
 #include INC_PLAT(gpio.h)
 #include INC_PLAT(rcc.h)
 
-#include <platform/debug_device.h>
-#include <platform/irq.h>
-#include <error.h>
-#include <types.h>
 #include <debug.h>
-#include <kdb.h>
+#include <error.h>
+#include <init_hook.h>
 #include <ipc.h>
-#include <ktimer.h>
-#include <softirq.h>
-#include <syscall.h>
-#include <systhread.h>
+#include <kdb.h>
 #include <kprobes.h>
 #include <ksym.h>
-#include <init_hook.h>
+#include <ktimer.h>
 #include <lib/stdio.h>
 #include <lib/string.h>
+#include <platform/debug_device.h>
+#include <platform/irq.h>
+#include <softirq.h>
+#include <syscall.h>
+#include <systhread.h>
+#include <types.h>
 
 static char banner[] =
-	"\n"
-	"====================================================\n"
-	" Copyright(C) 2013-2014 The F9 Microkernel Project  \n"
-	"====================================================\n"
-	"Git head: " GIT_HEAD "\n"
-	"Host: " MACH_TYPE "\n"
-	"Build: "  BUILD_TIME "\n"
-	"\n";
+    "\n"
+    "====================================================\n"
+    " Copyright(C) 2013-2014 The F9 Microkernel Project  \n"
+    "====================================================\n"
+    "Git head: " GIT_HEAD
+    "\n"
+    "Host: " MACH_TYPE
+    "\n"
+    "Build: " BUILD_TIME
+    "\n"
+    "\n";
 
 int main(void)
 {
-	run_init_hook(INIT_LEVEL_PLATFORM_EARLY);
-	irq_init();
-	irq_disable();
+    run_init_hook(INIT_LEVEL_PLATFORM_EARLY);
+    irq_init();
+    irq_disable();
 
 #ifdef CONFIG_FPU
-	*SCB_CPACR |= (SCB_CPACR_CP10_FULL | SCB_CPACR_CP11_FULL);
+    *SCB_CPACR |= (SCB_CPACR_CP10_FULL | SCB_CPACR_CP11_FULL);
 #endif
 
-	run_init_hook(INIT_LEVEL_PLATFORM);
+    run_init_hook(INIT_LEVEL_PLATFORM);
 
-	__l4_printf("%s", banner);
+    __l4_printf("%s", banner);
 
-	run_init_hook(INIT_LEVEL_KERNEL_EARLY);
+    run_init_hook(INIT_LEVEL_KERNEL_EARLY);
 
-	run_init_hook(INIT_LEVEL_KERNEL);
+    run_init_hook(INIT_LEVEL_KERNEL);
 
-	/* Not creating kernel thread here because it corrupts current stack
-	 */
-	create_idle_thread();
-	create_root_thread();
+    /* Not creating kernel thread here because it corrupts current stack
+     */
+    create_idle_thread();
+    create_root_thread();
 
-	ktimer_event_create(64, ipc_deliver, NULL);
+    ktimer_event_create(64, ipc_deliver, NULL);
 
-	mpu_enable(MPU_ENABLED);
+    mpu_enable(MPU_ENABLED);
 
-	run_init_hook(INIT_LEVEL_LAST);
+    run_init_hook(INIT_LEVEL_LAST);
 
-	switch_to_kernel();
+    switch_to_kernel();
 
-	/* Not reached */
-	return 0;
+    /* Not reached */
+    return 0;
 }
 
 void __l4_start(void)
 {
-	run_init_hook(INIT_LEVEL_EARLIEST);
+    run_init_hook(INIT_LEVEL_EARLIEST);
 
 #ifndef CONFIG_LOADER
-	/* Copy data segments */
-	memcpy(&kernel_data_start, &kernel_text_end,
-	       (&kernel_data_end - &kernel_data_start) * sizeof(uint32_t));
-	/* DATA (ROM) -> DATA (RAM) */
-	memcpy(&user_text_start, &user_text_flash_start,
-	       (&user_text_end - &user_text_start) * sizeof(uint32_t));
-	/* USER TEXT (ROM) -> USER TEXT (RAM) */
-	memcpy(&user_data_start, &user_text_flash_end,
-	       (&user_data_end - &user_data_start) * sizeof(uint32_t));
-	/* USER DATA (ROM) -> USER DATA (RAM) */
+    /* Copy data segments */
+    memcpy(&kernel_data_start, &kernel_text_end,
+           (&kernel_data_end - &kernel_data_start) * sizeof(uint32_t));
+    /* DATA (ROM) -> DATA (RAM) */
+    memcpy(&user_text_start, &user_text_flash_start,
+           (&user_text_end - &user_text_start) * sizeof(uint32_t));
+    /* USER TEXT (ROM) -> USER TEXT (RAM) */
+    memcpy(&user_data_start, &user_text_flash_end,
+           (&user_data_end - &user_data_start) * sizeof(uint32_t));
+    /* USER DATA (ROM) -> USER DATA (RAM) */
 #endif
 
-	/* Fill bss with zeroes */
-	memset(&bss_start, 0,
-	       (&bss_end - &bss_start) * sizeof(uint32_t));
-	memset(&kernel_ahb_start, 0,
-	       (&kernel_ahb_end - &kernel_ahb_start) * sizeof(uint32_t));
-	memset(&user_bss_start, 0,
-	       (&user_bss_end - &user_bss_start) * sizeof(uint32_t));
+    /* Fill bss with zeroes */
+    memset(&bss_start, 0, (&bss_end - &bss_start) * sizeof(uint32_t));
+    memset(&kernel_ahb_start, 0,
+           (&kernel_ahb_end - &kernel_ahb_start) * sizeof(uint32_t));
+    memset(&user_bss_start, 0,
+           (&user_bss_end - &user_bss_start) * sizeof(uint32_t));
 
-	sys_clock_init();
+    sys_clock_init();
 
-	/* entry point */
-	main();
+    /* entry point */
+    main();
 }
diff --git a/kernel/syscall.c b/kernel/syscall.c
index b99c6e1f..3cfe8724 100644
--- a/kernel/syscall.c
+++ b/kernel/syscall.c
@@ -3,116 +3,115 @@
  * found in the LICENSE file.
  */
 
-#include <syscall.h>
-#include <softirq.h>
-#include <thread.h>
-#include <sched.h>
 #include <debug.h>
+#include <init_hook.h>
 #include <ipc.h>
 #include <l4/utcb.h>
 #include <memory.h>
 #include <platform/armv7m.h>
 #include <platform/irq.h>
-#include <init_hook.h>
+#include <sched.h>
+#include <softirq.h>
+#include <syscall.h>
+#include <thread.h>
 
 tcb_t *caller;
 
 void __svc_handler(void)
 {
-	extern tcb_t *kernel;
+    extern tcb_t *kernel;
 
-	/* Kernel requests context switch, satisfy it */
-	if (thread_current() == kernel)
-		return;
+    /* Kernel requests context switch, satisfy it */
+    if (thread_current() == kernel)
+        return;
 
-	caller = thread_current();
+    caller = thread_current();
 
-	/* Dequeue before blocking (strict queue invariant) */
-	sched_dequeue(caller);
-	caller->state = T_SVC_BLOCKED;
+    /* Dequeue before blocking (strict queue invariant) */
+    sched_dequeue(caller);
+    caller->state = T_SVC_BLOCKED;
 
-	softirq_schedule(SYSCALL_SOFTIRQ);
+    softirq_schedule(SYSCALL_SOFTIRQ);
 }
 
 IRQ_HANDLER(svc_handler, __svc_handler);
 
 void syscall_init()
 {
-	softirq_register(SYSCALL_SOFTIRQ, syscall_handler);
+    softirq_register(SYSCALL_SOFTIRQ, syscall_handler);
 }
 
 INIT_HOOK(syscall_init, INIT_LEVEL_KERNEL);
 
 static void sys_thread_control(uint32_t *param1, uint32_t *param2)
 {
-	l4_thread_t dest = param1[REG_R0];
-	l4_thread_t space = param1[REG_R1];
-	l4_thread_t pager = param1[REG_R3];
-
-	if (space != L4_NILTHREAD) {
-		/* Creation of thread */
-		void *utcb = (void *) param2[0];	/* R4 */
-		mempool_t *utcb_pool = mempool_getbyid(mempool_search((memptr_t) utcb,
-		                                       UTCB_SIZE));
-
-		if (!utcb_pool || !(utcb_pool->flags & (MP_UR | MP_UW))) {
-			/* Incorrect UTCB relocation */
-			param1[REG_R0] = 0;
-			return;
-		}
-
-		/* Reject unaligned UTCB addresses to prevent over-mapping */
-		if (!addr_is_fpage_aligned((memptr_t) utcb)) {
-			/* UTCB must be aligned to fpage boundary */
-			param1[REG_R0] = 0;
-			return;
-		}
-
-		tcb_t *thr = thread_create(dest, utcb);
-		if (!thr) {
-			/* Thread creation failed */
-			param1[REG_R0] = 0;
-			return;
-		}
-		thread_space(thr, space, utcb);
-		thr->utcb->t_pager = pager;
-		param1[REG_R0] = 1;
-	} else {
-		/* Removal of thread */
-		tcb_t *thr = thread_by_globalid(dest);
-		if (!thr) {
-			/* Thread not found */
-			param1[REG_R0] = 0;
-			return;
-		}
-		/* thread_destroy() handles AS refcount via as_put() */
-		thread_destroy(thr);
-		param1[REG_R0] = 1;
-	}
+    l4_thread_t dest = param1[REG_R0];
+    l4_thread_t space = param1[REG_R1];
+    l4_thread_t pager = param1[REG_R3];
+
+    if (space != L4_NILTHREAD) {
+        /* Creation of thread */
+        void *utcb = (void *) param2[0]; /* R4 */
+        mempool_t *utcb_pool =
+            mempool_getbyid(mempool_search((memptr_t) utcb, UTCB_SIZE));
+
+        if (!utcb_pool || !(utcb_pool->flags & (MP_UR | MP_UW))) {
+            /* Incorrect UTCB relocation */
+            param1[REG_R0] = 0;
+            return;
+        }
+
+        /* Reject unaligned UTCB addresses to prevent over-mapping */
+        if (!addr_is_fpage_aligned((memptr_t) utcb)) {
+            /* UTCB must be aligned to fpage boundary */
+            param1[REG_R0] = 0;
+            return;
+        }
+
+        tcb_t *thr = thread_create(dest, utcb);
+        if (!thr) {
+            /* Thread creation failed */
+            param1[REG_R0] = 0;
+            return;
+        }
+        thread_space(thr, space, utcb);
+        thr->utcb->t_pager = pager;
+        param1[REG_R0] = 1;
+    } else {
+        /* Removal of thread */
+        tcb_t *thr = thread_by_globalid(dest);
+        if (!thr) {
+            /* Thread not found */
+            param1[REG_R0] = 0;
+            return;
+        }
+        /* thread_destroy() handles AS refcount via as_put() */
+        thread_destroy(thr);
+        param1[REG_R0] = 1;
+    }
 }
 
 void syscall_handler()
 {
-	uint32_t *svc_param1 = (uint32_t *) caller->ctx.sp;
-	uint32_t svc_num = ((char *) svc_param1[REG_PC])[-2];
-	uint32_t *svc_param2 = caller->ctx.regs;
-
-	if (svc_num == SYS_THREAD_CONTROL) {
-		/* Simply call thread_create
-		 * TODO: checking globalid
-		 * TODO: pagers and schedulers
-		 */
-		sys_thread_control(svc_param1, svc_param2);
-		caller->state = T_RUNNABLE;
-		sched_enqueue(caller);
-	} else if (svc_num == SYS_IPC) {
-		sys_ipc(svc_param1);
-	} else {
-		dbg_printf(DL_SYSCALL,
-		           "SVC: %d called [%d, %d, %d, %d]\n", svc_num,
-		           svc_param1[REG_R0], svc_param1[REG_R1],
-		           svc_param1[REG_R2], svc_param1[REG_R3]);
-		caller->state = T_RUNNABLE;
-		sched_enqueue(caller);
-	}
+    uint32_t *svc_param1 = (uint32_t *) caller->ctx.sp;
+    uint32_t svc_num = ((char *) svc_param1[REG_PC])[-2];
+    uint32_t *svc_param2 = caller->ctx.regs;
+
+    if (svc_num == SYS_THREAD_CONTROL) {
+        /* Simply call thread_create
+         * TODO: checking globalid
+         * TODO: pagers and schedulers
+         */
+        sys_thread_control(svc_param1, svc_param2);
+        caller->state = T_RUNNABLE;
+        sched_enqueue(caller);
+    } else if (svc_num == SYS_IPC) {
+        sys_ipc(svc_param1);
+    } else {
+        dbg_printf(DL_SYSCALL, "SVC: %d called [%d, %d, %d, %d]\n", svc_num,
+                   svc_param1[REG_R0], svc_param1[REG_R1], svc_param1[REG_R2],
+                   svc_param1[REG_R3]);
+        caller->state = T_RUNNABLE;
+        sched_enqueue(caller);
+    }
 }
diff --git a/kernel/systhread.c b/kernel/systhread.c
index 4460fb6a..09029ba0 100644
--- a/kernel/systhread.c
+++ b/kernel/systhread.c
@@ -3,11 +3,11 @@
  * found in the LICENSE file.
  */
 
+#include <ktimer.h>
 #include <platform/irq.h>
+#include <sched.h>
 #include <softirq.h>
 #include <thread.h>
-#include <sched.h>
-#include <ktimer.h>
 
 /*
  * @file systhread.c
@@ -26,107 +26,107 @@ static void idle_thread(void);
 
 void create_root_thread(void)
 {
-	root = thread_init(TID_TO_GLOBALID(THREAD_ROOT), &root_utcb);
-	thread_space(root, TID_TO_GLOBALID(THREAD_ROOT), &root_utcb);
-	as_map_user(root->as);
-
-	uint32_t regs[4] = {
-		[REG_R0] = (uint32_t) &kip,
-		[REG_R1] = (uint32_t) root->utcb,
-		[REG_R2] = 0,
-		[REG_R3] = 0,
-	};
-
-	thread_init_ctx((void *) &root_stack_end, root_thread, regs, root);
-
-	root->stack_base = (memptr_t) &root_stack_start;
-	root->stack_size = (uint32_t) &root_stack_end -
-	                   (uint32_t) &root_stack_start;
-	thread_init_canary(root);
-
-	root->priority = SCHED_PRIO_ROOT;
-	root->base_priority = SCHED_PRIO_ROOT;
-	root->state = T_RUNNABLE;
-	sched_enqueue(root);
+    root = thread_init(TID_TO_GLOBALID(THREAD_ROOT), &root_utcb);
+    thread_space(root, TID_TO_GLOBALID(THREAD_ROOT), &root_utcb);
+    as_map_user(root->as);
+
+    uint32_t regs[4] = {
+        [REG_R0] = (uint32_t) &kip,
+        [REG_R1] = (uint32_t) root->utcb,
+        [REG_R2] = 0,
+        [REG_R3] = 0,
+    };
+
+    thread_init_ctx((void *) &root_stack_end, root_thread, regs, root);
+
+    root->stack_base = (memptr_t) &root_stack_start;
+    root->stack_size =
+        (uint32_t) &root_stack_end - (uint32_t) &root_stack_start;
+    thread_init_canary(root);
+
+    root->priority = SCHED_PRIO_ROOT;
+    root->base_priority = SCHED_PRIO_ROOT;
+    root->state = T_RUNNABLE;
+    sched_enqueue(root);
 }
 
 void create_kernel_thread(void)
 {
-	kernel = thread_init(TID_TO_GLOBALID(THREAD_KERNEL), NULL);
-
-	thread_init_kernel_ctx(&kernel_stack_end, kernel);
-
-	/* Initialize stack tracking for kernel thread.
-	 * Kernel stack follows idle stack in memory layout.
-	 */
-	kernel->stack_base = (memptr_t) &idle_stack_end;
-	kernel->stack_size = (uint32_t) &kernel_stack_end -
-	                     (uint32_t) &idle_stack_end;
-	thread_init_canary(kernel);
-
-	/* This will prevent running other threads
-	 * than kernel until it will be initialized
-	 */
-	kernel->priority = SCHED_PRIO_SOFTIRQ;
-	kernel->base_priority = SCHED_PRIO_SOFTIRQ;
-	kernel->state = T_RUNNABLE;
-	sched_enqueue(kernel);
+    kernel = thread_init(TID_TO_GLOBALID(THREAD_KERNEL), NULL);
+
+    thread_init_kernel_ctx(&kernel_stack_end, kernel);
+
+    /* Initialize stack tracking for kernel thread.
+     * Kernel stack follows idle stack in memory layout.
+     */
+    kernel->stack_base = (memptr_t) &idle_stack_end;
+    kernel->stack_size =
+        (uint32_t) &kernel_stack_end - (uint32_t) &idle_stack_end;
+    thread_init_canary(kernel);
+
+    /* This will prevent running other threads
+     * than kernel until it will be initialized
+     */
+    kernel->priority = SCHED_PRIO_SOFTIRQ;
+    kernel->base_priority = SCHED_PRIO_SOFTIRQ;
+    kernel->state = T_RUNNABLE;
+    sched_enqueue(kernel);
 }
 
 void create_idle_thread(void)
 {
-	idle = thread_init(TID_TO_GLOBALID(THREAD_IDLE), NULL);
-	thread_init_ctx((void *) &idle_stack_end, idle_thread, NULL, idle);
-
-	idle->stack_base = (memptr_t) &idle_stack_start;
-	idle->stack_size = (uint32_t) &idle_stack_end -
-	                   (uint32_t) &idle_stack_start;
-	thread_init_canary(idle);
-
-	idle->priority = SCHED_PRIO_IDLE;
-	idle->base_priority = SCHED_PRIO_IDLE;
-	idle->state = T_RUNNABLE;
-	sched_enqueue(idle);
+    idle = thread_init(TID_TO_GLOBALID(THREAD_IDLE), NULL);
+    thread_init_ctx((void *) &idle_stack_end, idle_thread, NULL, idle);
+
+    idle->stack_base = (memptr_t) &idle_stack_start;
+    idle->stack_size =
+        (uint32_t) &idle_stack_end - (uint32_t) &idle_stack_start;
+    thread_init_canary(idle);
+
+    idle->priority = SCHED_PRIO_IDLE;
+    idle->base_priority = SCHED_PRIO_IDLE;
+    idle->state = T_RUNNABLE;
+    sched_enqueue(idle);
 }
 
 void switch_to_kernel(void) __NAKED;
 void switch_to_kernel(void)
 {
-	create_kernel_thread();
+    create_kernel_thread();
 
-	current = kernel;
-	init_ctx_switch(&kernel->ctx, kernel_thread);
+    current = kernel;
+    init_ctx_switch(&kernel->ctx, kernel_thread);
 }
 
 void set_kernel_state(thread_state_t state)
 {
-	/* Strict queue invariant: dequeue before blocking */
-	if (state != T_RUNNABLE)
-		sched_dequeue(kernel);
+    /* Strict queue invariant: dequeue before blocking */
+    if (state != T_RUNNABLE)
+        sched_dequeue(kernel);
 
-	kernel->state = state;
+    kernel->state = state;
 
-	if (state == T_RUNNABLE)
-		sched_enqueue(kernel);
+    if (state == T_RUNNABLE)
+        sched_enqueue(kernel);
 }
 
 static void kernel_thread(void)
 {
-	while (1) {
-		/* If all softirqs processed, call SVC to
-		 * switch context immediately
-		 */
-		softirq_execute();
-		irq_svc();
-	}
+    while (1) {
+        /* If all softirqs processed, call SVC to
+         * switch context immediately
+         */
+        softirq_execute();
+        irq_svc();
+    }
 }
 
 static void idle_thread(void)
 {
-	while (1)
+    while (1)
 #ifdef CONFIG_KTIMER_TICKLESS
-		ktimer_enter_tickless();
+        ktimer_enter_tickless();
 #else
-		wait_for_interrupt();
+        wait_for_interrupt();
 #endif /* CONFIG_KTIMER_TICKLESS */
 }
diff --git a/kernel/thread.c b/kernel/thread.c
index 56081864..ed405ccf 100644
--- a/kernel/thread.c
+++ b/kernel/thread.c
@@ -3,15 +3,15 @@
  * found in the LICENSE file.
  */
 
-#include <thread.h>
-#include <lib/ktable.h>
-#include <error.h>
 #include <debug.h>
-#include <sched.h>
-#include <platform/irq.h>
-#include <platform/armv7m.h>
+#include <error.h>
 #include <fpage_impl.h>
 #include <init_hook.h>
+#include <lib/ktable.h>
+#include <platform/armv7m.h>
+#include <platform/irq.h>
+#include <sched.h>
+#include <thread.h>
 
 /**
  * @file    thread.c
@@ -51,7 +51,7 @@ int thread_count;
  * See also platform/irq.h
  */
 
-volatile tcb_t *current; 			/* Currently on CPU */
+volatile tcb_t *current; /* Currently on CPU */
 void *current_utcb __USER_DATA;
 
 /* KIP declarations */
@@ -61,33 +61,32 @@ extern char *kip_extra;
 
 void thread_init_subsys()
 {
-	fpage_t *last = NULL;
-	int ret;
-
-	ktable_init(&thread_table);
-
-	kip.thread_info.s.system_base = THREAD_SYS;
-	kip.thread_info.s.user_base = THREAD_USER;
-
-	/* Create KIP fpages - these are critical for kernel operation.
-	 * Failure here indicates a severe configuration or memory problem.
-	 */
-	ret = assign_fpages_ext(-1, NULL,
-	                        (memptr_t) &kip, sizeof(kip_t),
-	                        &kip_fpage, &last);
-	if (ret < 0 || !kip_fpage) {
-		panic("THREAD: Failed to create KIP fpage (addr=%p sz=%d ret=%d)\n",
-		      &kip, sizeof(kip_t), ret);
-	}
-
-	last = NULL;
-	ret = assign_fpages_ext(-1, NULL,
-	                        (memptr_t) kip_extra, CONFIG_KIP_EXTRA_SIZE,
-	                        &kip_extra_fpage, &last);
-	if (ret < 0 || !kip_extra_fpage) {
-		panic("THREAD: Failed to create KIP extra fpage (addr=%p sz=%d ret=%d)\n",
-		      kip_extra, CONFIG_KIP_EXTRA_SIZE, ret);
-	}
+    fpage_t *last = NULL;
+    int ret;
+
+    ktable_init(&thread_table);
+
+    kip.thread_info.s.system_base = THREAD_SYS;
+    kip.thread_info.s.user_base = THREAD_USER;
+
+    /* Create KIP fpages - these are critical for kernel operation.
+     * Failure here indicates a severe configuration or memory problem.
+     */
+    ret = assign_fpages_ext(-1, NULL, (memptr_t) &kip, sizeof(kip_t),
+                            &kip_fpage, &last);
+    if (ret < 0 || !kip_fpage) {
+        panic("THREAD: Failed to create KIP fpage (addr=%p sz=%d ret=%d)\n",
+              &kip, sizeof(kip_t), ret);
+    }
+
+    last = NULL;
+    ret = assign_fpages_ext(-1, NULL, (memptr_t) kip_extra,
+                            CONFIG_KIP_EXTRA_SIZE, &kip_extra_fpage, &last);
+    if (ret < 0 || !kip_extra_fpage) {
+        panic(
+            "THREAD: Failed to create KIP extra fpage (addr=%p sz=%d ret=%d)\n",
+            kip_extra, CONFIG_KIP_EXTRA_SIZE, ret);
+    }
 }
 
 INIT_HOOK(thread_init_subsys, INIT_LEVEL_KERNEL);
@@ -99,28 +98,28 @@ extern tcb_t *caller;
  */
 static int thread_map_search(l4_thread_t globalid, int from, int to)
 {
-	int tid = GLOBALID_TO_TID(globalid);
+    int tid = GLOBALID_TO_TID(globalid);
 
-	/* Upper bound if beginning of array */
-	if (to == from || GLOBALID_TO_TID(thread_map[from]->t_globalid) >= tid)
-		return from;
+    /* Upper bound if beginning of array */
+    if (to == from || GLOBALID_TO_TID(thread_map[from]->t_globalid) >= tid)
+        return from;
 
-	while (from <= to) {
-		if ((to - from) <= 1)
-			return to;
+    while (from <= to) {
+        if ((to - from) <= 1)
+            return to;
 
-		int mid = from + (to - from) / 2;
+        int mid = from + (to - from) / 2;
 
-		if (GLOBALID_TO_TID(thread_map[mid]->t_globalid) > tid)
-			to = mid;
-		else if (GLOBALID_TO_TID(thread_map[mid]->t_globalid) < tid)
-			from = mid;
-		else
-			return mid;
-	}
+        if (GLOBALID_TO_TID(thread_map[mid]->t_globalid) > tid)
+            to = mid;
+        else if (GLOBALID_TO_TID(thread_map[mid]->t_globalid) < tid)
+            from = mid;
+        else
+            return mid;
+    }
 
-	/* not reached */
-	return -1;
+    /* not reached */
+    return -1;
 }
 
 /*
@@ -128,35 +127,35 @@ static int thread_map_search(l4_thread_t globalid, int from, int to)
  */
 static void thread_map_insert(l4_thread_t globalid, tcb_t *thr)
 {
-	if (thread_count == 0) {
-		thread_map[thread_count++] = thr;
-	} else {
-		int i = thread_map_search(globalid, 0, thread_count);
-		int j = thread_count;
-
-		/* Move forward
-		 * Don't check if count is out of range,
-		 * because we will fail on ktable_alloc
-		 */
-
-		for (; j > i; --j)
-			thread_map[j] = thread_map[j - 1];
-
-		thread_map[i] = thr;
-		++thread_count;
-	}
+    if (thread_count == 0) {
+        thread_map[thread_count++] = thr;
+    } else {
+        int i = thread_map_search(globalid, 0, thread_count);
+        int j = thread_count;
+
+        /* Move forward
+         * Don't check if count is out of range,
+         * because we will fail on ktable_alloc
+         */
+
+        for (; j > i; --j)
+            thread_map[j] = thread_map[j - 1];
+
+        thread_map[i] = thr;
+        ++thread_count;
+    }
 }
 
 static void thread_map_delete(l4_thread_t globalid)
 {
-	if (thread_count == 1) {
-		thread_count = 0;
-	} else {
-		int i = thread_map_search(globalid, 0, thread_count);
-		--thread_count;
-		for (; i < thread_count; i++)
-			thread_map[i] = thread_map[i + 1];
-	}
+    if (thread_count == 1) {
+        thread_count = 0;
+    } else {
+        int i = thread_map_search(globalid, 0, thread_count);
+        --thread_count;
+        for (; i < thread_count; i++)
+            thread_map[i] = thread_map[i + 1];
+    }
 }
 
 /*
@@ -164,241 +163,236 @@ static void thread_map_delete(l4_thread_t globalid)
  */
 tcb_t *thread_init(l4_thread_t globalid, utcb_t *utcb)
 {
-	tcb_t *thr = (tcb_t *) ktable_alloc(&thread_table);
+    tcb_t *thr = (tcb_t *) ktable_alloc(&thread_table);
 
-	if (!thr) {
-		set_caller_error(UE_OUT_OF_MEM);
-		return NULL;
-	}
+    if (!thr) {
+        set_caller_error(UE_OUT_OF_MEM);
+        return NULL;
+    }
 
-	thread_map_insert(globalid, thr);
-	thr->t_localid = 0x0;
+    thread_map_insert(globalid, thr);
+    thr->t_localid = 0x0;
 
-	thr->t_child = NULL;
-	thr->t_parent = NULL;
-	thr->t_sibling = NULL;
+    thr->t_child = NULL;
+    thr->t_parent = NULL;
+    thr->t_sibling = NULL;
 
-	thr->t_globalid = globalid;
-	if (utcb)
-		utcb->t_globalid = globalid;
+    thr->t_globalid = globalid;
+    if (utcb)
+        utcb->t_globalid = globalid;
 
-	thr->as = NULL;
-	thr->utcb = utcb;
-	thr->state = T_INACTIVE;
+    thr->as = NULL;
+    thr->utcb = utcb;
+    thr->state = T_INACTIVE;
 
-	thr->timeout_event = 0;
+    thr->timeout_event = 0;
 
-	/* Initialize scheduler fields */
-	thr->priority = SCHED_PRIO_DEFAULT;
-	thr->base_priority = SCHED_PRIO_DEFAULT;
-	thr->sched_link.prev = NULL;	/* NULL = not queued */
-	thr->sched_link.next = NULL;
+    /* Initialize scheduler fields */
+    thr->priority = SCHED_PRIO_DEFAULT;
+    thr->base_priority = SCHED_PRIO_DEFAULT;
+    thr->sched_link.prev = NULL; /* NULL = not queued */
+    thr->sched_link.next = NULL;
 
-	dbg_printf(DL_THREAD, "T: New thread: %t @[%p] \n", globalid, thr);
+    dbg_printf(DL_THREAD, "T: New thread: %t @[%p] \n", globalid, thr);
 
-	return thr;
+    return thr;
 }
 
 void thread_deinit(tcb_t *thr)
 {
-	thread_map_delete(thr->t_globalid);
-	ktable_free(&thread_table, (void *) thr);
+    thread_map_delete(thr->t_globalid);
+    ktable_free(&thread_table, (void *) thr);
 }
 
 /* Called from user thread */
 tcb_t *thread_create(l4_thread_t globalid, utcb_t *utcb)
 {
-	int id = GLOBALID_TO_TID(globalid);
+    int id = GLOBALID_TO_TID(globalid);
 
-	assert((intptr_t) caller);
+    assert((intptr_t) caller);
 
-	dbg_printf(DL_KDB, "THREAD_CREATE: gid=%p tid=%d utcb=%p\n",
-	           globalid, id, utcb);
+    dbg_printf(DL_KDB, "THREAD_CREATE: gid=%p tid=%d utcb=%p\n", globalid, id,
+               utcb);
 
-	if (id < THREAD_SYS ||
-	    globalid == L4_ANYTHREAD ||
-	    globalid == L4_ANYLOCALTHREAD) {
-		dbg_printf(DL_KDB, "THREAD_CREATE: rejected (id=%d)\n", id);
-		set_caller_error(UE_TC_NOT_AVAILABLE);
-		return NULL;
-	}
+    if (id < THREAD_SYS || globalid == L4_ANYTHREAD ||
+        globalid == L4_ANYLOCALTHREAD) {
+        dbg_printf(DL_KDB, "THREAD_CREATE: rejected (id=%d)\n", id);
+        set_caller_error(UE_TC_NOT_AVAILABLE);
+        return NULL;
+    }
 
-	tcb_t *thr = thread_init(globalid, utcb);
-	thr->t_parent = caller;
+    tcb_t *thr = thread_init(globalid, utcb);
+    thr->t_parent = caller;
 
-	/* Place under */
-	if (caller->t_child) {
-		tcb_t *t = caller->t_child;
+    /* Place under */
+    if (caller->t_child) {
+        tcb_t *t = caller->t_child;
 
-		while (t->t_sibling != 0)
-			t = t->t_sibling;
-		t->t_sibling = thr;
+        while (t->t_sibling != 0)
+            t = t->t_sibling;
+        t->t_sibling = thr;
 
-		thr->t_localid = t->t_localid + (1 << 6);
-	} else {
-		/* That is first thread in child chain */
-		caller->t_child = thr;
+        thr->t_localid = t->t_localid + (1 << 6);
+    } else {
+        /* That is first thread in child chain */
+        caller->t_child = thr;
 
-		thr->t_localid = (1 << 6);
-	}
+        thr->t_localid = (1 << 6);
+    }
 
-	return thr;
+    return thr;
 }
 
 void thread_destroy(tcb_t *thr)
 {
-	tcb_t *parent, *child, *prev_child;
-
-	/* Remove from scheduler ready queue if queued */
-	sched_dequeue(thr);
-
-	/* remove thr from its parent and its siblings */
-	parent = thr->t_parent;
-
-	if (parent->t_child == thr) {
-		parent->t_child = thr->t_sibling;
-	} else {
-		child = parent->t_child;
-		while (child != thr) {
-			prev_child = child;
-			child = child->t_sibling;
-		}
-		prev_child->t_sibling = child->t_sibling;
-	}
-
-	/* move thr's children to caller */
-	child = thr->t_child;
-
-	if (child) {
-		child->t_parent = caller;
-
-		while (child->t_sibling) {
-			child = child->t_sibling;
-			child->t_parent = caller;
-		}
-
-		/* connect thr's children to caller's children */
-		child->t_sibling = caller->t_child;
-		caller->t_child = thr->t_child;
-	}
-
-	/* Release address space reference.
-	 * This may free the AS if this was the last reference.
-	 */
-	if (thr->as)
-		as_put(thr->as);
-
-	thread_deinit(thr);
+    tcb_t *parent, *child, *prev_child;
+
+    /* Remove from scheduler ready queue if queued */
+    sched_dequeue(thr);
+
+    /* remove thr from its parent and its siblings */
+    parent = thr->t_parent;
+
+    if (parent->t_child == thr) {
+        parent->t_child = thr->t_sibling;
+    } else {
+        child = parent->t_child;
+        while (child != thr) {
+            prev_child = child;
+            child = child->t_sibling;
+        }
+        prev_child->t_sibling = child->t_sibling;
+    }
+
+    /* move thr's children to caller */
+    child = thr->t_child;
+
+    if (child) {
+        child->t_parent = caller;
+
+        while (child->t_sibling) {
+            child = child->t_sibling;
+            child->t_parent = caller;
+        }
+
+        /* connect thr's children to caller's children */
+        child->t_sibling = caller->t_child;
+        caller->t_child = thr->t_child;
+    }
+
+    /* Release address space reference.
+     * This may free the AS if this was the last reference.
+     */
+    if (thr->as)
+        as_put(thr->as);
+
+    thread_deinit(thr);
 }
 
 void thread_space(tcb_t *thr, l4_thread_t spaceid, utcb_t *utcb)
 {
-	/* If spaceid == dest than create new address space
-	 * else share address space between threads
-	 */
-	if (GLOBALID_TO_TID(thr->t_globalid) == GLOBALID_TO_TID(spaceid)) {
-		thr->as = as_create(thr->t_globalid);
-
-		if (!thr->as) {
-			dbg_printf(DL_KDB,
-			           "THREAD: as_create failed for %t\n",
-			           thr->t_globalid);
-			return;
-		}
-
-		/* Grant kip_fpage & kip_ext_fpage only to new AS.
-		 * These are critical for thread operation.
-		 */
-		if (map_fpage(NULL, thr->as, kip_fpage, GRANT) < 0) {
-			dbg_printf(DL_KDB, "THREAD: KIP map failed for %t\n",
-			           thr->t_globalid);
-		}
-		if (map_fpage(NULL, thr->as, kip_extra_fpage, GRANT) < 0) {
-			dbg_printf(DL_KDB, "THREAD: KIP extra map failed for %t\n",
-			           thr->t_globalid);
-		}
-
-		dbg_printf(DL_THREAD,
-		           "\tNew space: as: %p, utcb: %p \n", thr->as, utcb);
-	} else {
-		tcb_t *space;
-		as_t *shared_as;
-
-		irq_disable();
-		space = thread_by_globalid(spaceid);
-		if (!space || !space->as) {
-			irq_enable();
-			dbg_printf(DL_KDB,
-			           "THREAD: space thread %t not found\n",
-			           spaceid);
-			return;
-		}
-		shared_as = space->as;
-		as_get(shared_as);
-		irq_enable();
-
-		thr->as = shared_as;
-	}
-
-	/* If no caller, than it is mapping from kernel to root thread
-	 * (some special case for root_utcb)
-	 */
-	int ret;
-	if (caller) {
-		ret = map_area(caller->as, thr->as, (memptr_t) utcb,
-		         sizeof(utcb_t), GRANT, thread_ispriviliged(caller));
-	} else {
-		ret = map_area(thr->as, thr->as, (memptr_t) utcb,
-		         sizeof(utcb_t), GRANT, 1);
-	}
-
-	if (ret < 0)
-		dbg_printf(DL_KDB, "UTCB map_area failed: utcb=%p tid=%p\n",
-		           utcb, thr->t_globalid);
+    /* If spaceid == dest than create new address space
+     * else share address space between threads
+     */
+    if (GLOBALID_TO_TID(thr->t_globalid) == GLOBALID_TO_TID(spaceid)) {
+        thr->as = as_create(thr->t_globalid);
+
+        if (!thr->as) {
+            dbg_printf(DL_KDB, "THREAD: as_create failed for %t\n",
+                       thr->t_globalid);
+            return;
+        }
+
+        /* Grant kip_fpage & kip_ext_fpage only to new AS.
+         * These are critical for thread operation.
+         */
+        if (map_fpage(NULL, thr->as, kip_fpage, GRANT) < 0) {
+            dbg_printf(DL_KDB, "THREAD: KIP map failed for %t\n",
+                       thr->t_globalid);
+        }
+        if (map_fpage(NULL, thr->as, kip_extra_fpage, GRANT) < 0) {
+            dbg_printf(DL_KDB, "THREAD: KIP extra map failed for %t\n",
+                       thr->t_globalid);
+        }
+
+        dbg_printf(DL_THREAD, "\tNew space: as: %p, utcb: %p \n", thr->as,
+                   utcb);
+    } else {
+        tcb_t *space;
+        as_t *shared_as;
+
+        irq_disable();
+        space = thread_by_globalid(spaceid);
+        if (!space || !space->as) {
+            irq_enable();
+            dbg_printf(DL_KDB, "THREAD: space thread %t not found\n", spaceid);
+            return;
+        }
+        shared_as = space->as;
+        as_get(shared_as);
+        irq_enable();
+
+        thr->as = shared_as;
+    }
+
+    /* If no caller, than it is mapping from kernel to root thread
+     * (some special case for root_utcb)
+     */
+    int ret;
+    if (caller) {
+        ret = map_area(caller->as, thr->as, (memptr_t) utcb, sizeof(utcb_t),
+                       GRANT, thread_ispriviliged(caller));
+    } else {
+        ret = map_area(thr->as, thr->as, (memptr_t) utcb, sizeof(utcb_t), GRANT,
+                       1);
+    }
+
+    if (ret < 0)
+        dbg_printf(DL_KDB, "UTCB map_area failed: utcb=%p tid=%p\n", utcb,
+                   thr->t_globalid);
 }
 
 void thread_init_ctx(void *sp, void *pc, void *regs, tcb_t *thr)
 {
-	int i;
-
-	/* Reserve 8 words for fake context */
-	sp -= RESERVED_STACK;
-	thr->ctx.sp = (uint32_t) sp;
-
-	/* Set EXC_RETURN and CONTROL for thread and create initial stack for it
-	 * When thread is dispatched, on first context switch
-	 */
-	if (GLOBALID_TO_TID(thr->t_globalid) >= THREAD_ROOT) {
-		thr->ctx.ret = 0xFFFFFFFD;
-		thr->ctx.ctl = 0x3;
-	} else {
-		thr->ctx.ret = 0xFFFFFFF9;
-		thr->ctx.ctl = 0x0;
-	}
-
-	/* Initialize ctx.regs to zeros (r4-r11).
-	 * User-space uses r4-r11 as MR0-MR7 for IPC.
-	 */
-	for (i = 0; i < 8; i++)
-		thr->ctx.regs[i] = 0;
-
-	if (!regs) {
-		((uint32_t *) sp)[REG_R0] = 0x0;
-		((uint32_t *) sp)[REG_R1] = 0x0;
-		((uint32_t *) sp)[REG_R2] = 0x0;
-		((uint32_t *) sp)[REG_R3] = 0x0;
-	} else {
-		((uint32_t *) sp)[REG_R0] = ((uint32_t *) regs)[0];
-		((uint32_t *) sp)[REG_R1] = ((uint32_t *) regs)[1];
-		((uint32_t *) sp)[REG_R2] = ((uint32_t *) regs)[2];
-		((uint32_t *) sp)[REG_R3] = ((uint32_t *) regs)[3];
-	}
-
-	((uint32_t *) sp)[REG_R12] = 0x0;
-	((uint32_t *) sp)[REG_LR] = 0xFFFFFFFF;
-	((uint32_t *) sp)[REG_PC] = (uint32_t) pc;
-	((uint32_t *) sp)[REG_xPSR] = 0x1000000; /* Thumb bit on */
-
+    int i;
+
+    /* Reserve 8 words for fake context */
+    sp -= RESERVED_STACK;
+    thr->ctx.sp = (uint32_t) sp;
+
+    /* Set EXC_RETURN and CONTROL for thread and create initial stack for it
+     * When thread is dispatched, on first context switch
+     */
+    if (GLOBALID_TO_TID(thr->t_globalid) >= THREAD_ROOT) {
+        thr->ctx.ret = 0xFFFFFFFD;
+        thr->ctx.ctl = 0x3;
+    } else {
+        thr->ctx.ret = 0xFFFFFFF9;
+        thr->ctx.ctl = 0x0;
+    }
+
+    /* Initialize ctx.regs to zeros (r4-r11).
+     * User-space uses r4-r11 as MR0-MR7 for IPC.
+     */
+    for (i = 0; i < 8; i++)
+        thr->ctx.regs[i] = 0;
+
+    if (!regs) {
+        ((uint32_t *) sp)[REG_R0] = 0x0;
+        ((uint32_t *) sp)[REG_R1] = 0x0;
+        ((uint32_t *) sp)[REG_R2] = 0x0;
+        ((uint32_t *) sp)[REG_R3] = 0x0;
+    } else {
+        ((uint32_t *) sp)[REG_R0] = ((uint32_t *) regs)[0];
+        ((uint32_t *) sp)[REG_R1] = ((uint32_t *) regs)[1];
+        ((uint32_t *) sp)[REG_R2] = ((uint32_t *) regs)[2];
+        ((uint32_t *) sp)[REG_R3] = ((uint32_t *) regs)[3];
+    }
+
+    ((uint32_t *) sp)[REG_R12] = 0x0;
+    ((uint32_t *) sp)[REG_LR] = 0xFFFFFFFF;
+    ((uint32_t *) sp)[REG_PC] = (uint32_t) pc;
+    ((uint32_t *) sp)[REG_xPSR] = 0x1000000; /* Thumb bit on */
 }
 
 /* Kernel has no fake context, instead of that we rewind
@@ -408,21 +402,21 @@ void thread_init_ctx(void *sp, void *pc, void *regs, tcb_t *thr)
  */
 void thread_init_kernel_ctx(void *sp, tcb_t *thr)
 {
-	int i;
+    int i;
 
-	sp -= RESERVED_STACK;
+    sp -= RESERVED_STACK;
 
-	thr->ctx.sp = (uint32_t) sp;
-	thr->ctx.ret = 0xFFFFFFF9;
-	thr->ctx.ctl = 0x0;
+    thr->ctx.sp = (uint32_t) sp;
+    thr->ctx.ret = 0xFFFFFFF9;
+    thr->ctx.ctl = 0x0;
 
-	/* Initialize ctx.regs to zeros.
-	 * These hold r4-r11 which are restored by irq_restore.
-	 * User-space uses r4-r11 as MR0-MR7, so uninitialized
-	 * garbage here would corrupt IPC message registers.
-	 */
-	for (i = 0; i < 8; i++)
-		thr->ctx.regs[i] = 0;
+    /* Initialize ctx.regs to zeros.
+     * These hold r4-r11 which are restored by irq_restore.
+     * User-space uses r4-r11 as MR0-MR7, so uninitialized
+     * garbage here would corrupt IPC message registers.
+     */
+    for (i = 0; i < 8; i++)
+        thr->ctx.regs[i] = 0;
 }
 
 /*
@@ -430,133 +424,128 @@ void thread_init_kernel_ctx(void *sp, tcb_t *thr)
  */
 tcb_t *thread_by_globalid(l4_thread_t globalid)
 {
-	int idx = thread_map_search(globalid, 0, thread_count);
+    int idx = thread_map_search(globalid, 0, thread_count);
 
-	if (GLOBALID_TO_TID(thread_map[idx]->t_globalid)
-	    != GLOBALID_TO_TID(globalid))
-		return NULL;
-	return thread_map[idx];
+    if (GLOBALID_TO_TID(thread_map[idx]->t_globalid) !=
+        GLOBALID_TO_TID(globalid))
+        return NULL;
+    return thread_map[idx];
 }
 
 int thread_isrunnable(tcb_t *thr)
 {
-	return thr->state == T_RUNNABLE;
+    return thr->state == T_RUNNABLE;
 }
 
 tcb_t *thread_current()
 {
-	return (tcb_t *) current;
+    return (tcb_t *) current;
 }
 
 int thread_ispriviliged(tcb_t *thread)
 {
-	return GLOBALID_TO_TID(thread->t_globalid) == THREAD_ROOT;
+    return GLOBALID_TO_TID(thread->t_globalid) == THREAD_ROOT;
 }
 
 /* Switch context */
 void thread_switch(tcb_t *thr)
 {
-	tcb_t *prev = (tcb_t *) current;
-
-	assert((intptr_t) thr);
-	assert(thread_isrunnable(thr));
-
-	/* Restore previous thread's base priority if it was boosted.
-	 * This ensures IPC priority boost is temporary and only lasts
-	 * for one scheduling quantum.
-	 */
-	if (prev && prev->priority != prev->base_priority) {
-		sched_set_priority(prev, prev->base_priority);
-	}
-
-	/* Check stack canary before switching to this thread.
-	 * If canary is corrupted, the thread's stack has overflowed.
-	 */
-	if (!thread_check_canary(thr)) {
-		panic("Stack overflow: tid=%t, stack_base=%p, canary=%p\n",
-		      thr->t_globalid, thr->stack_base,
-		      thr->stack_base ? *((uint32_t *) thr->stack_base) : 0);
-	}
-
-	current = thr;
-	current_utcb = thr->utcb;
-	if (current->as)
-		as_setup_mpu(current->as, current->ctx.sp,
-		             ((uint32_t *) current->ctx.sp)[REG_PC],
-		             current->stack_base, current->stack_size);
+    tcb_t *prev = (tcb_t *) current;
+
+    assert((intptr_t) thr);
+    assert(thread_isrunnable(thr));
+
+    /* Restore previous thread's base priority if it was boosted.
+     * This ensures IPC priority boost is temporary and only lasts
+     * for one scheduling quantum.
+     */
+    if (prev && prev->priority != prev->base_priority) {
+        sched_set_priority(prev, prev->base_priority);
+    }
+
+    /* Check stack canary before switching to this thread.
+     * If canary is corrupted, the thread's stack has overflowed.
+     */
+    if (!thread_check_canary(thr)) {
+        panic("Stack overflow: tid=%t, stack_base=%p, canary=%p\n",
+              thr->t_globalid, thr->stack_base,
+              thr->stack_base ? *((uint32_t *) thr->stack_base) : 0);
+    }
+
+    current = thr;
+    current_utcb = thr->utcb;
+    if (current->as)
+        as_setup_mpu(current->as, current->ctx.sp,
+                     ((uint32_t *) current->ctx.sp)[REG_PC],
+                     current->stack_base, current->stack_size);
 }
 
 #ifdef CONFIG_KDB
 
 static char *kdb_get_thread_type(tcb_t *thr)
 {
-	int id = GLOBALID_TO_TID(thr->t_globalid);
-
-	if (id == THREAD_KERNEL)
-		return "KERN";
-	else if (id == THREAD_ROOT)
-		return "ROOT";
-	else if (id == THREAD_IDLE)
-		return "IDLE";
-	else if (id >= THREAD_USER)
-		return "[USR]";
-	else if (id >= THREAD_SYS)
-		return "[SYS]";
-
-	return "???";
+    int id = GLOBALID_TO_TID(thr->t_globalid);
+
+    if (id == THREAD_KERNEL)
+        return "KERN";
+    else if (id == THREAD_ROOT)
+        return "ROOT";
+    else if (id == THREAD_IDLE)
+        return "IDLE";
+    else if (id >= THREAD_USER)
+        return "[USR]";
+    else if (id >= THREAD_SYS)
+        return "[SYS]";
+
+    return "???";
 }
 
 void kdb_dump_threads(void)
 {
-	tcb_t *thr;
-	int idx;
+    tcb_t *thr;
+    int idx;
 
-	char *state[] = { "FREE", "RUN", "SVC", "RECV", "SEND" };
+    char *state[] = {"FREE", "RUN", "SVC", "RECV", "SEND"};
 
-	dbg_printf(DL_KDB, "%5s %8s %8s %6s %s\n",
-	           "type", "global", "local", "state", "parent");
+    dbg_printf(DL_KDB, "%5s %8s %8s %6s %s\n", "type", "global", "local",
+               "state", "parent");
 
-	for_each_in_ktable(thr, idx, (&thread_table)) {
-		dbg_printf(DL_KDB, "%5s %t %t %6s %t\n",
-		           kdb_get_thread_type(thr),
-		           thr->t_globalid, thr->t_localid, state[thr->state],
-		           (thr->t_parent) ? thr->t_parent->t_globalid : 0);
-	}
+    for_each_in_ktable (thr, idx, (&thread_table)) {
+        dbg_printf(DL_KDB, "%5s %t %t %6s %t\n", kdb_get_thread_type(thr),
+                   thr->t_globalid, thr->t_localid, state[thr->state],
+                   (thr->t_parent) ? thr->t_parent->t_globalid : 0);
+    }
 }
 
 void kdb_dump_stacks(void)
 {
-	tcb_t *thr;
-	int idx;
-
-	dbg_printf(DL_KDB, "%5s %8s %10s %10s %10s %6s\n",
-	           "type", "global", "stack_base", "stack_size", "sp", "canary");
-
-	for_each_in_ktable(thr, idx, (&thread_table)) {
-		char *canary_status;
-		uint32_t canary_val = 0;
-
-		if (!thr->stack_base) {
-			canary_status = "N/A";
-		} else {
-			canary_val = *((uint32_t *) thr->stack_base);
-			canary_status = (canary_val == STACK_CANARY) ? "OK" : "FAIL";
-		}
-
-		dbg_printf(DL_KDB, "%5s %t %p %10d %p %6s\n",
-		           kdb_get_thread_type(thr),
-		           thr->t_globalid,
-		           thr->stack_base,
-		           thr->stack_size,
-		           thr->ctx.sp,
-		           canary_status);
-
-		/* If canary failed, show what was found */
-		if (thr->stack_base && canary_val != STACK_CANARY) {
-			dbg_printf(DL_KDB, "      expected: %p, found: %p\n",
-			           STACK_CANARY, canary_val);
-		}
-	}
+    tcb_t *thr;
+    int idx;
+
+    dbg_printf(DL_KDB, "%5s %8s %10s %10s %10s %6s\n", "type", "global",
+               "stack_base", "stack_size", "sp", "canary");
+
+    for_each_in_ktable (thr, idx, (&thread_table)) {
+        char *canary_status;
+        uint32_t canary_val = 0;
+
+        if (!thr->stack_base) {
+            canary_status = "N/A";
+        } else {
+            canary_val = *((uint32_t *) thr->stack_base);
+            canary_status = (canary_val == STACK_CANARY) ? "OK" : "FAIL";
+        }
+
+        dbg_printf(DL_KDB, "%5s %t %p %10d %p %6s\n", kdb_get_thread_type(thr),
+                   thr->t_globalid, thr->stack_base, thr->stack_size,
+                   thr->ctx.sp, canary_status);
+
+        /* If canary failed, show what was found */
+        if (thr->stack_base && canary_val != STACK_CANARY) {
+            dbg_printf(DL_KDB, "      expected: %p, found: %p\n", STACK_CANARY,
+                       canary_val);
+        }
+    }
 }
 
-#endif	/* CONFIG_KDB */
+#endif /* CONFIG_KDB */
diff --git a/kernel/tickless-verify.c b/kernel/tickless-verify.c
index 6502e931..7a6886e0 100644
--- a/kernel/tickless-verify.c
+++ b/kernel/tickless-verify.c
@@ -16,11 +16,11 @@ static int verify_n = 0;
 static int verify_times = 0;
 
 static struct {
-	uint32_t ktimer_diff;
-	uint32_t hwtimer_diff;
-	uint32_t need;
-	uint32_t count;
-	uint32_t count_int;
+    uint32_t ktimer_diff;
+    uint32_t hwtimer_diff;
+    uint32_t need;
+    uint32_t count;
+    uint32_t count_int;
 } verify_records[TICKLESS_VERIFY_MAX_RECORD];
 
 static uint32_t verify_start_need;
@@ -36,171 +36,167 @@ static uint32_t verify_start_count_int;
 
 static void verify_save(uint32_t *systick, uint32_t *hwtimer)
 {
-	*systick = CONFIG_KTIMER_HEARTBEAT - systick_now();
-	*hwtimer = hwtimer_now();
+    *systick = CONFIG_KTIMER_HEARTBEAT - systick_now();
+    *hwtimer = hwtimer_now();
 }
 
 void tickless_verify_init()
 {
-	if (verify_enabled == 0) {
-		hwtimer_init();
-
-		for (int i = 0; i < TICKLESS_VERIFY_MAX_RECORD; i++) {
-			verify_records[i].need = 0;
-			verify_records[i].ktimer_diff = 0;
-			verify_records[i].hwtimer_diff = 0;
-			verify_records[i].count = 0;
-			verify_records[i].count_int = 0;
-		}
-
-		verify_n = 0;
-		verify_times = 0;
-
-		verify_enabled++;
-	}
+    if (verify_enabled == 0) {
+        hwtimer_init();
+
+        for (int i = 0; i < TICKLESS_VERIFY_MAX_RECORD; i++) {
+            verify_records[i].need = 0;
+            verify_records[i].ktimer_diff = 0;
+            verify_records[i].hwtimer_diff = 0;
+            verify_records[i].count = 0;
+            verify_records[i].count_int = 0;
+        }
+
+        verify_n = 0;
+        verify_times = 0;
+
+        verify_enabled++;
+    }
 }
 
 void tickless_verify_start(uint32_t ktimer_now, uint32_t need)
 {
-	verify_save(&verify_start_systick, &verify_start_hwtimer);
+    verify_save(&verify_start_systick, &verify_start_hwtimer);
 
-	verify_start_need = need;
-	verify_start_ktimer = ktimer_now;
-	verify_start_count = 0;
-	verify_start_count_int = 0;
+    verify_start_need = need;
+    verify_start_ktimer = ktimer_now;
+    verify_start_count = 0;
+    verify_start_count_int = 0;
 
-	verify_started = verify_enabled;
+    verify_started = verify_enabled;
 }
 
 void tickless_verify_stop(uint32_t ktimer_now)
 {
-	uint32_t systick;
-	uint32_t hwtimer;
-	uint32_t ktimer_diff;
-	uint32_t hwtimer_diff;
+    uint32_t systick;
+    uint32_t hwtimer;
+    uint32_t ktimer_diff;
+    uint32_t hwtimer_diff;
 
-	verify_save(&systick, &hwtimer);
+    verify_save(&systick, &hwtimer);
 
-	ktimer_diff = (ktimer_now - verify_start_ktimer) * CONFIG_KTIMER_HEARTBEAT
-	              + systick - verify_start_systick;
-	hwtimer_diff = (hwtimer - verify_start_hwtimer) * 2;
+    ktimer_diff = (ktimer_now - verify_start_ktimer) * CONFIG_KTIMER_HEARTBEAT +
+                  systick - verify_start_systick;
+    hwtimer_diff = (hwtimer - verify_start_hwtimer) * 2;
 
-	if (!verify_started)
-		return;
+    if (!verify_started)
+        return;
 
-	if (verify_n >= TICKLESS_VERIFY_MAX_RECORD)
-		verify_n = 0;
+    if (verify_n >= TICKLESS_VERIFY_MAX_RECORD)
+        verify_n = 0;
 
-	verify_records[verify_n].need =
-	    verify_start_need * CONFIG_KTIMER_HEARTBEAT -
-	    verify_start_systick;
-	verify_records[verify_n].ktimer_diff = ktimer_diff;
-	verify_records[verify_n].hwtimer_diff = hwtimer_diff;
-	verify_records[verify_n].count = verify_start_count;
-	verify_records[verify_n].count_int = verify_start_count_int;
+    verify_records[verify_n].need =
+        verify_start_need * CONFIG_KTIMER_HEARTBEAT - verify_start_systick;
+    verify_records[verify_n].ktimer_diff = ktimer_diff;
+    verify_records[verify_n].hwtimer_diff = hwtimer_diff;
+    verify_records[verify_n].count = verify_start_count;
+    verify_records[verify_n].count_int = verify_start_count_int;
 
-	verify_n++;
-	verify_times++;
+    verify_n++;
+    verify_times++;
 }
 
 void tickless_verify_count()
 {
-	verify_start_count++;
+    verify_start_count++;
 }
 
 void tickless_verify_count_int()
 {
-	verify_start_count_int++;
+    verify_start_count_int++;
 }
 
 int32_t tickless_verify_stat(int *times)
 {
-	int32_t sum = 0;
-	int n = verify_times;
-	uint32_t compensation = UINT32_MAX;
-	uint32_t int_compensation = UINT32_MAX;
+    int32_t sum = 0;
+    int n = verify_times;
+    uint32_t compensation = UINT32_MAX;
+    uint32_t int_compensation = UINT32_MAX;
 
-	if (n >= TICKLESS_VERIFY_MAX_RECORD) {
-		n = TICKLESS_VERIFY_MAX_RECORD;
-	}
+    if (n >= TICKLESS_VERIFY_MAX_RECORD) {
+        n = TICKLESS_VERIFY_MAX_RECORD;
+    }
 
 #ifdef CONFIG_KDB
-	dbg_printf(DL_KDB,
-	           "  Record  N: %10s | %10s | %10s | %10s | %10s | %s\n",
-	           "      NEED", "      REAL", "      KTIM", " REAL-NEED",
-	           " REAL-KTIM", "COUNT(INT)");
+    dbg_printf(DL_KDB, "  Record  N: %10s | %10s | %10s | %10s | %10s | %s\n",
+               "      NEED", "      REAL", "      KTIM", " REAL-NEED",
+               " REAL-KTIM", "COUNT(INT)");
 #endif
 
-	for (int i = 0; i < n; i++) {
-		int32_t hwtimer_need_diff =
-		    verify_records[i].hwtimer_diff -
-		    verify_records[i].need;
+    for (int i = 0; i < n; i++) {
+        int32_t hwtimer_need_diff =
+            verify_records[i].hwtimer_diff - verify_records[i].need;
 #ifdef CONFIG_KDB
-		int32_t hwtimer_ktimer_diff =
-		    verify_records[i].hwtimer_diff -
-		    verify_records[i].ktimer_diff;
-
-		dbg_printf(DL_KDB,
-		"%c Record %2d: %10d | %10d | %10d | %c%9d | %c%9d | %5d(%d)\n",
-		           i == verify_n - 1 ? '*' : ' ', i,
-		           verify_records[i].need,
-		           verify_records[i].hwtimer_diff,
-		           verify_records[i].ktimer_diff,
-		           hwtimer_need_diff >= 0 ? ' ' : '-',
-		           hwtimer_need_diff >= 0 ? hwtimer_need_diff : -hwtimer_need_diff,
-		           hwtimer_ktimer_diff >= 0 ? ' ' : '-',
-		           hwtimer_ktimer_diff >= 0 ? hwtimer_ktimer_diff : -hwtimer_ktimer_diff,
-		           verify_records[i].count,
-		           verify_records[i].count_int);
+        int32_t hwtimer_ktimer_diff =
+            verify_records[i].hwtimer_diff - verify_records[i].ktimer_diff;
+
+        dbg_printf(
+            DL_KDB,
+            "%c Record %2d: %10d | %10d | %10d | %c%9d | %c%9d | %5d(%d)\n",
+            i == verify_n - 1 ? '*' : ' ', i, verify_records[i].need,
+            verify_records[i].hwtimer_diff, verify_records[i].ktimer_diff,
+            hwtimer_need_diff >= 0 ? ' ' : '-',
+            hwtimer_need_diff >= 0 ? hwtimer_need_diff : -hwtimer_need_diff,
+            hwtimer_ktimer_diff >= 0 ? ' ' : '-',
+            hwtimer_ktimer_diff >= 0 ? hwtimer_ktimer_diff
+                                     : -hwtimer_ktimer_diff,
+            verify_records[i].count, verify_records[i].count_int);
 #endif /* CONFIG_KDB */
-		sum += hwtimer_need_diff;
-	}
+        sum += hwtimer_need_diff;
+    }
 
-	*times = verify_times;
+    *times = verify_times;
 
-	/* Tickless entering compensation */
-	for (int i = 0; i < n; i++) {
-		if (verify_records[i].count_int == 0) {
-			int32_t diff = verify_records[i].hwtimer_diff - verify_records[i].ktimer_diff;
+    /* Tickless entering compensation */
+    for (int i = 0; i < n; i++) {
+        if (verify_records[i].count_int == 0) {
+            int32_t diff =
+                verify_records[i].hwtimer_diff - verify_records[i].ktimer_diff;
 
-			if (diff > 0) {
-				int new_comp = diff / verify_records[i].count;
+            if (diff > 0) {
+                int new_comp = diff / verify_records[i].count;
 
-				if (verify_records[i].count * new_comp < diff) {
-					new_comp++;
-				}
+                if (verify_records[i].count * new_comp < diff) {
+                    new_comp++;
+                }
 
-				if (new_comp < compensation) {
-					compensation = new_comp;
-				}
-			}
-		}
-	}
+                if (new_comp < compensation) {
+                    compensation = new_comp;
+                }
+            }
+        }
+    }
 
-	/* Tickless interrupted compensation */
-	for (int i = 0; i < n; i++) {
-		if (verify_records[i].count_int == 0)
-			continue;
+    /* Tickless interrupted compensation */
+    for (int i = 0; i < n; i++) {
+        if (verify_records[i].count_int == 0)
+            continue;
 
-		int32_t diff = verify_records[i].hwtimer_diff -
-		               verify_records[i].ktimer_diff -
-		               verify_records[i].count * compensation;
+        int32_t diff = verify_records[i].hwtimer_diff -
+                       verify_records[i].ktimer_diff -
+                       verify_records[i].count * compensation;
 
-		if (diff > 0) {
-			int new_int_comp = diff / verify_records[i].count_int;
+        if (diff > 0) {
+            int new_int_comp = diff / verify_records[i].count_int;
 
-			if (verify_records[i].count_int * new_int_comp < diff) {
-				new_int_comp++;
-			}
+            if (verify_records[i].count_int * new_int_comp < diff) {
+                new_int_comp++;
+            }
 
-			if (new_int_comp < int_compensation) {
-				int_compensation = new_int_comp;
-			}
-		}
-	}
+            if (new_int_comp < int_compensation) {
+                int_compensation = new_int_comp;
+            }
+        }
+    }
 
-	dbg_printf(DL_KDB, "Suggest Compensation: %d(%d)\n",
-	           compensation, int_compensation);
+    dbg_printf(DL_KDB, "Suggest Compensation: %d(%d)\n", compensation,
+               int_compensation);
 
-	return sum / n;
+    return sum / n;
 }
diff --git a/kernel/user-log.c b/kernel/user-log.c
index dde7c3f5..53544774 100644
--- a/kernel/user-log.c
+++ b/kernel/user-log.c
@@ -3,21 +3,21 @@
  * found in the LICENSE file.
  */
 
-#include <user-log.h>
 #include <debug.h>
 #include <thread.h>
+#include <user-log.h>
 
 void user_log(tcb_t *from)
 {
-	char *format = (char *) from->ctx.regs[1];
-	va_list *va = (va_list *) from->ctx.regs[2];
+    char *format = (char *) from->ctx.regs[1];
+    va_list *va = (va_list *) from->ctx.regs[2];
 
-	/* Debug: validate pointers before use */
-	if (!format || (uint32_t)format < 0x08000000 ||
-	    (uint32_t)format > 0x20020000) {
-		dbg_printf(DL_KDB, "[ULOG: bad fmt %p]\n", format);
-		return;
-	}
+    /* Debug: validate pointers before use */
+    if (!format || (uint32_t) format < 0x08000000 ||
+        (uint32_t) format > 0x20020000) {
+        dbg_printf(DL_KDB, "[ULOG: bad fmt %p]\n", format);
+        return;
+    }
 
-	dbg_vprintf(DL_KDB, format, *va);
+    dbg_vprintf(DL_KDB, format, *va);
 }
diff --git a/loader/elf/elf.c b/loader/elf/elf.c
index 8973076d..ac377c37 100644
--- a/loader/elf/elf.c
+++ b/loader/elf/elf.c
@@ -13,233 +13,217 @@ void *str;
  * file is valid, < 0 if invalid.
  */
 
-int
-elf_checkFile(void *elfFile)
+int elf_checkFile(void *elfFile)
 {
-	return elf32_checkFile(elfFile);
+    return elf32_checkFile(elfFile);
 }
 
 /* Program Headers Access functions */
-uint16_t
-elf_getNumProgramHeaders(void *elfFile)
+uint16_t elf_getNumProgramHeaders(void *elfFile)
 {
-	return elf32_getNumProgramHeaders(elfFile);
+    return elf32_getNumProgramHeaders(elfFile);
 }
 
-uint32_t
-elf_getProgramHeaderFlags(void *elfFile, uint16_t ph)
+uint32_t elf_getProgramHeaderFlags(void *elfFile, uint16_t ph)
 {
-	return elf32_getProgramHeaderFlags(elfFile, ph);
+    return elf32_getProgramHeaderFlags(elfFile, ph);
 }
 
-uint32_t
-elf_getProgramHeaderType(void *elfFile, uint16_t ph)
+uint32_t elf_getProgramHeaderType(void *elfFile, uint16_t ph)
 {
-	return elf32_getProgramHeaderType(elfFile, ph);
+    return elf32_getProgramHeaderType(elfFile, ph);
 }
 
-uint32_t
-elf_getProgramHeaderPaddr(void *elfFile, uint16_t ph)
+uint32_t elf_getProgramHeaderPaddr(void *elfFile, uint16_t ph)
 {
-	return elf32_getProgramHeaderPaddr(elfFile, ph);
+    return elf32_getProgramHeaderPaddr(elfFile, ph);
 }
 
-uint32_t
-elf_getProgramHeaderVaddr(void *elfFile, uint16_t ph)
+uint32_t elf_getProgramHeaderVaddr(void *elfFile, uint16_t ph)
 {
-	return elf32_getProgramHeaderVaddr(elfFile, ph);
+    return elf32_getProgramHeaderVaddr(elfFile, ph);
 }
 
-uint32_t
-elf_getProgramHeaderMemorySize(void *elfFile, uint16_t ph)
+uint32_t elf_getProgramHeaderMemorySize(void *elfFile, uint16_t ph)
 {
-	return elf32_getProgramHeaderMemorySize(elfFile, ph);
+    return elf32_getProgramHeaderMemorySize(elfFile, ph);
 }
 
-uint32_t
-elf_getProgramHeaderFileSize(void *elfFile, uint16_t ph)
+uint32_t elf_getProgramHeaderFileSize(void *elfFile, uint16_t ph)
 {
-	return elf32_getProgramHeaderFileSize(elfFile, ph);
+    return elf32_getProgramHeaderFileSize(elfFile, ph);
 }
 
-uint32_t
-elf_getProgramHeaderOffset(void *elfFile, uint16_t ph)
+uint32_t elf_getProgramHeaderOffset(void *elfFile, uint16_t ph)
 {
-	return elf32_getProgramHeaderOffset(elfFile, ph);
+    return elf32_getProgramHeaderOffset(elfFile, ph);
 }
 
-char *
-elf_getSegmentStringTable(void *elfFile)
+char *elf_getSegmentStringTable(void *elfFile)
 {
-	return elf32_getSegmentStringTable(elfFile);
+    return elf32_getSegmentStringTable(elfFile);
 }
 
-char *
-elf_getStringTable(void *elfFile, int string_segment)
+char *elf_getStringTable(void *elfFile, int string_segment)
 {
-	return elf32_getStringTable(elfFile);
+    return elf32_getStringTable(elfFile);
 }
 
-unsigned
-elf_getNumSections(void *elfFile)
+unsigned elf_getNumSections(void *elfFile)
 {
-	return elf32_getNumSections(elfFile);
+    return elf32_getNumSections(elfFile);
 }
 
-char *
-elf_getSectionName(void *elfFile, int i)
+char *elf_getSectionName(void *elfFile, int i)
 {
-	return elf32_getSectionName(elfFile, i);
+    return elf32_getSectionName(elfFile, i);
 }
 
-uint32_t
-elf_getSectionFlags(void *elfFile, int i)
+uint32_t elf_getSectionFlags(void *elfFile, int i)
 {
-	return elf32_getSectionFlags(elfFile, i);
+    return elf32_getSectionFlags(elfFile, i);
 }
 
-uint32_t
-elf_getSectionType(void *elfFile, int i)
+uint32_t elf_getSectionType(void *elfFile, int i)
 {
-	return elf32_getSectionType(elfFile, i);
+    return elf32_getSectionType(elfFile, i);
 }
 
-uint32_t
-elf_getSectionSize(void *elfFile, int i)
+uint32_t elf_getSectionSize(void *elfFile, int i)
 {
-	return elf32_getSectionSize(elfFile, i);
+    return elf32_getSectionSize(elfFile, i);
 }
 
-uint32_t
-elf_getSectionAddr(void *elfFile, int i)
+uint32_t elf_getSectionAddr(void *elfFile, int i)
 {
-	return elf32_getSectionAddr(elfFile, i);
+    return elf32_getSectionAddr(elfFile, i);
 }
 
-void *
-elf_getSection(void *elfFile, int i)
+void *elf_getSection(void *elfFile, int i)
 {
-	return elf32_getSection(elfFile, i);
+    return elf32_getSection(elfFile, i);
 }
 
-void *
-elf_getSectionNamed(void *elfFile, char *_str)
+void *elf_getSectionNamed(void *elfFile, char *_str)
 {
-	return elf32_getSectionNamed(elfFile, _str);
+    return elf32_getSectionNamed(elfFile, _str);
 }
 
-void
-elf_getProgramHeaderInfo(void *elfFile, uint16_t ph, uint32_t *p_vaddr,
-                         uint32_t *p_paddr, uint32_t *p_filesz, uint32_t *p_offset,
-                         uint32_t *p_memsz)
+void elf_getProgramHeaderInfo(void *elfFile,
+                              uint16_t ph,
+                              uint32_t *p_vaddr,
+                              uint32_t *p_paddr,
+                              uint32_t *p_filesz,
+                              uint32_t *p_offset,
+                              uint32_t *p_memsz)
 {
-	*p_vaddr = elf_getProgramHeaderVaddr(elfFile, ph);
-	*p_paddr = elf_getProgramHeaderPaddr(elfFile, ph);
-	*p_filesz = elf_getProgramHeaderFileSize(elfFile, ph);
-	*p_offset = elf_getProgramHeaderOffset(elfFile, ph);
-	*p_memsz = elf_getProgramHeaderMemorySize(elfFile, ph);
+    *p_vaddr = elf_getProgramHeaderVaddr(elfFile, ph);
+    *p_paddr = elf_getProgramHeaderPaddr(elfFile, ph);
+    *p_filesz = elf_getProgramHeaderFileSize(elfFile, ph);
+    *p_offset = elf_getProgramHeaderOffset(elfFile, ph);
+    *p_memsz = elf_getProgramHeaderMemorySize(elfFile, ph);
 }
 
-uint32_t
-elf_getEntryPoint(void *elfFile)
+uint32_t elf_getEntryPoint(void *elfFile)
 {
-	return elf32_getEntryPoint(elfFile);
+    return elf32_getEntryPoint(elfFile);
 }
 
 
-bool
-elf_getMemoryBounds(void *elfFile, bool phys, uint32_t *min, uint32_t *max)
+bool elf_getMemoryBounds(void *elfFile, bool phys, uint32_t *min, uint32_t *max)
 {
-	uint32_t mem_min = UINT32_MAX;
-	uint32_t mem_max = 0;
-	int i;
+    uint32_t mem_min = UINT32_MAX;
+    uint32_t mem_max = 0;
+    int i;
 
-	if (elf_checkFile(elfFile) != 0) {
-		return false;
-	}
+    if (elf_checkFile(elfFile) != 0) {
+        return false;
+    }
 
-	for (i = 0; i < elf_getNumProgramHeaders(elfFile); i++) {
-		uint32_t sect_min, sect_max;
+    for (i = 0; i < elf_getNumProgramHeaders(elfFile); i++) {
+        uint32_t sect_min, sect_max;
 
-		if (elf_getProgramHeaderMemorySize(elfFile, i) == 0) {
-			continue;
-		}
+        if (elf_getProgramHeaderMemorySize(elfFile, i) == 0) {
+            continue;
+        }
 
-		if (phys) {
-			sect_min = elf_getProgramHeaderPaddr(elfFile, i);
-		} else {
-			sect_min = elf_getProgramHeaderVaddr(elfFile, i);
-		}
+        if (phys) {
+            sect_min = elf_getProgramHeaderPaddr(elfFile, i);
+        } else {
+            sect_min = elf_getProgramHeaderVaddr(elfFile, i);
+        }
 
-		sect_max = sect_min + elf_getProgramHeaderMemorySize(elfFile, i);
+        sect_max = sect_min + elf_getProgramHeaderMemorySize(elfFile, i);
 
-		if (sect_max > mem_max) {
-			mem_max = sect_max;
-		}
-		if (sect_min < mem_min) {
-			mem_min = sect_min;
-		}
-	}
-	*min = mem_min;
-	*max = mem_max;
+        if (sect_max > mem_max) {
+            mem_max = sect_max;
+        }
+        if (sect_min < mem_min) {
+            mem_min = sect_min;
+        }
+    }
+    *min = mem_min;
+    *max = mem_max;
 
-	return true;
+    return true;
 };
 
-bool
-elf_vaddrInProgramHeader(void *elfFile, uint16_t ph, uint32_t vaddr)
+bool elf_vaddrInProgramHeader(void *elfFile, uint16_t ph, uint32_t vaddr)
 {
-	uint32_t min = elf_getProgramHeaderVaddr(elfFile, ph);
-	uint32_t max = min + elf_getProgramHeaderMemorySize(elfFile, ph);
-	if (vaddr >= min && vaddr < max) {
-		return true;
-	} else {
-		return false;
-	}
+    uint32_t min = elf_getProgramHeaderVaddr(elfFile, ph);
+    uint32_t max = min + elf_getProgramHeaderMemorySize(elfFile, ph);
+    if (vaddr >= min && vaddr < max) {
+        return true;
+    } else {
+        return false;
+    }
 }
 
-uint32_t
-elf_vtopProgramHeader(void *elfFile, uint16_t ph, uint32_t vaddr)
+uint32_t elf_vtopProgramHeader(void *elfFile, uint16_t ph, uint32_t vaddr)
 {
-	uint32_t ph_phys = elf_getProgramHeaderPaddr(elfFile, ph);
-	uint32_t ph_virt = elf_getProgramHeaderVaddr(elfFile, ph);
-	uint32_t paddr;
+    uint32_t ph_phys = elf_getProgramHeaderPaddr(elfFile, ph);
+    uint32_t ph_virt = elf_getProgramHeaderVaddr(elfFile, ph);
+    uint32_t paddr;
 
-	paddr = vaddr - ph_virt + ph_phys;
+    paddr = vaddr - ph_virt + ph_phys;
 
-	return paddr;
+    return paddr;
 }
 
 uint32_t elf_loadFile(void *elfFile)
 {
-	int i;
-	int num_pheaders;
-	if (elf_checkFile(elfFile) != 0) {
-		return false;
-	}
-
-	num_pheaders = elf_getNumProgramHeaders(elfFile);
-	dbg_printf(DL_BASIC, "Number of program headers: %d\n", num_pheaders);
-
-	for (i = 0; i < num_pheaders; i++) {
-		/* Load that section */
-		uint32_t dest, src;
-		size_t len;
-
-		dest = elf_getProgramHeaderPaddr(elfFile, i);
-		dbg_printf(DL_BASIC, "Elf file pheader physical: 0x%x\n", (unsigned int)dest);
-		dbg_printf(DL_BASIC, "Elf file pheader virtual: 0x%x\n",
-		           (unsigned int)elf_getProgramHeaderVaddr(elfFile, i));
-		len = elf_getProgramHeaderFileSize(elfFile, i);
-		dbg_printf(DL_BASIC, "This section's size in file: %p\n", len);
-		src = (uint32_t)(uintptr_t) elfFile + elf_getProgramHeaderOffset(elfFile, i);
-		dbg_printf(DL_BASIC, "Elf program header offset: %p\n", src);
-		dbg_printf(DL_BASIC, "Copying to range from 0x%x to 0x%x of size: 0x%x\n",
-		           (unsigned int)dest, (unsigned int)dest + (unsigned int)len, (unsigned int)len);
-		memcpy((void*)(uintptr_t) dest, (void*)(uintptr_t) src, len);
-		dest += len;
-	}
-	dbg_printf(DL_BASIC, "\n");
-
-	return elf_getEntryPoint(elfFile);
+    int i;
+    int num_pheaders;
+    if (elf_checkFile(elfFile) != 0) {
+        return false;
+    }
+
+    num_pheaders = elf_getNumProgramHeaders(elfFile);
+    dbg_printf(DL_BASIC, "Number of program headers: %d\n", num_pheaders);
+
+    for (i = 0; i < num_pheaders; i++) {
+        /* Load that section */
+        uint32_t dest, src;
+        size_t len;
+
+        dest = elf_getProgramHeaderPaddr(elfFile, i);
+        dbg_printf(DL_BASIC, "Elf file pheader physical: 0x%x\n",
+                   (unsigned int) dest);
+        dbg_printf(DL_BASIC, "Elf file pheader virtual: 0x%x\n",
+                   (unsigned int) elf_getProgramHeaderVaddr(elfFile, i));
+        len = elf_getProgramHeaderFileSize(elfFile, i);
+        dbg_printf(DL_BASIC, "This section's size in file: %p\n", len);
+        src = (uint32_t) (uintptr_t) elfFile +
+              elf_getProgramHeaderOffset(elfFile, i);
+        dbg_printf(DL_BASIC, "Elf program header offset: %p\n", src);
+        dbg_printf(
+            DL_BASIC, "Copying to range from 0x%x to 0x%x of size: 0x%x\n",
+            (unsigned int) dest, (unsigned int) dest + (unsigned int) len,
+            (unsigned int) len);
+        memcpy((void *) (uintptr_t) dest, (void *) (uintptr_t) src, len);
+        dest += len;
+    }
+    dbg_printf(DL_BASIC, "\n");
+
+    return elf_getEntryPoint(elfFile);
 }
diff --git a/loader/elf/elf32.c b/loader/elf/elf32.c
index adf8acf1..288130b9 100644
--- a/loader/elf/elf32.c
+++ b/loader/elf/elf32.c
@@ -9,14 +9,13 @@
 
 int elf32_checkFile(struct Elf32_Header *file)
 {
-	if (file->e_ident[EI_MAG0] != ELFMAG0 ||
-	    file->e_ident[EI_MAG1] != ELFMAG1 ||
-	    file->e_ident[EI_MAG2] != ELFMAG2 ||
-	    file->e_ident[EI_MAG3] != ELFMAG3)
-		return -1;	/* not an elf file */
-	if (file->e_ident[EI_CLASS] != ELFCLASS32)
-		return -2;	/* not 32-bit file */
-	return 0;		/* elf file looks OK */
+    if (file->e_ident[EI_MAG0] != ELFMAG0 ||
+        file->e_ident[EI_MAG1] != ELFMAG1 ||
+        file->e_ident[EI_MAG2] != ELFMAG2 || file->e_ident[EI_MAG3] != ELFMAG3)
+        return -1; /* not an elf file */
+    if (file->e_ident[EI_CLASS] != ELFCLASS32)
+        return -2; /* not 32-bit file */
+    return 0;      /* elf file looks OK */
 }
 
 /*
@@ -24,13 +23,13 @@ int elf32_checkFile(struct Elf32_Header *file)
  */
 unsigned elf32_getNumSections(struct Elf32_Header *elfFile)
 {
-	return elfFile->e_shnum;
+    return elfFile->e_shnum;
 }
 
 char *elf32_getStringTable(struct Elf32_Header *elfFile)
 {
-	struct Elf32_Shdr *sections = elf32_getSectionTable(elfFile);
-	return (char *) elfFile + sections[elfFile->e_shstrndx].sh_offset;
+    struct Elf32_Shdr *sections = elf32_getSectionTable(elfFile);
+    return (char *) elfFile + sections[elfFile->e_shstrndx].sh_offset;
 }
 
 /* Returns a pointer to the program segment table, which is an array of
@@ -38,112 +37,117 @@ char *elf32_getStringTable(struct Elf32_Header *elfFile)
  * getNumProgramSegments. */
 struct Elf32_Phdr *elf32_getProgramSegmentTable(struct Elf32_Header *elfFile)
 {
-	struct Elf32_Header *fileHdr = elfFile;
-	return (struct Elf32_Phdr *)(fileHdr->e_phoff + (long) elfFile);
+    struct Elf32_Header *fileHdr = elfFile;
+    return (struct Elf32_Phdr *) (fileHdr->e_phoff + (long) elfFile);
 }
 
 /* Returns the number of program segments in this elf file. */
 uint16_t elf32_getNumProgramHeaders(struct Elf32_Header *elfFile)
 {
-	struct Elf32_Header *fileHdr = elfFile;
-	return fileHdr->e_phnum;
+    struct Elf32_Header *fileHdr = elfFile;
+    return fileHdr->e_phnum;
 }
 
 char *elf32_getSectionName(struct Elf32_Header *elfFile, int i)
 {
-	struct Elf32_Shdr *sections = elf32_getSectionTable(elfFile);
-	char *str_table = elf32_getSegmentStringTable(elfFile);
-	if (!str_table) {
-		return "<corrupted>";
-	} else {
-		return str_table + sections[i].sh_name;
-	}
+    struct Elf32_Shdr *sections = elf32_getSectionTable(elfFile);
+    char *str_table = elf32_getSegmentStringTable(elfFile);
+    if (!str_table) {
+        return "<corrupted>";
+    } else {
+        return str_table + sections[i].sh_name;
+    }
 }
 
 uint32_t elf32_getSectionSize(struct Elf32_Header *elfFile, int i)
 {
-	struct Elf32_Shdr *sections = elf32_getSectionTable(elfFile);
-	return sections[i].sh_size;
+    struct Elf32_Shdr *sections = elf32_getSectionTable(elfFile);
+    return sections[i].sh_size;
 }
 
 uint32_t elf32_getSectionAddr(struct Elf32_Header *elfFile, int i)
 {
-	struct Elf32_Shdr *sections = elf32_getSectionTable(elfFile);
-	return sections[i].sh_addr;
+    struct Elf32_Shdr *sections = elf32_getSectionTable(elfFile);
+    return sections[i].sh_addr;
 }
 
 void *elf32_getSection(struct Elf32_Header *elfFile, int i)
 {
-	struct Elf32_Shdr *sections = elf32_getSectionTable(elfFile);
-	return (char *) elfFile + sections[i].sh_offset;
+    struct Elf32_Shdr *sections = elf32_getSectionTable(elfFile);
+    return (char *) elfFile + sections[i].sh_offset;
 }
 
 void *elf32_getSectionNamed(struct Elf32_Header *elfFile, char *str)
 {
-	int numSections = elf32_getNumSections(elfFile);
-	int i;
-	for (i = 0; i < numSections; i++) {
-		if (strcmp(str, elf32_getSectionName(elfFile, i)) == 0) {
-			return elf32_getSection(elfFile, i);
-		}
-	}
-	return NULL;
+    int numSections = elf32_getNumSections(elfFile);
+    int i;
+    for (i = 0; i < numSections; i++) {
+        if (strcmp(str, elf32_getSectionName(elfFile, i)) == 0) {
+            return elf32_getSection(elfFile, i);
+        }
+    }
+    return NULL;
 }
 
 char *elf32_getSegmentStringTable(struct Elf32_Header *elfFile)
 {
-	struct Elf32_Header *fileHdr = (struct Elf32_Header *) elfFile;
-	if (fileHdr->e_shstrndx == 0) {
-		return NULL;
-	} else {
-		return elf32_getStringTable(elfFile);
-	}
+    struct Elf32_Header *fileHdr = (struct Elf32_Header *) elfFile;
+    if (fileHdr->e_shstrndx == 0) {
+        return NULL;
+    } else {
+        return elf32_getStringTable(elfFile);
+    }
 }
 
 #ifdef ELF_DEBUG
 void elf32_printStringTable(struct Elf32_Header *elfFile)
 {
-	int counter;
-	struct Elf32_Shdr *sections = elf32_getSectionTable(elfFile);
-	char * stringTable;
+    int counter;
+    struct Elf32_Shdr *sections = elf32_getSectionTable(elfFile);
+    char *stringTable;
 
-	if (!sections) {
-		dbg_printf(DL_BASIC, "No sections.\n");
-		return;
-	}
+    if (!sections) {
+        dbg_printf(DL_BASIC, "No sections.\n");
+        return;
+    }
 
-	stringTable = ((void *) elfFile) + sections[elfFile->e_shstrndx].sh_offset;
+    stringTable = ((void *) elfFile) + sections[elfFile->e_shstrndx].sh_offset;
 
-	dbg_printf(DL_BASIC, "File is %p; sections is %p; string table is %p\n", elfFile, sections, stringTable);
+    dbg_printf(DL_BASIC, "File is %p; sections is %p; string table is %p\n",
+               elfFile, sections, stringTable);
 
-	for (counter = 0; counter < sections[elfFile->e_shstrndx].sh_size; counter++) {
-		dbg_printf(DL_BASIC, "%02x %c ", stringTable[counter],
-		           stringTable[counter] >= 0x20 ? stringTable[counter] : '.');
-	}
+    for (counter = 0; counter < sections[elfFile->e_shstrndx].sh_size;
+         counter++) {
+        dbg_printf(DL_BASIC, "%02x %c ", stringTable[counter],
+                   stringTable[counter] >= 0x20 ? stringTable[counter] : '.');
+    }
 }
 #endif
 
 int elf32_getSegmentType(struct Elf32_Header *elfFile, int segment)
 {
-	return elf32_getProgramSegmentTable(elfFile)[segment].p_type;
+    return elf32_getProgramSegmentTable(elfFile)[segment].p_type;
 }
 
-void elf32_getSegmentInfo(struct Elf32_Header *elfFile, int segment,
-                          uint64_t *p_vaddr, uint64_t *p_addr,
-                          uint64_t *p_filesz, uint64_t *p_offset,
+void elf32_getSegmentInfo(struct Elf32_Header *elfFile,
+                          int segment,
+                          uint64_t *p_vaddr,
+                          uint64_t *p_addr,
+                          uint64_t *p_filesz,
+                          uint64_t *p_offset,
                           uint64_t *p_memsz)
 {
-	struct Elf32_Phdr *segments;
-
-	segments = elf32_getProgramSegmentTable(elfFile);
-	*p_addr = segments[segment].p_paddr;
-	*p_vaddr = segments[segment].p_vaddr;
-	*p_filesz = segments[segment].p_filesz;
-	*p_offset = segments[segment].p_offset;
-	*p_memsz = segments[segment].p_memsz;
+    struct Elf32_Phdr *segments;
+
+    segments = elf32_getProgramSegmentTable(elfFile);
+    *p_addr = segments[segment].p_paddr;
+    *p_vaddr = segments[segment].p_vaddr;
+    *p_filesz = segments[segment].p_filesz;
+    *p_offset = segments[segment].p_offset;
+    *p_memsz = segments[segment].p_memsz;
 }
 
 uint32_t elf32_getEntryPoint(struct Elf32_Header *elfFile)
 {
-	return elfFile->e_entry;
+    return elfFile->e_entry;
 }
diff --git a/loader/entry.c b/loader/entry.c
index 95a96221..092f3f54 100644
--- a/loader/entry.c
+++ b/loader/entry.c
@@ -9,14 +9,13 @@
 #include INC_PLAT(systick.h)
 #include INC_PLAT(nvic.h)
 
+#include <debug.h>
+#include <error.h>
+#include <lib/string.h>
 #include <platform/debug_uart.h>
 #include <platform/irq.h>
 #include <platform/link.h>
-#include <error.h>
-#include <debug.h>
 #include <types.h>
-#include <debug.h>
-#include <lib/string.h>
 
 #include <elf/elf.h>
 
@@ -35,80 +34,80 @@ void __loader_start(void);
 
 void nointerrupt(void)
 {
-	while (1)
-		/* wait */ ;
+    while (1)
+        /* wait */;
 }
 
 void dummy_handler(void)
 {
-	return;
+    return;
 }
 
 __ISR_VECTOR
-void (* const g_pfnVectors[])(void) = {
-	/* Core Level - ARM Cortex-M */
-	(void *) &stack_end,	/* initial stack pointer */
-	__loader_start,		/* reset handler */
-	nointerrupt,		/* NMI handler */
-	nointerrupt,		/* hard fault handler */
-	nointerrupt,		/* MPU fault handler */
-	nointerrupt,		/* bus fault handler */
-	nointerrupt,		/* usage fault handler */
-	0,			/* Reserved */
-	0,			/* Reserved */
-	0,			/* Reserved */
-	0,			/* Reserved */
-	nointerrupt,		/* SVCall handler */
-	nointerrupt,		/* Debug monitor handler */
-	0,			/* Reserved */
-	dummy_handler,		/* PendSV handler */
-	dummy_handler, 		/* SysTick handler */
-	/* Chip Level: vendor specific */
-	/* FIXME: use better IRQ vector generator */
+void (*const g_pfnVectors[])(void) = {
+    /* Core Level - ARM Cortex-M */
+    (void *) &stack_end, /* initial stack pointer */
+    __loader_start,      /* reset handler */
+    nointerrupt,         /* NMI handler */
+    nointerrupt,         /* hard fault handler */
+    nointerrupt,         /* MPU fault handler */
+    nointerrupt,         /* bus fault handler */
+    nointerrupt,         /* usage fault handler */
+    0,                   /* Reserved */
+    0,                   /* Reserved */
+    0,                   /* Reserved */
+    0,                   /* Reserved */
+    nointerrupt,         /* SVCall handler */
+    nointerrupt,         /* Debug monitor handler */
+    0,                   /* Reserved */
+    dummy_handler,       /* PendSV handler */
+    dummy_handler,       /* SysTick handler */
+                         /* Chip Level: vendor specific */
+                         /* FIXME: use better IRQ vector generator */
 #include INC_PLAT(nvic_table.h)
 };
 
 int main(void)
 {
-	void (*kernel_entry)(void);
+    void (*kernel_entry)(void);
 
-	irq_disable();
-	irq_init();
-	irq_enable();
+    irq_disable();
+    irq_init();
+    irq_enable();
 
-	dbg_layer = DL_BASIC;
-	dbg_uart_init();
+    dbg_layer = DL_BASIC;
+    dbg_uart_init();
 
-	dbg_printf(DL_BASIC, "loading kernel ...\n");
+    dbg_printf(DL_BASIC, "loading kernel ...\n");
 
-	dbg_printf(DL_BASIC, "ELF check result = %d\n",
-	           elf_checkFile((void *) 0x800c000));
+    dbg_printf(DL_BASIC, "ELF check result = %d\n",
+               elf_checkFile((void *) 0x800c000));
 
-	kernel_entry = (void (*)(void))(elf_loadFile((void *) 0x800c000));
-	irq_disable();
+    kernel_entry = (void (*)(void))(elf_loadFile((void *) 0x800c000));
+    irq_disable();
 
-	memory_remap_sram();
+    memory_remap_sram();
 
-	kernel_entry();
+    kernel_entry();
 
-	while (1)
-		;
-	/* Not reached */
-	return 0;
+    while (1)
+        ;
+    /* Not reached */
+    return 0;
 }
 
 void __loader_start(void)
 {
-	/* Copy data segments */
-	memcpy(&data_start, &kernel_flash_start + (&kernel_end - &kernel_start),
-	       (&data_end - &data_start) * sizeof(uint32_t));
-	/* DATA (ROM) -> DATA (RAM) */
+    /* Copy data segments */
+    memcpy(&data_start, &kernel_flash_start + (&kernel_end - &kernel_start),
+           (&data_end - &data_start) * sizeof(uint32_t));
+    /* DATA (ROM) -> DATA (RAM) */
 
-	/* Fill bss with zeroes */
-	memset(&bss_start, 0, (&bss_end - &bss_start) * sizeof(uint32_t));
+    /* Fill bss with zeroes */
+    memset(&bss_start, 0, (&bss_end - &bss_start) * sizeof(uint32_t));
 
-	sys_clock_init();
+    sys_clock_init();
 
-	/* entry point */
-	main();
+    /* entry point */
+    main();
 }
diff --git a/loader/include/elf/elf.h b/loader/include/elf/elf.h
index 3ec4ee2e..f295a644 100644
--- a/loader/include/elf/elf.h
+++ b/loader/include/elf/elf.h
@@ -11,8 +11,8 @@
 The ELF library is designed to make the task of parsing and getting information
 out of an ELF file easier.
 
-It provides function to obtain the various different fields in the ELF header, and
-the program and segment information.
+It provides function to obtain the various different fields in the ELF header,
+and the program and segment information.
 
 Also importantly, it provides a function elf_loadFile which will load a given
 ELF file into memory.
@@ -22,35 +22,35 @@ ELF file into memory.
 #ifndef __ELF_ELF_H__
 #define __ELF_ELF_H__
 
-#include "elf32.h"
 #include <debug.h>
 #include <types.h>
+#include "elf32.h"
 
 /*
  * constants for Elf32_Phdr.p_flags
  */
-#define PF_X		1	/* readable segment */
-#define PF_W		2	/* writeable segment */
-#define PF_R		4	/* executable segment */
+#define PF_X 1 /* readable segment */
+#define PF_W 2 /* writeable segment */
+#define PF_R 4 /* executable segment */
 
 /*
  * constants for indexing into Elf64_Header_t.e_ident
  */
-#define EI_MAG0		0
-#define EI_MAG1		1
-#define EI_MAG2		2
-#define EI_MAG3		3
-#define EI_CLASS	4
-#define EI_DATA		5
-#define EI_VERSION	6
-
-#define ELFMAG0         '\177'
-#define ELFMAG1         'E'
-#define ELFMAG2         'L'
-#define ELFMAG3         'F'
-
-#define ELFCLASS32      1
-#define ELFCLASS64      2
+#define EI_MAG0 0
+#define EI_MAG1 1
+#define EI_MAG2 2
+#define EI_MAG3 3
+#define EI_CLASS 4
+#define EI_DATA 5
+#define EI_VERSION 6
+
+#define ELFMAG0 '\177'
+#define ELFMAG1 'E'
+#define ELFMAG2 'L'
+#define ELFMAG3 'F'
+
+#define ELFCLASS32 1
+#define ELFCLASS64 2
 
 #define PT_NULL 0
 #define PT_LOAD 1
@@ -64,13 +64,13 @@ ELF file into memory.
 /* Section Header type bits */
 #define SHT_PROGBITS 1
 #define SHT_SYMTAB 2
-#define	SHT_NOBITS 8
+#define SHT_NOBITS 8
 #define SHT_REL 9
 
 /* Section Header flag bits */
 #define SHF_WRITE 1
 #define SHF_ALLOC 2
-#define SHF_EXECINSTR  4
+#define SHF_EXECINSTR 4
 
 /**/
 #define ELF_PRINT_PROGRAM_HEADERS 1
@@ -198,9 +198,13 @@ bool elf_vaddrInProgramHeader(void *elfFile, uint16_t ph, uint32_t vaddr);
  * @param min Pointer to return value of the minimum
  * @param max Pointer to return value of the maximum
  *
- * \return true on success. false on failure, if for example, it is an invalid ELF file
+ * \return true on success. false on failure, if for example, it is an invalid
+ * ELF file
  */
-bool elf_getMemoryBounds(void *elfFile, bool phys, uint32_t *min, uint32_t *max);
+bool elf_getMemoryBounds(void *elfFile,
+                         bool phys,
+                         uint32_t *min,
+                         uint32_t *max);
 
 /**
  * Find the entry point of an ELF file.
@@ -215,7 +219,8 @@ uint32_t elf_getEntryPoint(void *elfFile);
  * Load an ELF file into memory
  *
  * @param elfFile Pointer to a valid ELF file
- * @param phys If true load using the physical address, otherwise using the virtual addresses
+ * @param phys If true load using the physical address, otherwise using the
+ * virtual addresses
  *
  * \return true on success, false on failure.
  *
@@ -258,9 +263,13 @@ uint32_t elf_getSectionFlags(void *elfFile, int i);
 uint32_t elf_getSectionType(void *elfFile, int i);
 
 void *elf_getSection(void *elfFile, int i);
-void elf_getProgramHeaderInfo(void *elfFile, uint16_t ph, uint32_t *p_vaddr,
-			      uint32_t *p_paddr, uint32_t *p_filesz,
-			      uint32_t *p_offset, uint32_t *p_memsz);
+void elf_getProgramHeaderInfo(void *elfFile,
+                              uint16_t ph,
+                              uint32_t *p_vaddr,
+                              uint32_t *p_paddr,
+                              uint32_t *p_filesz,
+                              uint32_t *p_offset,
+                              uint32_t *p_memsz);
 
 
 /**
diff --git a/loader/include/elf/elf32.h b/loader/include/elf/elf32.h
index ea772afa..020a7013 100644
--- a/loader/include/elf/elf32.h
+++ b/loader/include/elf/elf32.h
@@ -12,64 +12,64 @@
  * File header
  */
 struct Elf32_Header {
-	unsigned char   e_ident[16];
-	uint16_t        e_type;	/* Relocatable=1, Executable=2 (+ some
-				 * more ..) */
-	uint16_t        e_machine;	/* Target architecture: MIPS=8 */
-	uint32_t        e_version;	/* Elf version (should be 1) */
-	uint32_t        e_entry;	/* Code entry point */
-	uint32_t        e_phoff;	/* Program header table */
-	uint32_t        e_shoff;	/* Section header table */
-	uint32_t        e_flags;	/* Flags */
-	uint16_t        e_ehsize;	/* ELF header size */
-	uint16_t        e_phentsize;	/* Size of one program segment
-					 * header */
-	uint16_t        e_phnum;	/* Number of program segment
-					 * headers */
-	uint16_t        e_shentsize;	/* Size of one section header */
-	uint16_t        e_shnum;	/* Number of section headers */
-	uint16_t        e_shstrndx;	/* Section header index of the
-					 * string table for section header
-					 * * names */
+    unsigned char e_ident[16];
+    uint16_t e_type;      /* Relocatable=1, Executable=2 (+ some
+                           * more ..) */
+    uint16_t e_machine;   /* Target architecture: MIPS=8 */
+    uint32_t e_version;   /* Elf version (should be 1) */
+    uint32_t e_entry;     /* Code entry point */
+    uint32_t e_phoff;     /* Program header table */
+    uint32_t e_shoff;     /* Section header table */
+    uint32_t e_flags;     /* Flags */
+    uint16_t e_ehsize;    /* ELF header size */
+    uint16_t e_phentsize; /* Size of one program segment
+                           * header */
+    uint16_t e_phnum;     /* Number of program segment
+                           * headers */
+    uint16_t e_shentsize; /* Size of one section header */
+    uint16_t e_shnum;     /* Number of section headers */
+    uint16_t e_shstrndx;  /* Section header index of the
+                           * string table for section header
+                           * * names */
 };
 
 /*
  * Section header
  */
 struct Elf32_Shdr {
-	uint32_t        sh_name;
-	uint32_t        sh_type;
-	uint32_t        sh_flags;
-	uint32_t        sh_addr;
-	uint32_t        sh_offset;
-	uint32_t        sh_size;
-	uint32_t        sh_link;
-	uint32_t        sh_info;
-	uint32_t        sh_addralign;
-	uint32_t        sh_entsize;
+    uint32_t sh_name;
+    uint32_t sh_type;
+    uint32_t sh_flags;
+    uint32_t sh_addr;
+    uint32_t sh_offset;
+    uint32_t sh_size;
+    uint32_t sh_link;
+    uint32_t sh_info;
+    uint32_t sh_addralign;
+    uint32_t sh_entsize;
 };
 
 /*
  * Program header
  */
 struct Elf32_Phdr {
-	uint32_t p_type;	/* Segment type: Loadable segment = 1 */
-	uint32_t p_offset;	/* Offset of segment in file */
-	uint32_t p_vaddr;	/* Reqd virtual address of segment
-					 * when loading */
-	uint32_t p_paddr;	/* Reqd physical address of
-					 * segment (ignore) */
-	uint32_t p_filesz;	/* How many bytes this segment
-					 * occupies in file */
-	uint32_t p_memsz;	/* How many bytes this segment
-					 * should occupy in * memory (when
-					 * * loading, expand the segment
-					 * by * concatenating enough zero
-					 * bytes to it) */
-	uint32_t p_flags;	/* Flags: logical "or" of PF_
-					 * constants below */
-	uint32_t p_align;	/* Reqd alignment of segment in
-					 * memory */
+    uint32_t p_type;   /* Segment type: Loadable segment = 1 */
+    uint32_t p_offset; /* Offset of segment in file */
+    uint32_t p_vaddr;  /* Reqd virtual address of segment
+                        * when loading */
+    uint32_t p_paddr;  /* Reqd physical address of
+                        * segment (ignore) */
+    uint32_t p_filesz; /* How many bytes this segment
+                        * occupies in file */
+    uint32_t p_memsz;  /* How many bytes this segment
+                        * should occupy in * memory (when
+                        * * loading, expand the segment
+                        * by * concatenating enough zero
+                        * bytes to it) */
+    uint32_t p_flags;  /* Flags: logical "or" of PF_
+                        * constants below */
+    uint32_t p_align;  /* Reqd alignment of segment in
+                        * memory */
 };
 
 int elf32_checkFile(struct Elf32_Header *file);
@@ -78,24 +78,25 @@ unsigned elf32_getNumSections(struct Elf32_Header *file);
 char *elf32_getStringTable(struct Elf32_Header *file);
 char *elf32_getSegmentStringTable(struct Elf32_Header *file);
 
-static inline struct Elf32_Shdr *
-elf32_getSectionTable(struct Elf32_Header *file)
+static inline struct Elf32_Shdr *elf32_getSectionTable(
+    struct Elf32_Header *file)
 {
-	/* Cast heaven! */
-	return (struct Elf32_Shdr *) (uintptr_t) (((uintptr_t) file) + file->e_shoff);
+    /* Cast heaven! */
+    return (struct Elf32_Shdr *) (uintptr_t) (((uintptr_t) file) +
+                                              file->e_shoff);
 }
 
 /* accessor functions */
-static inline uint32_t
-elf32_getSectionType(struct Elf32_Header *file, uint16_t s)
+static inline uint32_t elf32_getSectionType(struct Elf32_Header *file,
+                                            uint16_t s)
 {
-	return elf32_getSectionTable(file)[s].sh_type;
+    return elf32_getSectionTable(file)[s].sh_type;
 }
 
-static inline uint32_t
-elf32_getSectionFlags(struct Elf32_Header *file, uint16_t s)
+static inline uint32_t elf32_getSectionFlags(struct Elf32_Header *file,
+                                             uint16_t s)
 {
-	return elf32_getSectionTable(file)[s].sh_flags;
+    return elf32_getSectionTable(file)[s].sh_flags;
 }
 
 char *elf32_getSectionName(struct Elf32_Header *file, int i);
@@ -103,66 +104,72 @@ uint32_t elf32_getSectionSize(struct Elf32_Header *file, int i);
 uint32_t elf32_getSectionAddr(struct Elf32_Header *elfFile, int i);
 void *elf32_getSection(struct Elf32_Header *file, int i);
 void *elf32_getSectionNamed(struct Elf32_Header *file, char *str);
-int elf32_getSegmentType (struct Elf32_Header *file, int segment);
-void elf32_getSegmentInfo(struct Elf32_Header *file, int segment, uint64_t *p_vaddr,
-			  uint64_t *p_paddr, uint64_t *p_filesz,
-			  uint64_t *p_offset, uint64_t *p_memsz);
+int elf32_getSegmentType(struct Elf32_Header *file, int segment);
+void elf32_getSegmentInfo(struct Elf32_Header *file,
+                          int segment,
+                          uint64_t *p_vaddr,
+                          uint64_t *p_paddr,
+                          uint64_t *p_filesz,
+                          uint64_t *p_offset,
+                          uint64_t *p_memsz);
 
 
 
-uint32_t elf32_getEntryPoint (struct Elf32_Header *file);
+uint32_t elf32_getEntryPoint(struct Elf32_Header *file);
 
 /* Program header functions */
 uint16_t elf32_getNumProgramHeaders(struct Elf32_Header *file);
 
-static inline struct Elf32_Phdr *
-elf32_getProgramHeaderTable(struct Elf32_Header *file)
+static inline struct Elf32_Phdr *elf32_getProgramHeaderTable(
+    struct Elf32_Header *file)
 {
-	/* Cast heaven! */
-	return (struct Elf32_Phdr*) (uintptr_t) (((uintptr_t) file) + file->e_phoff);
+    /* Cast heaven! */
+    return (struct Elf32_Phdr *) (uintptr_t) (((uintptr_t) file) +
+                                              file->e_phoff);
 }
 
 /* accessor functions */
-static inline uint32_t
-elf32_getProgramHeaderFlags(struct Elf32_Header *file, uint16_t ph)
+static inline uint32_t elf32_getProgramHeaderFlags(struct Elf32_Header *file,
+                                                   uint16_t ph)
 {
-	return elf32_getProgramHeaderTable(file)[ph].p_flags;
+    return elf32_getProgramHeaderTable(file)[ph].p_flags;
 }
 
-static inline uint32_t
-elf32_getProgramHeaderType(struct Elf32_Header *file, uint16_t ph)
+static inline uint32_t elf32_getProgramHeaderType(struct Elf32_Header *file,
+                                                  uint16_t ph)
 {
-	return elf32_getProgramHeaderTable(file)[ph].p_type;
+    return elf32_getProgramHeaderTable(file)[ph].p_type;
 }
 
-static inline uint32_t
-elf32_getProgramHeaderFileSize(struct Elf32_Header *file, uint16_t ph)
+static inline uint32_t elf32_getProgramHeaderFileSize(struct Elf32_Header *file,
+                                                      uint16_t ph)
 {
-	return elf32_getProgramHeaderTable(file)[ph].p_filesz;
+    return elf32_getProgramHeaderTable(file)[ph].p_filesz;
 }
 
-static inline uint32_t
-elf32_getProgramHeaderMemorySize(struct Elf32_Header *file, uint16_t ph)
+static inline uint32_t elf32_getProgramHeaderMemorySize(
+    struct Elf32_Header *file,
+    uint16_t ph)
 {
-	return elf32_getProgramHeaderTable(file)[ph].p_memsz;
+    return elf32_getProgramHeaderTable(file)[ph].p_memsz;
 }
 
-static inline uint32_t
-elf32_getProgramHeaderVaddr(struct Elf32_Header *file, uint16_t ph)
+static inline uint32_t elf32_getProgramHeaderVaddr(struct Elf32_Header *file,
+                                                   uint16_t ph)
 {
-	return elf32_getProgramHeaderTable(file)[ph].p_vaddr;
+    return elf32_getProgramHeaderTable(file)[ph].p_vaddr;
 }
 
-static inline uint32_t
-elf32_getProgramHeaderPaddr(struct Elf32_Header *file, uint16_t ph)
+static inline uint32_t elf32_getProgramHeaderPaddr(struct Elf32_Header *file,
+                                                   uint16_t ph)
 {
-	return elf32_getProgramHeaderTable(file)[ph].p_paddr;
+    return elf32_getProgramHeaderTable(file)[ph].p_paddr;
 }
 
-static inline uint32_t
-elf32_getProgramHeaderOffset(struct Elf32_Header *file, uint16_t ph)
+static inline uint32_t elf32_getProgramHeaderOffset(struct Elf32_Header *file,
+                                                    uint16_t ph)
 {
-	return elf32_getProgramHeaderTable(file)[ph].p_offset;
+    return elf32_getProgramHeaderTable(file)[ph].p_offset;
 }
 
 #endif /* __ELF_ELF_32_H__ */
diff --git a/platform/bitops.c b/platform/bitops.c
index 699e1a85..02bceff7 100644
--- a/platform/bitops.c
+++ b/platform/bitops.c
@@ -11,78 +11,77 @@
 /* Atomic ops */
 void atomic_set(atomic_t *atom, atomic_t newval)
 {
-	__asm__ __volatile__("mov r1, %0" : : "r"(newval));
-	__asm__ __volatile__("atomic_try: ldrex r0, [%0]\n"
-	                     "strex r0, r1, [%0]\n"
-	                     "cmp r0, #0"
-	                     :
-	                     : "r"(atom));
-	__asm__ __volatile__("bne atomic_try");
+    __asm__ __volatile__("mov r1, %0" : : "r"(newval));
+    __asm__ __volatile__(
+        "atomic_try: ldrex r0, [%0]\n"
+        "strex r0, r1, [%0]\n"
+        "cmp r0, #0"
+        :
+        : "r"(atom));
+    __asm__ __volatile__("bne atomic_try");
 }
 
 uint32_t atomic_get(atomic_t *atom)
 {
-	atomic_t result;
+    atomic_t result;
 
-	__asm__ __volatile__("ldrex r0, [%0]"
-	                     :
-	                     : "r"(atom));
-	__asm__ __volatile__("clrex");
-	__asm__ __volatile__("mov %0, r0" : "=r"(result));
+    __asm__ __volatile__("ldrex r0, [%0]" : : "r"(atom));
+    __asm__ __volatile__("clrex");
+    __asm__ __volatile__("mov %0, r0" : "=r"(result));
 
-	return result;
+    return result;
 }
 
-#else	/* !CONFIG_SMP */
+#else /* !CONFIG_SMP */
 
 void atomic_set(atomic_t *atom, atomic_t newval)
 {
-	*atom = newval;
+    *atom = newval;
 }
 
 uint32_t atomic_get(atomic_t *atom)
 {
-	return *atom;
+    return *atom;
 }
 
-#endif	/* CONFIG_SMP */
+#endif /* CONFIG_SMP */
 
 uint32_t test_and_set_word(uint32_t *word)
 {
-	register int result = 1;
-
-	__asm__ __volatile__(
-	    "mov r1, #1\n"
-	    "mov r2, %[word]\n"
-	    "ldrex r0, [r2]\n"	/* Load value [r2] */
-	    "cmp r0, #0\n"	/* Checking is word set to 1 */
-
-	    "itt eq\n"
-	    "strexeq r0, r1, [r2]\n"
-	    "moveq %[result], r0\n"
-	    : [result] "=r"(result)
-	    : [word] "r"(word)
-	    : "r0", "r1", "r2");
-
-	return result == 0;
+    register int result = 1;
+
+    __asm__ __volatile__(
+        "mov r1, #1\n"
+        "mov r2, %[word]\n"
+        "ldrex r0, [r2]\n" /* Load value [r2] */
+        "cmp r0, #0\n"     /* Checking is word set to 1 */
+
+        "itt eq\n"
+        "strexeq r0, r1, [r2]\n"
+        "moveq %[result], r0\n"
+        : [result] "=r"(result)
+        : [word] "r"(word)
+        : "r0", "r1", "r2");
+
+    return result == 0;
 }
 
 uint32_t test_and_set_bit(uint32_t *word, int bitmask)
 {
-	register int result = 1;
-
-	__asm__ __volatile__(
-	    "mov r2, %[word]\n"
-	    "ldrex r0, [r2]\n"		/* Load value [r2] */
-	    "tst r0, %[bitmask]\n"	/* Compare value with bitmask */
-
-	    "ittt eq\n"
-	    "orreq r1, r0, %[bitmask]\n"	/* Set bit: r1 = r0 | bitmask */
-	    "strexeq r0, r1, [r2]\n"		/* Write value back to [r2] */
-	    "moveq %[result], r0\n"
-	    : [result] "=r"(result)
-	    : [word] "r"(word), [bitmask] "r"(bitmask)
-	    : "r0", "r1", "r2");
-
-	return result == 0;
+    register int result = 1;
+
+    __asm__ __volatile__(
+        "mov r2, %[word]\n"
+        "ldrex r0, [r2]\n"     /* Load value [r2] */
+        "tst r0, %[bitmask]\n" /* Compare value with bitmask */
+
+        "ittt eq\n"
+        "orreq r1, r0, %[bitmask]\n" /* Set bit: r1 = r0 | bitmask */
+        "strexeq r0, r1, [r2]\n"     /* Write value back to [r2] */
+        "moveq %[result], r0\n"
+        : [result] "=r"(result)
+        : [word] "r"(word), [bitmask] "r"(bitmask)
+        : "r0", "r1", "r2");
+
+    return result == 0;
 }
diff --git a/platform/breakpoint-hard.c b/platform/breakpoint-hard.c
index 9ad7192a..a9854748 100644
--- a/platform/breakpoint-hard.c
+++ b/platform/breakpoint-hard.c
@@ -7,15 +7,15 @@
 #error __FILE__ " is the part of KProbes implementation."
 #endif
 
-#include <platform/hw_debug.h>
-#include <platform/cortex_m.h>
-#include <platform/breakpoint.h>
+#include <debug.h>
 #include <platform/breakpoint-hard.h>
+#include <platform/breakpoint.h>
+#include <platform/cortex_m.h>
+#include <platform/hw_debug.h>
 #include <types.h>
-#include <debug.h>
 
 #define HW_BKPT_NULL_ID FPB_MAX_COMP
-#define IS_UPPER_HALFWORLD(addr)	(addr & 0x2)
+#define IS_UPPER_HALFWORLD(addr) (addr & 0x2)
 
 /* Runtime FPB availability flag.
  * QEMU netduinoplus2 does not emulate FPB hardware.
@@ -36,13 +36,13 @@ static void hard_breakpoint_release(struct breakpoint *b);
 
 static int get_avail_hard_breakpoint(void)
 {
-	int i;
-	/* Use runtime-detected comparator count */
-	for (i = 0; i < fpb_num_comp; i++) {
-		if (hard_breakpoints[i] == -1)
-			return i;
-	}
-	return -1;
+    int i;
+    /* Use runtime-detected comparator count */
+    for (i = 0; i < fpb_num_comp; i++) {
+        if (hard_breakpoints[i] == -1)
+            return i;
+    }
+    return -1;
 }
 
 /*
@@ -59,136 +59,135 @@ static int get_avail_hard_breakpoint(void)
  */
 static int detect_fpb_hardware(void)
 {
-	uint32_t ctrl_val;
-	int num_code;
+    uint32_t ctrl_val;
+    int num_code;
 
-	/* Try to enable FPB */
-	*FPB_CTRL = FPB_CTRL_KEY | FPB_CTRL_ENABLE;
+    /* Try to enable FPB */
+    *FPB_CTRL = FPB_CTRL_KEY | FPB_CTRL_ENABLE;
 
-	/* Read back and check if enable bit is set */
-	ctrl_val = *FPB_CTRL;
+    /* Read back and check if enable bit is set */
+    ctrl_val = *FPB_CTRL;
 
-	if (!(ctrl_val & FPB_CTRL_ENABLE))
-		return 0;
+    if (!(ctrl_val & FPB_CTRL_ENABLE))
+        return 0;
 
-	/* Extract NUM_CODE from FP_CTRL per ARMv7-M spec:
-	 * NUM_CODE1 (bits [7:4]) + NUM_CODE2 (bits [14:12]) shifted
-	 */
-	num_code = ((ctrl_val >> 4) & 0xF) |
-	           (((ctrl_val >> 12) & 0x7) << 4);
+    /* Extract NUM_CODE from FP_CTRL per ARMv7-M spec:
+     * NUM_CODE1 (bits [7:4]) + NUM_CODE2 (bits [14:12]) shifted
+     */
+    num_code = ((ctrl_val >> 4) & 0xF) | (((ctrl_val >> 12) & 0x7) << 4);
 
-	/* Cap at FPB_MAX_COMP to prevent array overflow */
-	if (num_code > FPB_MAX_COMP)
-		num_code = FPB_MAX_COMP;
+    /* Cap at FPB_MAX_COMP to prevent array overflow */
+    if (num_code > FPB_MAX_COMP)
+        num_code = FPB_MAX_COMP;
 
-	return num_code;
+    return num_code;
 }
 
 void hard_breakpoint_pool_init(void)
 {
-	int i;
-
-	/* Enable DebugMon exception - required for BOTH hardware and software
-	 * breakpoints. Without this, BKPT instructions cause HardFault.
-	 * Must be done before early return for FPB-absent case.
-	 */
-	*DCB_DEMCR |= DCB_DEMCR_TRCENA | DCB_DEMCR_MON_EN;
-
-	/* Clear debug status bits */
-	*SCB_HFSR = SCB_HFSR_DEBUGEVT;
-	*SCB_DFSR = SCB_DFSR_BKPT;
-	*SCB_DFSR = SCB_DFSR_HALTED;
-	*SCB_DFSR = SCB_DFSR_DWTTRAP;
-
-	/* Detect FPB hardware and get comparator count */
-	fpb_num_comp = detect_fpb_hardware();
-	fpb_available = (fpb_num_comp > 0);
-
-	if (!fpb_available) {
-		dbg_printf(DL_KDB,
-		           "FPB: Hardware not available (QEMU?), "
-		           "using software breakpoints only\n");
-		return;
-	}
-
-	dbg_printf(DL_KDB, "FPB: Hardware detected, %d comparators\n",
-	           fpb_num_comp);
-
-	/* Initialize only the detected number of comparators */
-	for (i = 0; i < fpb_num_comp; i++) {
-		hard_breakpoints[i] = -1;
-		*(FPB_COMP + i) = 0;
-	}
-
-	enable_all_hard_breakpoints();
-
-	/* Memory barriers to ensure FPB config is visible before use.
-	 * ARM recommends DSB+ISB after changing breakpoint state.
-	 */
-	__DSB();
-	__ISB();
+    int i;
+
+    /* Enable DebugMon exception - required for BOTH hardware and software
+     * breakpoints. Without this, BKPT instructions cause HardFault.
+     * Must be done before early return for FPB-absent case.
+     */
+    *DCB_DEMCR |= DCB_DEMCR_TRCENA | DCB_DEMCR_MON_EN;
+
+    /* Clear debug status bits */
+    *SCB_HFSR = SCB_HFSR_DEBUGEVT;
+    *SCB_DFSR = SCB_DFSR_BKPT;
+    *SCB_DFSR = SCB_DFSR_HALTED;
+    *SCB_DFSR = SCB_DFSR_DWTTRAP;
+
+    /* Detect FPB hardware and get comparator count */
+    fpb_num_comp = detect_fpb_hardware();
+    fpb_available = (fpb_num_comp > 0);
+
+    if (!fpb_available) {
+        dbg_printf(DL_KDB,
+                   "FPB: Hardware not available (QEMU?), "
+                   "using software breakpoints only\n");
+        return;
+    }
+
+    dbg_printf(DL_KDB, "FPB: Hardware detected, %d comparators\n",
+               fpb_num_comp);
+
+    /* Initialize only the detected number of comparators */
+    for (i = 0; i < fpb_num_comp; i++) {
+        hard_breakpoints[i] = -1;
+        *(FPB_COMP + i) = 0;
+    }
+
+    enable_all_hard_breakpoints();
+
+    /* Memory barriers to ensure FPB config is visible before use.
+     * ARM recommends DSB+ISB after changing breakpoint state.
+     */
+    __DSB();
+    __ISB();
 }
 
 struct breakpoint *hard_breakpoint_config(uint32_t addr, struct breakpoint *b)
 {
-	/* If FPB hardware not available, fall back to soft breakpoints */
-	if (!fpb_available)
-		return NULL;
-
-	if (breakpoint_type_by_addr(addr) == BKPT_HARD) {
-		int _hard_breakpoint_id = get_avail_hard_breakpoint();
-		int breakpoint_id = get_breakpoint_id(b);
-
-		if (breakpoint_id >= 0 && _hard_breakpoint_id >= 0) {
-			hard_breakpoints[_hard_breakpoint_id] = breakpoint_id;
-			b->type = BKPT_HARD;
-			b->addr = addr;
-			b->hard_breakpoint_id = _hard_breakpoint_id;
-			b->enable = hard_breakpoint_enable;
-			b->disable = hard_breakpoint_disable;
-			b->release = hard_breakpoint_release;
-			return b;
-		}
-	}
-
-	return NULL;
+    /* If FPB hardware not available, fall back to soft breakpoints */
+    if (!fpb_available)
+        return NULL;
+
+    if (breakpoint_type_by_addr(addr) == BKPT_HARD) {
+        int _hard_breakpoint_id = get_avail_hard_breakpoint();
+        int breakpoint_id = get_breakpoint_id(b);
+
+        if (breakpoint_id >= 0 && _hard_breakpoint_id >= 0) {
+            hard_breakpoints[_hard_breakpoint_id] = breakpoint_id;
+            b->type = BKPT_HARD;
+            b->addr = addr;
+            b->hard_breakpoint_id = _hard_breakpoint_id;
+            b->enable = hard_breakpoint_enable;
+            b->disable = hard_breakpoint_disable;
+            b->release = hard_breakpoint_release;
+            return b;
+        }
+    }
+
+    return NULL;
 }
 
 static void hard_breakpoint_enable(struct breakpoint *b)
 {
-	uint32_t addr = b->addr;
-
-	if (IS_UPPER_HALFWORLD(addr)) {
-		*(FPB_COMP + b->hard_breakpoint_id) =
-			FPB_COMP_REPLACE_UPPER |
-			(addr & FPB_COMP_ADDR_MASK) | FPB_COMP_ENABLE;
-	} else {
-		*(FPB_COMP + b->hard_breakpoint_id) =
-			FPB_COMP_REPLACE_LOWER |
-			(addr & FPB_COMP_ADDR_MASK) | FPB_COMP_ENABLE;
-	}
-
-	/* Ensure breakpoint is active before continuing execution */
-	__DSB();
-	__ISB();
+    uint32_t addr = b->addr;
+
+    if (IS_UPPER_HALFWORLD(addr)) {
+        *(FPB_COMP + b->hard_breakpoint_id) = FPB_COMP_REPLACE_UPPER |
+                                              (addr & FPB_COMP_ADDR_MASK) |
+                                              FPB_COMP_ENABLE;
+    } else {
+        *(FPB_COMP + b->hard_breakpoint_id) = FPB_COMP_REPLACE_LOWER |
+                                              (addr & FPB_COMP_ADDR_MASK) |
+                                              FPB_COMP_ENABLE;
+    }
+
+    /* Ensure breakpoint is active before continuing execution */
+    __DSB();
+    __ISB();
 }
 
 static void hard_breakpoint_disable(struct breakpoint *b)
 {
-	*(FPB_COMP + b->hard_breakpoint_id) &= ~FPB_COMP_ENABLE;
+    *(FPB_COMP + b->hard_breakpoint_id) &= ~FPB_COMP_ENABLE;
 
-	/* Ensure breakpoint is disabled before continuing */
-	__DSB();
-	__ISB();
+    /* Ensure breakpoint is disabled before continuing */
+    __DSB();
+    __ISB();
 }
 
 static void hard_breakpoint_release(struct breakpoint *b)
 {
-	*(FPB_COMP + b->hard_breakpoint_id) &= ~FPB_COMP_ENABLE;
-	hard_breakpoints[b->hard_breakpoint_id] = -1;
-	b->type = BKPT_NONE;
+    *(FPB_COMP + b->hard_breakpoint_id) &= ~FPB_COMP_ENABLE;
+    hard_breakpoints[b->hard_breakpoint_id] = -1;
+    b->type = BKPT_NONE;
 
-	/* Ensure breakpoint is released before continuing */
-	__DSB();
-	__ISB();
+    /* Ensure breakpoint is released before continuing */
+    __DSB();
+    __ISB();
 }
diff --git a/platform/breakpoint-soft.c b/platform/breakpoint-soft.c
index fa66128b..28d54c65 100644
--- a/platform/breakpoint-soft.c
+++ b/platform/breakpoint-soft.c
@@ -7,21 +7,21 @@
 #error __FILE__ " is the part of KProbes implementation."
 #endif
 
-#include <platform/cortex_m.h>
-#include <platform/breakpoint.h>
 #include <platform/breakpoint-soft.h>
+#include <platform/breakpoint.h>
+#include <platform/cortex_m.h>
 #include <types.h>
 
 static inline void insert_bkpt(struct breakpoint *b)
 {
-	uint16_t breakpoint_instr = 0xbe11;	/* ARM BKPT instruction */
+    uint16_t breakpoint_instr = 0xbe11; /* ARM BKPT instruction */
 
-	*(volatile uint16_t *) b->addr = breakpoint_instr;
+    *(volatile uint16_t *) b->addr = breakpoint_instr;
 }
 
 static inline void delete_bkpt(struct breakpoint *b)
 {
-	*(volatile uint16_t *) b->addr = b->back_instr;
+    *(volatile uint16_t *) b->addr = b->back_instr;
 }
 
 static void soft_breakpoint_enable(struct breakpoint *b);
@@ -30,36 +30,36 @@ static void soft_breakpoint_release(struct breakpoint *b);
 
 void soft_breakpoint_pool_init(void)
 {
-	/* Nothing to do. */
-	return;
+    /* Nothing to do. */
+    return;
 }
 
 struct breakpoint *soft_breakpoint_config(uint32_t addr, struct breakpoint *b)
 {
-	if (breakpoint_type_by_addr(addr) == BKPT_SOFT) {
-		b->type = BKPT_SOFT;
-		b->addr = addr;
-		b->back_instr = *(uint16_t *) addr;
-		b->enable = soft_breakpoint_enable;
-		b->disable = soft_breakpoint_disable;
-		b->release = soft_breakpoint_release;
+    if (breakpoint_type_by_addr(addr) == BKPT_SOFT) {
+        b->type = BKPT_SOFT;
+        b->addr = addr;
+        b->back_instr = *(uint16_t *) addr;
+        b->enable = soft_breakpoint_enable;
+        b->disable = soft_breakpoint_disable;
+        b->release = soft_breakpoint_release;
 
-		return b;
-	}
-	return NULL;
+        return b;
+    }
+    return NULL;
 }
 
 static void soft_breakpoint_enable(struct breakpoint *b)
 {
-	insert_bkpt(b);
+    insert_bkpt(b);
 }
 
 static void soft_breakpoint_disable(struct breakpoint *b)
 {
-	delete_bkpt(b);
+    delete_bkpt(b);
 }
 
 static void soft_breakpoint_release(struct breakpoint *b)
 {
-	b->type = BKPT_NONE;
+    b->type = BKPT_NONE;
 }
diff --git a/platform/breakpoint.c b/platform/breakpoint.c
index 66106b45..e16d046c 100644
--- a/platform/breakpoint.c
+++ b/platform/breakpoint.c
@@ -2,83 +2,83 @@
 #error __FILE__ " is the part of KProbes implementation."
 #endif
 
-#include <platform/irq.h>
-#include <platform/hw_debug.h>
-#include <platform/cortex_m.h>
 #include <platform/breakpoint.h>
+
 #include <platform/breakpoint-hard.h>
 #include <platform/breakpoint-soft.h>
+#include <platform/cortex_m.h>
+#include <platform/hw_debug.h>
+#include <platform/irq.h>
 
 static struct breakpoint breakpoints[BKPT_MAX_NUM];
 
 static struct breakpoint *breakpoint_config(int id, uint32_t addr)
 {
-	uint16_t t;
+    uint16_t t;
 
-	t = breakpoint_type_by_addr(addr);
+    t = breakpoint_type_by_addr(addr);
 
-	if (t == BKPT_HARD) {
-		return hard_breakpoint_config(addr, &breakpoints[id]);
-	} else if (t == BKPT_SOFT) {
-		return soft_breakpoint_config(addr, &breakpoints[id]);
-	}
+    if (t == BKPT_HARD) {
+        return hard_breakpoint_config(addr, &breakpoints[id]);
+    } else if (t == BKPT_SOFT) {
+        return soft_breakpoint_config(addr, &breakpoints[id]);
+    }
 
-	return NULL;
+    return NULL;
 }
 
 static struct breakpoint *get_avail_breakpoint(uint32_t addr)
 {
-	int i;
+    int i;
 
-	for (i = 0; i < BKPT_MAX_NUM; i++) {
-		if (breakpoints[i].type == BKPT_NONE)
-			return breakpoint_config(i, addr);
-	}
-	return NULL;
+    for (i = 0; i < BKPT_MAX_NUM; i++) {
+        if (breakpoints[i].type == BKPT_NONE)
+            return breakpoint_config(i, addr);
+    }
+    return NULL;
 }
 
 int get_breakpoint_id(struct breakpoint *b)
 {
-	uint32_t addr = (uint32_t)b;
-	uint32_t head_addr = (uint32_t)breakpoints;
+    uint32_t addr = (uint32_t) b;
+    uint32_t head_addr = (uint32_t) breakpoints;
 
-	if ((addr >= head_addr) &&
-	    (addr <= (uint32_t)&breakpoints[BKPT_MAX_NUM]))
-		return (addr - head_addr) / sizeof(struct breakpoint);
+    if ((addr >= head_addr) && (addr <= (uint32_t) &breakpoints[BKPT_MAX_NUM]))
+        return (addr - head_addr) / sizeof(struct breakpoint);
 
-	return -1;
+    return -1;
 }
 
 void breakpoint_pool_init(void)
 {
-	int i;
+    int i;
 
-	for (i = 0; i < FPB_MAX_COMP; i++) {
-		breakpoints[i].type = BKPT_NONE;
-		breakpoints[i].addr = 0;
-		breakpoints[i].raw_data = 0;
-	}
+    for (i = 0; i < FPB_MAX_COMP; i++) {
+        breakpoints[i].type = BKPT_NONE;
+        breakpoints[i].addr = 0;
+        breakpoints[i].raw_data = 0;
+    }
 
-	hard_breakpoint_pool_init();
-	soft_breakpoint_pool_init();
+    hard_breakpoint_pool_init();
+    soft_breakpoint_pool_init();
 }
 
 struct breakpoint *breakpoint_install(uint32_t addr)
 {
-	return get_avail_breakpoint(addr);
+    return get_avail_breakpoint(addr);
 }
 
 void breakpoint_uninstall(struct breakpoint *b)
 {
-	b->release(b);
+    b->release(b);
 }
 
 void enable_breakpoint(struct breakpoint *b)
 {
-	b->enable(b);
+    b->enable(b);
 }
 
 void disable_breakpoint(struct breakpoint *b)
 {
-	b->disable(b);
+    b->disable(b);
 }
diff --git a/platform/debug_device.c b/platform/debug_device.c
index 03c5e0df..73e05902 100644
--- a/platform/debug_device.c
+++ b/platform/debug_device.c
@@ -4,9 +4,10 @@
  */
 
 #include <types.h>
+
 #include <errno.h>
-#include <lib/stdio.h>
 #include <init_hook.h>
+#include <lib/stdio.h>
 #include <platform/debug_device.h>
 #ifdef CONFIG_DEBUG_DEV_UART
 #include <platform/debug_uart.h>
@@ -21,24 +22,22 @@ static dbg_dev_t *cur_dev = &dbg_dev[0];
 
 static uint8_t default_getchar(void)
 {
-	return (EOF);
+    return (EOF);
 }
 
 static void default_putchar(uint8_t chr)
 {
-	chr = 0;
+    chr = 0;
 }
 
-static void default_start_panic(void)
-{
-}
+static void default_start_panic(void) {}
 
 /*
  * Receive a character from debug port
  */
 uint8_t dbg_getchar(void)
 {
-	return ((*cur_dev->getchar)());
+    return ((*cur_dev->getchar)());
 }
 
 /*
@@ -46,7 +45,7 @@ uint8_t dbg_getchar(void)
  */
 void dbg_putchar(uint8_t chr)
 {
-	(*cur_dev->putchar)(chr);
+    (*cur_dev->putchar)(chr);
 }
 
 /*
@@ -55,9 +54,9 @@ void dbg_putchar(uint8_t chr)
  */
 void dbg_start_panic(void)
 {
-	if (!cur_dev || !cur_dev->start_panic)
-		return;
-	(*cur_dev->start_panic)();
+    if (!cur_dev || !cur_dev->start_panic)
+        return;
+    (*cur_dev->start_panic)();
 }
 
 /*
@@ -65,22 +64,22 @@ void dbg_start_panic(void)
  */
 static void dbg_device_init(void)
 {
-	int i;
+    int i;
 
-	for (i = 0; i < (DBG_DEV_MAX - 1); i++) {
-		dbg_dev_t *pdev = &dbg_dev[i];
-		pdev->dev_id = DBG_DEV_MAX;
-		pdev->getchar = default_getchar;
-		pdev->putchar = default_putchar;
-		pdev->start_panic = default_start_panic;
-	}
+    for (i = 0; i < (DBG_DEV_MAX - 1); i++) {
+        dbg_dev_t *pdev = &dbg_dev[i];
+        pdev->dev_id = DBG_DEV_MAX;
+        pdev->getchar = default_getchar;
+        pdev->putchar = default_putchar;
+        pdev->start_panic = default_start_panic;
+    }
 
 #ifdef CONFIG_DEBUG_DEV_UART
-	dbg_uart_init();
+    dbg_uart_init();
 #endif
 
 #ifdef CONFIG_DEBUG_DEV_RAM
-	dbg_ram_init();
+    dbg_ram_init();
 #endif
 }
 
@@ -89,49 +88,46 @@ static void dbg_device_init(void)
  */
 int32_t dbg_register_device(dbg_dev_t *device)
 {
-	dbg_dev_t *pdev;
-	if (!device)
-		return -EINVAL;
+    dbg_dev_t *pdev;
+    if (!device)
+        return -EINVAL;
 
-	if (device->dev_id >= DBG_DEV_MAX)
-		return -EINVAL;
+    if (device->dev_id >= DBG_DEV_MAX)
+        return -EINVAL;
 
-	pdev = &dbg_dev[device->dev_id];
-	pdev->dev_id = device->dev_id;
-	pdev->getchar = device->getchar;
-	pdev->putchar = device->putchar;
-	pdev->start_panic = device->start_panic;
+    pdev = &dbg_dev[device->dev_id];
+    pdev->dev_id = device->dev_id;
+    pdev->getchar = device->getchar;
+    pdev->putchar = device->putchar;
+    pdev->start_panic = device->start_panic;
 
-	return 0;
+    return 0;
 }
 
 int32_t dbg_change_device(dbg_dev_id_t dev_id)
 {
-	if (dev_id >= DBG_DEV_MAX)
-		return -EINVAL;
+    if (dev_id >= DBG_DEV_MAX)
+        return -EINVAL;
 
-	if (dbg_dev[dev_id].dev_id == DBG_DEV_MAX)
-		return -ENXIO;
-
-	cur_dev = &dbg_dev[dev_id];
-	return 0;
+    if (dbg_dev[dev_id].dev_id == DBG_DEV_MAX)
+        return -ENXIO;
 
+    cur_dev = &dbg_dev[dev_id];
+    return 0;
 }
 
-#else /* DEBUG_DEVICE_EXIST */
+#else  /* DEBUG_DEVICE_EXIST */
 uint8_t dbg_getchar(void)
 {
-	return (EOF);
+    return (EOF);
 }
 
 void dbg_putchar(uint8_t chr)
 {
-	chr = 0;
+    chr = 0;
 }
 
-void dbg_start_panic(void)
-{
-}
+void dbg_start_panic(void) {}
 #endif /* DEBUG_DEVICE_EXIST */
 
 #ifdef CONFIG_DEBUG
@@ -140,17 +136,15 @@ extern dbg_layer_t dbg_layer;
 void dbg_device_init_hook(void)
 {
 #ifdef DEBUG_DEVICE_EXIST
-	dbg_device_init();
+    dbg_device_init();
 #endif
-	dbg_layer = DL_KDB;  /* Minimal debug */
+    dbg_layer = DL_KDB; /* Minimal debug */
 }
 INIT_HOOK(dbg_device_init_hook, INIT_LEVEL_PLATFORM);
 #endif
 
 #ifdef CONFIG_STDIO_USE_DBGPORT
-uint8_t __l4_getchar(void)
-	__attribute__((weak, alias("dbg_getchar")));
+uint8_t __l4_getchar(void) __attribute__((weak, alias("dbg_getchar")));
 
-void __l4_putchar(uint8_t chr)
-	__attribute__((weak, alias("dbg_putchar")));
+void __l4_putchar(uint8_t chr) __attribute__((weak, alias("dbg_putchar")));
 #endif
diff --git a/platform/debug_ram.c b/platform/debug_ram.c
index 451039be..c7c12717 100644
--- a/platform/debug_ram.c
+++ b/platform/debug_ram.c
@@ -9,35 +9,35 @@
 
 #ifdef CONFIG_DEBUG_DEV_RAM
 typedef struct dbg_buf_t {
-	uint32_t	idx;
-	uint8_t		data[DBG_RAM_BUFSIZE];
+    uint32_t idx;
+    uint8_t data[DBG_RAM_BUFSIZE];
 } dbg_buf_t;
 
 static dbg_buf_t dbg_buf;
 
 static void dbg_ram_putchar(uint8_t chr)
 {
-	uint32_t idx;
+    uint32_t idx;
 
-	idx = dbg_buf.idx;
-	dbg_buf.data[idx++] = chr;
-	if (idx == DBG_RAM_BUFSIZE)
-		idx = 0;
+    idx = dbg_buf.idx;
+    dbg_buf.data[idx++] = chr;
+    if (idx == DBG_RAM_BUFSIZE)
+        idx = 0;
 
-	dbg_buf.idx = idx;
+    dbg_buf.idx = idx;
 }
 
 void dbg_ram_init(void)
 {
-	dbg_dev_t dbg_dev_ram;
+    dbg_dev_t dbg_dev_ram;
 
-	/* Initialize buffer */
-	memset(&dbg_buf, 0, sizeof(dbg_buf_t));
+    /* Initialize buffer */
+    memset(&dbg_buf, 0, sizeof(dbg_buf_t));
 
-	/* Register debug ram virtual device */
-	memset(&dbg_dev_ram, 0, sizeof(dbg_dev_t));
-	dbg_dev_ram.dev_id = DBG_DEV_RAM;
-	dbg_dev_ram.putchar = &dbg_ram_putchar;
-	dbg_register_device(&dbg_dev_ram);
+    /* Register debug ram virtual device */
+    memset(&dbg_dev_ram, 0, sizeof(dbg_dev_t));
+    dbg_dev_ram.dev_id = DBG_DEV_RAM;
+    dbg_dev_ram.putchar = &dbg_ram_putchar;
+    dbg_register_device(&dbg_dev_ram);
 }
 #endif /* CONFIG_DEBUG_DEV_RAM */
diff --git a/platform/debug_uart.c b/platform/debug_uart.c
index 7330d3f1..c4184049 100644
--- a/platform/debug_uart.c
+++ b/platform/debug_uart.c
@@ -3,10 +3,10 @@
  * found in the LICENSE file.
  */
 
+#include <lib/queue.h>
 #include <platform/debug_device.h>
 #include <platform/debug_uart.h>
 #include <platform/irq.h>
-#include <lib/queue.h>
 
 #ifdef CONFIG_KDB
 #include <softirq.h>
@@ -26,146 +26,143 @@ static void dbg_uart_send(int avail);
 
 void __uart_irq_handler(void)
 {
-	/* For RX: check SR status (RXNE) to ensure data is available.
-	 * For TX: check only CR1 interrupt enable (TXEIE) because QEMU's
-	 * USART emulation may not properly update SR TXE status bit.
-	 * This is safe because TXE interrupt only fires when TXE is set.
-	 */
-	if (usart_status(&console_uart, USART_RXNE)) {
-		/* USART RX - data received */
-		dbg_uart_recv();
-	}
-	if (usart_interrupt_status(&console_uart, USART_IT_TXE)) {
-		/* USART TX - transmit buffer empty */
-		dbg_uart_send(1);
-	}
+    /* For RX: check SR status (RXNE) to ensure data is available.
+     * For TX: check only CR1 interrupt enable (TXEIE) because QEMU's
+     * USART emulation may not properly update SR TXE status bit.
+     * This is safe because TXE interrupt only fires when TXE is set.
+     */
+    if (usart_status(&console_uart, USART_RXNE)) {
+        /* USART RX - data received */
+        dbg_uart_recv();
+    }
+    if (usart_interrupt_status(&console_uart, USART_IT_TXE)) {
+        /* USART TX - transmit buffer empty */
+        dbg_uart_send(1);
+    }
 }
 
 IRQ_HANDLER(BOARD_UART_HANDLER, __uart_irq_handler);
 
 static void dbg_uart_recv(void)
 {
-	uint8_t chr = usart_getc(&console_uart);
+    uint8_t chr = usart_getc(&console_uart);
 
-	/* Put sequence on queue */
-	queue_push(&(dbg_uart.rx), chr);
+    /* Put sequence on queue */
+    queue_push(&(dbg_uart.rx), chr);
 #ifndef LOADER
 #ifdef CONFIG_KDB
-	softirq_schedule(KDB_SOFTIRQ);
+    softirq_schedule(KDB_SOFTIRQ);
 #endif
 #endif
 }
 
 static void dbg_uart_send(int avail)
 {
-	uint8_t chr;
-
-	if (avail) {
-		if (!queue_is_empty(&(dbg_uart.tx))) {
-			queue_pop(&(dbg_uart.tx), &chr);
-			usart_putc(&console_uart, chr);
-			dbg_uart.ready = 0;
-			usart_config_interrupt(&console_uart, USART_IT_TXE, 1);
-		} else {
-			dbg_uart.ready = 1;
-			usart_config_interrupt(&console_uart, USART_IT_TXE, 0);
-		}
-	}
+    uint8_t chr;
+
+    if (avail) {
+        if (!queue_is_empty(&(dbg_uart.tx))) {
+            queue_pop(&(dbg_uart.tx), &chr);
+            usart_putc(&console_uart, chr);
+            dbg_uart.ready = 0;
+            usart_config_interrupt(&console_uart, USART_IT_TXE, 1);
+        } else {
+            dbg_uart.ready = 1;
+            usart_config_interrupt(&console_uart, USART_IT_TXE, 0);
+        }
+    }
 }
 
 static void dbg_async_putchar(char chr)
 {
-	/* If UART is busy, try to put chr into queue until slot is freed,
-	 * else write directly into UART
-	 */
-	if (!dbg_uart.ready) {
-		while (queue_push(&(dbg_uart.tx), chr) != QUEUE_OK)
-			/* wait */ ;
-	} else {
-		usart_putc(&console_uart, chr);
-		dbg_uart.ready = 0;
-		usart_config_interrupt(&console_uart, USART_IT_TXE, 1);
-	}
+    /* If UART is busy, try to put chr into queue until slot is freed,
+     * else write directly into UART
+     */
+    if (!dbg_uart.ready) {
+        while (queue_push(&(dbg_uart.tx), chr) != QUEUE_OK)
+            /* wait */;
+    } else {
+        usart_putc(&console_uart, chr);
+        dbg_uart.ready = 0;
+        usart_config_interrupt(&console_uart, USART_IT_TXE, 1);
+    }
 }
 
 static void dbg_sync_putchar(char chr)
 {
-	if (chr == '\n')
-		dbg_sync_putchar('\r');
+    if (chr == '\n')
+        dbg_sync_putchar('\r');
 
-	usart_putc(&console_uart, chr);
-	while (!usart_status(&console_uart, USART_TC))
-		/* wait */ ;
+    usart_putc(&console_uart, chr);
+    while (!usart_status(&console_uart, USART_TC))
+        /* wait */;
 }
 
 uint8_t dbg_uart_getchar(void)
 {
-	uint8_t chr = 0;
-
-	if (queue_pop(&(dbg_uart.rx), &chr) == QUEUE_EMPTY)
-		return 0;
-	return chr;
+    uint8_t chr = 0;
 
+    if (queue_pop(&(dbg_uart.rx), &chr) == QUEUE_EMPTY)
+        return 0;
+    return chr;
 }
 
 void dbg_uart_putchar(uint8_t chr)
 {
-	/* During panic, we cannot use async dbg uart, so switch to
-	 * synchronious mode
-	 */
-	if (dbg_state != DBG_PANIC)
-		dbg_async_putchar(chr);
-	else
-		dbg_sync_putchar(chr);
+    /* During panic, we cannot use async dbg uart, so switch to
+     * synchronious mode
+     */
+    if (dbg_state != DBG_PANIC)
+        dbg_async_putchar(chr);
+    else
+        dbg_sync_putchar(chr);
 }
 static void dbg_uart_start_panic(void)
 {
-	unsigned char chr;
+    unsigned char chr;
 
-	/* In panic condition, we can be in interrupt context or
-	 * not, so will write sequence synchronously */
+    /* In panic condition, we can be in interrupt context or
+     * not, so will write sequence synchronously */
 
-	/* Flush remaining sequence  in async buffer */
-	while (queue_pop(&(dbg_uart.tx), &chr) != QUEUE_EMPTY) {
-		dbg_sync_putchar(chr);
-	}
+    /* Flush remaining sequence  in async buffer */
+    while (queue_pop(&(dbg_uart.tx), &chr) != QUEUE_EMPTY) {
+        dbg_sync_putchar(chr);
+    }
 
-	dbg_state = DBG_PANIC;
+    dbg_state = DBG_PANIC;
 }
 
 void dbg_uart_init(void)
 {
-	dbg_dev_t dbg_dev_uart = {
-		.dev_id = DBG_DEV_UART,
-		.getchar = &dbg_uart_getchar,
-		.putchar = &dbg_uart_putchar,
-		.start_panic = &dbg_uart_start_panic
-	};
+    dbg_dev_t dbg_dev_uart = {.dev_id = DBG_DEV_UART,
+                              .getchar = &dbg_uart_getchar,
+                              .putchar = &dbg_uart_putchar,
+                              .start_panic = &dbg_uart_start_panic};
 
-	usart_init(&console_uart);
+    usart_init(&console_uart);
 
-	dbg_uart.ready = 1;
-	queue_init(&(dbg_uart.tx), dbg_uart_tx_buffer, SEND_BUFSIZE);
-	queue_init(&(dbg_uart.rx), dbg_uart_rx_buffer, RECV_BUFSIZE);
+    dbg_uart.ready = 1;
+    queue_init(&(dbg_uart.tx), dbg_uart_tx_buffer, SEND_BUFSIZE);
+    queue_init(&(dbg_uart.rx), dbg_uart_rx_buffer, RECV_BUFSIZE);
 
 #ifdef CONFIG_QEMU
-	/* Use sync output for reliable debugging under QEMU.
-	 * QEMU's USART TXE interrupt emulation is unreliable,
-	 * causing the async TX queue to block indefinitely.
-	 */
-	dbg_state = DBG_PANIC;
+    /* Use sync output for reliable debugging under QEMU.
+     * QEMU's USART TXE interrupt emulation is unreliable,
+     * causing the async TX queue to block indefinitely.
+     */
+    dbg_state = DBG_PANIC;
 #else
-	dbg_state = DBG_ASYNC;
+    dbg_state = DBG_ASYNC;
 #endif
-	usart_config_interrupt(&console_uart, USART_IT_RXNE, 1);
+    usart_config_interrupt(&console_uart, USART_IT_RXNE, 1);
 
-	/* UART must have higher priority (lower number) than PendSV (0xf)
-	 * so it can preempt and drain TX queue during debug output.
-	 * Otherwise dbg_async_putchar deadlocks waiting for queue space.
-	 */
-	NVIC_SetPriority(BOARD_UART_DEVICE, 0xe, 0);
-	NVIC_ClearPendingIRQ(BOARD_UART_DEVICE);
-	NVIC_EnableIRQ(BOARD_UART_DEVICE);
+    /* UART must have higher priority (lower number) than PendSV (0xf)
+     * so it can preempt and drain TX queue during debug output.
+     * Otherwise dbg_async_putchar deadlocks waiting for queue space.
+     */
+    NVIC_SetPriority(BOARD_UART_DEVICE, 0xe, 0);
+    NVIC_ClearPendingIRQ(BOARD_UART_DEVICE);
+    NVIC_EnableIRQ(BOARD_UART_DEVICE);
 
-	dbg_register_device(&dbg_dev_uart);
+    dbg_register_device(&dbg_dev_uart);
 }
diff --git a/platform/hw_debug.c b/platform/hw_debug.c
index 990fa035..da04ce84 100644
--- a/platform/hw_debug.c
+++ b/platform/hw_debug.c
@@ -7,39 +7,39 @@
 #error __FILE__ " is the part of KProbes implementation."
 #endif
 
-#include <platform/irq.h>
-#include <platform/hw_debug.h>
 #include <platform/cortex_m.h>
+#include <platform/hw_debug.h>
+#include <platform/irq.h>
 
 extern void arch_kprobe_handler(uint32_t *stack);
 
 void debugmon_handler(void) __NAKED;
 void debugmon_handler(void)
 {
-	/* select interrupted stack */
-	__asm__ __volatile__("and r0, lr, #4");
-	__asm__ __volatile__("cmp r0, #0");
-	__asm__ __volatile__("ite eq");
-	__asm__ __volatile__("mrseq r0, msp");
-	__asm__ __volatile__("mrsne r0, psp");
-
-	/* save r4-r11 */
-	__asm__ __volatile__("push {r4-r11}");
-	__asm__ __volatile__("mov r1, sp");
-
-	/*
-	 * arch_kprobe_handler(uint32_t *stack, uint32_t *kp_regs)
-	 * r0 = r0-r3,r12,lr,pc,psr
-	 * r1 = r4-r11
-	 */
-	__asm__ __volatile__("push {lr}");
-	__asm__ __volatile__("bl arch_kprobe_handler");
-	__asm__ __volatile__("pop {lr}");
-
-	/* override r4-r11 */
-	__asm__ __volatile__("pop {r4-r11}");
-
-	/* NOTE: No support stack modification for the time being */
-
-	__asm__ __volatile__("bx lr");
+    /* select interrupted stack */
+    __asm__ __volatile__("and r0, lr, #4");
+    __asm__ __volatile__("cmp r0, #0");
+    __asm__ __volatile__("ite eq");
+    __asm__ __volatile__("mrseq r0, msp");
+    __asm__ __volatile__("mrsne r0, psp");
+
+    /* save r4-r11 */
+    __asm__ __volatile__("push {r4-r11}");
+    __asm__ __volatile__("mov r1, sp");
+
+    /*
+     * arch_kprobe_handler(uint32_t *stack, uint32_t *kp_regs)
+     * r0 = r0-r3,r12,lr,pc,psr
+     * r1 = r4-r11
+     */
+    __asm__ __volatile__("push {lr}");
+    __asm__ __volatile__("bl arch_kprobe_handler");
+    __asm__ __volatile__("pop {lr}");
+
+    /* override r4-r11 */
+    __asm__ __volatile__("pop {r4-r11}");
+
+    /* NOTE: No support stack modification for the time being */
+
+    __asm__ __volatile__("bx lr");
 }
diff --git a/platform/irq.c b/platform/irq.c
index 830a8a39..79eb2d96 100644
--- a/platform/irq.c
+++ b/platform/irq.c
@@ -15,32 +15,32 @@ volatile uint32_t __irq_saved_regs[8];
 
 void irq_init(void)
 {
-	/* Set all 4-bit to pre-emption priority bit */
-	NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4);
+    /* Set all 4-bit to pre-emption priority bit */
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4);
 
-	/* Set default priority from high to low */
+    /* Set default priority from high to low */
 
-	NVIC_SetPriority(DebugMonitor_IRQn, 0x0, 0);
+    NVIC_SetPriority(DebugMonitor_IRQn, 0x0, 0);
 
-	NVIC_SetPriority(MemoryManagement_IRQn, 0x1, 0);
-	NVIC_SetPriority(BusFault_IRQn, 0x1, 0);
-	NVIC_SetPriority(UsageFault_IRQn, 0x1, 0);
+    NVIC_SetPriority(MemoryManagement_IRQn, 0x1, 0);
+    NVIC_SetPriority(BusFault_IRQn, 0x1, 0);
+    NVIC_SetPriority(UsageFault_IRQn, 0x1, 0);
 
-	NVIC_SetPriority(SysTick_IRQn, 0x3, 0);
+    NVIC_SetPriority(SysTick_IRQn, 0x3, 0);
 
-	/* SVCall and PendSV at lowest priority */
-	NVIC_SetPriority(SVCall_IRQn, 0xF, 0);
-	NVIC_SetPriority(PendSV_IRQn, 0xF, 0);
+    /* SVCall and PendSV at lowest priority */
+    NVIC_SetPriority(SVCall_IRQn, 0xF, 0);
+    NVIC_SetPriority(PendSV_IRQn, 0xF, 0);
 }
 
 #ifndef LOADER
 void pendsv_handler(void) __NAKED;
 void pendsv_handler(void)
 {
-	/* Save r4-r11 FIRST before any C code can corrupt them */
-	irq_save_regs_only();
-	irq_enter();
-	schedule_in_irq();
-	irq_return();
+    /* Save r4-r11 FIRST before any C code can corrupt them */
+    irq_save_regs_only();
+    irq_enter();
+    schedule_in_irq();
+    irq_return();
 }
 #endif
diff --git a/platform/kprobes-arch.c b/platform/kprobes-arch.c
index fe4bac23..2598dd2c 100644
--- a/platform/kprobes-arch.c
+++ b/platform/kprobes-arch.c
@@ -7,88 +7,87 @@
 #error __FILE__ " is the part of KProbes implementation."
 #endif
 
-#include <kprobes.h>
 #include <error.h>
+#include <kprobes.h>
+#include <platform/breakpoint.h>
 #include <platform/cortex_m.h>
 #include <platform/hw_debug.h>
-#include <platform/breakpoint.h>
 
 void kprobe_arch_init()
 {
-	breakpoint_pool_init();
+    breakpoint_pool_init();
 }
 
 int kprobe_arch_add(struct kprobe *kp)
 {
-	struct kprobe *found = kplist_search(kp->addr);
-	struct breakpoint *b;
-
-	/*
-	 * If there is no kprobe at this addr, give it a new bkpt,
-	 * otherwise share the existing bkpt.
-	 */
-
-	if (!found) {
-		b = breakpoint_install((uint32_t) kp->addr);
-		if (b) {
-			kp->bkpt = b;
-			enable_breakpoint(b);
-		} else
-			goto arch_add_error;
-	} else {
-		kp->bkpt = found->bkpt;
-	}
-
-	return 0;
+    struct kprobe *found = kplist_search(kp->addr);
+    struct breakpoint *b;
+
+    /*
+     * If there is no kprobe at this addr, give it a new bkpt,
+     * otherwise share the existing bkpt.
+     */
+
+    if (!found) {
+        b = breakpoint_install((uint32_t) kp->addr);
+        if (b) {
+            kp->bkpt = b;
+            enable_breakpoint(b);
+        } else
+            goto arch_add_error;
+    } else {
+        kp->bkpt = found->bkpt;
+    }
+
+    return 0;
 
 arch_add_error:
-	return -1;
+    return -1;
 }
 
 int kprobe_arch_del(struct kprobe *kp)
 {
-	struct kprobe *found = kplist_search(kp->addr);
+    struct kprobe *found = kplist_search(kp->addr);
 
-	/* Free bkpt when there is no kprobe at this addr */
-	if (!found)
-		breakpoint_uninstall(kp->bkpt);
-	return 0;
+    /* Free bkpt when there is no kprobe at this addr */
+    if (!found)
+        breakpoint_uninstall(kp->bkpt);
+    return 0;
 }
 
 void arch_kprobe_handler(uint32_t *stack, uint32_t *kp_regs)
 {
-	/*
-	 * For convenience currently we assume all cpu single-step is
-	 * enabled/disabled by arch_kprobe_handler.
-	 *
-	 * To execute instruction at the probed address, we have to disable
-	 * breakpoint before return from handler, and re-enable it in the
-	 * next instruction.
-	 */
-
-	if ((*SCB_DFSR & SCB_DFSR_DWTTRAP)) {
-		panic("DWT Watchpoint hit\n");
-	} else if ((*SCB_DFSR & SCB_DFSR_BKPT)) {
-
-		kprobe_prebreak(stack, kp_regs);
-
-		/* Clear BKPT status bit */
-		*SCB_DFSR  =  SCB_DFSR_BKPT;
-
-		cpu_enable_single_step();
-		kprobe_breakpoint_disable(stack);
-	} else if (*SCB_DFSR & SCB_DFSR_HALTED) {
-		kprobe_postbreak(stack, kp_regs);
-
-		/* Clear HALTED status bit */
-		*SCB_DFSR  =  SCB_DFSR_HALTED;
-
-		cpu_disable_single_step();
-		kprobe_breakpoint_enable(stack);
-	} else {
-		/*
-		 * sometimes DWT generates faults
-		 * without setting SCB_DFSR_DWTTRAP
-		 */
-	}
+    /*
+     * For convenience currently we assume all cpu single-step is
+     * enabled/disabled by arch_kprobe_handler.
+     *
+     * To execute instruction at the probed address, we have to disable
+     * breakpoint before return from handler, and re-enable it in the
+     * next instruction.
+     */
+
+    if ((*SCB_DFSR & SCB_DFSR_DWTTRAP)) {
+        panic("DWT Watchpoint hit\n");
+    } else if ((*SCB_DFSR & SCB_DFSR_BKPT)) {
+        kprobe_prebreak(stack, kp_regs);
+
+        /* Clear BKPT status bit */
+        *SCB_DFSR = SCB_DFSR_BKPT;
+
+        cpu_enable_single_step();
+        kprobe_breakpoint_disable(stack);
+    } else if (*SCB_DFSR & SCB_DFSR_HALTED) {
+        kprobe_postbreak(stack, kp_regs);
+
+        /* Clear HALTED status bit */
+        *SCB_DFSR = SCB_DFSR_HALTED;
+
+        cpu_disable_single_step();
+        kprobe_breakpoint_enable(stack);
+    } else {
+        /*
+         * sometimes DWT generates faults
+         * without setting SCB_DFSR_DWTTRAP
+         */
+    }
 }
diff --git a/platform/mpu.c b/platform/mpu.c
index ea772f15..c43e8d90 100644
--- a/platform/mpu.c
+++ b/platform/mpu.c
@@ -3,21 +3,15 @@
  * found in the LICENSE file.
  */
 
-#include <fpage.h>
-#include <memory.h>
 #include <debug.h>
 #include <error.h>
+#include <fpage.h>
+#include <memory.h>
 #include <platform/irq.h>
 #include <platform/mpu.h>
 
-void __attribute__((weak)) mpu_setup_region(int n, fpage_t *fp)
-{
-}
+void __attribute__((weak)) mpu_setup_region(int n, fpage_t *fp) {}
 
-void __attribute__((weak)) mpu_enable(mpu_state_t i)
-{
-}
+void __attribute__((weak)) mpu_enable(mpu_state_t i) {}
 
-void __attribute__((weak)) __memmanage_handler(void)
-{
-}
+void __attribute__((weak)) __memmanage_handler(void) {}
diff --git a/platform/spinlock.c b/platform/spinlock.c
index ccf0368c..cd41eced 100644
--- a/platform/spinlock.c
+++ b/platform/spinlock.c
@@ -13,37 +13,39 @@
 /* Basic spinlock ops for ARMv7M architecture */
 int spinlock_trylock(spinlock_t *sl)
 {
-	int result = 0;	/* Assuming lock is busy */
+    int result = 0; /* Assuming lock is busy */
 
-	__asm__ __volatile__("mov r1, #1");
-	__asm__ __volatile__("mov r7, %0" : : "r"(sl));
-	__asm__ __volatile__("ldrex r0, [r7]" :);
-	__asm__ __volatile__("cmp r0, #0");
+    __asm__ __volatile__("mov r1, #1");
+    __asm__ __volatile__("mov r7, %0" : : "r"(sl));
+    __asm__ __volatile__("ldrex r0, [r7]" :);
+    __asm__ __volatile__("cmp r0, #0");
 
-	/* Lock is not busy, trying to get it */
-	__asm__ __volatile__("itt eq\n"
-	                     "strexeq r0, r1, [r7]\n"
-	                     "moveq %0, r0"
-	                     : "=r"(result));
+    /* Lock is not busy, trying to get it */
+    __asm__ __volatile__(
+        "itt eq\n"
+        "strexeq r0, r1, [r7]\n"
+        "moveq %0, r0"
+        : "=r"(result));
 
-	return result;
+    return result;
 }
 
 void spinlock_lock(spinlock_t *sl)
 {
-	while (spinlock_trylock(sl) != 1)
-		/* */;
+    while (spinlock_trylock(sl) != 1)
+        /* */;
 }
 
 void spinlock_unlock(spinlock_t *sl)
 {
-	__asm__ __volatile__("mov r1, #0");
-	__asm__ __volatile__("spinlock_try: ldrex r0, [%0]\n"
-	                     "strex r0, r1, [%0]\n"
-	                     "cmp r0, #0"
-	                     :
-	                     : "r"(sl));
-	__asm__ __volatile__("bne spinlock_try");
+    __asm__ __volatile__("mov r1, #0");
+    __asm__ __volatile__(
+        "spinlock_try: ldrex r0, [%0]\n"
+        "strex r0, r1, [%0]\n"
+        "cmp r0, #0"
+        :
+        : "r"(sl));
+    __asm__ __volatile__("bne spinlock_try");
 }
 
 #endif
diff --git a/platform/stm32-common/gpio-f1.c b/platform/stm32-common/gpio-f1.c
index 38da0c44..d2962602 100644
--- a/platform/stm32-common/gpio-f1.c
+++ b/platform/stm32-common/gpio-f1.c
@@ -8,93 +8,99 @@
 
 #include INC_PLAT(gpio.c)
 
-inline static void gpio_cr(uint8_t port, uint8_t pin, uint8_t mode, uint8_t ospeed)
+inline static void gpio_cr(uint8_t port,
+                           uint8_t pin,
+                           uint8_t mode,
+                           uint8_t ospeed)
 {
-	uint32_t reg;
-	if (pin < 8) {
-		reg = *GPIO_CRL(port);
-		reg &= ~(GPIO_CR_M(pin));
-		reg |= (((mode << 2) | ospeed) << GPIO_CR_PIN(pin));
-		*GPIO_CRL(port) = reg;
-	} else {
-		reg = *GPIO_CRH(port);
-		reg &= ~(GPIO_CR_M(pin));
-		reg |= (((mode << 2) | ospeed) << GPIO_CR_PIN((pin-8)));
-		*GPIO_CRH(port) = reg;
-	}
+    uint32_t reg;
+    if (pin < 8) {
+        reg = *GPIO_CRL(port);
+        reg &= ~(GPIO_CR_M(pin));
+        reg |= (((mode << 2) | ospeed) << GPIO_CR_PIN(pin));
+        *GPIO_CRL(port) = reg;
+    } else {
+        reg = *GPIO_CRH(port);
+        reg &= ~(GPIO_CR_M(pin));
+        reg |= (((mode << 2) | ospeed) << GPIO_CR_PIN((pin - 8)));
+        *GPIO_CRH(port) = reg;
+    }
 }
 
 void __USER_TEXT gpio_config(struct gpio_cfg *cfg)
 {
-	uint8_t port, pin, cfg_data;
-
-	port = cfg->port;
-	pin = cfg->pin;
-
-	*RCC_APB2ENR |= (1 << (port + 2));
-
-	/* Mode and speed */
-	gpio_cr(port, pin, cfg->mode, cfg->ospeed);
-	
-	cfg_data = cfg->mode;
-	/* Input Push up or push down */
-	if ((((uint32_t)cfg_data) & ((uint32_t)0x10)) != 0x00) {
-		if (cfg_data == GPIO_MODE_IN_PD)
-			*GPIO_BRR(port) = GPIO_BRR_BR(pin);
-		else if (cfg_data == GPIO_MODE_IN_PU)
-			*GPIO_BSRR(port) = GPIO_BSRR_BS(pin);
-		return;
-	}
+    uint8_t port, pin, cfg_data;
+
+    port = cfg->port;
+    pin = cfg->pin;
+
+    *RCC_APB2ENR |= (1 << (port + 2));
+
+    /* Mode and speed */
+    gpio_cr(port, pin, cfg->mode, cfg->ospeed);
+
+    cfg_data = cfg->mode;
+    /* Input Push up or push down */
+    if ((((uint32_t) cfg_data) & ((uint32_t) 0x10)) != 0x00) {
+        if (cfg_data == GPIO_MODE_IN_PD)
+            *GPIO_BRR(port) = GPIO_BRR_BR(pin);
+        else if (cfg_data == GPIO_MODE_IN_PU)
+            *GPIO_BSRR(port) = GPIO_BSRR_BS(pin);
+        return;
+    }
 }
 
-void __USER_TEXT gpio_config_output(uint8_t port, uint8_t pin, uint8_t mode, uint8_t ospeed)
+void __USER_TEXT gpio_config_output(uint8_t port,
+                                    uint8_t pin,
+                                    uint8_t mode,
+                                    uint8_t ospeed)
 {
-	struct  gpio_cfg cfg = {
-		.port = port,
-		.pin = pin,
-		.mode = mode,
-		.ospeed = ospeed,
-		.func = 0,
-	};
-
-	gpio_config(&cfg);
+    struct gpio_cfg cfg = {
+        .port = port,
+        .pin = pin,
+        .mode = mode,
+        .ospeed = ospeed,
+        .func = 0,
+    };
+
+    gpio_config(&cfg);
 }
 
 void __USER_TEXT gpio_config_input(uint8_t port, uint8_t pin, uint8_t mode)
 {
-	struct  gpio_cfg cfg = {
-		.port = port,
-		.pin = pin,
-		.mode = mode,
-		.ospeed = 0,
-		.func = 0,
-	};
-
-	gpio_config(&cfg);
+    struct gpio_cfg cfg = {
+        .port = port,
+        .pin = pin,
+        .mode = mode,
+        .ospeed = 0,
+        .func = 0,
+    };
+
+    gpio_config(&cfg);
 }
 
 void __USER_TEXT gpio_out_high(uint8_t port, uint8_t pin)
 {
-	*GPIO_ODR(port) |= GPIO_ODR_PIN(pin);
+    *GPIO_ODR(port) |= GPIO_ODR_PIN(pin);
 }
 
 void __USER_TEXT gpio_out_low(uint8_t port, uint8_t pin)
 {
-	*GPIO_ODR(port) &= ~GPIO_ODR_PIN(pin);
+    *GPIO_ODR(port) &= ~GPIO_ODR_PIN(pin);
 }
 
 uint8_t __USER_TEXT gpio_input_bit(uint8_t port, uint8_t pin)
 {
-	if (*GPIO_IDR(port) & GPIO_IDR_PIN(pin))
-		return 1;
+    if (*GPIO_IDR(port) & GPIO_IDR_PIN(pin))
+        return 1;
 
-	return 0;
+    return 0;
 }
 
 void __USER_TEXT gpio_writebit(uint8_t port, uint8_t pin, uint8_t bitval)
 {
-	if (bitval != 0)
-		*GPIO_BSRR(port) = GPIO_BSRR_BS(pin);
-	else
-		*GPIO_BSRR(port) = GPIO_BSRR_BR(pin);
+    if (bitval != 0)
+        *GPIO_BSRR(port) = GPIO_BSRR_BS(pin);
+    else
+        *GPIO_BSRR(port) = GPIO_BSRR_BR(pin);
 }
diff --git a/platform/stm32-common/gpio-f4.c b/platform/stm32-common/gpio-f4.c
index 7e560e48..6a541b3e 100644
--- a/platform/stm32-common/gpio-f4.c
+++ b/platform/stm32-common/gpio-f4.c
@@ -10,152 +10,155 @@
 
 inline static void gpio_moder(uint8_t port, uint8_t pin, uint8_t type)
 {
-	uint32_t reg = *GPIO_MODER(port);
+    uint32_t reg = *GPIO_MODER(port);
 
-	reg &= ~(GPIO_MODER_M(pin));
-	reg |= (type << GPIO_MODER_PIN(pin));
+    reg &= ~(GPIO_MODER_M(pin));
+    reg |= (type << GPIO_MODER_PIN(pin));
 
-	*GPIO_MODER(port) = reg;
+    *GPIO_MODER(port) = reg;
 }
 
 inline static void gpio_otyper(uint8_t port, uint8_t pin, uint8_t type)
 {
-	uint32_t reg = *GPIO_OTYPER(port);
+    uint32_t reg = *GPIO_OTYPER(port);
 
-	reg &= ~(GPIO_OTYPER_M(pin));
-	reg |= (type << GPIO_OTYPER_PIN(pin));
+    reg &= ~(GPIO_OTYPER_M(pin));
+    reg |= (type << GPIO_OTYPER_PIN(pin));
 
-	*GPIO_OTYPER(port) = reg;
+    *GPIO_OTYPER(port) = reg;
 }
 
 inline static void gpio_ospeedr(uint8_t port, uint8_t pin, uint8_t speed)
 {
-	uint32_t reg = *GPIO_OSPEEDR(port);
+    uint32_t reg = *GPIO_OSPEEDR(port);
 
-	reg &= ~(GPIO_OSPEEDR_M(pin));
-	reg |= (speed << GPIO_OSPEEDR_PIN(pin));
+    reg &= ~(GPIO_OSPEEDR_M(pin));
+    reg |= (speed << GPIO_OSPEEDR_PIN(pin));
 
-	*GPIO_OSPEEDR(port) = reg;
+    *GPIO_OSPEEDR(port) = reg;
 }
 
 inline static void gpio_pupdr(uint8_t port, uint8_t pin, uint8_t mode)
 {
-	uint32_t reg = *GPIO_PUPDR(port);
+    uint32_t reg = *GPIO_PUPDR(port);
 
-	reg &= ~(GPIO_PUPDR_M(pin));
-	reg |= (mode << GPIO_PUPDR_PIN(pin));
+    reg &= ~(GPIO_PUPDR_M(pin));
+    reg |= (mode << GPIO_PUPDR_PIN(pin));
 
-	*GPIO_PUPDR(port) = reg;
+    *GPIO_PUPDR(port) = reg;
 }
 
 inline static void gpio_afr(uint8_t port, uint8_t pin, uint8_t func)
 {
-	uint32_t reg;
-
-	if (pin < 8) {
-		reg = *GPIO_AFRL(port);
-		reg &= ~(GPIO_AFRL_M(pin));
-		reg |= (func << GPIO_AFRL_PIN(pin));
-		*GPIO_AFRL(port) = reg;
-	} else {
-		reg = *GPIO_AFRH(port);
-		reg &= ~(GPIO_AFRH_M(pin));
-		reg |= (func << GPIO_AFRH_PIN(pin));
-		*GPIO_AFRH(port) = reg;
-	}
+    uint32_t reg;
+
+    if (pin < 8) {
+        reg = *GPIO_AFRL(port);
+        reg &= ~(GPIO_AFRL_M(pin));
+        reg |= (func << GPIO_AFRL_PIN(pin));
+        *GPIO_AFRL(port) = reg;
+    } else {
+        reg = *GPIO_AFRH(port);
+        reg &= ~(GPIO_AFRH_M(pin));
+        reg |= (func << GPIO_AFRH_PIN(pin));
+        *GPIO_AFRH(port) = reg;
+    }
 }
 
 void __USER_TEXT gpio_config(struct gpio_cfg *cfg)
 {
-	uint8_t port, pin, cfg_data;
+    uint8_t port, pin, cfg_data;
 
-	port = cfg->port;
-	pin = cfg->pin;
+    port = cfg->port;
+    pin = cfg->pin;
 
-	*RCC_AHB1ENR |= (1 << port);
+    *RCC_AHB1ENR |= (1 << port);
 
-	/* pupd */
-	cfg_data = cfg->pupd;
-	gpio_pupdr(port, pin, cfg_data);
+    /* pupd */
+    cfg_data = cfg->pupd;
+    gpio_pupdr(port, pin, cfg_data);
 
-	/* mode type */
-	cfg_data = cfg->type;
-	gpio_moder(port, pin, cfg_data);
+    /* mode type */
+    cfg_data = cfg->type;
+    gpio_moder(port, pin, cfg_data);
 
-	if (cfg_data == GPIO_MODER_IN)
-		return;
+    if (cfg_data == GPIO_MODER_IN)
+        return;
 
-	/* Alternative function */
-	if (cfg_data == GPIO_MODER_ALT) {
-		uint8_t func = cfg->func;
-		gpio_afr(port, pin, func);
-	}
+    /* Alternative function */
+    if (cfg_data == GPIO_MODER_ALT) {
+        uint8_t func = cfg->func;
+        gpio_afr(port, pin, func);
+    }
 
-	/* Sets pin output type */
-	cfg_data = cfg->o_type;
-	gpio_otyper(port, pin, cfg_data);
+    /* Sets pin output type */
+    cfg_data = cfg->o_type;
+    gpio_otyper(port, pin, cfg_data);
 
-	/* Speed */
-	cfg_data = cfg->speed;
-	gpio_ospeedr(port, pin, cfg_data);
+    /* Speed */
+    cfg_data = cfg->speed;
+    gpio_ospeedr(port, pin, cfg_data);
 }
 
-void __USER_TEXT gpio_config_output(uint8_t port, uint8_t pin, uint8_t pupd, uint8_t speed)
+void __USER_TEXT gpio_config_output(uint8_t port,
+                                    uint8_t pin,
+                                    uint8_t pupd,
+                                    uint8_t speed)
 {
-	struct  gpio_cfg cfg = {
-		.port = port,
-		.pin = pin,
-		.pupd = pupd,
-		.type = GPIO_MODER_OUT,
-		.func = 0,
-		.o_type = GPIO_OTYPER_PP,
-		.pupd = pupd,
-		.speed = speed,
-	};
-
-	*RCC_AHB1ENR |= (1 << port);
-	gpio_config(&cfg);
+    struct gpio_cfg cfg = {
+        .port = port,
+        .pin = pin,
+        .pupd = pupd,
+        .type = GPIO_MODER_OUT,
+        .func = 0,
+        .o_type = GPIO_OTYPER_PP,
+        .pupd = pupd,
+        .speed = speed,
+    };
+
+    *RCC_AHB1ENR |= (1 << port);
+    gpio_config(&cfg);
 }
 
 void __USER_TEXT gpio_config_input(uint8_t port, uint8_t pin, uint8_t pupd)
 {
-	struct  gpio_cfg cfg = {
-		.port = port,
-		.pin = pin,
-		.pupd = pupd,
-		.type = GPIO_MODER_IN,
-		.func = 0,
-		.o_type = 0,
-		.pupd = pupd,
-		.speed = 0,
-	};
-
-	*RCC_AHB1ENR |= (1 << port);
-	gpio_config(&cfg);
+    struct gpio_cfg cfg = {
+        .port = port,
+        .pin = pin,
+        .pupd = pupd,
+        .type = GPIO_MODER_IN,
+        .func = 0,
+        .o_type = 0,
+        .pupd = pupd,
+        .speed = 0,
+    };
+
+    *RCC_AHB1ENR |= (1 << port);
+    gpio_config(&cfg);
 }
 
 void __USER_TEXT gpio_out_high(uint8_t port, uint8_t pin)
 {
-	*GPIO_ODR(port) |= (1 << pin);
+    *GPIO_ODR(port) |= (1 << pin);
 }
 
 void __USER_TEXT gpio_out_low(uint8_t port, uint8_t pin)
 {
-	*GPIO_ODR(port) &= ~(1 << pin);
+    *GPIO_ODR(port) &= ~(1 << pin);
 }
 
 uint8_t __USER_TEXT gpio_input_bit(uint8_t port, uint8_t pin)
 {
-	if (*GPIO_IDR(port) & (1 << pin))
-		return 1;
+    if (*GPIO_IDR(port) & (1 << pin))
+        return 1;
 
-	return 0;
+    return 0;
 }
 
 void __USER_TEXT gpio_writebit(uint8_t port, uint8_t pin, uint8_t bitval)
 {
-	if (bitval != 0)
-		*GPIO_BSRR(port) = GPIO_BSRR_BS(pin);
-	else
-		*GPIO_BSRR(port) = GPIO_BSRR_BR(pin);
+    if (bitval != 0)
+        *GPIO_BSRR(port) = GPIO_BSRR_BS(pin);
+    else
+        *GPIO_BSRR(port) = GPIO_BSRR_BR(pin);
 }
diff --git a/platform/stm32-common/hwtimer.c b/platform/stm32-common/hwtimer.c
index 5b9e6120..76d21bb9 100644
--- a/platform/stm32-common/hwtimer.c
+++ b/platform/stm32-common/hwtimer.c
@@ -10,13 +10,13 @@
 
 void hwtimer_init()
 {
-	*RCC_APB1ENR |= 0x00000001;
-	*TIM2_PSC = 0;
-	*TIM2_ARR = 0xFFFFFFFF;
-	*TIM2_CR1 = 0x00000001;
+    *RCC_APB1ENR |= 0x00000001;
+    *TIM2_PSC = 0;
+    *TIM2_ARR = 0xFFFFFFFF;
+    *TIM2_CR1 = 0x00000001;
 }
 
 uint32_t hwtimer_now()
 {
-	return *TIM2_CNT;
+    return *TIM2_CNT;
 }
diff --git a/platform/stm32-common/mpu.c b/platform/stm32-common/mpu.c
index 239907fd..7d808c65 100644
--- a/platform/stm32-common/mpu.c
+++ b/platform/stm32-common/mpu.c
@@ -3,219 +3,220 @@
  * found in the LICENSE file.
  */
 
-#include <fpage.h>
-#include <memory.h>
 #include <debug.h>
 #include <error.h>
+#include <fpage.h>
+#include <memory.h>
+#include <platform/cortex_m.h>
 #include <platform/irq.h>
 #include <platform/mpu.h>
-#include <platform/cortex_m.h>
 
 #include INC_PLAT(mpu.c)
 
 void mpu_setup_region(int n, fpage_t *fp)
 {
-	static uint32_t *mpu_base = (uint32_t *) MPU_BASE_ADDR;
-	static uint32_t *mpu_attr = (uint32_t *) MPU_ATTR_ADDR;
-
-	if (fp) {
-		*mpu_base = (FPAGE_BASE(fp) & MPU_REGION_MASK) | 0x10 | (n & 0xF);
-		*mpu_attr = ((mempool_getbyid(fp->fpage.mpid)->flags & MP_UX) ?
-		             0 :
-		             (1 << 28)) |	/* XN bit */
-		            (0x3 << 24) /* Full access */ |
-		            ((fp->fpage.shift - 1) << 1) /* Region size*/ |
-		            1 /* Enable */;
-	} else {
-		/* Clean MPU region */
-		*mpu_base = 0x10 | (n & 0xF);
-		*mpu_attr = 0;
-	}
-
-	/* Memory barriers ensure MPU changes take effect immediately */
-	__DSB();
-	__ISB();
+    static uint32_t *mpu_base = (uint32_t *) MPU_BASE_ADDR;
+    static uint32_t *mpu_attr = (uint32_t *) MPU_ATTR_ADDR;
+
+    if (fp) {
+        *mpu_base = (FPAGE_BASE(fp) & MPU_REGION_MASK) | 0x10 | (n & 0xF);
+        *mpu_attr = ((mempool_getbyid(fp->fpage.mpid)->flags & MP_UX)
+                         ? 0
+                         : (1 << 28)) | /* XN bit */
+                    (0x3 << 24)         /* Full access */
+                    | ((fp->fpage.shift - 1) << 1) /* Region size*/ |
+                    1 /* Enable */;
+    } else {
+        /* Clean MPU region */
+        *mpu_base = 0x10 | (n & 0xF);
+        *mpu_attr = 0;
+    }
+
+    /* Memory barriers ensure MPU changes take effect immediately */
+    __DSB();
+    __ISB();
 }
 
 void mpu_enable(mpu_state_t i)
 {
-	static uint32_t *mpu_ctrl = (uint32_t*) MPU_CTRL_ADDR;
+    static uint32_t *mpu_ctrl = (uint32_t *) MPU_CTRL_ADDR;
 
-	*mpu_ctrl = i | MPU_PRIVDEFENA;
+    *mpu_ctrl = i | MPU_PRIVDEFENA;
 }
 
 int addr_in_mpu(uint32_t addr)
 {
-	static uint32_t *mpu_rnr = (uint32_t *) MPU_RNR_ADDR;
-	static uint32_t *mpu_base = (uint32_t *) MPU_BASE_ADDR;
-	static uint32_t *mpu_attr = (uint32_t *) MPU_ATTR_ADDR;
-	int i;
-
-	for (i = 0; i < 8; ++i) {
-		*mpu_rnr = i;
-		if (*mpu_attr & 0x1) {
-			uint32_t base = *mpu_base & MPU_REGION_MASK;
-			uint32_t size = 1 << (((*mpu_attr >> 1) & 0x1F) + 1);
-			if (addr >= base && addr < base + size)
-				return 1;
-		}
-	}
-
-	return 0;
+    static uint32_t *mpu_rnr = (uint32_t *) MPU_RNR_ADDR;
+    static uint32_t *mpu_base = (uint32_t *) MPU_BASE_ADDR;
+    static uint32_t *mpu_attr = (uint32_t *) MPU_ATTR_ADDR;
+    int i;
+
+    for (i = 0; i < 8; ++i) {
+        *mpu_rnr = i;
+        if (*mpu_attr & 0x1) {
+            uint32_t base = *mpu_base & MPU_REGION_MASK;
+            uint32_t size = 1 << (((*mpu_attr >> 1) & 0x1F) + 1);
+            if (addr >= base && addr < base + size)
+                return 1;
+        }
+    }
+
+    return 0;
 }
 
 int mpu_select_lru(as_t *as, uint32_t addr)
 {
-	fpage_t *fp = NULL;
-	int i;
-
-	/* Kernel fault? */
-	if (!as)
-		return 1;
-
-	if (addr_in_mpu(addr))
-		return 1;
-
-	fp = as->first;
-	while (fp) {
-		if (addr_in_fpage(addr, fp, 0)) {
-			fpage_t *sfp = as->mpu_stack_first;
-
-			/*
-			 * Fix from f9-riscv commit f88633c:
-			 * Remove fpage from list first to prevent circular list.
-			 * If fp is already in mpu_first list and we prepend without
-			 * removing, we create a cycle that causes infinite loops.
-			 */
-			remove_fpage_from_list(as, fp, mpu_first, mpu_next);
-			fp->mpu_next = as->mpu_first;
-			as->mpu_first = fp;
-
-			/* Get first avalible MPU index */
-			i = 0;
-			while (sfp) {
-				++i;
-				sfp = sfp->mpu_next;
-			}
-
-			/* Update MPU */
-			mpu_setup_region(i++, fp);
-
-			while (i < 8 && fp->mpu_next) {
-				mpu_setup_region(i++, fp->mpu_next);
-				fp = fp->mpu_next;
-			}
-
-			return 0;
-		}
-
-		fp = fp->as_next;
-	}
-
-	return 1;
+    fpage_t *fp = NULL;
+    int i;
+
+    /* Kernel fault? */
+    if (!as)
+        return 1;
+
+    if (addr_in_mpu(addr))
+        return 1;
+
+    fp = as->first;
+    while (fp) {
+        if (addr_in_fpage(addr, fp, 0)) {
+            fpage_t *sfp = as->mpu_stack_first;
+
+            /*
+             * Fix from f9-riscv commit f88633c:
+             * Remove fpage from list first to prevent circular list.
+             * If fp is already in mpu_first list and we prepend without
+             * removing, we create a cycle that causes infinite loops.
+             */
+            remove_fpage_from_list(as, fp, mpu_first, mpu_next);
+            fp->mpu_next = as->mpu_first;
+            as->mpu_first = fp;
+
+            /* Get first avalible MPU index */
+            i = 0;
+            while (sfp) {
+                ++i;
+                sfp = sfp->mpu_next;
+            }
+
+            /* Update MPU */
+            mpu_setup_region(i++, fp);
+
+            while (i < 8 && fp->mpu_next) {
+                mpu_setup_region(i++, fp->mpu_next);
+                fp = fp->mpu_next;
+            }
+
+            return 0;
+        }
+
+        fp = fp->as_next;
+    }
+
+    return 1;
 }
 
 void mpu_dump(int print_title)
 {
-	int i = 0;
-	uint32_t *mpu_rnr = (uint32_t *) MPU_RNR_ADDR;
-	uint32_t *mpu_base = (uint32_t *) MPU_BASE_ADDR;
-	uint32_t *mpu_attr = (uint32_t *) MPU_ATTR_ADDR;
-
-	if (print_title)
-		dbg_printf(DL_EMERG, "-------MPU------\n");
-	for (i = 0; i < 8; i++) {
-		*mpu_rnr = i;
-		if (*mpu_attr & 0x1) {
-			dbg_printf(DL_EMERG,
-			           "b:%p, sz:2**%d, attr:%04x\n", *mpu_base & MPU_REGION_MASK,
-			           ((*mpu_attr & 0x3E) >> 1) + 1, *mpu_attr >> 16);
-		}
-	}
+    int i = 0;
+    uint32_t *mpu_rnr = (uint32_t *) MPU_RNR_ADDR;
+    uint32_t *mpu_base = (uint32_t *) MPU_BASE_ADDR;
+    uint32_t *mpu_attr = (uint32_t *) MPU_ATTR_ADDR;
+
+    if (print_title)
+        dbg_printf(DL_EMERG, "-------MPU------\n");
+    for (i = 0; i < 8; i++) {
+        *mpu_rnr = i;
+        if (*mpu_attr & 0x1) {
+            dbg_printf(DL_EMERG, "b:%p, sz:2**%d, attr:%04x\n",
+                       *mpu_base & MPU_REGION_MASK,
+                       ((*mpu_attr & 0x3E) >> 1) + 1, *mpu_attr >> 16);
+        }
+    }
 }
 
 #ifdef CONFIG_KDB
 void kdb_dump_mpu(void)
 {
-	mpu_dump(0);
+    mpu_dump(0);
 }
 #endif
 
 static void dump_as_fpages(as_t *as)
 {
-	fpage_t *fp = as ? as->first : NULL;
-	int count = 0;
-
-	dbg_printf(DL_EMERG, "---AS fpages---\n");
-	while (fp && count < 16) {
-		dbg_printf(DL_EMERG, "  fp[%d]: base:%p, sz:2**%d\n",
-		           count, FPAGE_BASE(fp), fp->fpage.shift);
-		fp = fp->as_next;
-		count++;
-	}
-	if (fp)
-		dbg_printf(DL_EMERG, "  ... more fpages\n");
+    fpage_t *fp = as ? as->first : NULL;
+    int count = 0;
+
+    dbg_printf(DL_EMERG, "---AS fpages---\n");
+    while (fp && count < 16) {
+        dbg_printf(DL_EMERG, "  fp[%d]: base:%p, sz:2**%d\n", count,
+                   FPAGE_BASE(fp), fp->fpage.shift);
+        fp = fp->as_next;
+        count++;
+    }
+    if (fp)
+        dbg_printf(DL_EMERG, "  ... more fpages\n");
 }
 
 void __memmanage_handler(void)
 {
-	uint32_t mmsr = *((uint32_t *) MPU_FAULT_STATUS_ADDR);
-	uint32_t mmar = *((uint32_t *) MPU_FAULT_ADDRESS_ADDR);
-	tcb_t *current = thread_current();
-	int handled = 0;
-
-	/* Try to handle the fault first before printing diagnostics */
-	if (mmsr & MPU_MEM_FAULT) {
-		if (mpu_select_lru(current->as, mmar) == 0)
-			handled = 1;
-	}
-
-	if (mmsr & MPU_MUSTKERR) {
-		if (mpu_select_lru(current->as, (uint32_t)PSP() + 31) == 0)
-			handled = 1;
-	}
-
-	if (mmsr & MPU_IACCVIOL) {
-		uint32_t pc = PSP()[REG_PC];
-		if (mpu_select_lru(current->as, pc) == 0)
-			handled = 1;
-		else if (mpu_select_lru(current->as, pc + 2) == 0)
-			handled = 1;
-	}
-
-	/* If handled successfully, just clear status and return silently */
-	if (handled) {
-		*((uint32_t *) MPU_FAULT_STATUS_ADDR) = mmsr;
-		return;
-	}
-
-	/* Unhandled fault - show diagnostic info */
-	dbg_printf(DL_EMERG, "MEMFAULT: tid:%t, as:%p (spaceid:%p)\n",
-	           current->t_globalid, current->as,
-	           current->as ? current->as->as_spaceid : 0);
-	dbg_printf(DL_EMERG, "  mmsr:%p, mmar:%p, pc:%p, psp:%p\n",
-	           mmsr, mmar, PSP()[REG_PC], PSP());
-	dbg_printf(DL_EMERG, "  flags: %s%s%s%s%s\n",
-	           (mmsr & MPU_MEM_FAULT) ? "MMARVALID " : "",
-	           (mmsr & MPU_DACCVIOL) ? "DACCVIOL " : "",
-	           (mmsr & MPU_IACCVIOL) ? "IACCVIOL " : "",
-	           (mmsr & MPU_MSTKERR) ? "MSTKERR " : "",
-	           (mmsr & MPU_MUSTKERR) ? "MUSTKERR " : "");
-	dbg_printf(DL_EMERG, "  in_mpu(mmar)=%d, in_mpu(pc)=%d\n",
-	           addr_in_mpu(mmar), addr_in_mpu(PSP()[REG_PC]));
-
-	/* stack errors - always fatal */
-	if (mmsr & MPU_MSTKERR) {
-		panic("Corrupted Stack, current = %t, psp = %p\n",
-		      current->t_globalid, PSP());
-	}
-
-	/* Unhandled fault - dump diagnostics and panic */
-	dump_as_fpages(current->as);
-	mpu_dump(1);
-	panic("Memory fault mmsr:%p, mmar:%p,\n"
-	      "             current:%t, psp:%p, pc:%p\n",
-	      mmsr, mmar, current->t_globalid, PSP(), PSP()[REG_PC]);
+    uint32_t mmsr = *((uint32_t *) MPU_FAULT_STATUS_ADDR);
+    uint32_t mmar = *((uint32_t *) MPU_FAULT_ADDRESS_ADDR);
+    tcb_t *current = thread_current();
+    int handled = 0;
+
+    /* Try to handle the fault first before printing diagnostics */
+    if (mmsr & MPU_MEM_FAULT) {
+        if (mpu_select_lru(current->as, mmar) == 0)
+            handled = 1;
+    }
+
+    if (mmsr & MPU_MUSTKERR) {
+        if (mpu_select_lru(current->as, (uint32_t) PSP() + 31) == 0)
+            handled = 1;
+    }
+
+    if (mmsr & MPU_IACCVIOL) {
+        uint32_t pc = PSP()[REG_PC];
+        if (mpu_select_lru(current->as, pc) == 0)
+            handled = 1;
+        else if (mpu_select_lru(current->as, pc + 2) == 0)
+            handled = 1;
+    }
+
+    /* If handled successfully, just clear status and return silently */
+    if (handled) {
+        *((uint32_t *) MPU_FAULT_STATUS_ADDR) = mmsr;
+        return;
+    }
+
+    /* Unhandled fault - show diagnostic info */
+    dbg_printf(DL_EMERG, "MEMFAULT: tid:%t, as:%p (spaceid:%p)\n",
+               current->t_globalid, current->as,
+               current->as ? current->as->as_spaceid : 0);
+    dbg_printf(DL_EMERG, "  mmsr:%p, mmar:%p, pc:%p, psp:%p\n", mmsr, mmar,
+               PSP()[REG_PC], PSP());
+    dbg_printf(DL_EMERG, "  flags: %s%s%s%s%s\n",
+               (mmsr & MPU_MEM_FAULT) ? "MMARVALID " : "",
+               (mmsr & MPU_DACCVIOL) ? "DACCVIOL " : "",
+               (mmsr & MPU_IACCVIOL) ? "IACCVIOL " : "",
+               (mmsr & MPU_MSTKERR) ? "MSTKERR " : "",
+               (mmsr & MPU_MUSTKERR) ? "MUSTKERR " : "");
+    dbg_printf(DL_EMERG, "  in_mpu(mmar)=%d, in_mpu(pc)=%d\n",
+               addr_in_mpu(mmar), addr_in_mpu(PSP()[REG_PC]));
+
+    /* stack errors - always fatal */
+    if (mmsr & MPU_MSTKERR) {
+        panic("Corrupted Stack, current = %t, psp = %p\n", current->t_globalid,
+              PSP());
+    }
+
+    /* Unhandled fault - dump diagnostics and panic */
+    dump_as_fpages(current->as);
+    mpu_dump(1);
+    panic(
+        "Memory fault mmsr:%p, mmar:%p,\n"
+        "             current:%t, psp:%p, pc:%p\n",
+        mmsr, mmar, current->t_globalid, PSP(), PSP()[REG_PC]);
 }
 
 IRQ_HANDLER(memmanage_handler, __memmanage_handler);
diff --git a/platform/stm32-common/nvic.c b/platform/stm32-common/nvic.c
index c4e098e4..e58f4fa4 100644
--- a/platform/stm32-common/nvic.c
+++ b/platform/stm32-common/nvic.c
@@ -9,57 +9,58 @@
 
 #include INC_PLAT(nvic.c)
 
-#define AIRCR_VECTKEY_MASK    ((uint32_t) 0x05FA0000)
+#define AIRCR_VECTKEY_MASK ((uint32_t) 0x05FA0000)
 
 void _undefined_handler(void)
 {
-	while (1)
-		/* wait */ ;
+    while (1)
+        /* wait */;
 }
 
 /* for the sake of saving space, provide default device IRQ handler with
  * weak alias.
  */
-#define DEFAULT_IRQ_VEC(n)						\
-	void nvic_handler##n(void)					\
-		__attribute__((weak, alias("_undefined_handler")));
+#define DEFAULT_IRQ_VEC(n)     \
+    void nvic_handler##n(void) \
+        __attribute__((weak, alias("_undefined_handler")));
 
-#define IRQ_VEC_N_OP	DEFAULT_IRQ_VEC
+#define IRQ_VEC_N_OP DEFAULT_IRQ_VEC
 #include INC_PLAT(nvic_private.h)
 #undef IRQ_VEC_N_OP
 
-extern void (* const g_pfnVectors[])(void);
+extern void (*const g_pfnVectors[])(void);
 int nvic_is_setup(int irq)
 {
-	return !(g_pfnVectors[irq + 16] == _undefined_handler);
+    return !(g_pfnVectors[irq + 16] == _undefined_handler);
 }
 
 void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
 {
-	if (!(NVIC_PriorityGroup == NVIC_PriorityGroup_0 ||
-	      NVIC_PriorityGroup == NVIC_PriorityGroup_1 ||
-	      NVIC_PriorityGroup == NVIC_PriorityGroup_2 ||
-	      NVIC_PriorityGroup == NVIC_PriorityGroup_3 ||
-	      NVIC_PriorityGroup == NVIC_PriorityGroup_4))
-		return;
+    if (!(NVIC_PriorityGroup == NVIC_PriorityGroup_0 ||
+          NVIC_PriorityGroup == NVIC_PriorityGroup_1 ||
+          NVIC_PriorityGroup == NVIC_PriorityGroup_2 ||
+          NVIC_PriorityGroup == NVIC_PriorityGroup_3 ||
+          NVIC_PriorityGroup == NVIC_PriorityGroup_4))
+        return;
 
-	*SCB_AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+    *SCB_AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
 }
 
-void NVIC_SetPriority(IRQn_Type IRQn, uint8_t group_priority,
+void NVIC_SetPriority(IRQn_Type IRQn,
+                      uint8_t group_priority,
                       uint8_t sub_priority)
 {
-	uint8_t priority = 0x0, group_shifts = 0x0, sub_shifts = 0x0;
+    uint8_t priority = 0x0, group_shifts = 0x0, sub_shifts = 0x0;
 
-	sub_shifts = (0x700 - ((*SCB_AIRCR) & (uint32_t) 0x700)) >> 0x08;
-	group_shifts = 0x4 - sub_shifts;
+    sub_shifts = (0x700 - ((*SCB_AIRCR) & (uint32_t) 0x700)) >> 0x08;
+    group_shifts = 0x4 - sub_shifts;
 
-	priority = (group_priority << group_shifts) |
-	           (sub_priority & (0xf >> sub_shifts));
+    priority =
+        (group_priority << group_shifts) | (sub_priority & (0xf >> sub_shifts));
 
-	if (IRQn < 0)
-		((volatile uint8_t *) SCB_SHPR)[
-		        (((uint32_t) IRQn) & 0xf) - 4] = priority << 0x4;
-	else
-		NVIC->IP[IRQn] = priority << 0x4;
+    if (IRQn < 0)
+        ((volatile uint8_t *) SCB_SHPR)[(((uint32_t) IRQn) & 0xf) - 4] =
+            priority << 0x4;
+    else
+        NVIC->IP[IRQn] = priority << 0x4;
 }
diff --git a/platform/stm32-common/rcc.c b/platform/stm32-common/rcc.c
index 7f989d84..c0f8038f 100644
--- a/platform/stm32-common/rcc.c
+++ b/platform/stm32-common/rcc.c
@@ -3,183 +3,182 @@
  * found in the LICENSE file.
  */
 #include INC_PLAT(rcc.h)
-#include <platform/cortex_m.h>
 #include <error.h>
+#include <platform/cortex_m.h>
 #include INC_PLAT(rcc.c)
 
 #define HSE_STARTUP_TIMEOUT \
-	(uint16_t) (0x0500)	/*!< Time out for HSE start up */
+    (uint16_t) (0x0500) /*!< Time out for HSE start up */
 
 #if defined(STM32F4X)
-	#define PLL_M	8	/*!< PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
-	#define PLL_N	336
-	#define PLL_P	2	/*!< SYSCLK = PLL_VCO / PLL_P */
-	#define PLL_Q	7	/*!< USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
+#define PLL_M 8 /*!< PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
+#define PLL_N 336
+#define PLL_P 2 /*!< SYSCLK = PLL_VCO / PLL_P */
+#define PLL_Q 7 /*!< USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
 
-static __USER_DATA uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static __USER_DATA uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4,
+                                                   1, 2, 3, 4, 6, 7, 8, 9};
 #elif defined(STM32F1X)
-	#define PLL_MUL	6
+#define PLL_MUL 6
 #endif
 
 /* RCC Flag Mask */
-#define FLAG_MASK                 ((uint8_t)0x1F)
+#define FLAG_MASK ((uint8_t) 0x1F)
 
 
 void sys_clock_init(void)
 {
-	volatile uint32_t startup_count, HSE_status;
+    volatile uint32_t startup_count, HSE_status;
 
 #if defined(STM32F4X) && defined(CONFIG_FPU)
-	/* Enable the FPU */
-	*SCB_CPACR |= (0xf << 20);
-	/* Enable floating point state preservation */
-	*FPU_CCR |= FPU_CCR_ASPEN;
+    /* Enable the FPU */
+    *SCB_CPACR |= (0xf << 20);
+    /* Enable floating point state preservation */
+    *FPU_CCR |= FPU_CCR_ASPEN;
 #endif
-	/* Reset clock registers */
-	/* Set HSION bit */
-	*RCC_CR |= (uint32_t) 0x00000001;
+    /* Reset clock registers */
+    /* Set HSION bit */
+    *RCC_CR |= (uint32_t) 0x00000001;
 
 #if defined(STM32F1X)
-	*RCC_CFGR &= (uint32_t)0xF0FF0000;
+    *RCC_CFGR &= (uint32_t) 0xF0FF0000;
 #else
-	/* Reset CFGR register */
-	*RCC_CFGR = 0x00000000;
+    /* Reset CFGR register */
+    *RCC_CFGR = 0x00000000;
 #endif
-	/* Reset HSEON, CSSON and PLLON bits */
-	*RCC_CR &= (uint32_t) 0xFEF6FFFF;
+    /* Reset HSEON, CSSON and PLLON bits */
+    *RCC_CR &= (uint32_t) 0xFEF6FFFF;
 
 #if defined(STM32F4X)
-	/* Reset PLLCFGR register */
-	*RCC_PLLCFGR = 0x24003010;
+    /* Reset PLLCFGR register */
+    *RCC_PLLCFGR = 0x24003010;
 #elif defined(STM32F1X)
-	*RCC_CFGR &= (uint32_t)0xFF80FFFF;
+    *RCC_CFGR &= (uint32_t) 0xFF80FFFF;
 #endif
-	/* Reset HSEBYP bit */
-	*RCC_CR &= (uint32_t) 0xFFFBFFFF;
+    /* Reset HSEBYP bit */
+    *RCC_CR &= (uint32_t) 0xFFFBFFFF;
 
-	/* Disable all interrupts */
+    /* Disable all interrupts */
 #if defined(STM32F4X)
-	*RCC_CIR = 0x00000000;
+    *RCC_CIR = 0x00000000;
 #elif defined(STM32F1X)
-	*RCC_CIR = 0x009F0000;
+    *RCC_CIR = 0x009F0000;
 #endif
 
-	/* Set up the clock */
-	startup_count = 0;
-	HSE_status = 0;
-
-	/* Enable HSE */
-	*RCC_CR |= RCC_CR_HSEON;
-
-	/* Wait till HSE is ready and if Time out is reached exit */
-	do {
-		HSE_status = *RCC_CR & RCC_CR_HSERDY;
-		startup_count++;
-	} while ((HSE_status == 0) && (startup_count != HSE_STARTUP_TIMEOUT));
-
-	if ((*RCC_CR & RCC_CR_HSERDY) != 0) {
-		HSE_status = (uint32_t) 0x01;
-	} else {
-		HSE_status = (uint32_t) 0x00;
-	}
-
-	if (HSE_status == (uint32_t) 0x01) {
-		/* Enable high performance mode:
-		   system frequency is up to 168 MHz */
-		*RCC_APB1ENR |= RCC_APB1ENR_PWREN;
+    /* Set up the clock */
+    startup_count = 0;
+    HSE_status = 0;
+
+    /* Enable HSE */
+    *RCC_CR |= RCC_CR_HSEON;
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do {
+        HSE_status = *RCC_CR & RCC_CR_HSERDY;
+        startup_count++;
+    } while ((HSE_status == 0) && (startup_count != HSE_STARTUP_TIMEOUT));
+
+    if ((*RCC_CR & RCC_CR_HSERDY) != 0) {
+        HSE_status = (uint32_t) 0x01;
+    } else {
+        HSE_status = (uint32_t) 0x00;
+    }
+
+    if (HSE_status == (uint32_t) 0x01) {
+        /* Enable high performance mode:
+           system frequency is up to 168 MHz */
+        *RCC_APB1ENR |= RCC_APB1ENR_PWREN;
 #if defined(STM32F4X)
-		*PWR_CR |= PWR_CR_VOS;
+        *PWR_CR |= PWR_CR_VOS;
 #endif
-		/* HCLK = SYSCLK / 1 */
-		*RCC_CFGR |= RCC_CFGR_HPRE_DIV1;
+        /* HCLK = SYSCLK / 1 */
+        *RCC_CFGR |= RCC_CFGR_HPRE_DIV1;
 
-		/* PCLK2 = HCLK / 2 */
-		*RCC_CFGR |= RCC_CFGR_PPRE2_DIV2;
+        /* PCLK2 = HCLK / 2 */
+        *RCC_CFGR |= RCC_CFGR_PPRE2_DIV2;
 
-		/* PCLK1 = HCLK / 4 */
-		*RCC_CFGR |= RCC_CFGR_PPRE1_DIV4;
+        /* PCLK1 = HCLK / 4 */
+        *RCC_CFGR |= RCC_CFGR_PPRE1_DIV4;
 
-		/* Configure the main PLL */
+        /* Configure the main PLL */
 #if defined(STM32F4X)
-		/* PLL Options - See RM0090 Reference Manual pg. 95 */
-		*RCC_PLLCFGR = PLL_M | (PLL_N << 6) |
-		               (((PLL_P >> 1) - 1) << 16) |
-		               (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
+        /* PLL Options - See RM0090 Reference Manual pg. 95 */
+        *RCC_PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) - 1) << 16) |
+                       (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
 #elif defined(STM32F1X)
-		*RCC_CFGR |= PLL_MUL << 18;
+        *RCC_CFGR |= PLL_MUL << 18;
 #endif
-		/* Enable the main PLL */
-		*RCC_CR |= RCC_CR_PLLON;
+        /* Enable the main PLL */
+        *RCC_CR |= RCC_CR_PLLON;
 
-		/* Wait till the main PLL is ready */
-		while ((*RCC_CR & RCC_CR_PLLRDY) == 0)
-			/* wait */ ;
+        /* Wait till the main PLL is ready */
+        while ((*RCC_CR & RCC_CR_PLLRDY) == 0)
+            /* wait */;
 
-		/* Configure Flash prefetch, Instruction cache,
-		 * Data cache and wait state
-		 */
+        /* Configure Flash prefetch, Instruction cache,
+         * Data cache and wait state
+         */
 #if 0
 		*FLASH_ACR = FLASH_ACR_ICEN | FLASH_ACR_DCEN |
 		             FLASH_ACR_LATENCY_5WS;
 #endif
 #if defined(STM32F4X)
-		*FLASH_ACR = FLASH_ACR_LATENCY(5);
+        *FLASH_ACR = FLASH_ACR_LATENCY(5);
 #elif defined(STM32F1X)
-		*FLASH_ACR = FLASH_ACR_LATENCY(1);
+        *FLASH_ACR = FLASH_ACR_LATENCY(1);
 #endif
-		/* Select the main PLL as system clock source */
-		*RCC_CFGR &= (uint32_t)((uint32_t) ~(RCC_CFGR_SW_M));
-		*RCC_CFGR |= RCC_CFGR_SW_PLL;
-
-		/* Wait till the main PLL is used as system clock source */
-		while ((*RCC_CFGR & (uint32_t) RCC_CFGR_SWS_M) !=
-		       RCC_CFGR_SWS_PLL)
-			/* wait */ ;
-	} else {
-		/* HSE failed to start - fall back to HSI.
-		 * This is expected when running under QEMU emulation.
-		 * Use HSI (16MHz) as system clock directly without PLL.
-		 */
+        /* Select the main PLL as system clock source */
+        *RCC_CFGR &= (uint32_t) ((uint32_t) ~(RCC_CFGR_SW_M));
+        *RCC_CFGR |= RCC_CFGR_SW_PLL;
+
+        /* Wait till the main PLL is used as system clock source */
+        while ((*RCC_CFGR & (uint32_t) RCC_CFGR_SWS_M) != RCC_CFGR_SWS_PLL)
+            /* wait */;
+    } else {
+        /* HSE failed to start - fall back to HSI.
+         * This is expected when running under QEMU emulation.
+         * Use HSI (16MHz) as system clock directly without PLL.
+         */
 #if defined(STM32F4X)
-		/* Configure Flash latency for 16MHz (HSI) */
-		*FLASH_ACR = FLASH_ACR_LATENCY(0);
+        /* Configure Flash latency for 16MHz (HSI) */
+        *FLASH_ACR = FLASH_ACR_LATENCY(0);
 
-		/* Select HSI as system clock source (SW = 00) */
-		*RCC_CFGR &= (uint32_t)((uint32_t) ~(RCC_CFGR_SW_M));
+        /* Select HSI as system clock source (SW = 00) */
+        *RCC_CFGR &= (uint32_t) ((uint32_t) ~(RCC_CFGR_SW_M));
 
-		/* Wait till HSI is used as system clock source */
-		while ((*RCC_CFGR & (uint32_t) RCC_CFGR_SWS_M) != 0)
-			/* wait */ ;
+        /* Wait till HSI is used as system clock source */
+        while ((*RCC_CFGR & (uint32_t) RCC_CFGR_SWS_M) != 0)
+            /* wait */;
 #endif
-	}
+    }
 #if defined(STM32F4X)
-	/* Enable the CCM RAM clock */
-	*RCC_AHB1ENR |= (1 << 20);
+    /* Enable the CCM RAM clock */
+    *RCC_AHB1ENR |= (1 << 20);
 #endif
-	/* Enable Bus and Usage Faults */
-	*SCB_SHCSR |= SCB_SHCSR_BUSFAULTENA;
-	*SCB_SHCSR |= SCB_SHCSR_USEFAULTENA;
+    /* Enable Bus and Usage Faults */
+    *SCB_SHCSR |= SCB_SHCSR_BUSFAULTENA;
+    *SCB_SHCSR |= SCB_SHCSR_USEFAULTENA;
 }
 
 #if defined(STM32F4X)
 void __USER_TEXT RCC_AHB1PeriphClockCmd(uint32_t rcc_AHB1, uint8_t enable)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	if (enable != 0)
-		*RCC_AHB1ENR |= rcc_AHB1;
-	else
-		*RCC_AHB1ENR &= ~rcc_AHB1;
+    if (enable != 0)
+        *RCC_AHB1ENR |= rcc_AHB1;
+    else
+        *RCC_AHB1ENR &= ~rcc_AHB1;
 
 #elif defined(STM32F1X)
 void __USER_TEXT RCC_AHBPeriphClockCmd(uint32_t rcc_AHB, uint8_t enable)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	if (enable != 0)
-		*RCC_AHBENR |= rcc_AHB;
-	else
-		*RCC_AHBENR &= ~rcc_AHB;
+    if (enable != 0)
+        *RCC_AHBENR |= rcc_AHB;
+    else
+        *RCC_AHBENR &= ~rcc_AHB;
 
 #endif
 }
@@ -187,138 +186,140 @@ void __USER_TEXT RCC_AHBPeriphClockCmd(uint32_t rcc_AHB, uint8_t enable)
 #if defined(STM32F4X)
 void __USER_TEXT RCC_AHB1PeriphResetCmd(uint32_t rcc_AHB1, uint8_t enable)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	if (enable != 0)
-		*RCC_AHB1RSTR |= rcc_AHB1;
-	else
-		*RCC_AHB1RSTR &= ~rcc_AHB1;
+    if (enable != 0)
+        *RCC_AHB1RSTR |= rcc_AHB1;
+    else
+        *RCC_AHB1RSTR &= ~rcc_AHB1;
 
 #elif defined(STM32F1X)
 void __USER_TEXT RCC_AHBPeriphResetCmd(uint32_t rcc_AHB, uint8_t enable)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	if (enable != 0)
-		*RCC_AHBRSTR |= rcc_AHB;
-	else
-		*RCC_AHBRSTR &= ~rcc_AHB;
+    if (enable != 0)
+        *RCC_AHBRSTR |= rcc_AHB;
+    else
+        *RCC_AHBRSTR &= ~rcc_AHB;
 
 #endif
 }
 
 void __USER_TEXT RCC_APB1PeriphClockCmd(uint32_t rcc_APB1, uint8_t enable)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	if (enable != 0)
-		*RCC_APB1ENR |= rcc_APB1;
-	else
-		*RCC_APB1ENR &= ~rcc_APB1;
+    if (enable != 0)
+        *RCC_APB1ENR |= rcc_APB1;
+    else
+        *RCC_APB1ENR &= ~rcc_APB1;
 }
 
 void __USER_TEXT RCC_APB1PeriphResetCmd(uint32_t rcc_APB1, uint8_t enable)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	if (enable != 0)
-		*RCC_APB1RSTR |= rcc_APB1;
-	else
-		*RCC_APB1RSTR &= ~rcc_APB1;
+    if (enable != 0)
+        *RCC_APB1RSTR |= rcc_APB1;
+    else
+        *RCC_APB1RSTR &= ~rcc_APB1;
 }
 
 void __USER_TEXT RCC_APB2PeriphClockCmd(uint32_t rcc_APB2, uint8_t enable)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	if (enable != 0)
-		*RCC_APB2ENR |= rcc_APB2;
-	else
-		*RCC_APB2ENR &= ~rcc_APB2;
+    if (enable != 0)
+        *RCC_APB2ENR |= rcc_APB2;
+    else
+        *RCC_APB2ENR &= ~rcc_APB2;
 }
 
 void __USER_TEXT RCC_APB2PeriphResetCmd(uint32_t rcc_APB2, uint8_t enable)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	if (enable != 0)
-		*RCC_APB2RSTR |= rcc_APB2;
-	else
-		*RCC_APB2RSTR &= ~rcc_APB2;
+    if (enable != 0)
+        *RCC_APB2RSTR |= rcc_APB2;
+    else
+        *RCC_APB2RSTR &= ~rcc_APB2;
 }
 
 uint8_t __USER_TEXT RCC_GetFlagStatus(uint8_t flag)
 {
-	uint32_t tmp = 0;
-	uint32_t statusreg = 0;
-	uint8_t bitstatus = 0;
-
-	/* TODO: assertion */
-
-	tmp = flag >> 5;
-	if (tmp == 1)
-		statusreg = *RCC_CR;
-	else if (tmp == 2)
-		statusreg = *RCC_BDCR;
-	else
-		statusreg = *RCC_CSR;
-
-	tmp = flag & FLAG_MASK;
-	if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)0)
-		bitstatus = 1;
-	else
-		bitstatus = 0;
-
-	return bitstatus;
+    uint32_t tmp = 0;
+    uint32_t statusreg = 0;
+    uint8_t bitstatus = 0;
+
+    /* TODO: assertion */
+
+    tmp = flag >> 5;
+    if (tmp == 1)
+        statusreg = *RCC_CR;
+    else if (tmp == 2)
+        statusreg = *RCC_BDCR;
+    else
+        statusreg = *RCC_CSR;
+
+    tmp = flag & FLAG_MASK;
+    if ((statusreg & ((uint32_t) 1 << tmp)) != (uint32_t) 0)
+        bitstatus = 1;
+    else
+        bitstatus = 0;
+
+    return bitstatus;
 }
 
 void __USER_TEXT RCC_GetClocksFreq(struct rcc_clocks *clock)
 {
 #if defined(STM32F4X)
-	uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-
-	tmp = *RCC_CFGR & RCC_CFGR_SWS_M;
-
-	switch (tmp) {
-	case 0x00:
-		clock->sysclk_freq = HSI_VALUE;
-		break;
-	case 0x04:
-		clock->sysclk_freq = HSE_VALUE;
-		break;
-	case 0x08:
-		pllsource = (*RCC_PLLCFGR & RCC_PLLCFGR_PLLSRC_HSE) >> 22;
-		pllm = *RCC_PLLCFGR & RCC_PLLCFGR_PLLM;
-
-		if (pllsource != 0)
-			pllvco = (HSE_VALUE / pllm) * ((*RCC_PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
-		else
-			pllvco = (HSI_VALUE / pllm) * ((*RCC_PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
-
-		pllp = (((*RCC_PLLCFGR & RCC_PLLCFGR_PLLP) >> 16) + 1) * 2;
-		clock->sysclk_freq = pllvco / pllp;
-		break;
-	default:
-		clock->sysclk_freq = HSI_VALUE;
-		break;
-	}
-
-	tmp = *RCC_CFGR & RCC_CFGR_HPRE_M;
-	tmp = tmp >> 4;
-	presc = APBAHBPrescTable[tmp];
-
-	clock->hclk_freq = clock->sysclk_freq >> presc;
-
-	tmp = *RCC_CFGR & RCC_CFGR_PPRE1_M;
-	tmp = tmp >> 10;
-	presc = APBAHBPrescTable[tmp];
-
-	clock->pclk1_freq = clock->hclk_freq >> presc;
-
-	tmp = *RCC_CFGR & RCC_CFGR_PPRE2_M;
-	tmp = tmp >> 13;
-	presc = APBAHBPrescTable[tmp];
-
-	clock->pclk2_freq = clock->hclk_freq >> presc;
+    uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+
+    tmp = *RCC_CFGR & RCC_CFGR_SWS_M;
+
+    switch (tmp) {
+    case 0x00:
+        clock->sysclk_freq = HSI_VALUE;
+        break;
+    case 0x04:
+        clock->sysclk_freq = HSE_VALUE;
+        break;
+    case 0x08:
+        pllsource = (*RCC_PLLCFGR & RCC_PLLCFGR_PLLSRC_HSE) >> 22;
+        pllm = *RCC_PLLCFGR & RCC_PLLCFGR_PLLM;
+
+        if (pllsource != 0)
+            pllvco =
+                (HSE_VALUE / pllm) * ((*RCC_PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+        else
+            pllvco =
+                (HSI_VALUE / pllm) * ((*RCC_PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+
+        pllp = (((*RCC_PLLCFGR & RCC_PLLCFGR_PLLP) >> 16) + 1) * 2;
+        clock->sysclk_freq = pllvco / pllp;
+        break;
+    default:
+        clock->sysclk_freq = HSI_VALUE;
+        break;
+    }
+
+    tmp = *RCC_CFGR & RCC_CFGR_HPRE_M;
+    tmp = tmp >> 4;
+    presc = APBAHBPrescTable[tmp];
+
+    clock->hclk_freq = clock->sysclk_freq >> presc;
+
+    tmp = *RCC_CFGR & RCC_CFGR_PPRE1_M;
+    tmp = tmp >> 10;
+    presc = APBAHBPrescTable[tmp];
+
+    clock->pclk1_freq = clock->hclk_freq >> presc;
+
+    tmp = *RCC_CFGR & RCC_CFGR_PPRE2_M;
+    tmp = tmp >> 13;
+    presc = APBAHBPrescTable[tmp];
+
+    clock->pclk2_freq = clock->hclk_freq >> presc;
 #endif
 }
diff --git a/platform/stm32-common/systick.c b/platform/stm32-common/systick.c
index 300e8ff1..fb9d1c9f 100644
--- a/platform/stm32-common/systick.c
+++ b/platform/stm32-common/systick.c
@@ -10,26 +10,26 @@
 
 void init_systick(uint32_t tick_reload, uint32_t tick_next_reload)
 {
-	/* 250us at 168Mhz */
-	*SYSTICK_RELOAD = tick_reload - 1;
-	*SYSTICK_VAL = 0;
-	*SYSTICK_CTL = 0x00000007;
+    /* 250us at 168Mhz */
+    *SYSTICK_RELOAD = tick_reload - 1;
+    *SYSTICK_VAL = 0;
+    *SYSTICK_CTL = 0x00000007;
 
-	if (tick_next_reload)
-		*SYSTICK_RELOAD = tick_next_reload - 1;
+    if (tick_next_reload)
+        *SYSTICK_RELOAD = tick_next_reload - 1;
 }
 
 void systick_disable()
 {
-	*SYSTICK_CTL = 0x00000000;
+    *SYSTICK_CTL = 0x00000000;
 }
 
 uint32_t systick_now()
 {
-	return *SYSTICK_VAL;
+    return *SYSTICK_VAL;
 }
 
 uint32_t systick_flag_count()
 {
-	return (*SYSTICK_CTL & (1 << 16)) >> 16;
+    return (*SYSTICK_CTL & (1 << 16)) >> 16;
 }
diff --git a/platform/stm32-common/usart.c b/platform/stm32-common/usart.c
index 7c7a1530..d2a1ca74 100644
--- a/platform/stm32-common/usart.c
+++ b/platform/stm32-common/usart.c
@@ -9,129 +9,128 @@
 #include INC_PLAT(usart.c)
 
 struct usart_regs {
-	volatile uint16_t SR;
-	uint16_t reserved0;
-	volatile uint16_t DR;
-	uint16_t reserved1;
-	volatile uint16_t BRR;
-	uint16_t reserved2;
-	volatile uint16_t CR1;
-	uint16_t reserved3;
-	volatile uint16_t CR2;
-	uint16_t reserved4;
-	volatile uint16_t CR3;
-	uint16_t reserved5;
-	volatile uint16_t GTPR;
-	uint16_t reserved6;
+    volatile uint16_t SR;
+    uint16_t reserved0;
+    volatile uint16_t DR;
+    uint16_t reserved1;
+    volatile uint16_t BRR;
+    uint16_t reserved2;
+    volatile uint16_t CR1;
+    uint16_t reserved3;
+    volatile uint16_t CR2;
+    uint16_t reserved4;
+    volatile uint16_t CR3;
+    uint16_t reserved5;
+    volatile uint16_t GTPR;
+    uint16_t reserved6;
 };
 
 /* Calculates the value for the USART_BRR */
 /* TODO: Need more precise algorithm */
 static int16_t usart_baud(uint32_t base, uint32_t baud)
 {
-	uint16_t mantissa;
-	uint16_t fraction;
-	uint32_t apb_clock;
-
-	/* Detect system clock source to determine actual APB frequencies.
-	 * When HSE fails (common in QEMU), we fall back to HSI (16MHz)
-	 * with no PLL, so APB clocks are different from PLL case.
-	 */
-	uint32_t sws = *RCC_CFGR & RCC_CFGR_SWS_M;
-
-	if (sws == RCC_CFGR_SWS_PLL) {
-		/* PLL is system clock: SYSCLK=168MHz, APB1=42MHz, APB2=84MHz */
-		if (base == USART1_BASE)
-			apb_clock = 84000000;	/* APB2 for USART1/6 */
-		else
-			apb_clock = 42000000;	/* APB1 for USART2-5 */
-	} else {
-		/* HSI or HSE without PLL: assume 16MHz with no prescalers */
-		apb_clock = 16000000;
-	}
-
-	mantissa = apb_clock / (16 * baud);
-	fraction = (apb_clock / baud) % 16;
-
-	return (mantissa << 4) | fraction;
+    uint16_t mantissa;
+    uint16_t fraction;
+    uint32_t apb_clock;
+
+    /* Detect system clock source to determine actual APB frequencies.
+     * When HSE fails (common in QEMU), we fall back to HSI (16MHz)
+     * with no PLL, so APB clocks are different from PLL case.
+     */
+    uint32_t sws = *RCC_CFGR & RCC_CFGR_SWS_M;
+
+    if (sws == RCC_CFGR_SWS_PLL) {
+        /* PLL is system clock: SYSCLK=168MHz, APB1=42MHz, APB2=84MHz */
+        if (base == USART1_BASE)
+            apb_clock = 84000000; /* APB2 for USART1/6 */
+        else
+            apb_clock = 42000000; /* APB1 for USART2-5 */
+    } else {
+        /* HSI or HSE without PLL: assume 16MHz with no prescalers */
+        apb_clock = 16000000;
+    }
+
+    mantissa = apb_clock / (16 * baud);
+    fraction = (apb_clock / baud) % 16;
+
+    return (mantissa << 4) | fraction;
 }
 
-void usart_config_interrupt(struct usart_dev *usart, uint16_t it,
-                            uint8_t state)
+void usart_config_interrupt(struct usart_dev *usart, uint16_t it, uint8_t state)
 {
-	uint32_t it_reg, it_bit;
+    uint32_t it_reg, it_bit;
 
-	if (it == USART_IT_CTS && (usart->u_num == 4 || usart->u_num == 5))
-		return;
+    if (it == USART_IT_CTS && (usart->u_num == 4 || usart->u_num == 5))
+        return;
 
-	it_reg = usart->base + USART_IT_ENB_REG_OFFSET(it);
-	it_bit = (0x1 << USART_IT_POSITION(it));
+    it_reg = usart->base + USART_IT_ENB_REG_OFFSET(it);
+    it_bit = (0x1 << USART_IT_POSITION(it));
 
-	if (state)
-		*(volatile uint32_t *) it_reg |= it_bit;
-	else
-		*(volatile uint32_t *) it_reg &= ~it_bit;
+    if (state)
+        *(volatile uint32_t *) it_reg |= it_bit;
+    else
+        *(volatile uint32_t *) it_reg &= ~it_bit;
 }
 
 int usart_interrupt_status(struct usart_dev *usart, uint16_t it)
 {
-	uint32_t it_reg, it_bit;
+    uint32_t it_reg, it_bit;
 
-	if (it == USART_IT_CTS && (usart->u_num == 4 || usart->u_num == 5))
-		return 0;
+    if (it == USART_IT_CTS && (usart->u_num == 4 || usart->u_num == 5))
+        return 0;
 
-	it_reg = usart->base + USART_IT_ENB_REG_OFFSET(it);
-	it_bit = (0x1 << USART_IT_POSITION(it));
+    it_reg = usart->base + USART_IT_ENB_REG_OFFSET(it);
+    it_bit = (0x1 << USART_IT_POSITION(it));
 
-	return (*(volatile uint32_t *) it_reg & it_bit);
+    return (*(volatile uint32_t *) it_reg & it_bit);
 }
 
 int usart_status(struct usart_dev *usart, uint16_t st)
 {
-	struct usart_regs *uregs;
+    struct usart_regs *uregs;
 
-	uregs = (struct usart_regs *) usart->base;
+    uregs = (struct usart_regs *) usart->base;
 
-	return (uregs->SR & st);
+    return (uregs->SR & st);
 }
 
 uint8_t usart_getc(struct usart_dev *usart)
 {
-	struct usart_regs *uregs;
+    struct usart_regs *uregs;
 
-	uregs = (struct usart_regs *) usart->base;
-	return (uregs->DR & 0xff);
+    uregs = (struct usart_regs *) usart->base;
+    return (uregs->DR & 0xff);
 }
 
 void usart_putc(struct usart_dev *usart, uint8_t c)
 {
-	struct usart_regs *uregs;
+    struct usart_regs *uregs;
 
-	uregs = (struct usart_regs *) usart->base;
-	uregs->DR = c;
+    uregs = (struct usart_regs *) usart->base;
+    uregs->DR = c;
 }
 
 void usart_init(struct usart_dev *usart)
 {
-	struct usart_regs *uregs;
+    struct usart_regs *uregs;
 
-	*(usart->rcc_apbenr) |= usart->rcc_reset;
-	gpio_config(&usart->tx);
-	gpio_config(&usart->rx);
+    *(usart->rcc_apbenr) |= usart->rcc_reset;
+    gpio_config(&usart->tx);
+    gpio_config(&usart->rx);
 
-	uregs = (struct usart_regs *) usart->base;
+    uregs = (struct usart_regs *) usart->base;
 
-	uregs->CR1 |= USART_CR1_UE;
+    uregs->CR1 |= USART_CR1_UE;
 
-	/* FIXME: Hardcode 8-bit */
-	uregs->CR1 &= ~(USART_CR1_M9);
+    /* FIXME: Hardcode 8-bit */
+    uregs->CR1 &= ~(USART_CR1_M9);
 
-	/* FIXME: Hardcode 1 stop bit */
-	uregs->CR2 &= ~(3 << 12);
+    /* FIXME: Hardcode 1 stop bit */
+    uregs->CR2 &= ~(3 << 12);
 
-	/* Set baud rate */
-	uregs->BRR = usart_baud(usart->base, usart->baud);
+    /* Set baud rate */
+    uregs->BRR = usart_baud(usart->base, usart->baud);
 
-	/* Enable reciever and transmitter */
-	uregs->CR1 |= (USART_CR1_RE | USART_CR1_TE);
+    /* Enable reciever and transmitter */
+    uregs->CR1 |= (USART_CR1_RE | USART_CR1_TE);
 }
diff --git a/platform/stm32f429/dma2d.c b/platform/stm32f429/dma2d.c
index 615e3e0d..86159137 100644
--- a/platform/stm32f429/dma2d.c
+++ b/platform/stm32f429/dma2d.c
@@ -1,79 +1,79 @@
 #include <platform/stm32f429/dma2d.h>
 #include <platform/stm32f429/rcc.h>
 
-//CR MASK
-#define CR_MASK                     ((uint32_t)0xFFFCE0FC)
+// CR MASK
+#define CR_MASK ((uint32_t) 0xFFFCE0FC)
 
 void __USER_TEXT dma2d_reset(void)
 {
-	RCC_AHB1PeriphResetCmd(RCC_AHB1ENR_DMA2DEN, 1);
-	RCC_AHB1PeriphResetCmd(RCC_AHB1ENR_DMA2DEN, 0);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1ENR_DMA2DEN, 1);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1ENR_DMA2DEN, 0);
 }
 
 void __USER_TEXT dma2d_config(struct dma2d_cfg *cfg)
 {
-	uint32_t outgreen = 0;
-	uint32_t outred = 0;
-	uint32_t outalpha = 0;
-	uint32_t pixline = 0;
+    uint32_t outgreen = 0;
+    uint32_t outred = 0;
+    uint32_t outalpha = 0;
+    uint32_t pixline = 0;
 
-	//TODO: assertion
+    // TODO: assertion
 
-	*DMA2D_CR &= (uint32_t)CR_MASK;
-	*DMA2D_CR |= (cfg->mode);
+    *DMA2D_CR &= (uint32_t) CR_MASK;
+    *DMA2D_CR |= (cfg->mode);
 
-	*DMA2D_OPFCCR &= ~(uint32_t)DMA2D_OPFCCR_CM;
-	*DMA2D_OPFCCR |= (cfg->cmode);
+    *DMA2D_OPFCCR &= ~(uint32_t) DMA2D_OPFCCR_CM;
+    *DMA2D_OPFCCR |= (cfg->cmode);
 
-	if (cfg->cmode == DMA2D_ARGB8888) {
-		outgreen = cfg->output_green << 8;
-		outred = cfg->output_red << 16;
-		outalpha = cfg->output_alpha << 24;
-	} else if (cfg->cmode == DMA2D_RGB888) {
-		outgreen = cfg->output_green << 8;
-		outred = cfg->output_red << 16;
-		outalpha = (uint32_t)0x00000000;
-	} else if (cfg->cmode == DMA2D_RGB565) {
-		outgreen = cfg->output_green << 5;
-		outred = cfg->output_red << 11;
-		outalpha = (uint32_t)0x00000000;
-	} else if (cfg->cmode == DMA2D_ARGB1555) {
-		outgreen = cfg->output_green << 5;
-		outred = cfg->output_red << 10;
-		outalpha = cfg->output_alpha << 15;
-	} else {
-		// DMA2D_ARGB4444
-		outgreen = cfg->output_green << 4;
-		outred = cfg->output_red << 8;
-		outalpha = cfg->output_alpha << 12;
-	}
-	*DMA2D_OCOLR |= ((outgreen) | (outred) | (cfg->output_blue) | (outalpha));
+    if (cfg->cmode == DMA2D_ARGB8888) {
+        outgreen = cfg->output_green << 8;
+        outred = cfg->output_red << 16;
+        outalpha = cfg->output_alpha << 24;
+    } else if (cfg->cmode == DMA2D_RGB888) {
+        outgreen = cfg->output_green << 8;
+        outred = cfg->output_red << 16;
+        outalpha = (uint32_t) 0x00000000;
+    } else if (cfg->cmode == DMA2D_RGB565) {
+        outgreen = cfg->output_green << 5;
+        outred = cfg->output_red << 11;
+        outalpha = (uint32_t) 0x00000000;
+    } else if (cfg->cmode == DMA2D_ARGB1555) {
+        outgreen = cfg->output_green << 5;
+        outred = cfg->output_red << 10;
+        outalpha = cfg->output_alpha << 15;
+    } else {
+        // DMA2D_ARGB4444
+        outgreen = cfg->output_green << 4;
+        outred = cfg->output_red << 8;
+        outalpha = cfg->output_alpha << 12;
+    }
+    *DMA2D_OCOLR |= ((outgreen) | (outred) | (cfg->output_blue) | (outalpha));
 
-	*DMA2D_OMAR = (cfg->output_memory_address);
+    *DMA2D_OMAR = (cfg->output_memory_address);
 
-	*DMA2D_OOR &= ~(uint32_t)DMA2D_OOR_LO;
-	*DMA2D_OOR |= (cfg->output_offset);
+    *DMA2D_OOR &= ~(uint32_t) DMA2D_OOR_LO;
+    *DMA2D_OOR |= (cfg->output_offset);
 
-	pixline = cfg->pixel_per_line << 16;
-	*DMA2D_NLR &= ~(DMA2D_NLR_NL | DMA2D_NLR_PL);
-	*DMA2D_NLR |= ((cfg->number_of_line) | (pixline));
+    pixline = cfg->pixel_per_line << 16;
+    *DMA2D_NLR &= ~(DMA2D_NLR_NL | DMA2D_NLR_PL);
+    *DMA2D_NLR |= ((cfg->number_of_line) | (pixline));
 }
 
 void __USER_TEXT dma2d_start_transfer(void)
 {
-	*DMA2D_CR |= (uint32_t)DMA2D_CR_START;
+    *DMA2D_CR |= (uint32_t) DMA2D_CR_START;
 }
 
 uint8_t __USER_TEXT dma2d_get_flag(uint32_t flag)
 {
-	uint8_t bitstatus = 0;
+    uint8_t bitstatus = 0;
 
-	//TODO: assertion
+    // TODO: assertion
 
-	if (((*DMA2D_ISR) & flag) != (uint32_t)0)
-		bitstatus = 1;
-	else
-		bitstatus = 0;
+    if (((*DMA2D_ISR) & flag) != (uint32_t) 0)
+        bitstatus = 1;
+    else
+        bitstatus = 0;
 
-	return bitstatus;
+    return bitstatus;
 }
diff --git a/platform/stm32f429/fmc.c b/platform/stm32f429/fmc.c
index 05bb6ed5..ada443b3 100644
--- a/platform/stm32f429/fmc.c
+++ b/platform/stm32f429/fmc.c
@@ -2,95 +2,88 @@
 
 void __USER_TEXT fmc_sdram_config(struct fmc_sdram_cfg *cfg)
 {
-	uint32_t tmpr1 = 0;
-	uint32_t tmpr2 = 0;
-	uint32_t tmpr3 = 0;
-	uint32_t tmpr4 = 0;
-
-	/* TODO: assertion */
-
-	tmpr1 = (uint32_t)cfg->column_bits_number |
-	        cfg->row_bits_number |
-	        cfg->sdmemory_data_width |
-	        cfg->internal_bank_number |
-	        cfg->cas_latency |
-	        cfg->write_protection |
-	        cfg->sd_clock_period |
-	        cfg->readburst |
-	        cfg->readpipe_delay;
-
-	if (cfg->bank == FMC_Bank1_SDRAM) {
-		*FMC_Bank5_6_SDCR(cfg->bank) = tmpr1;
-	} else {
-		tmpr3 = (uint32_t)cfg->sd_clock_period |
-		        cfg->readburst |
-		        cfg->readpipe_delay;
-
-		*FMC_Bank5_6_SDCR(FMC_Bank1_SDRAM) = tmpr3;
-		*FMC_Bank5_6_SDCR(cfg->bank) = tmpr1;
-	}
-
-	if (cfg->bank == FMC_Bank1_SDRAM) {
-		tmpr2 = (uint32_t)((cfg->timing->lta_delay) - 1) |
-		        (((cfg->timing->esr_delay) - 1) << 4) |
-		        (((cfg->timing->sr_time) - 1) << 8) |
-		        (((cfg->timing->rc_delay) - 1) << 12) |
-		        (((cfg->timing->wr_time) - 1) << 16) |
-		        (((cfg->timing->rp_delay) - 1) << 20) |
-		        (((cfg->timing->rcd_delay) - 1) << 24);
-
-		*FMC_Bank5_6_SDTR(cfg->bank) = tmpr2;
-	} else {
-		tmpr2 = (uint32_t)((cfg->timing->lta_delay) - 1) |
-		        (((cfg->timing->esr_delay) - 1) << 4) |
-		        (((cfg->timing->sr_time) - 1) << 8) |
-		        (((cfg->timing->wr_time) - 1) << 16);
-
-		tmpr4 = (uint32_t)(((cfg->timing->rc_delay) - 1) << 12) |
-		        (((cfg->timing->rp_delay) - 1) << 20);
-
-		*FMC_Bank5_6_SDTR(FMC_Bank1_SDRAM) = tmpr4;
-		*FMC_Bank5_6_SDTR(cfg->bank) = tmpr2;
-	}
-
+    uint32_t tmpr1 = 0;
+    uint32_t tmpr2 = 0;
+    uint32_t tmpr3 = 0;
+    uint32_t tmpr4 = 0;
+
+    /* TODO: assertion */
+
+    tmpr1 = (uint32_t) cfg->column_bits_number | cfg->row_bits_number |
+            cfg->sdmemory_data_width | cfg->internal_bank_number |
+            cfg->cas_latency | cfg->write_protection | cfg->sd_clock_period |
+            cfg->readburst | cfg->readpipe_delay;
+
+    if (cfg->bank == FMC_Bank1_SDRAM) {
+        *FMC_Bank5_6_SDCR(cfg->bank) = tmpr1;
+    } else {
+        tmpr3 = (uint32_t) cfg->sd_clock_period | cfg->readburst |
+                cfg->readpipe_delay;
+
+        *FMC_Bank5_6_SDCR(FMC_Bank1_SDRAM) = tmpr3;
+        *FMC_Bank5_6_SDCR(cfg->bank) = tmpr1;
+    }
+
+    if (cfg->bank == FMC_Bank1_SDRAM) {
+        tmpr2 = (uint32_t) ((cfg->timing->lta_delay) - 1) |
+                (((cfg->timing->esr_delay) - 1) << 4) |
+                (((cfg->timing->sr_time) - 1) << 8) |
+                (((cfg->timing->rc_delay) - 1) << 12) |
+                (((cfg->timing->wr_time) - 1) << 16) |
+                (((cfg->timing->rp_delay) - 1) << 20) |
+                (((cfg->timing->rcd_delay) - 1) << 24);
+
+        *FMC_Bank5_6_SDTR(cfg->bank) = tmpr2;
+    } else {
+        tmpr2 = (uint32_t) ((cfg->timing->lta_delay) - 1) |
+                (((cfg->timing->esr_delay) - 1) << 4) |
+                (((cfg->timing->sr_time) - 1) << 8) |
+                (((cfg->timing->wr_time) - 1) << 16);
+
+        tmpr4 = (uint32_t) (((cfg->timing->rc_delay) - 1) << 12) |
+                (((cfg->timing->rp_delay) - 1) << 20);
+
+        *FMC_Bank5_6_SDTR(FMC_Bank1_SDRAM) = tmpr4;
+        *FMC_Bank5_6_SDTR(cfg->bank) = tmpr2;
+    }
 }
 
 uint8_t __USER_TEXT fmc_get_flag(uint32_t bank, uint32_t flag)
 {
-	uint8_t bitstatus = 0;
-	uint32_t tmpsr = 0x00000000;
+    uint8_t bitstatus = 0;
+    uint32_t tmpsr = 0x00000000;
 
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	if (bank == 999) {
-		/* TODO: bank2_nand, bank3_nand, bank4_pccard */
-	} else
-		tmpsr = *FMC_Bank5_6_SDSR;
+    if (bank == 999) {
+        /* TODO: bank2_nand, bank3_nand, bank4_pccard */
+    } else
+        tmpsr = *FMC_Bank5_6_SDSR;
 
-	if ((tmpsr & flag) != flag)
-		bitstatus = 0;
-	else
-		bitstatus = 1;
+    if ((tmpsr & flag) != flag)
+        bitstatus = 0;
+    else
+        bitstatus = 1;
 
-	return bitstatus;
+    return bitstatus;
 }
 
 void __USER_TEXT fmc_sdram_cmd_init(struct fmc_sdram_cmd *cmd)
 {
-	uint32_t tmpr = 0x0;
+    uint32_t tmpr = 0x0;
 
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	tmpr = (uint32_t)(cmd->mode | cmd->target |
-	                  (((cmd->auto_refresh_number) - 1) << 5) |
-	                  ((cmd->mode_register_definition) << 9));
+    tmpr = (uint32_t) (cmd->mode | cmd->target |
+                       (((cmd->auto_refresh_number) - 1) << 5) |
+                       ((cmd->mode_register_definition) << 9));
 
-	*FMC_Bank5_6_SDCMR = tmpr;
+    *FMC_Bank5_6_SDCMR = tmpr;
 }
 
 void __USER_TEXT fmc_set_refresh_count(uint32_t count)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	*FMC_Bank5_6_SDRTR |= (count << 1);
+    *FMC_Bank5_6_SDRTR |= (count << 1);
 }
diff --git a/platform/stm32f429/i2c.c b/platform/stm32f429/i2c.c
index df7bff20..26a8d61e 100644
--- a/platform/stm32f429/i2c.c
+++ b/platform/stm32f429/i2c.c
@@ -2,180 +2,184 @@
 #include <platform/stm32f429/rcc.h>
 
 /* I2C register mask */
-#define CR1_CLEAR_MASK           ((uint16_t)0xFBF5)
+#define CR1_CLEAR_MASK ((uint16_t) 0xFBF5)
 /* Flag mask */
-#define FLAG_MASK                ((uint32_t)0x00FFFFFF)
+#define FLAG_MASK ((uint32_t) 0x00FFFFFF)
 
 void __USER_TEXT i2c_reset(uint32_t i2cx)
 {
-	/* TODO: assertion */
-
-	if (i2cx == I2C1_BASE) {
-		RCC_APB1PeriphResetCmd(RCC_APB1RSTR_I2C1RST, 1);
-		RCC_APB1PeriphResetCmd(RCC_APB1RSTR_I2C1RST, 0);
-	} else if (i2cx == I2C2_BASE) {
-		RCC_APB1PeriphResetCmd(RCC_APB1RSTR_I2C2RST, 1);
-		RCC_APB1PeriphResetCmd(RCC_APB1RSTR_I2C2RST, 0);
-	} else if (i2cx == I2C3_BASE) {
-		RCC_APB1PeriphResetCmd(RCC_APB1RSTR_I2C2RST, 1);
-		RCC_APB1PeriphResetCmd(RCC_APB1RSTR_I2C2RST, 0);
-	}
+    /* TODO: assertion */
+
+    if (i2cx == I2C1_BASE) {
+        RCC_APB1PeriphResetCmd(RCC_APB1RSTR_I2C1RST, 1);
+        RCC_APB1PeriphResetCmd(RCC_APB1RSTR_I2C1RST, 0);
+    } else if (i2cx == I2C2_BASE) {
+        RCC_APB1PeriphResetCmd(RCC_APB1RSTR_I2C2RST, 1);
+        RCC_APB1PeriphResetCmd(RCC_APB1RSTR_I2C2RST, 0);
+    } else if (i2cx == I2C3_BASE) {
+        RCC_APB1PeriphResetCmd(RCC_APB1RSTR_I2C2RST, 1);
+        RCC_APB1PeriphResetCmd(RCC_APB1RSTR_I2C2RST, 0);
+    }
 }
 
-void __USER_TEXT i2c_config(uint32_t i2cx, struct i2c_cfg* cfg)
+void __USER_TEXT i2c_config(uint32_t i2cx, struct i2c_cfg *cfg)
 {
-	uint16_t tmpreg = 0, freqrange = 0;
-	uint16_t result = 0x04;
-	uint32_t pclk1 = 8000000;
-	struct rcc_clocks clocks;
-	/* TODO: assertion */
+    uint16_t tmpreg = 0, freqrange = 0;
+    uint16_t result = 0x04;
+    uint32_t pclk1 = 8000000;
+    struct rcc_clocks clocks;
+    /* TODO: assertion */
 
-	tmpreg = *I2C_CR2(i2cx);
-	tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ_ALL);
+    tmpreg = *I2C_CR2(i2cx);
+    tmpreg &= (uint16_t) ~((uint16_t) I2C_CR2_FREQ_ALL);
 
-	RCC_GetClocksFreq(&clocks);
-	pclk1 = clocks.pclk1_freq;
+    RCC_GetClocksFreq(&clocks);
+    pclk1 = clocks.pclk1_freq;
 
-	freqrange = (uint16_t)(pclk1 / 1000000);
-	tmpreg |= freqrange;
+    freqrange = (uint16_t) (pclk1 / 1000000);
+    tmpreg |= freqrange;
 
-	*I2C_CR2(i2cx) = tmpreg;
+    *I2C_CR2(i2cx) = tmpreg;
 
-	*I2C_CR1(i2cx) &= (uint16_t)~((uint16_t)I2C_CR1_PE);
-	tmpreg = 0;
+    *I2C_CR1(i2cx) &= (uint16_t) ~((uint16_t) I2C_CR1_PE);
+    tmpreg = 0;
 
-	if (cfg->clock_speed <= 100000) {
-		result = (uint16_t)(pclk1 / (cfg->clock_speed << 1));
+    if (cfg->clock_speed <= 100000) {
+        result = (uint16_t) (pclk1 / (cfg->clock_speed << 1));
 
-		if (result < 0x04)
-			result = 0x04;
+        if (result < 0x04)
+            result = 0x04;
 
-		tmpreg |= result;
-		*I2C_TRISE(i2cx) = freqrange + 1;
-	} else {
-		if (cfg->duty_cycle == I2C_DutyCycle_2) {
-			result = (uint16_t)(pclk1 / (cfg->clock_speed * 3));
-		} else {
-			result = (uint16_t)(pclk1 / (cfg->clock_speed * 25));
-			result |= I2C_DutyCycle_16_9;
-		}
+        tmpreg |= result;
+        *I2C_TRISE(i2cx) = freqrange + 1;
+    } else {
+        if (cfg->duty_cycle == I2C_DutyCycle_2) {
+            result = (uint16_t) (pclk1 / (cfg->clock_speed * 3));
+        } else {
+            result = (uint16_t) (pclk1 / (cfg->clock_speed * 25));
+            result |= I2C_DutyCycle_16_9;
+        }
 
-		if ((I2C_CCR_CCR(result)) == 0)
-			result |= (uint16_t)0x0001;
+        if ((I2C_CCR_CCR(result)) == 0)
+            result |= (uint16_t) 0x0001;
 
-		tmpreg |= (uint16_t)(result | I2C_CCR_FS);
-		*I2C_TRISE(i2cx) = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
-	}
-	*I2C_CCR(i2cx) = tmpreg;
-	*I2C_CR1(i2cx) |= I2C_CR1_PE;
+        tmpreg |= (uint16_t) (result | I2C_CCR_FS);
+        *I2C_TRISE(i2cx) =
+            (uint16_t) (((freqrange * (uint16_t) 300) / (uint16_t) 1000) +
+                        (uint16_t) 1);
+    }
+    *I2C_CCR(i2cx) = tmpreg;
+    *I2C_CR1(i2cx) |= I2C_CR1_PE;
 
-	tmpreg = *I2C_CR1(i2cx);
-	tmpreg &= CR1_CLEAR_MASK;
+    tmpreg = *I2C_CR1(i2cx);
+    tmpreg &= CR1_CLEAR_MASK;
 
-	tmpreg |= (uint16_t)((uint32_t)cfg->mode | cfg->ack);
-	*I2C_CR1(i2cx) = tmpreg;
+    tmpreg |= (uint16_t) ((uint32_t) cfg->mode | cfg->ack);
+    *I2C_CR1(i2cx) = tmpreg;
 
-	*I2C_OAR1(i2cx) = (cfg->acknowledged_address | cfg->own_address);
+    *I2C_OAR1(i2cx) = (cfg->acknowledged_address | cfg->own_address);
 }
 
 void __USER_TEXT i2c_cmd(uint32_t i2cx, uint8_t enable)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	if (enable != 0)
-		*I2C_CR1(i2cx) |= I2C_CR1_PE;
-	else
-		*I2C_CR1(i2cx) &= (uint16_t)~((uint16_t)I2C_CR1_PE);
+    if (enable != 0)
+        *I2C_CR1(i2cx) |= I2C_CR1_PE;
+    else
+        *I2C_CR1(i2cx) &= (uint16_t) ~((uint16_t) I2C_CR1_PE);
 }
 
 void __USER_TEXT i2c_generate_start(uint32_t i2cx, uint8_t enable)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	if (enable != 0)
-		*I2C_CR1(i2cx) |= I2C_CR1_START;
-	else
-		*I2C_CR1(i2cx) &= (uint16_t)~((uint16_t)I2C_CR1_START);
+    if (enable != 0)
+        *I2C_CR1(i2cx) |= I2C_CR1_START;
+    else
+        *I2C_CR1(i2cx) &= (uint16_t) ~((uint16_t) I2C_CR1_START);
 }
 
 uint8_t __USER_TEXT i2c_get_flag(uint32_t i2cx, uint32_t flag)
 {
-	uint8_t bitstatus = 0;
-	volatile uint32_t i2creg = 0, i2cxbase = 0;
+    uint8_t bitstatus = 0;
+    volatile uint32_t i2creg = 0, i2cxbase = 0;
 
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	i2cxbase = (uint32_t)i2cx;
-	i2creg = flag >> 28;
+    i2cxbase = (uint32_t) i2cx;
+    i2creg = flag >> 28;
 
-	flag &= FLAG_MASK;
+    flag &= FLAG_MASK;
 
-	if (i2creg != 0) {
-		i2cxbase += 0x14;
-	} else {
-		flag = (uint32_t)(flag >> 16);
-		i2cxbase += 0x18;
-	}
+    if (i2creg != 0) {
+        i2cxbase += 0x14;
+    } else {
+        flag = (uint32_t) (flag >> 16);
+        i2cxbase += 0x18;
+    }
 
-	if (((*(volatile uint32_t *)i2cxbase) & flag) != (uint32_t)0)
-		bitstatus = 1;
-	else
-		bitstatus = 0;
+    if (((*(volatile uint32_t *) i2cxbase) & flag) != (uint32_t) 0)
+        bitstatus = 1;
+    else
+        bitstatus = 0;
 
-	return bitstatus;
+    return bitstatus;
 }
 
 void __USER_TEXT i2c_acknowledge_config(uint32_t i2cx, uint8_t enable)
 {
-	/* TODO: assertion */
-	if (enable != 0)
-		*I2C_CR1(i2cx) |= I2C_CR1_ACK;
-	else
-		*I2C_CR1(i2cx) &= (uint16_t)~((uint16_t)I2C_CR1_ACK);
+    /* TODO: assertion */
+    if (enable != 0)
+        *I2C_CR1(i2cx) |= I2C_CR1_ACK;
+    else
+        *I2C_CR1(i2cx) &= (uint16_t) ~((uint16_t) I2C_CR1_ACK);
 }
 
-void __USER_TEXT i2c_send_7bit_address(uint32_t i2cx, uint8_t address, uint8_t direction)
+void __USER_TEXT i2c_send_7bit_address(uint32_t i2cx,
+                                       uint8_t address,
+                                       uint8_t direction)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	if (direction != I2C_Direction_Transmitter)
-		address |= I2C_OAR1_ADD(0);
-	else
-		address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD(0));
+    if (direction != I2C_Direction_Transmitter)
+        address |= I2C_OAR1_ADD(0);
+    else
+        address &= (uint8_t) ~((uint8_t) I2C_OAR1_ADD(0));
 
-	*I2C_DR(i2cx) = address;
+    *I2C_DR(i2cx) = address;
 }
 
 void __USER_TEXT i2c_generate_stop(uint32_t i2cx, uint8_t enable)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	if (enable != 0)
-		*I2C_CR1(i2cx) |= I2C_CR1_STOP;
-	else
-		*I2C_CR1(i2cx) &= (uint16_t)~((uint16_t)I2C_CR1_STOP);
+    if (enable != 0)
+        *I2C_CR1(i2cx) |= I2C_CR1_STOP;
+    else
+        *I2C_CR1(i2cx) &= (uint16_t) ~((uint16_t) I2C_CR1_STOP);
 }
 
 void __USER_TEXT i2c_software_reset_cmd(uint32_t i2cx, uint8_t enable)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	if (enable != 0)
-		*I2C_CR1(i2cx) |= I2C_CR1_SWRST;
-	else
-		*I2C_CR1(i2cx) &= (uint16_t)~((uint16_t)I2C_CR1_SWRST);
+    if (enable != 0)
+        *I2C_CR1(i2cx) |= I2C_CR1_SWRST;
+    else
+        *I2C_CR1(i2cx) &= (uint16_t) ~((uint16_t) I2C_CR1_SWRST);
 }
 
 void __USER_TEXT i2c_send(uint32_t i2cx, uint8_t data)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	*I2C_DR(i2cx) = data;
+    *I2C_DR(i2cx) = data;
 }
 
 uint8_t __USER_TEXT i2c_receive(uint32_t i2cx)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	return (uint8_t)(*I2C_DR(i2cx));
+    return (uint8_t) (*I2C_DR(i2cx));
 }
diff --git a/platform/stm32f429/ioe.c b/platform/stm32f429/ioe.c
index 10ab7ae6..abc1a75b 100644
--- a/platform/stm32f429/ioe.c
+++ b/platform/stm32f429/ioe.c
@@ -1,6 +1,6 @@
-#include <platform/stm32f429/ioe.h>
-#include <platform/stm32f429/i2c.h>
 #include <platform/stm32f429/gpio.h>
+#include <platform/stm32f429/i2c.h>
+#include <platform/stm32f429/ioe.h>
 #include <platform/stm32f429/rcc.h>
 
 #define TIMEOUT_MAX 0x3000
@@ -14,336 +14,338 @@ uint8_t static ioe_io_af_config(uint8_t pin, uint8_t enable);
 
 uint8_t __USER_TEXT ioe_init(void)
 {
-	ioe_gpio_init();
+    ioe_gpio_init();
 
-	ioe_i2c_init();
+    ioe_i2c_init();
 
-	if (ioe_is_operational()) {
-		return IOE_NOT_OPERATIONAL;
-	}
+    if (ioe_is_operational()) {
+        return IOE_NOT_OPERATIONAL;
+    }
 
-	ioe_reset();
+    ioe_reset();
 
-	ioe_funct(IOE_ADC_FCT, 1);
-	ioe_tp_init();
+    ioe_funct(IOE_ADC_FCT, 1);
+    ioe_tp_init();
 
-	return IOE_OK;
+    return IOE_OK;
 }
 
 uint8_t __USER_TEXT ioe_reset(void)
 {
-	uint8_t i = 0;
-	/* power down */
-	i2c_write_device_reg(IOE_REG_SYS_CTRL1, 0x02);
+    uint8_t i = 0;
+    /* power down */
+    i2c_write_device_reg(IOE_REG_SYS_CTRL1, 0x02);
 
-	/* FIXME: proper delay */
-	while (i < 20) /* delay 2 for here */
-		i++;
+    /* FIXME: proper delay */
+    while (i < 20) /* delay 2 for here */
+        i++;
 
-	/* power on */
-	i2c_write_device_reg(IOE_REG_SYS_CTRL1, 0x00);
+    /* power on */
+    i2c_write_device_reg(IOE_REG_SYS_CTRL1, 0x00);
 
-	return IOE_OK;
+    return IOE_OK;
 }
 
 void static __USER_TEXT ioe_i2c_init(void)
 {
-	struct i2c_cfg i2c_init;
-
-	if ((*I2C_CR1(I2C3_BASE) * I2C_CR1_PE) == 0) {
-		i2c_init.mode = I2C_Mode_I2C;
-		i2c_init.duty_cycle = I2C_DutyCycle_2;
-		i2c_init.own_address = 0x00;
-		i2c_init.ack = I2C_Ack_Enable;
-		i2c_init.acknowledged_address = I2C_AcknowledgedAddress_7bit;
-		i2c_init.clock_speed = I2C_SPEED;
+    struct i2c_cfg i2c_init;
 
-		i2c_config(I2C3_BASE, &i2c_init);
+    if ((*I2C_CR1(I2C3_BASE) * I2C_CR1_PE) == 0) {
+        i2c_init.mode = I2C_Mode_I2C;
+        i2c_init.duty_cycle = I2C_DutyCycle_2;
+        i2c_init.own_address = 0x00;
+        i2c_init.ack = I2C_Ack_Enable;
+        i2c_init.acknowledged_address = I2C_AcknowledgedAddress_7bit;
+        i2c_init.clock_speed = I2C_SPEED;
 
-		i2c_cmd(I2C3_BASE, 1);
-	}
+        i2c_config(I2C3_BASE, &i2c_init);
 
+        i2c_cmd(I2C3_BASE, 1);
+    }
 }
 
 void static __USER_TEXT ioe_gpio_init(void)
 {
-	struct gpio_cfg gpio_init;
-
-	RCC_APB1PeriphClockCmd(IOE_I2C_CLK, 1);
-	RCC_AHB1PeriphClockCmd(IOE_I2C_SCL_GPIO_CLK | IOE_I2C_SDA_GPIO_CLK |
-	                       IOE_IT_GPIO_CLK, 1);
-	RCC_APB2PeriphClockCmd(RCC_APB2ENR_SYSCFGEN, 1);
-
-	RCC_APB1PeriphResetCmd(IOE_I2C_CLK, 1);
-	RCC_APB1PeriphResetCmd(IOE_I2C_CLK, 0);
-
-	gpio_init.pin = 8;
-	gpio_init.type = GPIO_MODER_ALT;
-	gpio_init.speed = GPIO_OSPEEDR_50M;
-	gpio_init.o_type = GPIO_OTYPER_OD;
-	gpio_init.pupd = GPIO_PUPDR_NONE;
-	gpio_init.port = IOE_I2C_SCL_GPIO_PORT;
-	gpio_init.func = af_i2c3;
-	gpio_config(&gpio_init);
-
-	gpio_init.port = IOE_I2C_SDA_GPIO_PORT;
-	gpio_init.pin = 9;
-	gpio_config(&gpio_init);
+    struct gpio_cfg gpio_init;
+
+    RCC_APB1PeriphClockCmd(IOE_I2C_CLK, 1);
+    RCC_AHB1PeriphClockCmd(
+        IOE_I2C_SCL_GPIO_CLK | IOE_I2C_SDA_GPIO_CLK | IOE_IT_GPIO_CLK, 1);
+    RCC_APB2PeriphClockCmd(RCC_APB2ENR_SYSCFGEN, 1);
+
+    RCC_APB1PeriphResetCmd(IOE_I2C_CLK, 1);
+    RCC_APB1PeriphResetCmd(IOE_I2C_CLK, 0);
+
+    gpio_init.pin = 8;
+    gpio_init.type = GPIO_MODER_ALT;
+    gpio_init.speed = GPIO_OSPEEDR_50M;
+    gpio_init.o_type = GPIO_OTYPER_OD;
+    gpio_init.pupd = GPIO_PUPDR_NONE;
+    gpio_init.port = IOE_I2C_SCL_GPIO_PORT;
+    gpio_init.func = af_i2c3;
+    gpio_config(&gpio_init);
+
+    gpio_init.port = IOE_I2C_SDA_GPIO_PORT;
+    gpio_init.pin = 9;
+    gpio_config(&gpio_init);
 }
 
 uint8_t static __USER_TEXT ioe_tp_init(void)
 {
-	uint8_t i = 0;
-	/* Enable touch Panel functionality */
-	ioe_funct(IOE_TP_FCT, 1);
+    uint8_t i = 0;
+    /* Enable touch Panel functionality */
+    ioe_funct(IOE_TP_FCT, 1);
 
-	/* Select Sample Time, bit number and ADC Reference */
-	i2c_write_device_reg(IOE_REG_ADC_CTRL1, 0x49);
+    /* Select Sample Time, bit number and ADC Reference */
+    i2c_write_device_reg(IOE_REG_ADC_CTRL1, 0x49);
 
-	/* FIXME: proper delay */
-	while (i < 20) /* delay 2 for here */
-		i++;
+    /* FIXME: proper delay */
+    while (i < 20) /* delay 2 for here */
+        i++;
 
-	/* Select the ADC clock speed: 3.25 MHz */
-	i2c_write_device_reg(IOE_REG_ADC_CTRL2, 0x01);
+    /* Select the ADC clock speed: 3.25 MHz */
+    i2c_write_device_reg(IOE_REG_ADC_CTRL2, 0x01);
 
-	/* Select TSC pins in non default mode */
-	ioe_io_af_config((uint8_t)TOUCH_IO_ALL, 0);
+    /* Select TSC pins in non default mode */
+    ioe_io_af_config((uint8_t) TOUCH_IO_ALL, 0);
 
-	/* Select 2 nF filter capacitor */
-	i2c_write_device_reg(IOE_REG_TP_CFG, 0x9A);
+    /* Select 2 nF filter capacitor */
+    i2c_write_device_reg(IOE_REG_TP_CFG, 0x9A);
 
-	/* Select single point reading  */
-	i2c_write_device_reg(IOE_REG_FIFO_TH, 0x01);
+    /* Select single point reading  */
+    i2c_write_device_reg(IOE_REG_FIFO_TH, 0x01);
 
-	/* Write 0x01 to clear the FIFO memory content. */
-	i2c_write_device_reg(IOE_REG_FIFO_STA, 0x01);
+    /* Write 0x01 to clear the FIFO memory content. */
+    i2c_write_device_reg(IOE_REG_FIFO_STA, 0x01);
 
-	/* Write 0x00 to put the FIFO back into operation mode  */
-	i2c_write_device_reg(IOE_REG_FIFO_STA, 0x00);
+    /* Write 0x00 to put the FIFO back into operation mode  */
+    i2c_write_device_reg(IOE_REG_FIFO_STA, 0x00);
 
-	/* set the data format for Z value: 7 fractional part and 1 whole part */
-	i2c_write_device_reg(IOE_REG_TP_FRACT_XYZ, 0x01);
+    /* set the data format for Z value: 7 fractional part and 1 whole part */
+    i2c_write_device_reg(IOE_REG_TP_FRACT_XYZ, 0x01);
 
-	/* set the driving capability of the device for TSC pins: 50mA */
-	i2c_write_device_reg(IOE_REG_TP_I_DRIVE, 0x01);
+    /* set the driving capability of the device for TSC pins: 50mA */
+    i2c_write_device_reg(IOE_REG_TP_I_DRIVE, 0x01);
 
-	/* Use no tracking index, touch-panel controller operation mode (XYZ) and enable the TSC */
-	i2c_write_device_reg(IOE_REG_TP_CTRL, 0x03);
+    /* Use no tracking index, touch-panel controller operation mode (XYZ) and
+     * enable the TSC */
+    i2c_write_device_reg(IOE_REG_TP_CTRL, 0x03);
 
-	/*  Clear all the status pending bits */
-	i2c_write_device_reg(IOE_REG_INT_STA, 0xFF);
+    /*  Clear all the status pending bits */
+    i2c_write_device_reg(IOE_REG_INT_STA, 0xFF);
 
-	/* Initialize the TS structure to their default values */
-	/* TP_State.TouchDetected = TP_State.X = TP_State.Y = TP_State.Z = 0; */
+    /* Initialize the TS structure to their default values */
+    /* TP_State.TouchDetected = TP_State.X = TP_State.Y = TP_State.Z = 0; */
 
-	/* All configuration done */
-	return IOE_OK;
+    /* All configuration done */
+    return IOE_OK;
 }
 
 uint8_t static __USER_TEXT ioe_io_af_config(uint8_t pin, uint8_t enable)
 {
-	uint8_t tmp = 0;
+    uint8_t tmp = 0;
 
-	tmp = i2c_read_device_reg(IOE_REG_GPIO_AF);
+    tmp = i2c_read_device_reg(IOE_REG_GPIO_AF);
 
-	if (enable != 0)
-		tmp |= (uint8_t)pin;
-	else
-		tmp &= ~(uint8_t)pin;
+    if (enable != 0)
+        tmp |= (uint8_t) pin;
+    else
+        tmp &= ~(uint8_t) pin;
 
-	i2c_write_device_reg(IOE_REG_GPIO_AF, tmp);
+    i2c_write_device_reg(IOE_REG_GPIO_AF, tmp);
 
-	return IOE_OK;
+    return IOE_OK;
 }
 
 uint8_t __USER_TEXT ioe_funct(uint8_t func, uint8_t enable)
 {
-	uint8_t tmp = 0;
+    uint8_t tmp = 0;
 
-	tmp = i2c_read_device_reg(IOE_REG_SYS_CTRL2);
+    tmp = i2c_read_device_reg(IOE_REG_SYS_CTRL2);
 
-	if (enable != 0)
-		tmp &= ~(uint8_t)func;
-	else
-		tmp |= (uint8_t)func;
+    if (enable != 0)
+        tmp &= ~(uint8_t) func;
+    else
+        tmp |= (uint8_t) func;
 
-	i2c_write_device_reg(IOE_REG_SYS_CTRL2, tmp);
+    i2c_write_device_reg(IOE_REG_SYS_CTRL2, tmp);
 
-	return IOE_OK;
+    return IOE_OK;
 }
 
 uint8_t __USER_TEXT ioe_is_operational(void)
 {
-	if (ioe_read_id() != (uint16_t)STMPE811_ID) {
-		if (ioe_timeout == 0)
-			return(ioe_timeout_user_callback());
-		else
-			return IOE_FAILURE;
-	} else {
-		return IOE_OK;
-	}
+    if (ioe_read_id() != (uint16_t) STMPE811_ID) {
+        if (ioe_timeout == 0)
+            return (ioe_timeout_user_callback());
+        else
+            return IOE_FAILURE;
+    } else {
+        return IOE_OK;
+    }
 }
 
 uint16_t __USER_TEXT ioe_read_id(void)
 {
-	uint16_t tmp = 0;
+    uint16_t tmp = 0;
 
-	tmp = i2c_read_device_reg(0);
-	tmp = (uint32_t)(tmp << 8);
-	tmp |= (uint32_t)i2c_read_device_reg(1);
+    tmp = i2c_read_device_reg(0);
+    tmp = (uint32_t) (tmp << 8);
+    tmp |= (uint32_t) i2c_read_device_reg(1);
 
-	return (uint16_t)tmp;
+    return (uint16_t) tmp;
 }
 
 uint8_t __USER_TEXT i2c_read_device_reg(uint8_t addr)
 {
-	uint8_t tmp = 0;
+    uint8_t tmp = 0;
 
-	i2c_generate_start(I2C3_BASE, 1);
-	ioe_timeout = TIMEOUT_MAX;
+    i2c_generate_start(I2C3_BASE, 1);
+    ioe_timeout = TIMEOUT_MAX;
 
-	while (!i2c_get_flag(I2C3_BASE, I2C_FLAG_SB)) {
-		if (ioe_timeout -- == 0)
-			return(ioe_timeout_user_callback());
-	}
+    while (!i2c_get_flag(I2C3_BASE, I2C_FLAG_SB)) {
+        if (ioe_timeout-- == 0)
+            return (ioe_timeout_user_callback());
+    }
 
-	i2c_acknowledge_config(I2C3_BASE, 0);
+    i2c_acknowledge_config(I2C3_BASE, 0);
 
-	i2c_send_7bit_address(I2C3_BASE, IOE_ADDR, I2C_Direction_Transmitter);
+    i2c_send_7bit_address(I2C3_BASE, IOE_ADDR, I2C_Direction_Transmitter);
 
-	ioe_timeout = TIMEOUT_MAX;
-	while (!i2c_get_flag(I2C3_BASE, I2C_FLAG_ADDR)) {
-		if (ioe_timeout -- == 0)
-			return(ioe_timeout_user_callback());
-	}
+    ioe_timeout = TIMEOUT_MAX;
+    while (!i2c_get_flag(I2C3_BASE, I2C_FLAG_ADDR)) {
+        if (ioe_timeout-- == 0)
+            return (ioe_timeout_user_callback());
+    }
 
-	*I2C_SR2(I2C3_BASE); /* Read status register 2 to clear ADDR flag */
+    *I2C_SR2(I2C3_BASE); /* Read status register 2 to clear ADDR flag */
 
-	ioe_timeout = TIMEOUT_MAX;
-	while (!i2c_get_flag(I2C3_BASE, I2C_FLAG_TXE)) {
-		if (ioe_timeout -- == 0)
-			return(ioe_timeout_user_callback());
-	}
+    ioe_timeout = TIMEOUT_MAX;
+    while (!i2c_get_flag(I2C3_BASE, I2C_FLAG_TXE)) {
+        if (ioe_timeout-- == 0)
+            return (ioe_timeout_user_callback());
+    }
 
-	i2c_send(I2C3_BASE, addr);
+    i2c_send(I2C3_BASE, addr);
 
-	ioe_timeout = TIMEOUT_MAX;
-	while ((!i2c_get_flag(I2C3_BASE, I2C_FLAG_TXE)) || (!i2c_get_flag(I2C3_BASE, I2C_FLAG_BTF))) {
-		if (ioe_timeout -- == 0)
-			return(ioe_timeout_user_callback());
-	}
+    ioe_timeout = TIMEOUT_MAX;
+    while ((!i2c_get_flag(I2C3_BASE, I2C_FLAG_TXE)) ||
+           (!i2c_get_flag(I2C3_BASE, I2C_FLAG_BTF))) {
+        if (ioe_timeout-- == 0)
+            return (ioe_timeout_user_callback());
+    }
 
-	i2c_generate_start(I2C3_BASE, 1);
+    i2c_generate_start(I2C3_BASE, 1);
 
-	ioe_timeout = TIMEOUT_MAX;
-	while (!i2c_get_flag(I2C3_BASE, I2C_FLAG_SB)) {
-		if (ioe_timeout -- == 0)
-			return(ioe_timeout_user_callback());
-	}
+    ioe_timeout = TIMEOUT_MAX;
+    while (!i2c_get_flag(I2C3_BASE, I2C_FLAG_SB)) {
+        if (ioe_timeout-- == 0)
+            return (ioe_timeout_user_callback());
+    }
 
-	i2c_send_7bit_address(I2C3_BASE, IOE_ADDR, I2C_Direction_Receiver);
+    i2c_send_7bit_address(I2C3_BASE, IOE_ADDR, I2C_Direction_Receiver);
 
-	ioe_timeout = TIMEOUT_MAX;
-	while (!i2c_get_flag(I2C3_BASE, I2C_FLAG_ADDR)) {
-		if (ioe_timeout -- == 0)
-			return(ioe_timeout_user_callback());
-	}
+    ioe_timeout = TIMEOUT_MAX;
+    while (!i2c_get_flag(I2C3_BASE, I2C_FLAG_ADDR)) {
+        if (ioe_timeout-- == 0)
+            return (ioe_timeout_user_callback());
+    }
 
-	*I2C_SR2(I2C3_BASE); /* read status register 2 to clear ADDR flag (2) */
+    *I2C_SR2(I2C3_BASE); /* read status register 2 to clear ADDR flag (2) */
 
-	ioe_timeout = TIMEOUT_MAX;
-	while (!i2c_get_flag(I2C3_BASE, I2C_FLAG_RXNE)) {
-		if (ioe_timeout -- == 0)
-			return(ioe_timeout_user_callback());
-	}
+    ioe_timeout = TIMEOUT_MAX;
+    while (!i2c_get_flag(I2C3_BASE, I2C_FLAG_RXNE)) {
+        if (ioe_timeout-- == 0)
+            return (ioe_timeout_user_callback());
+    }
 
-	i2c_generate_stop(I2C3_BASE, 1);
+    i2c_generate_stop(I2C3_BASE, 1);
 
-	tmp = i2c_receive(I2C3_BASE);
+    tmp = i2c_receive(I2C3_BASE);
 
-	i2c_acknowledge_config(I2C3_BASE, 1);
+    i2c_acknowledge_config(I2C3_BASE, 1);
 
-	return tmp;
+    return tmp;
 }
 
 uint8_t __USER_TEXT i2c_write_device_reg(uint8_t addr, uint8_t value)
 {
-	uint32_t read_verif = 0;
+    uint32_t read_verif = 0;
 
-	i2c_generate_start(I2C3_BASE, 1);
+    i2c_generate_start(I2C3_BASE, 1);
 
-	ioe_timeout = TIMEOUT_MAX;
-	while (!i2c_get_flag(I2C3_BASE, I2C_FLAG_SB)) {
-		if (ioe_timeout-- == 0)
-			return (ioe_timeout_user_callback());
-	}
+    ioe_timeout = TIMEOUT_MAX;
+    while (!i2c_get_flag(I2C3_BASE, I2C_FLAG_SB)) {
+        if (ioe_timeout-- == 0)
+            return (ioe_timeout_user_callback());
+    }
 
-	i2c_send_7bit_address(I2C3_BASE, IOE_ADDR, I2C_Direction_Transmitter);
+    i2c_send_7bit_address(I2C3_BASE, IOE_ADDR, I2C_Direction_Transmitter);
 
-	ioe_timeout = TIMEOUT_MAX;
-	while (!i2c_get_flag(I2C3_BASE, I2C_FLAG_ADDR)) {
-		if (ioe_timeout-- == 0)
-			return (ioe_timeout_user_callback());
-	}
+    ioe_timeout = TIMEOUT_MAX;
+    while (!i2c_get_flag(I2C3_BASE, I2C_FLAG_ADDR)) {
+        if (ioe_timeout-- == 0)
+            return (ioe_timeout_user_callback());
+    }
 
-	*I2C_SR2(I2C3_BASE); /* read status register 2 to clear ADDR flag (1) */
+    *I2C_SR2(I2C3_BASE); /* read status register 2 to clear ADDR flag (1) */
 
-	ioe_timeout = TIMEOUT_MAX;
-	while (!i2c_get_flag(I2C3_BASE, I2C_FLAG_TXE)) {
-		if (ioe_timeout-- == 0)
-			return (ioe_timeout_user_callback());
-	}
+    ioe_timeout = TIMEOUT_MAX;
+    while (!i2c_get_flag(I2C3_BASE, I2C_FLAG_TXE)) {
+        if (ioe_timeout-- == 0)
+            return (ioe_timeout_user_callback());
+    }
 
-	i2c_send(I2C3_BASE, addr);
+    i2c_send(I2C3_BASE, addr);
 
-	ioe_timeout = TIMEOUT_MAX;
-	while (!i2c_get_flag(I2C3_BASE, I2C_FLAG_TXE)) {
-		if (ioe_timeout-- == 0)
-			return (ioe_timeout_user_callback());
-	}
+    ioe_timeout = TIMEOUT_MAX;
+    while (!i2c_get_flag(I2C3_BASE, I2C_FLAG_TXE)) {
+        if (ioe_timeout-- == 0)
+            return (ioe_timeout_user_callback());
+    }
 
-	i2c_send(I2C3_BASE, value);
+    i2c_send(I2C3_BASE, value);
 
-	ioe_timeout = TIMEOUT_MAX;
-	while ((!i2c_get_flag(I2C3_BASE, I2C_FLAG_TXE)) | (!i2c_get_flag(I2C3_BASE, I2C_FLAG_BTF))) {
-		if (ioe_timeout-- == 0)
-			return (ioe_timeout_user_callback());
-	}
+    ioe_timeout = TIMEOUT_MAX;
+    while ((!i2c_get_flag(I2C3_BASE, I2C_FLAG_TXE)) |
+           (!i2c_get_flag(I2C3_BASE, I2C_FLAG_BTF))) {
+        if (ioe_timeout-- == 0)
+            return (ioe_timeout_user_callback());
+    }
 
-	i2c_generate_stop(I2C3_BASE, 1);
+    i2c_generate_stop(I2C3_BASE, 1);
 
-	return read_verif;
+    return read_verif;
 }
 
 uint8_t __USER_TEXT ioe_timeout_user_callback(void)
 {
-	struct i2c_cfg i2c_init;
+    struct i2c_cfg i2c_init;
 
-	i2c_generate_stop(I2C3_BASE, 1);
-	i2c_software_reset_cmd(I2C3_BASE, 1);
-	i2c_software_reset_cmd(I2C3_BASE, 0);
+    i2c_generate_stop(I2C3_BASE, 1);
+    i2c_software_reset_cmd(I2C3_BASE, 1);
+    i2c_software_reset_cmd(I2C3_BASE, 0);
 
-	ioe_gpio_init();
+    ioe_gpio_init();
 
-	i2c_reset(I2C3_BASE);
-	i2c_init.mode = I2C_Mode_I2C;
-	i2c_init.duty_cycle = I2C_DutyCycle_2;
-	i2c_init.own_address = 0x00;
-	i2c_init.ack = I2C_Ack_Enable;
-	i2c_init.acknowledged_address = I2C_AcknowledgedAddress_7bit;
-	i2c_init.clock_speed = I2C_SPEED;
+    i2c_reset(I2C3_BASE);
+    i2c_init.mode = I2C_Mode_I2C;
+    i2c_init.duty_cycle = I2C_DutyCycle_2;
+    i2c_init.own_address = 0x00;
+    i2c_init.ack = I2C_Ack_Enable;
+    i2c_init.acknowledged_address = I2C_AcknowledgedAddress_7bit;
+    i2c_init.clock_speed = I2C_SPEED;
 
-	i2c_cmd(I2C3_BASE, 1);
-	i2c_config(I2C3_BASE, &i2c_init);
+    i2c_cmd(I2C3_BASE, 1);
+    i2c_config(I2C3_BASE, &i2c_init);
 
-	return 0;
+    return 0;
 }
 
 uint16_t __USER_TEXT ioe_tp_get_state(void)
 {
-	uint16_t status;
+    uint16_t status;
 
-	status = (i2c_read_device_reg(IOE_REG_TP_CTRL) & 0x80);
-	return status;
+    status = (i2c_read_device_reg(IOE_REG_TP_CTRL) & 0x80);
+    return status;
 }
diff --git a/platform/stm32f429/lcd.c b/platform/stm32f429/lcd.c
index f3d8d028..deee7fc4 100644
--- a/platform/stm32f429/lcd.c
+++ b/platform/stm32f429/lcd.c
@@ -1,10 +1,10 @@
-#include <platform/stm32f429/lcd.h>
+#include <platform/stm32f429/dma2d.h>
 #include <platform/stm32f429/gpio.h>
-#include <platform/stm32f429/spi.h>
+#include <platform/stm32f429/lcd.h>
+#include <platform/stm32f429/ltdc.h>
 #include <platform/stm32f429/rcc.h>
 #include <platform/stm32f429/sdram.h>
-#include <platform/stm32f429/ltdc.h>
-#include <platform/stm32f429/dma2d.h>
+#include <platform/stm32f429/spi.h>
 
 static __USER_DATA uint16_t current_Tcolor = 0x0000;
 static __USER_DATA uint16_t current_Bcolor = 0xFFFF;
@@ -13,521 +13,541 @@ static __USER_DATA uint32_t current_frame_buffer = LCD_FRAME_BUFFER;
 
 void __USER_TEXT lcd_init(void)
 {
-	struct ltdc_cfg ltdc_cfg;
+    struct ltdc_cfg ltdc_cfg;
 
-	lcd_ctrllines_init();
-	/* reset & then set */
-	lcd_chipselect(0);
-	lcd_chipselect(1);
+    lcd_ctrllines_init();
+    /* reset & then set */
+    lcd_chipselect(0);
+    lcd_chipselect(1);
 
-	lcd_spi_config();
+    lcd_spi_config();
 
-	lcd_poweron();
+    lcd_poweron();
 
-	RCC_APB2PeriphClockCmd(RCC_APB2ENR_LTDCEN, 1);
+    RCC_APB2PeriphClockCmd(RCC_APB2ENR_LTDCEN, 1);
 
-	RCC_AHB1PeriphClockCmd(RCC_AHB1ENR_DMA2DEN, 1);
+    RCC_AHB1PeriphClockCmd(RCC_AHB1ENR_DMA2DEN, 1);
 
-	lcd_af_gpio_init();
+    lcd_af_gpio_init();
 
-	sdram_init();
+    sdram_init();
 
-	ltdc_cfg.hs_polarity = LTDC_HSPolarity_AL;
-	ltdc_cfg.vs_polarity = LTDC_VSPolarity_AL;
-	ltdc_cfg.de_polarity = LTDC_DEPolarity_AL;
-	ltdc_cfg.pc_polarity = LTDC_PCPolarity_IPC;
+    ltdc_cfg.hs_polarity = LTDC_HSPolarity_AL;
+    ltdc_cfg.vs_polarity = LTDC_VSPolarity_AL;
+    ltdc_cfg.de_polarity = LTDC_DEPolarity_AL;
+    ltdc_cfg.pc_polarity = LTDC_PCPolarity_IPC;
 
-	ltdc_cfg.bg_red_value = 0;
-	ltdc_cfg.bg_green_value = 0;
-	ltdc_cfg.bg_blue_value = 0;
+    ltdc_cfg.bg_red_value = 0;
+    ltdc_cfg.bg_green_value = 0;
+    ltdc_cfg.bg_blue_value = 0;
 
-	RCC_PLLSAIConfig(192, 7, 4);
-	RCC_LTDCCLKDivConfig(RCC_PLLSAIDivR_Div8);
+    RCC_PLLSAIConfig(192, 7, 4);
+    RCC_LTDCCLKDivConfig(RCC_PLLSAIDivR_Div8);
 
-	RCC_PLLSAICmd(1);
+    RCC_PLLSAICmd(1);
 
-	while (RCC_GetFlagStatus(RCC_FLAG_PLLSAIRDY) == 0) ;
+    while (RCC_GetFlagStatus(RCC_FLAG_PLLSAIRDY) == 0)
+        ;
 
-	ltdc_cfg.horizontal_sync = 9;
-	ltdc_cfg.vertical_sync = 1;
-	ltdc_cfg.accumulated_hbp = 29;
-	ltdc_cfg.accumulated_vbp = 3;
-	ltdc_cfg.accumulated_active_w = 269;
-	ltdc_cfg.accumulated_active_h = 323;
-	ltdc_cfg.total_width = 279;
-	ltdc_cfg.total_height = 327;
+    ltdc_cfg.horizontal_sync = 9;
+    ltdc_cfg.vertical_sync = 1;
+    ltdc_cfg.accumulated_hbp = 29;
+    ltdc_cfg.accumulated_vbp = 3;
+    ltdc_cfg.accumulated_active_w = 269;
+    ltdc_cfg.accumulated_active_h = 323;
+    ltdc_cfg.total_width = 279;
+    ltdc_cfg.total_height = 327;
 
-	ltdc_config(&ltdc_cfg);
+    ltdc_config(&ltdc_cfg);
 }
 
 void __USER_TEXT lcd_write_cmd(uint8_t lcdreg)
 {
-	lcd_ctrllines_write(LCD_WRX_GPIO_PORT, LCD_WRX_PIN, 0);
+    lcd_ctrllines_write(LCD_WRX_GPIO_PORT, LCD_WRX_PIN, 0);
 
-	lcd_chipselect(0);
-	spi_i2s_send(LCD_SPI, lcdreg);
+    lcd_chipselect(0);
+    spi_i2s_send(LCD_SPI, lcdreg);
 
-	while (spi_i2s_get_flag(LCD_SPI, SPI_I2S_FLAG_TXE) == 0);
+    while (spi_i2s_get_flag(LCD_SPI, SPI_I2S_FLAG_TXE) == 0)
+        ;
 
-	while (spi_i2s_get_flag(LCD_SPI, SPI_I2S_FLAG_BSY) != 0);
+    while (spi_i2s_get_flag(LCD_SPI, SPI_I2S_FLAG_BSY) != 0)
+        ;
 
-	lcd_chipselect(1);
+    lcd_chipselect(1);
 }
 
 void __USER_TEXT lcd_write_data(uint8_t value)
 {
-	lcd_ctrllines_write(LCD_WRX_GPIO_PORT, LCD_WRX_PIN, 1);
+    lcd_ctrllines_write(LCD_WRX_GPIO_PORT, LCD_WRX_PIN, 1);
 
-	lcd_chipselect(0);
-	spi_i2s_send(LCD_SPI, value);
+    lcd_chipselect(0);
+    spi_i2s_send(LCD_SPI, value);
 
-	while (spi_i2s_get_flag(LCD_SPI, SPI_I2S_FLAG_TXE) == 0);
+    while (spi_i2s_get_flag(LCD_SPI, SPI_I2S_FLAG_TXE) == 0)
+        ;
 
-	while (spi_i2s_get_flag(LCD_SPI, SPI_I2S_FLAG_BSY) != 0);
+    while (spi_i2s_get_flag(LCD_SPI, SPI_I2S_FLAG_BSY) != 0)
+        ;
 
-	lcd_chipselect(1);
+    lcd_chipselect(1);
 }
 
 void __USER_TEXT lcd_poweron(void)
 {
-	uint32_t i;
-	lcd_write_cmd(0xCA);
-	lcd_write_data(0xC3);
-	lcd_write_data(0x08);
-	lcd_write_data(0x50);
-	lcd_write_cmd(0xCF); /* LCD_POWERB */
-	lcd_write_data(0x00);
-	lcd_write_data(0xC1);
-	lcd_write_data(0x30);
-	lcd_write_cmd(0xED); /* LCD_POWER_SEQ */
-	lcd_write_data(0x64);
-	lcd_write_data(0x03);
-	lcd_write_data(0x12);
-	lcd_write_data(0x81);
-	lcd_write_cmd(0xE8); /* LCD_DTCA */
-	lcd_write_data(0x85);
-	lcd_write_data(0x00);
-	lcd_write_data(0x78);
-	lcd_write_cmd(0xCB); /* LCD_POWERA */
-	lcd_write_data(0x39);
-	lcd_write_data(0x2C);
-	lcd_write_data(0x00);
-	lcd_write_data(0x34);
-	lcd_write_data(0x02);
-	lcd_write_cmd(0xF7); /* LCD_PRC */
-	lcd_write_data(0x20);
-	lcd_write_cmd(0xEA); /* LCD_DTCB */
-	lcd_write_data(0x00);
-	lcd_write_data(0x00);
-	lcd_write_cmd(0xB1); /* LCD_FRC */
-	lcd_write_data(0x00);
-	lcd_write_data(0x1B);
-	lcd_write_cmd(0xB6); /* LCD_DFC */
-	lcd_write_data(0x0A);
-	lcd_write_data(0xA2);
-	lcd_write_cmd(0xC0); /* LCD_Power1 */
-	lcd_write_data(0x10);
-	lcd_write_cmd(0xC1); /* LCD_Power2 */
-	lcd_write_data(0x10);
-	lcd_write_cmd(0xC5); /* LCD_VCOM1 */
-	lcd_write_data(0x45);
-	lcd_write_data(0x15);
-	lcd_write_cmd(0xC7); /* LCD_VCOM2 */
-	lcd_write_data(0x90);
-	lcd_write_cmd(0x36); /* LCD_MAC */
-	lcd_write_data(0xC8);
-	lcd_write_cmd(0xF2); /* LCD_3GAMMA_EN */
-	lcd_write_data(0x00);
-	lcd_write_cmd(0xB0); /* LCD_RGB_INTERFACE */
-	lcd_write_data(0xC2);
-	lcd_write_cmd(0xB6); /* LCD_DFC */
-	lcd_write_data(0x0A);
-	lcd_write_data(0xA7);
-	lcd_write_data(0x27);
-	lcd_write_data(0x04);
-
-	/* colomn address set */
-	lcd_write_cmd(0x2A); /* LCD_COLUMN_ADDR */
-	lcd_write_data(0x00);
-	lcd_write_data(0x00);
-	lcd_write_data(0x00);
-	lcd_write_data(0xEF);
-	/* Page Address Set */
-	lcd_write_cmd(0x2B); /* LCD_PAGE_ADDR */
-	lcd_write_data(0x00);
-	lcd_write_data(0x00);
-	lcd_write_data(0x01);
-	lcd_write_data(0x3F);
-	lcd_write_cmd(0xF6); /* LCD_INTERFACE */
-	lcd_write_data(0x01);
-	lcd_write_data(0x00);
-	lcd_write_data(0x06);
-
-	lcd_write_cmd(0x2C); /* LCD_GRAM */
-	/* L4_Sleep(200); */
-	/* L4_Sleep unable to be used at here, so I use while temporary */
-	/* TODO: A proper delay */
-	i = 0;
-	while (i < 400)
-		i++;
-
-	lcd_write_cmd(0x26); /* LCD_GAMMA */
-	lcd_write_data(0x01);
-
-	lcd_write_cmd(0xE0); /* LCD_PGAMMA */
-	lcd_write_data(0x0F);
-	lcd_write_data(0x29);
-	lcd_write_data(0x24);
-	lcd_write_data(0x0C);
-	lcd_write_data(0x0E);
-	lcd_write_data(0x09);
-	lcd_write_data(0x4E);
-	lcd_write_data(0x78);
-	lcd_write_data(0x3C);
-	lcd_write_data(0x09);
-	lcd_write_data(0x13);
-	lcd_write_data(0x05);
-	lcd_write_data(0x17);
-	lcd_write_data(0x11);
-	lcd_write_data(0x00);
-	lcd_write_cmd(0xE1); /* LCD_NGAMMA */
-	lcd_write_data(0x00);
-	lcd_write_data(0x16);
-	lcd_write_data(0x1B);
-	lcd_write_data(0x04);
-	lcd_write_data(0x11);
-	lcd_write_data(0x07);
-	lcd_write_data(0x31);
-	lcd_write_data(0x33);
-	lcd_write_data(0x42);
-	lcd_write_data(0x05);
-	lcd_write_data(0x0C);
-	lcd_write_data(0x0A);
-	lcd_write_data(0x28);
-	lcd_write_data(0x2F);
-	lcd_write_data(0x0F);
-
-	lcd_write_cmd(0x11); /* LCD_SLEEP_OUT */
-	/* L4_Sleep(200); */
-	/* L4_Sleep unable to be used at here, so I use while temporary */
-	/* TODO: A proper delay */
-	i = 0;
-	while (i < 400)
-		i++;
-	lcd_write_cmd(0x29); /* LCD_DISPLAY_ON */
-	/* GRAM start writing */
-	lcd_write_cmd(0x2C); /* LCD_GRAM */
+    uint32_t i;
+    lcd_write_cmd(0xCA);
+    lcd_write_data(0xC3);
+    lcd_write_data(0x08);
+    lcd_write_data(0x50);
+    lcd_write_cmd(0xCF); /* LCD_POWERB */
+    lcd_write_data(0x00);
+    lcd_write_data(0xC1);
+    lcd_write_data(0x30);
+    lcd_write_cmd(0xED); /* LCD_POWER_SEQ */
+    lcd_write_data(0x64);
+    lcd_write_data(0x03);
+    lcd_write_data(0x12);
+    lcd_write_data(0x81);
+    lcd_write_cmd(0xE8); /* LCD_DTCA */
+    lcd_write_data(0x85);
+    lcd_write_data(0x00);
+    lcd_write_data(0x78);
+    lcd_write_cmd(0xCB); /* LCD_POWERA */
+    lcd_write_data(0x39);
+    lcd_write_data(0x2C);
+    lcd_write_data(0x00);
+    lcd_write_data(0x34);
+    lcd_write_data(0x02);
+    lcd_write_cmd(0xF7); /* LCD_PRC */
+    lcd_write_data(0x20);
+    lcd_write_cmd(0xEA); /* LCD_DTCB */
+    lcd_write_data(0x00);
+    lcd_write_data(0x00);
+    lcd_write_cmd(0xB1); /* LCD_FRC */
+    lcd_write_data(0x00);
+    lcd_write_data(0x1B);
+    lcd_write_cmd(0xB6); /* LCD_DFC */
+    lcd_write_data(0x0A);
+    lcd_write_data(0xA2);
+    lcd_write_cmd(0xC0); /* LCD_Power1 */
+    lcd_write_data(0x10);
+    lcd_write_cmd(0xC1); /* LCD_Power2 */
+    lcd_write_data(0x10);
+    lcd_write_cmd(0xC5); /* LCD_VCOM1 */
+    lcd_write_data(0x45);
+    lcd_write_data(0x15);
+    lcd_write_cmd(0xC7); /* LCD_VCOM2 */
+    lcd_write_data(0x90);
+    lcd_write_cmd(0x36); /* LCD_MAC */
+    lcd_write_data(0xC8);
+    lcd_write_cmd(0xF2); /* LCD_3GAMMA_EN */
+    lcd_write_data(0x00);
+    lcd_write_cmd(0xB0); /* LCD_RGB_INTERFACE */
+    lcd_write_data(0xC2);
+    lcd_write_cmd(0xB6); /* LCD_DFC */
+    lcd_write_data(0x0A);
+    lcd_write_data(0xA7);
+    lcd_write_data(0x27);
+    lcd_write_data(0x04);
+
+    /* colomn address set */
+    lcd_write_cmd(0x2A); /* LCD_COLUMN_ADDR */
+    lcd_write_data(0x00);
+    lcd_write_data(0x00);
+    lcd_write_data(0x00);
+    lcd_write_data(0xEF);
+    /* Page Address Set */
+    lcd_write_cmd(0x2B); /* LCD_PAGE_ADDR */
+    lcd_write_data(0x00);
+    lcd_write_data(0x00);
+    lcd_write_data(0x01);
+    lcd_write_data(0x3F);
+    lcd_write_cmd(0xF6); /* LCD_INTERFACE */
+    lcd_write_data(0x01);
+    lcd_write_data(0x00);
+    lcd_write_data(0x06);
+
+    lcd_write_cmd(0x2C); /* LCD_GRAM */
+    /* L4_Sleep(200); */
+    /* L4_Sleep unable to be used at here, so I use while temporary */
+    /* TODO: A proper delay */
+    i = 0;
+    while (i < 400)
+        i++;
+
+    lcd_write_cmd(0x26); /* LCD_GAMMA */
+    lcd_write_data(0x01);
+
+    lcd_write_cmd(0xE0); /* LCD_PGAMMA */
+    lcd_write_data(0x0F);
+    lcd_write_data(0x29);
+    lcd_write_data(0x24);
+    lcd_write_data(0x0C);
+    lcd_write_data(0x0E);
+    lcd_write_data(0x09);
+    lcd_write_data(0x4E);
+    lcd_write_data(0x78);
+    lcd_write_data(0x3C);
+    lcd_write_data(0x09);
+    lcd_write_data(0x13);
+    lcd_write_data(0x05);
+    lcd_write_data(0x17);
+    lcd_write_data(0x11);
+    lcd_write_data(0x00);
+    lcd_write_cmd(0xE1); /* LCD_NGAMMA */
+    lcd_write_data(0x00);
+    lcd_write_data(0x16);
+    lcd_write_data(0x1B);
+    lcd_write_data(0x04);
+    lcd_write_data(0x11);
+    lcd_write_data(0x07);
+    lcd_write_data(0x31);
+    lcd_write_data(0x33);
+    lcd_write_data(0x42);
+    lcd_write_data(0x05);
+    lcd_write_data(0x0C);
+    lcd_write_data(0x0A);
+    lcd_write_data(0x28);
+    lcd_write_data(0x2F);
+    lcd_write_data(0x0F);
+
+    lcd_write_cmd(0x11); /* LCD_SLEEP_OUT */
+    /* L4_Sleep(200); */
+    /* L4_Sleep unable to be used at here, so I use while temporary */
+    /* TODO: A proper delay */
+    i = 0;
+    while (i < 400)
+        i++;
+    lcd_write_cmd(0x29); /* LCD_DISPLAY_ON */
+    /* GRAM start writing */
+    lcd_write_cmd(0x2C); /* LCD_GRAM */
 }
 
 void __USER_TEXT lcd_display_off(void)
 {
-	lcd_write_cmd(0x28);
+    lcd_write_cmd(0x28);
 }
 
 void __USER_TEXT lcd_spi_config(void)
 {
-	struct spi_cfg spi_init;
-	struct gpio_cfg gpio_init;
-	/* Enable clock */
-	RCC_AHB1PeriphClockCmd(LCD_SPI_SCK_GPIO_CLK | LCD_SPI_MISO_GPIO_CLK | LCD_SPI_MOSI_GPIO_CLK, 1);
-
-	RCC_APB2PeriphClockCmd(LCD_SPI_CLK, 1);
-
-	gpio_init.port = LCD_SPI_SCK_GPIO_PORT;
-	gpio_init.pin = LCD_SPI_SCK_PIN;
-	gpio_init.speed = GPIO_OSPEEDR_25M;
-	gpio_init.pupd = GPIO_PUPDR_DOWN;
-	gpio_init.type = GPIO_MODER_ALT;
-	gpio_init.func = af_spi5;
-	gpio_init.o_type = GPIO_OTYPER_PP;
-	gpio_config(&gpio_init);
-
-	gpio_init.port = LCD_SPI_MISO_GPIO_PORT;
-	gpio_init.pin = LCD_SPI_MISO_PIN;
-	gpio_config(&gpio_init);
-
-	gpio_init.port = LCD_SPI_MOSI_GPIO_PORT;
-	gpio_init.pin = LCD_SPI_MOSI_PIN;
-	gpio_config(&gpio_init);
-
-	spi_i2s_reset(LCD_SPI);
-
-	if ((*(SPI_CR1(LCD_SPI)) & (SPI_CR1_SPE)) == 0) {
-		spi_init.direction = (uint16_t)0x0000; /* 2 lines full duplex */
-		spi_init.mode = (uint16_t) 0x0104; /* master */
-		spi_init.size = (uint16_t) 0x0000; /* 8b */
-		spi_init.cpol = (uint16_t) 0x0000; /* low */
-		spi_init.cpha = (uint16_t) 0x0000; /* 1Edge */
-		spi_init.nss = (uint16_t) 0x0200; /* soft */
-		spi_init.baudrate = (uint16_t) 0x0018; /* prescaler 16 */
-		spi_init.firstbit = (uint16_t) 0x0000; /* MSB */
-		spi_init.crcpolynomial = 7;
-		spi_config(LCD_SPI, &spi_init);
-		/* Enable L3GD20_SPI */
-		spi_cmd(LCD_SPI, 1);
-	}
+    struct spi_cfg spi_init;
+    struct gpio_cfg gpio_init;
+    /* Enable clock */
+    RCC_AHB1PeriphClockCmd(
+        LCD_SPI_SCK_GPIO_CLK | LCD_SPI_MISO_GPIO_CLK | LCD_SPI_MOSI_GPIO_CLK,
+        1);
+
+    RCC_APB2PeriphClockCmd(LCD_SPI_CLK, 1);
+
+    gpio_init.port = LCD_SPI_SCK_GPIO_PORT;
+    gpio_init.pin = LCD_SPI_SCK_PIN;
+    gpio_init.speed = GPIO_OSPEEDR_25M;
+    gpio_init.pupd = GPIO_PUPDR_DOWN;
+    gpio_init.type = GPIO_MODER_ALT;
+    gpio_init.func = af_spi5;
+    gpio_init.o_type = GPIO_OTYPER_PP;
+    gpio_config(&gpio_init);
+
+    gpio_init.port = LCD_SPI_MISO_GPIO_PORT;
+    gpio_init.pin = LCD_SPI_MISO_PIN;
+    gpio_config(&gpio_init);
+
+    gpio_init.port = LCD_SPI_MOSI_GPIO_PORT;
+    gpio_init.pin = LCD_SPI_MOSI_PIN;
+    gpio_config(&gpio_init);
+
+    spi_i2s_reset(LCD_SPI);
+
+    if ((*(SPI_CR1(LCD_SPI)) & (SPI_CR1_SPE)) == 0) {
+        spi_init.direction = (uint16_t) 0x0000; /* 2 lines full duplex */
+        spi_init.mode = (uint16_t) 0x0104;      /* master */
+        spi_init.size = (uint16_t) 0x0000;      /* 8b */
+        spi_init.cpol = (uint16_t) 0x0000;      /* low */
+        spi_init.cpha = (uint16_t) 0x0000;      /* 1Edge */
+        spi_init.nss = (uint16_t) 0x0200;       /* soft */
+        spi_init.baudrate = (uint16_t) 0x0018;  /* prescaler 16 */
+        spi_init.firstbit = (uint16_t) 0x0000;  /* MSB */
+        spi_init.crcpolynomial = 7;
+        spi_config(LCD_SPI, &spi_init);
+        /* Enable L3GD20_SPI */
+        spi_cmd(LCD_SPI, 1);
+    }
 }
 
 void __USER_TEXT lcd_ctrllines_write(uint8_t port, uint8_t pin, uint8_t reset)
 {
-	gpio_writebit(port, pin, reset);
+    gpio_writebit(port, pin, reset);
 }
 
 void __USER_TEXT lcd_ctrllines_init(void)
 {
-	RCC_AHB1PeriphClockCmd(LCD_NCS_GPIO_CLK | LCD_WRX_GPIO_CLK, 1);
-	gpio_config_output(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, GPIO_PUPDR_NONE, GPIO_OSPEEDR_50M);
-	gpio_config_output(LCD_WRX_GPIO_PORT, LCD_WRX_PIN, GPIO_PUPDR_NONE, GPIO_OSPEEDR_50M);
+    RCC_AHB1PeriphClockCmd(LCD_NCS_GPIO_CLK | LCD_WRX_GPIO_CLK, 1);
+    gpio_config_output(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, GPIO_PUPDR_NONE,
+                       GPIO_OSPEEDR_50M);
+    gpio_config_output(LCD_WRX_GPIO_PORT, LCD_WRX_PIN, GPIO_PUPDR_NONE,
+                       GPIO_OSPEEDR_50M);
 
-	lcd_ctrllines_write(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, 1);
+    lcd_ctrllines_write(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, 1);
 }
 
 void __USER_TEXT lcd_chipselect(uint8_t enable)
 {
-	if (enable == 0)
-		*GPIO_BSRR(LCD_NCS_GPIO_PORT) = GPIO_BSRR_BR(LCD_NCS_PIN);
-	else
-		*GPIO_BSRR(LCD_NCS_GPIO_PORT) = GPIO_BSRR_BS(LCD_NCS_PIN);
+    if (enable == 0)
+        *GPIO_BSRR(LCD_NCS_GPIO_PORT) = GPIO_BSRR_BR(LCD_NCS_PIN);
+    else
+        *GPIO_BSRR(LCD_NCS_GPIO_PORT) = GPIO_BSRR_BS(LCD_NCS_PIN);
 }
 
 void __USER_TEXT lcd_af_gpio_init(void)
 {
-	struct gpio_cfg gpio_init;
-
-	RCC_AHB1PeriphClockCmd(RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \
-	                       RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
-	                       RCC_AHB1ENR_GPIOFEN | RCC_AHB1ENR_GPIOGEN, 1);
-
-	/* GPIOA */
-	gpio_init.port = GPIOA;
-	gpio_init.speed = GPIO_OSPEEDR_50M;
-	gpio_init.pupd = GPIO_PUPDR_NONE;
-	gpio_init.type = GPIO_MODER_ALT;
-	gpio_init.func = af_ltdc;
-	gpio_init.o_type = GPIO_OTYPER_PP;
-	gpio_init.pin = 3;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 4;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 6;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 11;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 12;
-	gpio_config(&gpio_init);
-
-	/* GPIOB */
-	gpio_init.port = GPIOB;
-	gpio_init.func = 0x09;
-	gpio_init.pin = 0;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 1;
-	gpio_config(&gpio_init);
-	gpio_init.func = af_ltdc;
-	gpio_init.pin = 8;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 9;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 10;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 11;
-	gpio_config(&gpio_init);
-
-	/* GPIOC */
-	gpio_init.port = GPIOC;
-	gpio_init.pin = 6;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 7;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 10;
-	gpio_config(&gpio_init);
-
-	/* GPIOD */
-	gpio_init.port = GPIOD;
-	gpio_init.pin = 3;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 6;
-	gpio_config(&gpio_init);
-
-	/* GPIOF */
-	gpio_init.port = GPIOF;
-	gpio_init.pin = 10;
-	gpio_config(&gpio_init);
-
-	/* GPIOG */
-	gpio_init.port = GPIOG;
-	gpio_init.pin = 6;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 7;
-	gpio_config(&gpio_init);
-	gpio_init.func = 0x09;
-	gpio_init.pin = 10;
-	gpio_config(&gpio_init);
-	gpio_init.func = af_ltdc;
-	gpio_init.pin = 11;
-	gpio_config(&gpio_init);
-	gpio_init.func = 0x09;
-	gpio_init.pin = 12;
-	gpio_config(&gpio_init);
-
+    struct gpio_cfg gpio_init;
+
+    RCC_AHB1PeriphClockCmd(RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN |
+                               RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN |
+                               RCC_AHB1ENR_GPIOFEN | RCC_AHB1ENR_GPIOGEN,
+                           1);
+
+    /* GPIOA */
+    gpio_init.port = GPIOA;
+    gpio_init.speed = GPIO_OSPEEDR_50M;
+    gpio_init.pupd = GPIO_PUPDR_NONE;
+    gpio_init.type = GPIO_MODER_ALT;
+    gpio_init.func = af_ltdc;
+    gpio_init.o_type = GPIO_OTYPER_PP;
+    gpio_init.pin = 3;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 4;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 6;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 11;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 12;
+    gpio_config(&gpio_init);
+
+    /* GPIOB */
+    gpio_init.port = GPIOB;
+    gpio_init.func = 0x09;
+    gpio_init.pin = 0;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 1;
+    gpio_config(&gpio_init);
+    gpio_init.func = af_ltdc;
+    gpio_init.pin = 8;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 9;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 10;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 11;
+    gpio_config(&gpio_init);
+
+    /* GPIOC */
+    gpio_init.port = GPIOC;
+    gpio_init.pin = 6;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 7;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 10;
+    gpio_config(&gpio_init);
+
+    /* GPIOD */
+    gpio_init.port = GPIOD;
+    gpio_init.pin = 3;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 6;
+    gpio_config(&gpio_init);
+
+    /* GPIOF */
+    gpio_init.port = GPIOF;
+    gpio_init.pin = 10;
+    gpio_config(&gpio_init);
+
+    /* GPIOG */
+    gpio_init.port = GPIOG;
+    gpio_init.pin = 6;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 7;
+    gpio_config(&gpio_init);
+    gpio_init.func = 0x09;
+    gpio_init.pin = 10;
+    gpio_config(&gpio_init);
+    gpio_init.func = af_ltdc;
+    gpio_init.pin = 11;
+    gpio_config(&gpio_init);
+    gpio_init.func = 0x09;
+    gpio_init.pin = 12;
+    gpio_config(&gpio_init);
 }
 
 void __USER_TEXT lcd_layer_init(void)
 {
-	struct ltdc_layer_cfg layer_init;
+    struct ltdc_layer_cfg layer_init;
 
-	/* Initialize Layer1 */
-	layer_init.horizontal_start = 30;
-	layer_init.horizontal_end = (LCD_PIXEL_WIDTH + 30 - 1);
-	layer_init.vertical_start = 4;
-	layer_init.vertical_end = (LCD_PIXEL_HEIGHT + 4 - 1);
+    /* Initialize Layer1 */
+    layer_init.horizontal_start = 30;
+    layer_init.horizontal_end = (LCD_PIXEL_WIDTH + 30 - 1);
+    layer_init.vertical_start = 4;
+    layer_init.vertical_end = (LCD_PIXEL_HEIGHT + 4 - 1);
 
-	layer_init.pixel_format = LTDC_Pixelformat_RGB565;
-	layer_init.constant_alpha = 255;
+    layer_init.pixel_format = LTDC_Pixelformat_RGB565;
+    layer_init.constant_alpha = 255;
 
-	layer_init.default_blue = 0;
-	layer_init.default_green = 0;
-	layer_init.default_red = 0;
-	layer_init.default_alpha = 0;
+    layer_init.default_blue = 0;
+    layer_init.default_green = 0;
+    layer_init.default_red = 0;
+    layer_init.default_alpha = 0;
 
-	layer_init.blending_factor1 = LTDC_BlendingFactor1_CA;
-	layer_init.blending_factor2 = LTDC_BlendingFactor2_CA;
+    layer_init.blending_factor1 = LTDC_BlendingFactor1_CA;
+    layer_init.blending_factor2 = LTDC_BlendingFactor2_CA;
 
-	layer_init.cfb_line_length = ((LCD_PIXEL_WIDTH * 2) + 3);
-	layer_init.cfb_pitch = (LCD_PIXEL_WIDTH * 2);
-	layer_init.cfb_line_number = LCD_PIXEL_HEIGHT;
-	layer_init.cfb_start_address = LCD_FRAME_BUFFER;
+    layer_init.cfb_line_length = ((LCD_PIXEL_WIDTH * 2) + 3);
+    layer_init.cfb_pitch = (LCD_PIXEL_WIDTH * 2);
+    layer_init.cfb_line_number = LCD_PIXEL_HEIGHT;
+    layer_init.cfb_start_address = LCD_FRAME_BUFFER;
 
-	ltdc_layer_config(LTDC_Layer1, &layer_init);
+    ltdc_layer_config(LTDC_Layer1, &layer_init);
 
-	/* Initialize Layer2 */
-	layer_init.cfb_start_address = LCD_FRAME_BUFFER + BUFFER_OFFSET;
+    /* Initialize Layer2 */
+    layer_init.cfb_start_address = LCD_FRAME_BUFFER + BUFFER_OFFSET;
 
-	layer_init.blending_factor1 = LTDC_BlendingFactor1_PAxCA;
-	layer_init.blending_factor2 = LTDC_BlendingFactor2_PAxCA;
+    layer_init.blending_factor1 = LTDC_BlendingFactor1_PAxCA;
+    layer_init.blending_factor2 = LTDC_BlendingFactor2_PAxCA;
 
-	ltdc_layer_config(LTDC_Layer2, &layer_init);
+    ltdc_layer_config(LTDC_Layer2, &layer_init);
 
-	/* ltdc configuration reload */
-	ltdc_reload_config(LTDC_IMReload);
+    /* ltdc configuration reload */
+    ltdc_reload_config(LTDC_IMReload);
 
-	/* Enable Layers */
-	ltdc_layer_cmd(LTDC_Layer1, 1);
-	ltdc_layer_cmd(LTDC_Layer2, 1);
+    /* Enable Layers */
+    ltdc_layer_cmd(LTDC_Layer1, 1);
+    ltdc_layer_cmd(LTDC_Layer2, 1);
 
-	/* ltdc configuration reload */
-	ltdc_reload_config(LTDC_IMReload);
+    /* ltdc configuration reload */
+    ltdc_reload_config(LTDC_IMReload);
 
-	/* dithering activation */
-	ltdc_dither_cmd(1);
+    /* dithering activation */
+    ltdc_dither_cmd(1);
 }
 
 void __USER_TEXT lcd_set_text_color(uint16_t color)
 {
-	current_Tcolor = color;
+    current_Tcolor = color;
 }
 
 void __USER_TEXT lcd_set_back_color(uint16_t color)
 {
-	current_Bcolor = color;
+    current_Bcolor = color;
 }
 
 void __USER_TEXT lcd_set_layer(uint32_t layerx)
 {
-	if (layerx == LCD_BACKGROUND_LAYER) {
-		current_frame_buffer = LCD_FRAME_BUFFER;
-		current_layer = LCD_BACKGROUND_LAYER;
-	} else {
-		current_frame_buffer = LCD_FRAME_BUFFER + BUFFER_OFFSET;
-		current_layer = LCD_FOREGROUND_LAYER;
-	}
+    if (layerx == LCD_BACKGROUND_LAYER) {
+        current_frame_buffer = LCD_FRAME_BUFFER;
+        current_layer = LCD_BACKGROUND_LAYER;
+    } else {
+        current_frame_buffer = LCD_FRAME_BUFFER + BUFFER_OFFSET;
+        current_layer = LCD_FOREGROUND_LAYER;
+    }
 }
 
 void __USER_TEXT lcd_clear(uint16_t color)
 {
-	uint32_t index = 0;
+    uint32_t index = 0;
 
-	for (index = 0x00; index < BUFFER_OFFSET; index++) {
-		*(volatile uint16_t *)(current_frame_buffer + (2 * index)) = color;
-	}
+    for (index = 0x00; index < BUFFER_OFFSET; index++) {
+        *(volatile uint16_t *) (current_frame_buffer + (2 * index)) = color;
+    }
 }
 
-void __USER_TEXT lcd_draw_line(uint16_t x, uint16_t y, uint16_t length, uint8_t direction)
+void __USER_TEXT lcd_draw_line(uint16_t x,
+                               uint16_t y,
+                               uint16_t length,
+                               uint8_t direction)
 {
-	struct dma2d_cfg dma2d_init;
-	uint32_t Xaddr = 0;
-	uint16_t red = 0, green = 0, blue = 0;
-
-	Xaddr = current_frame_buffer + 2 * (LCD_PIXEL_WIDTH * y + x);
-
-	red = (0xF800 & current_Tcolor) >> 11;
-	blue = 0x001F & current_Tcolor;
-	green = (0x07E0 & current_Tcolor) >> 5;
-
-	/* Initialize DMA2D */
-	dma2d_reset();
-	dma2d_init.mode = DMA2D_R2M;
-	dma2d_init.cmode = DMA2D_RGB565;
-	dma2d_init.output_green = green;
-	dma2d_init.output_blue = blue;
-	dma2d_init.output_red = red;
-	dma2d_init.output_alpha = 0x0F;
-	dma2d_init.output_memory_address = Xaddr;
-
-	if (direction == LCD_DIR_HORIZONTAL) {
-		dma2d_init.output_offset = 0;
-		dma2d_init.number_of_line = 1;
-		dma2d_init.pixel_per_line = length;
-	} else {
-		dma2d_init.output_offset = LCD_PIXEL_WIDTH - 1;
-		dma2d_init.number_of_line = length;
-		dma2d_init.pixel_per_line = 1;
-	}
-	dma2d_config(&dma2d_init);
-
-	dma2d_start_transfer();
-
-	while (dma2d_get_flag(DMA2D_FLAG_TC) == 0) ;
+    struct dma2d_cfg dma2d_init;
+    uint32_t Xaddr = 0;
+    uint16_t red = 0, green = 0, blue = 0;
+
+    Xaddr = current_frame_buffer + 2 * (LCD_PIXEL_WIDTH * y + x);
+
+    red = (0xF800 & current_Tcolor) >> 11;
+    blue = 0x001F & current_Tcolor;
+    green = (0x07E0 & current_Tcolor) >> 5;
+
+    /* Initialize DMA2D */
+    dma2d_reset();
+    dma2d_init.mode = DMA2D_R2M;
+    dma2d_init.cmode = DMA2D_RGB565;
+    dma2d_init.output_green = green;
+    dma2d_init.output_blue = blue;
+    dma2d_init.output_red = red;
+    dma2d_init.output_alpha = 0x0F;
+    dma2d_init.output_memory_address = Xaddr;
+
+    if (direction == LCD_DIR_HORIZONTAL) {
+        dma2d_init.output_offset = 0;
+        dma2d_init.number_of_line = 1;
+        dma2d_init.pixel_per_line = length;
+    } else {
+        dma2d_init.output_offset = LCD_PIXEL_WIDTH - 1;
+        dma2d_init.number_of_line = length;
+        dma2d_init.pixel_per_line = 1;
+    }
+    dma2d_config(&dma2d_init);
+
+    dma2d_start_transfer();
+
+    while (dma2d_get_flag(DMA2D_FLAG_TC) == 0)
+        ;
 }
 
-void __USER_TEXT lcd_draw_rect(uint16_t x, uint16_t y, uint16_t height, uint16_t width)
+void __USER_TEXT lcd_draw_rect(uint16_t x,
+                               uint16_t y,
+                               uint16_t height,
+                               uint16_t width)
 {
-	lcd_draw_line(x, y, width, LCD_DIR_HORIZONTAL);
-	lcd_draw_line(x, (y + height), width, LCD_DIR_HORIZONTAL);
+    lcd_draw_line(x, y, width, LCD_DIR_HORIZONTAL);
+    lcd_draw_line(x, (y + height), width, LCD_DIR_HORIZONTAL);
 
-	lcd_draw_line(x, y, height, LCD_DIR_VERTICAL);
-	lcd_draw_line((x + width), y, height, LCD_DIR_VERTICAL);
+    lcd_draw_line(x, y, height, LCD_DIR_VERTICAL);
+    lcd_draw_line((x + width), y, height, LCD_DIR_VERTICAL);
 }
 
-void __USER_TEXT lcd_fill_rect(uint16_t x, uint16_t y, uint16_t height, uint16_t width)
+void __USER_TEXT lcd_fill_rect(uint16_t x,
+                               uint16_t y,
+                               uint16_t height,
+                               uint16_t width)
 {
-	struct dma2d_cfg dma2d_init;
+    struct dma2d_cfg dma2d_init;
 
-	uint32_t Xaddr = 0;
-	uint16_t red = 0, green = 0, blue = 0;
+    uint32_t Xaddr = 0;
+    uint16_t red = 0, green = 0, blue = 0;
 
-	Xaddr = current_frame_buffer + 2 * (LCD_PIXEL_WIDTH * y + x);
+    Xaddr = current_frame_buffer + 2 * (LCD_PIXEL_WIDTH * y + x);
 
-	red = (0xF800 & current_Tcolor) >> 11;
-	blue = 0x001F & current_Tcolor;
-	green = (0x07E0 & current_Tcolor) >> 5;
+    red = (0xF800 & current_Tcolor) >> 11;
+    blue = 0x001F & current_Tcolor;
+    green = (0x07E0 & current_Tcolor) >> 5;
 
-	dma2d_reset();
-	dma2d_init.mode = DMA2D_R2M;
-	dma2d_init.cmode = DMA2D_RGB565;
-	dma2d_init.output_green = green;
-	dma2d_init.output_blue = blue;
-	dma2d_init.output_red = red;
-	dma2d_init.output_alpha = 0x0F;
-	dma2d_init.output_memory_address = Xaddr;
-	dma2d_init.output_offset = (LCD_PIXEL_WIDTH - width);
-	dma2d_init.number_of_line = height;
-	dma2d_init.pixel_per_line = width;
-	dma2d_config(&dma2d_init);
+    dma2d_reset();
+    dma2d_init.mode = DMA2D_R2M;
+    dma2d_init.cmode = DMA2D_RGB565;
+    dma2d_init.output_green = green;
+    dma2d_init.output_blue = blue;
+    dma2d_init.output_red = red;
+    dma2d_init.output_alpha = 0x0F;
+    dma2d_init.output_memory_address = Xaddr;
+    dma2d_init.output_offset = (LCD_PIXEL_WIDTH - width);
+    dma2d_init.number_of_line = height;
+    dma2d_init.pixel_per_line = width;
+    dma2d_config(&dma2d_init);
 
-	dma2d_start_transfer();
+    dma2d_start_transfer();
 
-	while (dma2d_get_flag(DMA2D_FLAG_TC) == 0) ;
+    while (dma2d_get_flag(DMA2D_FLAG_TC) == 0)
+        ;
 
-	lcd_set_text_color(current_Tcolor);
+    lcd_set_text_color(current_Tcolor);
 }
diff --git a/platform/stm32f429/ltdc.c b/platform/stm32f429/ltdc.c
index d3cd00af..9270afaf 100644
--- a/platform/stm32f429/ltdc.c
+++ b/platform/stm32f429/ltdc.c
@@ -1,139 +1,139 @@
 #include <platform/stm32f429/ltdc.h>
 
-#define GCR_MASK                    ((uint32_t)0x0FFE888F)
+#define GCR_MASK ((uint32_t) 0x0FFE888F)
 
 void __USER_TEXT ltdc_config(struct ltdc_cfg *cfg)
 {
-	uint32_t horizontalsync = 0;
-	uint32_t accumulatedHBP = 0;
-	uint32_t accumulatedactiveW = 0;
-	uint32_t totalwidth = 0;
-	uint32_t backgreen = 0;
-	uint32_t backred = 0;
-
-	/* TODO: assertion */
-
-	/* synchronization size */
-	*LTDC_SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
-	horizontalsync = (cfg->horizontal_sync << 16);
-	*LTDC_SSCR |= (horizontalsync | cfg->vertical_sync);
-
-	/* accumulated back porch */
-	*LTDC_BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
-	accumulatedHBP = (cfg->accumulated_hbp << 16);
-	*LTDC_BPCR |= (accumulatedHBP | cfg->accumulated_vbp);
-
-	/* accumulated active width */
-	*LTDC_AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
-	accumulatedactiveW = (cfg->accumulated_active_w << 16);
-	*LTDC_AWCR |= (accumulatedactiveW | cfg->accumulated_active_h);
-
-	/* total width */
-	*LTDC_TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
-	totalwidth = (cfg->total_width << 16);
-	*LTDC_TWCR |= (totalwidth | cfg->total_height);
-
-	*LTDC_GCR &= (uint32_t)GCR_MASK;
-	*LTDC_GCR |= (uint32_t)(cfg->hs_polarity | cfg->vs_polarity | \
-	                        cfg->de_polarity | cfg->pc_polarity);
-
-	/* background color */
-	backgreen = (cfg->bg_green_value << 8);
-	backred = (cfg->bg_red_value << 16);
-
-	*LTDC_BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
-	*LTDC_BCCR |= (backred | backgreen | cfg->bg_blue_value);
+    uint32_t horizontalsync = 0;
+    uint32_t accumulatedHBP = 0;
+    uint32_t accumulatedactiveW = 0;
+    uint32_t totalwidth = 0;
+    uint32_t backgreen = 0;
+    uint32_t backred = 0;
+
+    /* TODO: assertion */
+
+    /* synchronization size */
+    *LTDC_SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
+    horizontalsync = (cfg->horizontal_sync << 16);
+    *LTDC_SSCR |= (horizontalsync | cfg->vertical_sync);
+
+    /* accumulated back porch */
+    *LTDC_BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
+    accumulatedHBP = (cfg->accumulated_hbp << 16);
+    *LTDC_BPCR |= (accumulatedHBP | cfg->accumulated_vbp);
+
+    /* accumulated active width */
+    *LTDC_AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
+    accumulatedactiveW = (cfg->accumulated_active_w << 16);
+    *LTDC_AWCR |= (accumulatedactiveW | cfg->accumulated_active_h);
+
+    /* total width */
+    *LTDC_TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
+    totalwidth = (cfg->total_width << 16);
+    *LTDC_TWCR |= (totalwidth | cfg->total_height);
+
+    *LTDC_GCR &= (uint32_t) GCR_MASK;
+    *LTDC_GCR |= (uint32_t) (cfg->hs_polarity | cfg->vs_polarity |
+                             cfg->de_polarity | cfg->pc_polarity);
+
+    /* background color */
+    backgreen = (cfg->bg_green_value << 8);
+    backred = (cfg->bg_red_value << 16);
+
+    *LTDC_BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
+    *LTDC_BCCR |= (backred | backgreen | cfg->bg_blue_value);
 }
 
 void __USER_TEXT ltdc_layer_config(uint32_t layerx, struct ltdc_layer_cfg *cfg)
 {
-	uint32_t whsppos = 0;
-	uint32_t wvsppos = 0;
-	uint32_t dcgreen = 0;
-	uint32_t dcred = 0;
-	uint32_t dcalpha = 0;
-	uint32_t cfbp = 0;
-
-	/* TODO: assertion */
-
-	/* horizontal start and end position */
-	whsppos = cfg->horizontal_end << 16;
-	*LTDC_Layer_WHPCR(layerx) &= ~(LTDC_LxWHPCR_WHSPOS | LTDC_LxWHPCR_WHEPOS);
-	*LTDC_Layer_WHPCR(layerx) = (cfg->horizontal_start | whsppos);
-
-	/* vertical start and end position */
-	wvsppos = cfg->vertical_end << 16;
-	*LTDC_Layer_WVPCR(layerx) &= ~(LTDC_LxWVPCR_WVSPOS | LTDC_LxWVPCR_WVEPOS);
-	*LTDC_Layer_WVPCR(layerx) = (cfg->vertical_start | wvsppos);
-
-	/* pixel format */
-	*LTDC_Layer_PFCR(layerx) &= ~(LTDC_LxPFCR_PF);
-	*LTDC_Layer_PFCR(layerx) = (cfg->pixel_format);
-
-	/* default color */
-	dcgreen = (cfg->default_green << 8);
-	dcred = (cfg->default_red << 16);
-	dcalpha = (cfg->default_alpha << 24);
-	*LTDC_Layer_DCCR(layerx) &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
-	*LTDC_Layer_DCCR(layerx) = (cfg->default_blue | dcgreen | dcred | dcalpha);
-
-	/* constant alpha value */
-	*LTDC_Layer_CACR(layerx) &= ~(LTDC_LxCACR_CONSTA);
-	*LTDC_Layer_CACR(layerx) = (cfg->constant_alpha);
-
-	/* blending factors */
-	*LTDC_Layer_BFCR(layerx) &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
-	*LTDC_Layer_BFCR(layerx) = (cfg->blending_factor1 | cfg->blending_factor2);
-
-	/* color frame buffer start address */
-	*LTDC_Layer_CFBAR(layerx) &= ~(LTDC_LxCFBAR_CFBADD);
-	*LTDC_Layer_CFBAR(layerx) = (cfg->cfb_start_address);
-
-	/* color frame buffer pitch in byte */
-	cfbp = (cfg->cfb_pitch << 16);
-	*LTDC_Layer_CFBLR(layerx) &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
-	*LTDC_Layer_CFBLR(layerx) = (cfg->cfb_line_length | cfbp);
-
-	/* color frame buffer line number */
-	*LTDC_Layer_CFBLNR(layerx) &= ~(LTDC_LxCFBLNR_CFBLNBR);
-	*LTDC_Layer_CFBLNR(layerx) = (cfg->cfb_line_number);
+    uint32_t whsppos = 0;
+    uint32_t wvsppos = 0;
+    uint32_t dcgreen = 0;
+    uint32_t dcred = 0;
+    uint32_t dcalpha = 0;
+    uint32_t cfbp = 0;
+
+    /* TODO: assertion */
+
+    /* horizontal start and end position */
+    whsppos = cfg->horizontal_end << 16;
+    *LTDC_Layer_WHPCR(layerx) &= ~(LTDC_LxWHPCR_WHSPOS | LTDC_LxWHPCR_WHEPOS);
+    *LTDC_Layer_WHPCR(layerx) = (cfg->horizontal_start | whsppos);
+
+    /* vertical start and end position */
+    wvsppos = cfg->vertical_end << 16;
+    *LTDC_Layer_WVPCR(layerx) &= ~(LTDC_LxWVPCR_WVSPOS | LTDC_LxWVPCR_WVEPOS);
+    *LTDC_Layer_WVPCR(layerx) = (cfg->vertical_start | wvsppos);
+
+    /* pixel format */
+    *LTDC_Layer_PFCR(layerx) &= ~(LTDC_LxPFCR_PF);
+    *LTDC_Layer_PFCR(layerx) = (cfg->pixel_format);
+
+    /* default color */
+    dcgreen = (cfg->default_green << 8);
+    dcred = (cfg->default_red << 16);
+    dcalpha = (cfg->default_alpha << 24);
+    *LTDC_Layer_DCCR(layerx) &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN |
+                                  LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
+    *LTDC_Layer_DCCR(layerx) = (cfg->default_blue | dcgreen | dcred | dcalpha);
+
+    /* constant alpha value */
+    *LTDC_Layer_CACR(layerx) &= ~(LTDC_LxCACR_CONSTA);
+    *LTDC_Layer_CACR(layerx) = (cfg->constant_alpha);
+
+    /* blending factors */
+    *LTDC_Layer_BFCR(layerx) &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
+    *LTDC_Layer_BFCR(layerx) = (cfg->blending_factor1 | cfg->blending_factor2);
+
+    /* color frame buffer start address */
+    *LTDC_Layer_CFBAR(layerx) &= ~(LTDC_LxCFBAR_CFBADD);
+    *LTDC_Layer_CFBAR(layerx) = (cfg->cfb_start_address);
+
+    /* color frame buffer pitch in byte */
+    cfbp = (cfg->cfb_pitch << 16);
+    *LTDC_Layer_CFBLR(layerx) &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
+    *LTDC_Layer_CFBLR(layerx) = (cfg->cfb_line_length | cfbp);
+
+    /* color frame buffer line number */
+    *LTDC_Layer_CFBLNR(layerx) &= ~(LTDC_LxCFBLNR_CFBLNBR);
+    *LTDC_Layer_CFBLNR(layerx) = (cfg->cfb_line_number);
 }
 
 void __USER_TEXT ltdc_reload_config(uint32_t reload)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	*LTDC_SRCR = (uint32_t)reload;
+    *LTDC_SRCR = (uint32_t) reload;
 }
 
 void __USER_TEXT ltdc_cmd(uint8_t enable)
 {
-
-	if (enable != 0) {
-		*LTDC_GCR |= (uint32_t)LTDC_GCR_LTDCEN;
-	} else {
-		*LTDC_GCR &= ~(uint32_t)LTDC_GCR_LTDCEN;
-	}
+    if (enable != 0) {
+        *LTDC_GCR |= (uint32_t) LTDC_GCR_LTDCEN;
+    } else {
+        *LTDC_GCR &= ~(uint32_t) LTDC_GCR_LTDCEN;
+    }
 }
 
 void __USER_TEXT ltdc_layer_cmd(uint32_t layerx, uint8_t enable)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	if (enable != 0) {
-		*LTDC_Layer_CR(layerx) |= (uint32_t)LTDC_LxCR_LEN;
-	} else {
-		*LTDC_Layer_CR(layerx) &= ~(uint32_t)LTDC_LxCR_LEN;
-	}
+    if (enable != 0) {
+        *LTDC_Layer_CR(layerx) |= (uint32_t) LTDC_LxCR_LEN;
+    } else {
+        *LTDC_Layer_CR(layerx) &= ~(uint32_t) LTDC_LxCR_LEN;
+    }
 }
 
 void __USER_TEXT ltdc_dither_cmd(uint8_t enable)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	if (enable != 0) {
-		*LTDC_GCR |= (uint32_t)LTDC_GCR_DTEN;
-	} else {
-		*LTDC_GCR &= ~(uint32_t)LTDC_GCR_DTEN;
-	}
+    if (enable != 0) {
+        *LTDC_GCR |= (uint32_t) LTDC_GCR_DTEN;
+    } else {
+        *LTDC_GCR &= ~(uint32_t) LTDC_GCR_DTEN;
+    }
 }
diff --git a/platform/stm32f429/rcc.c b/platform/stm32f429/rcc.c
index 338abc06..9faabecc 100644
--- a/platform/stm32f429/rcc.c
+++ b/platform/stm32f429/rcc.c
@@ -3,48 +3,50 @@
  * found in the LICENSE file.
  */
 
-#define RCC_OFFSET              (RCC_BASE - PERIPH_BASE)
-#define CR_OFFSET               (RCC_OFFSET + 0x00)
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+#define CR_OFFSET (RCC_OFFSET + 0x00)
 /* Alias word address of PLLSAION bit */
-#define PLLSAION_BitNumber      0x1C
-#define CR_PLLSAION_BB          (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
+#define PLLSAION_BitNumber 0x1C
+#define CR_PLLSAION_BB \
+    (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
 
 void __USER_TEXT RCC_AHB3PeriphClockCmd(uint32_t rcc_AHB3, uint8_t enable)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	if (enable != 0)
-		*RCC_AHB3ENR |= rcc_AHB3;
-	else
-		*RCC_AHB3ENR &= ~rcc_AHB3;
+    if (enable != 0)
+        *RCC_AHB3ENR |= rcc_AHB3;
+    else
+        *RCC_AHB3ENR &= ~rcc_AHB3;
 }
 
-void __USER_TEXT RCC_PLLSAIConfig(uint32_t pllsain, uint32_t pllsaiq, uint32_t pllsair)
+void __USER_TEXT RCC_PLLSAIConfig(uint32_t pllsain,
+                                  uint32_t pllsaiq,
+                                  uint32_t pllsair)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	*RCC_PLLSAICFGR = (pllsain << 6) | (pllsaiq << 24) | (pllsair << 28);
+    *RCC_PLLSAICFGR = (pllsain << 6) | (pllsaiq << 24) | (pllsair << 28);
 }
 
 void __USER_TEXT RCC_LTDCCLKDivConfig(uint32_t div)
 {
-	uint32_t tmpreg = 0;
+    uint32_t tmpreg = 0;
 
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	tmpreg = *RCC_DCKCFGR;
+    tmpreg = *RCC_DCKCFGR;
 
-	tmpreg &= ~~RCC_DCKCFGR_PLLSAIDIVR;
+    tmpreg &= ~~RCC_DCKCFGR_PLLSAIDIVR;
 
-	tmpreg |= div;
+    tmpreg |= div;
 
-	*RCC_DCKCFGR = tmpreg;
+    *RCC_DCKCFGR = tmpreg;
 }
 
 void __USER_TEXT RCC_PLLSAICmd(uint32_t enable)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	*(volatile uint32_t *)CR_PLLSAION_BB = enable;
+    *(volatile uint32_t *) CR_PLLSAION_BB = enable;
 }
-
diff --git a/platform/stm32f429/sdram.c b/platform/stm32f429/sdram.c
index 36b3a5fb..e41fa891 100644
--- a/platform/stm32f429/sdram.c
+++ b/platform/stm32f429/sdram.c
@@ -1,213 +1,218 @@
-#include <platform/stm32f429/sdram.h>
-#include <platform/stm32f429/rcc.h>
-#include <platform/stm32f429/gpio.h>
 #include <platform/stm32f429/fmc.h>
+#include <platform/stm32f429/gpio.h>
+#include <platform/stm32f429/rcc.h>
+#include <platform/stm32f429/sdram.h>
 
 void static sdram_gpio_init(void);
 void static sdram_init_seq(void);
 
 void __USER_TEXT sdram_init(void)
 {
-	struct fmc_sdram_timing_cfg fs_timing_init;
-	struct fmc_sdram_cfg fs_init;
-
-	sdram_gpio_init();
-
-	RCC_AHB3PeriphClockCmd(RCC_AHB3ENR_FMCEN, 1);
-
-	fs_timing_init.lta_delay = 2; /* 2 clock cycles */
-	fs_timing_init.esr_delay = 7; /* 70ns */
-	fs_timing_init.sr_time = 4; /* 42ns */
-	fs_timing_init.rc_delay = 7; /* 70 */
-	fs_timing_init.wr_time = 2; /* 1+ 7ns */
-	fs_timing_init.rp_delay = 2; /* 20ns */
-	fs_timing_init.rcd_delay = 2; /* 20ns */
-
-	fs_init.bank = FMC_Bank2_SDRAM;
-	fs_init.column_bits_number = FMC_ColumnBits_Number_8b;
-	fs_init.row_bits_number = FMC_RowBits_Number_12b;
-	fs_init.sdmemory_data_width = SDRAM_MEMORY_WIDTH;
-	fs_init.internal_bank_number = FMC_InternalBank_Number_4;
-	fs_init.cas_latency = SDRAM_CAS_LATENCY;
-	fs_init.write_protection = FMC_Write_Protection_Disable;
-	fs_init.sd_clock_period = SDCLOCK_PERIOD;
-	fs_init.readburst = SDRAM_READBURST;
-	fs_init.readpipe_delay = FMC_ReadPipe_Delay_1;
-	fs_init.timing = &fs_timing_init;
-
-	fmc_sdram_config(&fs_init);
-
-	sdram_init_seq();
+    struct fmc_sdram_timing_cfg fs_timing_init;
+    struct fmc_sdram_cfg fs_init;
+
+    sdram_gpio_init();
+
+    RCC_AHB3PeriphClockCmd(RCC_AHB3ENR_FMCEN, 1);
+
+    fs_timing_init.lta_delay = 2; /* 2 clock cycles */
+    fs_timing_init.esr_delay = 7; /* 70ns */
+    fs_timing_init.sr_time = 4;   /* 42ns */
+    fs_timing_init.rc_delay = 7;  /* 70 */
+    fs_timing_init.wr_time = 2;   /* 1+ 7ns */
+    fs_timing_init.rp_delay = 2;  /* 20ns */
+    fs_timing_init.rcd_delay = 2; /* 20ns */
+
+    fs_init.bank = FMC_Bank2_SDRAM;
+    fs_init.column_bits_number = FMC_ColumnBits_Number_8b;
+    fs_init.row_bits_number = FMC_RowBits_Number_12b;
+    fs_init.sdmemory_data_width = SDRAM_MEMORY_WIDTH;
+    fs_init.internal_bank_number = FMC_InternalBank_Number_4;
+    fs_init.cas_latency = SDRAM_CAS_LATENCY;
+    fs_init.write_protection = FMC_Write_Protection_Disable;
+    fs_init.sd_clock_period = SDCLOCK_PERIOD;
+    fs_init.readburst = SDRAM_READBURST;
+    fs_init.readpipe_delay = FMC_ReadPipe_Delay_1;
+    fs_init.timing = &fs_timing_init;
+
+    fmc_sdram_config(&fs_init);
+
+    sdram_init_seq();
 }
 
 void static __USER_TEXT sdram_gpio_init(void)
 {
-	struct gpio_cfg gpio_init;
-
-	RCC_AHB1PeriphClockCmd(RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
-	                       RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | RCC_AHB1ENR_GPIOGEN, 1);
-
-	/* GPIOB */
-	gpio_init.port = GPIOB;
-	gpio_init.type = GPIO_MODER_ALT;
-	gpio_init.speed = GPIO_OSPEEDR_50M;
-	gpio_init.pupd = GPIO_PUPDR_NONE;
-	gpio_init.o_type = GPIO_OTYPER_PP;
-	gpio_init.func = af_fmc;
-	gpio_init.pin = 5;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 6;
-	gpio_config(&gpio_init);
-
-	/* GPIOC */
-	gpio_init.port = GPIOC;
-	gpio_init.pin = 0;
-	gpio_config(&gpio_init);
-
-	/* GPIOD */
-	gpio_init.port = GPIOD;
-	gpio_init.pin = 0;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 1;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 8;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 9;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 10;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 14;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 15;
-	gpio_config(&gpio_init);
-
-	/* GPIOE */
-	gpio_init.port = GPIOE;
-	gpio_init.pin = 0;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 1;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 7;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 8;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 9;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 10;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 11;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 12;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 13;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 14;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 15;
-	gpio_config(&gpio_init);
-
-	/* GPIOF */
-	gpio_init.port = GPIOF;
-	gpio_init.pin = 0;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 1;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 2;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 3;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 4;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 5;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 11;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 12;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 13;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 14;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 15;
-	gpio_config(&gpio_init);
-
-	/* GPIOG */
-	gpio_init.port = GPIOG;
-	gpio_init.pin = 0;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 1;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 4;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 5;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 8;
-	gpio_config(&gpio_init);
-	gpio_init.pin = 15;
-	gpio_config(&gpio_init);
-
+    struct gpio_cfg gpio_init;
+
+    RCC_AHB1PeriphClockCmd(RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN |
+                               RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN |
+                               RCC_AHB1ENR_GPIOFEN | RCC_AHB1ENR_GPIOGEN,
+                           1);
+
+    /* GPIOB */
+    gpio_init.port = GPIOB;
+    gpio_init.type = GPIO_MODER_ALT;
+    gpio_init.speed = GPIO_OSPEEDR_50M;
+    gpio_init.pupd = GPIO_PUPDR_NONE;
+    gpio_init.o_type = GPIO_OTYPER_PP;
+    gpio_init.func = af_fmc;
+    gpio_init.pin = 5;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 6;
+    gpio_config(&gpio_init);
+
+    /* GPIOC */
+    gpio_init.port = GPIOC;
+    gpio_init.pin = 0;
+    gpio_config(&gpio_init);
+
+    /* GPIOD */
+    gpio_init.port = GPIOD;
+    gpio_init.pin = 0;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 1;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 8;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 9;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 10;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 14;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 15;
+    gpio_config(&gpio_init);
+
+    /* GPIOE */
+    gpio_init.port = GPIOE;
+    gpio_init.pin = 0;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 1;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 7;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 8;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 9;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 10;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 11;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 12;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 13;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 14;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 15;
+    gpio_config(&gpio_init);
+
+    /* GPIOF */
+    gpio_init.port = GPIOF;
+    gpio_init.pin = 0;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 1;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 2;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 3;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 4;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 5;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 11;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 12;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 13;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 14;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 15;
+    gpio_config(&gpio_init);
+
+    /* GPIOG */
+    gpio_init.port = GPIOG;
+    gpio_init.pin = 0;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 1;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 4;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 5;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 8;
+    gpio_config(&gpio_init);
+    gpio_init.pin = 15;
+    gpio_config(&gpio_init);
 }
 
 void static __USER_TEXT sdram_init_seq(void)
 {
-	uint32_t i;
-	uint32_t tmpr = 0;
-	struct fmc_sdram_cmd fs_cmd;
-
-	fs_cmd.mode = FMC_Command_Mode_CLK_Enabled;
-	fs_cmd.target = FMC_Command_Target_bank2;
-	fs_cmd.auto_refresh_number = 1;
-	fs_cmd.mode_register_definition = 0;
+    uint32_t i;
+    uint32_t tmpr = 0;
+    struct fmc_sdram_cmd fs_cmd;
 
-	while (fmc_get_flag(FMC_Bank2_SDRAM, FMC_FLAG_BUSY) != 0) ;
+    fs_cmd.mode = FMC_Command_Mode_CLK_Enabled;
+    fs_cmd.target = FMC_Command_Target_bank2;
+    fs_cmd.auto_refresh_number = 1;
+    fs_cmd.mode_register_definition = 0;
 
-	fmc_sdram_cmd_init(&fs_cmd);
+    while (fmc_get_flag(FMC_Bank2_SDRAM, FMC_FLAG_BUSY) != 0)
+        ;
 
-	/* delay 100ms */
-	/* FIXME: a proper delay */
-	i = 0;
-	while (i < 100)
-		i++;
+    fmc_sdram_cmd_init(&fs_cmd);
 
-	fs_cmd.mode = FMC_Command_Mode_PALL;
-	fs_cmd.target = FMC_Command_Target_bank2;
-	fs_cmd.auto_refresh_number = 1;
-	fs_cmd.mode_register_definition = 0;
+    /* delay 100ms */
+    /* FIXME: a proper delay */
+    i = 0;
+    while (i < 100)
+        i++;
 
-	while (fmc_get_flag(FMC_Bank2_SDRAM, FMC_FLAG_BUSY) != 0) ;
+    fs_cmd.mode = FMC_Command_Mode_PALL;
+    fs_cmd.target = FMC_Command_Target_bank2;
+    fs_cmd.auto_refresh_number = 1;
+    fs_cmd.mode_register_definition = 0;
 
-	fmc_sdram_cmd_init(&fs_cmd);
+    while (fmc_get_flag(FMC_Bank2_SDRAM, FMC_FLAG_BUSY) != 0)
+        ;
 
-	fs_cmd.mode = FMC_Command_Mode_AutoRefresh;
-	fs_cmd.target = FMC_Command_Target_bank2;
-	fs_cmd.auto_refresh_number = 4;
-	fs_cmd.mode_register_definition = 0;
+    fmc_sdram_cmd_init(&fs_cmd);
 
-	while (fmc_get_flag(FMC_Bank2_SDRAM, FMC_FLAG_BUSY) != 0) ;
+    fs_cmd.mode = FMC_Command_Mode_AutoRefresh;
+    fs_cmd.target = FMC_Command_Target_bank2;
+    fs_cmd.auto_refresh_number = 4;
+    fs_cmd.mode_register_definition = 0;
 
-	fmc_sdram_cmd_init(&fs_cmd);
+    while (fmc_get_flag(FMC_Bank2_SDRAM, FMC_FLAG_BUSY) != 0)
+        ;
 
-	while (fmc_get_flag(FMC_Bank2_SDRAM, FMC_FLAG_BUSY) != 0) ;
+    fmc_sdram_cmd_init(&fs_cmd);
 
-	fmc_sdram_cmd_init(&fs_cmd);
+    while (fmc_get_flag(FMC_Bank2_SDRAM, FMC_FLAG_BUSY) != 0)
+        ;
 
-	tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2          |
-	       SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL   |
-	       SDRAM_MODEREG_CAS_LATENCY_3           |
-	       SDRAM_MODEREG_OPERATING_MODE_STANDARD |
-	       SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
+    fmc_sdram_cmd_init(&fs_cmd);
 
-	fs_cmd.mode = FMC_Command_Mode_LoadMode;
-	fs_cmd.target = FMC_Command_Target_bank2;
-	fs_cmd.auto_refresh_number = 1;
-	fs_cmd.mode_register_definition = tmpr;
+    tmpr = (uint32_t) SDRAM_MODEREG_BURST_LENGTH_2 |
+           SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | SDRAM_MODEREG_CAS_LATENCY_3 |
+           SDRAM_MODEREG_OPERATING_MODE_STANDARD |
+           SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
 
-	while (fmc_get_flag(FMC_Bank2_SDRAM, FMC_FLAG_BUSY) != 0) ;
+    fs_cmd.mode = FMC_Command_Mode_LoadMode;
+    fs_cmd.target = FMC_Command_Target_bank2;
+    fs_cmd.auto_refresh_number = 1;
+    fs_cmd.mode_register_definition = tmpr;
 
-	fmc_sdram_cmd_init(&fs_cmd);
+    while (fmc_get_flag(FMC_Bank2_SDRAM, FMC_FLAG_BUSY) != 0)
+        ;
 
-	fmc_set_refresh_count(1386);
+    fmc_sdram_cmd_init(&fs_cmd);
 
-	while (fmc_get_flag(FMC_Bank2_SDRAM, FMC_FLAG_BUSY) != 0) ;
+    fmc_set_refresh_count(1386);
 
+    while (fmc_get_flag(FMC_Bank2_SDRAM, FMC_FLAG_BUSY) != 0)
+        ;
 }
diff --git a/platform/stm32f429/spi.c b/platform/stm32f429/spi.c
index 087d7609..25423fb3 100644
--- a/platform/stm32f429/spi.c
+++ b/platform/stm32f429/spi.c
@@ -1,66 +1,66 @@
-#include <platform/stm32f429/spi.h>
 #include <platform/stm32f429/rcc.h>
+#include <platform/stm32f429/spi.h>
 
-#define CR1_CLEAR_MASK           ((uint16_t)0x3040)
-#define SPI_I2SCFGR_I2SMOD       ((uint16_t)0x0800)
+#define CR1_CLEAR_MASK ((uint16_t) 0x3040)
+#define SPI_I2SCFGR_I2SMOD ((uint16_t) 0x0800)
 
 void __USER_TEXT spi_config(uint32_t spix, struct spi_cfg *spi_init)
 {
-	uint16_t tmpreg = 0;
+    uint16_t tmpreg = 0;
 
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	tmpreg = *SPI_CR1(spix);
-	tmpreg &= CR1_CLEAR_MASK;
+    tmpreg = *SPI_CR1(spix);
+    tmpreg &= CR1_CLEAR_MASK;
 
-	tmpreg |= (uint16_t)((uint32_t)spi_init->direction | spi_init->mode |
-	                     spi_init->size | spi_init->cpol | spi_init->cpha |
-	                     spi_init->nss | spi_init->baudrate |
-	                     spi_init->firstbit);
+    tmpreg |=
+        (uint16_t) ((uint32_t) spi_init->direction | spi_init->mode |
+                    spi_init->size | spi_init->cpol | spi_init->cpha |
+                    spi_init->nss | spi_init->baudrate | spi_init->firstbit);
 
-	*SPI_CR1(spix) = tmpreg;
-	*SPI_I2SCFGR(spix) &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
-	*SPI_CRCPR(spix) = spi_init->crcpolynomial;
+    *SPI_CR1(spix) = tmpreg;
+    *SPI_I2SCFGR(spix) &= (uint16_t) ~((uint16_t) SPI_I2SCFGR_I2SMOD);
+    *SPI_CRCPR(spix) = spi_init->crcpolynomial;
 }
 
 void __USER_TEXT spi_cmd(uint32_t spix, uint8_t enable)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	if (enable != 0)
-		*SPI_CR1(spix) |= SPI_CR1_SPE;
-	else
-		*SPI_CR1(spix) &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
+    if (enable != 0)
+        *SPI_CR1(spix) |= SPI_CR1_SPE;
+    else
+        *SPI_CR1(spix) &= (uint16_t) ~((uint16_t) SPI_CR1_SPE);
 }
 
 void __USER_TEXT spi_i2s_send(uint32_t spix, uint16_t data)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	*SPI_DR(spix) = data;
+    *SPI_DR(spix) = data;
 }
 
 void __USER_TEXT spi_i2s_reset(uint32_t spix)
 {
-	/* TODO: assertion */
+    /* TODO: assertion */
 
-	/* TODO: SPI2,SPI3,SPI4,SPI6 */
-	if (spix == SPI1_BASE) {
-		/* SPI1 */
-	} else if (spix == SPI5_BASE) {
-		RCC_APB2PeriphResetCmd(RCC_APB2RSTR_SPI5RST, 1);
-		RCC_APB2PeriphResetCmd(RCC_APB2RSTR_SPI5RST, 0);
-	}
+    /* TODO: SPI2,SPI3,SPI4,SPI6 */
+    if (spix == SPI1_BASE) {
+        /* SPI1 */
+    } else if (spix == SPI5_BASE) {
+        RCC_APB2PeriphResetCmd(RCC_APB2RSTR_SPI5RST, 1);
+        RCC_APB2PeriphResetCmd(RCC_APB2RSTR_SPI5RST, 0);
+    }
 }
 
 uint8_t __USER_TEXT spi_i2s_get_flag(uint32_t spix, uint16_t flag)
 {
-	uint8_t bitstatus = 0;
-	/* TODO: assertion */
+    uint8_t bitstatus = 0;
+    /* TODO: assertion */
 
-	if (((*SPI_SR(spix)) & flag) != (uint16_t)0)
-		bitstatus = 1;
-	else
-		bitstatus = 0;
-	return bitstatus;
+    if (((*SPI_SR(spix)) & flag) != (uint16_t) 0)
+        bitstatus = 1;
+    else
+        bitstatus = 0;
+    return bitstatus;
 }
diff --git a/scripts/list_init_hooks.py b/scripts/list_init_hooks.py
index 36019fd1..35505765 100755
--- a/scripts/list_init_hooks.py
+++ b/scripts/list_init_hooks.py
@@ -25,16 +25,16 @@
 
 # Define in kernel/init_hook.h
 HOOK_LEVEL = OrderedDict([])
-HOOK_LEVEL.update({'INIT_LEVEL_EARLIEST': 1})
-HOOK_LEVEL.update({'INIT_LEVEL_PLATFORM_EARLY': 0x1000})
-HOOK_LEVEL.update({'INIT_LEVEL_PLATFORM': 0x2000})
-HOOK_LEVEL.update({'INIT_LEVEL_KERNEL_EARLY': 0x3000})
-HOOK_LEVEL.update({'INIT_LEVEL_KERNEL': 0x4000})
-HOOK_LEVEL.update({'INIT_LEVEL_LAST': 0xFFFFFFFF})
+HOOK_LEVEL.update({"INIT_LEVEL_EARLIEST": 1})
+HOOK_LEVEL.update({"INIT_LEVEL_PLATFORM_EARLY": 0x1000})
+HOOK_LEVEL.update({"INIT_LEVEL_PLATFORM": 0x2000})
+HOOK_LEVEL.update({"INIT_LEVEL_KERNEL_EARLY": 0x3000})
+HOOK_LEVEL.update({"INIT_LEVEL_KERNEL": 0x4000})
+HOOK_LEVEL.update({"INIT_LEVEL_LAST": 0xFFFFFFFF})
 
 # Dynamiclly adding variable on the fly
 for hook in HOOK_LEVEL:
-    exec('%s = %d' % (hook, HOOK_LEVEL[hook]))
+    exec("%s = %d" % (hook, HOOK_LEVEL[hook]))
 
 
 # ----------------- CLASS --------------------
@@ -48,19 +48,20 @@ def __init__(self, infile=None):
 
         # Parsing .config file
         self.parse_defconfig()
-        self.parse_config('.config', user_config=True)
+        self.parse_config(".config", user_config=True)
 
         # Parsing infile for Makefile
         if infile is not None:
             self.parse_makefile(infile)
 
     def parse_makefile(self, infile):
-        f = map(lambda x: x.strip('\r\n ').replace(' ', ''),
-                open(infile, 'r').readlines())
+        f = map(
+            lambda x: x.strip("\r\n ").replace(" ", ""), open(infile, "r").readlines()
+        )
 
         for i in f:
-            if len(i.split('?=')) == 2:
-                key, value = i.split('?=')
+            if len(i.split("?=")) == 2:
+                key, value = i.split("?=")
 
                 # Hack for ?=, if not set then set.
                 try:
@@ -69,24 +70,23 @@ def parse_makefile(self, infile):
                     self.__setattr__(key, value)
 
     def parse_config(self, path, user_config=False):
-        maps = map(lambda x: x.strip('\r\n '),
-                   open(path, 'r').readlines())
+        maps = map(lambda x: x.strip("\r\n "), open(path, "r").readlines())
 
         for i in maps:
-            if i and i.startswith('#') is False:
-                key, value = i.split('=')
+            if i and i.startswith("#") is False:
+                key, value = i.split("=")
 
                 if user_config:
                     self.__setattr__(key, True)
 
-                    if key.startswith('CONFIG_BOARD_'):
-                        self.__setattr__('BOARD', self.board[key])
+                    if key.startswith("CONFIG_BOARD_"):
+                        self.__setattr__("BOARD", self.board[key])
                 else:
-                    if key.startswith('CONFIG_BOARD_'):
-                        self.board[key] = path.split('/')[1]
+                    if key.startswith("CONFIG_BOARD_"):
+                        self.board[key] = path.split("/")[1]
 
     def parse_defconfig(self):
-        defconfig = glob.glob('board/*/defconfig')
+        defconfig = glob.glob("board/*/defconfig")
         for path in defconfig:
             self.parse_config(path)
 
@@ -94,35 +94,37 @@ def parse_defconfig(self):
 class hook:
 
     def __init__(self, s):
-        self.config = MakefileConfig('Makefile')
-        self.config.parse_makefile('mk/toolchain.mk')
+        self.config = MakefileConfig("Makefile")
+        self.config.parse_makefile("mk/toolchain.mk")
         self.parse(s)
 
     def __str__(self):
         return "%-30s%-30s%-30s%x" % (
-            self.files, self.hook_function, self.hook_level, self.hook_level_int)
+            self.files,
+            self.hook_function,
+            self.hook_level,
+            self.hook_level_int,
+        )
 
     def __lt__(self, other):
         return self.hook_level_int < other.hook_level_int
 
     def parse_from_obj(self, f):
-        path = 'build/%s/%s' % (self.config.BOARD, f.replace('.c', '.o'))
-        s = subprocess.check_output(['%sobjdump' % (self.config.CROSS_COMPILE),
-                                     '-s',
-                                     '-j',
-                                     '.init_hook',
-                                     path]).decode('utf-8')
+        path = "build/%s/%s" % (self.config.BOARD, f.replace(".c", ".o"))
+        s = subprocess.check_output(
+            ["%sobjdump" % (self.config.CROSS_COMPILE), "-s", "-j", ".init_hook", path]
+        ).decode("utf-8")
 
         # Get hook level
-        s = s.split('\n')[4].split(' ')[2]
+        s = s.split("\n")[4].split(" ")[2]
 
         # Convert to hex value
-        ret = int(''.join([s[i:i + 2] for i in range(0, len(s), 2)][::-1]), 16)
+        ret = int("".join([s[i : i + 2] for i in range(0, len(s), 2)][::-1]), 16)
         return ret
 
     def parse(self, s):
-        s = s.replace(' ', '')
-        self.files, hooks = s.split(':')
+        s = s.replace(" ", "")
+        self.files, hooks = s.split(":")
 
         # Regex for splitting function and level
         regex = r"\((.*?),(.*?)\)"
@@ -146,30 +148,30 @@ def print_by_level(hooks):
 
         token = False
         for hook in hooks:
-            if hook.hook_level_int > last_level and \
-                    hook.hook_level_int <= level_int:
+            if hook.hook_level_int > last_level and hook.hook_level_int <= level_int:
                 token = True
                 print(hook)
 
         if token is False:
-            print('--- None ---')
+            print("--- None ---")
 
         last_level = level_int
-        print('')
+        print("")
 
 
-if __name__ == '__main__':
+if __name__ == "__main__":
     # Change to top dir
     abspath = os.path.abspath(sys.path[0])
     dname = os.path.dirname(abspath)
     os.chdir(dname)
 
     # This command search all INIT_HOOK in top dir
-    grep_command = ['grep', '-e', 'INIT_HOOK', '-r', '--include', '*.c']
+    grep_command = ["grep", "-e", "INIT_HOOK", "-r", "--include", "*.c"]
 
     # Get grep output
-    grep_output = filter(lambda x: x, subprocess.check_output(
-        grep_command).decode('utf-8').split('\n'))
+    grep_output = filter(
+        lambda x: x, subprocess.check_output(grep_command).decode("utf-8").split("\n")
+    )
 
     # Process
     ph = parse_hooks(grep_output)
diff --git a/scripts/symmap.py b/scripts/symmap.py
index b87a92d6..1fa780a1 100755
--- a/scripts/symmap.py
+++ b/scripts/symmap.py
@@ -35,19 +35,20 @@ def __init__(self, infile=None):
 
         # Parsing .config file
         self.parse_defconfig()
-        self.parse_config('.config', user_config=True)
+        self.parse_config(".config", user_config=True)
 
         # Parsing infile for Makefile
         if infile is not None:
             self.parse_makefile(infile)
 
     def parse_makefile(self, infile):
-        f = map(lambda x: x.strip('\r\n ').replace(' ', ''),
-                open(infile, 'r').readlines())
+        f = map(
+            lambda x: x.strip("\r\n ").replace(" ", ""), open(infile, "r").readlines()
+        )
 
         for i in f:
-            if len(i.split('?=')) == 2:
-                key, value = i.split('?=')
+            if len(i.split("?=")) == 2:
+                key, value = i.split("?=")
 
                 # Hack for ?=, if not set then set.
                 try:
@@ -56,24 +57,23 @@ def parse_makefile(self, infile):
                     self.__setattr__(key, value)
 
     def parse_config(self, path, user_config=False):
-        maps = map(lambda x: x.strip('\r\n '),
-                   open(path, 'r').readlines())
+        maps = map(lambda x: x.strip("\r\n "), open(path, "r").readlines())
 
         for i in maps:
-            if i and i.startswith('#') is False:
-                key, value = i.split('=')
+            if i and i.startswith("#") is False:
+                key, value = i.split("=")
 
                 if user_config:
                     self.__setattr__(key, True)
 
-                    if key.startswith('CONFIG_BOARD_'):
-                        self.__setattr__('BOARD', self.board[key])
+                    if key.startswith("CONFIG_BOARD_"):
+                        self.__setattr__("BOARD", self.board[key])
                 else:
-                    if key.startswith('CONFIG_BOARD_'):
-                        self.board[key] = path.split('/')[1]
+                    if key.startswith("CONFIG_BOARD_"):
+                        self.board[key] = path.split("/")[1]
 
     def parse_defconfig(self):
-        defconfig = glob.glob('board/*/defconfig')
+        defconfig = glob.glob("board/*/defconfig")
         for path in defconfig:
             self.parse_config(path)
 
@@ -81,21 +81,21 @@ def parse_defconfig(self):
 class Symmap:
     def __init__(self):
         self.symmap = {}
-        self.config = ConfigParser('Makefile')
+        self.config = ConfigParser("Makefile")
         self.parse()
 
     def parse(self):
         try:
-            f = open('build/%s/f9_symmap.c' % (self.config.BOARD)).read()
+            f = open("build/%s/f9_symmap.c" % (self.config.BOARD)).read()
         except FileNotFoundError:
             sys.exit(filenotfound % (self.config.BOARD))
 
         # Regex out address
-        regex = r'{ \(void\*\) \((.*?)\), \d* }'
+        regex = r"{ \(void\*\) \((.*?)\), \d* }"
         address = re.findall(regex, f)
 
         # Regex out name
-        regex = r'\"(.*?)\\0\"'
+        regex = r"\"(.*?)\\0\""
         names = re.findall(regex, f)
 
         # Zip it into dict
@@ -104,12 +104,12 @@ def parse(self):
 
     def print_addr_by_name(self, name):
         if name in self.symmap:
-            print('Symbol : %s\nAddress: 0x%x' % (name, self.symmap[name]))
+            print("Symbol : %s\nAddress: 0x%x" % (name, self.symmap[name]))
         else:
             print('Cannot found "%s" in symmap.' % (name))
 
 
-if __name__ == '__main__':
+if __name__ == "__main__":
     if len(sys.argv) != 2:
         sys.exit(usage)
 
diff --git a/user/apps/l4test/assert.c b/user/apps/l4test/assert.c
index 6dceff07..8566bdb5 100644
--- a/user/apps/l4test/assert.c
+++ b/user/apps/l4test/assert.c
@@ -7,14 +7,13 @@
 #include <l4io.h>
 #include <platform/link.h>
 
-#include "config.h"
 #include "assert.h"
+#include "config.h"
 
-__USER_TEXT void
-__assert(const char *msg, const char *file, int line)
+__USER_TEXT void __assert(const char *msg, const char *file, int line)
 {
-	printf("\n\nassertion failed: %s, line %d in %s\n\n",
-	       msg, (int) line, file);
+    printf("\n\nassertion failed: %s, line %d in %s\n\n", msg, (int) line,
+           file);
 
-	L4_KDB_Enter("assertion failed");
+    L4_KDB_Enter("assertion failed");
 }
diff --git a/user/apps/l4test/assert.h b/user/apps/l4test/assert.h
index 4db91271..e2b3a6e5 100644
--- a/user/apps/l4test/assert.h
+++ b/user/apps/l4test/assert.h
@@ -7,6 +7,6 @@
 #define __ASSERT_H__
 
 extern void __assert(const char *, const char *, int);
-#define assert(EX)  ((EX)?((void)0):__assert(#EX , __FILE__, __LINE__))
+#define assert(EX) ((EX) ? ((void) 0) : __assert(#EX, __FILE__, __LINE__))
 
 #endif /* !__ASSERT_H__ */
diff --git a/user/apps/l4test/ipc.c b/user/apps/l4test/ipc.c
index c1adcd73..ab5b12a4 100644
--- a/user/apps/l4test/ipc.c
+++ b/user/apps/l4test/ipc.c
@@ -4,19 +4,19 @@
  * found in the LICENSE file.
  */
 
-#include <l4/ipc.h>
-#include <l4/space.h>
-#include <l4/thread.h>
 #include <l4/arch.h>
+#include <l4/ipc.h>
 #include <l4/kdebug.h>
 #include <l4/pager.h>
+#include <l4/space.h>
+#include <l4/thread.h>
 #include <l4io.h>
 #include <platform/cortex_m.h>
 
 #include "arch.h"
+#include "assert.h"
 #include "config.h"
 #include "l4test.h"
-#include "assert.h"
 
 __USER_BSS L4_ThreadId_t ipc_t1;
 __USER_BSS L4_ThreadId_t ipc_t2;
@@ -28,49 +28,51 @@ __USER_BSS L4_Word_t ipc_pf_abort_address = 0;
 __USER_TEXT
 L4_Word_t Word(L4_ThreadId_t t)
 {
-	return t.raw;
+    return t.raw;
 }
 
 __USER_TEXT
 const char *ipc_errorcode(L4_Word_t errcode)
 {
-	switch ((errcode >> 1) & 0x7) {
-	case 0:
-		return "ok (0)";
-	case 1:
-		return "timeout";
-	case 2:
-		return "non-existing partner";
-	case 3:
-		return "cancelled";
-	case 4:
-		return "message overflow";
-	case 5:
-		return "xfer timeout (current)";
-	case 6:
-		return "xfer timeout (partner)";
-	case 7:
-		return "aborted";
-	}
-	return "unknown";
+    switch ((errcode >> 1) & 0x7) {
+    case 0:
+        return "ok (0)";
+    case 1:
+        return "timeout";
+    case 2:
+        return "non-existing partner";
+    case 3:
+        return "cancelled";
+    case 4:
+        return "message overflow";
+    case 5:
+        return "xfer timeout (current)";
+    case 6:
+        return "xfer timeout (partner)";
+    case 7:
+        return "aborted";
+    }
+    return "unknown";
 }
 
 __USER_TEXT
 const char *ipc_errorphase(L4_Word_t errcode)
 {
-	return errcode & 0x1 ? "receive-phase" : "send-phase";
+    return errcode & 0x1 ? "receive-phase" : "send-phase";
 }
 
 
 __USER_TEXT
-void setup_ipc_threads(void *(*f1)(void *), void *(*f2)(void *),
-                       bool rcv_same_space, bool snd_same_space,
+void setup_ipc_threads(void *(*f1)(void *),
+                       void *(*f2)(void *),
+                       bool rcv_same_space,
+                       bool snd_same_space,
                        bool xcpu)
 {
-	ipc_t1 = pager_create_thread();
-	ipc_t2 = pager_create_thread();
-	pager_start_thread(ipc_t1, f1, NULL);
-	pager_start_thread(ipc_t2, f2, NULL);
+    ipc_t1 = pager_create_thread();
+    ipc_t2 = pager_create_thread();
+    pager_start_thread(ipc_t1, f1, NULL);
+    pager_start_thread(ipc_t2, f2, NULL);
 }
 
 /*
@@ -79,182 +81,178 @@ void setup_ipc_threads(void *(*f1)(void *), void *(*f2)(void *),
 __USER_TEXT
 static void *simple_ipc_t1_l(void *arg)
 {
-	L4_Msg_t msg;
-	L4_MsgTag_t tag;
-	L4_Word_t i;
-	L4_ThreadId_t tid;
-	L4_ThreadId_t from;
-
-	/* Correct message contents */
-	ipc_ok = true;
-
-	for (L4_Word_t n = 0; n < L4_NumMRs(); n++) {
-		for (L4_Word_t k = 1; k < L4_NumMRs(); k++)
-			L4_LoadMR(k, 0);
-		tag = L4_Receive(ipc_t2);
-		if (!L4_IpcSucceeded(tag)) {
-			printf("Xfer %d words -- IPC failed %s %s\n",
-			       (int) n,
-			       ipc_errorcode(L4_ErrorCode()),
-			       ipc_errorphase(L4_ErrorCode()));
-			ipc_ok = false;
-			break;
-		}
-
-		L4_MsgStore(tag, &msg);
-		if (L4_Label(tag) != 0xf00f) {
-			printf("Xfer %d words -- wrong label: 0x%lx != 0xf00f\n",
-			       (int) n, (long) L4_Label(tag));
-			ipc_ok = false;
-			break;
-		}
-
-		for (i = 1; i <= n; i++) {
-			L4_Word_t val = L4_MsgWord(&msg, i - 1);
-			if (val != i) {
-				printf("Xfer %d words -- wrong value in MR[%d]: "
-				       "0x%lx != 0x%lx\n",
-				       (int) n, (int) i, (long) val, (long) i);
-				ipc_ok = false;
-			}
-			if (!ipc_ok)
-				break;
-		}
-		if (!ipc_ok)
-			break;
-	}
-
-	print_result("Send Message transfer", ipc_ok);
-
-	/* Correct message contents */
-	ipc_ok = true;
-	tag = L4_Call(ipc_t2);
-
-	for (L4_Word_t n = 0; n < L4_NumMRs(); n++) {
-		L4_MsgStore(tag, &msg);
-		if (L4_Label(tag) != 0xf00d) {
-			L4_KDB_Enter("2 label");
-			printf("Xfer %d words -- wrong label: 0x%lx != 0xf00d\n",
-			       (int) n, (long) L4_Label(tag));
-			ipc_ok = false;
-			break;
-		}
-		for (i = 1; i <= n; i++) {
-			L4_Word_t val = L4_MsgWord(&msg, i - 1);
-			if (val != i) {
-				printf("Xfer %d words -- wrong value in MR[%d]: "
-				       "0x%lx != 0x%lx\n",
-				       (int) n, (int) i, (long) val, (long) i);
-				ipc_ok = false;
-				break;
-			}
-			if (!ipc_ok)
-				break;
-
-		}
-
-		if (n == L4_NumMRs() - 1)
-			break;
-
-		for (L4_Word_t k = 1; k < L4_NumMRs(); k++)
-			L4_LoadMR(k, 0);
-		tag = L4_ReplyWait(ipc_t2, &tid);
-
-		if (!L4_IpcSucceeded(tag)) {
-			printf("Xfer %d words -- IPC failed %s %s\n",
-			       (int) n,
-			       ipc_errorcode(L4_ErrorCode()),
-			       ipc_errorphase(L4_ErrorCode()));
-			ipc_ok = false;
-			break;
-		}
-
-	}
-
-	print_result("ReplyWait Message transfer", ipc_ok);
-	/* From parameter - kernel returns global ID */
-	tag = L4_Wait(&from);
-	ipc_ok = true;
-
-	if (from.raw != ipc_t2.raw) {
-		printf("Returned Id %lx != %lx (expected global)\n",
-		       Word(from), Word(ipc_t2));
-		ipc_ok = false;
-	}
-	print_result("From parameter", ipc_ok);
-	L4_Set_MsgTag(L4_Niltag);
-	L4_Send(ipc_t2);
-
-	return NULL;
+    L4_Msg_t msg;
+    L4_MsgTag_t tag;
+    L4_Word_t i;
+    L4_ThreadId_t tid;
+    L4_ThreadId_t from;
+
+    /* Correct message contents */
+    ipc_ok = true;
+
+    for (L4_Word_t n = 0; n < L4_NumMRs(); n++) {
+        for (L4_Word_t k = 1; k < L4_NumMRs(); k++)
+            L4_LoadMR(k, 0);
+        tag = L4_Receive(ipc_t2);
+        if (!L4_IpcSucceeded(tag)) {
+            printf("Xfer %d words -- IPC failed %s %s\n", (int) n,
+                   ipc_errorcode(L4_ErrorCode()),
+                   ipc_errorphase(L4_ErrorCode()));
+            ipc_ok = false;
+            break;
+        }
+
+        L4_MsgStore(tag, &msg);
+        if (L4_Label(tag) != 0xf00f) {
+            printf("Xfer %d words -- wrong label: 0x%lx != 0xf00f\n", (int) n,
+                   (long) L4_Label(tag));
+            ipc_ok = false;
+            break;
+        }
+
+        for (i = 1; i <= n; i++) {
+            L4_Word_t val = L4_MsgWord(&msg, i - 1);
+            if (val != i) {
+                printf(
+                    "Xfer %d words -- wrong value in MR[%d]: "
+                    "0x%lx != 0x%lx\n",
+                    (int) n, (int) i, (long) val, (long) i);
+                ipc_ok = false;
+            }
+            if (!ipc_ok)
+                break;
+        }
+        if (!ipc_ok)
+            break;
+    }
+
+    print_result("Send Message transfer", ipc_ok);
+
+    /* Correct message contents */
+    ipc_ok = true;
+    tag = L4_Call(ipc_t2);
+
+    for (L4_Word_t n = 0; n < L4_NumMRs(); n++) {
+        L4_MsgStore(tag, &msg);
+        if (L4_Label(tag) != 0xf00d) {
+            L4_KDB_Enter("2 label");
+            printf("Xfer %d words -- wrong label: 0x%lx != 0xf00d\n", (int) n,
+                   (long) L4_Label(tag));
+            ipc_ok = false;
+            break;
+        }
+        for (i = 1; i <= n; i++) {
+            L4_Word_t val = L4_MsgWord(&msg, i - 1);
+            if (val != i) {
+                printf(
+                    "Xfer %d words -- wrong value in MR[%d]: "
+                    "0x%lx != 0x%lx\n",
+                    (int) n, (int) i, (long) val, (long) i);
+                ipc_ok = false;
+                break;
+            }
+            if (!ipc_ok)
+                break;
+        }
+
+        if (n == L4_NumMRs() - 1)
+            break;
+
+        for (L4_Word_t k = 1; k < L4_NumMRs(); k++)
+            L4_LoadMR(k, 0);
+        tag = L4_ReplyWait(ipc_t2, &tid);
+
+        if (!L4_IpcSucceeded(tag)) {
+            printf("Xfer %d words -- IPC failed %s %s\n", (int) n,
+                   ipc_errorcode(L4_ErrorCode()),
+                   ipc_errorphase(L4_ErrorCode()));
+            ipc_ok = false;
+            break;
+        }
+    }
+
+    print_result("ReplyWait Message transfer", ipc_ok);
+    /* From parameter - kernel returns global ID */
+    tag = L4_Wait(&from);
+    ipc_ok = true;
+
+    if (from.raw != ipc_t2.raw) {
+        printf("Returned Id %lx != %lx (expected global)\n", Word(from),
+               Word(ipc_t2));
+        ipc_ok = false;
+    }
+    print_result("From parameter", ipc_ok);
+    L4_Set_MsgTag(L4_Niltag);
+    L4_Send(ipc_t2);
+
+    return NULL;
 }
 
 __USER_TEXT
 static void *simple_ipc_t2_l(void *arg)
 {
-	L4_Msg_t msg;
-	L4_ThreadId_t dt;
-	L4_MsgTag_t tag;
-
-	/* Message contents */
-	for (L4_Word_t n = 0; n < L4_NumMRs(); n++) {
-		L4_MsgClear(&msg);
-		L4_Set_Label(&msg.tag, 0xf00f);
-		for (L4_Word_t i = 1; i <= n; i++)
-			L4_MsgAppendWord(&msg, i);
-		L4_MsgLoad(&msg);
-		tag = L4_Send(ipc_t1);
-		if (!L4_IpcSucceeded(tag)) {
-			printf("Xfer %d words -- IPC failed %s %s\n",
-			       (int) n,
-			       ipc_errorcode(L4_ErrorCode()),
-			       ipc_errorphase(L4_ErrorCode()));
-			ipc_ok = false;
-			break;
-		}
-	}
-
-	L4_Receive(ipc_t1);
-
-	/* Message contents */
-	for (L4_Word_t n = 0; n < L4_NumMRs(); n++) {
-		L4_MsgClear(&msg);
-		L4_Set_Label(&msg.tag, 0xf00d);
-		for (L4_Word_t i = 1; i <= n; i++)
-			L4_MsgAppendWord(&msg, i);
-		L4_MsgLoad(&msg);
-		if (n == L4_NumMRs() - 1)
-			tag = L4_Send(ipc_t1);
-		else
-			tag = L4_ReplyWait(ipc_t1, &dt);
-
-		if (!L4_IpcSucceeded(tag)) {
-			printf("Xfer %d words -- IPC failed %s %s\n", (int) n,
-			       ipc_errorcode(L4_ErrorCode()),
-			       ipc_errorphase(L4_ErrorCode()));
-			ipc_ok = false;
-			break;
-		}
-
-	}
-
-	// From parameter test - send final message
-	L4_Set_MsgTag(L4_Niltag);
-	L4_Send(ipc_t1);
-	L4_Receive(ipc_t1);
-
-	printf("\nL4/Pistachio test suite complete\n");
-	return NULL;
+    L4_Msg_t msg;
+    L4_ThreadId_t dt;
+    L4_MsgTag_t tag;
+
+    /* Message contents */
+    for (L4_Word_t n = 0; n < L4_NumMRs(); n++) {
+        L4_MsgClear(&msg);
+        L4_Set_Label(&msg.tag, 0xf00f);
+        for (L4_Word_t i = 1; i <= n; i++)
+            L4_MsgAppendWord(&msg, i);
+        L4_MsgLoad(&msg);
+        tag = L4_Send(ipc_t1);
+        if (!L4_IpcSucceeded(tag)) {
+            printf("Xfer %d words -- IPC failed %s %s\n", (int) n,
+                   ipc_errorcode(L4_ErrorCode()),
+                   ipc_errorphase(L4_ErrorCode()));
+            ipc_ok = false;
+            break;
+        }
+    }
+
+    L4_Receive(ipc_t1);
+
+    /* Message contents */
+    for (L4_Word_t n = 0; n < L4_NumMRs(); n++) {
+        L4_MsgClear(&msg);
+        L4_Set_Label(&msg.tag, 0xf00d);
+        for (L4_Word_t i = 1; i <= n; i++)
+            L4_MsgAppendWord(&msg, i);
+        L4_MsgLoad(&msg);
+        if (n == L4_NumMRs() - 1)
+            tag = L4_Send(ipc_t1);
+        else
+            tag = L4_ReplyWait(ipc_t1, &dt);
+
+        if (!L4_IpcSucceeded(tag)) {
+            printf("Xfer %d words -- IPC failed %s %s\n", (int) n,
+                   ipc_errorcode(L4_ErrorCode()),
+                   ipc_errorphase(L4_ErrorCode()));
+            ipc_ok = false;
+            break;
+        }
+    }
+
+    // From parameter test - send final message
+    L4_Set_MsgTag(L4_Niltag);
+    L4_Send(ipc_t1);
+    L4_Receive(ipc_t1);
+
+    printf("\nL4/Pistachio test suite complete\n");
+    return NULL;
 }
 
 __USER_TEXT
 static void simple_ipc(void)
 {
-	printf("\nSimple IPC test (inter-as, only untyped words)\n");
-	setup_ipc_threads(simple_ipc_t1_l, simple_ipc_t2_l, true, true, false);
+    printf("\nSimple IPC test (inter-as, only untyped words)\n");
+    setup_ipc_threads(simple_ipc_t1_l, simple_ipc_t2_l, true, true, false);
 }
 
 __USER_TEXT
 void all_ipc_tests(void)
 {
-	simple_ipc();
+    simple_ipc();
 }
diff --git a/user/apps/l4test/l4test.h b/user/apps/l4test/l4test.h
index dc0c9297..3c4c1af7 100644
--- a/user/apps/l4test/l4test.h
+++ b/user/apps/l4test/l4test.h
@@ -8,46 +8,46 @@
 #define __L4TEST_H__
 
 /* define this for ANSI menus */
-//#define USE_ANSI 1
+// #define USE_ANSI 1
+#include <l4/kip.h>
 #include <stdbool.h>
 #include "string.h"
-#include <l4/kip.h>
 
 #define ESC "\e["
-#define LIGHT_RED    ESC "31;1m"
-#define LIGHT_GREEN  ESC "32;1m"
-#define LIGHT_BLUE   ESC "34;1m"
-#define BLACK        ESC "0m"
-#define HOME         ESC "0;0H"
-#define CLEAR_LINE   ESC "K"
+#define LIGHT_RED ESC "31;1m"
+#define LIGHT_GREEN ESC "32;1m"
+#define LIGHT_BLUE ESC "34;1m"
+#define BLACK ESC "0m"
+#define HOME ESC "0;0H"
+#define CLEAR_LINE ESC "K"
 #define CLEAR_SCREEN ESC "2J"
 
-#define STR_OK		(LIGHT_GREEN "OK" BLACK)
-#define STR_FAILED	(LIGHT_RED "FAILED" BLACK)
+#define STR_OK (LIGHT_GREEN "OK" BLACK)
+#define STR_FAILED (LIGHT_RED "FAILED" BLACK)
 
 /* memory stuff */
-#define PAGE_MASK   (~(PAGE_SIZE-1))
+#define PAGE_MASK (~(PAGE_SIZE - 1))
 
 #if !defined(NULL)
-#define NULL	0
+#define NULL 0
 #endif
 
 /* ex-reg flags */
-#define EX_HALT (1<<0)
-#define EX_RECV (1<<1)
-#define EX_SEND (1<<2)
-#define EX_SP   (1<<3)
-#define EX_IP   (1<<4)
-#define EX_FLAG (1<<5)
-#define EX_USER (1<<6)
-#define EX_PAGR (1<<7)
+#define EX_HALT (1 << 0)
+#define EX_RECV (1 << 1)
+#define EX_SEND (1 << 2)
+#define EX_SP (1 << 3)
+#define EX_IP (1 << 4)
+#define EX_FLAG (1 << 5)
+#define EX_USER (1 << 6)
+#define EX_PAGR (1 << 7)
 
 /* IPC flags */
-#define IF_PHS (1<<0)  /* phase bit (same as below) */
-#define IF_RCV (1<<0)  /* bit set if in recv phase */
-#define IF_RDR (1<<1)  /* redirected bit */
-#define IF_XPC (1<<2)  /* cross processor bit */
-#define IF_ERR (1<<3)  /* error bit */
+#define IF_PHS (1 << 0) /* phase bit (same as below) */
+#define IF_RCV (1 << 0) /* bit set if in recv phase */
+#define IF_RDR (1 << 1) /* redirected bit */
+#define IF_XPC (1 << 2) /* cross processor bit */
+#define IF_ERR (1 << 3) /* error bit */
 
 #define IPC_ERROR(tag) ((tag.X.flags & IF_ERR) == IF_ERR)
 
@@ -56,7 +56,7 @@ const char *ipc_errorphase(L4_Word_t errcode);
 
 
 /* testing macros */
-#define SET_MSG( msg, tst, ok, err) (msg = ((tst) ? ok : err))
+#define SET_MSG(msg, tst, ok, err) (msg = ((tst) ? ok : err))
 
 /* globals */
 extern void *next_touch;
@@ -75,33 +75,37 @@ void *get_pages(L4_Word_t count, int touch);
 void *get_new_page(void);
 
 /* do useful stuff */
-L4_Word_t safe_mem_touch( void *addr );
-void start_thread_ip_sp( L4_ThreadId_t tid, L4_Word_t ip, L4_Word_t sp );
+L4_Word_t safe_mem_touch(void *addr);
+void start_thread_ip_sp(L4_ThreadId_t tid, L4_Word_t ip, L4_Word_t sp);
 
 /* Thread/address space management */
-L4_ThreadId_t get_new_tid (void);
-L4_ThreadId_t create_thread (void (*func)(void), bool new_space,
-		int cpu, L4_Word_t spacectrl);
-L4_Word_t kill_thread (L4_ThreadId_t tid);
-void start_thread (L4_ThreadId_t tid, void (*func)(void));
+L4_ThreadId_t get_new_tid(void);
+L4_ThreadId_t create_thread(void (*func)(void),
+                            bool new_space,
+                            int cpu,
+                            L4_Word_t spacectrl);
+L4_Word_t kill_thread(L4_ThreadId_t tid);
+void start_thread(L4_ThreadId_t tid, void (*func)(void));
 
 
 /* architecture helper functions */
-void get_startup_values (void (*func)(void), L4_Word_t * ip, L4_Word_t * sp,
-		L4_Word_t * stack_size);
-void *code_addr( void *addr );
-void setup_exreg( L4_Word_t *ip, L4_Word_t *sp, void (*func)(void) );
+void get_startup_values(void (*func)(void),
+                        L4_Word_t *ip,
+                        L4_Word_t *sp,
+                        L4_Word_t *stack_size);
+void *code_addr(void *addr);
+void setup_exreg(L4_Word_t *ip, L4_Word_t *sp, void (*func)(void));
 
 
-L4_INLINE bool l4_has_feature( const char *feature_name )
+L4_INLINE bool l4_has_feature(const char *feature_name)
 {
-	void *kip = L4_GetKernelInterface();
-	char *name;
+    void *kip = L4_GetKernelInterface();
+    char *name;
 
-	for (L4_Word_t i = 0; (name = L4_Feature(kip,i)); i++)
-		if (!strcmp(feature_name, name))
-			return true;
-	return false;
+    for (L4_Word_t i = 0; (name = L4_Feature(kip, i)); i++)
+        if (!strcmp(feature_name, name))
+            return true;
+    return false;
 }
 
 #endif /* !__L4TEST_H__ */
diff --git a/user/apps/l4test/main.c b/user/apps/l4test/main.c
index fb15ccc0..5de9303a 100644
--- a/user/apps/l4test/main.c
+++ b/user/apps/l4test/main.c
@@ -4,21 +4,21 @@
  * found in the LICENSE file.
  */
 
-#include <user_runtime.h>
-#include <l4/kip.h>
-#include <l4/thread.h>
 #include <l4/ipc.h>
 #include <l4/kdebug.h>
+#include <l4/kip.h>
+#include <l4/thread.h>
 #include <l4io.h>
+#include <user_runtime.h>
 
 /* for the current arch */
-#include "platform/arch.h"
 #include <platform/cortex_m.h>
+#include "platform/arch.h"
 
 /* generic stuff */
+#include "assert.h"
 #include "config.h"
 #include "l4test.h"
-#include "assert.h"
 
 #define STACK_SIZE 512
 
@@ -26,140 +26,130 @@
 __USER_BSS static char *free_page;
 
 /* colours */
-static void
-set_colour(const char *col)
+static void set_colour(const char *col)
 {
 #ifdef USE_ANSI
-	printf("%s", col);
+    printf("%s", col);
 #endif
 }
 
-void
-print_uline(const char *msg, char c)
+void print_uline(const char *msg, char c)
 {
-	int i, len = strlen(msg);
+    int i, len = strlen(msg);
 
-	printf("%s\n", msg);
+    printf("%s\n", msg);
 
-	for (i = 0; i < len; i++)
-		putc(c);
-	putc('\n');
+    for (i = 0; i < len; i++)
+        putc(c);
+    putc('\n');
 }
 
-void
-print_h1(const char *msg)
+void print_h1(const char *msg)
 {
-	set_colour(LIGHT_BLUE);
-	print_uline(msg, '=');
-	set_colour(BLACK);
+    set_colour(LIGHT_BLUE);
+    print_uline(msg, '=');
+    set_colour(BLACK);
 }
 
-void
-print_h2(const char *msg)
+void print_h2(const char *msg)
 {
-	set_colour(LIGHT_RED);
-	print_uline(msg, '-');
-	set_colour(BLACK);
+    set_colour(LIGHT_RED);
+    print_uline(msg, '-');
+    set_colour(BLACK);
 }
 
-__USER_TEXT void
-print_result(const char *str, bool test)
+__USER_TEXT void print_result(const char *str, bool test)
 {
-	printf("  %s: ", str);
-	printf("  %s\n", (test) ? STR_OK : STR_FAILED);
-	if (! test)
-		L4_KDB_Enter("test failed");
+    printf("  %s: ", str);
+    printf("  %s\n", (test) ? STR_OK : STR_FAILED);
+    if (!test)
+        L4_KDB_Enter("test failed");
 }
 
-__USER_TEXT L4_Word_t
-safe_mem_touch(void *addr)
+__USER_TEXT L4_Word_t safe_mem_touch(void *addr)
 {
-	volatile L4_Word_t *ptr;
-	L4_Word_t copy;
+    volatile L4_Word_t *ptr;
+    L4_Word_t copy;
 
-	ptr = (L4_Word_t *) addr;
-	copy = *ptr;
-	*ptr = copy;
+    ptr = (L4_Word_t *) addr;
+    copy = *ptr;
+    *ptr = copy;
 
-	return copy;
+    return copy;
 }
 
-__USER_TEXT void *
-get_pages(L4_Word_t count, int touch)
+__USER_TEXT void *get_pages(L4_Word_t count, int touch)
 {
-	void *ret = free_page;
+    void *ret = free_page;
 
-	free_page += count * PAGE_SIZE;
+    free_page += count * PAGE_SIZE;
 
-	/* should we fault the pages in? */
-	if (touch != 0) {
-		char *addr = (char *) ret;
-		L4_Word_t i;
+    /* should we fault the pages in? */
+    if (touch != 0) {
+        char *addr = (char *) ret;
+        L4_Word_t i;
 
-		/* touch each page */
-		for (i = 0; i < count; i++) {
-			safe_mem_touch((void *) addr);
-			for (int j = 0; j < PAGE_SIZE; j++)
-				addr[j] = 0;
-			addr += PAGE_SIZE;
-		}
-	}
+        /* touch each page */
+        for (i = 0; i < count; i++) {
+            safe_mem_touch((void *) addr);
+            for (int j = 0; j < PAGE_SIZE; j++)
+                addr[j] = 0;
+            addr += PAGE_SIZE;
+        }
+    }
 
-	return (void *) ret;
+    return (void *) ret;
 }
 
-__USER_TEXT void *
-get_new_page(void)
+__USER_TEXT void *get_new_page(void)
 {
-	return get_pages(1, 0);
+    return get_pages(1, 0);
 }
 
-__USER_TEXT void
-get_startup_values(void (*func)(void),
-                   L4_Word_t *ip, L4_Word_t *sp,
-                   L4_Word_t *stack_size)
+__USER_TEXT void get_startup_values(void (*func)(void),
+                                    L4_Word_t *ip,
+                                    L4_Word_t *sp,
+                                    L4_Word_t *stack_size)
 {
-	/* Calculate intial SP */
-	L4_Word_t stack = (L4_Word_t) get_pages(STACK_PAGES, 1);
-	stack += STACK_PAGES * PAGE_SIZE;
+    /* Calculate intial SP */
+    L4_Word_t stack = (L4_Word_t) get_pages(STACK_PAGES, 1);
+    stack += STACK_PAGES * PAGE_SIZE;
 
-	*ip = (L4_Word_t) func;
-	*sp = stack;
-	*stack_size = STACK_PAGES * PAGE_SIZE;
+    *ip = (L4_Word_t) func;
+    *sp = stack;
+    *stack_size = STACK_PAGES * PAGE_SIZE;
 }
 
-void
-start_thread_ip_sp(L4_ThreadId_t tid, L4_Word_t ip, L4_Word_t sp)
+void start_thread_ip_sp(L4_ThreadId_t tid, L4_Word_t ip, L4_Word_t sp)
 {
-	L4_Msg_t msg;
+    L4_Msg_t msg;
 
-	L4_MsgClear(&msg);
-	L4_MsgAppendWord(&msg, ip);
-	L4_MsgAppendWord(&msg, sp);
-	L4_MsgLoad(&msg);
+    L4_MsgClear(&msg);
+    L4_MsgAppendWord(&msg, ip);
+    L4_MsgAppendWord(&msg, sp);
+    L4_MsgLoad(&msg);
 
-	L4_Send(tid);
+    L4_Send(tid);
 }
 
-void
-msec_sleep(L4_Word_t msec)
+void msec_sleep(L4_Word_t msec)
 {
-	L4_Sleep(L4_TimePeriod(msec * 1000));
+    L4_Sleep(L4_TimePeriod(msec * 1000));
 }
 
 __USER_TEXT void all_tests(void)
 {
-	extern void all_ipc_tests(void);
+    extern void all_ipc_tests(void);
 
-	all_ipc_tests();
+    all_ipc_tests();
 }
 
 __USER_TEXT
 static void *main(void *user)
 {
-	printf("\nL4/Pistachio test suite starts\n");
-	all_tests();
-	return NULL;
+    printf("\nL4/Pistachio test suite starts\n");
+    all_tests();
+    return NULL;
 }
 
 /* RES_FPAGE needs enough space for aligned thread nodes.
@@ -168,10 +158,7 @@ static void *main(void *user)
  * Use power-of-2 size (4096) to fit in a single MPU region.
  * With 768-byte stride, 4096 bytes supports 5 nodes (indices 1-5).
  */
-DECLARE_USER(
-	256,
-	l4test,
-	main,
-	DECLARE_FPAGE(0x0, 4096)
-	DECLARE_FPAGE(0x0, 512)
-);
+DECLARE_USER(256,
+             l4test,
+             main,
+             DECLARE_FPAGE(0x0, 4096) DECLARE_FPAGE(0x0, 512));
diff --git a/user/apps/l4test/platform/arch.h b/user/apps/l4test/platform/arch.h
index 8af55294..82418194 100644
--- a/user/apps/l4test/platform/arch.h
+++ b/user/apps/l4test/platform/arch.h
@@ -6,12 +6,12 @@
 #ifndef __USER_PLATFORM_ARCH_H__
 #define __USER_PLATFORM_ARCH_H__
 
-#define ARCH_NAME               "ARM-CM4"
+#define ARCH_NAME "ARM-CM4"
 
-#define PAGE_BITS		(8)
-#define PAGE_SIZE		(1 << PAGE_BITS)
-#define MAX_MEM			(4L*256L)
+#define PAGE_BITS (8)
+#define PAGE_SIZE (1 << PAGE_BITS)
+#define MAX_MEM (4L * 256L)
 
-#define STACK_PAGES             1
+#define STACK_PAGES 1
 
 #endif /* __USER_PLATFORM_ARCH_H__ */
diff --git a/user/apps/l4test/string.c b/user/apps/l4test/string.c
index 0167882a..e85797fc 100644
--- a/user/apps/l4test/string.c
+++ b/user/apps/l4test/string.c
@@ -6,59 +6,58 @@
 #include "string.h"
 #include <platform/link.h>
 
-int __USER_TEXT
-strlen(const char *str)
+int __USER_TEXT strlen(const char *str)
 {
-	int len = 0;
-	while (*str != '\0')
-		str++, len++;
+    int len = 0;
+    while (*str != '\0')
+        str++, len++;
 
-	return len;
+    return len;
 }
 
 int strcmp(const char *str1, const char *str2)
 {
-	while (*str1 && *str2) {
-		if (*str1 < *str2)
-			return -1;
-		if (*str1 > *str2)
-			return 1;
-		str1++;
-		str2++;
-	}
-	if (*str2)
-		return -1;
-	if (*str1)
-		return 1;
-	return 0;
+    while (*str1 && *str2) {
+        if (*str1 < *str2)
+            return -1;
+        if (*str1 > *str2)
+            return 1;
+        str1++;
+        str2++;
+    }
+    if (*str2)
+        return -1;
+    if (*str1)
+        return 1;
+    return 0;
 }
 
 int strcmp_of(const char *str_of, const char *search)
 {
-	while (*str_of && *search) {
-		if ((*str_of == '@') && (*search == '/')) {
-			while (*str_of && (*str_of != '/'))
-				str_of++;
-			if (!*str_of)
-				return -1;
-		}
-		if (*str_of < *search)
-			return -1;
-		if (*str_of > *search)
-			return 1;
-		str_of++;
-		search++;
-	}
-
-	if (*search)
-		return -1;
-
-	if (*str_of == '@')
-		while (*str_of && (*str_of != '/'))
-			str_of++;
-
-	if (*str_of)
-		return 1;
-
-	return 0;
+    while (*str_of && *search) {
+        if ((*str_of == '@') && (*search == '/')) {
+            while (*str_of && (*str_of != '/'))
+                str_of++;
+            if (!*str_of)
+                return -1;
+        }
+        if (*str_of < *search)
+            return -1;
+        if (*str_of > *search)
+            return 1;
+        str_of++;
+        search++;
+    }
+
+    if (*search)
+        return -1;
+
+    if (*str_of == '@')
+        while (*str_of && (*str_of != '/'))
+            str_of++;
+
+    if (*str_of)
+        return 1;
+
+    return 0;
 }
diff --git a/user/apps/l4test/string.h b/user/apps/l4test/string.h
index 88a91955..dc010258 100644
--- a/user/apps/l4test/string.h
+++ b/user/apps/l4test/string.h
@@ -8,10 +8,10 @@
 
 #include <l4/types.h>
 
-extern void hex( L4_Word_t num, char str[] );
-extern int strlen( const char *src );
-extern void strcpy( char *dst, const char *src );
-extern int strcmp( const char *str1, const char *str2 );
-extern int strcmp_of( const char *str_of, const char *search );
+extern void hex(L4_Word_t num, char str[]);
+extern int strlen(const char *src);
+extern void strcpy(char *dst, const char *src);
+extern int strcmp(const char *str1, const char *str2);
+extern int strcmp_of(const char *str_of, const char *search);
 
-#endif	/* __PIGGYBACKER__INCLUDE__STRING_H__ */
+#endif /* __PIGGYBACKER__INCLUDE__STRING_H__ */
diff --git a/user/apps/lcd_test/main.c b/user/apps/lcd_test/main.c
index 316a8c85..fe69ba0a 100644
--- a/user/apps/lcd_test/main.c
+++ b/user/apps/lcd_test/main.c
@@ -3,12 +3,12 @@
  * found in the LICENSE file.
  */
 
-#include <platform/link.h>
-#include <user_runtime.h>
 #include <l4/ipc.h>
-#include <l4/utcb.h>
 #include <l4/pager.h>
+#include <l4/utcb.h>
 #include <l4io.h>
+#include <platform/link.h>
+#include <user_runtime.h>
 #include INC_PLAT(lcd.h)
 #include INC_PLAT(ltdc.h)
 
@@ -16,39 +16,35 @@
 __USER_TEXT
 static void *main(void *arg)
 {
+    printf("lcd main\n");
+    /* testing lcd */
+    lcd_init();
+    lcd_layer_init();
+    ltdc_layer_cmd(LTDC_Layer1, 1);
+    ltdc_layer_cmd(LTDC_Layer2, 1);
+    ltdc_reload_config(LTDC_IMReload);
+    ltdc_cmd(1);
+    lcd_set_layer(LCD_FOREGROUND_LAYER);
+    lcd_clear(LCD_COLOR_WHITE);
 
-	printf("lcd main\n");
-	/* testing lcd */
-	lcd_init();
-	lcd_layer_init();
-	ltdc_layer_cmd(LTDC_Layer1, 1);
-	ltdc_layer_cmd(LTDC_Layer2, 1);
-	ltdc_reload_config(LTDC_IMReload);
-	ltdc_cmd(1);
-	lcd_set_layer(LCD_FOREGROUND_LAYER);
-	lcd_clear(LCD_COLOR_WHITE);
-	
-	lcd_set_back_color(0xCE79);
-	lcd_set_text_color(LCD_COLOR_BLACK);
-	lcd_draw_rect(20, 30, 20, 40);
+    lcd_set_back_color(0xCE79);
+    lcd_set_text_color(LCD_COLOR_BLACK);
+    lcd_draw_rect(20, 30, 20, 40);
 
-	while (1)
-		L4_Sleep(L4_Never);
+    while (1)
+        L4_Sleep(L4_Never);
 }
 
-DECLARE_USER(
-	4,
-	lcd_test,
-	main,
-	DECLARE_FPAGE(0x0, 2 * (UTCB_SIZE + STACK_SIZE))
-	DECLARE_FPAGE(0x0, 512)
-	DECLARE_FPAGE(0x40005000, 0x1000)
-	DECLARE_FPAGE(0x40015000, 0x0c00)
-	DECLARE_FPAGE(0x40020000, 0x3c00)
-	DECLARE_FPAGE(0x40028000, 0x8000)
-	DECLARE_FPAGE(0x42470000, 0x0c00)
-	DECLARE_FPAGE(0x40016800, 0x0c00)
-	DECLARE_FPAGE(0xA0000000, 0x1000)
-	DECLARE_FPAGE(0xD0000000, 0xA0000)
-	DECLARE_FPAGE(0xD00A0000, 0xA0000)
-);
+DECLARE_USER(4,
+             lcd_test,
+             main,
+             DECLARE_FPAGE(0x0, 2 * (UTCB_SIZE + STACK_SIZE))
+                 DECLARE_FPAGE(0x0, 512) DECLARE_FPAGE(0x40005000, 0x1000)
+                     DECLARE_FPAGE(0x40015000, 0x0c00) DECLARE_FPAGE(0x40020000,
+                                                                     0x3c00)
+                         DECLARE_FPAGE(0x40028000,
+                                       0x8000) DECLARE_FPAGE(0x42470000, 0x0c00)
+                             DECLARE_FPAGE(0x40016800, 0x0c00)
+                                 DECLARE_FPAGE(0xA0000000, 0x1000)
+                                     DECLARE_FPAGE(0xD0000000, 0xA0000)
+                                         DECLARE_FPAGE(0xD00A0000, 0xA0000));
diff --git a/user/apps/pingpong/main.c b/user/apps/pingpong/main.c
index c1e19180..776fee1b 100644
--- a/user/apps/pingpong/main.c
+++ b/user/apps/pingpong/main.c
@@ -3,13 +3,13 @@
  * found in the LICENSE file.
  */
 
-#include <platform/link.h>
-#include <user_runtime.h>
 #include <l4/ipc.h>
-#include <l4/utcb.h>
 #include <l4/pager.h>
 #include <l4/thread.h>
+#include <l4/utcb.h>
 #include <l4io.h>
+#include <platform/link.h>
+#include <user_runtime.h>
 
 #define STACK_SIZE 512
 
@@ -20,61 +20,57 @@ static L4_ThreadId_t threads[2] __USER_DATA;
 __USER_TEXT
 void *ping_thread(void *arg)
 {
-	L4_Msg_t msg;
-	L4_MsgTag_t tag;
+    L4_Msg_t msg;
+    L4_MsgTag_t tag;
 
-	L4_MsgClear(&msg);
-	L4_MsgLoad(&msg);
+    L4_MsgClear(&msg);
+    L4_MsgLoad(&msg);
 
-	while (1) {
-		tag = L4_Send_Timeout(threads[PONG_THREAD],
-		                      L4_TimePeriod(1000 * 1000));
+    while (1) {
+        tag = L4_Send_Timeout(threads[PONG_THREAD], L4_TimePeriod(1000 * 1000));
 
-		if (!L4_IpcSucceeded(tag)) {
-			printf("%p: send ipc fails\n", L4_MyGlobalId());
-			printf("%p: ErrorCode = 0x%x\n", L4_MyGlobalId(), L4_ErrorCode());
-		}
-	}
+        if (!L4_IpcSucceeded(tag)) {
+            printf("%p: send ipc fails\n", L4_MyGlobalId());
+            printf("%p: ErrorCode = 0x%x\n", L4_MyGlobalId(), L4_ErrorCode());
+        }
+    }
 }
 
 __USER_TEXT
 void *pong_thread(void *arg)
 {
-	L4_MsgTag_t tag;
-	L4_Msg_t msg;
+    L4_MsgTag_t tag;
+    L4_Msg_t msg;
 
-	while (1) {
-		tag = L4_Receive_Timeout(threads[PING_THREAD],
-		                         L4_TimePeriod(1000 * 1000));
-		L4_MsgStore(tag, &msg);
+    while (1) {
+        tag = L4_Receive_Timeout(threads[PING_THREAD],
+                                 L4_TimePeriod(1000 * 1000));
+        L4_MsgStore(tag, &msg);
 
-		if (!L4_IpcSucceeded(tag)) {
-			printf("%p: recv ipc fails\n", L4_MyGlobalId());
-			printf("%p: ErrorCode = 0x%x\n", L4_MyGlobalId(), L4_ErrorCode());
-		}
-		/* FIXME: workaround solution to avoid scheduler starvation */
-		L4_Sleep(L4_TimePeriod(500 * 1000));
-	}
+        if (!L4_IpcSucceeded(tag)) {
+            printf("%p: recv ipc fails\n", L4_MyGlobalId());
+            printf("%p: ErrorCode = 0x%x\n", L4_MyGlobalId(), L4_ErrorCode());
+        }
+        /* FIXME: workaround solution to avoid scheduler starvation */
+        L4_Sleep(L4_TimePeriod(500 * 1000));
+    }
 }
 
 __USER_TEXT
 static void *main(void *user)
 {
-	threads[PING_THREAD] = pager_create_thread();
-	threads[PONG_THREAD] = pager_create_thread();
-	pager_start_thread(threads[PING_THREAD], ping_thread, NULL);
-	pager_start_thread(threads[PONG_THREAD], pong_thread, NULL);
-	return 0;
+    threads[PING_THREAD] = pager_create_thread();
+    threads[PONG_THREAD] = pager_create_thread();
+    pager_start_thread(threads[PING_THREAD], ping_thread, NULL);
+    pager_start_thread(threads[PONG_THREAD], pong_thread, NULL);
+    return 0;
 }
 
 /* RES_FPAGE needs space for: pager + main + PING + PONG = 4 threads
  * Each thread needs NODE_SIZE_ALIGNED (768 bytes).
  * Use power-of-2 size (4096) to fit in single MPU region.
  */
-DECLARE_USER(
-	0,
-	pingpong,
-	main,
-	DECLARE_FPAGE(0x0, 4096)
-	DECLARE_FPAGE(0x0, 512)
-);
+DECLARE_USER(0,
+             pingpong,
+             main,
+             DECLARE_FPAGE(0x0, 4096) DECLARE_FPAGE(0x0, 512));
diff --git a/user/apps/tests/main.c b/user/apps/tests/main.c
index 8d13a111..8af10044 100644
--- a/user/apps/tests/main.c
+++ b/user/apps/tests/main.c
@@ -3,10 +3,10 @@
  * found in the LICENSE file.
  */
 
-#include <user_runtime.h>
-#include <l4/thread.h>
 #include <l4/ipc.h>
+#include <l4/thread.h>
 #include <l4io.h>
+#include <user_runtime.h>
 
 #include "tests.h"
 
@@ -20,53 +20,53 @@ __USER_BSS test_context_t test_ctx;
 __USER_TEXT
 static void run_all_tests(void)
 {
-	test_ctx.passed = 0;
-	test_ctx.failed = 0;
-
-	TEST_START("test_suite");
-
-	/* Thread identity tests (no thread creation needed) */
-	test_thread_self();
-	test_thread_global_id();
-	test_thread_pager();
-
-	/* Timer tests */
-	test_timer_period();
-	test_timer_sleep();
-
-	/* KIP tests */
-	test_kip_access();
-	test_kip_processors();
-
-	/* IPC tests (also validates thread creation via pager) */
-	test_ipc_basic();
-	/* TODO: test_ipc_multiword() has timing issues, needs debugging */
-
-	/* Functional safety tests */
-	test_ipc_timeout_send();
-	test_ipc_timeout_receive();
-	test_timer_zero_sleep();
-	test_timer_monotonicity();
-	test_thread_priority();
-	test_thread_yield();
-
-	/* Scheduler validation tests (based on formal invariants) */
-	test_sched_syscall();
-	test_sched_yield_returns();
-	test_sched_idle_fallback();
-	test_sched_round_robin();
-	test_sched_no_starvation();
-	test_sched_ipc_priority_boost();
-	/* Note: test_sched_priority_order() requires more thread resources */
+    test_ctx.passed = 0;
+    test_ctx.failed = 0;
+
+    TEST_START("test_suite");
+
+    /* Thread identity tests (no thread creation needed) */
+    test_thread_self();
+    test_thread_global_id();
+    test_thread_pager();
+
+    /* Timer tests */
+    test_timer_period();
+    test_timer_sleep();
+
+    /* KIP tests */
+    test_kip_access();
+    test_kip_processors();
+
+    /* IPC tests (also validates thread creation via pager) */
+    test_ipc_basic();
+    /* TODO: test_ipc_multiword() has timing issues, needs debugging */
+
+    /* Functional safety tests */
+    test_ipc_timeout_send();
+    test_ipc_timeout_receive();
+    test_timer_zero_sleep();
+    test_timer_monotonicity();
+    test_thread_priority();
+    test_thread_yield();
+
+    /* Scheduler validation tests (based on formal invariants) */
+    test_sched_syscall();
+    test_sched_yield_returns();
+    test_sched_idle_fallback();
+    test_sched_round_robin();
+    test_sched_no_starvation();
+    test_sched_ipc_priority_boost();
+    /* Note: test_sched_priority_order() requires more thread resources */
 
 #ifdef CONFIG_EXTI_INTERRUPT_TEST
-	/* IRQ test (requires hardware EXTI support) */
-	test_irq_exti();
+    /* IRQ test (requires hardware EXTI support) */
+    test_irq_exti();
 #endif
 
-	/* Summary and exit */
-	TEST_SUMMARY();
-	TEST_EXIT(test_ctx.failed > 0 ? 1 : 0);
+    /* Summary and exit */
+    TEST_SUMMARY();
+    TEST_EXIT(test_ctx.failed > 0 ? 1 : 0);
 }
 #endif /* !FAULT_TYPE */
 
@@ -77,17 +77,17 @@ static void run_all_tests(void)
 __USER_TEXT
 static void *test_main(void *user)
 {
-	printf("\nF9 Microkernel Tests\n");
+    printf("\nF9 Microkernel Tests\n");
 
 #ifdef FAULT_TYPE
-	/* Run fault test (does not return - triggers kernel panic) */
-	run_fault_test();
+    /* Run fault test (does not return - triggers kernel panic) */
+    run_fault_test();
 #else
-	/* Run test suite */
-	run_all_tests();
+    /* Run test suite */
+    run_all_tests();
 #endif
 
-	return NULL;
+    return NULL;
 }
 
 /*
@@ -102,21 +102,16 @@ static void *test_main(void *user)
  *   Smaller stack to make overflow easier to trigger
  */
 #if defined(FAULT_TYPE) && (FAULT_TYPE == FAULT_CANARY)
-/* Smaller stack for canary test (must match STACK_SIZE_WORDS in test-fault.c) */
-DECLARE_USER(
-	257,
-	tests,
-	test_main,
-	DECLARE_FPAGE(0x0, 2048)
-	DECLARE_FPAGE(0x0, 512)
-);
+/* Smaller stack for canary test (must match STACK_SIZE_WORDS in test-fault.c)
+ */
+DECLARE_USER(257,
+             tests,
+             test_main,
+             DECLARE_FPAGE(0x0, 2048) DECLARE_FPAGE(0x0, 512));
 #else
 /* Normal stack for test suite and MPU fault test */
-DECLARE_USER(
-	257,
-	tests,
-	test_main,
-	DECLARE_FPAGE(0x0, 8192)
-	DECLARE_FPAGE(0x0, 512)
-);
+DECLARE_USER(257,
+             tests,
+             test_main,
+             DECLARE_FPAGE(0x0, 8192) DECLARE_FPAGE(0x0, 512));
 #endif
diff --git a/user/apps/tests/test-fault.c b/user/apps/tests/test-fault.c
index 47de5c14..84474698 100644
--- a/user/apps/tests/test-fault.c
+++ b/user/apps/tests/test-fault.c
@@ -13,14 +13,13 @@
  * FAULT_TYPE=2 (canary): Stack overflow corrupts canary, triggers panic
  */
 
-#include <user_runtime.h>
 #include <l4/thread.h>
 #include <l4io.h>
+#include <user_runtime.h>
 #include "tests.h"
 
 /* Marker for expected fault - parsed by qemu-test.py */
-#define FAULT_EXPECT(name) \
-	printf("[FAULT:EXPECT] %s\n", name)
+#define FAULT_EXPECT(name) printf("[FAULT:EXPECT] %s\n", name)
 
 #if FAULT_TYPE == FAULT_MPU
 /*
@@ -37,8 +36,8 @@
 __USER_TEXT
 static void dummy_code_function(void)
 {
-	/* This function exists only to have a code address to write to */
-	__asm__ volatile ("nop");
+    /* This function exists only to have a code address to write to */
+    __asm__ volatile("nop");
 }
 
 /*
@@ -48,36 +47,36 @@ static void dummy_code_function(void)
 __USER_TEXT
 static void trigger_mpu_fault(void)
 {
-	volatile uint32_t *code_ptr;
+    volatile uint32_t *code_ptr;
 
-	/* Get address of code function */
-	code_ptr = (volatile uint32_t *)(uintptr_t)dummy_code_function;
+    /* Get address of code function */
+    code_ptr = (volatile uint32_t *) (uintptr_t) dummy_code_function;
 
-	printf("Attempting write to code at %p...\n", (void *)code_ptr);
+    printf("Attempting write to code at %p...\n", (void *) code_ptr);
 
-	/* This write should trigger MPU DACCVIOL (data access violation) */
-	*code_ptr = 0xDEADC0DE;
+    /* This write should trigger MPU DACCVIOL (data access violation) */
+    *code_ptr = 0xDEADC0DE;
 
-	/* If we get here, MPU is not protecting code - test fails */
-	printf("[FAULT:UNEXPECTED] No fault occurred - MPU not protecting code!\n");
+    /* If we get here, MPU is not protecting code - test fails */
+    printf("[FAULT:UNEXPECTED] No fault occurred - MPU not protecting code!\n");
 }
 
 __USER_TEXT
 void run_fault_test(void)
 {
-	printf("\n=== MPU Fault Test ===\n");
+    printf("\n=== MPU Fault Test ===\n");
 
-	/* Signal expected fault type */
-	FAULT_EXPECT("mpu_write_to_code");
+    /* Signal expected fault type */
+    FAULT_EXPECT("mpu_write_to_code");
 
-	/* Small delay to ensure output is flushed */
-	L4_Sleep(L4_TimePeriod(10000));
+    /* Small delay to ensure output is flushed */
+    L4_Sleep(L4_TimePeriod(10000));
 
-	/* Trigger the fault - should not return */
-	trigger_mpu_fault();
+    /* Trigger the fault - should not return */
+    trigger_mpu_fault();
 
-	/* Should never reach here */
-	printf("[FAULT:ERROR] Test did not trigger expected fault\n");
+    /* Should never reach here */
+    printf("[FAULT:ERROR] Test did not trigger expected fault\n");
 }
 
 #elif FAULT_TYPE == FAULT_CANARY
@@ -101,33 +100,32 @@ __USER_BSS static volatile int recursion_depth;
 #pragma GCC diagnostic push
 #pragma GCC diagnostic ignored "-Winfinite-recursion"
 __USER_TEXT
-__attribute__((noinline))
-static void stack_consumer(void)
+__attribute__((noinline)) static void stack_consumer(void)
 {
-	/* Local array to consume stack space */
-	volatile char buffer[64];
-	volatile char sum = 0;
-	int i;
-
-	/* Touch the buffer to prevent optimization */
-	for (i = 0; i < 64; i++) {
-		buffer[i] = (char)recursion_depth;
-		sum += buffer[i];  /* Read buffer to satisfy compiler */
-	}
-	(void)sum;  /* Prevent unused warning */
-
-	recursion_depth++;
-
-	/* Print progress every 10 levels */
-	if ((recursion_depth % 10) == 0) {
-		printf("Recursion depth: %d\n", recursion_depth);
-	}
-
-	/* Recurse deeper - this will eventually overflow */
-	stack_consumer();
-
-	/* Should never reach here due to stack overflow */
-	printf("Returned from depth %d\n", recursion_depth);
+    /* Local array to consume stack space */
+    volatile char buffer[64];
+    volatile char sum = 0;
+    int i;
+
+    /* Touch the buffer to prevent optimization */
+    for (i = 0; i < 64; i++) {
+        buffer[i] = (char) recursion_depth;
+        sum += buffer[i]; /* Read buffer to satisfy compiler */
+    }
+    (void) sum; /* Prevent unused warning */
+
+    recursion_depth++;
+
+    /* Print progress every 10 levels */
+    if ((recursion_depth % 10) == 0) {
+        printf("Recursion depth: %d\n", recursion_depth);
+    }
+
+    /* Recurse deeper - this will eventually overflow */
+    stack_consumer();
+
+    /* Should never reach here due to stack overflow */
+    printf("Returned from depth %d\n", recursion_depth);
 }
 #pragma GCC diagnostic pop
 
@@ -141,65 +139,65 @@ static void stack_consumer(void)
 __USER_TEXT
 static void corrupt_canary_directly(void)
 {
-	uint32_t *stack_ptr;
-	uint32_t *search_ptr;
-	uint32_t *stack_limit;
-	int found = 0;
-
-	/* Get current stack pointer */
-	__asm__ volatile ("mov %0, sp" : "=r" (stack_ptr));
-
-	printf("Current SP: %p\n", (void *)stack_ptr);
-
-	/* ARM stacks grow downward. Canary is at stack_base (lowest address).
-	 * Search from current SP down to approximate stack limit.
-	 * Be conservative to avoid faulting on invalid memory.
-	 */
-	stack_limit = stack_ptr - STACK_SIZE_WORDS;
-
-	for (search_ptr = stack_limit; search_ptr < stack_ptr; search_ptr++) {
-		if (*search_ptr == 0xDEADBEEF) {
-			printf("Found canary at %p\n", (void *)search_ptr);
-			printf("Corrupting canary...\n");
-			*search_ptr = 0xBADCAFE;
-			found = 1;
-			break;
-		}
-	}
-
-	if (!found) {
-		printf("Warning: Canary not found in search range\n");
-		printf("Trying recursion-based overflow...\n");
-		stack_consumer();
-	}
-
-	/* Trigger context switch to detect corruption */
-	printf("Triggering context switch...\n");
-	L4_Sleep(L4_TimePeriod(1000));
-
-	/* Should not reach here - kernel should panic */
-	printf("[FAULT:UNEXPECTED] No panic after canary corruption!\n");
+    uint32_t *stack_ptr;
+    uint32_t *search_ptr;
+    uint32_t *stack_limit;
+    int found = 0;
+
+    /* Get current stack pointer */
+    __asm__ volatile("mov %0, sp" : "=r"(stack_ptr));
+
+    printf("Current SP: %p\n", (void *) stack_ptr);
+
+    /* ARM stacks grow downward. Canary is at stack_base (lowest address).
+     * Search from current SP down to approximate stack limit.
+     * Be conservative to avoid faulting on invalid memory.
+     */
+    stack_limit = stack_ptr - STACK_SIZE_WORDS;
+
+    for (search_ptr = stack_limit; search_ptr < stack_ptr; search_ptr++) {
+        if (*search_ptr == 0xDEADBEEF) {
+            printf("Found canary at %p\n", (void *) search_ptr);
+            printf("Corrupting canary...\n");
+            *search_ptr = 0xBADCAFE;
+            found = 1;
+            break;
+        }
+    }
+
+    if (!found) {
+        printf("Warning: Canary not found in search range\n");
+        printf("Trying recursion-based overflow...\n");
+        stack_consumer();
+    }
+
+    /* Trigger context switch to detect corruption */
+    printf("Triggering context switch...\n");
+    L4_Sleep(L4_TimePeriod(1000));
+
+    /* Should not reach here - kernel should panic */
+    printf("[FAULT:UNEXPECTED] No panic after canary corruption!\n");
 }
 
 __USER_TEXT
 void run_fault_test(void)
 {
-	printf("\n=== Stack Canary Trip Test ===\n");
+    printf("\n=== Stack Canary Trip Test ===\n");
 
-	/* Signal expected fault type */
-	FAULT_EXPECT("stack_canary_trip");
+    /* Signal expected fault type */
+    FAULT_EXPECT("stack_canary_trip");
 
-	/* Small delay to ensure output is flushed */
-	L4_Sleep(L4_TimePeriod(10000));
+    /* Small delay to ensure output is flushed */
+    L4_Sleep(L4_TimePeriod(10000));
 
-	/* Initialize recursion counter */
-	recursion_depth = 0;
+    /* Initialize recursion counter */
+    recursion_depth = 0;
 
-	/* Try direct canary corruption first, fall back to recursion */
-	corrupt_canary_directly();
+    /* Try direct canary corruption first, fall back to recursion */
+    corrupt_canary_directly();
 
-	/* Should never reach here */
-	printf("[FAULT:ERROR] Test did not trigger expected fault\n");
+    /* Should never reach here */
+    printf("[FAULT:ERROR] Test did not trigger expected fault\n");
 }
 
 #else
@@ -207,7 +205,7 @@ void run_fault_test(void)
 __USER_TEXT
 void run_fault_test(void)
 {
-	printf("[FAULT:ERROR] No fault type selected\n");
-	printf("Use: make run-tests FAULT=mpu|canary\n");
+    printf("[FAULT:ERROR] No fault type selected\n");
+    printf("Use: make run-tests FAULT=mpu|canary\n");
 }
 #endif
diff --git a/user/apps/tests/test-ipc.c b/user/apps/tests/test-ipc.c
index 7f237947..c614f66f 100644
--- a/user/apps/tests/test-ipc.c
+++ b/user/apps/tests/test-ipc.c
@@ -4,8 +4,8 @@
  */
 
 #include <l4/ipc.h>
-#include <l4/thread.h>
 #include <l4/pager.h>
+#include <l4/thread.h>
 #include <l4io.h>
 
 #include "tests.h"
@@ -30,29 +30,29 @@ __USER_BSS static volatile int receiver_done;
 __USER_TEXT
 static void *receiver_thread(void *arg)
 {
-	L4_MsgTag_t tag;
-	L4_Msg_t msg;
-	L4_ThreadId_t from;
-
-	/* Signal ready before blocking on receive */
-	receiver_ready = 1;
-
-	/* Wait for message from sender (with timeout to avoid blocking forever) */
-	tag = L4_Wait_Timeout(L4_TimePeriod(500000), &from);
-
-	if (L4_IpcSucceeded(tag)) {
-		L4_MsgStore(tag, &msg);
-		received_value = L4_MsgWord(&msg, 0);
-		received_label = L4_Label(tag);
-		received_from = from.raw;
-	} else {
-		received_value = 0;
-		received_label = 0;
-		received_from = 0;
-	}
-
-	receiver_done = 1;
-	return NULL;
+    L4_MsgTag_t tag;
+    L4_Msg_t msg;
+    L4_ThreadId_t from;
+
+    /* Signal ready before blocking on receive */
+    receiver_ready = 1;
+
+    /* Wait for message from sender (with timeout to avoid blocking forever) */
+    tag = L4_Wait_Timeout(L4_TimePeriod(500000), &from);
+
+    if (L4_IpcSucceeded(tag)) {
+        L4_MsgStore(tag, &msg);
+        received_value = L4_MsgWord(&msg, 0);
+        received_label = L4_Label(tag);
+        received_from = from.raw;
+    } else {
+        received_value = 0;
+        received_label = 0;
+        received_from = 0;
+    }
+
+    receiver_done = 1;
+    return NULL;
 }
 
 /*
@@ -62,36 +62,36 @@ static void *receiver_thread(void *arg)
 __USER_TEXT
 static void *sender_thread(void *arg)
 {
-	L4_Msg_t msg;
-	L4_MsgTag_t tag;
-	int timeout;
-
-	/* Wait for receiver to be ready (handshake) */
-	timeout = 100;
-	while (!receiver_ready && timeout > 0) {
-		L4_Sleep(L4_TimePeriod(1000)); /* 1ms */
-		timeout--;
-	}
-
-	if (!receiver_ready) {
-		printf("Sender: receiver not ready\n");
-		return NULL;
-	}
-
-	/* Send magic value to receiver */
-	L4_MsgClear(&msg);
-	L4_Set_Label(&msg.tag, IPC_MAGIC_LABEL);
-	L4_MsgAppendWord(&msg, IPC_MAGIC_VALUE);
-	L4_MsgLoad(&msg);
-
-	/* Use timeout to avoid blocking forever */
-	tag = L4_Send_Timeout(receiver_tid, L4_TimePeriod(100000));
-
-	if (!L4_IpcSucceeded(tag)) {
-		printf("IPC send failed\n");
-	}
-
-	return NULL;
+    L4_Msg_t msg;
+    L4_MsgTag_t tag;
+    int timeout;
+
+    /* Wait for receiver to be ready (handshake) */
+    timeout = 100;
+    while (!receiver_ready && timeout > 0) {
+        L4_Sleep(L4_TimePeriod(1000)); /* 1ms */
+        timeout--;
+    }
+
+    if (!receiver_ready) {
+        printf("Sender: receiver not ready\n");
+        return NULL;
+    }
+
+    /* Send magic value to receiver */
+    L4_MsgClear(&msg);
+    L4_Set_Label(&msg.tag, IPC_MAGIC_LABEL);
+    L4_MsgAppendWord(&msg, IPC_MAGIC_VALUE);
+    L4_MsgLoad(&msg);
+
+    /* Use timeout to avoid blocking forever */
+    tag = L4_Send_Timeout(receiver_tid, L4_TimePeriod(100000));
+
+    if (!L4_IpcSucceeded(tag)) {
+        printf("IPC send failed\n");
+    }
+
+    return NULL;
 }
 
 /*
@@ -101,64 +101,60 @@ static void *sender_thread(void *arg)
 __USER_TEXT
 void test_ipc_basic(void)
 {
-	int timeout;
-	int ok;
-
-	TEST_RUN("ipc_basic");
-
-	/* Initialize shared state */
-	received_value = 0;
-	received_label = 0;
-	received_from = 0;
-	receiver_ready = 0;
-	receiver_done = 0;
-
-	/* Create receiver thread first (so it's ready to receive) */
-	receiver_tid = pager_create_thread();
-	if (receiver_tid.raw == 0) {
-		printf("Failed to create receiver thread\n");
-		TEST_FAIL("ipc_basic");
-		return;
-	}
-
-	/* Create sender thread */
-	sender_tid = pager_create_thread();
-	if (sender_tid.raw == 0) {
-		printf("Failed to create sender thread\n");
-		TEST_FAIL("ipc_basic");
-		return;
-	}
-
-	/* Start receiver first, then sender */
-	pager_start_thread(receiver_tid, receiver_thread, NULL);
-	pager_start_thread(sender_tid, sender_thread, NULL);
-
-	/* Wait for receiver to complete (simple polling with timeout) */
-	timeout = 100; /* ~1 second with 10ms sleeps */
-	while (!receiver_done && timeout > 0) {
-		L4_Sleep(L4_TimePeriod(10000)); /* 10ms */
-		timeout--;
-	}
-
-	/* Verify: value, label, and sender TID */
-	ok = receiver_done &&
-	     received_value == IPC_MAGIC_VALUE &&
-	     received_label == IPC_MAGIC_LABEL &&
-	     received_from == sender_tid.raw;
-
-	if (ok) {
-		TEST_PASS("ipc_basic");
-	} else {
-		printf("IPC failed: val=0x%lx label=0x%lx from=0x%lx\n",
-		       (unsigned long)received_value,
-		       (unsigned long)received_label,
-		       (unsigned long)received_from);
-		printf("  expected: val=0x%lx label=0x%lx from=0x%lx\n",
-		       (unsigned long)IPC_MAGIC_VALUE,
-		       (unsigned long)IPC_MAGIC_LABEL,
-		       (unsigned long)sender_tid.raw);
-		TEST_FAIL("ipc_basic");
-	}
+    int timeout;
+    int ok;
+
+    TEST_RUN("ipc_basic");
+
+    /* Initialize shared state */
+    received_value = 0;
+    received_label = 0;
+    received_from = 0;
+    receiver_ready = 0;
+    receiver_done = 0;
+
+    /* Create receiver thread first (so it's ready to receive) */
+    receiver_tid = pager_create_thread();
+    if (receiver_tid.raw == 0) {
+        printf("Failed to create receiver thread\n");
+        TEST_FAIL("ipc_basic");
+        return;
+    }
+
+    /* Create sender thread */
+    sender_tid = pager_create_thread();
+    if (sender_tid.raw == 0) {
+        printf("Failed to create sender thread\n");
+        TEST_FAIL("ipc_basic");
+        return;
+    }
+
+    /* Start receiver first, then sender */
+    pager_start_thread(receiver_tid, receiver_thread, NULL);
+    pager_start_thread(sender_tid, sender_thread, NULL);
+
+    /* Wait for receiver to complete (simple polling with timeout) */
+    timeout = 100; /* ~1 second with 10ms sleeps */
+    while (!receiver_done && timeout > 0) {
+        L4_Sleep(L4_TimePeriod(10000)); /* 10ms */
+        timeout--;
+    }
+
+    /* Verify: value, label, and sender TID */
+    ok = receiver_done && received_value == IPC_MAGIC_VALUE &&
+         received_label == IPC_MAGIC_LABEL && received_from == sender_tid.raw;
+
+    if (ok) {
+        TEST_PASS("ipc_basic");
+    } else {
+        printf("IPC failed: val=0x%lx label=0x%lx from=0x%lx\n",
+               (unsigned long) received_value, (unsigned long) received_label,
+               (unsigned long) received_from);
+        printf("  expected: val=0x%lx label=0x%lx from=0x%lx\n",
+               (unsigned long) IPC_MAGIC_VALUE, (unsigned long) IPC_MAGIC_LABEL,
+               (unsigned long) sender_tid.raw);
+        TEST_FAIL("ipc_basic");
+    }
 }
 
 /* Multi-word IPC test state */
@@ -179,33 +175,33 @@ __USER_BSS static L4_ThreadId_t multi_receiver_tid;
 __USER_TEXT
 static void *multi_receiver_thread(void *arg)
 {
-	L4_MsgTag_t tag;
-	L4_Msg_t msg;
-	L4_ThreadId_t from;
-	L4_Word_t i;
-
-	/* Signal ready before blocking */
-	multi_receiver_ready = 1;
-
-	/* Use timeout to avoid blocking forever */
-	tag = L4_Wait_Timeout(L4_TimePeriod(500000), &from);
-
-	if (L4_IpcSucceeded(tag)) {
-		L4_MsgStore(tag, &msg);
-		multi_word_count = L4_UntypedWords(tag);
-		multi_label = L4_Label(tag);
-		multi_from = from.raw;
-		for (i = 0; i < multi_word_count && i < 4; i++) {
-			multi_words[i] = L4_MsgWord(&msg, i);
-		}
-	} else {
-		multi_word_count = 0;
-		multi_label = 0;
-		multi_from = 0;
-	}
-
-	multi_receiver_done = 1;
-	return NULL;
+    L4_MsgTag_t tag;
+    L4_Msg_t msg;
+    L4_ThreadId_t from;
+    L4_Word_t i;
+
+    /* Signal ready before blocking */
+    multi_receiver_ready = 1;
+
+    /* Use timeout to avoid blocking forever */
+    tag = L4_Wait_Timeout(L4_TimePeriod(500000), &from);
+
+    if (L4_IpcSucceeded(tag)) {
+        L4_MsgStore(tag, &msg);
+        multi_word_count = L4_UntypedWords(tag);
+        multi_label = L4_Label(tag);
+        multi_from = from.raw;
+        for (i = 0; i < multi_word_count && i < 4; i++) {
+            multi_words[i] = L4_MsgWord(&msg, i);
+        }
+    } else {
+        multi_word_count = 0;
+        multi_label = 0;
+        multi_from = 0;
+    }
+
+    multi_receiver_done = 1;
+    return NULL;
 }
 
 /*
@@ -215,36 +211,36 @@ static void *multi_receiver_thread(void *arg)
 __USER_TEXT
 static void *multi_sender_thread(void *arg)
 {
-	L4_Msg_t msg;
-	L4_MsgTag_t tag;
-	int timeout;
-
-	/* Wait for receiver to be ready (handshake) */
-	timeout = 100;
-	while (!multi_receiver_ready && timeout > 0) {
-		L4_Sleep(L4_TimePeriod(1000)); /* 1ms */
-		timeout--;
-	}
-
-	if (!multi_receiver_ready) {
-		/* Receiver not ready, abort */
-		return NULL;
-	}
-
-	/* Send 4 words */
-	L4_MsgClear(&msg);
-	L4_Set_Label(&msg.tag, IPC_MULTI_LABEL);
-	L4_MsgAppendWord(&msg, 0x11111111);
-	L4_MsgAppendWord(&msg, 0x22222222);
-	L4_MsgAppendWord(&msg, 0x33333333);
-	L4_MsgAppendWord(&msg, 0x44444444);
-	L4_MsgLoad(&msg);
-
-	/* Use timeout to avoid blocking forever */
-	tag = L4_Send_Timeout(multi_receiver_tid, L4_TimePeriod(100000));
-	(void)tag;
-
-	return NULL;
+    L4_Msg_t msg;
+    L4_MsgTag_t tag;
+    int timeout;
+
+    /* Wait for receiver to be ready (handshake) */
+    timeout = 100;
+    while (!multi_receiver_ready && timeout > 0) {
+        L4_Sleep(L4_TimePeriod(1000)); /* 1ms */
+        timeout--;
+    }
+
+    if (!multi_receiver_ready) {
+        /* Receiver not ready, abort */
+        return NULL;
+    }
+
+    /* Send 4 words */
+    L4_MsgClear(&msg);
+    L4_Set_Label(&msg.tag, IPC_MULTI_LABEL);
+    L4_MsgAppendWord(&msg, 0x11111111);
+    L4_MsgAppendWord(&msg, 0x22222222);
+    L4_MsgAppendWord(&msg, 0x33333333);
+    L4_MsgAppendWord(&msg, 0x44444444);
+    L4_MsgLoad(&msg);
+
+    /* Use timeout to avoid blocking forever */
+    tag = L4_Send_Timeout(multi_receiver_tid, L4_TimePeriod(100000));
+    (void) tag;
+
+    return NULL;
 }
 
 /*
@@ -254,64 +250,59 @@ static void *multi_sender_thread(void *arg)
 __USER_TEXT
 void test_ipc_multiword(void)
 {
-	L4_ThreadId_t mw_receiver, mw_sender;
-	int timeout;
-	int ok;
-
-	TEST_RUN("ipc_multiword");
-
-	multi_word_count = 0;
-	multi_words[0] = multi_words[1] = 0;
-	multi_words[2] = multi_words[3] = 0;
-	multi_label = 0;
-	multi_from = 0;
-	multi_receiver_ready = 0;
-	multi_receiver_done = 0;
-
-	/* Create threads */
-	mw_receiver = pager_create_thread();
-	if (mw_receiver.raw == 0) {
-		printf("Failed to create multi-word receiver\n");
-		TEST_FAIL("ipc_multiword");
-		return;
-	}
-
-	mw_sender = pager_create_thread();
-	if (mw_sender.raw == 0) {
-		printf("Failed to create multi-word sender\n");
-		TEST_FAIL("ipc_multiword");
-		return;
-	}
-
-	/* Store TIDs for threads to use (separate from basic IPC test) */
-	multi_receiver_tid = mw_receiver;
-	multi_sender_tid = mw_sender;
-
-	pager_start_thread(mw_receiver, multi_receiver_thread, NULL);
-	pager_start_thread(mw_sender, multi_sender_thread, NULL);
-
-	timeout = 50;
-	while (!multi_receiver_done && timeout > 0) {
-		L4_Sleep(L4_TimePeriod(10000));
-		timeout--;
-	}
-
-	/* Verify all 4 words, label, and sender TID */
-	ok = multi_receiver_done &&
-	     multi_word_count >= 4 &&
-	     multi_words[0] == 0x11111111 &&
-	     multi_words[1] == 0x22222222 &&
-	     multi_words[2] == 0x33333333 &&
-	     multi_words[3] == 0x44444444 &&
-	     multi_label == IPC_MULTI_LABEL &&
-	     multi_from == mw_sender.raw;
-
-	if (ok) {
-		TEST_PASS("ipc_multiword");
-	} else {
-		printf("Multi-word IPC failed: count=%lu label=0x%lx\n",
-		       (unsigned long)multi_word_count,
-		       (unsigned long)multi_label);
-		TEST_FAIL("ipc_multiword");
-	}
+    L4_ThreadId_t mw_receiver, mw_sender;
+    int timeout;
+    int ok;
+
+    TEST_RUN("ipc_multiword");
+
+    multi_word_count = 0;
+    multi_words[0] = multi_words[1] = 0;
+    multi_words[2] = multi_words[3] = 0;
+    multi_label = 0;
+    multi_from = 0;
+    multi_receiver_ready = 0;
+    multi_receiver_done = 0;
+
+    /* Create threads */
+    mw_receiver = pager_create_thread();
+    if (mw_receiver.raw == 0) {
+        printf("Failed to create multi-word receiver\n");
+        TEST_FAIL("ipc_multiword");
+        return;
+    }
+
+    mw_sender = pager_create_thread();
+    if (mw_sender.raw == 0) {
+        printf("Failed to create multi-word sender\n");
+        TEST_FAIL("ipc_multiword");
+        return;
+    }
+
+    /* Store TIDs for threads to use (separate from basic IPC test) */
+    multi_receiver_tid = mw_receiver;
+    multi_sender_tid = mw_sender;
+
+    pager_start_thread(mw_receiver, multi_receiver_thread, NULL);
+    pager_start_thread(mw_sender, multi_sender_thread, NULL);
+
+    timeout = 50;
+    while (!multi_receiver_done && timeout > 0) {
+        L4_Sleep(L4_TimePeriod(10000));
+        timeout--;
+    }
+
+    /* Verify all 4 words, label, and sender TID */
+    ok = multi_receiver_done && multi_word_count >= 4 &&
+         multi_words[0] == 0x11111111 && multi_words[1] == 0x22222222 &&
+         multi_words[2] == 0x33333333 && multi_words[3] == 0x44444444 &&
+         multi_label == IPC_MULTI_LABEL && multi_from == mw_sender.raw;
+
+    if (ok) {
+        TEST_PASS("ipc_multiword");
+    } else {
+        printf("Multi-word IPC failed: count=%lu label=0x%lx\n",
+               (unsigned long) multi_word_count, (unsigned long) multi_label);
+        TEST_FAIL("ipc_multiword");
+    }
 }
diff --git a/user/apps/tests/test-irq.c b/user/apps/tests/test-irq.c
index 5064e0e0..24a916d3 100644
--- a/user/apps/tests/test-irq.c
+++ b/user/apps/tests/test-irq.c
@@ -25,48 +25,48 @@ static volatile uint32_t exti1_count;
 __USER_TEXT
 static void exti_config(uint32_t line, uint32_t mode, uint32_t trigger_type)
 {
-	struct exti_regs *exti_regs = (struct exti_regs *)EXTI_BASE;
+    struct exti_regs *exti_regs = (struct exti_regs *) EXTI_BASE;
 
-	/* Clear EXTI mask */
-	exti_regs->IMR &= ~EXTI_LINE(line);
-	exti_regs->EMR &= ~EXTI_LINE(line);
+    /* Clear EXTI mask */
+    exti_regs->IMR &= ~EXTI_LINE(line);
+    exti_regs->EMR &= ~EXTI_LINE(line);
 
-	*((volatile uint32_t *)(EXTI_BASE + mode)) |= EXTI_LINE(line);
+    *((volatile uint32_t *) (EXTI_BASE + mode)) |= EXTI_LINE(line);
 
-	if (trigger_type == EXTI_RISING_FALLING_TRIGGER) {
-		exti_regs->RTSR |= EXTI_LINE(line);
-		exti_regs->FTSR |= EXTI_LINE(line);
-	} else {
-		*((volatile uint32_t *)(EXTI_BASE + mode)) |= EXTI_LINE(line);
-	}
+    if (trigger_type == EXTI_RISING_FALLING_TRIGGER) {
+        exti_regs->RTSR |= EXTI_LINE(line);
+        exti_regs->FTSR |= EXTI_LINE(line);
+    } else {
+        *((volatile uint32_t *) (EXTI_BASE + mode)) |= EXTI_LINE(line);
+    }
 }
 
 __USER_TEXT
 static void exti_launch_sw_interrupt(uint32_t line)
 {
-	struct exti_regs *exti_regs = (struct exti_regs *)EXTI_BASE;
-	exti_regs->SWIER |= EXTI_LINE(line);
+    struct exti_regs *exti_regs = (struct exti_regs *) EXTI_BASE;
+    exti_regs->SWIER |= EXTI_LINE(line);
 }
 
 __USER_TEXT
 static void exti_clear(uint32_t line)
 {
-	struct exti_regs *exti_regs = (struct exti_regs *)EXTI_BASE;
-	exti_regs->PR = EXTI_LINE(line);
+    struct exti_regs *exti_regs = (struct exti_regs *) EXTI_BASE;
+    exti_regs->PR = EXTI_LINE(line);
 }
 
 __USER_TEXT
 static void exti0_handler(void)
 {
-	exti_clear(0);
-	exti0_count++;
+    exti_clear(0);
+    exti0_count++;
 }
 
 __USER_TEXT
 static void exti1_handler(void)
 {
-	exti_clear(1);
-	exti1_count++;
+    exti_clear(1);
+    exti1_count++;
 }
 
 /*
@@ -76,39 +76,38 @@ static void exti1_handler(void)
 __USER_TEXT
 void test_irq_exti(void)
 {
-	TEST_RUN("irq_exti");
-
-	exti0_count = 0;
-	exti1_count = 0;
-
-	/* Register interrupt handlers */
-	request_irq(EXTI0_IRQn, exti0_handler, 1);
-	request_irq(EXTI1_IRQn, exti1_handler, 1);
-
-	/* Configure EXTI lines */
-	exti_config(0, EXTI_INTERRUPT_MODE, EXTI_RISING_TRIGGER);
-	exti_config(1, EXTI_INTERRUPT_MODE, EXTI_RISING_TRIGGER);
-
-	/* Trigger software interrupts */
-	exti_launch_sw_interrupt(0);
-	L4_Sleep(L4_TimePeriod(10000)); /* 10ms */
-
-	exti_launch_sw_interrupt(1);
-	L4_Sleep(L4_TimePeriod(10000)); /* 10ms */
-
-	/* Cleanup */
-	free_irq(EXTI0_IRQn);
-	free_irq(EXTI1_IRQn);
-
-	/* Verify interrupts fired */
-	if (exti0_count > 0 && exti1_count > 0) {
-		TEST_PASS("irq_exti");
-	} else {
-		printf("EXTI counts: exti0=%lu exti1=%lu\n",
-		       (unsigned long)exti0_count,
-		       (unsigned long)exti1_count);
-		TEST_FAIL("irq_exti");
-	}
+    TEST_RUN("irq_exti");
+
+    exti0_count = 0;
+    exti1_count = 0;
+
+    /* Register interrupt handlers */
+    request_irq(EXTI0_IRQn, exti0_handler, 1);
+    request_irq(EXTI1_IRQn, exti1_handler, 1);
+
+    /* Configure EXTI lines */
+    exti_config(0, EXTI_INTERRUPT_MODE, EXTI_RISING_TRIGGER);
+    exti_config(1, EXTI_INTERRUPT_MODE, EXTI_RISING_TRIGGER);
+
+    /* Trigger software interrupts */
+    exti_launch_sw_interrupt(0);
+    L4_Sleep(L4_TimePeriod(10000)); /* 10ms */
+
+    exti_launch_sw_interrupt(1);
+    L4_Sleep(L4_TimePeriod(10000)); /* 10ms */
+
+    /* Cleanup */
+    free_irq(EXTI0_IRQn);
+    free_irq(EXTI1_IRQn);
+
+    /* Verify interrupts fired */
+    if (exti0_count > 0 && exti1_count > 0) {
+        TEST_PASS("irq_exti");
+    } else {
+        printf("EXTI counts: exti0=%lu exti1=%lu\n",
+               (unsigned long) exti0_count, (unsigned long) exti1_count);
+        TEST_FAIL("irq_exti");
+    }
 }
 
 #endif /* CONFIG_EXTI_INTERRUPT_TEST */
diff --git a/user/apps/tests/test-kip.c b/user/apps/tests/test-kip.c
index 23cea0c8..57e29b2e 100644
--- a/user/apps/tests/test-kip.c
+++ b/user/apps/tests/test-kip.c
@@ -14,19 +14,19 @@
 __USER_TEXT
 void test_kip_access(void)
 {
-	void *kip;
+    void *kip;
 
-	TEST_RUN("kip_access");
+    TEST_RUN("kip_access");
 
-	kip = L4_GetKernelInterface();
+    kip = L4_GetKernelInterface();
 
-	/* KIP pointer should be non-NULL */
-	if (kip) {
-		TEST_PASS("kip_access");
-	} else {
-		printf("L4_GetKernelInterface() returned NULL\n");
-		TEST_FAIL("kip_access");
-	}
+    /* KIP pointer should be non-NULL */
+    if (kip) {
+        TEST_PASS("kip_access");
+    } else {
+        printf("L4_GetKernelInterface() returned NULL\n");
+        TEST_FAIL("kip_access");
+    }
 }
 
 /*
@@ -35,26 +35,25 @@ void test_kip_access(void)
 __USER_TEXT
 void test_kip_processors(void)
 {
-	void *kip;
-	L4_Word_t num_procs;
-
-	TEST_RUN("kip_processors");
-
-	kip = L4_GetKernelInterface();
-	if (!kip) {
-		printf("L4_GetKernelInterface() returned NULL\n");
-		TEST_FAIL("kip_processors");
-		return;
-	}
-
-	num_procs = L4_NumProcessors(kip);
-
-	/* Should have at least 1 processor */
-	if (num_procs >= 1) {
-		TEST_PASS("kip_processors");
-	} else {
-		printf("L4_NumProcessors() returned %lu\n",
-		       (unsigned long)num_procs);
-		TEST_FAIL("kip_processors");
-	}
+    void *kip;
+    L4_Word_t num_procs;
+
+    TEST_RUN("kip_processors");
+
+    kip = L4_GetKernelInterface();
+    if (!kip) {
+        printf("L4_GetKernelInterface() returned NULL\n");
+        TEST_FAIL("kip_processors");
+        return;
+    }
+
+    num_procs = L4_NumProcessors(kip);
+
+    /* Should have at least 1 processor */
+    if (num_procs >= 1) {
+        TEST_PASS("kip_processors");
+    } else {
+        printf("L4_NumProcessors() returned %lu\n", (unsigned long) num_procs);
+        TEST_FAIL("kip_processors");
+    }
 }
diff --git a/user/apps/tests/test-safety.c b/user/apps/tests/test-safety.c
index b27a1052..331e184f 100644
--- a/user/apps/tests/test-safety.c
+++ b/user/apps/tests/test-safety.c
@@ -16,9 +16,9 @@
  */
 
 #include <l4/ipc.h>
-#include <l4/thread.h>
 #include <l4/pager.h>
 #include <l4/schedule.h>
+#include <l4/thread.h>
 #include <l4io.h>
 
 #include "tests.h"
@@ -32,33 +32,33 @@
 __USER_TEXT
 void test_ipc_timeout_send(void)
 {
-	L4_MsgTag_t tag;
-	L4_Msg_t msg;
-	L4_ThreadId_t invalid_tid;
-	L4_Time_t timeout;
+    L4_MsgTag_t tag;
+    L4_Msg_t msg;
+    L4_ThreadId_t invalid_tid;
+    L4_Time_t timeout;
 
-	TEST_RUN("ipc_timeout_send");
+    TEST_RUN("ipc_timeout_send");
 
-	/* Create an invalid TID (high number unlikely to exist) */
-	invalid_tid.raw = 0xFFFF0000;
+    /* Create an invalid TID (high number unlikely to exist) */
+    invalid_tid.raw = 0xFFFF0000;
 
-	/* Short timeout: ~10ms */
-	timeout = L4_TimePeriod(10000);
+    /* Short timeout: ~10ms */
+    timeout = L4_TimePeriod(10000);
 
-	/* Try to send - should timeout, not hang */
-	L4_MsgClear(&msg);
-	L4_MsgAppendWord(&msg, 0xDEADBEEF);
-	L4_MsgLoad(&msg);
+    /* Try to send - should timeout, not hang */
+    L4_MsgClear(&msg);
+    L4_MsgAppendWord(&msg, 0xDEADBEEF);
+    L4_MsgLoad(&msg);
 
-	tag = L4_Send_Timeout(invalid_tid, timeout);
+    tag = L4_Send_Timeout(invalid_tid, timeout);
 
-	/* Expect IPC to fail (no valid receiver) */
-	if (L4_IpcFailed(tag)) {
-		TEST_PASS("ipc_timeout_send");
-	} else {
-		printf("Unexpected: IPC succeeded to invalid TID\n");
-		TEST_FAIL("ipc_timeout_send");
-	}
+    /* Expect IPC to fail (no valid receiver) */
+    if (L4_IpcFailed(tag)) {
+        TEST_PASS("ipc_timeout_send");
+    } else {
+        printf("Unexpected: IPC succeeded to invalid TID\n");
+        TEST_FAIL("ipc_timeout_send");
+    }
 }
 
 /*
@@ -70,26 +70,26 @@ void test_ipc_timeout_send(void)
 __USER_TEXT
 void test_ipc_timeout_receive(void)
 {
-	L4_MsgTag_t tag;
-	L4_ThreadId_t from;
-	L4_Time_t timeout;
-
-	TEST_RUN("ipc_timeout_receive");
-
-	/* Short timeout: ~10ms */
-	timeout = L4_TimePeriod(10000);
-
-	/* Wait for message that will never come */
-	tag = L4_Wait_Timeout(timeout, &from);
-
-	/* Expect timeout (IPC failed) since no sender */
-	if (L4_IpcFailed(tag)) {
-		TEST_PASS("ipc_timeout_receive");
-	} else {
-		printf("Unexpected: received message from 0x%lx\n",
-		       (unsigned long)from.raw);
-		TEST_FAIL("ipc_timeout_receive");
-	}
+    L4_MsgTag_t tag;
+    L4_ThreadId_t from;
+    L4_Time_t timeout;
+
+    TEST_RUN("ipc_timeout_receive");
+
+    /* Short timeout: ~10ms */
+    timeout = L4_TimePeriod(10000);
+
+    /* Wait for message that will never come */
+    tag = L4_Wait_Timeout(timeout, &from);
+
+    /* Expect timeout (IPC failed) since no sender */
+    if (L4_IpcFailed(tag)) {
+        TEST_PASS("ipc_timeout_receive");
+    } else {
+        printf("Unexpected: received message from 0x%lx\n",
+               (unsigned long) from.raw);
+        TEST_FAIL("ipc_timeout_receive");
+    }
 }
 
 /*
@@ -107,13 +107,13 @@ void test_ipc_timeout_receive(void)
 __USER_TEXT
 void test_timer_zero_sleep(void)
 {
-	TEST_RUN("timer_zero_sleep");
+    TEST_RUN("timer_zero_sleep");
 
-	/* Small sleep should work */
-	L4_Sleep(L4_TimePeriod(1000)); /* 1ms */
+    /* Small sleep should work */
+    L4_Sleep(L4_TimePeriod(1000)); /* 1ms */
 
-	/* If we reach here without hanging, test passes */
-	TEST_PASS("timer_zero_sleep");
+    /* If we reach here without hanging, test passes */
+    TEST_PASS("timer_zero_sleep");
 }
 
 /*
@@ -131,33 +131,33 @@ __USER_BSS static volatile int monotonicity_counter;
 __USER_TEXT
 void test_timer_monotonicity(void)
 {
-	int i;
-	int prev_counter;
-	int ok = 1;
-
-	TEST_RUN("timer_monotonicity");
-
-	monotonicity_counter = 0;
-
-	/* Sleep multiple times and verify counter increases */
-	for (i = 0; i < 5; i++) {
-		prev_counter = monotonicity_counter;
-		L4_Sleep(L4_TimePeriod(1000)); /* 1ms */
-		monotonicity_counter = i + 1;
-
-		if (monotonicity_counter <= prev_counter && i > 0) {
-			printf("Monotonicity violation at iteration %d\n", i);
-			ok = 0;
-			break;
-		}
-	}
-
-	/* Additionally verify we can measure elapsed "time" */
-	if (ok && monotonicity_counter == 5) {
-		TEST_PASS("timer_monotonicity");
-	} else {
-		TEST_FAIL("timer_monotonicity");
-	}
+    int i;
+    int prev_counter;
+    int ok = 1;
+
+    TEST_RUN("timer_monotonicity");
+
+    monotonicity_counter = 0;
+
+    /* Sleep multiple times and verify counter increases */
+    for (i = 0; i < 5; i++) {
+        prev_counter = monotonicity_counter;
+        L4_Sleep(L4_TimePeriod(1000)); /* 1ms */
+        monotonicity_counter = i + 1;
+
+        if (monotonicity_counter <= prev_counter && i > 0) {
+            printf("Monotonicity violation at iteration %d\n", i);
+            ok = 0;
+            break;
+        }
+    }
+
+    /* Additionally verify we can measure elapsed "time" */
+    if (ok && monotonicity_counter == 5) {
+        TEST_PASS("timer_monotonicity");
+    } else {
+        TEST_FAIL("timer_monotonicity");
+    }
 }
 
 /*
@@ -176,24 +176,24 @@ void test_timer_monotonicity(void)
 __USER_TEXT
 void test_thread_priority(void)
 {
-	L4_ThreadId_t self;
-	L4_Word_t result;
+    L4_ThreadId_t self;
+    L4_Word_t result;
 
-	TEST_RUN("thread_priority");
+    TEST_RUN("thread_priority");
 
-	self = L4_Myself();
+    self = L4_Myself();
 
-	/* Try to set priority (may or may not succeed based on policy) */
-	result = L4_Set_Priority(self, 100);
+    /* Try to set priority (may or may not succeed based on policy) */
+    result = L4_Set_Priority(self, 100);
 
-	/* L4_Schedule returns thread state or 0 on error */
-	if (result != L4_SCHEDRESULT_ERROR) {
-		TEST_PASS("thread_priority");
-	} else {
-		/* Some kernels may not allow self-priority change */
-		printf("Priority change returned error (may be policy)\n");
-		TEST_PASS("thread_priority");
-	}
+    /* L4_Schedule returns thread state or 0 on error */
+    if (result != L4_SCHEDRESULT_ERROR) {
+        TEST_PASS("thread_priority");
+    } else {
+        /* Some kernels may not allow self-priority change */
+        printf("Priority change returned error (may be policy)\n");
+        TEST_PASS("thread_priority");
+    }
 }
 
 /*
@@ -204,15 +204,15 @@ void test_thread_priority(void)
 __USER_TEXT
 void test_thread_yield(void)
 {
-	int i;
+    int i;
 
-	TEST_RUN("thread_yield");
+    TEST_RUN("thread_yield");
 
-	/* Yield multiple times - should not hang */
-	for (i = 0; i < 3; i++) {
-		L4_Yield();
-	}
+    /* Yield multiple times - should not hang */
+    for (i = 0; i < 3; i++) {
+        L4_Yield();
+    }
 
-	/* If we get here, yield works */
-	TEST_PASS("thread_yield");
+    /* If we get here, yield works */
+    TEST_PASS("thread_yield");
 }
diff --git a/user/apps/tests/test-sched.c b/user/apps/tests/test-sched.c
index 28ba5518..613a5893 100644
--- a/user/apps/tests/test-sched.c
+++ b/user/apps/tests/test-sched.c
@@ -41,12 +41,12 @@
  * than the test environment provides, so tests focus on core mechanisms.
  */
 
-#include <user_runtime.h>
 #include <l4/ipc.h>
-#include <l4/thread.h>
 #include <l4/pager.h>
 #include <l4/schedule.h>
+#include <l4/thread.h>
 #include <l4io.h>
+#include <user_runtime.h>
 
 #include "tests.h"
 
@@ -60,24 +60,24 @@
 __USER_TEXT
 void test_sched_priority_order(void)
 {
-	L4_ThreadId_t self;
-	L4_Word_t result;
-
-	TEST_RUN("sched_priority_order");
-
-	self = L4_Myself();
-	result = L4_Set_Priority(self, 15);
-
-	/*
-	 * L4_Set_Priority returns thread state on success, 0 on error.
-	 * Policy may deny self-priority change, but syscall path works.
-	 */
-	if (result != L4_SCHEDRESULT_ERROR) {
-		TEST_PASS("sched_priority_order");
-	} else {
-		printf("Note: priority change denied by policy\n");
-		TEST_PASS("sched_priority_order");
-	}
+    L4_ThreadId_t self;
+    L4_Word_t result;
+
+    TEST_RUN("sched_priority_order");
+
+    self = L4_Myself();
+    result = L4_Set_Priority(self, 15);
+
+    /*
+     * L4_Set_Priority returns thread state on success, 0 on error.
+     * Policy may deny self-priority change, but syscall path works.
+     */
+    if (result != L4_SCHEDRESULT_ERROR) {
+        TEST_PASS("sched_priority_order");
+    } else {
+        printf("Note: priority change denied by policy\n");
+        TEST_PASS("sched_priority_order");
+    }
 }
 
 /*
@@ -90,22 +90,22 @@ void test_sched_priority_order(void)
 __USER_TEXT
 void test_sched_round_robin(void)
 {
-	int i;
-	volatile int counter = 0;
-
-	TEST_RUN("sched_round_robin");
-
-	for (i = 0; i < 5; i++) {
-		L4_Yield();
-		counter++;
-	}
-
-	if (counter == 5) {
-		TEST_PASS("sched_round_robin");
-	} else {
-		printf("Yield loop incomplete: %d/5\n", counter);
-		TEST_FAIL("sched_round_robin");
-	}
+    int i;
+    volatile int counter = 0;
+
+    TEST_RUN("sched_round_robin");
+
+    for (i = 0; i < 5; i++) {
+        L4_Yield();
+        counter++;
+    }
+
+    if (counter == 5) {
+        TEST_PASS("sched_round_robin");
+    } else {
+        printf("Yield loop incomplete: %d/5\n", counter);
+        TEST_FAIL("sched_round_robin");
+    }
 }
 
 /*
@@ -123,24 +123,24 @@ void test_sched_round_robin(void)
 __USER_TEXT
 void test_sched_no_starvation(void)
 {
-	int i;
-	volatile int progress = 0;
-
-	TEST_RUN("sched_no_starvation");
-
-	for (i = 0; i < 3; i++) {
-		L4_Sleep(L4_TimePeriod(5000)); /* 5ms - tests timer */
-		progress++;
-		L4_Yield(); /* tests scheduler */
-		progress++;
-	}
-
-	if (progress == 6) {
-		TEST_PASS("sched_no_starvation");
-	} else {
-		printf("Progress halted: %d/6\n", progress);
-		TEST_FAIL("sched_no_starvation");
-	}
+    int i;
+    volatile int progress = 0;
+
+    TEST_RUN("sched_no_starvation");
+
+    for (i = 0; i < 3; i++) {
+        L4_Sleep(L4_TimePeriod(5000)); /* 5ms - tests timer */
+        progress++;
+        L4_Yield(); /* tests scheduler */
+        progress++;
+    }
+
+    if (progress == 6) {
+        TEST_PASS("sched_no_starvation");
+    } else {
+        printf("Progress halted: %d/6\n", progress);
+        TEST_FAIL("sched_no_starvation");
+    }
 }
 
 /*
@@ -154,22 +154,22 @@ void test_sched_no_starvation(void)
 __USER_TEXT
 void test_sched_yield_returns(void)
 {
-	int i;
-	volatile int counter = 0;
-
-	TEST_RUN("sched_yield_returns");
-
-	for (i = 0; i < 10; i++) {
-		L4_Yield();
-		counter++;
-	}
-
-	if (counter == 10) {
-		TEST_PASS("sched_yield_returns");
-	} else {
-		printf("Yield stuck: %d/10\n", counter);
-		TEST_FAIL("sched_yield_returns");
-	}
+    int i;
+    volatile int counter = 0;
+
+    TEST_RUN("sched_yield_returns");
+
+    for (i = 0; i < 10; i++) {
+        L4_Yield();
+        counter++;
+    }
+
+    if (counter == 10) {
+        TEST_PASS("sched_yield_returns");
+    } else {
+        printf("Yield stuck: %d/10\n", counter);
+        TEST_FAIL("sched_yield_returns");
+    }
 }
 
 /*
@@ -185,12 +185,12 @@ void test_sched_yield_returns(void)
 __USER_TEXT
 void test_sched_idle_fallback(void)
 {
-	TEST_RUN("sched_idle_fallback");
+    TEST_RUN("sched_idle_fallback");
 
-	/* Sleep puts us in blocked state; idle runs; timer wakes us */
-	L4_Sleep(L4_TimePeriod(50000)); /* 50ms */
+    /* Sleep puts us in blocked state; idle runs; timer wakes us */
+    L4_Sleep(L4_TimePeriod(50000)); /* 50ms */
 
-	TEST_PASS("sched_idle_fallback");
+    TEST_PASS("sched_idle_fallback");
 }
 
 /*
@@ -212,16 +212,16 @@ void test_sched_idle_fallback(void)
 __USER_TEXT
 void test_sched_ipc_priority_boost(void)
 {
-	TEST_RUN("sched_ipc_priority_boost");
+    TEST_RUN("sched_ipc_priority_boost");
 
-	/*
-	 * F9's priority boost is kernel-internal (not exposed via syscall).
-	 * Validate the scheduler handles priority changes correctly by
-	 * confirming yield works after IPC-like operations.
-	 */
-	L4_Yield();
+    /*
+     * F9's priority boost is kernel-internal (not exposed via syscall).
+     * Validate the scheduler handles priority changes correctly by
+     * confirming yield works after IPC-like operations.
+     */
+    L4_Yield();
 
-	TEST_PASS("sched_ipc_priority_boost");
+    TEST_PASS("sched_ipc_priority_boost");
 }
 
 /*
@@ -233,19 +233,19 @@ void test_sched_ipc_priority_boost(void)
 __USER_TEXT
 void test_sched_syscall(void)
 {
-	L4_ThreadId_t self;
-	L4_Word_t result;
+    L4_ThreadId_t self;
+    L4_Word_t result;
 
-	TEST_RUN("sched_syscall");
+    TEST_RUN("sched_syscall");
 
-	self = L4_Myself();
-	result = L4_Set_Priority(self, 100);
+    self = L4_Myself();
+    result = L4_Set_Priority(self, 100);
 
-	if (result != L4_SCHEDRESULT_ERROR) {
-		TEST_PASS("sched_syscall");
-	} else {
-		/* Policy denial is acceptable - syscall path works */
-		printf("Note: priority 100 denied by policy\n");
-		TEST_PASS("sched_syscall");
-	}
+    if (result != L4_SCHEDRESULT_ERROR) {
+        TEST_PASS("sched_syscall");
+    } else {
+        /* Policy denial is acceptable - syscall path works */
+        printf("Note: priority 100 denied by policy\n");
+        TEST_PASS("sched_syscall");
+    }
 }
diff --git a/user/apps/tests/test-thread.c b/user/apps/tests/test-thread.c
index fa19067b..06008ade 100644
--- a/user/apps/tests/test-thread.c
+++ b/user/apps/tests/test-thread.c
@@ -3,10 +3,10 @@
  * found in the LICENSE file.
  */
 
-#include <l4/types.h>
-#include <l4/thread.h>
-#include <l4/pager.h>
 #include <l4/ipc.h>
+#include <l4/pager.h>
+#include <l4/thread.h>
+#include <l4/types.h>
 #include <l4io.h>
 
 #include "tests.h"
@@ -21,10 +21,10 @@ __USER_BSS static volatile L4_Word_t worker_tid_raw;
 __USER_TEXT
 static void *worker_thread(void *arg)
 {
-	/* Record our thread ID */
-	worker_tid_raw = L4_Myself().raw;
-	worker_executed = 1;
-	return NULL;
+    /* Record our thread ID */
+    worker_tid_raw = L4_Myself().raw;
+    worker_executed = 1;
+    return NULL;
 }
 
 /*
@@ -33,20 +33,20 @@ static void *worker_thread(void *arg)
 __USER_TEXT
 void test_thread_self(void)
 {
-	L4_ThreadId_t my_tid;
+    L4_ThreadId_t my_tid;
 
-	TEST_RUN("thread_self");
+    TEST_RUN("thread_self");
 
-	my_tid = L4_Myself();
+    my_tid = L4_Myself();
 
-	/* Thread ID should be non-zero and not nilthread */
-	if (!L4_IsNilThread(my_tid)) {
-		TEST_PASS("thread_self");
-	} else {
-		printf("L4_Myself() returned invalid TID: 0x%lx\n",
-		       (unsigned long)my_tid.raw);
-		TEST_FAIL("thread_self");
-	}
+    /* Thread ID should be non-zero and not nilthread */
+    if (!L4_IsNilThread(my_tid)) {
+        TEST_PASS("thread_self");
+    } else {
+        printf("L4_Myself() returned invalid TID: 0x%lx\n",
+               (unsigned long) my_tid.raw);
+        TEST_FAIL("thread_self");
+    }
 }
 
 /*
@@ -55,21 +55,20 @@ void test_thread_self(void)
 __USER_TEXT
 void test_thread_global_id(void)
 {
-	L4_ThreadId_t my_tid, global_tid;
+    L4_ThreadId_t my_tid, global_tid;
 
-	TEST_RUN("thread_global_id");
+    TEST_RUN("thread_global_id");
 
-	my_tid = L4_Myself();
-	global_tid = L4_MyGlobalId();
+    my_tid = L4_Myself();
+    global_tid = L4_MyGlobalId();
 
-	if (my_tid.raw == global_tid.raw) {
-		TEST_PASS("thread_global_id");
-	} else {
-		printf("L4_Myself()=0x%lx != L4_MyGlobalId()=0x%lx\n",
-		       (unsigned long)my_tid.raw,
-		       (unsigned long)global_tid.raw);
-		TEST_FAIL("thread_global_id");
-	}
+    if (my_tid.raw == global_tid.raw) {
+        TEST_PASS("thread_global_id");
+    } else {
+        printf("L4_Myself()=0x%lx != L4_MyGlobalId()=0x%lx\n",
+               (unsigned long) my_tid.raw, (unsigned long) global_tid.raw);
+        TEST_FAIL("thread_global_id");
+    }
 }
 
 /*
@@ -78,19 +77,19 @@ void test_thread_global_id(void)
 __USER_TEXT
 void test_thread_pager(void)
 {
-	L4_ThreadId_t pager_tid;
+    L4_ThreadId_t pager_tid;
 
-	TEST_RUN("thread_pager");
+    TEST_RUN("thread_pager");
 
-	pager_tid = L4_Pager();
+    pager_tid = L4_Pager();
 
-	/* Pager should be a valid thread (non-zero) */
-	if (pager_tid.raw != 0) {
-		TEST_PASS("thread_pager");
-	} else {
-		printf("L4_Pager() returned nil thread\n");
-		TEST_FAIL("thread_pager");
-	}
+    /* Pager should be a valid thread (non-zero) */
+    if (pager_tid.raw != 0) {
+        TEST_PASS("thread_pager");
+    } else {
+        printf("L4_Pager() returned nil thread\n");
+        TEST_FAIL("thread_pager");
+    }
 }
 
 /*
@@ -99,39 +98,38 @@ void test_thread_pager(void)
 __USER_TEXT
 void test_thread_create(void)
 {
-	L4_ThreadId_t worker_tid;
-	int timeout;
-
-	TEST_RUN("thread_create");
-
-	worker_executed = 0;
-	worker_tid_raw = 0;
-
-	/* Create worker thread via pager */
-	worker_tid = pager_create_thread();
-	if (worker_tid.raw == 0) {
-		printf("Failed to create worker thread\n");
-		TEST_FAIL("thread_create");
-		return;
-	}
-
-	/* Start the worker */
-	pager_start_thread(worker_tid, worker_thread, NULL);
-
-	/* Wait for worker to execute */
-	timeout = 50;
-	while (!worker_executed && timeout > 0) {
-		L4_Sleep(L4_TimePeriod(10000)); /* 10ms */
-		timeout--;
-	}
-
-	/* Verify worker executed and TID matches what we created */
-	if (worker_executed && worker_tid_raw == worker_tid.raw) {
-		TEST_PASS("thread_create");
-	} else {
-		printf("Worker TID mismatch: created=0x%lx reported=0x%lx\n",
-		       (unsigned long)worker_tid.raw,
-		       (unsigned long)worker_tid_raw);
-		TEST_FAIL("thread_create");
-	}
+    L4_ThreadId_t worker_tid;
+    int timeout;
+
+    TEST_RUN("thread_create");
+
+    worker_executed = 0;
+    worker_tid_raw = 0;
+
+    /* Create worker thread via pager */
+    worker_tid = pager_create_thread();
+    if (worker_tid.raw == 0) {
+        printf("Failed to create worker thread\n");
+        TEST_FAIL("thread_create");
+        return;
+    }
+
+    /* Start the worker */
+    pager_start_thread(worker_tid, worker_thread, NULL);
+
+    /* Wait for worker to execute */
+    timeout = 50;
+    while (!worker_executed && timeout > 0) {
+        L4_Sleep(L4_TimePeriod(10000)); /* 10ms */
+        timeout--;
+    }
+
+    /* Verify worker executed and TID matches what we created */
+    if (worker_executed && worker_tid_raw == worker_tid.raw) {
+        TEST_PASS("thread_create");
+    } else {
+        printf("Worker TID mismatch: created=0x%lx reported=0x%lx\n",
+               (unsigned long) worker_tid.raw, (unsigned long) worker_tid_raw);
+        TEST_FAIL("thread_create");
+    }
 }
diff --git a/user/apps/tests/test-timer.c b/user/apps/tests/test-timer.c
index 75185dee..1b038f1f 100644
--- a/user/apps/tests/test-timer.c
+++ b/user/apps/tests/test-timer.c
@@ -14,20 +14,20 @@
 __USER_TEXT
 void test_timer_period(void)
 {
-	L4_Time_t time;
+    L4_Time_t time;
 
-	TEST_RUN("timer_period");
+    TEST_RUN("timer_period");
 
-	/* Create a 1ms time period */
-	time = L4_TimePeriod(1000);
+    /* Create a 1ms time period */
+    time = L4_TimePeriod(1000);
 
-	/* Time value should be non-zero */
-	if (time.raw != 0) {
-		TEST_PASS("timer_period");
-	} else {
-		printf("L4_TimePeriod(1000) returned zero\n");
-		TEST_FAIL("timer_period");
-	}
+    /* Time value should be non-zero */
+    if (time.raw != 0) {
+        TEST_PASS("timer_period");
+    } else {
+        printf("L4_TimePeriod(1000) returned zero\n");
+        TEST_FAIL("timer_period");
+    }
 }
 
 /*
@@ -37,11 +37,11 @@ void test_timer_period(void)
 __USER_TEXT
 void test_timer_sleep(void)
 {
-	TEST_RUN("timer_sleep");
+    TEST_RUN("timer_sleep");
 
-	/* Just verify sleep returns without hanging */
-	L4_Sleep(L4_TimePeriod(1000)); /* 1ms */
+    /* Just verify sleep returns without hanging */
+    L4_Sleep(L4_TimePeriod(1000)); /* 1ms */
 
-	/* If we get here, sleep works */
-	TEST_PASS("timer_sleep");
+    /* If we get here, sleep works */
+    TEST_PASS("timer_sleep");
 }
diff --git a/user/apps/tests/tests.h b/user/apps/tests/tests.h
index e1ec64b5..8089de06 100644
--- a/user/apps/tests/tests.h
+++ b/user/apps/tests/tests.h
@@ -25,8 +25,8 @@
 
 /* Test context structure */
 typedef struct {
-	int passed;
-	int failed;
+    int passed;
+    int failed;
 } test_context_t;
 
 /* Global test context - defined in main.c */
@@ -42,49 +42,47 @@ extern test_context_t test_ctx;
  */
 
 /* ANSI color codes */
-#define ANSI_GREEN  "\033[32m"
-#define ANSI_RED    "\033[31m"
-#define ANSI_RESET  "\033[0m"
-
-#define TEST_START(suite) \
-	do { \
-		printf("[TEST:START] %s\n", suite); \
-		printf("=== Running %s ===\n", suite); \
-	} while (0)
-
-#define TEST_RUN(name) \
-	printf("[TEST:RUN] %s\n", name)
-
-#define TEST_PASS(name) \
-	do { \
-		test_ctx.passed++; \
-		printf("[TEST:PASS] %s\n", name); \
-		printf("Test %-40s[ " ANSI_GREEN "OK" ANSI_RESET " ]\n", name); \
-	} while (0)
-
-#define TEST_FAIL(name) \
-	do { \
-		test_ctx.failed++; \
-		printf("[TEST:FAIL] %s\n", name); \
-		printf("Test %-40s[" ANSI_RED "FAIL" ANSI_RESET "]\n", name); \
-	} while (0)
-
-#define TEST_SUMMARY() \
-	printf("[TEST:SUMMARY] passed=%d failed=%d\n", \
-	       test_ctx.passed, test_ctx.failed)
-
-#define TEST_EXIT(code) \
-	printf("[TEST:EXIT] %d\n", code)
+#define ANSI_GREEN "\033[32m"
+#define ANSI_RED "\033[31m"
+#define ANSI_RESET "\033[0m"
+
+#define TEST_START(suite)                      \
+    do {                                       \
+        printf("[TEST:START] %s\n", suite);    \
+        printf("=== Running %s ===\n", suite); \
+    } while (0)
+
+#define TEST_RUN(name) printf("[TEST:RUN] %s\n", name)
+
+#define TEST_PASS(name)                                                 \
+    do {                                                                \
+        test_ctx.passed++;                                              \
+        printf("[TEST:PASS] %s\n", name);                               \
+        printf("Test %-40s[ " ANSI_GREEN "OK" ANSI_RESET " ]\n", name); \
+    } while (0)
+
+#define TEST_FAIL(name)                                               \
+    do {                                                              \
+        test_ctx.failed++;                                            \
+        printf("[TEST:FAIL] %s\n", name);                             \
+        printf("Test %-40s[" ANSI_RED "FAIL" ANSI_RESET "]\n", name); \
+    } while (0)
+
+#define TEST_SUMMARY()                                              \
+    printf("[TEST:SUMMARY] passed=%d failed=%d\n", test_ctx.passed, \
+           test_ctx.failed)
+
+#define TEST_EXIT(code) printf("[TEST:EXIT] %d\n", code)
 
 /* Test assertion - non-blocking unlike L4_KDB_Enter */
 #define TEST_ASSERT(name, condition) \
-	do { \
-		if (condition) { \
-			TEST_PASS(name); \
-		} else { \
-			TEST_FAIL(name); \
-		} \
-	} while (0)
+    do {                             \
+        if (condition) {             \
+            TEST_PASS(name);         \
+        } else {                     \
+            TEST_FAIL(name);         \
+        }                            \
+    } while (0)
 
 /* Test function declarations */
 
@@ -129,7 +127,7 @@ void test_sched_ipc_priority_boost(void);
 void test_sched_syscall(void);
 
 /* Fault test type constants */
-#define FAULT_MPU    1
+#define FAULT_MPU 1
 #define FAULT_CANARY 2
 
 /* Fault tests (test-fault.c) - requires FAULT_TYPE define */
diff --git a/user/include/l4/ipc.h b/user/include/l4/ipc.h
index b88fd818..28fbc30b 100644
--- a/user/include/l4/ipc.h
+++ b/user/include/l4/ipc.h
@@ -17,37 +17,37 @@
  */
 L4_INLINE L4_Bool_t L4_IpcSucceeded(L4_MsgTag_t t)
 {
-	return (t.X.flags & 0x8) == 0;
+    return (t.X.flags & 0x8) == 0;
 }
 
 L4_INLINE L4_Bool_t L4_IpcFailed(L4_MsgTag_t t)
 {
-	return (t.X.flags & 0x8) != 0;
+    return (t.X.flags & 0x8) != 0;
 }
 
 L4_INLINE L4_Bool_t L4_IpcPropagated(L4_MsgTag_t t)
 {
-	return (t.X.flags & 0x1) != 0;
+    return (t.X.flags & 0x1) != 0;
 }
 
 L4_INLINE L4_Bool_t L4_IpcRedirected(L4_MsgTag_t t)
 {
-	return (t.X.flags & 0x2) != 0;
+    return (t.X.flags & 0x2) != 0;
 }
 
 L4_INLINE L4_Bool_t L4_IpcXcpu(L4_MsgTag_t t)
 {
-	return (t.X.flags & 0x4) != 0;
+    return (t.X.flags & 0x4) != 0;
 }
 
-L4_INLINE void L4_Set_Propagation(L4_MsgTag_t * t)
+L4_INLINE void L4_Set_Propagation(L4_MsgTag_t *t)
 {
-	t->X.flags = 1;
+    t->X.flags = 1;
 }
 
 L4_INLINE L4_Word_t L4_Timeouts(L4_Time_t SndTimeout, L4_Time_t RcvTimeout)
 {
-	return (SndTimeout.raw << 16) + (RcvTimeout.raw);
+    return (SndTimeout.raw << 16) + (RcvTimeout.raw);
 }
 
 /*
@@ -76,137 +76,124 @@ L4_INLINE L4_Word_t L4_Timeouts(L4_Time_t SndTimeout, L4_Time_t RcvTimeout)
  *   L4_Lreply_Wait		(to, &from)
  *
  */
-L4_INLINE L4_MsgTag_t L4_Call_Timeouts(
-		L4_ThreadId_t to,
-		L4_Time_t SndTimeout,
-		L4_Time_t RcvTimeout)
+L4_INLINE L4_MsgTag_t L4_Call_Timeouts(L4_ThreadId_t to,
+                                       L4_Time_t SndTimeout,
+                                       L4_Time_t RcvTimeout)
 {
-	L4_ThreadId_t dummy;
-	return L4_Ipc(to, to, L4_Timeouts (SndTimeout, RcvTimeout),
-			&dummy);
+    L4_ThreadId_t dummy;
+    return L4_Ipc(to, to, L4_Timeouts(SndTimeout, RcvTimeout), &dummy);
 }
 
 #if defined(__cplusplus)
-L4_INLINE L4_MsgTag_t L4_Call(
-		L4_ThreadId_t to,
-		L4_Time_t SndTimeout,
-		L4_Time_t RcvTimeout)
+L4_INLINE L4_MsgTag_t L4_Call(L4_ThreadId_t to,
+                              L4_Time_t SndTimeout,
+                              L4_Time_t RcvTimeout)
 {
-	return L4_Call_Timeouts (to, SndTimeout, RcvTimeout);
+    return L4_Call_Timeouts(to, SndTimeout, RcvTimeout);
 }
 #endif
 
 L4_INLINE L4_MsgTag_t L4_Call(L4_ThreadId_t to)
 {
-	return L4_Call_Timeouts(to, L4_Never, L4_Never);
+    return L4_Call_Timeouts(to, L4_Never, L4_Never);
 }
 
-L4_INLINE L4_MsgTag_t L4_Send_Timeout(
-		L4_ThreadId_t to, L4_Time_t SndTimeout)
+L4_INLINE L4_MsgTag_t L4_Send_Timeout(L4_ThreadId_t to, L4_Time_t SndTimeout)
 {
-	return L4_Ipc (to, L4_nilthread,
-			(L4_Word_t) SndTimeout.raw,
-			(L4_ThreadId_t *) 0);
+    return L4_Ipc(to, L4_nilthread, (L4_Word_t) SndTimeout.raw,
+                  (L4_ThreadId_t *) 0);
 }
 
 #if defined(__cplusplus)
 L4_INLINE L4_MsgTag_t L4_Send(L4_ThreadId_t to, L4_Time_t SndTimeout)
 {
-	return L4_Send_Timeout(to, SndTimeout);
+    return L4_Send_Timeout(to, SndTimeout);
 }
 #endif
 
 L4_INLINE L4_MsgTag_t L4_Send(L4_ThreadId_t to)
 {
-	return L4_Send_Timeout(to, L4_Never);
+    return L4_Send_Timeout(to, L4_Never);
 }
 
 L4_INLINE L4_MsgTag_t L4_Reply(L4_ThreadId_t to)
 {
-	return L4_Send_Timeout(to, L4_ZeroTime);
+    return L4_Send_Timeout(to, L4_ZeroTime);
 }
 
-L4_INLINE L4_MsgTag_t L4_Receive_Timeout(
-		L4_ThreadId_t from,
-		L4_Time_t RcvTimeout)
+L4_INLINE L4_MsgTag_t L4_Receive_Timeout(L4_ThreadId_t from,
+                                         L4_Time_t RcvTimeout)
 {
-	L4_ThreadId_t dummy;
-	return L4_Ipc(L4_nilthread, from, (L4_Word_t) RcvTimeout.raw, &dummy);
+    L4_ThreadId_t dummy;
+    return L4_Ipc(L4_nilthread, from, (L4_Word_t) RcvTimeout.raw, &dummy);
 }
 
 #if defined(__cplusplus)
 L4_INLINE L4_MsgTag_t L4_Receive(L4_ThreadId_t from, L4_Time_t RcvTimeout)
 {
-	return L4_Receive_Timeout(from, RcvTimeout);
+    return L4_Receive_Timeout(from, RcvTimeout);
 }
 #endif
 
 L4_INLINE L4_MsgTag_t L4_Receive(L4_ThreadId_t from)
 {
-	return L4_Receive_Timeout(from, L4_Never);
+    return L4_Receive_Timeout(from, L4_Never);
 }
 
-L4_INLINE L4_MsgTag_t L4_Wait_Timeout(
-		L4_Time_t RcvTimeout,
-		L4_ThreadId_t *from)
+L4_INLINE L4_MsgTag_t L4_Wait_Timeout(L4_Time_t RcvTimeout, L4_ThreadId_t *from)
 {
-	return L4_Ipc(L4_nilthread, L4_anythread,
-			(L4_Word_t) RcvTimeout.raw, from);
+    return L4_Ipc(L4_nilthread, L4_anythread, (L4_Word_t) RcvTimeout.raw, from);
 }
 
 #if defined(__cplusplus)
 L4_INLINE L4_MsgTag_t L4_Wait(L4_Time_t RcvTimeout, L4_ThreadId_t *from)
 {
-	return L4_Wait_Timeout(RcvTimeout, from);
+    return L4_Wait_Timeout(RcvTimeout, from);
 }
 #endif
 
 L4_INLINE L4_MsgTag_t L4_Wait(L4_ThreadId_t *from)
 {
-	return L4_Wait_Timeout(L4_Never, from);
+    return L4_Wait_Timeout(L4_Never, from);
 }
 
-L4_INLINE L4_MsgTag_t L4_ReplyWait_Timeout(
-		L4_ThreadId_t to,
-		L4_Time_t RcvTimeout,
-		L4_ThreadId_t *from)
+L4_INLINE L4_MsgTag_t L4_ReplyWait_Timeout(L4_ThreadId_t to,
+                                           L4_Time_t RcvTimeout,
+                                           L4_ThreadId_t *from)
 {
-	return L4_Ipc(to, L4_anythread,
-			L4_Timeouts(L4_ZeroTime, RcvTimeout),
-			from);
+    return L4_Ipc(to, L4_anythread, L4_Timeouts(L4_ZeroTime, RcvTimeout), from);
 }
 
 #if defined(__cplusplus)
-L4_INLINE L4_MsgTag_t L4_ReplyWait(
-		L4_ThreadId_t to,
-		L4_Time_t RcvTimeout,
-		L4_ThreadId_t *from)
+L4_INLINE L4_MsgTag_t L4_ReplyWait(L4_ThreadId_t to,
+                                   L4_Time_t RcvTimeout,
+                                   L4_ThreadId_t *from)
 {
-	return L4_ReplyWait_Timeout(to, RcvTimeout, from);
+    return L4_ReplyWait_Timeout(to, RcvTimeout, from);
 }
 #endif
 
 
 L4_INLINE L4_MsgTag_t L4_ReplyWait(L4_ThreadId_t to, L4_ThreadId_t *from)
 {
-	return L4_ReplyWait_Timeout(to, L4_Never, from);
+    return L4_ReplyWait_Timeout(to, L4_Never, from);
 }
 
 L4_INLINE void L4_Sleep(L4_Time_t t)
 {
-	L4_Ipc(L4_nilthread, L4_nilthread, (L4_Word_t) t.raw, NULL);
+    L4_Ipc(L4_nilthread, L4_nilthread, (L4_Word_t) t.raw, NULL);
 }
 
 L4_INLINE L4_MsgTag_t L4_Lcall(L4_ThreadId_t to)
 {
-	L4_ThreadId_t dummy;
-	return L4_Lipc(to, to, L4_Timeouts(L4_Never, L4_Never), &dummy);
+    L4_ThreadId_t dummy;
+    return L4_Lipc(to, to, L4_Timeouts(L4_Never, L4_Never), &dummy);
 }
 
 L4_INLINE L4_MsgTag_t L4_LreplyWait(L4_ThreadId_t to, L4_ThreadId_t *from)
 {
-	return L4_Lipc(to, L4_anylocalthread,
-			L4_Timeouts(L4_ZeroTime, L4_Never), from);
+    return L4_Lipc(to, L4_anylocalthread, L4_Timeouts(L4_ZeroTime, L4_Never),
+                   from);
 }
 
 #endif /* !__L4__IPC_H__ */
diff --git a/user/include/l4/kdebug.h b/user/include/l4/kdebug.h
index 2656ac88..0a607643 100644
--- a/user/include/l4/kdebug.h
+++ b/user/include/l4/kdebug.h
@@ -12,7 +12,7 @@
 /*
  * Compatibility with old naming scheme.
  */
-#define enter_kdebug(x)		L4_KDB_Enter(x)
-#define kd_inchar()		L4_KDB_ReadChar_Blocked()
+#define enter_kdebug(x) L4_KDB_Enter(x)
+#define kd_inchar() L4_KDB_ReadChar_Blocked()
 
 #endif /* !__L4__KDEBUG_H__ */
diff --git a/user/include/l4/kip.h b/user/include/l4/kip.h
index 6c98d991..98acc061 100644
--- a/user/include/l4/kip.h
+++ b/user/include/l4/kip.h
@@ -7,231 +7,212 @@
 #ifndef __L4__KERNEL_IFACE_PAGE_H__
 #define __L4__KERNEL_IFACE_PAGE_H__
 
-#include <l4/types.h>
 #include <l4/kip_types.h>
+#include <l4/types.h>
 #include __L4_INC_ARCH(syscalls.h)
 
 #if defined(L4_64BIT)
-# define __PAD32	__pad32:32
-# define __PLUS32	+ 32
+#define __PAD32 \
+    __pad32:    \
+    32
+#define __PLUS32 +32
 #else
-# define __PAD32	:0
-# define __PLUS32
+#define __PAD32	:0
+#define __PLUS32
 #endif
 
 typedef union {
-	L4_Word_t raw;
-	struct {
-		L4_BITFIELD4(L4_Word_t,
-				__padding:16,
-				subid:8,
-				id:8,
-				__PAD32
-			    );
-	} x;
+    L4_Word_t raw;
+    struct {
+        L4_BITFIELD4(L4_Word_t, __padding : 16, subid : 8, id : 8, __PAD32);
+    } x;
 } L4_KernelId_t;
 
 typedef union {
-	L4_Word_t raw;
-	struct {
-		L4_BITFIELD4( L4_Word_t,
-				__padding:16,
-				subversion:8,
-				version:8,
-				__PAD32
-			    );
-	} x;
+    L4_Word_t raw;
+    struct {
+        L4_BITFIELD4(L4_Word_t,
+                     __padding : 16,
+                     subversion : 8,
+                     version : 8,
+                     __PAD32);
+    } x;
 } L4_ApiVersion_t;
 
 typedef union {
-	L4_Word_t raw;
-	struct {
-		L4_BITFIELD3(L4_Word_t,
-				ee:2,
-				ww:2,
-				__padding:28 __PLUS32
-			    );
-	} x;
+    L4_Word_t raw;
+    struct {
+        L4_BITFIELD3(L4_Word_t, ee : 2, ww : 2, __padding : 28 __PLUS32);
+    } x;
 } L4_ApiFlags_t;
 
 typedef struct {
-	L4_BITFIELD2(L4_Word_t,
-			MemDescPtr:L4_BITS_PER_WORD / 2,
-			n:L4_BITS_PER_WORD / 2
-		    );
+    L4_BITFIELD2(L4_Word_t,
+                 MemDescPtr : L4_BITS_PER_WORD / 2,
+                 n : L4_BITS_PER_WORD / 2);
 } L4_MemoryInfo_t;
 
 typedef struct {
-	L4_Word_t magic;
-	L4_ApiVersion_t	ApiVersion;
-	L4_ApiFlags_t ApiFlags;
-	L4_Word_t KernelVerPtr;
-
-	/* 0x10 */
-	L4_Word_t __padding10[17];
-	L4_MemoryInfo_t	MemoryInfo;
-	L4_Word_t __padding58[2];
-
-	/* 0x60 */
-	struct {
-		L4_Word_t low;
-		L4_Word_t high;
-	} MainMem;
-
-	/* 0x68 */
-	struct {
-		L4_Word_t low;
-		L4_Word_t high;
-	} ReservedMem[2];
-
-	/* 0x78 */
-	struct {
-		L4_Word_t low;
-		L4_Word_t high;
-	} DedicatedMem[5];
-
-	/* 0xA0 */
-	L4_Word_t __paddingA0[2];
-
-	union {
-		L4_Word_t raw;
-		struct {
-			L4_BITFIELD4(L4_Word_t,
-					m:10,
-					a:6,
-					s:6,
-					__padding:10 __PLUS32
-				    );
-		} X;
-	} UtcbAreaInfo;
-
-	union {
-		L4_Word_t raw;
-		struct {
-			L4_BITFIELD2(L4_Word_t,
-					s:6,
-					__padding:26 __PLUS32
-				    );
-		} X;
-	} KipAreaInfo;
-
-	/* 0xB0 */
-	L4_Word_t __paddingB0[2];
-	L4_Word_t BootInfo;
-	L4_Word_t ProcDescPtr;
-
-	/* 0xC0 */
-	union {
-		L4_Word_t raw;
-		struct {
-			L4_BITFIELD3(L4_Word_t,
-					ReadPrecision:16,
-					SchedulePrecision:16,
-					__PAD32
-				    );
-		} X;
-	} ClockInfo;
-
-	union {
-		L4_Word_t raw;
-		struct {
-			L4_BITFIELD4(L4_Word_t,
-					t:8,
-					SystemBase:12,
-					UserBase:12,
-					__PAD32
-				    );
-		} X;
-	} ThreadInfo;
-
-	union {
-		L4_Word_t raw;
-		struct {
-			L4_BITFIELD3(L4_Word_t,
-					rwx:3,
-					__padding:7,
-					page_size_mask:22 __PLUS32
-				    );
-		} X;
-	} PageInfo;
-
-	union {
-		L4_Word_t raw;
-		struct {
-			L4_BITFIELD3(L4_Word_t,
-					processors:16,
-					__pading:12 __PLUS32,
-					s:4
-				    );
-		} X;
-	} ProcessorInfo;
-
-	/* 0xD0 */
-	L4_Word_t SpaceControl;
-	L4_Word_t ThreadControl;
-	L4_Word_t ProcessorControl;
-	L4_Word_t MemoryControl;
-
-	/* 0xE0 */
-	L4_Word_t Ipc;
-	L4_Word_t Lipc;
-	L4_Word_t Unmap;
-	L4_Word_t ExchangeRegisters;
-
-	/* 0xF0 */
-	L4_Word_t SystemClock;
-	L4_Word_t ThreadSwitch;
-	L4_Word_t Schedule;
-	L4_Word_t __paddingF0;
-
-	/* 0x100 */
-	L4_Word_t __padding100[4];
-
-	/* 0x110 */
-	L4_Word_t ArchSyscall0;
-	L4_Word_t ArchSyscall1;
-	L4_Word_t ArchSyscall2;
-	L4_Word_t ArchSyscall3;
+    L4_Word_t magic;
+    L4_ApiVersion_t ApiVersion;
+    L4_ApiFlags_t ApiFlags;
+    L4_Word_t KernelVerPtr;
+
+    /* 0x10 */
+    L4_Word_t __padding10[17];
+    L4_MemoryInfo_t MemoryInfo;
+    L4_Word_t __padding58[2];
+
+    /* 0x60 */
+    struct {
+        L4_Word_t low;
+        L4_Word_t high;
+    } MainMem;
+
+    /* 0x68 */
+    struct {
+        L4_Word_t low;
+        L4_Word_t high;
+    } ReservedMem[2];
+
+    /* 0x78 */
+    struct {
+        L4_Word_t low;
+        L4_Word_t high;
+    } DedicatedMem[5];
+
+    /* 0xA0 */
+    L4_Word_t __paddingA0[2];
+
+    union {
+        L4_Word_t raw;
+        struct {
+            L4_BITFIELD4(L4_Word_t,
+                         m : 10,
+                         a : 6,
+                         s : 6,
+                         __padding : 10 __PLUS32);
+        } X;
+    } UtcbAreaInfo;
+
+    union {
+        L4_Word_t raw;
+        struct {
+            L4_BITFIELD2(L4_Word_t, s : 6, __padding : 26 __PLUS32);
+        } X;
+    } KipAreaInfo;
+
+    /* 0xB0 */
+    L4_Word_t __paddingB0[2];
+    L4_Word_t BootInfo;
+    L4_Word_t ProcDescPtr;
+
+    /* 0xC0 */
+    union {
+        L4_Word_t raw;
+        struct {
+            L4_BITFIELD3(L4_Word_t,
+                         ReadPrecision : 16,
+                         SchedulePrecision : 16,
+                         __PAD32);
+        } X;
+    } ClockInfo;
+
+    union {
+        L4_Word_t raw;
+        struct {
+            L4_BITFIELD4(L4_Word_t,
+                         t : 8,
+                         SystemBase : 12,
+                         UserBase : 12,
+                         __PAD32);
+        } X;
+    } ThreadInfo;
+
+    union {
+        L4_Word_t raw;
+        struct {
+            L4_BITFIELD3(L4_Word_t,
+                         rwx : 3,
+                         __padding : 7,
+                         page_size_mask : 22 __PLUS32);
+        } X;
+    } PageInfo;
+
+    union {
+        L4_Word_t raw;
+        struct {
+            L4_BITFIELD3(L4_Word_t,
+                         processors : 16,
+                         __pading : 12 __PLUS32,
+                         s : 4);
+        } X;
+    } ProcessorInfo;
+
+    /* 0xD0 */
+    L4_Word_t SpaceControl;
+    L4_Word_t ThreadControl;
+    L4_Word_t ProcessorControl;
+    L4_Word_t MemoryControl;
+
+    /* 0xE0 */
+    L4_Word_t Ipc;
+    L4_Word_t Lipc;
+    L4_Word_t Unmap;
+    L4_Word_t ExchangeRegisters;
+
+    /* 0xF0 */
+    L4_Word_t SystemClock;
+    L4_Word_t ThreadSwitch;
+    L4_Word_t Schedule;
+    L4_Word_t __paddingF0;
+
+    /* 0x100 */
+    L4_Word_t __padding100[4];
+
+    /* 0x110 */
+    L4_Word_t ArchSyscall0;
+    L4_Word_t ArchSyscall1;
+    L4_Word_t ArchSyscall2;
+    L4_Word_t ArchSyscall3;
 } L4_KernelInterfacePage_t;
 
 typedef union {
-	L4_Word_t raw[4];
-	struct {
-		L4_Word_t ExternalFreq;
-		L4_Word_t InternalFreq;
-		L4_Word_t __padding[2];
-	} X;
+    L4_Word_t raw[4];
+    struct {
+        L4_Word_t ExternalFreq;
+        L4_Word_t InternalFreq;
+        L4_Word_t __padding[2];
+    } X;
 } L4_ProcDesc_t;
 
 typedef struct {
-	L4_KernelId_t KernelId;
-
-	union {
-		L4_Word_t raw;
-		struct {
-			L4_BITFIELD4(L4_Word_t,
-					day:5,
-					month:4,
-					year:7,
-					__padding:16 __PLUS32
-				    );
-		} X;
-	} KernelGenDate;
-
-	union {
-		L4_Word_t raw;
-		struct {
-			L4_BITFIELD4(L4_Word_t,
-					subsubver:16,
-					subver:8,
-					ver:8,
-					__PAD32
-				    );
-		} X;
-	} KernelVer;
-
-	L4_Word_t Supplier;
-	char VersionString[0];
+    L4_KernelId_t KernelId;
+
+    union {
+        L4_Word_t raw;
+        struct {
+            L4_BITFIELD4(L4_Word_t,
+                         day : 5,
+                         month : 4,
+                         year : 7,
+                         __padding : 16 __PLUS32);
+        } X;
+    } KernelGenDate;
+
+    union {
+        L4_Word_t raw;
+        struct {
+            L4_BITFIELD4(L4_Word_t,
+                         subsubver : 16,
+                         subver : 8,
+                         ver : 8,
+                         __PAD32);
+        } X;
+    } KernelVer;
+
+    L4_Word_t Supplier;
+    char VersionString[0];
 } L4_KernelDesc_t;
 
 /*
@@ -239,55 +220,55 @@ typedef struct {
  */
 #ifndef L4_MAGIC
 #if defined(L4_BIG_ENDIAN)
-# define L4_MAGIC	(('L' << 24) + ('4' << 16) + (230 << 8) + 'K')
+#define L4_MAGIC (('L' << 24) + ('4' << 16) + (230 << 8) + 'K')
 #else
-# define L4_MAGIC	(('K' << 24) + (230 << 16) + ('4' << 8) + 'L')
+#define L4_MAGIC (('K' << 24) + (230 << 16) + ('4' << 8) + 'L')
 #endif
 #endif /* L4_MAGIC  */
 
 /* Values for API version field. */
-#define L4_APIVERSION_2		(0x02)
-#define L4_APIVERSION_4		(0x04)
-#define L4_APIVERSION_X0	(0x83)
-#define L4_APIVERSION_X1	(0x83)
-#define L4_APIVERSION_X2	(0x84)
-#define L4_APIVERSION_L4SEC	(0x85)
-#define L4_APIVERSION_N1	(0x86)
-#define L4_APISUBVERSION_X0	(0x80)
-#define L4_APISUBVERSION_X1	(0x81)
-#define L4_APIVERSION_OKL	(0xA0)
+#define L4_APIVERSION_2 (0x02)
+#define L4_APIVERSION_4 (0x04)
+#define L4_APIVERSION_X0 (0x83)
+#define L4_APIVERSION_X1 (0x83)
+#define L4_APIVERSION_X2 (0x84)
+#define L4_APIVERSION_L4SEC (0x85)
+#define L4_APIVERSION_N1 (0x86)
+#define L4_APISUBVERSION_X0 (0x80)
+#define L4_APISUBVERSION_X1 (0x81)
+#define L4_APIVERSION_OKL (0xA0)
 
 /* Values for API flags field. */
-#define L4_APIFLAG_LE		(0x00)
-#define L4_APIFLAG_BE		(0x01)
-#define L4_APIFLAG_32BIT	(0x00)
-#define L4_APIFLAG_64BIT	(0x01)
+#define L4_APIFLAG_LE (0x00)
+#define L4_APIFLAG_BE (0x01)
+#define L4_APIFLAG_32BIT (0x00)
+#define L4_APIFLAG_64BIT (0x01)
 
 /* Values for kernel id/subid field. */
-#define L4_KID_L4_486		((0 << 8) + 1)
-#define L4_KID_L4_PENTIUM	((0 << 8) + 2)
-#define L4_KID_L4_X86		((0 << 8) + 3)
-#define L4_KID_L4_MIPS		((1 << 8) + 1)
-#define L4_KID_L4_ALPHA		((2 << 8) + 1)
-#define L4_KID_FIASCO		((3 << 8) + 1)
-#define L4_KID_L4KA_HAZELNUT	((4 << 8) + 1)
-#define L4_KID_L4KA_PISTACHIO	((4 << 8) + 2)
-#define L4_KID_L4KA_STRAWBERRY	((4 << 8) + 3)
-#define L4_KID_NICTA_PISTACHIO	((5 << 8) + 1)
+#define L4_KID_L4_486 ((0 << 8) + 1)
+#define L4_KID_L4_PENTIUM ((0 << 8) + 2)
+#define L4_KID_L4_X86 ((0 << 8) + 3)
+#define L4_KID_L4_MIPS ((1 << 8) + 1)
+#define L4_KID_L4_ALPHA ((2 << 8) + 1)
+#define L4_KID_FIASCO ((3 << 8) + 1)
+#define L4_KID_L4KA_HAZELNUT ((4 << 8) + 1)
+#define L4_KID_L4KA_PISTACHIO ((4 << 8) + 2)
+#define L4_KID_L4KA_STRAWBERRY ((4 << 8) + 3)
+#define L4_KID_NICTA_PISTACHIO ((5 << 8) + 1)
 
 /* Values for kernel Supplier field. */
 #if defined(L4_BIG_ENDIAN)
-# define L4_SUPL_GMD	(('G' << 24) + ('M' << 16) + ('D' << 8) + ' ')
-# define L4_SUPL_IBM	(('I' << 24) + ('B' << 16) + ('M' << 8) + ' ')
-# define L4_SUPL_UNSW	(('U' << 24) + ('N' << 16) + ('S' << 8) + 'W')
-# define L4_SUPL_UKA	(('U' << 24) + ('K' << 16) + ('a' << 8) + ' ')
-# define L4_SUPL_NICTA	(('N' << 24) + ('I' << 16) + ('C' << 8) + 'T')
+#define L4_SUPL_GMD (('G' << 24) + ('M' << 16) + ('D' << 8) + ' ')
+#define L4_SUPL_IBM (('I' << 24) + ('B' << 16) + ('M' << 8) + ' ')
+#define L4_SUPL_UNSW (('U' << 24) + ('N' << 16) + ('S' << 8) + 'W')
+#define L4_SUPL_UKA (('U' << 24) + ('K' << 16) + ('a' << 8) + ' ')
+#define L4_SUPL_NICTA (('N' << 24) + ('I' << 16) + ('C' << 8) + 'T')
 #else
-# define L4_SUPL_GMD	((' ' << 24) + ('D' << 16) + ('M' << 8) + 'G')
-# define L4_SUPL_IBM	((' ' << 24) + ('M' << 16) + ('B' << 8) + 'I')
-# define L4_SUPL_UNSW	(('W' << 24) + ('S' << 16) + ('N' << 8) + 'U')
-# define L4_SUPL_UKA	((' ' << 24) + ('a' << 16) + ('K' << 8) + 'U')
-# define L4_SUPL_NICTA	(('T' << 24) + ('C' << 16) + ('I' << 8) + 'N')
+#define L4_SUPL_GMD ((' ' << 24) + ('D' << 16) + ('M' << 8) + 'G')
+#define L4_SUPL_IBM ((' ' << 24) + ('M' << 16) + ('B' << 8) + 'I')
+#define L4_SUPL_UNSW (('W' << 24) + ('S' << 16) + ('N' << 8) + 'U')
+#define L4_SUPL_UKA ((' ' << 24) + ('a' << 16) + ('K' << 8) + 'U')
+#define L4_SUPL_NICTA (('T' << 24) + ('C' << 16) + ('I' << 8) + 'N')
 #endif
 
 /*
@@ -295,340 +276,331 @@ typedef struct {
  */
 L4_INLINE void *L4_GetKernelInterface(void)
 {
-	L4_ApiVersion_t version;
-	L4_ApiFlags_t flags;
-	L4_KernelId_t kernel_id;
-	return L4_KernelInterface(&version.raw, &flags.raw, &kernel_id.raw);
+    L4_ApiVersion_t version;
+    L4_ApiFlags_t flags;
+    L4_KernelId_t kernel_id;
+    return L4_KernelInterface(&version.raw, &flags.raw, &kernel_id.raw);
 }
 
 #if defined(__cplusplus)
 L4_INLINE void *L4_KernelInterface(void)
 {
-	return L4_GetKernelInterface();
+    return L4_GetKernelInterface();
 }
 #endif
 
 L4_INLINE L4_Word_t L4_ApiVersion(void)
 {
-	L4_ApiVersion_t version;
-	L4_ApiFlags_t flags;
-	L4_KernelId_t kernel_id;
-	L4_KernelInterface(&version.raw, &flags.raw, &kernel_id.raw);
-	return version.raw;
+    L4_ApiVersion_t version;
+    L4_ApiFlags_t flags;
+    L4_KernelId_t kernel_id;
+    L4_KernelInterface(&version.raw, &flags.raw, &kernel_id.raw);
+    return version.raw;
 }
 
 L4_INLINE L4_Word_t L4_ApiFlags(void)
 {
-	L4_ApiVersion_t version;
-	L4_ApiFlags_t flags;
-	L4_KernelId_t kernel_id;
-	L4_KernelInterface(&version.raw, &flags.raw, &kernel_id.raw);
-	return flags.raw;
+    L4_ApiVersion_t version;
+    L4_ApiFlags_t flags;
+    L4_KernelId_t kernel_id;
+    L4_KernelInterface(&version.raw, &flags.raw, &kernel_id.raw);
+    return flags.raw;
 }
 
 L4_INLINE L4_Word_t L4_KernelId(void)
 {
-	L4_ApiVersion_t version;
-	L4_ApiFlags_t flags;
-	L4_KernelId_t kernel_id;
-	L4_KernelInterface(&version.raw, &flags.raw, &kernel_id.raw);
-	return kernel_id.raw;
+    L4_ApiVersion_t version;
+    L4_ApiFlags_t flags;
+    L4_KernelId_t kernel_id;
+    L4_KernelInterface(&version.raw, &flags.raw, &kernel_id.raw);
+    return kernel_id.raw;
 }
 
-L4_INLINE void L4_KernelGenDate(
-		void *KernelInterface, L4_Word_t *year,
-		L4_Word_t *month, L4_Word_t *day)
+L4_INLINE void L4_KernelGenDate(void *KernelInterface,
+                                L4_Word_t *year,
+                                L4_Word_t *month,
+                                L4_Word_t *day)
 {
-	L4_KernelInterfacePage_t *kip;
-	L4_Word_t gen;
+    L4_KernelInterfacePage_t *kip;
+    L4_Word_t gen;
 
-	kip = (L4_KernelInterfacePage_t *) KernelInterface;
-	gen = ((L4_Word_t *)((L4_Word_t)
-			KernelInterface + kip->KernelVerPtr))[1];
+    kip = (L4_KernelInterfacePage_t *) KernelInterface;
+    gen = ((L4_Word_t *) ((L4_Word_t) KernelInterface + kip->KernelVerPtr))[1];
 
-	*year = ((gen >> 9) & 0x7f) + 2000;
-	*month = ((gen >> 5) & 0x0f);
-	*day = (gen & 0x1f);
+    *year = ((gen >> 9) & 0x7f) + 2000;
+    *month = ((gen >> 5) & 0x0f);
+    *day = (gen & 0x1f);
 }
 
 L4_INLINE L4_Word_t L4_KernelVersion(void *KernelInterface)
 {
-	L4_KernelInterfacePage_t *kip;
-	kip = (L4_KernelInterfacePage_t *) KernelInterface;
-	return ((L4_Word_t *)((L4_Word_t)
-			KernelInterface + kip->KernelVerPtr))[2];
+    L4_KernelInterfacePage_t *kip;
+    kip = (L4_KernelInterfacePage_t *) KernelInterface;
+    return ((L4_Word_t *) ((L4_Word_t) KernelInterface + kip->KernelVerPtr))[2];
 }
 
 L4_INLINE L4_Word_t L4_KernelSupplier(void *KernelInterface)
 {
-	L4_KernelInterfacePage_t *kip;
-	kip = (L4_KernelInterfacePage_t *) KernelInterface;
-	return ((L4_Word_t *)((L4_Word_t)
-			KernelInterface + kip->KernelVerPtr))[3];
+    L4_KernelInterfacePage_t *kip;
+    kip = (L4_KernelInterfacePage_t *) KernelInterface;
+    return ((L4_Word_t *) ((L4_Word_t) KernelInterface + kip->KernelVerPtr))[3];
 }
 
 L4_INLINE L4_Word_t L4_NumProcessors(void *KernelInterface)
 {
-	L4_KernelInterfacePage_t * kip;
-	kip = (L4_KernelInterfacePage_t *) KernelInterface;
-	return kip->ProcessorInfo.X.processors + 1;
+    L4_KernelInterfacePage_t *kip;
+    kip = (L4_KernelInterfacePage_t *) KernelInterface;
+    return kip->ProcessorInfo.X.processors + 1;
 }
 
-L4_INLINE L4_Word_t L4_NumMemoryDescriptors (void *KernelInterface)
+L4_INLINE L4_Word_t L4_NumMemoryDescriptors(void *KernelInterface)
 {
-	L4_KernelInterfacePage_t *kip;
-	kip = (L4_KernelInterfacePage_t *) KernelInterface;
-	return kip->MemoryInfo.n;
+    L4_KernelInterfacePage_t *kip;
+    kip = (L4_KernelInterfacePage_t *) KernelInterface;
+    return kip->MemoryInfo.n;
 }
 
 L4_INLINE L4_Word_t L4_PageSizeMask(void *KernelInterface)
 {
-	L4_KernelInterfacePage_t *kip;
-	kip = (L4_KernelInterfacePage_t *) KernelInterface;
-	return kip->PageInfo.X.page_size_mask << 10;
+    L4_KernelInterfacePage_t *kip;
+    kip = (L4_KernelInterfacePage_t *) KernelInterface;
+    return kip->PageInfo.X.page_size_mask << 10;
 }
 
 L4_INLINE L4_Word_t L4_PageRights(void *KernelInterface)
 {
-	L4_KernelInterfacePage_t *kip;
-	kip = (L4_KernelInterfacePage_t *) KernelInterface;
-	return kip->PageInfo.X.rwx;
+    L4_KernelInterfacePage_t *kip;
+    kip = (L4_KernelInterfacePage_t *) KernelInterface;
+    return kip->PageInfo.X.rwx;
 }
 
 L4_INLINE L4_Word_t L4_ThreadIdBits(void *KernelInterface)
 {
-	L4_KernelInterfacePage_t *kip;
-	kip = (L4_KernelInterfacePage_t *) KernelInterface;
-	return kip->ThreadInfo.X.t;
+    L4_KernelInterfacePage_t *kip;
+    kip = (L4_KernelInterfacePage_t *) KernelInterface;
+    return kip->ThreadInfo.X.t;
 }
 
 L4_INLINE L4_Word_t L4_ThreadIdSystemBase(void *KernelInterface)
 {
-	L4_KernelInterfacePage_t *kip;
-	kip = (L4_KernelInterfacePage_t *) KernelInterface;
-	return kip->ThreadInfo.X.SystemBase;
+    L4_KernelInterfacePage_t *kip;
+    kip = (L4_KernelInterfacePage_t *) KernelInterface;
+    return kip->ThreadInfo.X.SystemBase;
 }
 
 L4_INLINE L4_Word_t L4_ThreadIdUserBase(void *KernelInterface)
 {
-	L4_KernelInterfacePage_t * kip;
-	kip = (L4_KernelInterfacePage_t *) KernelInterface;
-	return kip->ThreadInfo.X.UserBase;
+    L4_KernelInterfacePage_t *kip;
+    kip = (L4_KernelInterfacePage_t *) KernelInterface;
+    return kip->ThreadInfo.X.UserBase;
 }
 
 L4_INLINE L4_Word_t L4_ReadPrecision(void *KernelInterface)
 {
-	L4_KernelInterfacePage_t *kip;
-	kip = (L4_KernelInterfacePage_t *) KernelInterface;
-	return kip->ClockInfo.X.ReadPrecision;
+    L4_KernelInterfacePage_t *kip;
+    kip = (L4_KernelInterfacePage_t *) KernelInterface;
+    return kip->ClockInfo.X.ReadPrecision;
 }
 
 L4_INLINE L4_Word_t L4_SchedulePrecision(void *KernelInterface)
 {
-	L4_KernelInterfacePage_t *kip;
-	kip = (L4_KernelInterfacePage_t *) KernelInterface;
-	return kip->ClockInfo.X.SchedulePrecision;
+    L4_KernelInterfacePage_t *kip;
+    kip = (L4_KernelInterfacePage_t *) KernelInterface;
+    return kip->ClockInfo.X.SchedulePrecision;
 }
 
 L4_INLINE L4_Word_t L4_UtcbAreaSizeLog2(void *KernelInterface)
 {
-	L4_KernelInterfacePage_t *kip;
-	kip = (L4_KernelInterfacePage_t *) KernelInterface;
-	return kip->UtcbAreaInfo.X.s;
+    L4_KernelInterfacePage_t *kip;
+    kip = (L4_KernelInterfacePage_t *) KernelInterface;
+    return kip->UtcbAreaInfo.X.s;
 }
 
 L4_INLINE L4_Word_t L4_UtcbAreaSize(void *KernelInterface)
 {
-	return 1UL << L4_UtcbAreaSizeLog2 (KernelInterface);
+    return 1UL << L4_UtcbAreaSizeLog2(KernelInterface);
 }
 
 L4_INLINE L4_Word_t L4_UtcbAlignmentLog2(void *KernelInterface)
 {
-	L4_KernelInterfacePage_t *kip;
-	kip = (L4_KernelInterfacePage_t *) KernelInterface;
-	return kip->UtcbAreaInfo.X.a;
+    L4_KernelInterfacePage_t *kip;
+    kip = (L4_KernelInterfacePage_t *) KernelInterface;
+    return kip->UtcbAreaInfo.X.a;
 }
 
 L4_INLINE L4_Word_t L4_UtcbSize(void *KernelInterface)
 {
-	L4_KernelInterfacePage_t *kip;
-	kip = (L4_KernelInterfacePage_t *) KernelInterface;
-	return (1UL << kip->UtcbAreaInfo.X.a) * kip->UtcbAreaInfo.X.m;
+    L4_KernelInterfacePage_t *kip;
+    kip = (L4_KernelInterfacePage_t *) KernelInterface;
+    return (1UL << kip->UtcbAreaInfo.X.a) * kip->UtcbAreaInfo.X.m;
 }
 
 L4_INLINE L4_Word_t L4_KipAreaSizeLog2(void *KernelInterface)
 {
-	L4_KernelInterfacePage_t *kip;
-	kip = (L4_KernelInterfacePage_t *) KernelInterface;
-	return kip->KipAreaInfo.X.s;
+    L4_KernelInterfacePage_t *kip;
+    kip = (L4_KernelInterfacePage_t *) KernelInterface;
+    return kip->KipAreaInfo.X.s;
 }
 
-L4_INLINE L4_Word_t L4_KipAreaSize (void *KernelInterface)
+L4_INLINE L4_Word_t L4_KipAreaSize(void *KernelInterface)
 {
-	return 1UL << L4_KipAreaSizeLog2(KernelInterface);
+    return 1UL << L4_KipAreaSizeLog2(KernelInterface);
 }
 
-L4_INLINE L4_Word_t L4_BootInfo (void *KernelInterface)
+L4_INLINE L4_Word_t L4_BootInfo(void *KernelInterface)
 {
-	L4_KernelInterfacePage_t *kip;
-	kip = (L4_KernelInterfacePage_t *) KernelInterface;
-	return kip->BootInfo;
+    L4_KernelInterfacePage_t *kip;
+    kip = (L4_KernelInterfacePage_t *) KernelInterface;
+    return kip->BootInfo;
 }
 
 L4_INLINE char *L4_KernelVersionString(void *KernelInterface)
 {
-	L4_KernelInterfacePage_t * kip;
-	kip = (L4_KernelInterfacePage_t *) KernelInterface;
-	return (char *) ((L4_Word_t)
-			KernelInterface + kip->KernelVerPtr +
-			sizeof (L4_Word_t) * 4);
+    L4_KernelInterfacePage_t *kip;
+    kip = (L4_KernelInterfacePage_t *) KernelInterface;
+    return (char *) ((L4_Word_t) KernelInterface + kip->KernelVerPtr +
+                     sizeof(L4_Word_t) * 4);
 }
 
-L4_INLINE char *L4_Feature (void *KernelInterface, L4_Word_t num)
+L4_INLINE char *L4_Feature(void *KernelInterface, L4_Word_t num)
 {
-	char *str = L4_KernelVersionString (KernelInterface);
+    char *str = L4_KernelVersionString(KernelInterface);
 
-	do {
-		while (*str++ != 0) {}
-		if (*str == 0)
-			return (char *) 0;
-	} while (num--);
+    do {
+        while (*str++ != 0) {
+        }
+        if (*str == 0)
+            return (char *) 0;
+    } while (num--);
 
-	return str;
+    return str;
 }
 #if defined(__cplusplus)
 L4_INLINE L4_Bool_t L4_HasFeature(const char *feature_name)
 {
-	void *kip = L4_GetKernelInterface();
-	char *name;
+    void *kip = L4_GetKernelInterface();
+    char *name;
 
-	for (L4_Word_t i = 0; (name = L4_Feature(kip, i)) != '\0'; i++) {
-		const char *n = name;
-		const char *fn = feature_name;
+    for (L4_Word_t i = 0; (name = L4_Feature(kip, i)) != '\0'; i++) {
+        const char *n = name;
+        const char *fn = feature_name;
 
-		while (*n == *fn++)
-			if (*n++ == 0)
-				return true;
-		if (*(L4_Word8_t *)n - *(L4_Word8_t *)--fn)
-			return true;
-	}
-	return false;
+        while (*n == *fn++)
+            if (*n++ == 0)
+                return true;
+        if (*(L4_Word8_t *) n - *(L4_Word8_t *) --fn)
+            return true;
+    }
+    return false;
 }
 #endif
 
 typedef union {
-	L4_Word_t raw[2];
-	struct {
-		L4_BITFIELD5(L4_Word_t,
-				type	:4,
-				t		:4,
-				__padding1	:1,
-				v		:1,
-				low		:L4_BITS_PER_WORD - 10
-			    );
-		L4_BITFIELD2(L4_Word_t,
-				__padding2	:10,
-				high	:L4_BITS_PER_WORD - 10
-			    );
-	} x;
+    L4_Word_t raw[2];
+    struct {
+        L4_BITFIELD5(L4_Word_t,
+                     type : 4,
+                     t : 4,
+                     __padding1 : 1,
+                     v : 1,
+                     low : L4_BITS_PER_WORD - 10);
+        L4_BITFIELD2(L4_Word_t, __padding2 : 10, high : L4_BITS_PER_WORD - 10);
+    } x;
 } L4_MemoryDesc_t;
 
-#define L4_UndefinedMemoryType			(0x0)
-#define L4_ConventionalMemoryType		(0x1)
-#define L4_ReservedMemoryType			(0x2)
-#define L4_DedicatedMemoryType			(0x3)
-#define L4_SharedMemoryType			(0x4)
-#define L4_BootLoaderSpecificMemoryType		(0xe)
-#define L4_ArchitectureSpecificMemoryType	(0xf)
+#define L4_UndefinedMemoryType (0x0)
+#define L4_ConventionalMemoryType (0x1)
+#define L4_ReservedMemoryType (0x2)
+#define L4_DedicatedMemoryType (0x3)
+#define L4_SharedMemoryType (0x4)
+#define L4_BootLoaderSpecificMemoryType (0xe)
+#define L4_ArchitectureSpecificMemoryType (0xf)
 
-L4_INLINE L4_MemoryDesc_t *L4_MemoryDesc(
-		void *KernelInterface,
-		L4_Word_t num)
+L4_INLINE L4_MemoryDesc_t *L4_MemoryDesc(void *KernelInterface, L4_Word_t num)
 {
-	L4_KernelInterfacePage_t *kip;
-	kip = (L4_KernelInterfacePage_t *) KernelInterface;
+    L4_KernelInterfacePage_t *kip;
+    kip = (L4_KernelInterfacePage_t *) KernelInterface;
 
-	if (num >= kip->MemoryInfo.n)
-		return (L4_MemoryDesc_t *) 0;
+    if (num >= kip->MemoryInfo.n)
+        return (L4_MemoryDesc_t *) 0;
 
-	return (L4_MemoryDesc_t *)
-		((L4_Word_t) kip + kip->MemoryInfo.MemDescPtr) + num;
+    return (L4_MemoryDesc_t *) ((L4_Word_t) kip + kip->MemoryInfo.MemDescPtr) +
+           num;
 }
 
 L4_INLINE L4_Bool_t L4_IsMemoryDescVirtual(L4_MemoryDesc_t *m)
 {
-	return m->x.v;
+    return m->x.v;
 }
 
 L4_INLINE L4_Word_t L4_MemoryDescType(L4_MemoryDesc_t *m)
 {
-	return (m->x.type >= 0x0E) ? (m->x.type + (m->x.t << 4)) : (m->x.type);
+    return (m->x.type >= 0x0E) ? (m->x.type + (m->x.t << 4)) : (m->x.type);
 }
 
 L4_INLINE L4_Word_t L4_MemoryDescLow(L4_MemoryDesc_t *m)
 {
-	return m->x.low << 10;
+    return m->x.low << 10;
 }
 
 L4_INLINE L4_Word_t L4_MemoryDescHigh(L4_MemoryDesc_t *m)
 {
-	return (m->x.high << 10) + 0x3ff;
+    return (m->x.high << 10) + 0x3ff;
 }
 
 #if defined(__cplusplus)
 L4_INLINE L4_Bool_t L4_IsVirtual(L4_MemoryDesc_t *m)
 {
-	return L4_IsMemoryDescVirtual(m);
+    return L4_IsMemoryDescVirtual(m);
 }
 
 L4_INLINE L4_Word_t L4_Type(L4_MemoryDesc_t *m)
 {
-	return L4_MemoryDescType(m);
+    return L4_MemoryDescType(m);
 }
 
 L4_INLINE L4_Word_t L4_Low(L4_MemoryDesc_t *m)
 {
-	return L4_MemoryDescLow(m);
+    return L4_MemoryDescLow(m);
 }
 
 L4_INLINE L4_Word_t L4_High(L4_MemoryDesc_t *m)
 {
-	return L4_MemoryDescHigh(m);
+    return L4_MemoryDescHigh(m);
 }
 #endif /* __cplusplus */
 
-L4_INLINE L4_ProcDesc_t *L4_ProcDesc (void *KernelInterface, L4_Word_t cpu)
+L4_INLINE L4_ProcDesc_t *L4_ProcDesc(void *KernelInterface, L4_Word_t cpu)
 {
-	L4_KernelInterfacePage_t *kip;
-	kip = (L4_KernelInterfacePage_t *) KernelInterface;
+    L4_KernelInterfacePage_t *kip;
+    kip = (L4_KernelInterfacePage_t *) KernelInterface;
 
-	if (cpu > kip->ProcessorInfo.X.processors)
-		return (L4_ProcDesc_t *) 0;
+    if (cpu > kip->ProcessorInfo.X.processors)
+        return (L4_ProcDesc_t *) 0;
 
-	return (L4_ProcDesc_t *)
-		((L4_Word_t)kip + kip->ProcDescPtr +
-		 ((1 << kip->ProcessorInfo.X.s) * cpu));
+    return (L4_ProcDesc_t *) ((L4_Word_t) kip + kip->ProcDescPtr +
+                              ((1 << kip->ProcessorInfo.X.s) * cpu));
 }
 
 L4_INLINE L4_Word_t L4_ProcDescExternalFreq(L4_ProcDesc_t *p)
 {
-	return p->X.ExternalFreq;
+    return p->X.ExternalFreq;
 }
 
 L4_INLINE L4_Word_t L4_ProcDescInternalFreq(L4_ProcDesc_t *p)
 {
-	return p->X.InternalFreq;
+    return p->X.InternalFreq;
 }
 
 #if defined(__cplusplus)
-L4_INLINE L4_Word_t L4_ExternalFreq (L4_ProcDesc_t *p)
+L4_INLINE L4_Word_t L4_ExternalFreq(L4_ProcDesc_t *p)
 {
-	return L4_ProcDescExternalFreq(p);
+    return L4_ProcDescExternalFreq(p);
 }
 
 L4_INLINE L4_Word_t L4_InternalFreq(L4_ProcDesc_t *p)
 {
-	return L4_ProcDescInternalFreq(p);
+    return L4_ProcDescInternalFreq(p);
 }
 #endif /* __cplusplus */
 
diff --git a/user/include/l4/message.h b/user/include/l4/message.h
index 300ef9ec..c0d7fe65 100644
--- a/user/include/l4/message.h
+++ b/user/include/l4/message.h
@@ -13,342 +13,339 @@
 #include __L4_INC_ARCH(specials.h)
 
 #if defined(L4_64BIT)
-# define __PLUS32	+ 32
+#define __PLUS32 +32
 #else
-# define __PLUS32
+#define __PLUS32
 #endif
 
 /*
  * Message tag
  */
 typedef union {
-	L4_Word_t raw;
-	struct {
+    L4_Word_t raw;
+    struct {
 #if defined(L4_BIG_ENDIAN)
-		L4_Word_t	label:16 __PLUS32;
-		L4_Word_t	flags:4;
-		L4_Word_t	t:6;
-		L4_Word_t	u:6;
+        L4_Word_t label : 16 __PLUS32;
+        L4_Word_t flags : 4;
+        L4_Word_t t : 6;
+        L4_Word_t u : 6;
 #else
-		L4_Word_t	u:6;
-		L4_Word_t	t:6;
-		L4_Word_t	flags:4;
-		L4_Word_t	label:16 __PLUS32;
+        L4_Word_t u : 6;
+        L4_Word_t t : 6;
+        L4_Word_t flags : 4;
+        L4_Word_t label : 16 __PLUS32;
 #endif
-	} X;
+    } X;
 
 } L4_MsgTag_t;
 
-#define L4_Niltag		((L4_MsgTag_t) { raw : 0UL })
+#define L4_Niltag ((L4_MsgTag_t) {raw : 0UL})
 
-L4_INLINE L4_Bool_t L4_IsMsgTagEqual(
-		const L4_MsgTag_t l, const L4_MsgTag_t r)
+L4_INLINE L4_Bool_t L4_IsMsgTagEqual(const L4_MsgTag_t l, const L4_MsgTag_t r)
 {
-	return l.raw == r.raw;
+    return l.raw == r.raw;
 }
 
-L4_INLINE L4_Bool_t L4_IsMsgTagNotEqual(
-		const L4_MsgTag_t l, const L4_MsgTag_t r)
+L4_INLINE L4_Bool_t L4_IsMsgTagNotEqual(const L4_MsgTag_t l,
+                                        const L4_MsgTag_t r)
 {
-	return l.raw != r.raw;
+    return l.raw != r.raw;
 }
 
-L4_INLINE L4_MsgTag_t L4_MsgTagAddLabel(
-		const L4_MsgTag_t t, int label)
+L4_INLINE L4_MsgTag_t L4_MsgTagAddLabel(const L4_MsgTag_t t, int label)
 {
-	L4_MsgTag_t tag = t;
-	tag.X.label = label;
-	return tag;
+    L4_MsgTag_t tag = t;
+    tag.X.label = label;
+    return tag;
 }
 
 L4_INLINE L4_MsgTag_t L4_MsgTagAddLabelTo(L4_MsgTag_t *t, int label)
 {
-	t->X.label = label;
-	return *t;
+    t->X.label = label;
+    return *t;
 }
 
 L4_INLINE L4_Word_t L4_Label(L4_MsgTag_t t)
 {
-	return t.X.label;
+    return t.X.label;
 }
 
 L4_INLINE L4_Word_t L4_UntypedWords(L4_MsgTag_t t)
 {
-	return t.X.u;
+    return t.X.u;
 }
 
 L4_INLINE L4_Word_t L4_TypedWords(L4_MsgTag_t t)
 {
-	return t.X.t;
+    return t.X.t;
 }
 
 L4_INLINE void L4_Set_Label(L4_MsgTag_t *t, L4_Word_t label)
 {
-	t->X.label = label;
+    t->X.label = label;
 }
 
 L4_INLINE L4_MsgTag_t L4_MsgTag(void)
 {
-	L4_MsgTag_t msgtag;
-	L4_StoreMR(0, &msgtag.raw);
-	return msgtag;
+    L4_MsgTag_t msgtag;
+    L4_StoreMR(0, &msgtag.raw);
+    return msgtag;
 }
 
 L4_INLINE void L4_Set_MsgTag(L4_MsgTag_t t)
 {
-	L4_LoadMR(0, t.raw);
+    L4_LoadMR(0, t.raw);
 }
 
 /*
  * Map item
  */
 typedef union {
-	L4_Word_t raw[2];
-	struct {
+    L4_Word_t raw[2];
+    struct {
 #if defined(L4_BIG_ENDIAN)
-		L4_Word_t	snd_base:22 __PLUS32;
-		L4_Word_t	__zeros:6;
-		L4_Word_t	__type:3;
-		L4_Word_t	C:1;
+        L4_Word_t snd_base : 22 __PLUS32;
+        L4_Word_t __zeros : 6;
+        L4_Word_t __type : 3;
+        L4_Word_t C : 1;
 #else
-		L4_Word_t	C:1;
-		L4_Word_t	__type:3;
-		L4_Word_t	__zeros:6;
-		L4_Word_t	snd_base:22 __PLUS32;
+        L4_Word_t C : 1;
+        L4_Word_t __type : 3;
+        L4_Word_t __zeros : 6;
+        L4_Word_t snd_base : 22 __PLUS32;
 #endif
-		L4_Fpage_t	snd_fpage;
-	} X;
+        L4_Fpage_t snd_fpage;
+    } X;
 } L4_MapItem_t;
 
 L4_INLINE L4_MapItem_t L4_MapItem(L4_Fpage_t f, L4_Word_t SndBase)
 {
-	L4_MapItem_t item;
-	item.raw[0] = 0;
-	item.X.__type = 0x04;
-	item.X.snd_base = SndBase >> 10;
-	item.X.snd_fpage.raw = f.raw;
-	return item;
+    L4_MapItem_t item;
+    item.raw[0] = 0;
+    item.X.__type = 0x04;
+    item.X.snd_base = SndBase >> 10;
+    item.X.snd_fpage.raw = f.raw;
+    return item;
 }
 
 L4_INLINE L4_Bool_t L4_IsMapItem(L4_MapItem_t m)
 {
-	return m.X.__type == 0x04;
+    return m.X.__type == 0x04;
 }
 
 L4_INLINE L4_Fpage_t L4_MapItemSndFpage(L4_MapItem_t m)
 {
-	return m.X.snd_fpage;
+    return m.X.snd_fpage;
 }
 
 L4_INLINE L4_Word_t L4_MapItemSndBase(L4_MapItem_t m)
 {
-	return m.X.snd_base << 10;
+    return m.X.snd_base << 10;
 }
 
 /*
  * Grant item
  */
 typedef union {
-	L4_Word_t raw[2];
-	struct {
+    L4_Word_t raw[2];
+    struct {
 #if defined(L4_BIG_ENDIAN)
-		L4_Word_t	snd_base:22 __PLUS32;
-		L4_Word_t	__zeros:6;
-		L4_Word_t	__type:3;
-		L4_Word_t	C:1;
+        L4_Word_t snd_base : 22 __PLUS32;
+        L4_Word_t __zeros : 6;
+        L4_Word_t __type : 3;
+        L4_Word_t C : 1;
 #else
-		L4_Word_t	C:1;
-		L4_Word_t	__type:3;
-		L4_Word_t	__zeros:6;
-		L4_Word_t	snd_base:22 __PLUS32;
+        L4_Word_t C : 1;
+        L4_Word_t __type : 3;
+        L4_Word_t __zeros : 6;
+        L4_Word_t snd_base : 22 __PLUS32;
 #endif
-		L4_Fpage_t	snd_fpage;
-	} X;
+        L4_Fpage_t snd_fpage;
+    } X;
 } L4_GrantItem_t;
 
 L4_INLINE L4_Bool_t L4_IsGrantItem(L4_GrantItem_t g)
 {
-	return g.X.__type == 0x05;
+    return g.X.__type == 0x05;
 }
 
 L4_INLINE L4_GrantItem_t L4_GrantItem(L4_Fpage_t f, L4_Word_t SndBase)
 {
-	L4_GrantItem_t item;
-	item.raw[0] = 0;
-	item.X.__type = 0x05;
-	item.X.snd_base = SndBase >> 10;
-	item.X.snd_fpage.raw = f.raw;
-	return item;
+    L4_GrantItem_t item;
+    item.raw[0] = 0;
+    item.X.__type = 0x05;
+    item.X.snd_base = SndBase >> 10;
+    item.X.snd_fpage.raw = f.raw;
+    return item;
 }
 
 L4_INLINE L4_Fpage_t L4_GrantItemSndFpage(L4_GrantItem_t m)
 {
-	return m.X.snd_fpage;
+    return m.X.snd_fpage;
 }
 
 L4_INLINE L4_Word_t L4_GrantItemSndBase(L4_GrantItem_t m)
 {
-	return m.X.snd_base << 10;
+    return m.X.snd_base << 10;
 }
 
 /*
  * String item
  */
 typedef union {
-	L4_Word_t raw[2];
-	struct {
+    L4_Word_t raw[2];
+    struct {
 #if defined(L4_BIG_ENDIAN)
-		L4_Word_t	string_length:22 __PLUS32;
-		L4_Word_t	c:1;
-		L4_Word_t	j:5;
-		L4_Word_t	__type:3;
-		L4_Word_t	C:1;
+        L4_Word_t string_length : 22 __PLUS32;
+        L4_Word_t c : 1;
+        L4_Word_t j : 5;
+        L4_Word_t __type : 3;
+        L4_Word_t C : 1;
 #else
-		L4_Word_t	C:1;
-		L4_Word_t	__type:3;
-		L4_Word_t	j:5;
-		L4_Word_t	c:1;
-		L4_Word_t	string_length:22 __PLUS32;
+        L4_Word_t C : 1;
+        L4_Word_t __type : 3;
+        L4_Word_t j : 5;
+        L4_Word_t c : 1;
+        L4_Word_t string_length : 22 __PLUS32;
 #endif
-		union {
-			void *string_ptr;
-			void *substring_ptr[0];
-		} str;
-	} X;
+        union {
+            void *string_ptr;
+            void *substring_ptr[0];
+        } str;
+    } X;
 } L4_StringItem_t;
 
 L4_INLINE L4_StringItem_t L4_StringItem(int size, void *address)
 {
-	L4_StringItem_t item;
-	item.X.C = 0;
-	item.X.__type = 0;
-	item.X.j = 0;
-	item.X.c = 0;
-	item.X.string_length = size;
-	item.X.str.string_ptr = address;
-	return item;
+    L4_StringItem_t item;
+    item.X.C = 0;
+    item.X.__type = 0;
+    item.X.j = 0;
+    item.X.c = 0;
+    item.X.string_length = size;
+    item.X.str.string_ptr = address;
+    return item;
 }
 
 L4_INLINE L4_Bool_t L4_IsStringItem(L4_StringItem_t *s)
 {
-	return (s->X.__type & 0x04) == 0;
+    return (s->X.__type & 0x04) == 0;
 }
 
 L4_INLINE L4_Bool_t L4_CompoundString(L4_StringItem_t *s)
 {
-	return s->X.c != 0;
+    return s->X.c != 0;
 }
 
 L4_INLINE L4_Word_t L4_Substrings(L4_StringItem_t *s)
 {
-	return s->X.j + 1;
+    return s->X.j + 1;
 }
 
-L4_INLINE void * L4_Substring(L4_StringItem_t *s, L4_Word_t n)
+L4_INLINE void *L4_Substring(L4_StringItem_t *s, L4_Word_t n)
 {
-	return s->X.str.substring_ptr[n - 1];
+    return s->X.str.substring_ptr[n - 1];
 }
 
-L4_INLINE L4_StringItem_t *__L4_EndOfString(
-		L4_StringItem_t *s, L4_StringItem_t **p)
+L4_INLINE L4_StringItem_t *__L4_EndOfString(L4_StringItem_t *s,
+                                            L4_StringItem_t **p)
 {
-	L4_StringItem_t *prev;
-	do {
-		prev = s;
-		s = (L4_StringItem_t *) &s->X.str.substring_ptr[s->X.j + 1];
-	} while (prev->X.c);
-	if (p)
-		*p = prev;
-	return s;
+    L4_StringItem_t *prev;
+    do {
+        prev = s;
+        s = (L4_StringItem_t *) &s->X.str.substring_ptr[s->X.j + 1];
+    } while (prev->X.c);
+    if (p)
+        *p = prev;
+    return s;
 }
 
-L4_INLINE L4_StringItem_t *__L4_EndOfStrings(
-		L4_StringItem_t *s, L4_StringItem_t **p)
+L4_INLINE L4_StringItem_t *__L4_EndOfStrings(L4_StringItem_t *s,
+                                             L4_StringItem_t **p)
 {
-	L4_StringItem_t *prev;
-	do {
-		prev = s;
-		s = __L4_EndOfString(s, (L4_StringItem_t **) 0);
-	} while (prev->X.C);
-	if (p)
-		*p = prev;
-	return s;
+    L4_StringItem_t *prev;
+    do {
+        prev = s;
+        s = __L4_EndOfString(s, (L4_StringItem_t **) 0);
+    } while (prev->X.C);
+    if (p)
+        *p = prev;
+    return s;
 }
 
-L4_INLINE void __L4_Copy_String(
-		L4_StringItem_t *d, L4_StringItem_t *s)
+L4_INLINE void __L4_Copy_String(L4_StringItem_t *d, L4_StringItem_t *s)
 {
-	L4_Word_t *dest, *from, *end;
-	from = (L4_Word_t *) s;
-	dest = (L4_Word_t *) d;
-	end = (L4_Word_t *) __L4_EndOfString(s, (L4_StringItem_t **) 0);
-	while (from < end)
-		*dest++ = *from++;
+    L4_Word_t *dest, *from, *end;
+    from = (L4_Word_t *) s;
+    dest = (L4_Word_t *) d;
+    end = (L4_Word_t *) __L4_EndOfString(s, (L4_StringItem_t **) 0);
+    while (from < end)
+        *dest++ = *from++;
 }
 
-L4_INLINE L4_StringItem_t *L4_AddSubstringTo(
-		L4_StringItem_t *dest, L4_StringItem_t *substr)
+L4_INLINE L4_StringItem_t *L4_AddSubstringTo(L4_StringItem_t *dest,
+                                             L4_StringItem_t *substr)
 {
-	L4_StringItem_t *prev;
-	dest = __L4_EndOfString(dest, &prev);
-	prev->X.c = 1;
-	__L4_Copy_String(dest, substr);
-	return dest;
+    L4_StringItem_t *prev;
+    dest = __L4_EndOfString(dest, &prev);
+    prev->X.c = 1;
+    __L4_Copy_String(dest, substr);
+    return dest;
 }
 
-L4_INLINE L4_StringItem_t *L4_AddSubstringAddressTo(
-		L4_StringItem_t *dest, void *substring_addr)
+L4_INLINE L4_StringItem_t *L4_AddSubstringAddressTo(L4_StringItem_t *dest,
+                                                    void *substring_addr)
 {
-	L4_StringItem_t *last;
-	__L4_EndOfString(dest, &last);
-	last->X.j++;
-	last->X.str.substring_ptr[last->X.j] = substring_addr;
-	return dest;
+    L4_StringItem_t *last;
+    __L4_EndOfString(dest, &last);
+    last->X.j++;
+    last->X.str.substring_ptr[last->X.j] = substring_addr;
+    return dest;
 }
 
 /*
  * CtrlXfer Item
  */
 typedef union {
-	L4_Word_t raw[0];
+    L4_Word_t raw[0];
 #if defined(L4_BIG_ENDIAN)
-	struct {
-		L4_Word_t	mask:20 __PLUS32;
-		L4_Word_t	id:8;
-		L4_Word_t	__type:3;
-		L4_Word_t	C:1;
+    struct {
+        L4_Word_t mask : 20 __PLUS32;
+        L4_Word_t id : 8;
+        L4_Word_t __type : 3;
+        L4_Word_t C : 1;
 #else
-	struct {
-			L4_Word_t	C:1;
-			L4_Word_t	__type:3;
-			L4_Word_t	id:8;
-			L4_Word_t	mask:20 __PLUS32;
+    struct {
+        L4_Word_t C : 1;
+        L4_Word_t __type : 3;
+        L4_Word_t id : 8;
+        L4_Word_t mask : 20 __PLUS32;
 #endif
-	} X;
+    } X;
 } L4_CtrlXferItem_t;
 
 
 L4_INLINE L4_Bool_t L4_IsCtrlXferItem(L4_CtrlXferItem_t *s)
 {
-	return (s->X.__type == 6);
+    return (s->X.__type == 6);
 }
 
-L4_INLINE void L4_CtrlXferItemInit (L4_CtrlXferItem_t *c, L4_Word_t id)
+L4_INLINE void L4_CtrlXferItemInit(L4_CtrlXferItem_t *c, L4_Word_t id)
 {
-	c->raw[0] = 0;
-	c->X.__type = 0x06;
-	c->X.id = id;
-	c->X.mask = 0;
+    c->raw[0] = 0;
+    c->X.__type = 0x06;
+    c->X.id = id;
+    c->X.mask = 0;
 }
 
-L4_INLINE void L4_FaultConfCtrlXferItemInit(
-		L4_CtrlXferItem_t *c, L4_Word_t fault_id,
-		L4_Word_t fault_mask)
+L4_INLINE void L4_FaultConfCtrlXferItemInit(L4_CtrlXferItem_t *c,
+                                            L4_Word_t fault_id,
+                                            L4_Word_t fault_mask)
 {
-	c->raw[0] = 0;
-	c->X.__type = 0x06;
-	c->X.id = fault_id;
-	c->X.mask = fault_mask;
+    c->raw[0] = 0;
+    c->X.__type = 0x06;
+    c->X.id = fault_id;
+    c->X.mask = fault_mask;
 }
 
 
@@ -356,317 +353,318 @@ L4_INLINE void L4_FaultConfCtrlXferItemInit(
  * Cache allocation hints
  */
 typedef struct L4_CacheAllocationHint {
-	L4_Word_t raw;
+    L4_Word_t raw;
 } L4_CacheAllocationHint_t;
 
-#define L4_UseDefaultCacheAllocation ((L4_CacheAllocationHint_t) { raw: 0 })
+#define L4_UseDefaultCacheAllocation ((L4_CacheAllocationHint_t) {raw : 0})
 
-L4_INLINE L4_CacheAllocationHint_t L4_CacheAlloctionHint(
-		const L4_StringItem_t s)
+L4_INLINE L4_CacheAllocationHint_t
+L4_CacheAlloctionHint(const L4_StringItem_t s)
 {
-	L4_CacheAllocationHint_t hint;
-	hint.raw = s.raw[0] & 0x6;
-	return hint;
+    L4_CacheAllocationHint_t hint;
+    hint.raw = s.raw[0] & 0x6;
+    return hint;
 }
 
-L4_INLINE L4_Bool_t L4_IsCacheAllocationHintEqual(
-		const L4_CacheAllocationHint_t l, const L4_CacheAllocationHint_t r)
+L4_INLINE L4_Bool_t
+L4_IsCacheAllocationHintEqual(const L4_CacheAllocationHint_t l,
+                              const L4_CacheAllocationHint_t r)
 {
-	return (l.raw & 0x6) == (r.raw & 0x6);
+    return (l.raw & 0x6) == (r.raw & 0x6);
 }
 
-L4_INLINE L4_Bool_t L4_IsCacheAllocationHintNotEqual(
-		const L4_CacheAllocationHint_t l, const L4_CacheAllocationHint_t r)
+L4_INLINE L4_Bool_t
+L4_IsCacheAllocationHintNotEqual(const L4_CacheAllocationHint_t l,
+                                 const L4_CacheAllocationHint_t r)
 {
-	return (l.raw & 0x6) != (r.raw & 0x6);
+    return (l.raw & 0x6) != (r.raw & 0x6);
 }
 
-L4_INLINE L4_StringItem_t L4_AddCacheAllocationHint(
-		const L4_StringItem_t dest, const L4_CacheAllocationHint_t h)
+L4_INLINE L4_StringItem_t
+L4_AddCacheAllocationHint(const L4_StringItem_t dest,
+                          const L4_CacheAllocationHint_t h)
 {
-	L4_StringItem_t item = dest;
-	item.raw[0] |= (h.raw & 0x6);
-	return item;
+    L4_StringItem_t item = dest;
+    item.raw[0] |= (h.raw & 0x6);
+    return item;
 }
 
-L4_INLINE L4_StringItem_t L4_AddCacheAllocationHintTo(
-		L4_StringItem_t * dest, const L4_CacheAllocationHint_t h)
+L4_INLINE L4_StringItem_t
+L4_AddCacheAllocationHintTo(L4_StringItem_t *dest,
+                            const L4_CacheAllocationHint_t h)
 {
-	dest->raw[0] |= (h.raw & 0x6);
-	return *dest;
+    dest->raw[0] |= (h.raw & 0x6);
+    return *dest;
 }
 
 /*
  * Message objects
  */
 typedef union {
-	L4_Word_t raw[__L4_NUM_MRS];
-	L4_Word_t msg[__L4_NUM_MRS];
-		L4_MsgTag_t tag;
+    L4_Word_t raw[__L4_NUM_MRS];
+    L4_Word_t msg[__L4_NUM_MRS];
+    L4_MsgTag_t tag;
 } L4_Msg_t;
 
-L4_INLINE void L4_MsgPut(
-		L4_Msg_t *msg, L4_Word_t label,
-		int u, L4_Word_t *Untyped,
-		int t, void * Items)
+L4_INLINE void L4_MsgPut(L4_Msg_t *msg,
+                         L4_Word_t label,
+                         int u,
+                         L4_Word_t *Untyped,
+                         int t,
+                         void *Items)
 {
-	int i;
-	for (i = 0; i < u; i++)
-		msg->msg[i+1] = Untyped[i];
-	for (i = 0; i < t; i++)
-		msg->msg[i+u+1] = ((L4_Word_t *) Items)[i];
-	msg->tag.X.label = label;
-	msg->tag.X.flags = 0;
-	msg->tag.X.u = u;
-	msg->tag.X.t = t;
+    int i;
+    for (i = 0; i < u; i++)
+        msg->msg[i + 1] = Untyped[i];
+    for (i = 0; i < t; i++)
+        msg->msg[i + u + 1] = ((L4_Word_t *) Items)[i];
+    msg->tag.X.label = label;
+    msg->tag.X.flags = 0;
+    msg->tag.X.u = u;
+    msg->tag.X.t = t;
 }
 
-L4_INLINE void L4_MsgGet(
-		const L4_Msg_t *msg, L4_Word_t *Untyped,
-		void *Items)
+L4_INLINE void L4_MsgGet(const L4_Msg_t *msg, L4_Word_t *Untyped, void *Items)
 {
-	int i, u, t;
-	u = msg->tag.X.u;
-	t = msg->tag.X.t;
-	for (i = 0; i < u; i++)
-		Untyped[i] = msg->msg[i + 1];
-	for (i = 0; i < t; i++)
-		((L4_Word_t *) Items)[i] = msg->msg[i + 1 + u];
+    int i, u, t;
+    u = msg->tag.X.u;
+    t = msg->tag.X.t;
+    for (i = 0; i < u; i++)
+        Untyped[i] = msg->msg[i + 1];
+    for (i = 0; i < t; i++)
+        ((L4_Word_t *) Items)[i] = msg->msg[i + 1 + u];
 }
 
 L4_INLINE L4_MsgTag_t L4_MsgMsgTag(const L4_Msg_t *msg)
 {
-	return msg->tag;
+    return msg->tag;
 }
 
 L4_INLINE void L4_Set_MsgMsgTag(L4_Msg_t *msg, L4_MsgTag_t t)
 {
-	msg->tag = t;
+    msg->tag = t;
 }
 
 L4_INLINE L4_Word_t L4_MsgLabel(const L4_Msg_t *msg)
 {
-	return msg->tag.X.label;
+    return msg->tag.X.label;
 }
 
 L4_INLINE void L4_Set_MsgLabel(L4_Msg_t *msg, L4_Word_t label)
 {
-	msg->tag.X.label = label;
+    msg->tag.X.label = label;
 }
 
-L4_INLINE void L4_MsgLoad (L4_Msg_t *msg)
+L4_INLINE void L4_MsgLoad(L4_Msg_t *msg)
 {
-	L4_LoadMRs(0, msg->tag.X.u + msg->tag.X.t + 1, &msg->msg[0]);
+    L4_LoadMRs(0, msg->tag.X.u + msg->tag.X.t + 1, &msg->msg[0]);
 }
 
 L4_INLINE void L4_MsgStore(L4_MsgTag_t t, L4_Msg_t *msg)
 {
-	L4_StoreMRs(1, t.X.u + t.X.t, &msg->msg[1]);
-	msg->tag = t;
+    L4_StoreMRs(1, t.X.u + t.X.t, &msg->msg[1]);
+    msg->tag = t;
 }
 
 L4_INLINE void L4_MsgClear(L4_Msg_t *msg)
 {
-	msg->msg[0] = 0;
+    msg->msg[0] = 0;
 }
 
 L4_INLINE void L4_MsgAppendWord(L4_Msg_t *msg, L4_Word_t w)
 {
-	if (msg->tag.X.t) {
-		L4_Word_t i = 1 + msg->tag.X.u + msg->tag.X.t;
-		for ( ; i > (L4_Word_t)(msg->tag.X.u + 1); i--)
-			msg->msg[i] = msg->msg[i-1];
-	}
-	msg->msg[++msg->tag.X.u] = w;
+    if (msg->tag.X.t) {
+        L4_Word_t i = 1 + msg->tag.X.u + msg->tag.X.t;
+        for (; i > (L4_Word_t) (msg->tag.X.u + 1); i--)
+            msg->msg[i] = msg->msg[i - 1];
+    }
+    msg->msg[++msg->tag.X.u] = w;
 }
 
 L4_INLINE void L4_MsgAppendMapItem(L4_Msg_t *msg, L4_MapItem_t m)
 {
-	msg->msg[msg->tag.X.u + msg->tag.X.t + 1] = m.raw[0];
-	msg->msg[msg->tag.X.u + msg->tag.X.t + 2] = m.raw[1];
-	msg->tag.X.t += 2;
+    msg->msg[msg->tag.X.u + msg->tag.X.t + 1] = m.raw[0];
+    msg->msg[msg->tag.X.u + msg->tag.X.t + 2] = m.raw[1];
+    msg->tag.X.t += 2;
 }
 
 L4_INLINE void L4_MsgAppendGrantItem(L4_Msg_t *msg, L4_GrantItem_t g)
 {
-	msg->msg[msg->tag.X.u + msg->tag.X.t + 1] = g.raw[0];
-	msg->msg[msg->tag.X.u + msg->tag.X.t + 2] = g.raw[1];
-	msg->tag.X.t += 2;
+    msg->msg[msg->tag.X.u + msg->tag.X.t + 1] = g.raw[0];
+    msg->msg[msg->tag.X.u + msg->tag.X.t + 2] = g.raw[1];
+    msg->tag.X.t += 2;
 }
 
 L4_INLINE void L4_MsgAppendSimpleStringItem(L4_Msg_t *msg, L4_StringItem_t s)
 {
-	s.X.c = 0;
-	s.X.j = 0;
-	msg->msg[msg->tag.X.u + msg->tag.X.t + 1] = s.raw[0];
-	msg->msg[msg->tag.X.u + msg->tag.X.t + 2] = s.raw[1];
-	msg->tag.X.t += 2;
+    s.X.c = 0;
+    s.X.j = 0;
+    msg->msg[msg->tag.X.u + msg->tag.X.t + 1] = s.raw[0];
+    msg->msg[msg->tag.X.u + msg->tag.X.t + 2] = s.raw[1];
+    msg->tag.X.t += 2;
 }
 
-L4_INLINE void L4_MsgAppendStringItem(
-		L4_Msg_t *msg, L4_StringItem_t *s)
+L4_INLINE void L4_MsgAppendStringItem(L4_Msg_t *msg, L4_StringItem_t *s)
 {
-	L4_StringItem_t *d = (L4_StringItem_t *)
-			&msg->msg[msg->tag.X.u + msg->tag.X.t + 1];
-	L4_StringItem_t *e = __L4_EndOfString(s, (L4_StringItem_t **) 0);
-	int size = ((L4_Word_t) e - (L4_Word_t) s) / sizeof (L4_Word_t);
-	__L4_Copy_String(d, s);
-	msg->tag.X.t += size;
+    L4_StringItem_t *d =
+        (L4_StringItem_t *) &msg->msg[msg->tag.X.u + msg->tag.X.t + 1];
+    L4_StringItem_t *e = __L4_EndOfString(s, (L4_StringItem_t **) 0);
+    int size = ((L4_Word_t) e - (L4_Word_t) s) / sizeof(L4_Word_t);
+    __L4_Copy_String(d, s);
+    msg->tag.X.t += size;
 }
 
 L4_INLINE void L4_MsgAppendCtrlXferItem(L4_Msg_t *msg, L4_CtrlXferItem_t *c)
 {
-	L4_Word_t reg=0, num=0, mask = c->X.mask;
-	/* Add regs according to mask */
-	for (reg += __L4_Lsb(mask); mask != 0;
-			mask >>= __L4_Lsb(mask) + 1, reg += __L4_Lsb(mask) + 1, num++)
-		msg->msg[msg->tag.X.u + msg->tag.X.t + 2 + num] = c->raw[reg + 1];
-
-	/* Add item */
-	if (num) {
-		msg->msg[msg->tag.X.u + msg->tag.X.t + 1] = c->raw[0];
-		msg->tag.X.t += 1 + num;
-	}
-}
-
-L4_INLINE void L4_AppendFaultConfCtrlXferItems(
-		L4_Msg_t *msg,
-		L4_Word64_t fault_id_mask,
-		L4_Word_t fault_mask,
-		L4_Word_t C)
-{
-	L4_CtrlXferItem_t item;
-	L4_Word_t fault_id = 0;
-	L4_Word_t fault_id_mask_low = fault_id_mask;
-	L4_Word_t fault_id_mask_high = (fault_id_mask >> 32);
-
-	for (fault_id += __L4_Lsb(fault_id_mask_low); fault_id_mask_low != 0;
-			fault_id_mask_low >>= __L4_Lsb(fault_id_mask_low) + 1,
-			fault_id += __L4_Lsb(fault_id_mask_low) + 1) {
-		L4_FaultConfCtrlXferItemInit(&item, fault_id, fault_mask);
-		item.X.C = 1;
-		L4_MsgAppendWord(msg, item.raw[0]);
-	}
-
-	fault_id = 32;
-	for (fault_id += __L4_Lsb(fault_id_mask_high); fault_id_mask_high != 0;
-			fault_id_mask_high >>= __L4_Lsb(fault_id_mask_high) + 1,
-			fault_id += __L4_Lsb(fault_id_mask_high) + 1) {
-		L4_FaultConfCtrlXferItemInit(&item, fault_id, fault_mask);
-		item.X.C = 1;
-		L4_MsgAppendWord(msg, item.raw[0]);
-	}
-
-	item.X.C = C;
-	msg->msg[msg->tag.X.u + msg->tag.X.t] = item.raw[0];
+    L4_Word_t reg = 0, num = 0, mask = c->X.mask;
+    /* Add regs according to mask */
+    for (reg += __L4_Lsb(mask); mask != 0;
+         mask >>= __L4_Lsb(mask) + 1, reg += __L4_Lsb(mask) + 1, num++)
+        msg->msg[msg->tag.X.u + msg->tag.X.t + 2 + num] = c->raw[reg + 1];
+
+    /* Add item */
+    if (num) {
+        msg->msg[msg->tag.X.u + msg->tag.X.t + 1] = c->raw[0];
+        msg->tag.X.t += 1 + num;
+    }
+}
+
+L4_INLINE void L4_AppendFaultConfCtrlXferItems(L4_Msg_t *msg,
+                                               L4_Word64_t fault_id_mask,
+                                               L4_Word_t fault_mask,
+                                               L4_Word_t C)
+{
+    L4_CtrlXferItem_t item;
+    L4_Word_t fault_id = 0;
+    L4_Word_t fault_id_mask_low = fault_id_mask;
+    L4_Word_t fault_id_mask_high = (fault_id_mask >> 32);
+
+    for (fault_id += __L4_Lsb(fault_id_mask_low); fault_id_mask_low != 0;
+         fault_id_mask_low >>= __L4_Lsb(fault_id_mask_low) + 1,
+         fault_id += __L4_Lsb(fault_id_mask_low) + 1) {
+        L4_FaultConfCtrlXferItemInit(&item, fault_id, fault_mask);
+        item.X.C = 1;
+        L4_MsgAppendWord(msg, item.raw[0]);
+    }
+
+    fault_id = 32;
+    for (fault_id += __L4_Lsb(fault_id_mask_high); fault_id_mask_high != 0;
+         fault_id_mask_high >>= __L4_Lsb(fault_id_mask_high) + 1,
+         fault_id += __L4_Lsb(fault_id_mask_high) + 1) {
+        L4_FaultConfCtrlXferItemInit(&item, fault_id, fault_mask);
+        item.X.C = 1;
+        L4_MsgAppendWord(msg, item.raw[0]);
+    }
+
+    item.X.C = C;
+    msg->msg[msg->tag.X.u + msg->tag.X.t] = item.raw[0];
 }
 
 L4_INLINE void L4_MsgPutWord(L4_Msg_t *msg, L4_Word_t u, L4_Word_t w)
 {
-	msg->msg[u + 1] = w;
+    msg->msg[u + 1] = w;
 }
 
-L4_INLINE void L4_MsgPutMapItem (L4_Msg_t *msg, L4_Word_t t, L4_MapItem_t m)
+L4_INLINE void L4_MsgPutMapItem(L4_Msg_t *msg, L4_Word_t t, L4_MapItem_t m)
 {
-	msg->msg[msg->tag.X.u + t + 1] = m.raw[0];
-	msg->msg[msg->tag.X.u + t + 2] = m.raw[1];
+    msg->msg[msg->tag.X.u + t + 1] = m.raw[0];
+    msg->msg[msg->tag.X.u + t + 2] = m.raw[1];
 }
 
-L4_INLINE void L4_MsgPutGrantItem(
-		L4_Msg_t *msg, L4_Word_t t,
-		L4_GrantItem_t g)
+L4_INLINE void L4_MsgPutGrantItem(L4_Msg_t *msg, L4_Word_t t, L4_GrantItem_t g)
 {
-	msg->msg[msg->tag.X.u + t + 1] = g.raw[0];
-	msg->msg[msg->tag.X.u + t + 2] = g.raw[1];
+    msg->msg[msg->tag.X.u + t + 1] = g.raw[0];
+    msg->msg[msg->tag.X.u + t + 2] = g.raw[1];
 }
 
-L4_INLINE void L4_MsgPutSimpleStringItem(
-		L4_Msg_t *msg, L4_Word_t t,
-		L4_StringItem_t s)
+L4_INLINE void L4_MsgPutSimpleStringItem(L4_Msg_t *msg,
+                                         L4_Word_t t,
+                                         L4_StringItem_t s)
 {
-	s.X.c = 0;
-	s.X.j = 0;
-	msg->msg[msg->tag.X.u + t + 1] = s.raw[0];
-	msg->msg[msg->tag.X.u + t + 2] = s.raw[1];
+    s.X.c = 0;
+    s.X.j = 0;
+    msg->msg[msg->tag.X.u + t + 1] = s.raw[0];
+    msg->msg[msg->tag.X.u + t + 2] = s.raw[1];
 }
 
-L4_INLINE void L4_MsgPutStringItem(
-		L4_Msg_t *msg, L4_Word_t t,
-		L4_StringItem_t * s)
+L4_INLINE void L4_MsgPutStringItem(L4_Msg_t *msg,
+                                   L4_Word_t t,
+                                   L4_StringItem_t *s)
 {
-	L4_StringItem_t *d = (L4_StringItem_t *) &msg->msg[msg->tag.X.u + t + 1];
-	__L4_Copy_String(d, s);
+    L4_StringItem_t *d = (L4_StringItem_t *) &msg->msg[msg->tag.X.u + t + 1];
+    __L4_Copy_String(d, s);
 }
 
-L4_INLINE void L4_MsgPutCtrlXferItem(L4_Msg_t *msg, L4_Word_t t, L4_CtrlXferItem_t *c)
+L4_INLINE void L4_MsgPutCtrlXferItem(L4_Msg_t *msg,
+                                     L4_Word_t t,
+                                     L4_CtrlXferItem_t *c)
 {
-	L4_Word_t reg = 0, num = 0, mask = c->X.mask;
+    L4_Word_t reg = 0, num = 0, mask = c->X.mask;
 
-	/* Put regs according to mask */
-	for (reg += __L4_Lsb(mask); mask != 0;
-			mask >>= __L4_Lsb(mask) + 1,
-			reg += __L4_Lsb(mask) +1, num++)
-		msg->msg[msg->tag.X.u + t + 2 + num] = c->raw[reg + 1];
-
-	/* Put item */
-	if (num)
-		msg->msg[msg->tag.X.u + t + 1] = c->raw[0];
+    /* Put regs according to mask */
+    for (reg += __L4_Lsb(mask); mask != 0;
+         mask >>= __L4_Lsb(mask) + 1, reg += __L4_Lsb(mask) + 1, num++)
+        msg->msg[msg->tag.X.u + t + 2 + num] = c->raw[reg + 1];
 
+    /* Put item */
+    if (num)
+        msg->msg[msg->tag.X.u + t + 1] = c->raw[0];
 }
 
 L4_INLINE L4_Word_t L4_MsgWord(L4_Msg_t *msg, L4_Word_t u)
 {
-	return msg->msg[u + 1];
+    return msg->msg[u + 1];
 }
 
 L4_INLINE void L4_MsgGetWord(L4_Msg_t *msg, L4_Word_t u, L4_Word_t *w)
 {
-	*w = msg->msg[u + 1];
+    *w = msg->msg[u + 1];
 }
 
-L4_INLINE L4_Word_t L4_MsgGetMapItem(
-		L4_Msg_t *msg, L4_Word_t t,
-		L4_MapItem_t *m)
+L4_INLINE L4_Word_t L4_MsgGetMapItem(L4_Msg_t *msg,
+                                     L4_Word_t t,
+                                     L4_MapItem_t *m)
 {
-	m->raw[0] = msg->msg[msg->tag.X.u + t + 1];
-	m->raw[1] = msg->msg[msg->tag.X.u + t + 2];
-	return 2;
+    m->raw[0] = msg->msg[msg->tag.X.u + t + 1];
+    m->raw[1] = msg->msg[msg->tag.X.u + t + 2];
+    return 2;
 }
 
-L4_INLINE L4_Word_t L4_MsgGetGrantItem(
-		L4_Msg_t *msg, L4_Word_t t,
-		L4_GrantItem_t *g)
+L4_INLINE L4_Word_t L4_MsgGetGrantItem(L4_Msg_t *msg,
+                                       L4_Word_t t,
+                                       L4_GrantItem_t *g)
 {
-	g->raw[0] = msg->msg[msg->tag.X.u + t + 1];
-	g->raw[1] = msg->msg[msg->tag.X.u + t + 2];
-	return 2;
+    g->raw[0] = msg->msg[msg->tag.X.u + t + 1];
+    g->raw[1] = msg->msg[msg->tag.X.u + t + 2];
+    return 2;
 }
 
-L4_INLINE L4_Word_t L4_MsgGetStringItem(
-		L4_Msg_t *msg, L4_Word_t t,
-		L4_StringItem_t *s)
+L4_INLINE L4_Word_t L4_MsgGetStringItem(L4_Msg_t *msg,
+                                        L4_Word_t t,
+                                        L4_StringItem_t *s)
 {
-	L4_StringItem_t *b = (L4_StringItem_t *) &msg->msg[msg->tag.X.u + t + 1];
-	L4_StringItem_t *e = __L4_EndOfString(b, &s);
-	__L4_Copy_String(s, b);
-	return ((L4_Word_t) e - (L4_Word_t) b) / sizeof(L4_Word_t);
+    L4_StringItem_t *b = (L4_StringItem_t *) &msg->msg[msg->tag.X.u + t + 1];
+    L4_StringItem_t *e = __L4_EndOfString(b, &s);
+    __L4_Copy_String(s, b);
+    return ((L4_Word_t) e - (L4_Word_t) b) / sizeof(L4_Word_t);
 }
 
-L4_INLINE L4_Word_t L4_MsgGetCtrlXferItem (L4_Msg_t *msg, L4_Word_t mr, L4_CtrlXferItem_t *c)
+L4_INLINE L4_Word_t L4_MsgGetCtrlXferItem(L4_Msg_t *msg,
+                                          L4_Word_t mr,
+                                          L4_CtrlXferItem_t *c)
 {
-	L4_Word_t reg = 0, num = 0, mask = 0;
+    L4_Word_t reg = 0, num = 0, mask = 0;
 
-	/* Store item */
-	c->raw[0] = msg->msg[mr];
-	mask = c->X.mask;
+    /* Store item */
+    c->raw[0] = msg->msg[mr];
+    mask = c->X.mask;
 
-	/* Store regs according to mask */
-	for (reg += __L4_Lsb(mask); mask != 0;
-			mask >>= __L4_Lsb(mask) + 1,
-			reg += __L4_Lsb(mask) + 1, num++)
-		c->raw[reg + 1] = msg->msg[mr + 1 + num];
+    /* Store regs according to mask */
+    for (reg += __L4_Lsb(mask); mask != 0;
+         mask >>= __L4_Lsb(mask) + 1, reg += __L4_Lsb(mask) + 1, num++)
+        c->raw[reg + 1] = msg->msg[mr + 1 + num];
 
-	return num + 1;
+    return num + 1;
 }
 
 /*
@@ -674,166 +672,165 @@ L4_INLINE L4_Word_t L4_MsgGetCtrlXferItem (L4_Msg_t *msg, L4_Word_t mr, L4_CtrlX
  */
 
 typedef union {
-	L4_Word_t raw;
-	struct {
+    L4_Word_t raw;
+    struct {
 #if defined(L4_BIG_ENDIAN)
-		L4_Word_t	RcvWindow:28 __PLUS32;
-		L4_Word_t	__zeros:2;
-		L4_Word_t	c:1;
-		L4_Word_t	s:1;
+        L4_Word_t RcvWindow : 28 __PLUS32;
+        L4_Word_t __zeros : 2;
+        L4_Word_t c : 1;
+        L4_Word_t s : 1;
 #else
-		L4_Word_t	s:1;
-		L4_Word_t	c:1;
-		L4_Word_t	__zeros:2;
-		L4_Word_t	RcvWindow:28 __PLUS32;
+        L4_Word_t s : 1;
+        L4_Word_t c : 1;
+        L4_Word_t __zeros : 2;
+        L4_Word_t RcvWindow : 28 __PLUS32;
 #endif
-	} X;
+    } X;
 } L4_Acceptor_t;
 
 typedef union {
-	L4_Word_t raw[__L4_NUM_BRS - 1];
-	L4_StringItem_t	string[0];
+    L4_Word_t raw[__L4_NUM_BRS - 1];
+    L4_StringItem_t string[0];
 } L4_MsgBuffer_t;
 
-#define L4_UntypedWordsAcceptor		((L4_Acceptor_t) { raw: 0 })
-#define L4_StringItemsAcceptor		((L4_Acceptor_t) { raw: 1 })
-#define L4_CtrlXferAcceptor		((L4_Acceptor_t) { raw: 2 })
+#define L4_UntypedWordsAcceptor ((L4_Acceptor_t) {raw : 0})
+#define L4_StringItemsAcceptor ((L4_Acceptor_t) {raw : 1})
+#define L4_CtrlXferAcceptor ((L4_Acceptor_t) {raw : 2})
 
 L4_INLINE L4_Acceptor_t L4_MapGrantItems(L4_Fpage_t RcvWindow)
 {
-	L4_Acceptor_t a;
-	a.raw = RcvWindow.raw;
-	a.X.s = 0;
-	a.X.__zeros = 0;
-	return a;
+    L4_Acceptor_t a;
+    a.raw = RcvWindow.raw;
+    a.X.s = 0;
+    a.X.__zeros = 0;
+    return a;
 }
 
-L4_INLINE L4_Acceptor_t L4_AddAcceptor(
-		const L4_Acceptor_t l, const L4_Acceptor_t r)
+L4_INLINE L4_Acceptor_t L4_AddAcceptor(const L4_Acceptor_t l,
+                                       const L4_Acceptor_t r)
 {
-	L4_Acceptor_t a;
-	a.raw = 0;
-	a.X.s = (l.X.s | r.X.s);
-	a.X.RcvWindow = (r.X.RcvWindow != 0) ? r.X.RcvWindow : l.X.RcvWindow;
-	return a;
+    L4_Acceptor_t a;
+    a.raw = 0;
+    a.X.s = (l.X.s | r.X.s);
+    a.X.RcvWindow = (r.X.RcvWindow != 0) ? r.X.RcvWindow : l.X.RcvWindow;
+    return a;
 }
 
-L4_INLINE L4_Acceptor_t L4_AddAcceptorTo(
-		L4_Acceptor_t l, const L4_Acceptor_t r)
+L4_INLINE L4_Acceptor_t L4_AddAcceptorTo(L4_Acceptor_t l, const L4_Acceptor_t r)
 {
-	l.X.s = (l.X.s | r.X.s);
-	if (r.X.RcvWindow != 0)
-		l.X.RcvWindow = r.X.RcvWindow;
-	return l;
+    l.X.s = (l.X.s | r.X.s);
+    if (r.X.RcvWindow != 0)
+        l.X.RcvWindow = r.X.RcvWindow;
+    return l;
 }
 
-L4_INLINE L4_Acceptor_t L4_RemoveAcceptor(
-		const L4_Acceptor_t l, const L4_Acceptor_t r)
+L4_INLINE L4_Acceptor_t L4_RemoveAcceptor(const L4_Acceptor_t l,
+                                          const L4_Acceptor_t r)
 {
-	L4_Acceptor_t a = l;
-	if (r.X.s)
-		a.X.s = 0;
-	if (r.X.RcvWindow != 0)
-		a.X.RcvWindow = 0;
-	return a;
+    L4_Acceptor_t a = l;
+    if (r.X.s)
+        a.X.s = 0;
+    if (r.X.RcvWindow != 0)
+        a.X.RcvWindow = 0;
+    return a;
 }
 
-L4_INLINE L4_Acceptor_t L4_RemoveAcceptorFrom(
-		L4_Acceptor_t l, const L4_Acceptor_t r)
+L4_INLINE L4_Acceptor_t L4_RemoveAcceptorFrom(L4_Acceptor_t l,
+                                              const L4_Acceptor_t r)
 {
-	if (r.X.s)
-		l.X.s = 0;
-	if (r.X.RcvWindow != 0)
-		l.X.RcvWindow = 0;
-	return l;
+    if (r.X.s)
+        l.X.s = 0;
+    if (r.X.RcvWindow != 0)
+        l.X.RcvWindow = 0;
+    return l;
 }
 
 L4_INLINE L4_Bool_t L4_HasStringItems(const L4_Acceptor_t a)
 {
-	return (a.raw & 0x01UL) == 1;
+    return (a.raw & 0x01UL) == 1;
 }
 
 L4_INLINE L4_Bool_t L4_HasMapGrantItems(const L4_Acceptor_t a)
 {
-	return (a.raw & ~0x0fUL) != 0;
+    return (a.raw & ~0x0fUL) != 0;
 }
 
 L4_INLINE L4_Fpage_t L4_RcvWindow(const L4_Acceptor_t a)
 {
-	L4_Fpage_t fp;
-	fp.raw = a.raw;
-	fp.X.rwx = 0;
-	return fp;
+    L4_Fpage_t fp;
+    fp.raw = a.raw;
+    fp.X.rwx = 0;
+    return fp;
 }
 
 L4_INLINE void L4_Accept(const L4_Acceptor_t a)
 {
-	L4_LoadBR (0, a.raw);
+    L4_LoadBR(0, a.raw);
 }
 
-L4_INLINE void L4_AcceptStrings(
-		const L4_Acceptor_t a, L4_MsgBuffer_t *b)
+L4_INLINE void L4_AcceptStrings(const L4_Acceptor_t a, L4_MsgBuffer_t *b)
 {
-	const L4_StringItem_t *prev, *t, *s = (const L4_StringItem_t *) &b->string[0];
-	int n, i = 1;
+    const L4_StringItem_t *prev, *t,
+        *s = (const L4_StringItem_t *) &b->string[0];
+    int n, i = 1;
 
-	L4_LoadBR(0, a.raw);
-	do {
-		prev = s;
-		do {
-			t = s;
-			n = s->X.j + 2;
-			s = (const L4_StringItem_t *) &s->X.str.substring_ptr[n-1];
-			L4_LoadBRs (i, n, (const L4_Word_t *) t);
-			i += n;
-		} while (t->X.c);
-	} while (prev->X.C);
+    L4_LoadBR(0, a.raw);
+    do {
+        prev = s;
+        do {
+            t = s;
+            n = s->X.j + 2;
+            s = (const L4_StringItem_t *) &s->X.str.substring_ptr[n - 1];
+            L4_LoadBRs(i, n, (const L4_Word_t *) t);
+            i += n;
+        } while (t->X.c);
+    } while (prev->X.C);
 }
 
 L4_INLINE L4_Acceptor_t L4_Accepted(void)
 {
-	L4_Acceptor_t a;
-	L4_StoreBR(0, &a.raw);
-	return a;
+    L4_Acceptor_t a;
+    L4_StoreBR(0, &a.raw);
+    return a;
 }
 
 L4_INLINE void L4_MsgBufferClear(L4_MsgBuffer_t *b)
 {
-	b->raw[0] = b->raw[2] = 0;
+    b->raw[0] = b->raw[2] = 0;
 }
 
-L4_INLINE void L4_MsgBufferAppendSimpleRcvString(
-		L4_MsgBuffer_t *b, L4_StringItem_t s)
+L4_INLINE void L4_MsgBufferAppendSimpleRcvString(L4_MsgBuffer_t *b,
+                                                 L4_StringItem_t s)
 {
-	L4_StringItem_t *prev, *tmp;
+    L4_StringItem_t *prev, *tmp;
 
-	s.X.j = 0;
-	s.X.c = 0;
+    s.X.j = 0;
+    s.X.c = 0;
 
-	if (b->raw[0] || b->raw[2]) {
-		tmp = __L4_EndOfStrings((L4_StringItem_t *) &b[0], &prev);
-		prev->X.C = 1;
-		*tmp = s;
-	} else {
-		b->raw[2] = ~0UL;
-		((L4_StringItem_t *) b)[0] = s;
-		b->string[0].X.C = 0;
-	}
+    if (b->raw[0] || b->raw[2]) {
+        tmp = __L4_EndOfStrings((L4_StringItem_t *) &b[0], &prev);
+        prev->X.C = 1;
+        *tmp = s;
+    } else {
+        b->raw[2] = ~0UL;
+        ((L4_StringItem_t *) b)[0] = s;
+        b->string[0].X.C = 0;
+    }
 }
 
-L4_INLINE void L4_MsgBufferAppendRcvString(
-		L4_MsgBuffer_t *b, L4_StringItem_t *s)
+L4_INLINE void L4_MsgBufferAppendRcvString(L4_MsgBuffer_t *b,
+                                           L4_StringItem_t *s)
 {
-	L4_StringItem_t *prev, *tmp;
+    L4_StringItem_t *prev, *tmp;
 
-	if (b->raw[0] || b->raw[2]) {
-		tmp = __L4_EndOfStrings((L4_StringItem_t *) &b->raw[0], &prev);
-		prev->X.C = 1;
-	} else
-		tmp = (L4_StringItem_t *) &b->raw[0];
+    if (b->raw[0] || b->raw[2]) {
+        tmp = __L4_EndOfStrings((L4_StringItem_t *) &b->raw[0], &prev);
+        prev->X.C = 1;
+    } else
+        tmp = (L4_StringItem_t *) &b->raw[0];
 
-	__L4_Copy_String(tmp, s);
-	tmp->X.C = 0;
+    __L4_Copy_String(tmp, s);
+    tmp->X.C = 0;
 }
 
 #undef __PLUS32
diff --git a/user/include/l4/misc.h b/user/include/l4/misc.h
index e7ee5a1b..255ec16a 100644
--- a/user/include/l4/misc.h
+++ b/user/include/l4/misc.h
@@ -12,27 +12,27 @@
 /*
  * Memory attributes
  */
-#define L4_DefaultMemory	0
+#define L4_DefaultMemory 0
 
 /*
  * Derived functions
  */
 L4_INLINE L4_Word_t L4_Set_PageAttribute(L4_Fpage_t f, L4_Word_t attribute)
 {
-	L4_Word_t attributes[4];
-	attributes[0] = attribute;
+    L4_Word_t attributes[4];
+    attributes[0] = attribute;
 
-	L4_Set_Rights(&f, 0);			/* Set a to 0 */
-	L4_LoadMR(0, f.raw);
-	return L4_MemoryControl(0, attributes);
+    L4_Set_Rights(&f, 0); /* Set a to 0 */
+    L4_LoadMR(0, f.raw);
+    return L4_MemoryControl(0, attributes);
 }
 
-L4_INLINE L4_Word_t L4_Set_PageAttributes(
-		L4_Word_t n, L4_Fpage_t *f,
-		const L4_Word_t *attributes)
+L4_INLINE L4_Word_t L4_Set_PageAttributes(L4_Word_t n,
+                                          L4_Fpage_t *f,
+                                          const L4_Word_t *attributes)
 {
-	L4_LoadMRs (0, n, (L4_Word_t *) f);
-	return L4_MemoryControl (n - 1, attributes);
+    L4_LoadMRs(0, n, (L4_Word_t *) f);
+    return L4_MemoryControl(n - 1, attributes);
 }
 
 #endif /* !__L4__MISC_H__ */
diff --git a/user/include/l4/pagefault.h b/user/include/l4/pagefault.h
index 2fd7a06d..a9f8ed41 100644
--- a/user/include/l4/pagefault.h
+++ b/user/include/l4/pagefault.h
@@ -10,29 +10,29 @@
 #include __L4_INC_ARCH(message.h)
 
 #if defined(L4_64BIT)
-# define __PLUS32	+ 32
+#define __PLUS32 +32
 #else
-# define __PLUS32
+#define __PLUS32
 #endif
 
 typedef union L4_PfRequest {
     L4_Word_t raw[3];
     struct {
 #if defined(L4_BIG_ENDIAN)
-	unsigned	__padding:12 __PLUS32:	/* -2 */
-	unsigned	wrx:4;
-	unsigned	__zero:4;
-	unsigned	t:6;			/* 0 */
-	unsigned	u:6;			/* 2 */
+        unsigned __padding : 12 __PLUS32 : /* -2 */
+                                           unsigned wrx : 4;
+        unsigned __zero : 4;
+        unsigned t : 6; /* 0 */
+        unsigned u : 6; /* 2 */
 #else
-	unsigned	u:6;			/* 2 */
-	unsigned	t:6;			/* 0 */
-	unsigned	__zero:4;
-	unsigned	wrx:4;
-	unsigned	__padding:12 __PLUS32:	/* -2 */
+        unsigned u : 6; /* 2 */
+        unsigned t : 6; /* 0 */
+        unsigned __zero : 4;
+        unsigned wrx : 4;
+        unsigned __padding : 12 __PLUS32 : /* -2 */
 #endif
-	L4_Word_t	fault_address;
-	L4_Word_t	fault_ip;
+        L4_Word_t fault_address;
+        L4_Word_t fault_ip;
     } X;
 } L4_PfRequest_t;
 
@@ -40,17 +40,17 @@ typedef union L4_PfReply {
     L4_Word_t raw[3];
     struct {
 #if defined(L4_BIG_ENDIAN)
-	unsigned	__padding:16 __PLUS32:	/* 0 */
-	unsigned	__zero:4;
-	unsigned	t:6;			/* 2 */
-	unsigned	u:6;			/* 0 */
+        unsigned __padding : 16 __PLUS32 : /* 0 */
+                                           unsigned __zero : 4;
+        unsigned t : 6; /* 2 */
+        unsigned u : 6; /* 0 */
 #else
-	unsigned	u:6;			/* 0 */
-	unsigned	t:6;			/* 2 */
-	unsigned	__zero:4;
-	unsigned	__padding:16 __PLUS32:	/* 0 */
+        unsigned u : 6; /* 0 */
+        unsigned t : 6; /* 2 */
+        unsigned __zero : 4;
+        unsigned __padding : 16 __PLUS32 : /* 0 */
 #endif
-	L4_MapItem_t MapItem;
+        L4_MapItem_t MapItem;
     } X;
 } L4_PfReply_t;
 
diff --git a/user/include/l4/pager.h b/user/include/l4/pager.h
index 0cf0c3b0..e79e5e17 100644
--- a/user/include/l4/pager.h
+++ b/user/include/l4/pager.h
@@ -6,18 +6,18 @@
 #ifndef __PAGER_H__
 #define __PAGER_H__
 
-#define RES_FPAGE		0
-#define HEAP_FPAGE		1
+#define RES_FPAGE 0
+#define HEAP_FPAGE 1
 
 
-#define THREAD_MAX_NUM	32
+#define THREAD_MAX_NUM 32
 
 /* msg tag label */
-#define PAGER_REQUEST_LABEL		0xf000
-#define PAGER_REPLY_LABEL		0xf001
+#define PAGER_REQUEST_LABEL 0xf000
+#define PAGER_REPLY_LABEL 0xf001
 
-#include <user_runtime.h>
 #include <platform/link.h>
+#include <user_runtime.h>
 
 enum {
     PAGER_REQ_TYPE,
@@ -43,10 +43,10 @@ __USER_TEXT
 L4_ThreadId_t pager_create_thread(void);
 
 __USER_TEXT
-L4_Word_t pager_start_thread(L4_ThreadId_t tid, void * (*thr_routine)(void *),
+L4_Word_t pager_start_thread(L4_ThreadId_t tid,
+                             void *(*thr_routine)(void *),
                              void *arg);
 
 __USER_TEXT
-void pager_thread(user_struct *user,
-                  void * (*entry_main)(void *user));
+void pager_thread(user_struct *user, void *(*entry_main)(void *user));
 #endif
diff --git a/user/include/l4/platform/arch.h b/user/include/l4/platform/arch.h
index 537c9cc6..e678aed0 100644
--- a/user/include/l4/platform/arch.h
+++ b/user/include/l4/platform/arch.h
@@ -1,187 +1,187 @@
-/* Copyright (c) 2002, 2003, 2005-2010 Karlsruhe University. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
+/* Copyright (c) 2002, 2003, 2005-2010 Karlsruhe University. All rights
+ * reserved. Use of this source code is governed by a BSD-style license that can
+ * be found in the LICENSE file.
  */
 
 #ifndef __L4_PLATFORM_ARCH_H__
 #define __L4_PLATFORM_ARCH_H__
 
-#include <l4/platform/specials.h>
-#include <l4/kip.h>
 #include <l4/ipc.h>
+#include <l4/kip.h>
+#include <l4/platform/specials.h>
 
 typedef union {
-	L4_Word_t	raw;
-	struct {
-		unsigned	rwx: 4;
-		unsigned	__two: 6;
-		unsigned	s: 6;
-		unsigned	p: 16;
-	} X;
+    L4_Word_t raw;
+    struct {
+        unsigned rwx : 4;
+        unsigned __two : 6;
+        unsigned s : 6;
+        unsigned p : 16;
+    } X;
 } L4_IoFpage_t;
 
 #if defined(__cplusplus)
 L4_INLINE L4_Fpage_t L4_Fpage(L4_IoFpage_t f)
 {
-	L4_Fpage_t out;
-	out.raw = f.raw;
-	return out;
+    L4_Fpage_t out;
+    out.raw = f.raw;
+    return out;
 }
 #endif
 
 L4_INLINE L4_Fpage_t L4_IoFpage(L4_Word_t BasePort, int FpageSize)
 {
-	L4_IoFpage_t fp;
-	L4_Fpage_t out;
-	L4_Word_t msb = __L4_Msb(FpageSize);
-	fp.X.p = BasePort;
-	fp.X.__two = 2;
-	fp.X.s = (1UL << msb) < (L4_Word_t) FpageSize ? msb + 1 : msb;
-	fp.X.rwx = L4_NoAccess;
-	out.raw = fp.raw;
-	return out;
+    L4_IoFpage_t fp;
+    L4_Fpage_t out;
+    L4_Word_t msb = __L4_Msb(FpageSize);
+    fp.X.p = BasePort;
+    fp.X.__two = 2;
+    fp.X.s = (1UL << msb) < (L4_Word_t) FpageSize ? msb + 1 : msb;
+    fp.X.rwx = L4_NoAccess;
+    out.raw = fp.raw;
+    return out;
 }
 
 L4_INLINE L4_Fpage_t L4_IoFpageLog2(L4_Word_t BasePort, int FpageSize)
 {
-	L4_IoFpage_t fp;
-	L4_Fpage_t out;
-	fp.X.p = BasePort;
-	fp.X.__two = 2;
-	fp.X.s = FpageSize;
-	fp.X.rwx = L4_NoAccess;
-	out.raw = fp.raw;
-	return out;
+    L4_IoFpage_t fp;
+    L4_Fpage_t out;
+    fp.X.p = BasePort;
+    fp.X.__two = 2;
+    fp.X.s = FpageSize;
+    fp.X.rwx = L4_NoAccess;
+    out.raw = fp.raw;
+    return out;
 }
 
 L4_INLINE L4_Word_t L4_IoFpagePort(L4_Fpage_t f)
 {
-	L4_IoFpage_t iofp;
-	iofp.raw = f.raw;
-	return iofp.X.p;
+    L4_IoFpage_t iofp;
+    iofp.raw = f.raw;
+    return iofp.X.p;
 }
 
 L4_INLINE L4_Word_t L4_IoFpageSize(L4_Fpage_t f)
 {
-	L4_IoFpage_t iofp;
-	iofp.raw = f.raw;
-	return (1UL << iofp.X.s);
+    L4_IoFpage_t iofp;
+    iofp.raw = f.raw;
+    return (1UL << iofp.X.s);
 }
 
 L4_INLINE L4_Word_t L4_IoFpageSizeLog2(L4_Fpage_t f)
 {
-	L4_IoFpage_t iofp;
-	iofp.raw = f.raw;
-	return iofp.X.s;
+    L4_IoFpage_t iofp;
+    iofp.raw = f.raw;
+    return iofp.X.s;
 }
 
 L4_INLINE L4_Bool_t L4_IsIoFpage(L4_Fpage_t f)
 {
-	L4_IoFpage_t iofp;
-	iofp.raw = f.raw;
-	return (iofp.X.__two == 2);
-}
-
-
-#define L4_CTRLXFER_GPREGS_ID		(0)
-#define L4_CTRLXFER_FPUREGS_ID		(1)
-#define L4_CTRLXFER_CREGS_ID		(2)
-#define L4_CTRLXFER_DREGS_ID		(3)
-#define L4_CTRLXFER_CSREGS_ID		(4)
-#define L4_CTRLXFER_SSREGS_ID		(5)
-#define L4_CTRLXFER_DSREGS_ID		(6)
-#define L4_CTRLXFER_ESREGS_ID		(7)
-#define L4_CTRLXFER_FSREGS_ID		(8)
-#define L4_CTRLXFER_GSREGS_ID		(9)
-#define L4_CTRLXFER_TRREGS_ID		(10)
-#define L4_CTRLXFER_LDTRREGS_ID		(11)
-#define L4_CTRLXFER_IDTRREGS_ID		(12)
-#define L4_CTRLXFER_GDTRREGS_ID		(13)
-#define L4_CTRLXFER_NONREGEXC_ID	(14)
-#define L4_CTRLXFER_EXECCTRL_ID		(15)
-#define L4_CTRLXFER_OTHERREGS_ID	(16)
-#define L4_CTRLXFER_INVALID_ID		(255)
-#define L4_CTRLXFER_FAULT_MASK(id)	(1 << id)
-
-#define L4_CTRLXFER_GPREGS_SIZE		(10)
-#define L4_CTRLXFER_FPUREGS_SIZE	(1)
-#define L4_CTRLXFER_CREGS_SIZE		(8)
-#define L4_CTRLXFER_DREGS_SIZE		(6)
-#define L4_CTRLXFER_SEGREG_SIZE		(4)
-#define L4_CTRLXFER_DTRREG_SIZE		(2)
-#define L4_CTRLXFER_NONREGEXC_SIZE	(10)
-#define L4_CTRLXFER_EXECCTRL_SIZE	(3)
-#define L4_CTRLXFER_OTHERREGS_SIZE	(9)
-
-#define L4_FAULT_PAGEFAULT		2
-#define L4_FAULT_EXCEPTION		3
-#define L4_FAULT_PREEMPTION		5
-#define L4_CTRLXFER_HVM_FAULT(id)	(9+id)
-#define L4_CTRLXFER_FAULT_ID_MASK(id)	(1ULL << id)
-
-#define L4_CTRLXFER_GPREGS_EIP		(0)
-#define L4_CTRLXFER_GPREGS_EFLAGS	(1)
-#define L4_CTRLXFER_GPREGS_EDI		(2)
-#define L4_CTRLXFER_GPREGS_ESI		(3)
-#define L4_CTRLXFER_GPREGS_EBP		(4)
-#define L4_CTRLXFER_GPREGS_ESP		(5)
-#define L4_CTRLXFER_GPREGS_EBX		(6)
-#define L4_CTRLXFER_GPREGS_EDX		(7)
-#define L4_CTRLXFER_GPREGS_ECX		(8)
-#define L4_CTRLXFER_GPREGS_EAX		(9)
-
-#define L4_CTRLXFER_CREGS_CR0		(0)
-#define L4_CTRLXFER_CREGS_CR0_SHADOW	(1)
-#define L4_CTRLXFER_CREGS_CR0_MASK	(2)
-#define L4_CTRLXFER_CREGS_CR2		(3)
-#define L4_CTRLXFER_CREGS_CR3		(4)
-#define L4_CTRLXFER_CREGS_CR4		(5)
-#define L4_CTRLXFER_CREGS_CR4_SHADOW	(6)
-#define L4_CTRLXFER_CREGS_CR4_MASK	(7)
-
-#define L4_CTRLXFER_DREGS_DR0		(0)
-#define L4_CTRLXFER_DREGS_DR1		(1)
-#define L4_CTRLXFER_DREGS_DR2		(2)
-#define L4_CTRLXFER_DREGS_DR3		(3)
-#define L4_CTRLXFER_DREGS_DR6		(4)
-#define L4_CTRLXFER_DREGS_DR7		(5)
-
-#define L4_CTRLXFER_CSREGS_CS		(0)
-#define L4_CTRLXFER_CSREGS_CS_BASE	(1)
-#define L4_CTRLXFER_CSREGS_CS_LIMIT	(2)
-#define L4_CTRLXFER_CSREGS_CS_ATTR	(3)
-
-#define L4_CTRLXFER_NONREGEXC_ACTIVITY	(0)
-#define L4_CTRLXFER_NONREGEXC_INT	(1)
-#define L4_CTRLXFER_NONREGEXC_DBG_EXC	(2)
-#define L4_CTRLXFER_NONREGEXC_ENT_INFO	(3)
-#define L4_CTRLXFER_NONREGEXC_ENT_EEC	(4)
-#define L4_CTRLXFER_NONREGEXC_ENT_ILEN	(5)
-#define L4_CTRLXFER_NONREGEXC_EX_INFO	(6)
-#define L4_CTRLXFER_NONREGEXC_EX_EEC	(7)
-#define L4_CTRLXFER_NONREGEXC_IDT_INFO	(8)
-#define L4_CTRLXFER_NONREGEXC_IDT_EEC	(9)
-
-#define L4_CTRLXFER_EXEC_PIN		(0)
-#define L4_CTRLXFER_EXEC_CPU		(1)
-#define L4_CTRLXFER_EXEC_EXC_BITMAP	(2)
-
-#define L4_CTRLXFER_OTHERREGS_SYS_CS	 (0)
-#define L4_CTRLXFER_OTHERREGS_SYS_EIP	 (1)
-#define L4_CTRLXFER_OTHERREGS_SYS_ESP	 (2)
-#define L4_CTRLXFER_OTHERREGS_DBG_LOW	 (3)
-#define L4_CTRLXFER_OTHERREGS_DBG_HIGH	 (4)
-#define L4_CTRLXFER_OTHERREGS_RDTSC_LOW	 (5)
+    L4_IoFpage_t iofp;
+    iofp.raw = f.raw;
+    return (iofp.X.__two == 2);
+}
+
+
+#define L4_CTRLXFER_GPREGS_ID (0)
+#define L4_CTRLXFER_FPUREGS_ID (1)
+#define L4_CTRLXFER_CREGS_ID (2)
+#define L4_CTRLXFER_DREGS_ID (3)
+#define L4_CTRLXFER_CSREGS_ID (4)
+#define L4_CTRLXFER_SSREGS_ID (5)
+#define L4_CTRLXFER_DSREGS_ID (6)
+#define L4_CTRLXFER_ESREGS_ID (7)
+#define L4_CTRLXFER_FSREGS_ID (8)
+#define L4_CTRLXFER_GSREGS_ID (9)
+#define L4_CTRLXFER_TRREGS_ID (10)
+#define L4_CTRLXFER_LDTRREGS_ID (11)
+#define L4_CTRLXFER_IDTRREGS_ID (12)
+#define L4_CTRLXFER_GDTRREGS_ID (13)
+#define L4_CTRLXFER_NONREGEXC_ID (14)
+#define L4_CTRLXFER_EXECCTRL_ID (15)
+#define L4_CTRLXFER_OTHERREGS_ID (16)
+#define L4_CTRLXFER_INVALID_ID (255)
+#define L4_CTRLXFER_FAULT_MASK(id) (1 << id)
+
+#define L4_CTRLXFER_GPREGS_SIZE (10)
+#define L4_CTRLXFER_FPUREGS_SIZE (1)
+#define L4_CTRLXFER_CREGS_SIZE (8)
+#define L4_CTRLXFER_DREGS_SIZE (6)
+#define L4_CTRLXFER_SEGREG_SIZE (4)
+#define L4_CTRLXFER_DTRREG_SIZE (2)
+#define L4_CTRLXFER_NONREGEXC_SIZE (10)
+#define L4_CTRLXFER_EXECCTRL_SIZE (3)
+#define L4_CTRLXFER_OTHERREGS_SIZE (9)
+
+#define L4_FAULT_PAGEFAULT 2
+#define L4_FAULT_EXCEPTION 3
+#define L4_FAULT_PREEMPTION 5
+#define L4_CTRLXFER_HVM_FAULT(id) (9 + id)
+#define L4_CTRLXFER_FAULT_ID_MASK(id) (1ULL << id)
+
+#define L4_CTRLXFER_GPREGS_EIP (0)
+#define L4_CTRLXFER_GPREGS_EFLAGS (1)
+#define L4_CTRLXFER_GPREGS_EDI (2)
+#define L4_CTRLXFER_GPREGS_ESI (3)
+#define L4_CTRLXFER_GPREGS_EBP (4)
+#define L4_CTRLXFER_GPREGS_ESP (5)
+#define L4_CTRLXFER_GPREGS_EBX (6)
+#define L4_CTRLXFER_GPREGS_EDX (7)
+#define L4_CTRLXFER_GPREGS_ECX (8)
+#define L4_CTRLXFER_GPREGS_EAX (9)
+
+#define L4_CTRLXFER_CREGS_CR0 (0)
+#define L4_CTRLXFER_CREGS_CR0_SHADOW (1)
+#define L4_CTRLXFER_CREGS_CR0_MASK (2)
+#define L4_CTRLXFER_CREGS_CR2 (3)
+#define L4_CTRLXFER_CREGS_CR3 (4)
+#define L4_CTRLXFER_CREGS_CR4 (5)
+#define L4_CTRLXFER_CREGS_CR4_SHADOW (6)
+#define L4_CTRLXFER_CREGS_CR4_MASK (7)
+
+#define L4_CTRLXFER_DREGS_DR0 (0)
+#define L4_CTRLXFER_DREGS_DR1 (1)
+#define L4_CTRLXFER_DREGS_DR2 (2)
+#define L4_CTRLXFER_DREGS_DR3 (3)
+#define L4_CTRLXFER_DREGS_DR6 (4)
+#define L4_CTRLXFER_DREGS_DR7 (5)
+
+#define L4_CTRLXFER_CSREGS_CS (0)
+#define L4_CTRLXFER_CSREGS_CS_BASE (1)
+#define L4_CTRLXFER_CSREGS_CS_LIMIT (2)
+#define L4_CTRLXFER_CSREGS_CS_ATTR (3)
+
+#define L4_CTRLXFER_NONREGEXC_ACTIVITY (0)
+#define L4_CTRLXFER_NONREGEXC_INT (1)
+#define L4_CTRLXFER_NONREGEXC_DBG_EXC (2)
+#define L4_CTRLXFER_NONREGEXC_ENT_INFO (3)
+#define L4_CTRLXFER_NONREGEXC_ENT_EEC (4)
+#define L4_CTRLXFER_NONREGEXC_ENT_ILEN (5)
+#define L4_CTRLXFER_NONREGEXC_EX_INFO (6)
+#define L4_CTRLXFER_NONREGEXC_EX_EEC (7)
+#define L4_CTRLXFER_NONREGEXC_IDT_INFO (8)
+#define L4_CTRLXFER_NONREGEXC_IDT_EEC (9)
+
+#define L4_CTRLXFER_EXEC_PIN (0)
+#define L4_CTRLXFER_EXEC_CPU (1)
+#define L4_CTRLXFER_EXEC_EXC_BITMAP (2)
+
+#define L4_CTRLXFER_OTHERREGS_SYS_CS (0)
+#define L4_CTRLXFER_OTHERREGS_SYS_EIP (1)
+#define L4_CTRLXFER_OTHERREGS_SYS_ESP (2)
+#define L4_CTRLXFER_OTHERREGS_DBG_LOW (3)
+#define L4_CTRLXFER_OTHERREGS_DBG_HIGH (4)
+#define L4_CTRLXFER_OTHERREGS_RDTSC_LOW (5)
 #define L4_CTRLXFER_OTHERREGS_RDTSC_HIGH (6)
-#define L4_CTRLXFER_OTHERREGS_VAPIC	 (7)
-#define L4_CTRLXFER_OTHERREGS_TPR_THRSH	 (8)
+#define L4_CTRLXFER_OTHERREGS_VAPIC (7)
+#define L4_CTRLXFER_OTHERREGS_TPR_THRSH (8)
 
 
-#define L4_CTRLXFER_REG_ID(id, reg)	((id * 0x10) + reg)
+#define L4_CTRLXFER_REG_ID(id, reg) ((id * 0x10) + reg)
 
-#endif	/* __L4_PLATFORM_ARCH_H__ */
+#endif /* __L4_PLATFORM_ARCH_H__ */
 
-#if 0	/* FIXME: IA32 specific implementation */
+#if 0 /* FIXME: IA32 specific implementation */
 /*
  * IA32 GPRegs
  */
@@ -658,31 +658,31 @@ L4_INLINE L4_Word_t L4_MsgGetOtherRegsCtrlXferItem(L4_Msg_t *msg, L4_Word_t mr,
 }
 
 #if defined(__cplusplus)
-#define DECLARE_INIT_SET_APPEND(type)					\
-L4_INLINE void L4_Init (L4_##type##_t *c)				\
-{									\
-    L4_##type##Init(c);							\
-}									\
-									\
-L4_INLINE void L4_Set (L4_##type##_t *c, L4_Word_t reg, L4_Word_t val)	\
-{									\
-    L4_##type##Set(c, reg, val);					\
-}									\
-									\
-L4_INLINE void L4_Append (L4_Msg_t *msg, L4_##type##_t *c)	        \
-{									\
-    L4_MsgAppend##type(msg, c);						\
-}                                                                       \
-                                                                        \
-L4_INLINE void L4_Put (L4_Msg_t *msg, L4_Word_t t, L4_##type##_t *c)    \
-{									\
-    L4_MsgPut##type(msg, t, c);                                         \
-}                                                                       \
-                                                                        \
-L4_INLINE L4_Word_t L4_Get (L4_Msg_t *msg, L4_Word_t mr, L4_##type##_t *c) \
-{									\
-    return L4_MsgGet##type(msg, mr, c);                                 \
-}
+#define DECLARE_INIT_SET_APPEND(type)                                         \
+    L4_INLINE void L4_Init(L4_##type##_t *c)                                  \
+    {                                                                         \
+        L4_##type##Init(c);                                                   \
+    }                                                                         \
+                                                                              \
+    L4_INLINE void L4_Set(L4_##type##_t *c, L4_Word_t reg, L4_Word_t val)     \
+    {                                                                         \
+        L4_##type##Set(c, reg, val);                                          \
+    }                                                                         \
+                                                                              \
+    L4_INLINE void L4_Append(L4_Msg_t *msg, L4_##type##_t *c)                 \
+    {                                                                         \
+        L4_MsgAppend##type(msg, c);                                           \
+    }                                                                         \
+                                                                              \
+    L4_INLINE void L4_Put(L4_Msg_t *msg, L4_Word_t t, L4_##type##_t *c)       \
+    {                                                                         \
+        L4_MsgPut##type(msg, t, c);                                           \
+    }                                                                         \
+                                                                              \
+    L4_INLINE L4_Word_t L4_Get(L4_Msg_t *msg, L4_Word_t mr, L4_##type##_t *c) \
+    {                                                                         \
+        return L4_MsgGet##type(msg, mr, c);                                   \
+    }
 
 DECLARE_INIT_SET_APPEND(GPRegsCtrlXferItem)
 DECLARE_INIT_SET_APPEND(CRegsCtrlXferItem)
@@ -691,31 +691,31 @@ DECLARE_INIT_SET_APPEND(NonRegExcCtrlXferItem)
 DECLARE_INIT_SET_APPEND(ExecCtrlXferItem)
 DECLARE_INIT_SET_APPEND(OtherRegsCtrlXferItem)
 
-#define DECLARE_INIT_SET_APPEND_ID(type)                                \
-L4_INLINE void L4_Init (L4_##type##_t *c, L4_Word_t id)                 \
-{									\
-    L4_##type##Init(c, id);                                             \
-}									\
-									\
-L4_INLINE void L4_Set (L4_##type##_t *c, L4_Word_t reg, L4_Word_t val)	\
-{									\
-    L4_##type##Set(c, reg, val);					\
-}									\
-									\
-L4_INLINE void L4_Append (L4_Msg_t *msg, L4_##type##_t *c)	        \
-{									\
-    L4_MsgAppend##type(msg, c);						\
-}                                                                       \
-                                                                        \
-L4_INLINE void L4_Put (L4_Msg_t *msg, L4_Word_t t, L4_##type##_t *c)    \
-{									\
-    L4_MsgPut##type(msg, t, c);                                         \
-}                                                                       \
-                                                                        \
-L4_INLINE L4_Word_t L4_Get (L4_Msg_t *msg, L4_Word_t mr, L4_##type##_t *c) \
-{									\
-    return L4_MsgGet##type(msg, mr, c);                                 \
-}
+#define DECLARE_INIT_SET_APPEND_ID(type)                                      \
+    L4_INLINE void L4_Init(L4_##type##_t *c, L4_Word_t id)                    \
+    {                                                                         \
+        L4_##type##Init(c, id);                                               \
+    }                                                                         \
+                                                                              \
+    L4_INLINE void L4_Set(L4_##type##_t *c, L4_Word_t reg, L4_Word_t val)     \
+    {                                                                         \
+        L4_##type##Set(c, reg, val);                                          \
+    }                                                                         \
+                                                                              \
+    L4_INLINE void L4_Append(L4_Msg_t *msg, L4_##type##_t *c)                 \
+    {                                                                         \
+        L4_MsgAppend##type(msg, c);                                           \
+    }                                                                         \
+                                                                              \
+    L4_INLINE void L4_Put(L4_Msg_t *msg, L4_Word_t t, L4_##type##_t *c)       \
+    {                                                                         \
+        L4_MsgPut##type(msg, t, c);                                           \
+    }                                                                         \
+                                                                              \
+    L4_INLINE L4_Word_t L4_Get(L4_Msg_t *msg, L4_Word_t mr, L4_##type##_t *c) \
+    {                                                                         \
+        return L4_MsgGet##type(msg, mr, c);                                   \
+    }
 
 DECLARE_INIT_SET_APPEND_ID(SegCtrlXferItem)
 DECLARE_INIT_SET_APPEND_ID(DTRCtrlXferItem)
@@ -725,45 +725,45 @@ DECLARE_INIT_SET_APPEND_ID(DTRCtrlXferItem)
 /**********************************************************************
  *                       EVT Logging
  **********************************************************************/
-#define L4_LOG_SELECTOR_SIZE		(4096)
+#define L4_LOG_SELECTOR_SIZE (4096)
 /*
  * Must be a power f 2
  */
-#define L4_LOG_LD_MAX_RESOURCES                 2
-#define L4_LOG_MAX_RESOURCES                    (1 <<  L4_LOG_LD_MAX_RESOURCES)
-#define L4_LOG_RESOURCE_PMC			0  /* performance counters at context switch */
+#define L4_LOG_LD_MAX_RESOURCES 2
+#define L4_LOG_MAX_RESOURCES (1 << L4_LOG_LD_MAX_RESOURCES)
+#define L4_LOG_RESOURCE_PMC 0 /* performance counters at context switch */
 
-#define L4_LOG_MAX_LOGIDS			32
-#define L4_LOG_NULL_LOGID			(0xFFFFFFFF)
-#define L4_LOG_IDLE_LOGID			(0)
-#define L4_LOG_ROOTSERVER_LOGID                 (1)
+#define L4_LOG_MAX_LOGIDS 32
+#define L4_LOG_NULL_LOGID (0xFFFFFFFF)
+#define L4_LOG_IDLE_LOGID (0)
+#define L4_LOG_ROOTSERVER_LOGID (1)
 
-#define L4_LOG_EVENT_BIT			 5
-#define L4_LOG_CURRENT_BIT			 6
-#define L4_LOG_CORRESPONDENT_BIT		 7
-#define L4_LOG_TIMESTAMP_BIT                     8
-#define L4_LOG_PADDING_BIT			 10
-#define L4_LOG_COUNTER_BIT			 12
-#define L4_LOG_ADD_BIT                           13
-#define L4_LOG_ALL_FLAGS			 0xFFE0
+#define L4_LOG_EVENT_BIT 5
+#define L4_LOG_CURRENT_BIT 6
+#define L4_LOG_CORRESPONDENT_BIT 7
+#define L4_LOG_TIMESTAMP_BIT 8
+#define L4_LOG_PADDING_BIT 10
+#define L4_LOG_COUNTER_BIT 12
+#define L4_LOG_ADD_BIT 13
+#define L4_LOG_ALL_FLAGS 0xFFE0
 
 
-#define L4_LOG_TIMESTAMP_OFF                     0x0
-#define L4_LOG_TIMESTAMP_VIRTUAL		0x1
-#define L4_LOG_TIMESTAMP_RDTSC                  0x2
-#define L4_LOG_TIMESTAMP_TICK                   0x3
+#define L4_LOG_TIMESTAMP_OFF 0x0
+#define L4_LOG_TIMESTAMP_VIRTUAL 0x1
+#define L4_LOG_TIMESTAMP_RDTSC 0x2
+#define L4_LOG_TIMESTAMP_TICK 0x3
 
-#define L4_LOG_TIMESTAMP_ENABLED	(0x3 << LOG_TIMESTAMP_BIT)
-#define L4_LOG_TIMESTAMP_NOT_VIRTUAL	(0x2 << LOG_TIMESTAMP_BIT)
-#define L4_LOG_TIMESTAMP_RDTSC_OR_TICK	(0x1 << LOG_TIMESTAMP_BIT)
+#define L4_LOG_TIMESTAMP_ENABLED (0x3 << LOG_TIMESTAMP_BIT)
+#define L4_LOG_TIMESTAMP_NOT_VIRTUAL (0x2 << LOG_TIMESTAMP_BIT)
+#define L4_LOG_TIMESTAMP_RDTSC_OR_TICK (0x1 << LOG_TIMESTAMP_BIT)
 
-#define L4_LOG_CPU_TSC_PRECISION	8
+#define L4_LOG_CPU_TSC_PRECISION 8
 
-#define L4_LOG_SIZE_MASK_MASK		(0x1F)
-#define L4_LOG_MAX_LOG_SIZE_MASK        (32768 -1)
-#define L4_LOG_PADDING_MASK             (0x3 << LOG_PADDING_BIT)
+#define L4_LOG_SIZE_MASK_MASK (0x1F)
+#define L4_LOG_MAX_LOG_SIZE_MASK (32768 - 1)
+#define L4_LOG_PADDING_MASK (0x3 << LOG_PADDING_BIT)
 
-#define L4_LOG_SIZE_N_PADDING_MASK	(LOG_SIZE_MASK_MASK | LOG_PADDING_MASK)
+#define L4_LOG_SIZE_N_PADDING_MASK (LOG_SIZE_MASK_MASK | LOG_PADDING_MASK)
 
 typedef L4_Word16_t                     L4_LogSel_t;
 
@@ -791,31 +791,36 @@ typedef union {
 } __attribute__((packed)) L4_LogCtrl_t;
 
 
-#define L4_LOG_GET_IDX(offset, c)	\
-    (L4_Word_t* ) (c + (offset / sizeof(L4_LogFile_Control_t)))
+#define L4_LOG_GET_IDX(offset, c) \
+    (L4_Word_t *) (c + (offset / sizeof(L4_LogFile_Control_t)))
 
-#define L4_LOG_MASK(idx, mask)       ((L4_Word_t) (idx) & (mask))
+#define L4_LOG_MASK(idx, mask) ((L4_Word_t) (idx) & (mask))
 
-#define L4_LOG_INC_LOG(idx, ctrl)      \
-    idx = (L4_Word_t *) (L4_LOG_MASK((idx + 1), ((1UL << ctrl->X.size_mask) -1)) |\
-                         L4_LOG_MASK(idx, (~((1UL << ctrl->X.size_mask) -1))))
+#define L4_LOG_INC_LOG(idx, ctrl)                                      \
+    idx =                                                              \
+        (L4_Word_t *) (L4_LOG_MASK((idx + 1),                          \
+                                   ((1UL << ctrl->X.size_mask) - 1)) | \
+                       L4_LOG_MASK(idx, (~((1UL << ctrl->X.size_mask) - 1))))
 
-#define L4_LOG_DEC_LOG(idx, ctrl)      \
-	idx = (L4_Word_t *) (L4_LOG_MASK((idx - 1), ((1UL << ctrl->X.size_mask) -1)) | \
-                         L4_LOG_MASK(idx, (~((1UL << ctrl->X.size_mask) -1))))
+#define L4_LOG_DEC_LOG(idx, ctrl)                                      \
+    idx =                                                              \
+        (L4_Word_t *) (L4_LOG_MASK((idx - 1),                          \
+                                   ((1UL << ctrl->X.size_mask) - 1)) | \
+                       L4_LOG_MASK(idx, (~((1UL << ctrl->X.size_mask) - 1))))
 
-#define L4_LOG_NEXT_LOG(idx, ctrl)	\
-    (L4_Word_t *) (L4_LOG_MASK((idx + 1), ((1UL << ctrl->X.size_mask) -1)) |\
-			 L4_LOG_MASK(idx, (~((1UL << ctrl->X.size_mask) -1))))
+#define L4_LOG_NEXT_LOG(idx, ctrl)                                            \
+    (L4_Word_t *) (L4_LOG_MASK((idx + 1), ((1UL << ctrl->X.size_mask) - 1)) | \
+                   L4_LOG_MASK(idx, (~((1UL << ctrl->X.size_mask) - 1))))
 
-#define L4_LOG_PREV_LOG(idx, ctrl)						\
-    (L4_Word_t *) (L4_LOG_MASK((idx - 1), ((1UL << ctrl->X.size_mask) -1)) |\
-			 L4_LOG_MASK(idx, (~((1UL << ctrl->X.size_mask) -1))))
-#define L4_LOG_FIRST_LOG(ctrl) \
-    (L4_Word_t *) (L4_LOG_MASK(L4_LOG_GET_IDX(ctrl->X.current_offset, ctrl), (~((1UL << ctrl->X.size_mask) -1))))
+#define L4_LOG_PREV_LOG(idx, ctrl)                                            \
+    (L4_Word_t *) (L4_LOG_MASK((idx - 1), ((1UL << ctrl->X.size_mask) - 1)) | \
+                   L4_LOG_MASK(idx, (~((1UL << ctrl->X.size_mask) - 1))))
+#define L4_LOG_FIRST_LOG(ctrl)                                               \
+    (L4_Word_t *) (L4_LOG_MASK(L4_LOG_GET_IDX(ctrl->X.current_offset, ctrl), \
+                               (~((1UL << ctrl->X.size_mask) - 1))))
 
-#define L4_LOG_ENTRIES(ctrl)            (1UL << (ctrl->X.size_mask - 2))
-#define L4_LOG_SIZE(ctrl)               (1UL << ctrl->X.size_mask)
+#define L4_LOG_ENTRIES(ctrl) (1UL << (ctrl->X.size_mask - 2))
+#define L4_LOG_SIZE(ctrl) (1UL << ctrl->X.size_mask)
 
 
 
@@ -853,32 +858,32 @@ L4_INLINE L4_Word_t L4_Set_Logid(L4_ThreadId_t tid, L4_Word_t logid)
  **********************************************************************/
 #if 0
 /* P4 */
-#define L4_X86_PMC_TSC_WEIGHT		    (617)
-#define L4_X86_PMC_UC_WEIGHT		    (712)
-#define L4_X86_PMC_MQW_WEIGHT		    (475)
-#define L4_X86_PMC_RB_WEIGHT		     (56)
-#define L4_X86_PMC_MB_WEIGHT		  (34046)
-#define L4_X86_PMC_MR_WEIGHT		    (173)
-#define L4_X86_PMC_MLR_WEIGHT		   (2996)
-#define L4_X86_PMC_LDM_WEIGHT		   (1355)
+#define L4_X86_PMC_TSC_WEIGHT (617)
+#define L4_X86_PMC_UC_WEIGHT (712)
+#define L4_X86_PMC_MQW_WEIGHT (475)
+#define L4_X86_PMC_RB_WEIGHT (56)
+#define L4_X86_PMC_MB_WEIGHT (34046)
+#define L4_X86_PMC_MR_WEIGHT (173)
+#define L4_X86_PMC_MLR_WEIGHT (2996)
+#define L4_X86_PMC_LDM_WEIGHT (1355)
 #else
 /* Pentium D */
-#define L4_X86_PMC_TSC_WEIGHT		   (1418)
-#define L4_X86_PMC_UC_WEIGHT		   (1285)
-#define L4_X86_PMC_LDM_WEIGHT		   (881)
-#define L4_X86_PMC_MR_WEIGHT		   (649)
-#define L4_X86_PMC_MB_WEIGHT		   (23421)
-#define L4_X86_PMC_MLR_WEIGHT		   (4320)
-#define L4_X86_PMC_RB_WEIGHT		   (840)
-#define L4_X86_PMC_MQW_WEIGHT		   (75)
+#define L4_X86_PMC_TSC_WEIGHT (1418)
+#define L4_X86_PMC_UC_WEIGHT (1285)
+#define L4_X86_PMC_LDM_WEIGHT (881)
+#define L4_X86_PMC_MR_WEIGHT (649)
+#define L4_X86_PMC_MB_WEIGHT (23421)
+#define L4_X86_PMC_MLR_WEIGHT (4320)
+#define L4_X86_PMC_RB_WEIGHT (840)
+#define L4_X86_PMC_MQW_WEIGHT (75)
 #endif
 
 
-#define L4_X86_PMC_TSC                     (0)
-#define L4_X86_PMC_TSC_SHIFT               6
-#define L4_X86_PMC_UC                      (0)
-#define L4_X86_PMC_RB                      (5)
-#define L4_X86_PMC_MR                      (13)
-#define L4_X86_PMC_LDM                     (14)
+#define L4_X86_PMC_TSC (0)
+#define L4_X86_PMC_TSC_SHIFT 6
+#define L4_X86_PMC_UC (0)
+#define L4_X86_PMC_RB (5)
+#define L4_X86_PMC_MR (13)
+#define L4_X86_PMC_LDM (14)
 
-#endif	/* IA32 specific implementation */
+#endif /* IA32 specific implementation */
diff --git a/user/include/l4/platform/kdebug.h b/user/include/l4/platform/kdebug.h
index 242bf138..90003ce1 100644
--- a/user/include/l4/platform/kdebug.h
+++ b/user/include/l4/platform/kdebug.h
@@ -6,51 +6,51 @@
 #ifndef __L4_PLATFORM_KDEBUG_H__
 #define __L4_PLATFORM_KDEBUG_H__
 
-#define L4_KDB_Enter(str...)			\
-do {						\
-} while (0)
-#endif	/* __L4_PLATFORM_KDEBUG_H__ */
+#define L4_KDB_Enter(str...) \
+    do {                     \
+    } while (0)
+#endif /* __L4_PLATFORM_KDEBUG_H__ */
 
 
-#if 0	/* FIXME: IA32 specific implementation */
+#if 0 /* FIXME: IA32 specific implementation */
 
 #ifndef __L4__X86__KDEBUG_H__
 #define __L4__X86__KDEBUG_H__
 
-#define __L4_KDB_Op(op, name)			\
-L4_INLINE void L4_KDB_##name (void)		\
-{						\
-    __asm__ __volatile__ (			\
-	"/* L4_KDB_"#name"() */		\n"	\
-	"	int	$3		\n"	\
-	"	cmpb	%0, %%al	\n"	\
-	:					\
-	: "i" (op));				\
-}
+#define __L4_KDB_Op(op, name)                    \
+    L4_INLINE void L4_KDB_##name(void)           \
+    {                                            \
+        __asm__ __volatile__("/* L4_KDB_" #name  \
+                             "() */		\n"         \
+                             "	int	$3		\n"       \
+                             "	cmpb	%0, %%al	\n" \
+                             :                   \
+                             : "i"(op));         \
+    }
 
-#define __L4_KDB_Op_Arg(op, name, argtype)	\
-L4_INLINE void L4_KDB_##name (argtype arg)	\
-{						\
-    __asm__ __volatile__ (			\
-	"/* L4_KDB_"#name"() */		\n"	\
-	"	int	$3		\n"	\
-	"	cmpb	%1, %%al	\n"	\
-	:					\
-	: "a" (arg), "i" (op));			\
-}
+#define __L4_KDB_Op_Arg(op, name, argtype)         \
+    L4_INLINE void L4_KDB_##name(argtype arg)      \
+    {                                              \
+        __asm__ __volatile__("/* L4_KDB_" #name    \
+                             "() */		\n"           \
+                             "	int	$3		\n"         \
+                             "	cmpb	%1, %%al	\n"   \
+                             :                     \
+                             : "a"(arg), "i"(op)); \
+    }
 
-#define __L4_KDB_Op_Ret(op, name, rettype)	\
-L4_INLINE rettype L4_KDB_##name (void)		\
-{						\
-    rettype ret;				\
-    __asm__ __volatile__ (			\
-	"/* L4_KDB_"#name"() */		\n"	\
-	"	int	$3		\n"	\
-	"	cmpb	%1, %%al	\n"	\
-	: "=a" (ret)				\
-	: "i" (op));				\
-    return ret;					\
-}
+#define __L4_KDB_Op_Ret(op, name, rettype)       \
+    L4_INLINE rettype L4_KDB_##name(void)        \
+    {                                            \
+        rettype ret;                             \
+        __asm__ __volatile__("/* L4_KDB_" #name  \
+                             "() */		\n"         \
+                             "	int	$3		\n"       \
+                             "	cmpb	%1, %%al	\n" \
+                             : "=a"(ret)         \
+                             : "i"(op));         \
+        return ret;                              \
+    }
 
 
 __L4_KDB_Op_Arg (0x00, PrintChar, char);
@@ -63,4 +63,4 @@ __L4_KDB_Op_Ret (0x0d, ReadChar_Blocked, char);
 
 #endif /* !__L4__X86__KDEBUG_H__ */
 
-#endif	/* IA32 specific implementation */
+#endif /* IA32 specific implementation */
diff --git a/user/include/l4/platform/specials.h b/user/include/l4/platform/specials.h
index d1503fc8..f126c6a8 100644
--- a/user/include/l4/platform/specials.h
+++ b/user/include/l4/platform/specials.h
@@ -12,31 +12,27 @@ L4_INLINE int __L4_Msb(L4_Word_t w) __attribute__((const));
 
 L4_INLINE int __L4_Msb(L4_Word_t w)
 {
-	int zeros;
-	__asm__ __volatile__(
-	    "clz %0, %1\n"
-	    : /* outputs */ "=r"(zeros)
-	    : /* inputs */ "r"(w)
-	);
-	return 31 - zeros;
+    int zeros;
+    __asm__ __volatile__("clz %0, %1\n"
+                         : /* outputs */ "=r"(zeros)
+                         : /* inputs */ "r"(w));
+    return 31 - zeros;
 }
 
 L4_INLINE int __L4_Lsb(L4_Word_t w) __attribute__((const));
 
 L4_INLINE int __L4_Lsb(L4_Word_t w)
 {
-	L4_Word_t bitnum;
-	__asm__ __volatile__(
-	    "bsf %1, %0\n"
-	    : /* outputs */ "=r"(bitnum)
-	    : /* inputs */ "rm"(w)
-	);
-	return bitnum;
+    L4_Word_t bitnum;
+    __asm__ __volatile__("bsf %1, %0\n"
+                         : /* outputs */ "=r"(bitnum)
+                         : /* inputs */ "rm"(w));
+    return bitnum;
 }
 
-#endif	/* __L4_PLATFORM_SPECIALS_H__ */
+#endif /* __L4_PLATFORM_SPECIALS_H__ */
 
-#if 0	/* FIXME: IA32 specific implementation */
+#if 0 /* FIXME: IA32 specific implementation */
 
 #ifndef __L4__IA32__SPECIALS_H__
 #define __L4__IA32__SPECIALS_H__
@@ -83,7 +79,7 @@ L4_INLINE L4_Word64_t __L4_Rdpmc(const L4_Word_t ctrsel)
  * Control parameter for SpaceControl system call.
  */
 
-#define L4_LargeSpace		0
+#define L4_LargeSpace 0
 
 L4_INLINE L4_Word_t L4_SmallSpace(L4_Word_t location, L4_Word_t size)
 {
@@ -102,12 +98,12 @@ L4_INLINE L4_Word_t L4_SmallSpace(L4_Word_t location, L4_Word_t size)
 /*
  * Memory attributes for MemoryControl system call.
  */
-#define L4_WriteBackMemory		1
-#define L4_WriteThroughMemory		2
-#define L4_UncacheableMemory		4
-#define L4_WriteCombiningMemory		5
-#define L4_WriteProtectedMemory		8
+#define L4_WriteBackMemory 1
+#define L4_WriteThroughMemory 2
+#define L4_UncacheableMemory 4
+#define L4_WriteCombiningMemory 5
+#define L4_WriteProtectedMemory 8
 
 #endif /* !__L4__IA32__SPECIALS_H__ */
 
-#endif	/* IA32 specific implementation */
+#endif /* IA32 specific implementation */
diff --git a/user/include/l4/platform/syscalls.h b/user/include/l4/platform/syscalls.h
index 15a112f6..96d5f131 100644
--- a/user/include/l4/platform/syscalls.h
+++ b/user/include/l4/platform/syscalls.h
@@ -35,7 +35,7 @@ L4_Word_t L4_ThreadControl(L4_ThreadId_t dest,
                            L4_ThreadId_t SpaceSpecifier,
                            L4_ThreadId_t Scheduler,
                            L4_ThreadId_t Pager,
-                           void * UtcbLocation);
+                           void *UtcbLocation);
 __USER_TEXT
 L4_Clock_t L4_SystemClock(void);
 
@@ -48,17 +48,17 @@ L4_Word_t L4_Schedule(L4_ThreadId_t dest,
                       L4_Word_t ProcessorControl,
                       L4_Word_t PrioControl,
                       L4_Word_t PreemptionControl,
-                      L4_Word_t * old_TimeControl);
+                      L4_Word_t *old_TimeControl);
 __USER_TEXT
 L4_MsgTag_t L4_Ipc(L4_ThreadId_t to,
                    L4_ThreadId_t FromSpecifier,
                    L4_Word_t Timeouts,
-                   L4_ThreadId_t * from);
+                   L4_ThreadId_t *from);
 __USER_TEXT
 L4_MsgTag_t L4_Lipc(L4_ThreadId_t to,
                     L4_ThreadId_t FromSpecifier,
                     L4_Word_t Timeouts,
-                    L4_ThreadId_t * from);
+                    L4_ThreadId_t *from);
 __USER_TEXT
 void L4_Unmap(L4_Word_t control);
 
@@ -75,7 +75,6 @@ L4_Word_t L4_ProcessorControl(L4_Word_t ProcessorNo,
                               L4_Word_t ExternalFrequency,
                               L4_Word_t voltage);
 __USER_TEXT
-L4_Word_t L4_MemoryControl(L4_Word_t control,
-                           const L4_Word_t * attributes);
+L4_Word_t L4_MemoryControl(L4_Word_t control, const L4_Word_t *attributes);
 
 #endif /* !__L4_PLATFORM_SYSCALLS_H__ */
diff --git a/user/include/l4/platform/types.h b/user/include/l4/platform/types.h
index 5e3d123e..300474e0 100644
--- a/user/include/l4/platform/types.h
+++ b/user/include/l4/platform/types.h
@@ -11,20 +11,20 @@
 #define L4_LITTLE_ENDIAN
 
 typedef unsigned int __attribute__((__mode__(__DI__))) L4_Word64_t;
-typedef unsigned int		L4_Word32_t;
-typedef unsigned short		L4_Word16_t;
-typedef unsigned char		L4_Word8_t;
+typedef unsigned int L4_Word32_t;
+typedef unsigned short L4_Word16_t;
+typedef unsigned char L4_Word8_t;
 
-typedef unsigned long		L4_Word_t;
+typedef unsigned long L4_Word_t;
 
 typedef signed int __attribute__((__mode__(__DI__))) L4_SignedWord64_t;
-typedef signed int		L4_SignedWord32_t;
-typedef signed short		L4_SignedWord16_t;
-typedef signed char		L4_SignedWord8_t;
+typedef signed int L4_SignedWord32_t;
+typedef signed short L4_SignedWord16_t;
+typedef signed char L4_SignedWord8_t;
 
-typedef signed long		L4_SignedWord_t;
+typedef signed long L4_SignedWord_t;
 
-typedef unsigned int		L4_Size_t;
-typedef L4_Word64_t		L4_Paddr_t;
+typedef unsigned int L4_Size_t;
+typedef L4_Word64_t L4_Paddr_t;
 
 #endif /* !__L4_PLATFORM_TYPES_H__ */
diff --git a/user/include/l4/platform/vregs.h b/user/include/l4/platform/vregs.h
index 7933c395..85f51acc 100644
--- a/user/include/l4/platform/vregs.h
+++ b/user/include/l4/platform/vregs.h
@@ -10,17 +10,17 @@
 
 #include <l4/utcb.h>
 
-#define __L4_NUM_MRS	16
-#define __L4_NUM_BRS	8
-
-register L4_Word32_t __L4_MR0 asm ("r4");
-register L4_Word32_t __L4_MR1 asm ("r5");
-register L4_Word32_t __L4_MR2 asm ("r6");
-register L4_Word32_t __L4_MR3 asm ("r7");
-register L4_Word32_t __L4_MR4 asm ("r8");
-register L4_Word32_t __L4_MR5 asm ("r9");
-register L4_Word32_t __L4_MR6 asm ("r10");
-register L4_Word32_t __L4_MR7 asm ("r11");
+#define __L4_NUM_MRS 16
+#define __L4_NUM_BRS 8
+
+register L4_Word32_t __L4_MR0 asm("r4");
+register L4_Word32_t __L4_MR1 asm("r5");
+register L4_Word32_t __L4_MR2 asm("r6");
+register L4_Word32_t __L4_MR3 asm("r7");
+register L4_Word32_t __L4_MR4 asm("r8");
+register L4_Word32_t __L4_MR5 asm("r9");
+register L4_Word32_t __L4_MR6 asm("r10");
+register L4_Word32_t __L4_MR7 asm("r11");
 
 /*
  * All virtual registers on ARM is located in a user Level Thread
@@ -28,103 +28,103 @@ register L4_Word32_t __L4_MR7 asm ("r11");
  */
 L4_INLINE utcb_t *__L4_Utcb(void)
 {
-	extern void *current_utcb;
-	return current_utcb;
+    extern void *current_utcb;
+    return current_utcb;
 }
 
 /*
  * Location of TCRs within UTCB.
  */
-#define __L4_TCR_THREAD_WORD_0			(-4)
-#define __L4_TCR_THREAD_WORD_1			(-5)
-#define __L4_TCR_VIRTUAL_ACTUAL_SENDER		(-6)
-#define __L4_TCR_INTENDED_RECEIVER		(-7)
-#define __L4_TCR_XFER_TIMEOUT			(-8)
-#define __L4_TCR_ERROR_CODE			(-9)
-#define __L4_TCR_PREEMPT_FLAGS			(-10)
-#define __L4_TCR_COP_FLAGS			(-10)
-#define __L4_TCR_EXCEPTION_HANDLER		(-11)
-#define __L4_TCR_PAGER				(-12)
-#define __L4_TCR_USER_DEFINED_HANDLE		(-13)
-#define __L4_TCR_PROCESSOR_NO			(-14)
-#define __L4_TCR_MY_GLOBAL_ID			(-15)
+#define __L4_TCR_THREAD_WORD_0 (-4)
+#define __L4_TCR_THREAD_WORD_1 (-5)
+#define __L4_TCR_VIRTUAL_ACTUAL_SENDER (-6)
+#define __L4_TCR_INTENDED_RECEIVER (-7)
+#define __L4_TCR_XFER_TIMEOUT (-8)
+#define __L4_TCR_ERROR_CODE (-9)
+#define __L4_TCR_PREEMPT_FLAGS (-10)
+#define __L4_TCR_COP_FLAGS (-10)
+#define __L4_TCR_EXCEPTION_HANDLER (-11)
+#define __L4_TCR_PAGER (-12)
+#define __L4_TCR_USER_DEFINED_HANDLE (-13)
+#define __L4_TCR_PROCESSOR_NO (-14)
+#define __L4_TCR_MY_GLOBAL_ID (-15)
 
 /*
  * Thread Control Registers.
  */
 L4_INLINE L4_Word_t __L4_TCR_MyGlobalId(void)
 {
-	return __L4_Utcb()->t_globalid;
+    return __L4_Utcb()->t_globalid;
 }
 
 L4_INLINE L4_Word_t __L4_TCR_MyLocalId(void)
 {
-	return (L4_Word_t) __L4_Utcb();
+    return (L4_Word_t) __L4_Utcb();
 }
 
 L4_INLINE L4_Word_t __L4_TCR_ProcessorNo(void)
 {
-	return (__L4_Utcb())->processor_no;
+    return (__L4_Utcb())->processor_no;
 }
 
 L4_INLINE L4_Word_t __L4_TCR_UserDefinedHandle(void)
 {
-	return __L4_Utcb()->user_defined_handle;
+    return __L4_Utcb()->user_defined_handle;
 }
 
 L4_INLINE void __L4_TCR_Set_UserDefinedHandle(L4_Word_t w)
 {
-	__L4_Utcb()->user_defined_handle = w;
+    __L4_Utcb()->user_defined_handle = w;
 }
 
 L4_INLINE L4_Word_t __L4_TCR_Pager(void)
 {
-	return __L4_Utcb()->t_pager;
+    return __L4_Utcb()->t_pager;
 }
 
 L4_INLINE void __L4_TCR_Set_Pager(L4_Word_t w)
 {
-	__L4_Utcb()->t_pager = w;
+    __L4_Utcb()->t_pager = w;
 }
 
 L4_INLINE L4_Word_t __L4_TCR_ExceptionHandler(void)
 {
-	return __L4_Utcb()->exception_handler;
+    return __L4_Utcb()->exception_handler;
 }
 
 L4_INLINE void __L4_TCR_Set_ExceptionHandler(L4_Word_t w)
 {
-	__L4_Utcb()->exception_handler = w;
+    __L4_Utcb()->exception_handler = w;
 }
 
 L4_INLINE L4_Word_t __L4_TCR_ErrorCode(void)
 {
-	return __L4_Utcb()->error_code;
+    return __L4_Utcb()->error_code;
 }
 
 L4_INLINE L4_Word_t __L4_TCR_XferTimeout(void)
 {
-	return __L4_Utcb()->xfer_timeouts;
+    return __L4_Utcb()->xfer_timeouts;
 }
 
 L4_INLINE void __L4_TCR_Set_XferTimeout(L4_Word_t w)
 {
-	__L4_Utcb()->xfer_timeouts = w;
+    __L4_Utcb()->xfer_timeouts = w;
 }
 
 L4_INLINE L4_Word_t __L4_TCR_IntendedReceiver(void)
 {
-	return __L4_Utcb()->intended_receiver;
+    return __L4_Utcb()->intended_receiver;
 }
 
 L4_INLINE L4_Word_t __L4_TCR_ActualSender(void)
 {
-	return __L4_Utcb()->sender;
+    return __L4_Utcb()->sender;
 }
 
 L4_INLINE void __L4_TCR_Set_VirtualSender(L4_Word_t w)
 {
-	__L4_Utcb()->sender = w;
+    __L4_Utcb()->sender = w;
 }
 
 /*
@@ -132,89 +132,167 @@ L4_INLINE void __L4_TCR_Set_VirtualSender(L4_Word_t w)
  */
 L4_INLINE L4_Word32_t L4_NumMRs(void)
 {
-	return __L4_NUM_MRS;
+    return __L4_NUM_MRS;
 }
 
 L4_INLINE void L4_StoreMR(int i, L4_Word_t *w)
 {
-	switch (i) {
-	case 0: *w = __L4_MR0; break;
-	case 1: *w = __L4_MR1; break;
-	case 2: *w = __L4_MR2; break;
-	case 3: *w = __L4_MR3; break;
-	case 4: *w = __L4_MR4; break;
-	case 5: *w = __L4_MR5; break;
-	case 6: *w = __L4_MR6; break;
-	case 7: *w = __L4_MR7; break;
-	default:
-		if (i >= 0 && i < __L4_NUM_MRS)
-			*w = __L4_Utcb()->mr[i - 8];
-		else
-			*w = 0;
-	}
+    switch (i) {
+    case 0:
+        *w = __L4_MR0;
+        break;
+    case 1:
+        *w = __L4_MR1;
+        break;
+    case 2:
+        *w = __L4_MR2;
+        break;
+    case 3:
+        *w = __L4_MR3;
+        break;
+    case 4:
+        *w = __L4_MR4;
+        break;
+    case 5:
+        *w = __L4_MR5;
+        break;
+    case 6:
+        *w = __L4_MR6;
+        break;
+    case 7:
+        *w = __L4_MR7;
+        break;
+    default:
+        if (i >= 0 && i < __L4_NUM_MRS)
+            *w = __L4_Utcb()->mr[i - 8];
+        else
+            *w = 0;
+    }
 }
 
 L4_INLINE void L4_LoadMR(int i, L4_Word_t w)
 {
-	switch (i) {
-	case 0: __L4_MR0 = w; break;
-	case 1: __L4_MR1 = w; break;
-	case 2: __L4_MR2 = w; break;
-	case 3: __L4_MR3 = w; break;
-	case 4: __L4_MR4 = w; break;
-	case 5: __L4_MR5 = w; break;
-	case 6: __L4_MR6 = w; break;
-	case 7: __L4_MR7 = w; break;
-	default:
-		if (i >= 0 && i < __L4_NUM_MRS)
-			__L4_Utcb()->mr[i - 8] = w;
-	}
+    switch (i) {
+    case 0:
+        __L4_MR0 = w;
+        break;
+    case 1:
+        __L4_MR1 = w;
+        break;
+    case 2:
+        __L4_MR2 = w;
+        break;
+    case 3:
+        __L4_MR3 = w;
+        break;
+    case 4:
+        __L4_MR4 = w;
+        break;
+    case 5:
+        __L4_MR5 = w;
+        break;
+    case 6:
+        __L4_MR6 = w;
+        break;
+    case 7:
+        __L4_MR7 = w;
+        break;
+    default:
+        if (i >= 0 && i < __L4_NUM_MRS)
+            __L4_Utcb()->mr[i - 8] = w;
+    }
 }
 
-L4_INLINE void L4_StoreMRs(int i, int k, L4_Word_t * w)
+L4_INLINE void L4_StoreMRs(int i, int k, L4_Word_t *w)
 {
-	if (i < 0 || k <= 0 || i + k > __L4_NUM_MRS)
-		return;
-
-	switch (i) {
-	case 0: *w++ = __L4_MR0; if (--k <= 0) break;
-	case 1: *w++ = __L4_MR1; if (--k <= 0) break;
-	case 2: *w++ = __L4_MR2; if (--k <= 0) break;
-	case 3: *w++ = __L4_MR3; if (--k <= 0) break;
-	case 4: *w++ = __L4_MR4; if (--k <= 0) break;
-	case 5: *w++ = __L4_MR5; if (--k <= 0) break;
-	case 6: *w++ = __L4_MR6; if (--k <= 0) break;
-	case 7: *w++ = __L4_MR7; if (--k <= 0) break;
-	default:
-		{
-			uint32_t *mr = __L4_Utcb()->mr;
-			while (k-- > 0)
-				*w++ = *mr++;
-		}
-	}
+    if (i < 0 || k <= 0 || i + k > __L4_NUM_MRS)
+        return;
+
+    switch (i) {
+    case 0:
+        *w++ = __L4_MR0;
+        if (--k <= 0)
+            break;
+    case 1:
+        *w++ = __L4_MR1;
+        if (--k <= 0)
+            break;
+    case 2:
+        *w++ = __L4_MR2;
+        if (--k <= 0)
+            break;
+    case 3:
+        *w++ = __L4_MR3;
+        if (--k <= 0)
+            break;
+    case 4:
+        *w++ = __L4_MR4;
+        if (--k <= 0)
+            break;
+    case 5:
+        *w++ = __L4_MR5;
+        if (--k <= 0)
+            break;
+    case 6:
+        *w++ = __L4_MR6;
+        if (--k <= 0)
+            break;
+    case 7:
+        *w++ = __L4_MR7;
+        if (--k <= 0)
+            break;
+    default: {
+        uint32_t *mr = __L4_Utcb()->mr;
+        while (k-- > 0)
+            *w++ = *mr++;
+    }
+    }
 }
 
 L4_INLINE void L4_LoadMRs(int i, int k, L4_Word_t *w)
 {
-	if (i < 0 || k <= 0 || i + k > __L4_NUM_MRS)
-		return;
-
-	switch (i) {
-	case 0: __L4_MR0 = *w++; if (--k <= 0) break;
-	case 1: __L4_MR1 = *w++; if (--k <= 0) break;
-	case 2: __L4_MR2 = *w++; if (--k <= 0) break;
-	case 3: __L4_MR3 = *w++; if (--k <= 0) break;
-	case 4: __L4_MR4 = *w++; if (--k <= 0) break;
-	case 5: __L4_MR5 = *w++; if (--k <= 0) break;
-	case 6: __L4_MR6 = *w++; if (--k <= 0) break;
-	case 7: __L4_MR7 = *w++; if (--k <= 0) break;
-	default:
-		{
-			uint32_t *mr = __L4_Utcb()->mr;
-			while (k-- > 0)
-				*mr++ = *w++;
-		}
-	}
+    if (i < 0 || k <= 0 || i + k > __L4_NUM_MRS)
+        return;
+
+    switch (i) {
+    case 0:
+        __L4_MR0 = *w++;
+        if (--k <= 0)
+            break;
+    case 1:
+        __L4_MR1 = *w++;
+        if (--k <= 0)
+            break;
+    case 2:
+        __L4_MR2 = *w++;
+        if (--k <= 0)
+            break;
+    case 3:
+        __L4_MR3 = *w++;
+        if (--k <= 0)
+            break;
+    case 4:
+        __L4_MR4 = *w++;
+        if (--k <= 0)
+            break;
+    case 5:
+        __L4_MR5 = *w++;
+        if (--k <= 0)
+            break;
+    case 6:
+        __L4_MR6 = *w++;
+        if (--k <= 0)
+            break;
+    case 7:
+        __L4_MR7 = *w++;
+        if (--k <= 0)
+            break;
+    default: {
+        uint32_t *mr = __L4_Utcb()->mr;
+        while (k-- > 0)
+            *mr++ = *w++;
+    }
+    }
 }
 
 /*
@@ -222,43 +300,43 @@ L4_INLINE void L4_LoadMRs(int i, int k, L4_Word_t *w)
  */
 L4_INLINE L4_Word32_t L4_NumBRs(void)
 {
-	return __L4_NUM_BRS;
+    return __L4_NUM_BRS;
 }
 
 L4_INLINE void L4_StoreBR(int i, L4_Word_t *w)
 {
-	if (i >= 0 && i < __L4_NUM_BRS)
-		*w = __L4_Utcb()->br[i];
+    if (i >= 0 && i < __L4_NUM_BRS)
+        *w = __L4_Utcb()->br[i];
 }
 
 L4_INLINE void L4_LoadBR(int i, L4_Word_t w)
 {
-	if (i >= 0 && i < __L4_NUM_BRS)
-		__L4_Utcb()->br[i] = w;
+    if (i >= 0 && i < __L4_NUM_BRS)
+        __L4_Utcb()->br[i] = w;
 }
 
 L4_INLINE void L4_StoreBRs(int i, int k, L4_Word_t *w)
 {
-	L4_Word_t * br;
+    L4_Word_t *br;
 
-	if (i < 0 || k <= 0 || i + k > __L4_NUM_BRS)
-		return;
+    if (i < 0 || k <= 0 || i + k > __L4_NUM_BRS)
+        return;
 
-	br = __L4_Utcb()->br + i;
-	while (k-- > 0)
-		*w++ = *br++;
+    br = __L4_Utcb()->br + i;
+    while (k-- > 0)
+        *w++ = *br++;
 }
 
 L4_INLINE void L4_LoadBRs(int i, int k, const L4_Word_t *w)
 {
-	L4_Word_t *br;
+    L4_Word_t *br;
 
-	if (i < 0 || k <= 0 || i + k > __L4_NUM_BRS)
-		return;
+    if (i < 0 || k <= 0 || i + k > __L4_NUM_BRS)
+        return;
 
-	br = __L4_Utcb()->br + i;
-	while (k-- > 0)
-		*br++ = *w++;
+    br = __L4_Utcb()->br + i;
+    while (k-- > 0)
+        *br++ = *w++;
 }
 
 #endif /* !__L4_PLATFORM_VREGS_H__ */
diff --git a/user/include/l4/schedule.h b/user/include/l4/schedule.h
index 7892fe4c..d811e126 100644
--- a/user/include/l4/schedule.h
+++ b/user/include/l4/schedule.h
@@ -14,80 +14,82 @@
  */
 L4_INLINE void L4_Yield(void)
 {
-	L4_ThreadSwitch(L4_nilthread);
+    L4_ThreadSwitch(L4_nilthread);
 }
 
 L4_INLINE L4_Word_t L4_Set_Priority(L4_ThreadId_t tid, L4_Word_t prio)
 {
-	L4_Word_t dummy;
-	prio &= 0xff;
-	return L4_Schedule(tid, ~0UL, ~0UL, prio, ~0UL, &dummy);
+    L4_Word_t dummy;
+    prio &= 0xff;
+    return L4_Schedule(tid, ~0UL, ~0UL, prio, ~0UL, &dummy);
 }
 
 L4_INLINE L4_Word_t L4_Set_Stride(L4_ThreadId_t tid, L4_Word_t stride)
 {
-	L4_Word_t dummy;
-	return L4_Schedule(tid, ~0UL, ~0UL, (stride << 16) | 0xffff, ~0UL, &dummy);
+    L4_Word_t dummy;
+    return L4_Schedule(tid, ~0UL, ~0UL, (stride << 16) | 0xffff, ~0UL, &dummy);
 }
 
 L4_INLINE L4_Word_t L4_Set_ProcessorNo(L4_ThreadId_t tid, L4_Word_t cpu_no)
 {
-	L4_Word_t dummy;
-	cpu_no &= 0xffff;
-	return L4_Schedule(tid, ~0UL, cpu_no, ~0UL, ~0UL, &dummy);
+    L4_Word_t dummy;
+    cpu_no &= 0xffff;
+    return L4_Schedule(tid, ~0UL, cpu_no, ~0UL, ~0UL, &dummy);
 }
 
-L4_INLINE L4_Word_t L4_Set_Timeslice(
-		L4_ThreadId_t tid, L4_Time_t timeslice,
-		L4_Time_t totalquantum)
+L4_INLINE L4_Word_t L4_Set_Timeslice(L4_ThreadId_t tid,
+                                     L4_Time_t timeslice,
+                                     L4_Time_t totalquantum)
 {
-	L4_Word_t timectrl = (timeslice.raw << 16) | totalquantum.raw;
-	return L4_Schedule(tid, timectrl, ~0UL, ~0UL, ~0UL, &timectrl);
+    L4_Word_t timectrl = (timeslice.raw << 16) | totalquantum.raw;
+    return L4_Schedule(tid, timectrl, ~0UL, ~0UL, ~0UL, &timectrl);
 }
 
-L4_INLINE L4_Word_t L4_Timeslice(
-		L4_ThreadId_t tid, L4_Time_t *timeslice,
-		L4_Time_t *totalquantum)
+L4_INLINE L4_Word_t L4_Timeslice(L4_ThreadId_t tid,
+                                 L4_Time_t *timeslice,
+                                 L4_Time_t *totalquantum)
 {
-	L4_Word_t res, timectrl;
-	res = L4_Schedule(tid, ~0UL, ~0UL, ~0UL, ~0UL, &timectrl);
-	timeslice->raw = timectrl >> 16;
-	totalquantum->raw = timectrl;
-	return res;
+    L4_Word_t res, timectrl;
+    res = L4_Schedule(tid, ~0UL, ~0UL, ~0UL, ~0UL, &timectrl);
+    timeslice->raw = timectrl >> 16;
+    totalquantum->raw = timectrl;
+    return res;
 }
 
-L4_INLINE L4_Word_t L4_Set_PreemptionDelay(
-		L4_ThreadId_t tid, L4_Word_t sensitivePrio,
-		L4_Word_t maxDelay)
+L4_INLINE L4_Word_t L4_Set_PreemptionDelay(L4_ThreadId_t tid,
+                                           L4_Word_t sensitivePrio,
+                                           L4_Word_t maxDelay)
 {
-	L4_Word_t dummy;
-	L4_Word_t pctrl = ((sensitivePrio & 0xff) << 16) | (maxDelay & 0xffff);
-	return L4_Schedule(tid, ~0UL, ~0UL, ~0UL, pctrl, &dummy);
+    L4_Word_t dummy;
+    L4_Word_t pctrl = ((sensitivePrio & 0xff) << 16) | (maxDelay & 0xffff);
+    return L4_Schedule(tid, ~0UL, ~0UL, ~0UL, pctrl, &dummy);
 }
 
-L4_INLINE L4_Word_t L4_HS_Schedule(
-		L4_ThreadId_t tid, L4_Word_t control,
-		L4_ThreadId_t domain, L4_Word_t prio,
-		L4_Word_t stride, L4_Word_t *old_control)
+L4_INLINE L4_Word_t L4_HS_Schedule(L4_ThreadId_t tid,
+                                   L4_Word_t control,
+                                   L4_ThreadId_t domain,
+                                   L4_Word_t prio,
+                                   L4_Word_t stride,
+                                   L4_Word_t *old_control)
 {
-	L4_Word_t preemption_control = ((control & 0x3f) << 26) | (1 << 25);
-	L4_Word_t time_control = domain.raw;
-	L4_Word_t prio_control = (stride << 16) | (prio & 0x1ff);
+    L4_Word_t preemption_control = ((control & 0x3f) << 26) | (1 << 25);
+    L4_Word_t time_control = domain.raw;
+    L4_Word_t prio_control = (stride << 16) | (prio & 0x1ff);
 
-	return L4_Schedule(tid, time_control, ~0UL,
-			prio_control, preemption_control, old_control);
+    return L4_Schedule(tid, time_control, ~0UL, prio_control,
+                       preemption_control, old_control);
 }
 
 /*
  * Result values from schedule system call
  */
-#define L4_SCHEDRESULT_ERROR		(0)
-#define L4_SCHEDRESULT_DEAD		(1)
-#define L4_SCHEDRESULT_INACTIVE		(2)
-#define L4_SCHEDRESULT_RUNNING		(3)
-#define L4_SCHEDRESULT_PENDING_SEND	(4)
-#define L4_SCHEDRESULT_SENDING		(5)
-#define L4_SCHEDRESULT_WAITING		(6)
-#define L4_SCHEDRESULT_RECEIVING	(7)
+#define L4_SCHEDRESULT_ERROR (0)
+#define L4_SCHEDRESULT_DEAD (1)
+#define L4_SCHEDRESULT_INACTIVE (2)
+#define L4_SCHEDRESULT_RUNNING (3)
+#define L4_SCHEDRESULT_PENDING_SEND (4)
+#define L4_SCHEDRESULT_SENDING (5)
+#define L4_SCHEDRESULT_WAITING (6)
+#define L4_SCHEDRESULT_RECEIVING (7)
 
 #endif /* !__L4__SCHEDULE_H__ */
diff --git a/user/include/l4/space.h b/user/include/l4/space.h
index e0b69310..3edbf825 100644
--- a/user/include/l4/space.h
+++ b/user/include/l4/space.h
@@ -14,74 +14,74 @@
  */
 L4_INLINE L4_Fpage_t L4_UnmapFpage(L4_Fpage_t f)
 {
-	L4_LoadMR(0, f.raw);
-	L4_Unmap((L4_Word_t)0);
-	L4_StoreMR(0, &f.raw);
-	return f;
+    L4_LoadMR(0, f.raw);
+    L4_Unmap((L4_Word_t) 0);
+    L4_StoreMR(0, &f.raw);
+    return f;
 }
 
 L4_INLINE void L4_UnmapFpages(L4_Word_t n, L4_Fpage_t *fpages)
 {
-	L4_LoadMRs(0, n, (L4_Word_t *) fpages);
-	L4_Unmap(n - 1);
-	L4_StoreMRs(0, n, (L4_Word_t *) fpages);
+    L4_LoadMRs(0, n, (L4_Word_t *) fpages);
+    L4_Unmap(n - 1);
+    L4_StoreMRs(0, n, (L4_Word_t *) fpages);
 }
 
 #if defined(__cplusplus)
 L4_INLINE L4_Fpage_t L4_Unmap(L4_Fpage_t f)
 {
-	return L4_UnmapFpage(f);
+    return L4_UnmapFpage(f);
 }
 
 L4_INLINE void L4_Unmap(L4_Word_t n, L4_Fpage_t *fpages)
 {
-	L4_UnmapFpages(n, fpages);
+    L4_UnmapFpages(n, fpages);
 }
 #endif
 
 L4_INLINE L4_Fpage_t L4_Flush(L4_Fpage_t f)
 {
-	L4_LoadMR(0, f.raw);
-	L4_Unmap(0x40);
-	L4_StoreMR(0, &f.raw);
-	return f;
+    L4_LoadMR(0, f.raw);
+    L4_Unmap(0x40);
+    L4_StoreMR(0, &f.raw);
+    return f;
 }
 
 L4_INLINE void L4_FlushFpages(L4_Word_t n, L4_Fpage_t *fpages)
 {
-	L4_LoadMRs(0, n, (L4_Word_t *) fpages);
-	L4_Unmap(0x40 + n - 1);
-	L4_StoreMRs(0, n, (L4_Word_t *) fpages);
+    L4_LoadMRs(0, n, (L4_Word_t *) fpages);
+    L4_Unmap(0x40 + n - 1);
+    L4_StoreMRs(0, n, (L4_Word_t *) fpages);
 }
 
 #if defined(__cplusplus)
 L4_INLINE void L4_Flush(L4_Word_t n, L4_Fpage_t *f)
 {
-	L4_FlushFpages(n, f);
+    L4_FlushFpages(n, f);
 }
 #endif
 
 L4_INLINE L4_Fpage_t L4_GetStatus(L4_Fpage_t f)
 {
-	L4_LoadMR(0, f.raw & ~0x0f);
-	L4_Unmap((L4_Word_t) 0);
-	L4_StoreMR(0, &f.raw);
-	return f;
+    L4_LoadMR(0, f.raw & ~0x0f);
+    L4_Unmap((L4_Word_t) 0);
+    L4_StoreMR(0, &f.raw);
+    return f;
 }
 
 L4_INLINE L4_Bool_t L4_WasWritten(L4_Fpage_t f)
 {
-	return (f.raw & L4_Writable) != 0;
+    return (f.raw & L4_Writable) != 0;
 }
 
 L4_INLINE L4_Bool_t L4_WasReferenced(L4_Fpage_t f)
 {
-	return (f.raw & L4_Readable) != 0;
+    return (f.raw & L4_Readable) != 0;
 }
 
 L4_INLINE L4_Bool_t L4_WaseXecuted(L4_Fpage_t f)
 {
-	return (f.raw & L4_eXecutable) != 0;
+    return (f.raw & L4_eXecutable) != 0;
 }
 
 #endif /* !__L4__SPACE_H__ */
diff --git a/user/include/l4/thread.h b/user/include/l4/thread.h
index 0d70fc33..8eacca64 100644
--- a/user/include/l4/thread.h
+++ b/user/include/l4/thread.h
@@ -7,56 +7,57 @@
 #ifndef __L4__THREAD_H__
 #define __L4__THREAD_H__
 
-#include <platform/link.h>
 #include <l4/types.h>
+#include <platform/link.h>
 #include __L4_INC_ARCH(syscalls.h)
 #include __L4_INC_ARCH(vregs.h)
 
-#define L4_ERROR_OK			(0)
-#define L4_ERROR_NO_PRIVILEGE		(1)
-#define L4_ERROR_INVALID_THREAD		(2)
-#define L4_ERROR_INVALID_SPACE		(3)
-#define L4_ERROR_INVALID_SCHEDULER	(4)
-#define L4_ERROR_INVALID_PARAM		(5)
-#define L4_ERROR_UTCB_AREA		(6)
-#define L4_ERROR_KIP_AREA		(7)
-#define L4_ERROR_NO_MEM			(8)
-
-#define DECLARE_THREAD(name, sub) \
-	void name(void) __attribute__ ((naked));	\
-void __USER_TEXT name(void)			\
-{						\
-	register void *kip_ptr asm ("r0");	\
-	register void *utcb_ptr asm ("r1");	\
-	sub(kip_ptr, utcb_ptr);			\
-	while (1);				\
-}
+#define L4_ERROR_OK (0)
+#define L4_ERROR_NO_PRIVILEGE (1)
+#define L4_ERROR_INVALID_THREAD (2)
+#define L4_ERROR_INVALID_SPACE (3)
+#define L4_ERROR_INVALID_SCHEDULER (4)
+#define L4_ERROR_INVALID_PARAM (5)
+#define L4_ERROR_UTCB_AREA (6)
+#define L4_ERROR_KIP_AREA (7)
+#define L4_ERROR_NO_MEM (8)
+
+#define DECLARE_THREAD(name, sub)           \
+    void name(void) __attribute__((naked)); \
+    void __USER_TEXT name(void)             \
+    {                                       \
+        register void *kip_ptr asm("r0");   \
+        register void *utcb_ptr asm("r1");  \
+        sub(kip_ptr, utcb_ptr);             \
+        while (1)                           \
+            ;                               \
+    }
 
 /*
  * Thread states
  */
 typedef struct L4_ThreadState {
-	L4_Word_t raw;
+    L4_Word_t raw;
 } L4_ThreadState_t;
 
 L4_INLINE L4_Bool_t L4_ThreadWasHalted(L4_ThreadState_t s)
 {
-	return s.raw & (1 << 0);
+    return s.raw & (1 << 0);
 }
 
 L4_INLINE L4_Bool_t L4_ThreadWasReceiving(L4_ThreadState_t s)
 {
-	return s.raw & (1 << 1);
+    return s.raw & (1 << 1);
 }
 
 L4_INLINE L4_Bool_t L4_ThreadWasSending(L4_ThreadState_t s)
 {
-	return s.raw & (1 << 2);
+    return s.raw & (1 << 2);
 }
 
 L4_INLINE L4_Bool_t L4_ThreadWasIpcing(L4_ThreadState_t s)
 {
-	return s.raw & (3 << 1);
+    return s.raw & (3 << 1);
 }
 
 /*
@@ -64,135 +65,135 @@ L4_INLINE L4_Bool_t L4_ThreadWasIpcing(L4_ThreadState_t s)
  */
 L4_INLINE L4_ThreadId_t L4_MyGlobalId(void)
 {
-	L4_ThreadId_t id;
-	id.raw = __L4_TCR_MyGlobalId ();
-	return id;
+    L4_ThreadId_t id;
+    id.raw = __L4_TCR_MyGlobalId();
+    return id;
 }
 
 L4_INLINE L4_ThreadId_t L4_MyLocalId(void)
 {
-	L4_ThreadId_t id;
-	id.raw = __L4_TCR_MyLocalId ();
-	return id;
+    L4_ThreadId_t id;
+    id.raw = __L4_TCR_MyLocalId();
+    return id;
 }
 
 L4_INLINE L4_ThreadId_t L4_Myself(void)
 {
-	return L4_MyGlobalId ();
+    return L4_MyGlobalId();
 }
 
 L4_INLINE L4_Word_t L4_ProcessorNo(void)
 {
-	return __L4_TCR_ProcessorNo();
+    return __L4_TCR_ProcessorNo();
 }
 
 L4_INLINE L4_Word_t L4_UserDefinedHandle(void)
 {
-	return __L4_TCR_UserDefinedHandle();
+    return __L4_TCR_UserDefinedHandle();
 }
 
 L4_INLINE void L4_Set_UserDefinedHandle(L4_Word_t NewValue)
 {
-	__L4_TCR_Set_UserDefinedHandle(NewValue);
+    __L4_TCR_Set_UserDefinedHandle(NewValue);
 }
 
 L4_INLINE L4_ThreadId_t L4_Pager(void)
 {
-	L4_ThreadId_t id;
-	id.raw = __L4_TCR_Pager();
-	return id;
+    L4_ThreadId_t id;
+    id.raw = __L4_TCR_Pager();
+    return id;
 }
 
 L4_INLINE void L4_Set_Pager(L4_ThreadId_t NewPager)
 {
-	__L4_TCR_Set_Pager(NewPager.raw);
+    __L4_TCR_Set_Pager(NewPager.raw);
 }
 
 L4_INLINE L4_ThreadId_t L4_ExceptionHandler(void)
 {
-	L4_ThreadId_t id;
-	id.raw = __L4_TCR_ExceptionHandler();
-	return id;
+    L4_ThreadId_t id;
+    id.raw = __L4_TCR_ExceptionHandler();
+    return id;
 }
 
 L4_INLINE void L4_Set_ExceptionHandler(L4_ThreadId_t NewHandler)
 {
-	__L4_TCR_Set_ExceptionHandler(NewHandler.raw);
+    __L4_TCR_Set_ExceptionHandler(NewHandler.raw);
 }
 
 L4_INLINE L4_Word_t L4_ErrorCode(void)
 {
-	return __L4_TCR_ErrorCode();
+    return __L4_TCR_ErrorCode();
 }
 
 L4_INLINE const char *L4_ErrorCode_String(L4_Word_t err)
 {
-	switch (err) {
-	case L4_ERROR_OK:
-		return "l4_error_ok";
-	case L4_ERROR_NO_PRIVILEGE:
-		return "l4_error_no_privilege";
-	case L4_ERROR_INVALID_THREAD:
-		return "l4_error_invalid_thread";
-	case L4_ERROR_INVALID_SPACE:
-		return "l4_error_invalid_space";
-	case L4_ERROR_INVALID_SCHEDULER:
-		return "l4_error_invalid_scheduler";
-	case L4_ERROR_INVALID_PARAM:
-		return "l4_error_invalid_param";
-	case L4_ERROR_UTCB_AREA:
-		return "l4_error_utcb_area";
-	case L4_ERROR_KIP_AREA:
-		return "l4_error_kip_area";
-	case L4_ERROR_NO_MEM:
-		return "l4_error_no_mem";
-	default:
-		return "invalid error code";
-	};
+    switch (err) {
+    case L4_ERROR_OK:
+        return "l4_error_ok";
+    case L4_ERROR_NO_PRIVILEGE:
+        return "l4_error_no_privilege";
+    case L4_ERROR_INVALID_THREAD:
+        return "l4_error_invalid_thread";
+    case L4_ERROR_INVALID_SPACE:
+        return "l4_error_invalid_space";
+    case L4_ERROR_INVALID_SCHEDULER:
+        return "l4_error_invalid_scheduler";
+    case L4_ERROR_INVALID_PARAM:
+        return "l4_error_invalid_param";
+    case L4_ERROR_UTCB_AREA:
+        return "l4_error_utcb_area";
+    case L4_ERROR_KIP_AREA:
+        return "l4_error_kip_area";
+    case L4_ERROR_NO_MEM:
+        return "l4_error_no_mem";
+    default:
+        return "invalid error code";
+    };
 };
 
 L4_INLINE L4_Word_t L4_XferTimeouts(void)
 {
-	return __L4_TCR_XferTimeout();
+    return __L4_TCR_XferTimeout();
 }
 
 L4_INLINE void L4_Set_XferTimeouts(L4_Word_t NewValue)
 {
-	__L4_TCR_Set_XferTimeout(NewValue);
+    __L4_TCR_Set_XferTimeout(NewValue);
 }
 
 L4_INLINE L4_ThreadId_t L4_IntendedReceiver(void)
 {
-	L4_ThreadId_t id;
-	id.raw = __L4_TCR_IntendedReceiver ();
-	return id;
+    L4_ThreadId_t id;
+    id.raw = __L4_TCR_IntendedReceiver();
+    return id;
 }
 
 L4_INLINE L4_ThreadId_t L4_ActualSender(void)
 {
-	L4_ThreadId_t id;
-	id.raw = __L4_TCR_ActualSender();
-	return id;
+    L4_ThreadId_t id;
+    id.raw = __L4_TCR_ActualSender();
+    return id;
 }
 
 L4_INLINE void L4_Set_VirtualSender(L4_ThreadId_t t)
 {
-	__L4_TCR_Set_VirtualSender(t.raw);
+    __L4_TCR_Set_VirtualSender(t.raw);
 }
 
 L4_INLINE L4_Word_t L4_WordSizeMask(void)
 {
 #if defined(__L4_TCR_WORD_SIZE_MASK)
-	return __L4_TCR_WordSizeMask();
+    return __L4_TCR_WordSizeMask();
 #else
-	return (~((L4_Word_t) 0));
+    return (~((L4_Word_t) 0));
 #endif
 }
 
 L4_INLINE void L4_Reset_WordSizeMask(void)
 {
 #if defined(__L4_TCR_WORD_SIZE_MASK)
-	__L4_TCR_Set_WordSizeMask(~((L4_Word_t) 0));
+    __L4_TCR_Set_WordSizeMask(~((L4_Word_t) 0));
 #endif
 }
 
@@ -228,305 +229,271 @@ L4_INLINE void L4_Reset_WordSizeMask(void)
  */
 L4_INLINE L4_ThreadId_t L4_GlobalIdOf(L4_ThreadId_t t)
 {
-	L4_Word_t dummy;
-	L4_ThreadId_t dummy_id;
+    L4_Word_t dummy;
+    L4_ThreadId_t dummy_id;
 
-	if (L4_IsLocalId (t))
-		return L4_ExchangeRegisters(
-				t, 0, 0, 0, 0, 0, L4_nilthread,
-				&dummy, &dummy, &dummy, &dummy, &dummy,
-				&dummy_id);
-	else
-		return t;
+    if (L4_IsLocalId(t))
+        return L4_ExchangeRegisters(t, 0, 0, 0, 0, 0, L4_nilthread, &dummy,
+                                    &dummy, &dummy, &dummy, &dummy, &dummy_id);
+    else
+        return t;
 }
 
 L4_INLINE L4_Bool_t L4_SameThreads(L4_ThreadId_t l, L4_ThreadId_t r)
 {
-	return L4_GlobalIdOf(l).raw == L4_GlobalIdOf (r).raw;
+    return L4_GlobalIdOf(l).raw == L4_GlobalIdOf(r).raw;
 }
 
 L4_INLINE L4_ThreadId_t L4_LocalIdOf(L4_ThreadId_t t)
 {
-	L4_Word_t dummy;
-	L4_ThreadId_t dummy_id;
+    L4_Word_t dummy;
+    L4_ThreadId_t dummy_id;
 
-	if (L4_IsGlobalId (t))
-		return L4_ExchangeRegisters(
-				t, 0, 0, 0, 0, 0, L4_nilthread,
-				&dummy, &dummy, &dummy, &dummy, &dummy,
-				&dummy_id);
-	else
-		return t;
+    if (L4_IsGlobalId(t))
+        return L4_ExchangeRegisters(t, 0, 0, 0, 0, 0, L4_nilthread, &dummy,
+                                    &dummy, &dummy, &dummy, &dummy, &dummy_id);
+    else
+        return t;
 }
 
 L4_INLINE L4_Word_t L4_UserDefinedHandleOf(L4_ThreadId_t t)
 {
-	L4_Word_t dummy, handle;
-	L4_ThreadId_t dummy_id;
+    L4_Word_t dummy, handle;
+    L4_ThreadId_t dummy_id;
 
-	(void) L4_ExchangeRegisters(
-			t, (1 << 9), 0, 0, 0, 0, L4_nilthread,
-			&dummy, &dummy, &dummy, &dummy, &handle,
-			&dummy_id);
+    (void) L4_ExchangeRegisters(t, (1 << 9), 0, 0, 0, 0, L4_nilthread, &dummy,
+                                &dummy, &dummy, &dummy, &handle, &dummy_id);
 
-	return handle;
+    return handle;
 }
 
-L4_INLINE void L4_Set_UserDefinedHandleOf(
-		L4_ThreadId_t t, L4_Word_t handle)
+L4_INLINE void L4_Set_UserDefinedHandleOf(L4_ThreadId_t t, L4_Word_t handle)
 {
-	L4_Word_t dummy;
-	L4_ThreadId_t dummy_id;
+    L4_Word_t dummy;
+    L4_ThreadId_t dummy_id;
 
-	(void) L4_ExchangeRegisters(
-			t, (1 << 6), 0, 0, 0, handle, L4_nilthread,
-			&dummy, &dummy, &dummy, &dummy, &dummy,
-			&dummy_id);
+    (void) L4_ExchangeRegisters(t, (1 << 6), 0, 0, 0, handle, L4_nilthread,
+                                &dummy, &dummy, &dummy, &dummy, &dummy,
+                                &dummy_id);
 }
 
 L4_INLINE L4_ThreadId_t L4_PagerOf(L4_ThreadId_t t)
 {
-	L4_Word_t dummy;
-	L4_ThreadId_t pager;
+    L4_Word_t dummy;
+    L4_ThreadId_t pager;
 
-	(void) L4_ExchangeRegisters(
-			t, (1 << 9), 0, 0, 0, 0, L4_nilthread,
-			&dummy, &dummy, &dummy, &dummy, &dummy,
-			&pager);
+    (void) L4_ExchangeRegisters(t, (1 << 9), 0, 0, 0, 0, L4_nilthread, &dummy,
+                                &dummy, &dummy, &dummy, &dummy, &pager);
 
-	return pager;
+    return pager;
 }
 
-L4_INLINE void L4_Set_PagerOf(
-		L4_ThreadId_t t, L4_ThreadId_t p)
+L4_INLINE void L4_Set_PagerOf(L4_ThreadId_t t, L4_ThreadId_t p)
 {
-	L4_Word_t dummy;
-	L4_ThreadId_t dummy_id;
+    L4_Word_t dummy;
+    L4_ThreadId_t dummy_id;
 
-	(void) L4_ExchangeRegisters(
-			t, (1 << 7), 0, 0, 0, 0, p,
-			&dummy, &dummy, &dummy, &dummy, &dummy,
-			&dummy_id);
+    (void) L4_ExchangeRegisters(t, (1 << 7), 0, 0, 0, 0, p, &dummy, &dummy,
+                                &dummy, &dummy, &dummy, &dummy_id);
 }
 
 L4_INLINE void L4_Start(L4_ThreadId_t t)
 {
-	L4_Word_t dummy;
-	L4_ThreadId_t dummy_id;
+    L4_Word_t dummy;
+    L4_ThreadId_t dummy_id;
 
-	(void) L4_ExchangeRegisters(
-			t, (1 << 8) + 6, 0, 0, 0, 0, L4_nilthread,
-			&dummy, &dummy, &dummy, &dummy, &dummy,
-			&dummy_id);
+    (void) L4_ExchangeRegisters(t, (1 << 8) + 6, 0, 0, 0, 0, L4_nilthread,
+                                &dummy, &dummy, &dummy, &dummy, &dummy,
+                                &dummy_id);
 }
 
 L4_INLINE void L4_Start_SpIp(L4_ThreadId_t t, L4_Word_t sp, L4_Word_t ip)
 {
-	L4_Word_t dummy;
-	L4_ThreadId_t dummy_id;
+    L4_Word_t dummy;
+    L4_ThreadId_t dummy_id;
 
-	(void) L4_ExchangeRegisters(
-			t, (3 << 3) + (1 << 8) + 6, sp, ip, 0, 0,
-			L4_nilthread,
-			&dummy, &dummy, &dummy, &dummy, &dummy,
-			&dummy_id);
+    (void) L4_ExchangeRegisters(t, (3 << 3) + (1 << 8) + 6, sp, ip, 0, 0,
+                                L4_nilthread, &dummy, &dummy, &dummy, &dummy,
+                                &dummy, &dummy_id);
 }
 
 
-L4_INLINE void L4_Start_SpIpFlags(
-		L4_ThreadId_t t, L4_Word_t sp,
-		L4_Word_t ip, L4_Word_t flags)
+L4_INLINE void L4_Start_SpIpFlags(L4_ThreadId_t t,
+                                  L4_Word_t sp,
+                                  L4_Word_t ip,
+                                  L4_Word_t flags)
 {
-	L4_Word_t dummy;
-	L4_ThreadId_t dummy_id;
+    L4_Word_t dummy;
+    L4_ThreadId_t dummy_id;
 
-	(void) L4_ExchangeRegisters(
-			t, (7 << 3) + (1 << 8) + 6, sp, ip, flags, 0,
-			L4_nilthread,
-			&dummy, &dummy, &dummy, &dummy, &dummy,
-			&dummy_id);
+    (void) L4_ExchangeRegisters(t, (7 << 3) + (1 << 8) + 6, sp, ip, flags, 0,
+                                L4_nilthread, &dummy, &dummy, &dummy, &dummy,
+                                &dummy, &dummy_id);
 }
 
 L4_INLINE L4_ThreadState_t L4_Stop(L4_ThreadId_t t)
 {
-	L4_Word_t dummy;
-	L4_ThreadId_t dummy_id;
-	L4_ThreadState_t state;
+    L4_Word_t dummy;
+    L4_ThreadId_t dummy_id;
+    L4_ThreadState_t state;
 
-	(void) L4_ExchangeRegisters(
-			t, 1 + (1 << 8) + (1 << 9), 0, 0, 0, 0,
-			L4_nilthread, &state.raw, &dummy, &dummy,
-			&dummy, &dummy, &dummy_id);
+    (void) L4_ExchangeRegisters(t, 1 + (1 << 8) + (1 << 9), 0, 0, 0, 0,
+                                L4_nilthread, &state.raw, &dummy, &dummy,
+                                &dummy, &dummy, &dummy_id);
 
-	return state;
+    return state;
 }
 
-L4_INLINE L4_ThreadState_t L4_Stop_SpIpFlags(
-		L4_ThreadId_t t,
-		L4_Word_t *sp,
-		L4_Word_t *ip,
-		L4_Word_t *flags)
+L4_INLINE L4_ThreadState_t L4_Stop_SpIpFlags(L4_ThreadId_t t,
+                                             L4_Word_t *sp,
+                                             L4_Word_t *ip,
+                                             L4_Word_t *flags)
 {
-	L4_Word_t dummy;
-	L4_ThreadId_t dummy_id;
-	L4_ThreadState_t state;
+    L4_Word_t dummy;
+    L4_ThreadId_t dummy_id;
+    L4_ThreadState_t state;
 
-	(void) L4_ExchangeRegisters(
-			t, 1 + (1 << 8) + (1 << 9), 0, 0, 0, 0,
-			L4_nilthread, &state.raw, sp, ip, flags,
-			&dummy, &dummy_id);
+    (void) L4_ExchangeRegisters(t, 1 + (1 << 8) + (1 << 9), 0, 0, 0, 0,
+                                L4_nilthread, &state.raw, sp, ip, flags, &dummy,
+                                &dummy_id);
 
-	return state;
+    return state;
 }
 
 L4_INLINE L4_ThreadState_t L4_AbortReceive_and_stop(L4_ThreadId_t t)
 {
-	L4_Word_t dummy;
-	L4_ThreadId_t dummy_id;
-	L4_ThreadState_t state;
+    L4_Word_t dummy;
+    L4_ThreadId_t dummy_id;
+    L4_ThreadState_t state;
 
-	(void) L4_ExchangeRegisters(
-			t, 3 + (1 << 8) + (1 << 9), 0, 0, 0, 0,
-			L4_nilthread, &state.raw, &dummy, &dummy,
-			&dummy, &dummy, &dummy_id);
+    (void) L4_ExchangeRegisters(t, 3 + (1 << 8) + (1 << 9), 0, 0, 0, 0,
+                                L4_nilthread, &state.raw, &dummy, &dummy,
+                                &dummy, &dummy, &dummy_id);
 
-	return state;
+    return state;
 }
 
-L4_INLINE L4_ThreadState_t L4_AbortReceive_and_stop_SpIpFlags(
-		L4_ThreadId_t t,
-		L4_Word_t *sp,
-		L4_Word_t *ip,
-		L4_Word_t *flags)
+L4_INLINE L4_ThreadState_t L4_AbortReceive_and_stop_SpIpFlags(L4_ThreadId_t t,
+                                                              L4_Word_t *sp,
+                                                              L4_Word_t *ip,
+                                                              L4_Word_t *flags)
 {
-	L4_Word_t dummy;
-	L4_ThreadId_t dummy_id;
-	L4_ThreadState_t state;
+    L4_Word_t dummy;
+    L4_ThreadId_t dummy_id;
+    L4_ThreadState_t state;
 
-	(void) L4_ExchangeRegisters(
-			t, 3 + (1 << 8) + (1 << 9), 0, 0, 0, 0,
-			L4_nilthread, &state.raw, sp, ip, flags,
-			&dummy, &dummy_id);
+    (void) L4_ExchangeRegisters(t, 3 + (1 << 8) + (1 << 9), 0, 0, 0, 0,
+                                L4_nilthread, &state.raw, sp, ip, flags, &dummy,
+                                &dummy_id);
 
-	return state;
+    return state;
 }
 
 L4_INLINE L4_ThreadState_t L4_AbortSend_and_stop(L4_ThreadId_t t)
 {
-	L4_Word_t dummy;
-	L4_ThreadId_t dummy_id;
-	L4_ThreadState_t state;
+    L4_Word_t dummy;
+    L4_ThreadId_t dummy_id;
+    L4_ThreadState_t state;
 
-	(void) L4_ExchangeRegisters(
-			t, 5 + (1 << 8) + (1 << 9), 0, 0, 0, 0,
-			L4_nilthread, &state.raw, &dummy, &dummy,
-			&dummy, &dummy, &dummy_id);
+    (void) L4_ExchangeRegisters(t, 5 + (1 << 8) + (1 << 9), 0, 0, 0, 0,
+                                L4_nilthread, &state.raw, &dummy, &dummy,
+                                &dummy, &dummy, &dummy_id);
 
-	return state;
+    return state;
 }
 
-L4_INLINE L4_ThreadState_t L4_AbortSend_and_stop_SpIpFlags(
-		L4_ThreadId_t t,
-		L4_Word_t *sp,
-		L4_Word_t *ip,
-		L4_Word_t *flags)
+L4_INLINE L4_ThreadState_t L4_AbortSend_and_stop_SpIpFlags(L4_ThreadId_t t,
+                                                           L4_Word_t *sp,
+                                                           L4_Word_t *ip,
+                                                           L4_Word_t *flags)
 {
+    L4_Word_t dummy;
+    L4_ThreadId_t dummy_id;
+    L4_ThreadState_t state;
 
-	L4_Word_t dummy;
-	L4_ThreadId_t dummy_id;
-	L4_ThreadState_t state;
-
-	(void) L4_ExchangeRegisters(
-			t, 5 + (1 << 8) + (1 << 9), 0, 0, 0, 0,
-			L4_nilthread, &state.raw, sp, ip, flags,
-			&dummy, &dummy_id);
+    (void) L4_ExchangeRegisters(t, 5 + (1 << 8) + (1 << 9), 0, 0, 0, 0,
+                                L4_nilthread, &state.raw, sp, ip, flags, &dummy,
+                                &dummy_id);
 
-	return state;
+    return state;
 }
 
 L4_INLINE L4_ThreadState_t L4_AbortIpc_and_stop(L4_ThreadId_t t)
 {
-	L4_Word_t dummy;
-	L4_ThreadId_t dummy_id;
-	L4_ThreadState_t state;
+    L4_Word_t dummy;
+    L4_ThreadId_t dummy_id;
+    L4_ThreadState_t state;
 
-	(void) L4_ExchangeRegisters(
-			t, 7 + (1 << 8) + (1 << 9), 0, 0, 0, 0,
-			L4_nilthread, &state.raw, &dummy, &dummy,
-			&dummy, &dummy, &dummy_id);
+    (void) L4_ExchangeRegisters(t, 7 + (1 << 8) + (1 << 9), 0, 0, 0, 0,
+                                L4_nilthread, &state.raw, &dummy, &dummy,
+                                &dummy, &dummy, &dummy_id);
 
-	return state;
+    return state;
 }
 
-L4_INLINE L4_ThreadState_t L4_AbortIpc_and_stop_SpIpFlags(
-		L4_ThreadId_t t,
-		L4_Word_t *sp,
-		L4_Word_t *ip,
-		L4_Word_t *flags)
+L4_INLINE L4_ThreadState_t L4_AbortIpc_and_stop_SpIpFlags(L4_ThreadId_t t,
+                                                          L4_Word_t *sp,
+                                                          L4_Word_t *ip,
+                                                          L4_Word_t *flags)
 {
-	L4_Word_t dummy;
-	L4_ThreadId_t dummy_id;
-	L4_ThreadState_t state;
+    L4_Word_t dummy;
+    L4_ThreadId_t dummy_id;
+    L4_ThreadState_t state;
 
-	(void) L4_ExchangeRegisters(
-			t, 7 + (1 << 8) + (1 << 9), 0, 0, 0, 0,
-			L4_nilthread, &state.raw, sp, ip, flags,
-			&dummy, &dummy_id);
+    (void) L4_ExchangeRegisters(t, 7 + (1 << 8) + (1 << 9), 0, 0, 0, 0,
+                                L4_nilthread, &state.raw, sp, ip, flags, &dummy,
+                                &dummy_id);
 
-	return state;
+    return state;
 }
 
-#define L4_EXREGS_CTRLXFER_CONF_FLAG    	(1UL <<  9)
-#define L4_EXREGS_CTRLXFER_READ_FLAG    	(1UL << 10)
-#define L4_EXREGS_CTRLXFER_WRITE_FLAG    	(1UL << 11)
-#define L4_EXREGS_EXCHANDLER_FLAG		(1UL << 12)
-#define L4_EXREGS_SCHEDULER_FLAG		(1UL << 13)
+#define L4_EXREGS_CTRLXFER_CONF_FLAG (1UL << 9)
+#define L4_EXREGS_CTRLXFER_READ_FLAG (1UL << 10)
+#define L4_EXREGS_CTRLXFER_WRITE_FLAG (1UL << 11)
+#define L4_EXREGS_EXCHANDLER_FLAG (1UL << 12)
+#define L4_EXREGS_SCHEDULER_FLAG (1UL << 13)
 
-L4_INLINE L4_Word_t L4_AssociateInterrupt(
-		L4_ThreadId_t InterruptThread,
-		L4_ThreadId_t HandlerThread)
+L4_INLINE L4_Word_t L4_AssociateInterrupt(L4_ThreadId_t InterruptThread,
+                                          L4_ThreadId_t HandlerThread)
 {
-	return L4_ThreadControl(
-			InterruptThread, InterruptThread,
-			L4_nilthread, HandlerThread, (void *) -1);
+    return L4_ThreadControl(InterruptThread, InterruptThread, L4_nilthread,
+                            HandlerThread, (void *) -1);
 }
 
-L4_INLINE L4_Word_t L4_DeassociateInterrupt(
-		L4_ThreadId_t InterruptThread)
+L4_INLINE L4_Word_t L4_DeassociateInterrupt(L4_ThreadId_t InterruptThread)
 {
-	return L4_ThreadControl(
-			InterruptThread, InterruptThread,
-			L4_nilthread, InterruptThread, (void *) -1);
+    return L4_ThreadControl(InterruptThread, InterruptThread, L4_nilthread,
+                            InterruptThread, (void *) -1);
 }
 
 L4_INLINE L4_Word_t L4_ConfCtrlXferItems(L4_ThreadId_t dest)
 {
-	L4_Word_t dummy, old_control;
-	L4_ThreadId_t dummy_tid;
-	L4_ExchangeRegisters(
-			dest, L4_EXREGS_CTRLXFER_CONF_FLAG, 0, 0 , 0, 0, L4_nilthread,
-			&old_control, &dummy, &dummy, &dummy, &dummy, &dummy_tid);
-	return old_control;
+    L4_Word_t dummy, old_control;
+    L4_ThreadId_t dummy_tid;
+    L4_ExchangeRegisters(dest, L4_EXREGS_CTRLXFER_CONF_FLAG, 0, 0, 0, 0,
+                         L4_nilthread, &old_control, &dummy, &dummy, &dummy,
+                         &dummy, &dummy_tid);
+    return old_control;
 }
 
 L4_INLINE L4_Word_t L4_ReadCtrlXferItems(L4_ThreadId_t dest)
 {
-	L4_Word_t dummy, old_control;
-	L4_ThreadId_t dummy_tid;
-	L4_ExchangeRegisters(
-			dest, L4_EXREGS_CTRLXFER_READ_FLAG, 0, 0 , 0, 0, L4_nilthread,
-			&old_control, &dummy, &dummy, &dummy, &dummy, &dummy_tid);
-	return old_control;
+    L4_Word_t dummy, old_control;
+    L4_ThreadId_t dummy_tid;
+    L4_ExchangeRegisters(dest, L4_EXREGS_CTRLXFER_READ_FLAG, 0, 0, 0, 0,
+                         L4_nilthread, &old_control, &dummy, &dummy, &dummy,
+                         &dummy, &dummy_tid);
+    return old_control;
 }
 
 L4_INLINE L4_Word_t L4_WriteCtrlXferItems(L4_ThreadId_t dest)
 {
-	L4_Word_t dummy, old_control;
-	L4_ThreadId_t dummy_tid;
-	L4_ExchangeRegisters(
-			dest, L4_EXREGS_CTRLXFER_WRITE_FLAG, 0, 0 , 0, 0, L4_nilthread,
-			&old_control, &dummy, &dummy, &dummy, &dummy, &dummy_tid);
-	return old_control;
+    L4_Word_t dummy, old_control;
+    L4_ThreadId_t dummy_tid;
+    L4_ExchangeRegisters(dest, L4_EXREGS_CTRLXFER_WRITE_FLAG, 0, 0, 0, 0,
+                         L4_nilthread, &old_control, &dummy, &dummy, &dummy,
+                         &dummy, &dummy_tid);
+    return old_control;
 }
 
 #endif /* !__L4__THREAD_H__ */
diff --git a/user/include/l4/types.h b/user/include/l4/types.h
index 328ca760..415be842 100644
--- a/user/include/l4/types.h
+++ b/user/include/l4/types.h
@@ -26,153 +26,235 @@
  */
 #define L4_HAVE_SIGNED_WORD
 
-typedef L4_Word_t		L4_Bool_t;
+typedef L4_Word_t L4_Bool_t;
 
-#define L4_INLINE		static inline __attribute__((always_inline))
-#define L4_BITS_PER_WORD	(sizeof (L4_Word_t) * 8)
+#define L4_INLINE static inline __attribute__((always_inline))
+#define L4_BITS_PER_WORD (sizeof(L4_Word_t) * 8)
 
 #if defined(L4_64BIT)
-# define __PLUS32	+ (sizeof (L4_Word_t) * 8 - 32)
-# define __14		32
-# define __18		32
+#define __PLUS32 +(sizeof(L4_Word_t) * 8 - 32)
+#define __14 32
+#define __18 32
 #else
-# define __PLUS32	+ 0
-# define __14		14
-# define __18		18
+#define __PLUS32 +0
+#define __14 14
+#define __18 18
 #endif
 
 #if defined(L4_BIG_ENDIAN)
-#define L4_BITFIELD2(t,a,b)		t b; t a
-#define L4_BITFIELD3(t,a,b,c)		t c; t b; t a
-#define L4_BITFIELD4(t,a,b,c,d)		t d; t c; t b; t a
-#define L4_BITFIELD5(t,a,b,c,d,e)	t e; t d; t c; t b; t a
-#define L4_BITFIELD6(t,a,b,c,d,e,f)	t f; t e; t d; t c; t b; t a
-#define L4_BITFIELD7(t,a,b,c,d,e,f,g)	t g; t f; t e; t d; t c; t b; t a
-#define L4_BITFIELD8(t,a,b,c,d,e,f,g,h)	t h; t g; t f; t e; t d; t c; t b; t a
-#define L4_BITFIELD9(t,a,b,c,d,e,f,g,h,i)	\
-	t i; t h; t g; t f; t e; t d; t c; t b; t a
-#define L4_SHUFFLE2(a,b)		b,a
-#define L4_SHUFFLE3(a,b,c)		c,b,a
-#define L4_SHUFFLE4(a,b,c,d)		d,c,b,a
-#define L4_SHUFFLE5(a,b,c,d,e)		e,d,c,b,a
-#define L4_SHUFFLE6(a,b,c,d,e,f)	f,e,d,c,b,a
-#define L4_SHUFFLE7(a,b,c,d,e,f,g)	g,f,e,d,c,b,a
+#define L4_BITFIELD2(t, a, b) \
+    t b;                      \
+    t a
+#define L4_BITFIELD3(t, a, b, c) \
+    t c;                         \
+    t b;                         \
+    t a
+#define L4_BITFIELD4(t, a, b, c, d) \
+    t d;                            \
+    t c;                            \
+    t b;                            \
+    t a
+#define L4_BITFIELD5(t, a, b, c, d, e) \
+    t e;                               \
+    t d;                               \
+    t c;                               \
+    t b;                               \
+    t a
+#define L4_BITFIELD6(t, a, b, c, d, e, f) \
+    t f;                                  \
+    t e;                                  \
+    t d;                                  \
+    t c;                                  \
+    t b;                                  \
+    t a
+#define L4_BITFIELD7(t, a, b, c, d, e, f, g) \
+    t g;                                     \
+    t f;                                     \
+    t e;                                     \
+    t d;                                     \
+    t c;                                     \
+    t b;                                     \
+    t a
+#define L4_BITFIELD8(t, a, b, c, d, e, f, g, h) \
+    t h;                                        \
+    t g;                                        \
+    t f;                                        \
+    t e;                                        \
+    t d;                                        \
+    t c;                                        \
+    t b;                                        \
+    t a
+#define L4_BITFIELD9(t, a, b, c, d, e, f, g, h, i) \
+    t i;                                           \
+    t h;                                           \
+    t g;                                           \
+    t f;                                           \
+    t e;                                           \
+    t d;                                           \
+    t c;                                           \
+    t b;                                           \
+    t a
+#define L4_SHUFFLE2(a, b) b, a
+#define L4_SHUFFLE3(a, b, c) c, b, a
+#define L4_SHUFFLE4(a, b, c, d) d, c, b, a
+#define L4_SHUFFLE5(a, b, c, d, e) e, d, c, b, a
+#define L4_SHUFFLE6(a, b, c, d, e, f) f, e, d, c, b, a
+#define L4_SHUFFLE7(a, b, c, d, e, f, g) g, f, e, d, c, b, a
 #else
-#define L4_BITFIELD2(t,a,b)		t a; t b
-#define L4_BITFIELD3(t,a,b,c)		t a; t b; t c
-#define L4_BITFIELD4(t,a,b,c,d)		t a; t b; t c; t d
-#define L4_BITFIELD5(t,a,b,c,d,e)	t a; t b; t c; t d; t e
-#define L4_BITFIELD6(t,a,b,c,d,e,f)	t a; t b; t c; t d; t e; t f
-#define L4_BITFIELD7(t,a,b,c,d,e,f,g)	t a; t b; t c; t d; t e; t f; t g
-#define L4_BITFIELD8(t,a,b,c,d,e,f,g,h)	t a; t b; t c; t d; t e; t f; t g; t h
-#define L4_BITFIELD9(t,a,b,c,d,e,f,g,h,i)	\
-	t a; t b; t c; t d; t e; t f; t g; t h; t i
-#define L4_SHUFFLE2(a,b)		a,b
-#define L4_SHUFFLE3(a,b,c)		a,b,c
-#define L4_SHUFFLE4(a,b,c,d)		a,b,c,d
-#define L4_SHUFFLE5(a,b,c,d,e)		a,b,c,d,e
-#define L4_SHUFFLE6(a,b,c,d,e,f)	a,b,c,d,e,f
-#define L4_SHUFFLE7(a,b,c,d,e,f,g)	a,b,c,d,e,f,g
+#define L4_BITFIELD2(t, a, b) \
+    t a;                      \
+    t b
+#define L4_BITFIELD3(t, a, b, c) \
+    t a;                         \
+    t b;                         \
+    t c
+#define L4_BITFIELD4(t, a, b, c, d) \
+    t a;                            \
+    t b;                            \
+    t c;                            \
+    t d
+#define L4_BITFIELD5(t, a, b, c, d, e) \
+    t a;                               \
+    t b;                               \
+    t c;                               \
+    t d;                               \
+    t e
+#define L4_BITFIELD6(t, a, b, c, d, e, f) \
+    t a;                                  \
+    t b;                                  \
+    t c;                                  \
+    t d;                                  \
+    t e;                                  \
+    t f
+#define L4_BITFIELD7(t, a, b, c, d, e, f, g) \
+    t a;                                     \
+    t b;                                     \
+    t c;                                     \
+    t d;                                     \
+    t e;                                     \
+    t f;                                     \
+    t g
+#define L4_BITFIELD8(t, a, b, c, d, e, f, g, h) \
+    t a;                                        \
+    t b;                                        \
+    t c;                                        \
+    t d;                                        \
+    t e;                                        \
+    t f;                                        \
+    t g;                                        \
+    t h
+#define L4_BITFIELD9(t, a, b, c, d, e, f, g, h, i) \
+    t a;                                           \
+    t b;                                           \
+    t c;                                           \
+    t d;                                           \
+    t e;                                           \
+    t f;                                           \
+    t g;                                           \
+    t h;                                           \
+    t i
+#define L4_SHUFFLE2(a, b) a, b
+#define L4_SHUFFLE3(a, b, c) a, b, c
+#define L4_SHUFFLE4(a, b, c, d) a, b, c, d
+#define L4_SHUFFLE5(a, b, c, d, e) a, b, c, d, e
+#define L4_SHUFFLE6(a, b, c, d, e, f) a, b, c, d, e, f
+#define L4_SHUFFLE7(a, b, c, d, e, f, g) a, b, c, d, e, f, g
 #endif
 
 /*
  * Error codes
  */
 
-#define L4_ErrOk		(0)
-#define L4_ErrNoPrivilege	(1)
-#define L4_ErrInvalidThread	(2)
-#define L4_ErrInvalidSpace	(3)
-#define L4_ErrInvalidScheduler	(4)
-#define L4_ErrInvalidParam	(5)
-#define L4_ErrUtcbArea		(6)
-#define L4_ErrKipArea		(7)
-#define L4_ErrNoMem		(8)
+#define L4_ErrOk (0)
+#define L4_ErrNoPrivilege (1)
+#define L4_ErrInvalidThread (2)
+#define L4_ErrInvalidSpace (3)
+#define L4_ErrInvalidScheduler (4)
+#define L4_ErrInvalidParam (5)
+#define L4_ErrUtcbArea (6)
+#define L4_ErrKipArea (7)
+#define L4_ErrNoMem (8)
 
 /*
  * Fpages
  */
 typedef union {
-	L4_Word_t raw;
-	struct {
-		L4_BITFIELD4(L4_Word_t,
-				rwx : 3,
-				extended : 1,
-				s : 6,
-				b : 22 __PLUS32);
-	} X;
+    L4_Word_t raw;
+    struct {
+        L4_BITFIELD4(L4_Word_t, rwx : 3, extended : 1, s : 6, b : 22 __PLUS32);
+    } X;
 } L4_Fpage_t;
 
-#define L4_Readable		(0x04)
-#define L4_Writable		(0x02)
-#define L4_eXecutable		(0x01)
-#define L4_FullyAccessible	(0x07)
-#define L4_ReadWriteOnly	(0x06)
-#define L4_ReadeXecOnly		(0x05)
-#define L4_NoAccess		(0x00)
+#define L4_Readable (0x04)
+#define L4_Writable (0x02)
+#define L4_eXecutable (0x01)
+#define L4_FullyAccessible (0x07)
+#define L4_ReadWriteOnly (0x06)
+#define L4_ReadeXecOnly (0x05)
+#define L4_NoAccess (0x00)
 
-#define L4_Nilpage		((L4_Fpage_t) { raw : 0UL })
-#define L4_CompleteAddressSpace	((L4_Fpage_t) { X : { L4_SHUFFLE4(0, 0, 1, 0) }})
+#define L4_Nilpage ((L4_Fpage_t) {raw : 0UL})
+#define L4_CompleteAddressSpace ((L4_Fpage_t) {X : {L4_SHUFFLE4(0, 0, 1, 0)}})
 
 #include __L4_INC_ARCH(specials.h)
 
 L4_INLINE L4_Bool_t L4_IsNilFpage(L4_Fpage_t f)
 {
-	return f.raw == 0;
+    return f.raw == 0;
 }
 
 L4_INLINE L4_Word_t L4_Rights(L4_Fpage_t f)
 {
-	return f.X.rwx;
+    return f.X.rwx;
 }
 
 L4_INLINE L4_Fpage_t L4_Set_Rights(L4_Fpage_t *f, L4_Word_t rwx)
 {
-	f->X.rwx = rwx;
-	return *f;
+    f->X.rwx = rwx;
+    return *f;
 }
 
 L4_INLINE L4_Fpage_t L4_FpageAddRights(L4_Fpage_t f, L4_Word_t rwx)
 {
-	f.X.rwx |= rwx;
-	return f;
+    f.X.rwx |= rwx;
+    return f;
 }
 
-L4_INLINE L4_Fpage_t L4_FpageAddRightsTo(L4_Fpage_t * f, L4_Word_t rwx)
+L4_INLINE L4_Fpage_t L4_FpageAddRightsTo(L4_Fpage_t *f, L4_Word_t rwx)
 {
-	f->X.rwx |= rwx;
-	return *f;
+    f->X.rwx |= rwx;
+    return *f;
 }
 
 L4_INLINE L4_Fpage_t L4_FpageRemoveRights(L4_Fpage_t f, L4_Word_t rwx)
 {
-	f.X.rwx &= ~rwx;
-	return f;
+    f.X.rwx &= ~rwx;
+    return f;
 }
 
 L4_INLINE L4_Fpage_t L4_FpageRemoveRightsFrom(L4_Fpage_t *f, L4_Word_t rwx)
 {
-	f->X.rwx &= ~rwx;
-	return *f;
+    f->X.rwx &= ~rwx;
+    return *f;
 }
 
 #if defined(__cplusplus)
-static inline L4_Fpage_t operator +(const L4_Fpage_t &f, L4_Word_t rwx)
+static inline L4_Fpage_t operator+(const L4_Fpage_t &f, L4_Word_t rwx)
 {
-	return L4_FpageAddRights(f, rwx);
+    return L4_FpageAddRights(f, rwx);
 }
 
-static inline L4_Fpage_t operator +=(L4_Fpage_t &f, L4_Word_t rwx)
+static inline L4_Fpage_t operator+=(L4_Fpage_t &f, L4_Word_t rwx)
 {
-	return L4_FpageAddRightsTo(&f, rwx);
+    return L4_FpageAddRightsTo(&f, rwx);
 }
 
-static inline L4_Fpage_t operator -(const L4_Fpage_t &f, L4_Word_t rwx)
+static inline L4_Fpage_t operator-(const L4_Fpage_t &f, L4_Word_t rwx)
 {
-	return L4_FpageRemoveRights(f, rwx);
+    return L4_FpageRemoveRights(f, rwx);
 }
 
-static inline L4_Fpage_t operator -=(L4_Fpage_t &f, L4_Word_t rwx)
+static inline L4_Fpage_t operator-=(L4_Fpage_t &f, L4_Word_t rwx)
 {
     return L4_FpageRemoveRightsFrom(&f, rwx);
 }
@@ -180,215 +262,208 @@ static inline L4_Fpage_t operator -=(L4_Fpage_t &f, L4_Word_t rwx)
 
 L4_INLINE L4_Fpage_t L4_Fpage(L4_Word_t BaseAddress, L4_Word_t FpageSize)
 {
-	L4_Fpage_t fp;
-	L4_Word_t msb = __L4_Msb(FpageSize);
-	fp.raw = BaseAddress;
-	fp.X.s = (1UL << msb) < FpageSize ? msb + 1 : msb;
-	fp.X.rwx = L4_NoAccess;
-	return fp;
+    L4_Fpage_t fp;
+    L4_Word_t msb = __L4_Msb(FpageSize);
+    fp.raw = BaseAddress;
+    fp.X.s = (1UL << msb) < FpageSize ? msb + 1 : msb;
+    fp.X.rwx = L4_NoAccess;
+    return fp;
 }
 
 L4_INLINE L4_Fpage_t L4_FpageLog2(L4_Word_t BaseAddress, int FpageSize)
 {
-	L4_Fpage_t fp;
-	fp.raw = BaseAddress;
-	fp.X.s = FpageSize;
-	fp.X.rwx = L4_NoAccess;
-	return fp;
+    L4_Fpage_t fp;
+    fp.raw = BaseAddress;
+    fp.X.s = FpageSize;
+    fp.X.rwx = L4_NoAccess;
+    return fp;
 }
 
 L4_INLINE L4_Word_t L4_Address(L4_Fpage_t f)
 {
-	return f.raw & ~((1UL << f.X.s) - 1);
+    return f.raw & ~((1UL << f.X.s) - 1);
 }
 
 L4_INLINE L4_Word_t L4_Size(L4_Fpage_t f)
 {
-	return f.X.s == 0 ? 0 : (1UL << f.X.s);
+    return f.X.s == 0 ? 0 : (1UL << f.X.s);
 }
 
 L4_INLINE L4_Word_t L4_SizeLog2(L4_Fpage_t f)
 {
-	return f.X.s;
+    return f.X.s;
 }
 
 /*
  * Thread IDs
  */
 typedef union {
-	L4_Word_t raw;
-	struct {
-		L4_BITFIELD2(L4_Word_t,
-				version : __14,
-				thread_no : __18);
-	} X;
+    L4_Word_t raw;
+    struct {
+        L4_BITFIELD2(L4_Word_t, version : __14, thread_no : __18);
+    } X;
 } L4_GthreadId_t;
 
 typedef union {
-	L4_Word_t raw;
-	struct {
-		L4_BITFIELD2(L4_Word_t,
-				__zeros : 6,
-				local_id : 26 __PLUS32);
-	} X;
+    L4_Word_t raw;
+    struct {
+        L4_BITFIELD2(L4_Word_t, __zeros : 6, local_id : 26 __PLUS32);
+    } X;
 } L4_LthreadId_t;
 
 typedef union {
-	L4_Word_t raw;
-	L4_GthreadId_t global;
-	L4_LthreadId_t local;
+    L4_Word_t raw;
+    L4_GthreadId_t global;
+    L4_LthreadId_t local;
 } L4_ThreadId_t;
 
-#define L4_nilthread		((L4_ThreadId_t) { raw : 0UL})
-#define L4_anythread		((L4_ThreadId_t) { raw : ~0UL})
-#define L4_anylocalthread	((L4_ThreadId_t) { local : { X : \
-					{ L4_SHUFFLE2(0, \
-						((1UL << (8 * sizeof(L4_Word_t) - 6)) - 1)) \
-					} } })
+#define L4_nilthread ((L4_ThreadId_t) {raw : 0UL})
+#define L4_anythread ((L4_ThreadId_t) {raw : ~0UL})
+#define L4_anylocalthread                                                      \
+    ((L4_ThreadId_t) {                                                         \
+        local :                                                                \
+            {X : {L4_SHUFFLE2(0, ((1UL << (8 * sizeof(L4_Word_t) - 6)) - 1))}} \
+    })
 
 L4_INLINE L4_ThreadId_t L4_GlobalId(L4_Word_t threadno, L4_Word_t version)
 {
-	L4_ThreadId_t t;
-	t.global.X.thread_no = threadno;
-	t.global.X.version = version;
-	return t;
+    L4_ThreadId_t t;
+    t.global.X.thread_no = threadno;
+    t.global.X.version = version;
+    return t;
 }
 
 L4_INLINE L4_Word_t L4_Version(L4_ThreadId_t t)
 {
-	return t.global.X.version;
+    return t.global.X.version;
 }
 
 L4_INLINE L4_Word_t L4_ThreadNo(L4_ThreadId_t t)
 {
-	return t.global.X.thread_no;
+    return t.global.X.thread_no;
 }
 
-L4_INLINE L4_Bool_t L4_IsThreadEqual(
-		const L4_ThreadId_t l,
-		const L4_ThreadId_t r)
+L4_INLINE L4_Bool_t L4_IsThreadEqual(const L4_ThreadId_t l,
+                                     const L4_ThreadId_t r)
 {
-	return l.raw == r.raw;
+    return l.raw == r.raw;
 }
 
-L4_INLINE L4_Bool_t L4_IsThreadNotEqual(
-		const L4_ThreadId_t l,
-		const L4_ThreadId_t r)
+L4_INLINE L4_Bool_t L4_IsThreadNotEqual(const L4_ThreadId_t l,
+                                        const L4_ThreadId_t r)
 {
-	return l.raw != r.raw;
+    return l.raw != r.raw;
 }
 
 #if defined(__cplusplus)
-static inline L4_Bool_t operator ==(
-		const L4_ThreadId_t & l,
-		const L4_ThreadId_t & r)
+static inline L4_Bool_t operator==(const L4_ThreadId_t &l,
+                                   const L4_ThreadId_t &r)
 {
-	return l.raw == r.raw;
+    return l.raw == r.raw;
 }
 
-static inline L4_Bool_t operator !=(
-		const L4_ThreadId_t & l,
-		const L4_ThreadId_t & r)
+static inline L4_Bool_t operator!=(const L4_ThreadId_t &l,
+                                   const L4_ThreadId_t &r)
 {
-	return l.raw != r.raw;
+    return l.raw != r.raw;
 }
 #endif /* __cplusplus */
 
 L4_INLINE L4_Bool_t L4_IsNilThread(L4_ThreadId_t t)
 {
-	return t.raw == 0;
+    return t.raw == 0;
 }
 
 L4_INLINE L4_Bool_t L4_IsLocalId(L4_ThreadId_t t)
 {
-	return t.local.X.__zeros == 0;
+    return t.local.X.__zeros == 0;
 }
 
 L4_INLINE L4_Bool_t L4_IsGlobalId(L4_ThreadId_t t)
 {
-	return t.local.X.__zeros != 0;
+    return t.local.X.__zeros != 0;
 }
 
 /*
  * Clock
  */
 typedef union {
-	L4_Word64_t raw;
-	struct {
-		L4_Word32_t low;
-		L4_Word32_t high;
-	} X;
+    L4_Word64_t raw;
+    struct {
+        L4_Word32_t low;
+        L4_Word32_t high;
+    } X;
 } L4_Clock_t;
 
 #if defined(__cplusplus)
-static inline L4_Clock_t operator +(const L4_Clock_t & l, const int r)
+static inline L4_Clock_t operator+(const L4_Clock_t &l, const int r)
 {
-	return (L4_Clock_t) { raw : l.raw + r };
+    return (L4_Clock_t) {raw : l.raw + r};
 }
 
-static inline L4_Clock_t operator +(const L4_Clock_t & l, const L4_Word64_t r)
+static inline L4_Clock_t operator+(const L4_Clock_t &l, const L4_Word64_t r)
 {
-	return (L4_Clock_t) { raw : l.raw + r };
+    return (L4_Clock_t) {raw : l.raw + r};
 }
 
-static inline L4_Clock_t operator +(const L4_Clock_t & l, const L4_Clock_t r)
+static inline L4_Clock_t operator+(const L4_Clock_t &l, const L4_Clock_t r)
 {
-	return (L4_Clock_t) { raw : l.raw + r.raw };
+    return (L4_Clock_t) {raw : l.raw + r.raw};
 }
 
-static inline L4_Clock_t operator -(const L4_Clock_t & l, const int r)
+static inline L4_Clock_t operator-(const L4_Clock_t &l, const int r)
 {
-	return (L4_Clock_t) { raw : l.raw - r };
+    return (L4_Clock_t) {raw : l.raw - r};
 }
 
-static inline L4_Clock_t operator -(const L4_Clock_t & l, const L4_Word64_t r)
+static inline L4_Clock_t operator-(const L4_Clock_t &l, const L4_Word64_t r)
 {
-	return (L4_Clock_t) { raw : l.raw - r };
+    return (L4_Clock_t) {raw : l.raw - r};
 }
 
-static inline L4_Clock_t operator -(const L4_Clock_t & l, const L4_Clock_t r)
+static inline L4_Clock_t operator-(const L4_Clock_t &l, const L4_Clock_t r)
 {
-	return (L4_Clock_t) { raw : l.raw - r.raw };
+    return (L4_Clock_t) {raw : l.raw - r.raw};
 }
 #endif /* __cplusplus */
 
 L4_INLINE L4_Clock_t L4_ClockAddUsec(const L4_Clock_t c, const L4_Word64_t r)
 {
-	return (L4_Clock_t) { raw : c.raw + r };
+    return (L4_Clock_t) {raw : c.raw + r};
 }
 
 L4_INLINE L4_Clock_t L4_ClockSubUsec(const L4_Clock_t c, const L4_Word64_t r)
 {
-	return (L4_Clock_t) { raw : c.raw - r };
+    return (L4_Clock_t) {raw : c.raw - r};
 }
 
 #if defined(__cplusplus)
-static inline L4_Bool_t operator <(const L4_Clock_t &l, const L4_Clock_t &r)
+static inline L4_Bool_t operator<(const L4_Clock_t &l, const L4_Clock_t &r)
 {
-	return l.raw < r.raw;
+    return l.raw < r.raw;
 }
 
-static inline L4_Bool_t operator >(const L4_Clock_t &l, const L4_Clock_t &r)
+static inline L4_Bool_t operator>(const L4_Clock_t &l, const L4_Clock_t &r)
 {
-	return l.raw > r.raw;
+    return l.raw > r.raw;
 }
 
-static inline L4_Bool_t operator <=(const L4_Clock_t &l, const L4_Clock_t &r)
+static inline L4_Bool_t operator<=(const L4_Clock_t &l, const L4_Clock_t &r)
 {
-	return l.raw <= r.raw;
+    return l.raw <= r.raw;
 }
 
-static inline L4_Bool_t operator >=(const L4_Clock_t &l, const L4_Clock_t &r)
+static inline L4_Bool_t operator>=(const L4_Clock_t &l, const L4_Clock_t &r)
 {
-	return l.raw >= r.raw;
+    return l.raw >= r.raw;
 }
 
-static inline L4_Bool_t operator ==(const L4_Clock_t &l, const L4_Clock_t &r)
+static inline L4_Bool_t operator==(const L4_Clock_t &l, const L4_Clock_t &r)
 {
-	return l.raw == r.raw;
+    return l.raw == r.raw;
 }
 
-static inline L4_Bool_t operator !=(const L4_Clock_t &l, const L4_Clock_t &r)
+static inline L4_Bool_t operator!=(const L4_Clock_t &l, const L4_Clock_t &r)
 {
     return l.raw != r.raw;
 }
@@ -397,104 +472,111 @@ static inline L4_Bool_t operator !=(const L4_Clock_t &l, const L4_Clock_t &r)
 
 L4_INLINE L4_Bool_t L4_IsClockEarlier(const L4_Clock_t l, const L4_Clock_t r)
 {
-	return l.raw < r.raw;
+    return l.raw < r.raw;
 }
 
 L4_INLINE L4_Bool_t L4_IsClockLater(const L4_Clock_t l, const L4_Clock_t r)
 {
-	return l.raw > r.raw;
+    return l.raw > r.raw;
 }
 
 L4_INLINE L4_Bool_t L4_IsClockEqual(const L4_Clock_t l, const L4_Clock_t r)
 {
-	return l.raw == r.raw;
+    return l.raw == r.raw;
 }
 
 L4_INLINE L4_Bool_t L4_IsClockNotEqual(const L4_Clock_t l, const L4_Clock_t r)
 {
-	return l.raw != r.raw;
+    return l.raw != r.raw;
 }
 
 /*
  * Time
  */
 typedef union {
-	L4_Word16_t raw;
-	struct {
-		L4_BITFIELD3(L4_Word_t,
-				m : 10,
-				e : 5,
-				a : 1);
-	} period;
-	struct {
-		L4_BITFIELD4(L4_Word_t,
-				m : 10,
-				c : 1,
-				e : 4,
-				a : 1);
-	} point;
+    L4_Word16_t raw;
+    struct {
+        L4_BITFIELD3(L4_Word_t, m : 10, e : 5, a : 1);
+    } period;
+    struct {
+        L4_BITFIELD4(L4_Word_t, m : 10, c : 1, e : 4, a : 1);
+    } point;
 } L4_Time_t;
 
-#define L4_Never	((L4_Time_t) { raw : 0UL })
-#define L4_ZeroTime	((L4_Time_t) { period : { L4_SHUFFLE3(0, 1, 0) }})
+#define L4_Never ((L4_Time_t) {raw : 0UL})
+#define L4_ZeroTime ((L4_Time_t) {period : {L4_SHUFFLE3(0, 1, 0)}})
 
 L4_INLINE L4_Time_t L4_TimePeriod(L4_Word64_t microseconds)
 {
-#   define __L4_SET_TIMEPERIOD(exp, man) \
-	do { time.period.m = man; time.period.e = exp; } while (0)
-#   define __L4_TRY_EXPONENT(N) \
-	else if (microseconds < (1UL << N)) \
-	__L4_SET_TIMEPERIOD (N - 10, microseconds >> (N - 10))
-
-	L4_Time_t time;
-	time.raw = 0;
-
-	if (__builtin_constant_p(microseconds)) {
-		if (0) {}
-		__L4_TRY_EXPONENT (10); __L4_TRY_EXPONENT(11);
-		__L4_TRY_EXPONENT (12); __L4_TRY_EXPONENT(13);
-		__L4_TRY_EXPONENT (14); __L4_TRY_EXPONENT(15);
-		__L4_TRY_EXPONENT (16); __L4_TRY_EXPONENT(17);
-		__L4_TRY_EXPONENT (18); __L4_TRY_EXPONENT(19);
-		__L4_TRY_EXPONENT (20); __L4_TRY_EXPONENT(21);
-		__L4_TRY_EXPONENT (22); __L4_TRY_EXPONENT(23);
-		__L4_TRY_EXPONENT (24); __L4_TRY_EXPONENT(25);
-		__L4_TRY_EXPONENT (26); __L4_TRY_EXPONENT(27);
-		__L4_TRY_EXPONENT (28); __L4_TRY_EXPONENT(29);
-		__L4_TRY_EXPONENT (30); __L4_TRY_EXPONENT(31);
-		else
-			return L4_Never;
-	}
-	else {
-		L4_Word_t l4_exp = 0;
-		L4_Word_t man = microseconds;
-		while (man >= (1 << 10)) {
-			man >>= 1;
-			l4_exp++;
-		}
-		if (l4_exp <= 31)
-			__L4_SET_TIMEPERIOD(l4_exp, man);
-		else
-			return L4_Never;
-	}
+#define __L4_SET_TIMEPERIOD(exp, man) \
+    do {                              \
+        time.period.m = man;          \
+        time.period.e = exp;          \
+    } while (0)
+#define __L4_TRY_EXPONENT(N)            \
+    else if (microseconds < (1UL << N)) \
+        __L4_SET_TIMEPERIOD(N - 10, microseconds >> (N - 10))
 
-	return time;
-#   undef __L4_TRY_EXPONENT
-#   undef __L4_SET_TIMEPERIOD
+    L4_Time_t time;
+    time.raw = 0;
+
+    if (__builtin_constant_p(microseconds)) {
+        if (0) {
+        }
+        __L4_TRY_EXPONENT(10);
+        __L4_TRY_EXPONENT(11);
+        __L4_TRY_EXPONENT(12);
+        __L4_TRY_EXPONENT(13);
+        __L4_TRY_EXPONENT(14);
+        __L4_TRY_EXPONENT(15);
+        __L4_TRY_EXPONENT(16);
+        __L4_TRY_EXPONENT(17);
+        __L4_TRY_EXPONENT(18);
+        __L4_TRY_EXPONENT(19);
+        __L4_TRY_EXPONENT(20);
+        __L4_TRY_EXPONENT(21);
+        __L4_TRY_EXPONENT(22);
+        __L4_TRY_EXPONENT(23);
+        __L4_TRY_EXPONENT(24);
+        __L4_TRY_EXPONENT(25);
+        __L4_TRY_EXPONENT(26);
+        __L4_TRY_EXPONENT(27);
+        __L4_TRY_EXPONENT(28);
+        __L4_TRY_EXPONENT(29);
+        __L4_TRY_EXPONENT(30);
+        __L4_TRY_EXPONENT(31);
+        else return L4_Never;
+    } else {
+        L4_Word_t l4_exp = 0;
+        L4_Word_t man = microseconds;
+        while (man >= (1 << 10)) {
+            man >>= 1;
+            l4_exp++;
+        }
+        if (l4_exp <= 31)
+            __L4_SET_TIMEPERIOD(l4_exp, man);
+        else
+            return L4_Never;
+    }
+
+    return time;
+#undef __L4_TRY_EXPONENT
+#undef __L4_SET_TIMEPERIOD
 }
 
 #if 0
 L4_INLINE L4_Time_t L4_TimePoint (L4_Clock_t at)
 {
-#   define __L4_SET_TIMEPOINT(exp, man, carry) \
-        do { time.point.m = man; \
-	     time.point.e = exp; \
-	     time.point.c = carry; \
-	     time.point.a = 1; \
-	} while (0)
-#   define __L4_TRY_EXPONENT(N) \
-	else if (microseconds < (1 << (10+N))) \
-	    __L4_SET_TIMEPOINT (N, now.raw >> N, (now.raw >> (N+10)) & 0x1)
+#define __L4_SET_TIMEPOINT(exp, man, carry) \
+    do {                                    \
+        time.point.m = man;                 \
+        time.point.e = exp;                 \
+        time.point.c = carry;               \
+        time.point.a = 1;                   \
+    } while (0)
+#define __L4_TRY_EXPONENT(N)                 \
+    else if (microseconds < (1 << (10 + N))) \
+        __L4_SET_TIMEPOINT(N, now.raw >> N, (now.raw >> (N + 10)) & 0x1)
 
     L4_Clock_t now = L4_SystemClock ();
     L4_Word_t int microseconds = now.raw - at.raw;
@@ -526,8 +608,8 @@ L4_INLINE L4_Time_t L4_TimePoint (L4_Clock_t at)
     }
 
     return time;
-#   undef __L4_TRY_EXPONENT
-#   undef __L4_SET_TIMEPOINT
+#undef __L4_TRY_EXPONENT
+#undef __L4_SET_TIMEPOINT
 }
 #endif
 
diff --git a/user/include/libposix/pthread.h b/user/include/libposix/pthread.h
index d1a4e7b1..dd2ecc77 100644
--- a/user/include/libposix/pthread.h
+++ b/user/include/libposix/pthread.h
@@ -10,7 +10,8 @@
 
 int pthread_create(pthread_t *restrict thread,
                    const pthread_attr_t *restrict attr,
-                   void *(*start_routine)(void*), void *restrict arg);
+                   void *(*start_routine)(void *),
+                   void *restrict arg);
 int pthread_detach(pthread_t thread);
 void pthread_exit(void *value_ptr);
 int pthread_join(pthread_t thread, void **value_ptr);
diff --git a/user/include/libposix/sys/types.h b/user/include/libposix/sys/types.h
index 7fa3f41d..0801af9e 100644
--- a/user/include/libposix/sys/types.h
+++ b/user/include/libposix/sys/types.h
@@ -5,7 +5,7 @@
 
 /* FIXME: This should be moved to time.h */
 struct timespec {
-	uint64_t nsec;
+    uint64_t nsec;
 };
 
 /* FIXME: Define proper type for pthread type */
diff --git a/user/include/libposix/unimplemented.h b/user/include/libposix/unimplemented.h
index 8356e732..5f134e36 100644
--- a/user/include/libposix/unimplemented.h
+++ b/user/include/libposix/unimplemented.h
@@ -2,17 +2,16 @@
 #define __UNIMPLEMENTED_H__
 
 #define ESC "\e["
-#define LIGHT_RED    ESC "31;1m"
-#define BLACK        ESC "0m"
+#define LIGHT_RED ESC "31;1m"
+#define BLACK ESC "0m"
 
 #include <l4io.h>
 
-#define UNIMPLEMENTED()						\
-	do {							\
-		printf("%s", LIGHT_RED);			\
-		printf("\nUnimplemented: %s, at %s:%d",		\
-		       __func__, __FILE__, __LINE__);		\
-		printf("%s\n", BLACK);				\
-	} while (0)						\
+#define UNIMPLEMENTED()                                                        \
+    do {                                                                       \
+        printf("%s", LIGHT_RED);                                               \
+        printf("\nUnimplemented: %s, at %s:%d", __func__, __FILE__, __LINE__); \
+        printf("%s\n", BLACK);                                                 \
+    } while (0)
 
 #endif
diff --git a/user/include/user_interrupt.h b/user/include/user_interrupt.h
index eca05ace..6d4c659e 100644
--- a/user/include/user_interrupt.h
+++ b/user/include/user_interrupt.h
@@ -2,15 +2,15 @@
 #define _USER_INTERRUPT_H_
 #include INC_PLAT(nvic.h)
 
-#include <l4/thread.h>
+#include <interrupt_ipc.h>
+#include <l4/ipc.h>
 #include <l4/kip.h>
+#include <l4/thread.h>
 #include <l4/utcb.h>
-#include <l4/ipc.h>
 #include <types.h>
 #include <user_runtime.h>
-#include <interrupt_ipc.h>
 
-#define IRQ_STACK_SIZE	512
+#define IRQ_STACK_SIZE 512
 
 typedef void (*irq_handler_t)(void);
 
diff --git a/user/include/user_runtime.h b/user/include/user_runtime.h
index eafc12fa..328140a4 100644
--- a/user/include/user_runtime.h
+++ b/user/include/user_runtime.h
@@ -6,48 +6,44 @@
 #ifndef USER_RUNTIME_H
 #define USER_RUNTIME_H
 
-#include <l4/types.h>
 #include <l4/ipc.h>
+#include <l4/types.h>
 
 typedef struct user_struct user_struct;
 typedef void (*user_entry)(user_struct *);
 
 typedef struct {
-	L4_Word_t base;
-	L4_Word_t size;
+    L4_Word_t base;
+    L4_Word_t size;
 } user_fpage_t;
 
 struct user_struct {
-	L4_Word_t tid;
-	void (*entry)(void);
-	L4_Word_t thread_num;
-	user_fpage_t *fpages;
-	const char *name;
+    L4_Word_t tid;
+    void (*entry)(void);
+    L4_Word_t thread_num;
+    user_fpage_t *fpages;
+    const char *name;
 };
 
-#define DECLARE_FPAGE(_base, _size)	\
-	{.base = _base, .size = _size},
-
-#define DECLARE_USER(_tid, _name, _entry, ...)	\
-	user_fpage_t _user_fpages_##_name[]	\
-			__attribute__((section(".user_data"))) = {	\
-		__VA_ARGS__	\
-		{.base = 0x0, .size = 0x0}	\
-	};	\
-	static void _user_entry_##_name(void);	\
-	user_struct _user_struct_##_name	\
-			__attribute__((section(".user_runtime"))) = {	\
-		.tid = _tid,	\
-		.entry = _user_entry_##_name,	\
-		.fpages = _user_fpages_##_name,	\
-		.name = #_name,	\
-	};	\
-	static void __USER_TEXT _user_entry_##_name(void)	\
-	{	\
-		pager_thread(&_user_struct_##_name, _entry);  \
-		while (1)	\
-			L4_Sleep(L4_Never);	\
-	}
+#define DECLARE_FPAGE(_base, _size) {.base = _base, .size = _size},
+
+#define DECLARE_USER(_tid, _name, _entry, ...)                             \
+    user_fpage_t _user_fpages_##_name[] __attribute__((                    \
+        section(".user_data"))) = {__VA_ARGS__{.base = 0x0, .size = 0x0}}; \
+    static void _user_entry_##_name(void);                                 \
+    user_struct _user_struct_##_name                                       \
+        __attribute__((section(".user_runtime"))) = {                      \
+            .tid = _tid,                                                   \
+            .entry = _user_entry_##_name,                                  \
+            .fpages = _user_fpages_##_name,                                \
+            .name = #_name,                                                \
+    };                                                                     \
+    static void __USER_TEXT _user_entry_##_name(void)                      \
+    {                                                                      \
+        pager_thread(&_user_struct_##_name, _entry);                       \
+        while (1)                                                          \
+            L4_Sleep(L4_Never);                                            \
+    }
 
 #include <l4/pager.h>
 
diff --git a/user/lib/io/l4io.c b/user/lib/io/l4io.c
index c19d4319..e4c95d49 100644
--- a/user/lib/io/l4io.c
+++ b/user/lib/io/l4io.c
@@ -3,39 +3,36 @@
  * found in the LICENSE file.
  */
 
-#include <l4io.h>
 #include <l4/ipc.h>
-#include <thread.h>
+#include <l4io.h>
 #include <platform/link.h>
+#include <thread.h>
 
 int __USER_TEXT printf(const char *format, ...)
 {
-	L4_Msg_t msg;
-	va_list va;
+    L4_Msg_t msg;
+    va_list va;
 
-	va_start(va, format);
+    va_start(va, format);
 
-	L4_MsgClear(&msg);
-	L4_MsgAppendWord(&msg, (L4_Word_t)format);
-	L4_MsgAppendWord(&msg, (L4_Word_t)&va);
+    L4_MsgClear(&msg);
+    L4_MsgAppendWord(&msg, (L4_Word_t) format);
+    L4_MsgAppendWord(&msg, (L4_Word_t) &va);
 
-	L4_MsgLoad(&msg);
-	L4_Send((L4_ThreadId_t) {
-		.raw = TID_TO_GLOBALID(THREAD_LOG)
-	});
+    L4_MsgLoad(&msg);
+    L4_Send((L4_ThreadId_t) {.raw = TID_TO_GLOBALID(THREAD_LOG)});
 
-	va_end(va);
+    va_end(va);
 
-	return 0;
+    return 0;
 }
 
 void __USER_TEXT putc(int c)
 {
-	printf("%c", c);
+    printf("%c", c);
 }
 
-int __USER_TEXT __attribute((weak))
-semihost_puts(char *log)
+int __USER_TEXT __attribute((weak)) semihost_puts(char *log)
 {
-	return 0;
+    return 0;
 }
diff --git a/user/lib/io/semihost-io.c b/user/lib/io/semihost-io.c
index 98a17bcd..316380e3 100644
--- a/user/lib/io/semihost-io.c
+++ b/user/lib/io/semihost-io.c
@@ -6,80 +6,77 @@
 #include "lib/string.h"
 
 enum SEMIHOST_SYSCALL {
-	SYS_OPEN = 0x01,
-	SYS_CLOSE,
-	SYS_WRITEC,
-	SYS_WRITE0,
-	SYS_WRITE,
-	SYS_READ,
-	SYS_READC,
-	SYS_ISERROR,
-	SYS_ISTTY,
-	SYS_SEEK,
-	SYS_FLEN = 0xC,
-	SYS_TMPNAM,
-	SYS_REMOVE,
-	SYS_RENAME,
-	SYS_CLOCK,
-	SYS_TIME,
-	SYS_SYSTEM,
-	SYS_ERRNO,
-	SYS_GET_CMDLINE = 0x15,
-	SYS_HEAPINFO,
-	SYS_EXIT = 0x18,
-	SYS_ELAPSED = 0x30,
-	SYS_TICKFREQ
+    SYS_OPEN = 0x01,
+    SYS_CLOSE,
+    SYS_WRITEC,
+    SYS_WRITE0,
+    SYS_WRITE,
+    SYS_READ,
+    SYS_READC,
+    SYS_ISERROR,
+    SYS_ISTTY,
+    SYS_SEEK,
+    SYS_FLEN = 0xC,
+    SYS_TMPNAM,
+    SYS_REMOVE,
+    SYS_RENAME,
+    SYS_CLOCK,
+    SYS_TIME,
+    SYS_SYSTEM,
+    SYS_ERRNO,
+    SYS_GET_CMDLINE = 0x15,
+    SYS_HEAPINFO,
+    SYS_EXIT = 0x18,
+    SYS_ELAPSED = 0x30,
+    SYS_TICKFREQ
 };
 
 typedef union param_t {
-	int entry_int;
-	void *entry_ptr;
-	char *entry_chr;
+    int entry_int;
+    void *entry_ptr;
+    char *entry_chr;
 } param;
 
-extern int strlen( const char *src );
+extern int strlen(const char *src);
 
 int __USER_TEXT semihost_call(enum SEMIHOST_SYSCALL action, void *param)
 {
-	static volatile int result;
-	__asm__ __volatile__(
-		"bkpt 0xAB\n"
-		"nop\n"
-		"bx lr\n"
-		: "=r" (result) ::
-	);
-	return result;
+    static volatile int result;
+    __asm__ __volatile__(
+        "bkpt 0xAB\n"
+        "nop\n"
+        "bx lr\n"
+        : "=r"(result)::);
+    return result;
 }
 
 int __USER_TEXT semihost_open(char *file, int mode)
 {
-	return semihost_call(SYS_OPEN, (param []) {
-	                                {.entry_chr = file},
-	                                {.entry_int = mode},
-	                                {.entry_int = strlen(file)}});
+    return semihost_call(SYS_OPEN, (param[]) {{.entry_chr = file},
+                                              {.entry_int = mode},
+                                              {.entry_int = strlen(file)}});
 }
 
 int __USER_TEXT semihost_close(int fp)
 {
-	return semihost_call(SYS_CLOSE, (param []) {{.entry_int = fp}});
+    return semihost_call(SYS_CLOSE, (param[]) {{.entry_int = fp}});
 }
 
 int __USER_TEXT semihost_write(int fp, char *buffer)
 {
-	return semihost_call(SYS_WRITE, (param []) {
-	                                 {.entry_int = fp},
-	                                 {.entry_chr = buffer},
-	                                 {.entry_int = strlen(buffer)}});
+    return semihost_call(SYS_WRITE, (param[]) {{.entry_int = fp},
+                                               {.entry_chr = buffer},
+                                               {.entry_int = strlen(buffer)}});
 }
 
 int __USER_TEXT semihost_puts(char *log)
 {
-	char file[6] = "mylog";
-	int handle;
-	handle = semihost_open(file, 6);
-	if (handle == -1)
-		return -1;
-	semihost_write(handle, log);
-	semihost_close(handle);
-	return 0;
+    char file[6] = "mylog";
+    int handle;
+    handle = semihost_open(file, 6);
+    if (handle == -1)
+        return -1;
+    semihost_write(handle, log);
+    semihost_close(handle);
+    return 0;
 }
diff --git a/user/lib/io/user_interrupt.c b/user/lib/io/user_interrupt.c
index 4676af89..c5e7ab6d 100644
--- a/user/lib/io/user_interrupt.c
+++ b/user/lib/io/user_interrupt.c
@@ -2,119 +2,117 @@
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-#include <user_interrupt.h>
 #include <interrupt_ipc.h>
-#include <l4io.h>
 #include <l4/ipc.h>
 #include <l4/pager.h>
+#include <l4io.h>
 #include <thread.h>
+#include <user_interrupt.h>
 
 __USER_TEXT
 static void *__interrupt_handler_thread(void *arg)
 {
-	do {
-		L4_Msg_t msg;
-		L4_MsgTag_t tag;
-		irq_handler_t handler;
-		L4_Word_t action;
-		L4_ThreadId_t recv_tid = {
-			.raw = TID_TO_GLOBALID(THREAD_INTERRUPT)};
-
-		tag = L4_Receive(recv_tid);
-
-		L4_MsgStore(tag, &msg);
-		handler = (irq_handler_t)L4_MsgWord(&msg, IRQ_IPC_HANDLER);
-		action = L4_MsgWord(&msg, IRQ_IPC_ACTION);
-
-		switch (action) {
-		case USER_IRQ_ENABLE:
-			handler();
-			break;
-		case USER_IRQ_FREE:
-			return NULL;
-		}
-	} while(1);
-
+    do {
+        L4_Msg_t msg;
+        L4_MsgTag_t tag;
+        irq_handler_t handler;
+        L4_Word_t action;
+        L4_ThreadId_t recv_tid = {.raw = TID_TO_GLOBALID(THREAD_INTERRUPT)};
+
+        tag = L4_Receive(recv_tid);
+
+        L4_MsgStore(tag, &msg);
+        handler = (irq_handler_t) L4_MsgWord(&msg, IRQ_IPC_HANDLER);
+        action = L4_MsgWord(&msg, IRQ_IPC_ACTION);
+
+        switch (action) {
+        case USER_IRQ_ENABLE:
+            handler();
+            break;
+        case USER_IRQ_FREE:
+            return NULL;
+        }
+    } while (1);
 }
 
 __USER_TEXT
-static void __irq_msg(
-	L4_Msg_t *out_msg, L4_ThreadId_t tid,
-	unsigned int irq, irq_handler_t handler,
-	L4_Word_t action, uint16_t priority)
+static void __irq_msg(L4_Msg_t *out_msg,
+                      L4_ThreadId_t tid,
+                      unsigned int irq,
+                      irq_handler_t handler,
+                      L4_Word_t action,
+                      uint16_t priority)
 {
-	L4_Word_t irq_data[IRQ_IPC_MSG_NUM];
+    L4_Word_t irq_data[IRQ_IPC_MSG_NUM];
 
-	L4_MsgClear(out_msg);
+    L4_MsgClear(out_msg);
 
-	irq_data[IRQ_IPC_IRQN] = (L4_Word_t)irq;
-	irq_data[IRQ_IPC_TID] = (L4_Word_t)tid.raw;
-	irq_data[IRQ_IPC_HANDLER] = (L4_Word_t)handler;
-	irq_data[IRQ_IPC_ACTION] = (L4_Word_t)action;
-	irq_data[IRQ_IPC_PRIORITY] = (L4_Word_t)priority;
+    irq_data[IRQ_IPC_IRQN] = (L4_Word_t) irq;
+    irq_data[IRQ_IPC_TID] = (L4_Word_t) tid.raw;
+    irq_data[IRQ_IPC_HANDLER] = (L4_Word_t) handler;
+    irq_data[IRQ_IPC_ACTION] = (L4_Word_t) action;
+    irq_data[IRQ_IPC_PRIORITY] = (L4_Word_t) priority;
 
-	/* Create msg for irq request */
-	L4_MsgPut(out_msg, USER_INTERRUPT_LABEL,
-              IRQ_IPC_MSG_NUM, irq_data, 0, NULL);
+    /* Create msg for irq request */
+    L4_MsgPut(out_msg, USER_INTERRUPT_LABEL, IRQ_IPC_MSG_NUM, irq_data, 0,
+              NULL);
 }
 
 __USER_TEXT
 static L4_Word_t __request_irq(L4_Msg_t *msg)
 {
-	L4_MsgTag_t ret;
-	L4_ThreadId_t send_tid = {
-		.raw = TID_TO_GLOBALID(THREAD_IRQ_REQUEST)};
+    L4_MsgTag_t ret;
+    L4_ThreadId_t send_tid = {.raw = TID_TO_GLOBALID(THREAD_IRQ_REQUEST)};
 
-	/* Load msg to registers */
-	L4_MsgLoad(msg);
+    /* Load msg to registers */
+    L4_MsgLoad(msg);
 
-	/* register irq in kernel */
-	ret = L4_Send(send_tid);
+    /* register irq in kernel */
+    ret = L4_Send(send_tid);
 
-	return ret.raw;
+    return ret.raw;
 }
 
 __USER_TEXT
 L4_Word_t request_irq(int irq, irq_handler_t handler, uint16_t priority)
 {
-	L4_Msg_t msg;
-	L4_ThreadId_t tid;
+    L4_Msg_t msg;
+    L4_ThreadId_t tid;
 
-	/* Create thread for interrupt handler */
-	tid = pager_create_thread();
-	pager_start_thread(tid, __interrupt_handler_thread, NULL);
-	__irq_msg(&msg, tid, irq, handler, USER_IRQ_ENABLE, priority);
+    /* Create thread for interrupt handler */
+    tid = pager_create_thread();
+    pager_start_thread(tid, __interrupt_handler_thread, NULL);
+    __irq_msg(&msg, tid, irq, handler, USER_IRQ_ENABLE, priority);
 
-	return __request_irq(&msg);
+    return __request_irq(&msg);
 }
 
 __USER_TEXT
 L4_Word_t enable_irq(int irq)
 {
-	L4_Msg_t msg;
+    L4_Msg_t msg;
 
-	__irq_msg(&msg, L4_nilthread, irq, NULL, USER_IRQ_ENABLE, -1);
+    __irq_msg(&msg, L4_nilthread, irq, NULL, USER_IRQ_ENABLE, -1);
 
-	return __request_irq(&msg);
+    return __request_irq(&msg);
 }
 
 __USER_TEXT
 L4_Word_t disable_irq(int irq)
 {
-	L4_Msg_t msg;
+    L4_Msg_t msg;
 
-	__irq_msg(&msg, L4_nilthread, irq, NULL, USER_IRQ_DISABLE, -1);
+    __irq_msg(&msg, L4_nilthread, irq, NULL, USER_IRQ_DISABLE, -1);
 
-	return __request_irq(&msg);
+    return __request_irq(&msg);
 }
 
 __USER_TEXT
 L4_Word_t free_irq(int irq)
 {
-	L4_Msg_t msg;
+    L4_Msg_t msg;
 
-	__irq_msg(&msg, L4_nilthread, irq, NULL, USER_IRQ_FREE, -1);
+    __irq_msg(&msg, L4_nilthread, irq, NULL, USER_IRQ_FREE, -1);
 
-	return __request_irq(&msg);
+    return __request_irq(&msg);
 }
-
diff --git a/user/lib/l4/pager.c b/user/lib/l4/pager.c
index 0b90a153..9db33133 100644
--- a/user/lib/l4/pager.c
+++ b/user/lib/l4/pager.c
@@ -3,383 +3,382 @@
  * found in the LICENSE file.
  */
 
-#include <l4io.h>
 #include <l4/ipc.h>
-#include <l4/utcb.h>
-#include <l4/pager.h>
 #include <l4/kip_types.h>
+#include <l4/pager.h>
+#include <l4/utcb.h>
+#include <l4io.h>
 
 #define STACK_SIZE 0x200
 
 /* Kernel requires 256-byte alignment for UTCB addresses */
 #define NODE_ALIGN 256
 #define NODE_SIZE_ALIGNED \
-	(((UTCB_SIZE + STACK_SIZE) + NODE_ALIGN - 1) & ~(NODE_ALIGN - 1))
+    (((UTCB_SIZE + STACK_SIZE) + NODE_ALIGN - 1) & ~(NODE_ALIGN - 1))
 
 typedef void *thr_handler_t(void *);
 
 struct thread_node {
-	L4_Word_t base;			/* stack + utcb */
-	L4_ThreadId_t tid;
+    L4_Word_t base; /* stack + utcb */
+    L4_ThreadId_t tid;
 };
 
 static inline void use_thread_node(struct thread_node *node)
 {
-	node->base |= 0x1;
+    node->base |= 0x1;
 }
 
 static inline void free_thread_node(struct thread_node *node)
 {
-	node->base &= ~0x1;
+    node->base &= ~0x1;
 }
 
-#define IS_THREAD_NODE_USED(node) \
-	((node)->base & 0x1)
+#define IS_THREAD_NODE_USED(node) ((node)->base & 0x1)
 
-#define THREAD_NODE_BASE(node) \
-	((node)->base & ~0x1)
+#define THREAD_NODE_BASE(node) ((node)->base & ~0x1)
 
 struct thread_pool {
-	struct thread_node *all_nodes;
-	L4_Word_t node_num;
-	L4_ThreadId_t pager_tid;
+    struct thread_node *all_nodes;
+    L4_Word_t node_num;
+    L4_ThreadId_t pager_tid;
 };
 
 static inline int find_thread_index(struct thread_pool *pool, L4_ThreadId_t tid)
 {
-	return ((tid.raw - (pool->pager_tid).raw) >> 14) - 1;
+    return ((tid.raw - (pool->pager_tid).raw) >> 14) - 1;
 }
 
 static inline L4_Word_t user_fpage_number(user_fpage_t *fpages)
 {
-	int num = 0;
+    int num = 0;
 
-	while (fpages[num].base != 0 || fpages[num].size != 0)
-		num++;
+    while (fpages[num].base != 0 || fpages[num].size != 0)
+        num++;
 
-	return num;
+    return num;
 }
 
 __USER_TEXT
 static struct thread_pool *init_thread_pool(L4_Word_t res_base,
-        L4_Word_t res_size,
-        L4_Word_t heap_base,
-        L4_Word_t heap_size)
+                                            L4_Word_t res_size,
+                                            L4_Word_t heap_base,
+                                            L4_Word_t heap_size)
 {
-	L4_Word_t node_num, i;
-	L4_Word_t num1, num2;
-	struct thread_pool *pool;
-	struct thread_node *nodes;
+    L4_Word_t node_num, i;
+    L4_Word_t num1, num2;
+    struct thread_pool *pool;
+    struct thread_node *nodes;
 
-	num1 = (heap_size - sizeof(struct thread_pool)) / sizeof(struct thread_node);
-	num2 = (res_size) / NODE_SIZE_ALIGNED;
+    num1 =
+        (heap_size - sizeof(struct thread_pool)) / sizeof(struct thread_node);
+    num2 = (res_size) / NODE_SIZE_ALIGNED;
 
-	node_num = (num1 < num2) ? num1 : num2;
-	node_num = (node_num > THREAD_MAX_NUM) ? THREAD_MAX_NUM : node_num;
+    node_num = (num1 < num2) ? num1 : num2;
+    node_num = (node_num > THREAD_MAX_NUM) ? THREAD_MAX_NUM : node_num;
 
-	pool = (struct thread_pool *)heap_base;
-	nodes = (struct thread_node *)(heap_base + sizeof(struct thread_pool));
+    pool = (struct thread_pool *) heap_base;
+    nodes = (struct thread_node *) (heap_base + sizeof(struct thread_pool));
 
-	pool->node_num = node_num;
-	pool->all_nodes = nodes;
-	pool->pager_tid = L4_MyGlobalId();
+    pool->node_num = node_num;
+    pool->all_nodes = nodes;
+    pool->pager_tid = L4_MyGlobalId();
 
-	if (res_base & 0x1) {
-		printf("unalign res base\n");
-		return NULL;
-	}
+    if (res_base & 0x1) {
+        printf("unalign res base\n");
+        return NULL;
+    }
 
-	for (i = 1 ; i < node_num ; i++) {
-		nodes[i].base = res_base;
-		nodes[i].tid.raw = 0;
-		res_base += NODE_SIZE_ALIGNED;
-	}
+    for (i = 1; i < node_num; i++) {
+        nodes[i].base = res_base;
+        nodes[i].tid.raw = 0;
+        res_base += NODE_SIZE_ALIGNED;
+    }
 
-	return pool;
+    return pool;
 }
 
 __USER_TEXT
 static L4_Word_t fetch_free_thread_index(struct thread_pool *pool)
 {
-	int i;
-	struct thread_node *node;
+    int i;
+    struct thread_node *node;
 
-	for (i = 1 ; i < pool->node_num ; i++) {
-		node = &pool->all_nodes[i];
-		if (!IS_THREAD_NODE_USED(node))
-			break;
-	}
+    for (i = 1; i < pool->node_num; i++) {
+        node = &pool->all_nodes[i];
+        if (!IS_THREAD_NODE_USED(node))
+            break;
+    }
 
-	if (i == pool->node_num)
-		return 0;
+    if (i == pool->node_num)
+        return 0;
 
-	return i;
+    return i;
 }
 
 __USER_TEXT
 static struct thread_node *find_thread_node(struct thread_pool *pool,
-        L4_ThreadId_t tid)
+                                            L4_ThreadId_t tid)
 {
-	int i;
+    int i;
 
-	for (i = 1 ; i < pool->node_num ; i++) {
-		if (pool->all_nodes[i].tid.raw == tid.raw &&
-		    IS_THREAD_NODE_USED(&pool->all_nodes[i])) {
-			return &pool->all_nodes[i];
-		}
-	}
+    for (i = 1; i < pool->node_num; i++) {
+        if (pool->all_nodes[i].tid.raw == tid.raw &&
+            IS_THREAD_NODE_USED(&pool->all_nodes[i])) {
+            return &pool->all_nodes[i];
+        }
+    }
 
-	return NULL;
+    return NULL;
 }
 
 __USER_TEXT
 static void release_thread(struct thread_pool *pool, L4_ThreadId_t tid)
 {
-	L4_Word_t idx;
-
-	idx = find_thread_index(pool, tid);
+    L4_Word_t idx;
 
-	if (idx >= pool->node_num) {
-		printf("tid %p not found.\n", tid);
-		return;
-	}
+    idx = find_thread_index(pool, tid);
 
-	free_thread_node(&pool->all_nodes[idx]);
-	L4_ThreadControl(tid, L4_nilthread, L4_nilthread,
-	                 L4_nilthread, (void *) - 1);
+    if (idx >= pool->node_num) {
+        printf("tid %p not found.\n", tid);
+        return;
+    }
 
+    free_thread_node(&pool->all_nodes[idx]);
+    L4_ThreadControl(tid, L4_nilthread, L4_nilthread, L4_nilthread,
+                     (void *) -1);
 }
 
 __USER_TEXT
-void thread_container(kip_t *kip_ptr, utcb_t *utcb_ptr,
-                      L4_Word_t entry, L4_Word_t entry_arg)
+void thread_container(kip_t *kip_ptr,
+                      utcb_t *utcb_ptr,
+                      L4_Word_t entry,
+                      L4_Word_t entry_arg)
 {
-	L4_Msg_t msg;
-	((thr_handler_t *)entry)((void *)entry_arg);
-
-	L4_MsgClear(&msg);
-	L4_Set_MsgLabel(&msg, PAGER_REQUEST_LABEL);
-	L4_MsgAppendWord(&msg, THREAD_FREE);
-	L4_MsgLoad(&msg);
-	L4_Call(L4_Pager());
+    L4_Msg_t msg;
+    ((thr_handler_t *) entry)((void *) entry_arg);
+
+    L4_MsgClear(&msg);
+    L4_Set_MsgLabel(&msg, PAGER_REQUEST_LABEL);
+    L4_MsgAppendWord(&msg, THREAD_FREE);
+    L4_MsgLoad(&msg);
+    L4_Call(L4_Pager());
 }
 
 __USER_TEXT
 static void start_thread(L4_ThreadId_t t,
-                         L4_Word_t entry, L4_Word_t entry_arg,
-                         L4_Word_t sp, L4_Word_t stack_size)
+                         L4_Word_t entry,
+                         L4_Word_t entry_arg,
+                         L4_Word_t sp,
+                         L4_Word_t stack_size)
 {
-	L4_Msg_t msg;
+    L4_Msg_t msg;
 
-	L4_MsgClear(&msg);
-	L4_MsgAppendWord(&msg, (L4_Word_t)thread_container);
-	L4_MsgAppendWord(&msg, sp);
-	L4_MsgAppendWord(&msg, stack_size);
-	L4_MsgAppendWord(&msg, entry);
-	L4_MsgAppendWord(&msg, entry_arg);
-	L4_MsgLoad(&msg);
+    L4_MsgClear(&msg);
+    L4_MsgAppendWord(&msg, (L4_Word_t) thread_container);
+    L4_MsgAppendWord(&msg, sp);
+    L4_MsgAppendWord(&msg, stack_size);
+    L4_MsgAppendWord(&msg, entry);
+    L4_MsgAppendWord(&msg, entry_arg);
+    L4_MsgLoad(&msg);
 
-	L4_Send(t);
+    L4_Send(t);
 }
 
 __USER_TEXT
 static L4_ThreadId_t __thread_create(struct thread_pool *pool)
 {
-	L4_ThreadId_t child, myself;
-	L4_Word_t thr_idx;
-	L4_Word_t free_mem;
-	struct thread_node *node;
-
-	thr_idx = fetch_free_thread_index(pool);
-	if (thr_idx == 0) {
-		printf("No free res for new thread\n");
-		child.raw = 0;
-		return child;
-	}
-
-	child.raw = (pool->pager_tid).raw + (thr_idx << 14);
-	node = &pool->all_nodes[thr_idx];
-	node->tid = child;
-	use_thread_node(node);
-
-	myself = L4_MyGlobalId();
-	free_mem = (L4_Word_t)THREAD_NODE_BASE(node);
-
-	/* Create thread with shared address space (spaceid=myself).
-	 * Since spaceid != dest, the kernel's thread_space() will share
-	 * the pager's address space with the child. All fpages in the
-	 * pager's AS (including RES_FPAGE for stack/UTCB, UTEXT, UDATA,
-	 * UBSS) are automatically accessible to the child.
-	 *
-	 * Note: The kernel maps the UTCB via map_area() during ThreadControl.
-	 * The stack region is part of RES_FPAGE which is already in the
-	 * pager's AS, so no explicit mapping is needed here.
-	 */
-	L4_ThreadControl(child, myself, L4_nilthread, myself, (void *)free_mem);
-
-	return child;
+    L4_ThreadId_t child, myself;
+    L4_Word_t thr_idx;
+    L4_Word_t free_mem;
+    struct thread_node *node;
+
+    thr_idx = fetch_free_thread_index(pool);
+    if (thr_idx == 0) {
+        printf("No free res for new thread\n");
+        child.raw = 0;
+        return child;
+    }
+
+    child.raw = (pool->pager_tid).raw + (thr_idx << 14);
+    node = &pool->all_nodes[thr_idx];
+    node->tid = child;
+    use_thread_node(node);
+
+    myself = L4_MyGlobalId();
+    free_mem = (L4_Word_t) THREAD_NODE_BASE(node);
+
+    /* Create thread with shared address space (spaceid=myself).
+     * Since spaceid != dest, the kernel's thread_space() will share
+     * the pager's address space with the child. All fpages in the
+     * pager's AS (including RES_FPAGE for stack/UTCB, UTEXT, UDATA,
+     * UBSS) are automatically accessible to the child.
+     *
+     * Note: The kernel maps the UTCB via map_area() during ThreadControl.
+     * The stack region is part of RES_FPAGE which is already in the
+     * pager's AS, so no explicit mapping is needed here.
+     */
+    L4_ThreadControl(child, myself, L4_nilthread, myself, (void *) free_mem);
+
+    return child;
 }
 
 __USER_TEXT
-static L4_Word_t __thread_start(struct thread_pool *pool, L4_ThreadId_t tid,
+static L4_Word_t __thread_start(struct thread_pool *pool,
+                                L4_ThreadId_t tid,
                                 L4_Word_t entry,
                                 L4_Word_t entry_arg)
 {
-	struct thread_node *node;
-	L4_Word_t stack;
+    struct thread_node *node;
+    L4_Word_t stack;
 
-	node = find_thread_node(pool, tid);
+    node = find_thread_node(pool, tid);
 
-	if (!node) {
-		printf("__thread_start: node not found for %p\n", tid.raw);
-		return (L4_Word_t) - 1;
-	}
+    if (!node) {
+        printf("__thread_start: node not found for %p\n", tid.raw);
+        return (L4_Word_t) -1;
+    }
 
-	stack = (L4_Word_t)THREAD_NODE_BASE(node) + UTCB_SIZE + STACK_SIZE;
-	start_thread(tid, entry, entry_arg, stack, STACK_SIZE);
+    stack = (L4_Word_t) THREAD_NODE_BASE(node) + UTCB_SIZE + STACK_SIZE;
+    start_thread(tid, entry, entry_arg, stack, STACK_SIZE);
 
-	return 0;
+    return 0;
 }
 
 __USER_TEXT
 L4_ThreadId_t pager_create_thread(void)
 {
-	L4_ThreadId_t tid;
-	L4_Msg_t msg;
-	L4_MsgTag_t tag;
-	L4_ThreadId_t pager_tid = L4_Pager();
+    L4_ThreadId_t tid;
+    L4_Msg_t msg;
+    L4_MsgTag_t tag;
+    L4_ThreadId_t pager_tid = L4_Pager();
 
-	printf("pager_create: me=%p pager=%p\n",
-	       L4_Myself().raw, pager_tid.raw);
+    printf("pager_create: me=%p pager=%p\n", L4_Myself().raw, pager_tid.raw);
 
-	L4_MsgClear(&msg);
-	L4_Set_Label(&msg.tag, PAGER_REQUEST_LABEL);
-	L4_MsgAppendWord(&msg, THREAD_CREATE);
+    L4_MsgClear(&msg);
+    L4_Set_Label(&msg.tag, PAGER_REQUEST_LABEL);
+    L4_MsgAppendWord(&msg, THREAD_CREATE);
 
-	L4_MsgLoad(&msg);
-	tag = L4_Call(pager_tid);
+    L4_MsgLoad(&msg);
+    tag = L4_Call(pager_tid);
 
-	if (L4_Label(tag) == PAGER_REPLY_LABEL)
-		L4_StoreMR(1, &tid.raw);
-	else
-		tid.raw = 0;
+    if (L4_Label(tag) == PAGER_REPLY_LABEL)
+        L4_StoreMR(1, &tid.raw);
+    else
+        tid.raw = 0;
 
-	return tid;
+    return tid;
 }
 
 __USER_TEXT
-L4_Word_t pager_start_thread(L4_ThreadId_t tid, void * (*thr_routine)(void *),
+L4_Word_t pager_start_thread(L4_ThreadId_t tid,
+                             void *(*thr_routine)(void *),
                              void *arg)
 {
-	L4_Msg_t msg;
-	L4_MsgTag_t tag;
-	L4_Word_t ret;
+    L4_Msg_t msg;
+    L4_MsgTag_t tag;
+    L4_Word_t ret;
 
-	printf("pager_start: tid=%p\n", tid.raw);
+    printf("pager_start: tid=%p\n", tid.raw);
 
-	L4_MsgClear(&msg);
-	L4_Set_Label(&msg.tag, PAGER_REQUEST_LABEL);
-	L4_MsgAppendWord(&msg, THREAD_START);
-	L4_MsgAppendWord(&msg, (L4_Word_t)tid.raw);
-	L4_MsgAppendWord(&msg, (L4_Word_t)thr_routine);
-	/* TODO: Ignore arg now */
+    L4_MsgClear(&msg);
+    L4_Set_Label(&msg.tag, PAGER_REQUEST_LABEL);
+    L4_MsgAppendWord(&msg, THREAD_START);
+    L4_MsgAppendWord(&msg, (L4_Word_t) tid.raw);
+    L4_MsgAppendWord(&msg, (L4_Word_t) thr_routine);
+    /* TODO: Ignore arg now */
 
-	L4_MsgLoad(&msg);
-	tag = L4_Call(L4_Pager());
+    L4_MsgLoad(&msg);
+    tag = L4_Call(L4_Pager());
 
-	if (L4_Label(tag) == PAGER_REPLY_LABEL) {
-		L4_StoreMR(1, &ret);
-	} else {
-		ret = -1;
-	}
+    if (L4_Label(tag) == PAGER_REPLY_LABEL) {
+        L4_StoreMR(1, &ret);
+    } else {
+        ret = -1;
+    }
 
-	return ret;
+    return ret;
 }
 
 __USER_TEXT
-void pager_thread(user_struct *user,
-                  void * (*entry_main)(void *))
+void pager_thread(user_struct *user, void *(*entry_main)(void *) )
 {
-	L4_Word_t fpage_num;
-	L4_ThreadId_t main_tid;
-	struct thread_pool *pool;
-
-	printf("pager: starting\n");
-
-	fpage_num = user_fpage_number(user->fpages);
-
-	if (fpage_num < 2) {
-		/* TODO: fpage 0: stack + tcb, fpage 1: heap */
-		printf("pager: There is no enough fpages\n");
-		return;
-	}
-
-	pool = init_thread_pool(user->fpages[RES_FPAGE].base,
-	                        user->fpages[RES_FPAGE].size,
-	                        user->fpages[HEAP_FPAGE].base,
-	                        user->fpages[HEAP_FPAGE].size);
-
-	/* Create main entry thread */
-	main_tid = __thread_create(pool);
-	__thread_start(pool, main_tid, (L4_Word_t)entry_main, 0);
-
-	/* Handle ipc request */
-	while (1) {
-		L4_Msg_t msg;
-		L4_ThreadId_t request_tid;
-		L4_MsgTag_t tag;
-		L4_Word_t req;
-
-		tag = L4_Wait(&request_tid);
-		if (!L4_IpcSucceeded(tag)) {			/* TODO: error message */
-			printf("Invalid tag\n");
-			continue;
-		}
-
-		if (L4_Label(tag) != PAGER_REQUEST_LABEL) {
-			printf("Invalid label = %p\n", L4_Label(tag));
-			continue;
-		}
-
-		L4_MsgStore(tag, &msg);
-		req = L4_MsgWord(&msg, 0);
-
-		switch (req) {
-		case THREAD_CREATE: {
-				L4_ThreadId_t tid;
-				tid = __thread_create(pool);
-
-				/* return tid back */
-				L4_MsgClear(&msg);
-				L4_Set_Label(&msg.tag, PAGER_REPLY_LABEL);
-				L4_MsgAppendWord(&msg, tid.raw);
-				L4_MsgLoad(&msg);
-				L4_Send(request_tid);
-			}
-			break;
-		case THREAD_START: {
-				L4_Word_t entry;
-				L4_ThreadId_t tid;
-				L4_Word_t ret;
-
-				tid.raw = L4_MsgWord(&msg, 1);
-				entry = L4_MsgWord(&msg, 2);
-				/* TODO : ignore entry argument now */
-
-				ret = __thread_start(pool, tid, entry, 0);
-
-				L4_MsgClear(&msg);
-				L4_Set_Label(&msg.tag, PAGER_REPLY_LABEL);
-				L4_MsgAppendWord(&msg, ret);
-				L4_MsgLoad(&msg);
-				L4_Send(request_tid);
-			}
-			break;
-		case THREAD_FREE:
-			release_thread(pool, request_tid);
-			break;
-		case THREAD_WAIT:
-			break;
-		}
-	}
+    L4_Word_t fpage_num;
+    L4_ThreadId_t main_tid;
+    struct thread_pool *pool;
+
+    printf("pager: starting\n");
+
+    fpage_num = user_fpage_number(user->fpages);
+
+    if (fpage_num < 2) {
+        /* TODO: fpage 0: stack + tcb, fpage 1: heap */
+        printf("pager: There is no enough fpages\n");
+        return;
+    }
+
+    pool = init_thread_pool(
+        user->fpages[RES_FPAGE].base, user->fpages[RES_FPAGE].size,
+        user->fpages[HEAP_FPAGE].base, user->fpages[HEAP_FPAGE].size);
+
+    /* Create main entry thread */
+    main_tid = __thread_create(pool);
+    __thread_start(pool, main_tid, (L4_Word_t) entry_main, 0);
+
+    /* Handle ipc request */
+    while (1) {
+        L4_Msg_t msg;
+        L4_ThreadId_t request_tid;
+        L4_MsgTag_t tag;
+        L4_Word_t req;
+
+        tag = L4_Wait(&request_tid);
+        if (!L4_IpcSucceeded(tag)) { /* TODO: error message */
+            printf("Invalid tag\n");
+            continue;
+        }
+
+        if (L4_Label(tag) != PAGER_REQUEST_LABEL) {
+            printf("Invalid label = %p\n", L4_Label(tag));
+            continue;
+        }
+
+        L4_MsgStore(tag, &msg);
+        req = L4_MsgWord(&msg, 0);
+
+        switch (req) {
+        case THREAD_CREATE: {
+            L4_ThreadId_t tid;
+            tid = __thread_create(pool);
+
+            /* return tid back */
+            L4_MsgClear(&msg);
+            L4_Set_Label(&msg.tag, PAGER_REPLY_LABEL);
+            L4_MsgAppendWord(&msg, tid.raw);
+            L4_MsgLoad(&msg);
+            L4_Send(request_tid);
+        } break;
+        case THREAD_START: {
+            L4_Word_t entry;
+            L4_ThreadId_t tid;
+            L4_Word_t ret;
+
+            tid.raw = L4_MsgWord(&msg, 1);
+            entry = L4_MsgWord(&msg, 2);
+            /* TODO : ignore entry argument now */
+
+            ret = __thread_start(pool, tid, entry, 0);
+
+            L4_MsgClear(&msg);
+            L4_Set_Label(&msg.tag, PAGER_REPLY_LABEL);
+            L4_MsgAppendWord(&msg, ret);
+            L4_MsgLoad(&msg);
+            L4_Send(request_tid);
+        } break;
+        case THREAD_FREE:
+            release_thread(pool, request_tid);
+            break;
+        case THREAD_WAIT:
+            break;
+        }
+    }
 }
diff --git a/user/lib/l4/platform/syscalls.c b/user/lib/l4/platform/syscalls.c
index eda519a0..d9ec14a7 100644
--- a/user/lib/l4/platform/syscalls.c
+++ b/user/lib/l4/platform/syscalls.c
@@ -5,8 +5,8 @@
 
 /* ARM Cortex-M syscall implementations */
 
-#include <platform/link.h>
 #include <l4/types.h>
+#include <platform/link.h>
 #include <syscall.h>
 #include __L4_INC_ARCH(syscalls.h)
 
@@ -15,7 +15,7 @@ void *L4_KernelInterface(L4_Word_t *ApiVersion,
                          L4_Word_t *ApiFlags,
                          L4_Word_t *KernelId)
 {
-	return &kip_start;
+    return &kip_start;
 }
 
 __USER_TEXT
@@ -33,9 +33,9 @@ L4_ThreadId_t L4_ExchangeRegisters(L4_ThreadId_t dest,
                                    L4_Word_t *old_UserDefhandle,
                                    L4_ThreadId_t *old_pager)
 {
-	L4_ThreadId_t	result = {0};
-	/* FIXME: unimplemented */
-	return result;
+    L4_ThreadId_t result = {0};
+    /* FIXME: unimplemented */
+    return result;
 }
 
 __USER_TEXT
@@ -45,34 +45,31 @@ L4_Word_t L4_ThreadControl(L4_ThreadId_t dest,
                            L4_ThreadId_t Pager,
                            void *UtcbLocation)
 {
-	register L4_Word_t r0 __asm__("r0") = dest.raw;
-	register L4_Word_t r1 __asm__("r1") = SpaceSpecifier.raw;
-	register L4_Word_t r2 __asm__("r2") = Scheduler.raw;
-	register L4_Word_t r3 __asm__("r3") = Pager.raw;
-	register L4_Word_t r4 __asm__("r4") = (L4_Word_t)UtcbLocation;
-
-	__asm__ __volatile__(
-	    "svc %[syscall_num]\n"
-	    : "+r"(r0)
-	    : "r"(r1), "r"(r2), "r"(r3), "r"(r4),
-	      [syscall_num] "i"(SYS_THREAD_CONTROL)
-	    : "memory");
-
-	return r0;
+    register L4_Word_t r0 __asm__("r0") = dest.raw;
+    register L4_Word_t r1 __asm__("r1") = SpaceSpecifier.raw;
+    register L4_Word_t r2 __asm__("r2") = Scheduler.raw;
+    register L4_Word_t r3 __asm__("r3") = Pager.raw;
+    register L4_Word_t r4 __asm__("r4") = (L4_Word_t) UtcbLocation;
+
+    __asm__ __volatile__("svc %[syscall_num]\n"
+                         : "+r"(r0)
+                         : "r"(r1), "r"(r2), "r"(r3),
+                           "r"(r4), [syscall_num] "i"(SYS_THREAD_CONTROL)
+                         : "memory");
+
+    return r0;
 }
 
 __USER_TEXT
 L4_Clock_t L4_SystemClock(void)
 {
-	L4_Clock_t result = {0};
-	/* FIXME: unimplemented */
-	return result;
+    L4_Clock_t result = {0};
+    /* FIXME: unimplemented */
+    return result;
 }
 
 __USER_TEXT
-void L4_ThreadSwitch(L4_ThreadId_t dest)
-{
-}
+void L4_ThreadSwitch(L4_ThreadId_t dest) {}
 
 __USER_TEXT
 L4_Word_t L4_Schedule(L4_ThreadId_t dest,
@@ -82,8 +79,8 @@ L4_Word_t L4_Schedule(L4_ThreadId_t dest,
                       L4_Word_t PreemptionControl,
                       L4_Word_t *old_TimeControl)
 {
-	L4_Word_t result = 0;
-	return result;
+    L4_Word_t result = 0;
+    return result;
 }
 
 __USER_TEXT
@@ -92,24 +89,22 @@ L4_MsgTag_t L4_Ipc(L4_ThreadId_t to,
                    L4_Word_t Timeouts,
                    L4_ThreadId_t *from)
 {
-	L4_MsgTag_t result;
-	register L4_Word_t r0 __asm__("r0") = to.raw;
-	register L4_Word_t r1 __asm__("r1") = FromSpecifier.raw;
-	register L4_Word_t r2 __asm__("r2") = Timeouts;
+    L4_MsgTag_t result;
+    register L4_Word_t r0 __asm__("r0") = to.raw;
+    register L4_Word_t r1 __asm__("r1") = FromSpecifier.raw;
+    register L4_Word_t r2 __asm__("r2") = Timeouts;
 
-	__asm__ __volatile__(
-	    "svc %[syscall_num]\n"
-	    : "+r"(r0)
-	    : "r"(r1), "r"(r2),
-	      [syscall_num] "i"(SYS_IPC)
-	    : "memory");
+    __asm__ __volatile__("svc %[syscall_num]\n"
+                         : "+r"(r0)
+                         : "r"(r1), "r"(r2), [syscall_num] "i"(SYS_IPC)
+                         : "memory");
 
-	result.raw = __L4_MR0;
+    result.raw = __L4_MR0;
 
-	if (from)
-		from->raw = r0;
+    if (from)
+        from->raw = r0;
 
-	return result;
+    return result;
 }
 
 
@@ -119,13 +114,11 @@ L4_MsgTag_t L4_Lipc(L4_ThreadId_t to,
                     L4_Word_t Timeouts,
                     L4_ThreadId_t *from)
 {
-	return L4_Ipc(to, FromSpecifier, Timeouts, from);
+    return L4_Ipc(to, FromSpecifier, Timeouts, from);
 }
 
 __USER_TEXT
-void L4_Unmap(L4_Word_t control)
-{
-}
+void L4_Unmap(L4_Word_t control) {}
 
 __USER_TEXT
 L4_Word_t L4_SpaceControl(L4_ThreadId_t SpaceSpecifier,
@@ -135,8 +128,8 @@ L4_Word_t L4_SpaceControl(L4_ThreadId_t SpaceSpecifier,
                           L4_ThreadId_t redirector,
                           L4_Word_t *old_control)
 {
-	L4_Word_t result = 0;
-	return result;
+    L4_Word_t result = 0;
+    return result;
 }
 
 __USER_TEXT
@@ -145,14 +138,13 @@ L4_Word_t L4_ProcessorControl(L4_Word_t ProcessorNo,
                               L4_Word_t ExternalFrequency,
                               L4_Word_t voltage)
 {
-	L4_Word_t result = 0;
-	return result;
+    L4_Word_t result = 0;
+    return result;
 }
 
 __USER_TEXT
-L4_Word_t L4_MemoryControl(L4_Word_t control,
-                           const L4_Word_t *attributes)
+L4_Word_t L4_MemoryControl(L4_Word_t control, const L4_Word_t *attributes)
 {
-	L4_Word_t result = 0;
-	return result;
+    L4_Word_t result = 0;
+    return result;
 }
diff --git a/user/lib/libposix/fork.c b/user/lib/libposix/fork.c
index 232d9e6c..7f074a7b 100644
--- a/user/lib/libposix/fork.c
+++ b/user/lib/libposix/fork.c
@@ -4,6 +4,6 @@
 
 int __USER_TEXT fork()
 {
-	UNIMPLEMENTED();
-	return 0;
+    UNIMPLEMENTED();
+    return 0;
 }
diff --git a/user/lib/libposix/pthread.c b/user/lib/libposix/pthread.c
index 438aaeb2..6ad96ef6 100644
--- a/user/lib/libposix/pthread.c
+++ b/user/lib/libposix/pthread.c
@@ -3,86 +3,88 @@
  * found in the LICENSE file.
  */
 
-#include <libposix/pthread.h>
 #include <l4/ipc.h>
-#include <l4/utcb.h>
 #include <l4/pager.h>
+#include <l4/utcb.h>
 #include <l4io.h>
+#include <libposix/pthread.h>
 #include <platform/link.h>
 
 int __USER_TEXT pthread_create(pthread_t *restrict thread,
                                const pthread_attr_t *restrict attr,
-                               void *(*start_routine)(void*), void *restrict arg)
+                               void *(*start_routine)(void *),
+                               void *restrict arg)
 {
-	L4_ThreadId_t tid = pager_create_thread();
+    L4_ThreadId_t tid = pager_create_thread();
 
-	pager_start_thread(tid, start_routine, NULL);
+    pager_start_thread(tid, start_routine, NULL);
 
-	return *(int *) &tid;
+    return *(int *) &tid;
 }
 
 __USER_TEXT int pthread_detach(pthread_t thread)
 {
-	return 0;	
+    return 0;
 }
 
-__USER_TEXT void pthread_exit(void *value_ptr) 
+__USER_TEXT void pthread_exit(void *value_ptr)
 {
-	return;
+    return;
 }
 
 __USER_TEXT int pthread_join(pthread_t thread, void **value_ptr)
 {
-	return 0;
+    return 0;
 }
 
 __USER_TEXT int pthread_mutex_init(pthread_mutex_t *mutex,
-		                   const pthread_mutexattr_t *restrict attr)
+                                   const pthread_mutexattr_t *restrict attr)
 {
-	return 0;
+    return 0;
 }
 
 __USER_TEXT int pthread_mutex_destroy(pthread_mutex_t *mutex)
 {
-	return 0;
+    return 0;
 }
 
 __USER_TEXT int pthread_mutex_lock(pthread_mutex_t *mutex)
 {
-	/* Busy trying */
-	while (pthread_mutex_trylock(mutex));
+    /* Busy trying */
+    while (pthread_mutex_trylock(mutex))
+        ;
 
-	return 0;
+    return 0;
 }
 
 __USER_TEXT int pthread_mutex_trylock(pthread_mutex_t *mutex)
 {
-	register int result = 1;
-
-	__asm__ __volatile__(
-	    "mov r1, #1\n"
-	    "mov r2, %[mutex]\n"
-	    "ldrex r0, [r2]\n"	/* Load value [r2] */
-	    "cmp r0, #0\n"	/* Checking is word set to 1 */
-
-	    "itt eq\n"
-	    "strexeq r0, r1, [r2]\n"
-	    "moveq %[result], r0\n"
-	    : [result] "=r"(result)
-	    : [mutex] "r"(mutex)
-	    : "r0", "r1", "r2");
-
-	return result;
+    register int result = 1;
+
+    __asm__ __volatile__(
+        "mov r1, #1\n"
+        "mov r2, %[mutex]\n"
+        "ldrex r0, [r2]\n" /* Load value [r2] */
+        "cmp r0, #0\n"     /* Checking is word set to 1 */
+
+        "itt eq\n"
+        "strexeq r0, r1, [r2]\n"
+        "moveq %[result], r0\n"
+        : [result] "=r"(result)
+        : [mutex] "r"(mutex)
+        : "r0", "r1", "r2");
+
+    return result;
 }
 
 __USER_TEXT int pthread_mutex_unlock(pthread_mutex_t *mutex)
 {
-	*mutex = 0;
-	return 0;
+    *mutex = 0;
+    return 0;
 }
 
 __USER_TEXT int pthread_mutex_timedlock(pthread_mutex_t *restrict mutex,
                                         const struct timespec *restrict abstime)
 {
-	return 0;
+    return 0;
 }
diff --git a/user/root_thread.c b/user/root_thread.c
index 851c71b8..3572d3b1 100644
--- a/user/root_thread.c
+++ b/user/root_thread.c
@@ -3,10 +3,10 @@
  * found in the LICENSE file.
  */
 
-#include <l4/thread.h>
+#include <l4/ipc.h>
 #include <l4/kip.h>
+#include <l4/thread.h>
 #include <l4/utcb.h>
-#include <l4/ipc.h>
 #include <l4io.h>
 #include <types.h>
 #include <user_runtime.h>
@@ -16,64 +16,63 @@ extern user_struct user_runtime_end[];
 
 int __USER_TEXT L4_Map(L4_ThreadId_t where, memptr_t base, size_t size)
 {
-	L4_Msg_t msg;
-	L4_Word_t page[2] = {
-		(base & 0xFFFFFFC0) | 0xA,
-		size & 0xFFFFFFC0
-	};
+    L4_Msg_t msg;
+    L4_Word_t page[2] = {(base & 0xFFFFFFC0) | 0xA, size & 0xFFFFFFC0};
 
-	L4_MsgPut(&msg, 0, 0, NULL, 2, page);
-	L4_MsgLoad(&msg);
+    L4_MsgPut(&msg, 0, 0, NULL, 2, page);
+    L4_MsgLoad(&msg);
 
-	L4_Send(where);
-	return 0;
+    L4_Send(where);
+    return 0;
 }
 
 memptr_t __USER_TEXT get_free_base(kip_t *kip_ptr)
 {
-	kip_mem_desc_t *desc = ((void *) kip_ptr) +
-	                       kip_ptr->memory_info.s.memory_desc_ptr;
-	int n = kip_ptr->memory_info.s.n;
-	int i = 0;
+    kip_mem_desc_t *desc =
+        ((void *) kip_ptr) + kip_ptr->memory_info.s.memory_desc_ptr;
+    int n = kip_ptr->memory_info.s.n;
+    int i = 0;
 
-	for (i = 0; i < n; ++i) {
-		if ((desc[i].size & 0x3F) == 4)
-			return desc[i].base & 0xFFFFFFC0;
-	}
+    for (i = 0; i < n; ++i) {
+        if ((desc[i].size & 0x3F) == 4)
+            return desc[i].base & 0xFFFFFFC0;
+    }
 
-	return 0;
+    return 0;
 }
 
 void __USER_TEXT map_user_sections(kip_t *kip_ptr, L4_ThreadId_t tid)
 {
-	kip_mem_desc_t *desc = ((void *) kip_ptr) +
-	                       kip_ptr->memory_info.s.memory_desc_ptr;
-	int n = kip_ptr->memory_info.s.n;
-	int i = 0;
-
-	for (i = 0; i < n; ++i) {
-		uint32_t tag = desc[i].size & 0x3F;
-		if (tag == 2 || tag == 3) {
-			L4_Map(tid, desc[i].base, desc[i].size);
-		}
-	}
+    kip_mem_desc_t *desc =
+        ((void *) kip_ptr) + kip_ptr->memory_info.s.memory_desc_ptr;
+    int n = kip_ptr->memory_info.s.n;
+    int i = 0;
+
+    for (i = 0; i < n; ++i) {
+        uint32_t tag = desc[i].size & 0x3F;
+        if (tag == 2 || tag == 3) {
+            L4_Map(tid, desc[i].base, desc[i].size);
+        }
+    }
 }
 
-static void __USER_TEXT start_thread(L4_ThreadId_t t, L4_Word_t ip,
-                                     L4_Word_t sp, L4_Word_t stack_size)
+static void __USER_TEXT start_thread(L4_ThreadId_t t,
+                                     L4_Word_t ip,
+                                     L4_Word_t sp,
+                                     L4_Word_t stack_size)
 {
-	L4_Msg_t msg;
+    L4_Msg_t msg;
 
-	L4_MsgClear(&msg);
-	L4_MsgAppendWord(&msg, ip);
-	L4_MsgAppendWord(&msg, sp);
-	L4_MsgAppendWord(&msg, stack_size);
-	L4_MsgAppendWord(&msg, 0);
-	L4_MsgAppendWord(&msg, 0);
+    L4_MsgClear(&msg);
+    L4_MsgAppendWord(&msg, ip);
+    L4_MsgAppendWord(&msg, sp);
+    L4_MsgAppendWord(&msg, stack_size);
+    L4_MsgAppendWord(&msg, 0);
+    L4_MsgAppendWord(&msg, 0);
 
-	L4_MsgLoad(&msg);
+    L4_MsgLoad(&msg);
 
-	L4_Send(t);
+    L4_Send(t);
 }
 
 #define STACK_SIZE 0x200
@@ -85,84 +84,86 @@ static void __USER_TEXT start_thread(L4_ThreadId_t t, L4_Word_t ip,
 #define FPAGE_ALIGN_MASK (~(FPAGE_ALIGN_SIZE - 1))
 static inline L4_Word_t fpage_align_safe(L4_Word_t addr)
 {
-	L4_Word_t aligned = (addr + FPAGE_ALIGN_SIZE - 1) & FPAGE_ALIGN_MASK;
-	/* Check for overflow: if aligned < addr, we wrapped around */
-	if (aligned < addr)
-		return FPAGE_ALIGN_MASK;  /* Return max aligned address */
-	return aligned;
+    L4_Word_t aligned = (addr + FPAGE_ALIGN_SIZE - 1) & FPAGE_ALIGN_MASK;
+    /* Check for overflow: if aligned < addr, we wrapped around */
+    if (aligned < addr)
+        return FPAGE_ALIGN_MASK; /* Return max aligned address */
+    return aligned;
 }
-#define FPAGE_ALIGN(addr) fpage_align_safe((L4_Word_t)(addr))
+#define FPAGE_ALIGN(addr) fpage_align_safe((L4_Word_t) (addr))
 
 void __USER_TEXT __root_thread(kip_t *kip_ptr, utcb_t *utcb_ptr)
 {
-	L4_ThreadId_t myself = {.raw = utcb_ptr->t_globalid};
-	char *free_mem = (char *) get_free_base(kip_ptr);
-
-	/* Validate free_mem base - 0 means no free memory found */
-	if (!free_mem) {
-		/* No free memory available, halt */
-		while (1)
-			L4_Sleep(L4_Never);
-	}
-
-	for (user_struct *ptr = user_runtime_start; ptr != user_runtime_end; ++ptr) {
-		L4_ThreadId_t tid;
-		L4_Word_t stack;
-		user_fpage_t *fpage = ptr->fpages;
-
-		tid = L4_GlobalId(ptr->tid + kip_ptr->thread_info.s.user_base, 2);
-
-		/* Align UTCB base BEFORE ThreadControl to prevent kernel's
-		 * mempool_align_base() from rounding down into previous allocation
-		 */
-		free_mem = (char *) FPAGE_ALIGN(free_mem);
-
-		/* create thread */
-		L4_ThreadControl(tid, tid, L4_nilthread, myself, free_mem);
-		free_mem += UTCB_SIZE;
-
-		/* map user_text, user_data and user_bss */
-		map_user_sections(kip_ptr, tid);
-
-		/* map thread stack - align first to prevent overlap */
-		free_mem = (char *) FPAGE_ALIGN(free_mem);
-		L4_Map(tid, (L4_Word_t)free_mem, STACK_SIZE);
-		free_mem += STACK_SIZE;
-		stack = (L4_Word_t)free_mem;
-
-		/* map fpages */
-		while (fpage->base || fpage->size) {
-			if (fpage->base) {
-				L4_Map(tid, fpage->base, fpage->size);
-			} else {
-				/* Align dynamic allocations to the fpage's own size.
-				 * This ensures the fpage can be a single MPU region.
-				 * fpage->size MUST be a non-zero power of 2.
-				 */
-				if (!fpage->size || (fpage->size & (fpage->size - 1))) {
-					printf("ERROR: invalid fpage size %p\n",
-					       (void *)fpage->size);
-					fpage++;
-					continue;
-				}
-				L4_Word_t align_mask = ~(fpage->size - 1);
-				free_mem = (char *)(((L4_Word_t)free_mem + fpage->size - 1) & align_mask);
-				L4_Map(tid, (L4_Word_t)free_mem, fpage->size);
-				fpage->base = (L4_Word_t)free_mem;
-				free_mem += fpage->size;
-			}
-
-			fpage++;
-		}
-
-		/* start thread */
-		start_thread(tid, (L4_Word_t)ptr->entry, stack, STACK_SIZE);
-	}
-
-	printf("root_thread: all user threads started\n");
-
-	while (1)
-		L4_Sleep(L4_Never);
+    L4_ThreadId_t myself = {.raw = utcb_ptr->t_globalid};
+    char *free_mem = (char *) get_free_base(kip_ptr);
+
+    /* Validate free_mem base - 0 means no free memory found */
+    if (!free_mem) {
+        /* No free memory available, halt */
+        while (1)
+            L4_Sleep(L4_Never);
+    }
+
+    for (user_struct *ptr = user_runtime_start; ptr != user_runtime_end;
+         ++ptr) {
+        L4_ThreadId_t tid;
+        L4_Word_t stack;
+        user_fpage_t *fpage = ptr->fpages;
+
+        tid = L4_GlobalId(ptr->tid + kip_ptr->thread_info.s.user_base, 2);
+
+        /* Align UTCB base BEFORE ThreadControl to prevent kernel's
+         * mempool_align_base() from rounding down into previous allocation
+         */
+        free_mem = (char *) FPAGE_ALIGN(free_mem);
+
+        /* create thread */
+        L4_ThreadControl(tid, tid, L4_nilthread, myself, free_mem);
+        free_mem += UTCB_SIZE;
+
+        /* map user_text, user_data and user_bss */
+        map_user_sections(kip_ptr, tid);
+
+        /* map thread stack - align first to prevent overlap */
+        free_mem = (char *) FPAGE_ALIGN(free_mem);
+        L4_Map(tid, (L4_Word_t) free_mem, STACK_SIZE);
+        free_mem += STACK_SIZE;
+        stack = (L4_Word_t) free_mem;
+
+        /* map fpages */
+        while (fpage->base || fpage->size) {
+            if (fpage->base) {
+                L4_Map(tid, fpage->base, fpage->size);
+            } else {
+                /* Align dynamic allocations to the fpage's own size.
+                 * This ensures the fpage can be a single MPU region.
+                 * fpage->size MUST be a non-zero power of 2.
+                 */
+                if (!fpage->size || (fpage->size & (fpage->size - 1))) {
+                    printf("ERROR: invalid fpage size %p\n",
+                           (void *) fpage->size);
+                    fpage++;
+                    continue;
+                }
+                L4_Word_t align_mask = ~(fpage->size - 1);
+                free_mem = (char *) (((L4_Word_t) free_mem + fpage->size - 1) &
+                                     align_mask);
+                L4_Map(tid, (L4_Word_t) free_mem, fpage->size);
+                fpage->base = (L4_Word_t) free_mem;
+                free_mem += fpage->size;
+            }
+
+            fpage++;
+        }
+
+        /* start thread */
+        start_thread(tid, (L4_Word_t) ptr->entry, stack, STACK_SIZE);
+    }
+
+    printf("root_thread: all user threads started\n");
+
+    while (1)
+        L4_Sleep(L4_Never);
 }
 
 DECLARE_THREAD(root_thread, __root_thread);