diff --git a/esp-hal/README.md b/esp-hal/README.md index a0a568dff6c..44466642767 100644 --- a/esp-hal/README.md +++ b/esp-hal/README.md @@ -120,10 +120,10 @@ For help getting started with this HAL, please refer to [The Rust on ESP Book] a | Driver | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | | ----------------- |:-----:|:--------:|:--------:|:--------:|:--------:|:---------:|:--------:|:--------:|:--------:|:--------:|:---------:| -| Camera interface | ❌ | | | | | | | ❌ | ❌ | ⚒️ | ❌ | +| Camera interface | ❌ | | | | | | | ❌ | ❌ | ⚒️ | ⚒️ | | MIPI-CSI | | | | | | | | ❌ | | | | | MIPI-DSI | | | | | | | | ⚒️ | | | | -| RGB display | ⚒️ | | | | | | | ❌ | ❌ | ⚒️ | ❌ | +| RGB display | ⚒️ | | | | | | | ❌ | ❌ | ⚒️ | ⚒️ | | SPI LCD interface | | | | | | | | | [❌][5374] [^1] | | | ### Signal processing diff --git a/esp-hal/src/dma/engine/mod.rs b/esp-hal/src/dma/engine/mod.rs index a97a35f84d3..9fec2ff0ffc 100644 --- a/esp-hal/src/dma/engine/mod.rs +++ b/esp-hal/src/dma/engine/mod.rs @@ -186,7 +186,7 @@ pub trait DmaChannel: Sized + crate::private::Sealed { type Tx: DmaTxChannel + From; /// Splits the DMA channel into its RX and TX halves. - #[cfg(any(esp32c5, esp32c6, esp32h2, esp32s3))] // TODO relax this to allow splitting on all chips + #[cfg(dma_separate_in_out_interrupts)] // TODO relax this to allow splitting on all chips fn split(self) -> (Self::Rx, Self::Tx) { // This function is exposed safely on chips that have separate IN and OUT // interrupt handlers. diff --git a/esp-hal/src/lcd_cam/cam.rs b/esp-hal/src/lcd_cam/cam.rs index fb975d6e313..87cfb3578ac 100644 --- a/esp-hal/src/lcd_cam/cam.rs +++ b/esp-hal/src/lcd_cam/cam.rs @@ -64,7 +64,15 @@ use crate::{ OutputSignal, interconnect::{PeripheralInput, PeripheralOutput}, }, - lcd_cam::{BitOrder, ByteOrder, CamDmaRxChannel, ClockError, ErasedRxChannel, calculate_clkm}, + lcd_cam::{ + BitOrder, + ByteOrder, + CamDmaRxChannel, + ClockError, + ErasedRxChannel, + calculate_clkm, + ll, + }, pac, peripherals::LCD_CAM, soc::clocks::{ClockTree, LcdCamCamClockConfig, LcdCamInstance}, @@ -240,9 +248,7 @@ impl<'d> Camera<'d> { w.cam_vsync_inv().bit(config.invert_vsync) }); - self.regs() - .cam_rgb_yuv() - .write(|w| w.cam_conv_bypass().clear_bit()); + ll::set_cam_conv_bypass(self.regs()); self.regs() .cam_ctrl() diff --git a/esp-hal/src/lcd_cam/lcd/dpi.rs b/esp-hal/src/lcd_cam/lcd/dpi.rs index d98bb94074a..2e0a09bb736 100644 --- a/esp-hal/src/lcd_cam/lcd/dpi.rs +++ b/esp-hal/src/lcd_cam/lcd/dpi.rs @@ -112,6 +112,7 @@ use crate::{ ErasedTxChannel, LcdDmaTxChannel, lcd::{ClockConfig, ClockMode, DelayMode, Lcd}, + ll, }, pac, time::Rate, @@ -165,10 +166,13 @@ where self.lcd .configure_clocks(&ClockConfig { clock_mode: config.clock_mode, - // Due to https://www.espressif.com/sites/default/files/documentation/esp32-s3_errata_en.pdf - // the LCD_PCLK divider must be at least 2. To make up for this the user - // provided frequency is doubled to match. - frequency: config.frequency * 2, + // ESP32-S3 errata requires LCD_PCLK to divide LCD_CLK by at least 2. + // Double the requested frequency so the extra divider still matches. + frequency: if cfg!(esp32s3) { + config.frequency * 2 + } else { + config.frequency + }, }) .map_err(ConfigError::Clock)?; @@ -176,23 +180,17 @@ where .lcd_user() .modify(|_, w| w.lcd_reset().set_bit()); - self.regs() - .lcd_rgb_yuv() - .write(|w| w.lcd_conv_bypass().clear_bit()); + ll::set_lcd_conv_bypass(self.regs()); self.regs().lcd_user().modify(|_, w| { if config.format.enable_2byte_mode { - w.lcd_8bits_order().bit(false); w.lcd_byte_order() .bit(config.format.byte_order == ByteOrder::Inverted); } else { - w.lcd_8bits_order() - .bit(config.format.byte_order == ByteOrder::Inverted); w.lcd_byte_order().bit(false); } w.lcd_bit_order() .bit(config.format.bit_order == BitOrder::Inverted); - w.lcd_2byte_en().bit(config.format.enable_2byte_mode); // Only valid in Intel8080 mode. w.lcd_cmd().clear_bit(); @@ -201,42 +199,31 @@ where // This needs to be explicitly set for RGB mode. w.lcd_dout().set_bit() }); + ll::set_8bits_order( + self.regs(), + !config.format.enable_2byte_mode && config.format.byte_order == ByteOrder::Inverted, + ); + ll::set_2byte_mode(self.regs(), config.format.enable_2byte_mode); let timing = &config.timing; - self.regs().lcd_ctrl().modify(|_, w| unsafe { - // Enable RGB mode, and input VSYNC, HSYNC, and DE signals. - w.lcd_rgb_mode_en().set_bit(); - - w.lcd_hb_front() - .bits((timing.horizontal_blank_front_porch as u16).saturating_sub(1)); - w.lcd_va_height() - .bits((timing.vertical_active_height as u16).saturating_sub(1)); - w.lcd_vt_height() - .bits((timing.vertical_total_height as u16).saturating_sub(1)) - }); - self.regs().lcd_ctrl1().modify(|_, w| unsafe { - w.lcd_vb_front() - .bits((timing.vertical_blank_front_porch as u8).saturating_sub(1)); - w.lcd_ha_width() - .bits((timing.horizontal_active_width as u16).saturating_sub(1)); - w.lcd_ht_width() - .bits((timing.horizontal_total_width as u16).saturating_sub(1)) - }); - self.regs().lcd_ctrl2().modify(|_, w| unsafe { - w.lcd_vsync_width() - .bits((timing.vsync_width as u8).saturating_sub(1)); - w.lcd_vsync_idle_pol().bit(config.vsync_idle_level.into()); - w.lcd_de_idle_pol().bit(config.de_idle_level.into()); - w.lcd_hs_blank_en().bit(config.hs_blank_en); - w.lcd_hsync_width() - .bits((timing.hsync_width as u8).saturating_sub(1)); - w.lcd_hsync_idle_pol().bit(config.hsync_idle_level.into()); - w.lcd_hsync_position().bits(timing.hsync_position as u8) - }); - + ll::configure_rgb_timing( + self.regs(), + (timing.horizontal_blank_front_porch as u16).saturating_sub(1), + (timing.vertical_active_height as u16).saturating_sub(1), + (timing.vertical_total_height as u16).saturating_sub(1), + (timing.vertical_blank_front_porch as u16).saturating_sub(1), + (timing.horizontal_active_width as u16).saturating_sub(1), + (timing.horizontal_total_width as u16).saturating_sub(1), + (timing.vsync_width as u16).saturating_sub(1), + config.vsync_idle_level.into(), + config.de_idle_level.into(), + config.hs_blank_en, + (timing.hsync_width as u8).saturating_sub(1), + config.hsync_idle_level.into(), + timing.hsync_position as u8, + ); self.regs().lcd_misc().modify(|_, w| unsafe { - // TODO: Find out what this field actually does. - // Set the threshold for Async Tx FIFO full event. (5 bits) + #[cfg(not(esp32s31))] w.lcd_afifo_threshold_num().bits((1 << 5) - 1); // Doesn't matter for RGB mode. @@ -250,30 +237,13 @@ where // Enable blank region when LCD sends data out. w.lcd_bk_en().bit(!config.disable_black_region) }); - self.regs().lcd_dly_mode().modify(|_, w| unsafe { - w.lcd_de_mode().bits(config.de_mode as u8); - w.lcd_hsync_mode().bits(config.hsync_mode as u8); - w.lcd_vsync_mode().bits(config.vsync_mode as u8); - w - }); - self.regs().lcd_data_dout_mode().modify(|_, w| unsafe { - w.dout0_mode().bits(config.output_bit_mode as u8); - w.dout1_mode().bits(config.output_bit_mode as u8); - w.dout2_mode().bits(config.output_bit_mode as u8); - w.dout3_mode().bits(config.output_bit_mode as u8); - w.dout4_mode().bits(config.output_bit_mode as u8); - w.dout5_mode().bits(config.output_bit_mode as u8); - w.dout6_mode().bits(config.output_bit_mode as u8); - w.dout7_mode().bits(config.output_bit_mode as u8); - w.dout8_mode().bits(config.output_bit_mode as u8); - w.dout9_mode().bits(config.output_bit_mode as u8); - w.dout10_mode().bits(config.output_bit_mode as u8); - w.dout11_mode().bits(config.output_bit_mode as u8); - w.dout12_mode().bits(config.output_bit_mode as u8); - w.dout13_mode().bits(config.output_bit_mode as u8); - w.dout14_mode().bits(config.output_bit_mode as u8); - w.dout15_mode().bits(config.output_bit_mode as u8) - }); + ll::set_sync_delay( + self.regs(), + config.de_mode as u8, + config.hsync_mode as u8, + config.vsync_mode as u8, + ); + ll::set_data_bit_delay(self.regs(), config.output_bit_mode as u8); self.regs() .lcd_user() @@ -481,16 +451,8 @@ where next_frame_en: bool, mut buf: TX, ) -> Result, (DmaError, Self, TX)> { - let result = unsafe { - self.tx_channel - .prepare_transfer(DmaPeripheral::LCD_CAM, &mut buf) - } - .and_then(|_| self.tx_channel.start_transfer()); - if let Err(err) = result { - return Err((err, self, buf)); - } - - // Reset LCD control unit and Async Tx FIFO + // Reset before DMA start. AXI-GDMA can fill the LCD AFIFO immediately; a later + // FIFO reset would drop the first pixels of the frame. self.regs() .lcd_user() .modify(|_, w| w.lcd_reset().set_bit()); @@ -504,6 +466,15 @@ where w.lcd_next_frame_en().bit(next_frame_en) }); + let result = unsafe { + self.tx_channel + .prepare_transfer(DmaPeripheral::LCD_CAM, &mut buf) + } + .and_then(|_| self.tx_channel.start_transfer()); + if let Err(err) = result { + return Err((err, self, buf)); + } + // Start the transfer. self.regs().lcd_user().modify(|_, w| { w.lcd_update().set_bit(); diff --git a/esp-hal/src/lcd_cam/lcd/i8080.rs b/esp-hal/src/lcd_cam/lcd/i8080.rs index 4a3296a6316..1e1ae44c527 100644 --- a/esp-hal/src/lcd_cam/lcd/i8080.rs +++ b/esp-hal/src/lcd_cam/lcd/i8080.rs @@ -65,6 +65,7 @@ use crate::{ Lcd, LcdDmaTxChannel, lcd::{ClockConfig, ClockMode, DelayMode}, + ll, }, pac, time::Rate, @@ -118,28 +119,27 @@ where self.lcd .configure_clocks(&ClockConfig { clock_mode: config.clock_mode, - // Due to https://www.espressif.com/sites/default/files/documentation/esp32-s3_errata_en.pdf - // the LCD_PCLK divider must be at least 2. To make up for this the user - // provided frequency is doubled to match. - frequency: config.frequency * 2, + // ESP32-S3 errata requires LCD_PCLK to divide LCD_CLK by at least 2. + // Double the requested frequency so the extra divider still matches. + frequency: if cfg!(esp32s3) { + config.frequency * 2 + } else { + config.frequency + }, }) .map_err(ConfigError::Clock)?; - self.regs() - .lcd_ctrl() - .write(|w| w.lcd_rgb_mode_en().clear_bit()); - self.regs() - .lcd_rgb_yuv() - .write(|w| w.lcd_conv_bypass().clear_bit()); + ll::set_rgb_mode_en(self.regs(), false); + ll::set_lcd_conv_bypass(self.regs()); self.regs().lcd_user().modify(|_, w| { - w.lcd_8bits_order().bit(false); w.lcd_bit_order().bit(false); - w.lcd_byte_order().bit(false); - w.lcd_2byte_en().bit(false) + w.lcd_byte_order().bit(false) }); + ll::set_8bits_order(self.regs(), false); + ll::set_2byte_mode(self.regs(), false); self.regs().lcd_misc().write(|w| unsafe { - // Set the threshold for Async Tx FIFO full event. (5 bits) + #[cfg(not(esp32s31))] w.lcd_afifo_threshold_num().bits(0); // Configure the setup cycles in LCD non-RGB mode. Setup cycles // expected = this value + 1. (6 bit) @@ -169,27 +169,8 @@ where // The default value of LCD_CD w.lcd_cd_idle_edge().bit(config.cd_idle_edge) }); - self.regs() - .lcd_dly_mode() - .write(|w| unsafe { w.lcd_cd_mode().bits(config.cd_mode as u8) }); - self.regs().lcd_data_dout_mode().write(|w| unsafe { - w.dout0_mode().bits(config.output_bit_mode as u8); - w.dout1_mode().bits(config.output_bit_mode as u8); - w.dout2_mode().bits(config.output_bit_mode as u8); - w.dout3_mode().bits(config.output_bit_mode as u8); - w.dout4_mode().bits(config.output_bit_mode as u8); - w.dout5_mode().bits(config.output_bit_mode as u8); - w.dout6_mode().bits(config.output_bit_mode as u8); - w.dout7_mode().bits(config.output_bit_mode as u8); - w.dout8_mode().bits(config.output_bit_mode as u8); - w.dout9_mode().bits(config.output_bit_mode as u8); - w.dout10_mode().bits(config.output_bit_mode as u8); - w.dout11_mode().bits(config.output_bit_mode as u8); - w.dout12_mode().bits(config.output_bit_mode as u8); - w.dout13_mode().bits(config.output_bit_mode as u8); - w.dout14_mode().bits(config.output_bit_mode as u8); - w.dout15_mode().bits(config.output_bit_mode as u8) - }); + ll::set_cd_delay(self.regs(), config.cd_mode as u8); + ll::set_data_bit_delay(self.regs(), config.output_bit_mode as u8); self.regs() .lcd_user() @@ -214,9 +195,7 @@ where /// mode. pub fn set_8bits_order(&mut self, byte_order: ByteOrder) -> &mut Self { let is_inverted = byte_order != ByteOrder::default(); - self.regs() - .lcd_user() - .modify(|_, w| w.lcd_8bits_order().bit(is_inverted)); + ll::set_8bits_order(self.regs(), is_inverted); self } @@ -388,19 +367,14 @@ where w.lcd_cmd().set_bit(); w.lcd_cmd_2_cycle_en().clear_bit() }); - self.regs() - .lcd_cmd_val() - .write(|w| unsafe { w.lcd_cmd_value().bits(value.into() as _) }); + ll::write_command(self.regs(), value.into() as u32, None); } Command::Two(first, second) => { self.regs().lcd_user().modify(|_, w| { w.lcd_cmd().set_bit(); w.lcd_cmd_2_cycle_en().set_bit() }); - let cmd = first.into() as u32 | ((second.into() as u32) << 16); - self.regs() - .lcd_cmd_val() - .write(|w| unsafe { w.lcd_cmd_value().bits(cmd) }); + ll::write_command(self.regs(), first.into() as u32, Some(second.into() as u32)); } } @@ -417,9 +391,8 @@ where } else { w.lcd_dummy().clear_bit() } - .lcd_2byte_en() - .bit(is_2byte_mode) }); + ll::set_2byte_mode(self.regs(), is_2byte_mode); // Use continous mode for DMA. FROM the S3 TRM: // > In a continuous output, LCD module keeps sending data till: diff --git a/esp-hal/src/lcd_cam/lcd/mod.rs b/esp-hal/src/lcd_cam/lcd/mod.rs index 2cb1bcbc8b6..a5baa7b2c0b 100644 --- a/esp-hal/src/lcd_cam/lcd/mod.rs +++ b/esp-hal/src/lcd_cam/lcd/mod.rs @@ -74,8 +74,14 @@ impl<'d, Dm: DriverMode> Lcd<'d, Dm> { self.regs().lcd_clock().write(|w| unsafe { // Force enable the clock for all configuration registers. w.clk_en().set_bit(); - w.lcd_clk_equ_sysclk().clear_bit(); - w.lcd_clkcnt_n().bits(2 - 1); // Must not be 0. + if cfg!(esp32s3) { + // ESP32-S3 errata: LCD_PCLK must divide LCD_CLK by at least 2. + w.lcd_clk_equ_sysclk().clear_bit(); + w.lcd_clkcnt_n().bits(2 - 1); // Must not be 0. + } else { + // ESP32-S31: PCLK tracks LCD_CLK. + w.lcd_clk_equ_sysclk().set_bit(); + } w.lcd_ck_idle_edge() .bit(config.clock_mode.polarity == Polarity::IdleHigh); w.lcd_ck_out_edge() diff --git a/esp-hal/src/lcd_cam/ll.rs b/esp-hal/src/lcd_cam/ll.rs new file mode 100644 index 00000000000..ebaa9b8b089 --- /dev/null +++ b/esp-hal/src/lcd_cam/ll.rs @@ -0,0 +1,205 @@ +//! Chip-specific LCD_CAM register helpers. + +use crate::pac; + +pub(super) fn set_lcd_conv_bypass(regs: &pac::lcd_cam::RegisterBlock) { + regs.lcd_rgb_yuv().write(|w| { + cfg_select! { + esp32s31 => w.lcd_conv_enable().clear_bit(), + _ => w.lcd_conv_bypass().clear_bit(), + } + }); +} + +pub(super) fn set_cam_conv_bypass(regs: &pac::lcd_cam::RegisterBlock) { + regs.cam_rgb_yuv().write(|w| { + cfg_select! { + esp32s31 => w.cam_conv_enable().clear_bit(), + _ => w.cam_conv_bypass().clear_bit(), + } + }); +} + +pub(super) fn set_rgb_mode_en(regs: &pac::lcd_cam::RegisterBlock, enable: bool) { + let reg = cfg_select! { + esp32s3 => regs.lcd_ctrl(), + esp32s31 => regs.lcd_misc(), + }; + reg.modify(|_, w| w.lcd_rgb_mode_en().bit(enable)); +} + +pub(super) fn set_2byte_mode(regs: &pac::lcd_cam::RegisterBlock, enable: bool) { + regs.lcd_user().modify(|_, w| { + cfg_select! { + esp32s31 => unsafe { w.lcd_byte_mode().bits(if enable { 1 } else { 0 }) }, + _ => w.lcd_2byte_en().bit(enable), + } + }); +} + +pub(super) fn set_8bits_order(regs: &pac::lcd_cam::RegisterBlock, inverted: bool) { + regs.lcd_user().modify(|_, w| { + cfg_select! { + esp32s31 => unsafe { + w.lcd_dout_byte_swizzle_enable().bit(inverted); + w.lcd_dout_byte_swizzle_mode().bits(0) + }, + _ => w.lcd_8bits_order().bit(inverted), + } + }); +} + +pub(super) fn set_cd_delay(regs: &pac::lcd_cam::RegisterBlock, mode: u8) { + let reg = cfg_select! { + esp32s31 => regs.lcd_dly_mode_cfg1(), + _ => regs.lcd_dly_mode(), + }; + reg.write(|w| unsafe { w.lcd_cd_mode().bits(mode) }); +} + +pub(super) fn set_data_bit_delay(regs: &pac::lcd_cam::RegisterBlock, mode: u8) { + let dout_0_15 = cfg_select! { + esp32s31 => { + regs.lcd_dly_mode_cfg2() + } + _ => + regs.lcd_data_dout_mode() + }; + + dout_0_15.write(|w| unsafe { + w.dout0_mode().bits(mode); + w.dout1_mode().bits(mode); + w.dout2_mode().bits(mode); + w.dout3_mode().bits(mode); + w.dout4_mode().bits(mode); + w.dout5_mode().bits(mode); + w.dout6_mode().bits(mode); + w.dout7_mode().bits(mode); + w.dout8_mode().bits(mode); + w.dout9_mode().bits(mode); + w.dout10_mode().bits(mode); + w.dout11_mode().bits(mode); + w.dout12_mode().bits(mode); + w.dout13_mode().bits(mode); + w.dout14_mode().bits(mode); + w.dout15_mode().bits(mode) + }); + + #[cfg(rgb_display_output_lines = "24")] + regs.lcd_dly_mode_cfg1().modify(|_, w| unsafe { + w.dout16_mode().bits(mode); + w.dout17_mode().bits(mode); + w.dout18_mode().bits(mode); + w.dout19_mode().bits(mode); + w.dout20_mode().bits(mode); + w.dout21_mode().bits(mode); + w.dout22_mode().bits(mode); + w.dout23_mode().bits(mode) + }); +} + +pub(super) fn set_sync_delay( + regs: &pac::lcd_cam::RegisterBlock, + de_mode: u8, + hsync_mode: u8, + vsync_mode: u8, +) { + let reg = cfg_select! { + esp32s31 => regs.lcd_dly_mode_cfg1(), + _ => regs.lcd_dly_mode(), + }; + + reg.modify(|_, w| unsafe { + w.lcd_de_mode().bits(de_mode); + w.lcd_hsync_mode().bits(hsync_mode); + w.lcd_vsync_mode().bits(vsync_mode) + }); +} + +pub(super) fn write_command(regs: &pac::lcd_cam::RegisterBlock, first: u32, second: Option) { + cfg_select! { + esp32s3 => { + let value = match second { + Some(second) => first | (second << 16), + None => first, + }; + regs.lcd_cmd_val() + .write(|w| unsafe { w.lcd_cmd_value().bits(value) }); + } + _ => { + regs.lcd_first_cmd_val() + .write(|w| unsafe { w.lcd_first_cmd_value().bits(first) }); + if let Some(second) = second { + regs.lcd_latter_cmd_val() + .write(|w| unsafe { w.lcd_latter_cmd_value().bits(second) }); + } + } + } +} + +#[expect(clippy::too_many_arguments)] +pub(super) fn configure_rgb_timing( + regs: &pac::lcd_cam::RegisterBlock, + hb_front: u16, + va_height: u16, + vt_height: u16, + vb_front: u16, + ha_width: u16, + ht_width: u16, + vsync_width: u16, + vsync_idle_high: bool, + de_idle_high: bool, + hs_blank_en: bool, + hsync_width: u8, + hsync_idle_high: bool, + hsync_position: u8, +) { + cfg_select! { + esp32s3 => { + regs.lcd_ctrl().modify(|_, w| unsafe { + w.lcd_rgb_mode_en().set_bit(); + w.lcd_hb_front().bits(hb_front); + w.lcd_va_height().bits(va_height); + w.lcd_vt_height().bits(vt_height) + }); + regs.lcd_ctrl1().modify(|_, w| unsafe { + w.lcd_vb_front().bits(vb_front as u8); + w.lcd_ha_width().bits(ha_width); + w.lcd_ht_width().bits(ht_width) + }); + regs.lcd_ctrl2().modify(|_, w| unsafe { + w.lcd_vsync_width().bits(vsync_width as u8); + w.lcd_vsync_idle_pol().bit(vsync_idle_high); + w.lcd_de_idle_pol().bit(de_idle_high); + w.lcd_hs_blank_en().bit(hs_blank_en); + w.lcd_hsync_width().bits(hsync_width); + w.lcd_hsync_idle_pol().bit(hsync_idle_high); + w.lcd_hsync_position().bits(hsync_position) + }); + } + _ => { + regs.lcd_misc().modify(|_, w| w.lcd_rgb_mode_en().set_bit()); + regs.lcd_rgb_blank().write(|w| unsafe { + w.lcd_hb_front().bits(hb_front); + w.lcd_vb_front().bits(vb_front) + }); + regs.lcd_rgb_vertical().write(|w| unsafe { + w.lcd_va_height().bits(va_height); + w.lcd_vt_height().bits(vt_height) + }); + regs.lcd_rgb_horizontal().write(|w| unsafe { + w.lcd_ha_width().bits(ha_width); + w.lcd_ht_width().bits(ht_width) + }); + regs.lcd_rgb_ctrl().write(|w| unsafe { + w.lcd_vsync_width().bits(vsync_width); + w.lcd_vsync_idle_pol().bit(vsync_idle_high); + w.lcd_de_idle_pol().bit(de_idle_high); + w.lcd_hs_blank_en().bit(hs_blank_en); + w.lcd_hsync_width().bits(hsync_width); + w.lcd_hsync_idle_pol().bit(hsync_idle_high); + w.lcd_hsync_position().bits(hsync_position) + }); + } + } +} diff --git a/esp-hal/src/lcd_cam/mod.rs b/esp-hal/src/lcd_cam/mod.rs index 91d39d67649..c3b1540d6f4 100644 --- a/esp-hal/src/lcd_cam/mod.rs +++ b/esp-hal/src/lcd_cam/mod.rs @@ -21,6 +21,7 @@ use crate::{ pub mod cam; pub mod lcd; +pub(crate) mod ll; /// DMA TX channel trait for LCD (I8080, DPI) peripherals. /// diff --git a/esp-hal/src/soc/esp32s31/clocks.rs b/esp-hal/src/soc/esp32s31/clocks.rs index bc2159d7e3f..a3373cc1b95 100644 --- a/esp-hal/src/soc/esp32s31/clocks.rs +++ b/esp-hal/src/soc/esp32s31/clocks.rs @@ -620,3 +620,82 @@ impl SdmInstance { .modify(|_, w| w.sigmadelta_clk_en().bit(en)); } } + +impl LcdCamInstance { + fn enable_shared_core_clock(self, clocks: &ClockTree, en: bool) { + let idx = self as usize; + let sibling_held = clocks.lcd_cam_lcd_clock_refcount[idx] > 0 + || clocks.lcd_cam_cam_clock_refcount[idx] > 0; + if !en && sibling_held { + return; + } + + HP_SYS::regs().lcdcam_mem_lp_ctrl().modify(|_, w| { + w.lcdcam_mem_lp_force_ctrl().set_bit(); + w.lcdcam_mem_lp_en().bit(!en) + }); + // Shared LCD/CAM core clock. Source 0 = XTAL. Divider stores N - 1. + HP_SYS_CLKRST::regs() + .lcdcam_lcdcam_ctrl0() + .modify(|_, w| unsafe { + w.clk_en().bit(en); + w.clk_src_sel().bits(0); + w.clk_div_num().bits(0) + }); + } + + fn enable_lcd_clock_impl(self, clocks: &mut ClockTree, en: bool) { + self.enable_shared_core_clock(clocks, en); + HP_SYS_CLKRST::regs() + .lcdcam_lcd_ctrl0() + .modify(|_, w| w.clk_en().bit(en)); + } + + fn configure_lcd_clock_impl( + self, + _clocks: &mut ClockTree, + _old_config: Option, + new_config: LcdCamLcdClockConfig, + ) { + // Register stores N - 1. Source: 0 = XTAL, 1 = PLL_F160M, 2 = APLL. + let div_num = (new_config.div_num() - 1) as u8; + HP_SYS_CLKRST::regs() + .lcdcam_lcd_ctrl0() + .modify(|_, w| unsafe { + w.clk_src_sel().bits(match new_config.sclk() { + LcdCamLcdClockSclk::XtalClk => 0, + LcdCamLcdClockSclk::PllF160m => 1, + }); + w.clk_div_num().bits(div_num); + w.clk_div_denominator().bits(new_config.div_a() as u8); + w.clk_div_numerator().bits(new_config.div_b() as u8) + }); + } + + fn enable_cam_clock_impl(self, clocks: &mut ClockTree, en: bool) { + self.enable_shared_core_clock(clocks, en); + HP_SYS_CLKRST::regs() + .lcdcam_cam_ctrl0() + .modify(|_, w| w.clk_en().bit(en)); + } + + fn configure_cam_clock_impl( + self, + _clocks: &mut ClockTree, + _old_config: Option, + new_config: LcdCamCamClockConfig, + ) { + let div_num = (new_config.div_num() - 1) as u8; + HP_SYS_CLKRST::regs() + .lcdcam_cam_ctrl0() + .modify(|_, w| unsafe { + w.clk_src_sel().bits(match new_config.sclk() { + LcdCamCamClockSclk::XtalClk => 0, + LcdCamCamClockSclk::PllF160m => 1, + }); + w.clk_div_num().bits(div_num); + w.clk_div_denominator().bits(new_config.div_a() as u8); + w.clk_div_numerator().bits(new_config.div_b() as u8) + }); + } +} diff --git a/esp-metadata-generated/src/_build_script_utils.rs b/esp-metadata-generated/src/_build_script_utils.rs index 5c3abb8a9c4..89ce69c7f28 100644 --- a/esp-metadata-generated/src/_build_script_utils.rs +++ b/esp-metadata-generated/src/_build_script_utils.rs @@ -366,6 +366,7 @@ impl Chip { "wifi_mac_version=\"1\"", "wifi_csi_supported", "phy_combo_module", + "rgb_display_output_lines=\"24\"", "ledc_version=\"1\"", "ledc_channel_count=\"8\"", "soc_has_sdm_ch0", @@ -646,6 +647,7 @@ impl Chip { "cargo:rustc-cfg=wifi_mac_version=\"1\"", "cargo:rustc-cfg=wifi_csi_supported", "cargo:rustc-cfg=phy_combo_module", + "cargo:rustc-cfg=rgb_display_output_lines=\"24\"", "cargo:rustc-cfg=ledc_version=\"1\"", "cargo:rustc-cfg=ledc_channel_count=\"8\"", "cargo:rustc-cfg=soc_has_sdm_ch0", @@ -7185,6 +7187,7 @@ impl Chip { "phy_combo_module", "phy_backed_up_digital_register_count=\"21\"", "phy_backed_up_digital_register_count_is_set", + "rgb_display_output_lines=\"16\"", "ledc_version=\"2\"", "ledc_channel_count=\"8\"", "soc_has_sdm_ch0", @@ -7527,6 +7530,7 @@ impl Chip { "cargo:rustc-cfg=phy_combo_module", "cargo:rustc-cfg=phy_backed_up_digital_register_count=\"21\"", "cargo:rustc-cfg=phy_backed_up_digital_register_count_is_set", + "cargo:rustc-cfg=rgb_display_output_lines=\"16\"", "cargo:rustc-cfg=ledc_version=\"2\"", "cargo:rustc-cfg=ledc_channel_count=\"8\"", "cargo:rustc-cfg=soc_has_sdm_ch0", @@ -7907,6 +7911,7 @@ impl Chip { "soc_has_hp_sys_clkrst", "soc_has_i2c0", "soc_has_i2c1", + "soc_has_lcd_cam", "soc_has_interrupt_core0", "soc_has_interrupt_core1", "soc_has_io_mux", @@ -7971,6 +7976,8 @@ impl Chip { "rmt_driver_supported", "sdmmc_driver_supported", "usb_otg_hs_driver_supported", + "camera_driver_supported", + "rgb_display_driver_supported", "adc_driver_supported", "lp_timer_driver_supported", "sdm_driver_supported", @@ -8048,6 +8055,7 @@ impl Chip { "sdmmc_has_iomux", "sdmmc_psram_dma", "usb_otg_hs_fifo_depth_words=\"896\"", + "rgb_display_output_lines=\"24\"", "soc_has_sdm_ch0", "soc_has_sdm_ch1", "soc_has_sdm_ch2", @@ -8097,6 +8105,8 @@ impl Chip { "spi_master_dma_engine=\"AXI_GDMA\"", "aes_supports_dma", "aes_dma_engine=\"AXI_GDMA\"", + "lcd_cam_supports_dma", + "lcd_cam_dma_engine=\"AXI_GDMA\"", "dma_can_access_psram", "dma_max_priority=\"15\"", "dma_max_priority_is_set", @@ -8164,6 +8174,10 @@ impl Chip { "soc_has_clock_node_rmt_sclk", "soc_clock_node_rmt_sclk_is_configurable", "soc_has_clock_node_sdm_function_clock", + "soc_has_clock_node_lcd_cam_lcd_clock", + "soc_clock_node_lcd_cam_lcd_clock_is_configurable", + "soc_has_clock_node_lcd_cam_cam_clock", + "soc_clock_node_lcd_cam_cam_clock_is_configurable", "has_dram_region", "has_dram2_uninit_region", "has_irom_region", @@ -8191,6 +8205,7 @@ impl Chip { "cargo:rustc-cfg=soc_has_hp_sys_clkrst", "cargo:rustc-cfg=soc_has_i2c0", "cargo:rustc-cfg=soc_has_i2c1", + "cargo:rustc-cfg=soc_has_lcd_cam", "cargo:rustc-cfg=soc_has_interrupt_core0", "cargo:rustc-cfg=soc_has_interrupt_core1", "cargo:rustc-cfg=soc_has_io_mux", @@ -8255,6 +8270,8 @@ impl Chip { "cargo:rustc-cfg=rmt_driver_supported", "cargo:rustc-cfg=sdmmc_driver_supported", "cargo:rustc-cfg=usb_otg_hs_driver_supported", + "cargo:rustc-cfg=camera_driver_supported", + "cargo:rustc-cfg=rgb_display_driver_supported", "cargo:rustc-cfg=adc_driver_supported", "cargo:rustc-cfg=lp_timer_driver_supported", "cargo:rustc-cfg=sdm_driver_supported", @@ -8332,6 +8349,7 @@ impl Chip { "cargo:rustc-cfg=sdmmc_has_iomux", "cargo:rustc-cfg=sdmmc_psram_dma", "cargo:rustc-cfg=usb_otg_hs_fifo_depth_words=\"896\"", + "cargo:rustc-cfg=rgb_display_output_lines=\"24\"", "cargo:rustc-cfg=soc_has_sdm_ch0", "cargo:rustc-cfg=soc_has_sdm_ch1", "cargo:rustc-cfg=soc_has_sdm_ch2", @@ -8381,6 +8399,8 @@ impl Chip { "cargo:rustc-cfg=spi_master_dma_engine=\"AXI_GDMA\"", "cargo:rustc-cfg=aes_supports_dma", "cargo:rustc-cfg=aes_dma_engine=\"AXI_GDMA\"", + "cargo:rustc-cfg=lcd_cam_supports_dma", + "cargo:rustc-cfg=lcd_cam_dma_engine=\"AXI_GDMA\"", "cargo:rustc-cfg=dma_can_access_psram", "cargo:rustc-cfg=dma_max_priority=\"15\"", "cargo:rustc-cfg=dma_max_priority_is_set", @@ -8448,6 +8468,10 @@ impl Chip { "cargo:rustc-cfg=soc_has_clock_node_rmt_sclk", "cargo:rustc-cfg=soc_clock_node_rmt_sclk_is_configurable", "cargo:rustc-cfg=soc_has_clock_node_sdm_function_clock", + "cargo:rustc-cfg=soc_has_clock_node_lcd_cam_lcd_clock", + "cargo:rustc-cfg=soc_clock_node_lcd_cam_lcd_clock_is_configurable", + "cargo:rustc-cfg=soc_has_clock_node_lcd_cam_cam_clock", + "cargo:rustc-cfg=soc_clock_node_lcd_cam_cam_clock_is_configurable", "cargo:rustc-cfg=has_dram_region", "cargo:rustc-cfg=has_dram2_uninit_region", "cargo:rustc-cfg=has_irom_region", @@ -9332,6 +9356,7 @@ impl Chip { "rmt_channel_ram_size, values(\"64\",\"48\")", "bt_controller, values(\"btdm\",\"npl\")", "wifi_mac_version, values(\"1\",\"3\",\"2\")", + "rgb_display_output_lines, values(\"24\",\"16\")", "ledc_version, values(\"1\",\"2\",\"3\")", "ledc_channel_count, values(\"8\",\"6\")", "rng_apb_cycle_wait_num, values(\"16\")", @@ -9369,7 +9394,7 @@ impl Chip { "usb_otg_hs_fifo_depth_words, values(\"896\")", "mipi_dsi_dma_engine, values(\"VDMA\")", "rmt_dma_engine, values(\"AHB_GDMA\")", - "lcd_cam_dma_engine, values(\"AHB_GDMA\")", + "lcd_cam_dma_engine, values(\"AHB_GDMA\",\"AXI_GDMA\")", ] } } diff --git a/esp-metadata-generated/src/_generated_esp32.rs b/esp-metadata-generated/src/_generated_esp32.rs index 83388432b2e..ddbae7aad76 100644 --- a/esp-metadata-generated/src/_generated_esp32.rs +++ b/esp-metadata-generated/src/_generated_esp32.rs @@ -340,6 +340,12 @@ macro_rules! property { ("phy.combo_module") => { true }; + ("rgb_display.output_lines") => { + 24 + }; + ("rgb_display.output_lines", str) => { + stringify!(24) + }; ("ledc.version") => { 1 }; diff --git a/esp-metadata-generated/src/_generated_esp32s3.rs b/esp-metadata-generated/src/_generated_esp32s3.rs index 31d0c5657aa..9d6911f658a 100644 --- a/esp-metadata-generated/src/_generated_esp32s3.rs +++ b/esp-metadata-generated/src/_generated_esp32s3.rs @@ -367,6 +367,12 @@ macro_rules! property { ("phy.backed_up_digital_register_count", str) => { stringify!(21) }; + ("rgb_display.output_lines") => { + 16 + }; + ("rgb_display.output_lines", str) => { + stringify!(16) + }; ("ledc.version") => { 2 }; diff --git a/esp-metadata-generated/src/_generated_esp32s31.rs b/esp-metadata-generated/src/_generated_esp32s31.rs index 82ad759e3b9..4a1abd5d0fe 100644 --- a/esp-metadata-generated/src/_generated_esp32s31.rs +++ b/esp-metadata-generated/src/_generated_esp32s31.rs @@ -286,6 +286,12 @@ macro_rules! property { ("usb_otg_hs.fifo_depth_words", str) => { stringify!(896) }; + ("rgb_display.output_lines") => { + 24 + }; + ("rgb_display.output_lines", str) => { + stringify!(24) + }; ("sdm.channel_count") => { 8 }; @@ -526,6 +532,32 @@ macro_rules! property { ::soc::clocks::RmtSclkConfig::RcFastClk, crate ::soc::clocks::RmtSclkConfig::XtalClk] }; + ("clock_tree.lcd_cam.lcd_clock.sclk") => { + [crate ::soc::clocks::LcdCamLcdClockSclk::XtalClk, crate + ::soc::clocks::LcdCamLcdClockSclk::PllF160m] + }; + ("clock_tree.lcd_cam.lcd_clock.div_num") => { + (1, 256) + }; + ("clock_tree.lcd_cam.lcd_clock.div_a") => { + (1, 255) + }; + ("clock_tree.lcd_cam.lcd_clock.div_b") => { + (0, 255) + }; + ("clock_tree.lcd_cam.cam_clock.sclk") => { + [crate ::soc::clocks::LcdCamCamClockSclk::XtalClk, crate + ::soc::clocks::LcdCamCamClockSclk::PllF160m] + }; + ("clock_tree.lcd_cam.cam_clock.div_num") => { + (1, 256) + }; + ("clock_tree.lcd_cam.cam_clock.div_a") => { + (1, 255) + }; + ("clock_tree.lcd_cam.cam_clock.div_b") => { + (0, 255) + }; } #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] @@ -996,16 +1028,17 @@ macro_rules! for_each_dma_channel { _for_each_inner_dma_channel!(("AHB_GDMA", DMA_CH4, 4, interrupt_in = AHB_PDMA_IN_CH4, interrupt_out = AHB_PDMA_OUT_CH4, compatible = [UHCI0])); _for_each_inner_dma_channel!(("AXI_GDMA", DMA_AXI_CH0, 0, interrupt_in = - AXI_PDMA_IN_CH0, interrupt_out = AXI_PDMA_OUT_CH0, compatible = [SPI2, SPI3, AES, - SHA])); _for_each_inner_dma_channel!(("AXI_GDMA", DMA_AXI_CH1, 1, interrupt_in = - AXI_PDMA_IN_CH1, interrupt_out = AXI_PDMA_OUT_CH1, compatible = [SPI2, SPI3, AES, - SHA])); _for_each_inner_dma_channel!(("AXI_GDMA", DMA_AXI_CH2, 2, interrupt_in = - AXI_PDMA_IN_CH2, interrupt_out = AXI_PDMA_OUT_CH2, compatible = [SPI2, SPI3, AES, - SHA])); _for_each_inner_dma_channel!((names("AHB_GDMA", DMA_CH0), ("AHB_GDMA", - DMA_CH1), ("AHB_GDMA", DMA_CH2), ("AHB_GDMA", DMA_CH3), ("AHB_GDMA", DMA_CH4), - ("AXI_GDMA", DMA_AXI_CH0), ("AXI_GDMA", DMA_AXI_CH1), ("AXI_GDMA", - DMA_AXI_CH2))); _for_each_inner_dma_channel!((separate_any_type("AHB_GDMA", - any_channel = AhbGdmaChannel), ("AXI_GDMA", any_channel = AxiGdmaChannel))); + AXI_PDMA_IN_CH0, interrupt_out = AXI_PDMA_OUT_CH0, compatible = [LCD_CAM, SPI2, + SPI3, AES, SHA])); _for_each_inner_dma_channel!(("AXI_GDMA", DMA_AXI_CH1, 1, + interrupt_in = AXI_PDMA_IN_CH1, interrupt_out = AXI_PDMA_OUT_CH1, compatible = + [LCD_CAM, SPI2, SPI3, AES, SHA])); _for_each_inner_dma_channel!(("AXI_GDMA", + DMA_AXI_CH2, 2, interrupt_in = AXI_PDMA_IN_CH2, interrupt_out = AXI_PDMA_OUT_CH2, + compatible = [LCD_CAM, SPI2, SPI3, AES, SHA])); + _for_each_inner_dma_channel!((names("AHB_GDMA", DMA_CH0), ("AHB_GDMA", DMA_CH1), + ("AHB_GDMA", DMA_CH2), ("AHB_GDMA", DMA_CH3), ("AHB_GDMA", DMA_CH4), ("AXI_GDMA", + DMA_AXI_CH0), ("AXI_GDMA", DMA_AXI_CH1), ("AXI_GDMA", DMA_AXI_CH2))); + _for_each_inner_dma_channel!((separate_any_type("AHB_GDMA", any_channel = + AhbGdmaChannel), ("AXI_GDMA", any_channel = AxiGdmaChannel))); _for_each_inner_dma_channel!((shared)); _for_each_inner_dma_channel!((split("AHB_GDMA", DMA_CH0, 0, interrupt_in = AHB_PDMA_IN_CH0, interrupt_out = AHB_PDMA_OUT_CH0, compatible = [UHCI0]), @@ -1016,11 +1049,12 @@ macro_rules! for_each_dma_channel { AHB_PDMA_OUT_CH3, compatible = [UHCI0]), ("AHB_GDMA", DMA_CH4, 4, interrupt_in = AHB_PDMA_IN_CH4, interrupt_out = AHB_PDMA_OUT_CH4, compatible = [UHCI0]), ("AXI_GDMA", DMA_AXI_CH0, 0, interrupt_in = AXI_PDMA_IN_CH0, interrupt_out = - AXI_PDMA_OUT_CH0, compatible = [SPI2, SPI3, AES, SHA]), ("AXI_GDMA", DMA_AXI_CH1, - 1, interrupt_in = AXI_PDMA_IN_CH1, interrupt_out = AXI_PDMA_OUT_CH1, compatible = - [SPI2, SPI3, AES, SHA]), ("AXI_GDMA", DMA_AXI_CH2, 2, interrupt_in = - AXI_PDMA_IN_CH2, interrupt_out = AXI_PDMA_OUT_CH2, compatible = [SPI2, SPI3, AES, - SHA]))); _for_each_inner_dma_channel!((no_own_interrupt)); + AXI_PDMA_OUT_CH0, compatible = [LCD_CAM, SPI2, SPI3, AES, SHA]), ("AXI_GDMA", + DMA_AXI_CH1, 1, interrupt_in = AXI_PDMA_IN_CH1, interrupt_out = AXI_PDMA_OUT_CH1, + compatible = [LCD_CAM, SPI2, SPI3, AES, SHA]), ("AXI_GDMA", DMA_AXI_CH2, 2, + interrupt_in = AXI_PDMA_IN_CH2, interrupt_out = AXI_PDMA_OUT_CH2, compatible = + [LCD_CAM, SPI2, SPI3, AES, SHA]))); + _for_each_inner_dma_channel!((no_own_interrupt)); }; } #[macro_export] @@ -1033,37 +1067,43 @@ macro_rules! for_each_dma_channel_peri_pair { UHCI0)); _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH2, UHCI0)); _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH3, UHCI0)); _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH4, UHCI0)); + _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH0, LCD_CAM)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH0, SPI2)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH0, SPI3)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH0, AES)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH0, SHA)); + _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH1, LCD_CAM)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH1, SPI2)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH1, SPI3)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH1, AES)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH1, SHA)); + _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH2, LCD_CAM)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH2, SPI2)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH2, SPI3)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH2, AES)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", DMA_AXI_CH2, SHA)); _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", any_channel = AhbGdmaChannel, UHCI0)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", any_channel = - AxiGdmaChannel, SPI2)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", - any_channel = AxiGdmaChannel, SPI3)); + AxiGdmaChannel, LCD_CAM)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", + any_channel = AxiGdmaChannel, SPI2)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", any_channel = AxiGdmaChannel, - AES)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", any_channel = - AxiGdmaChannel, SHA)); + SPI3)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", any_channel = + AxiGdmaChannel, AES)); _for_each_inner_dma_channel_peri_pair!(("AXI_GDMA", + any_channel = AxiGdmaChannel, SHA)); _for_each_inner_dma_channel_peri_pair!((channels("AHB_GDMA", DMA_CH0, UHCI0), ("AHB_GDMA", DMA_CH1, UHCI0), ("AHB_GDMA", DMA_CH2, UHCI0), ("AHB_GDMA", DMA_CH3, - UHCI0), ("AHB_GDMA", DMA_CH4, UHCI0), ("AXI_GDMA", DMA_AXI_CH0, SPI2), - ("AXI_GDMA", DMA_AXI_CH0, SPI3), ("AXI_GDMA", DMA_AXI_CH0, AES), ("AXI_GDMA", - DMA_AXI_CH0, SHA), ("AXI_GDMA", DMA_AXI_CH1, SPI2), ("AXI_GDMA", DMA_AXI_CH1, - SPI3), ("AXI_GDMA", DMA_AXI_CH1, AES), ("AXI_GDMA", DMA_AXI_CH1, SHA), - ("AXI_GDMA", DMA_AXI_CH2, SPI2), ("AXI_GDMA", DMA_AXI_CH2, SPI3), ("AXI_GDMA", - DMA_AXI_CH2, AES), ("AXI_GDMA", DMA_AXI_CH2, SHA))); + UHCI0), ("AHB_GDMA", DMA_CH4, UHCI0), ("AXI_GDMA", DMA_AXI_CH0, LCD_CAM), + ("AXI_GDMA", DMA_AXI_CH0, SPI2), ("AXI_GDMA", DMA_AXI_CH0, SPI3), ("AXI_GDMA", + DMA_AXI_CH0, AES), ("AXI_GDMA", DMA_AXI_CH0, SHA), ("AXI_GDMA", DMA_AXI_CH1, + LCD_CAM), ("AXI_GDMA", DMA_AXI_CH1, SPI2), ("AXI_GDMA", DMA_AXI_CH1, SPI3), + ("AXI_GDMA", DMA_AXI_CH1, AES), ("AXI_GDMA", DMA_AXI_CH1, SHA), ("AXI_GDMA", + DMA_AXI_CH2, LCD_CAM), ("AXI_GDMA", DMA_AXI_CH2, SPI2), ("AXI_GDMA", DMA_AXI_CH2, + SPI3), ("AXI_GDMA", DMA_AXI_CH2, AES), ("AXI_GDMA", DMA_AXI_CH2, SHA))); _for_each_inner_dma_channel_peri_pair!((any_channels("AHB_GDMA", any_channel = - AhbGdmaChannel, UHCI0), ("AXI_GDMA", any_channel = AxiGdmaChannel, SPI2), - ("AXI_GDMA", any_channel = AxiGdmaChannel, SPI3), ("AXI_GDMA", any_channel = - AxiGdmaChannel, AES), ("AXI_GDMA", any_channel = AxiGdmaChannel, SHA))); + AhbGdmaChannel, UHCI0), ("AXI_GDMA", any_channel = AxiGdmaChannel, LCD_CAM), + ("AXI_GDMA", any_channel = AxiGdmaChannel, SPI2), ("AXI_GDMA", any_channel = + AxiGdmaChannel, SPI3), ("AXI_GDMA", any_channel = AxiGdmaChannel, AES), + ("AXI_GDMA", any_channel = AxiGdmaChannel, SHA))); }; } #[macro_export] @@ -1100,6 +1140,14 @@ macro_rules! with_aes_dma_engine { } #[macro_export] #[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] +macro_rules! with_lcd_cam_dma_engine { + ($($pattern:tt => $code:tt;)*) => { + macro_rules! _with_inner_lcd_cam_dma_engine { $(($pattern) => $code;)* ($other : + tt) => {} } _with_inner_lcd_cam_dma_engine!(("AXI_GDMA", AxiGdmaChannel)); + }; +} +#[macro_export] +#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))] macro_rules! with_spi_master_dma_engine { ($($pattern:tt => $code:tt;)*) => { macro_rules! _with_inner_spi_master_dma_engine { $(($pattern) => $code;)* ($other @@ -1500,6 +1548,37 @@ macro_rules! for_each_sw_interrupt { /// todo!() /// } /// } +/// impl LcdCamInstance { +/// // LCD_CAM_LCD_CLOCK +/// +/// fn enable_lcd_clock_impl(self, _clocks: &mut ClockTree, _en: bool) { +/// todo!() +/// } +/// +/// fn configure_lcd_clock_impl( +/// self, +/// _clocks: &mut ClockTree, +/// _old_config: Option, +/// _new_config: LcdCamLcdClockConfig, +/// ) { +/// todo!() +/// } +/// +/// // LCD_CAM_CAM_CLOCK +/// +/// fn enable_cam_clock_impl(self, _clocks: &mut ClockTree, _en: bool) { +/// todo!() +/// } +/// +/// fn configure_cam_clock_impl( +/// self, +/// _clocks: &mut ClockTree, +/// _old_config: Option, +/// _new_config: LcdCamCamClockConfig, +/// ) { +/// todo!() +/// } +/// } /// impl RmtInstance { /// // RMT_SCLK /// @@ -1632,6 +1711,11 @@ macro_rules! define_clock_tree_types { } #[derive(Clone, Copy, PartialEq, Eq, Debug)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] + pub enum LcdCamInstance { + LcdCam = 0, + } + #[derive(Clone, Copy, PartialEq, Eq, Debug)] + #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum RmtInstance { Rmt = 0, } @@ -1858,6 +1942,148 @@ macro_rules! define_clock_tree_types { self.div_num as u32 } } + #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)] + #[cfg_attr(feature = "defmt", derive(defmt::Format))] + pub enum LcdCamLcdClockSclk { + #[default] + /// Selects `XTAL_CLK`. + XtalClk, + /// Selects `PLL_F160M`. + PllF160m, + } + /// Configures the `LCD_CAM_LCD_CLOCK` clock node. + /// + /// The output is calculated as `OUTPUT = (sclk * div_a) / (div_num * div_a + div_b)`. + #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] + #[cfg_attr(feature = "defmt", derive(defmt::Format))] + pub struct LcdCamLcdClockConfig { + sclk: LcdCamLcdClockSclk, + div_num: u32, + div_a: u32, + div_b: u32, + } + impl LcdCamLcdClockConfig { + /// Creates a new configuration for the LCD_CLOCK clock node. + /// + /// ## Panics + /// + /// Panics if the div_num value is outside the + /// valid range (1 ..= 256). + /// + /// Panics if the div_a value is outside the + /// valid range (1 ..= 255). + /// + /// Panics if the div_b value is outside the + /// valid range (0 ..= 255). + pub const fn new( + sclk: LcdCamLcdClockSclk, + div_num: u32, + div_a: u32, + div_b: u32, + ) -> Self { + ::core::assert!( + div_num >= 1 && div_num <= 256, + "`LCD_CAM_LCD_CLOCK` div_num must be between 1 and 256 (inclusive)." + ); + ::core::assert!( + div_a >= 1 && div_a <= 255, + "`LCD_CAM_LCD_CLOCK` div_a must be between 1 and 255 (inclusive)." + ); + ::core::assert!( + div_b <= 255, + "`LCD_CAM_LCD_CLOCK` div_b must be between 0 and 255 (inclusive)." + ); + Self { + sclk, + div_num, + div_a, + div_b, + } + } + pub(crate) fn sclk(self) -> LcdCamLcdClockSclk { + self.sclk + } + pub(crate) fn div_num(self) -> u32 { + self.div_num as u32 + } + pub(crate) fn div_a(self) -> u32 { + self.div_a as u32 + } + pub(crate) fn div_b(self) -> u32 { + self.div_b as u32 + } + } + #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)] + #[cfg_attr(feature = "defmt", derive(defmt::Format))] + pub enum LcdCamCamClockSclk { + #[default] + /// Selects `XTAL_CLK`. + XtalClk, + /// Selects `PLL_F160M`. + PllF160m, + } + /// Configures the `LCD_CAM_CAM_CLOCK` clock node. + /// + /// The output is calculated as `OUTPUT = (sclk * div_a) / (div_num * div_a + div_b)`. + #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] + #[cfg_attr(feature = "defmt", derive(defmt::Format))] + pub struct LcdCamCamClockConfig { + sclk: LcdCamCamClockSclk, + div_num: u32, + div_a: u32, + div_b: u32, + } + impl LcdCamCamClockConfig { + /// Creates a new configuration for the CAM_CLOCK clock node. + /// + /// ## Panics + /// + /// Panics if the div_num value is outside the + /// valid range (1 ..= 256). + /// + /// Panics if the div_a value is outside the + /// valid range (1 ..= 255). + /// + /// Panics if the div_b value is outside the + /// valid range (0 ..= 255). + pub const fn new( + sclk: LcdCamCamClockSclk, + div_num: u32, + div_a: u32, + div_b: u32, + ) -> Self { + ::core::assert!( + div_num >= 1 && div_num <= 256, + "`LCD_CAM_CAM_CLOCK` div_num must be between 1 and 256 (inclusive)." + ); + ::core::assert!( + div_a >= 1 && div_a <= 255, + "`LCD_CAM_CAM_CLOCK` div_a must be between 1 and 255 (inclusive)." + ); + ::core::assert!( + div_b <= 255, + "`LCD_CAM_CAM_CLOCK` div_b must be between 0 and 255 (inclusive)." + ); + Self { + sclk, + div_num, + div_a, + div_b, + } + } + pub(crate) fn sclk(self) -> LcdCamCamClockSclk { + self.sclk + } + pub(crate) fn div_num(self) -> u32 { + self.div_num as u32 + } + pub(crate) fn div_a(self) -> u32 { + self.div_a as u32 + } + pub(crate) fn div_b(self) -> u32 { + self.div_b as u32 + } + } /// The list of clock signals that the `RMT_SCLK` multiplexer can output. #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] @@ -2011,6 +2237,8 @@ macro_rules! define_clock_tree_types { iomux_function_clock: Option, timg_calibration_clock: Option, i2c_function_clock: [Option; 2], + lcd_cam_lcd_clock: [Option; 1], + lcd_cam_cam_clock: [Option; 1], rmt_sclk: [Option; 1], spi_function_clock: [Option; 2], timg_function_clock: [Option; 2], @@ -2036,6 +2264,8 @@ macro_rules! define_clock_tree_types { timg_calibration_clock_refcount: u32, sdm_function_clock_refcount: [u32; 1], i2c_function_clock_refcount: [u32; 2], + lcd_cam_lcd_clock_refcount: [u32; 1], + lcd_cam_cam_clock_refcount: [u32; 1], rmt_sclk_refcount: [u32; 1], spi_function_clock_refcount: [u32; 2], timg_function_clock_refcount: [u32; 2], @@ -2090,6 +2320,14 @@ macro_rules! define_clock_tree_types { pub fn i2c1_function_clock(&self) -> Option { self.i2c_function_clock[I2cInstance::I2c1 as usize] } + /// Returns the current configuration of the LCD_CAM_LCD_CLOCK clock tree node + pub fn lcd_cam_lcd_clock(&self) -> Option { + self.lcd_cam_lcd_clock[LcdCamInstance::LcdCam as usize] + } + /// Returns the current configuration of the LCD_CAM_CAM_CLOCK clock tree node + pub fn lcd_cam_cam_clock(&self) -> Option { + self.lcd_cam_cam_clock[LcdCamInstance::LcdCam as usize] + } /// Returns the current configuration of the RMT_SCLK clock tree node pub fn rmt_sclk(&self) -> Option { self.rmt_sclk[RmtInstance::Rmt as usize] @@ -2166,6 +2404,8 @@ macro_rules! define_clock_tree_types { iomux_function_clock: None, timg_calibration_clock: None, i2c_function_clock: [None; 2], + lcd_cam_lcd_clock: [None; 1], + lcd_cam_cam_clock: [None; 1], rmt_sclk: [None; 1], spi_function_clock: [None; 2], timg_function_clock: [None; 2], @@ -2191,6 +2431,8 @@ macro_rules! define_clock_tree_types { timg_calibration_clock_refcount: 0, sdm_function_clock_refcount: [0; 1], i2c_function_clock_refcount: [0; 2], + lcd_cam_lcd_clock_refcount: [0; 1], + lcd_cam_cam_clock_refcount: [0; 1], rmt_sclk_refcount: [0; 1], spi_function_clock_refcount: [0; 2], timg_function_clock_refcount: [0; 2], @@ -2218,6 +2460,10 @@ macro_rules! define_clock_tree_types { ::core::sync::atomic::AtomicU32::new(0); static I2C_FUNCTION_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 2] = [const { ::core::sync::atomic::AtomicU32::new(0) }; 2]; + static LCD_CAM_LCD_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] = + [const { ::core::sync::atomic::AtomicU32::new(0) }; 1]; + static LCD_CAM_CAM_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] = + [const { ::core::sync::atomic::AtomicU32::new(0) }; 1]; static RMT_SCLK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] = [const { ::core::sync::atomic::AtomicU32::new(0) }; 1]; static SPI_FUNCTION_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 2] = @@ -3020,6 +3266,150 @@ macro_rules! define_clock_tree_types { } } } + impl LcdCamInstance { + pub fn configure_lcd_clock(self, clocks: &mut ClockTree, config: LcdCamLcdClockConfig) { + let old_config = clocks.lcd_cam_lcd_clock[self as usize].replace(config); + refresh_lcd_cam_lcd_clock_downstream(clocks, self); + if clocks.lcd_cam_lcd_clock_refcount[self as usize] > 0 { + match config.sclk { + LcdCamLcdClockSclk::XtalClk => request_xtal_clk(clocks), + LcdCamLcdClockSclk::PllF160m => request_pll_f160m(clocks), + } + self.configure_lcd_clock_impl(clocks, old_config, config); + if let Some(old_config) = old_config { + match old_config.sclk { + LcdCamLcdClockSclk::XtalClk => release_xtal_clk(clocks), + LcdCamLcdClockSclk::PllF160m => release_pll_f160m(clocks), + } + } + } else { + self.configure_lcd_clock_impl(clocks, old_config, config); + } + } + pub fn lcd_clock_config(self, clocks: &mut ClockTree) -> Option { + clocks.lcd_cam_lcd_clock[self as usize] + } + pub fn request_lcd_clock(self, clocks: &mut ClockTree) { + trace!("Requesting {:?}::LCD_CLOCK", self); + if increment_reference_count(&mut clocks.lcd_cam_lcd_clock_refcount[self as usize]) + { + trace!("Enabling {:?}::LCD_CLOCK", self); + crate::rtc_cntl::WakeLock::acquire(); + match unwrap!(clocks.lcd_cam_lcd_clock[self as usize]).sclk { + LcdCamLcdClockSclk::XtalClk => request_xtal_clk(clocks), + LcdCamLcdClockSclk::PllF160m => request_pll_f160m(clocks), + } + self.enable_lcd_clock_impl(clocks, true); + } + } + pub fn release_lcd_clock(self, clocks: &mut ClockTree) { + trace!("Releasing {:?}::LCD_CLOCK", self); + if decrement_reference_count(&mut clocks.lcd_cam_lcd_clock_refcount[self as usize]) + { + trace!("Disabling {:?}::LCD_CLOCK", self); + crate::rtc_cntl::WakeLock::release(); + self.enable_lcd_clock_impl(clocks, false); + match unwrap!(clocks.lcd_cam_lcd_clock[self as usize]).sclk { + LcdCamLcdClockSclk::XtalClk => release_xtal_clk(clocks), + LcdCamLcdClockSclk::PllF160m => release_pll_f160m(clocks), + } + } + } + #[allow(unused_variables)] + pub fn lcd_clock_config_frequency( + clocks: &mut ClockTree, + config: LcdCamLcdClockConfig, + ) -> u32 { + (((match config.sclk { + LcdCamLcdClockSclk::XtalClk => xtal_clk_frequency(), + LcdCamLcdClockSclk::PllF160m => pll_f160m_frequency(), + } as u64) + * (config.div_a() as u64)) + / (((config.div_num() * config.div_a()) + config.div_b()) as u64)) + as u32 + } + pub fn lcd_clock_frequency(self) -> u32 { + LCD_CAM_LCD_CLOCK_FREQ_CACHE[self as usize] + .load(::core::sync::atomic::Ordering::Acquire) + } + pub fn lcd_clock_source_frequency(sclk: LcdCamLcdClockSclk) -> u32 { + match sclk { + LcdCamLcdClockSclk::XtalClk => xtal_clk_frequency(), + LcdCamLcdClockSclk::PllF160m => pll_f160m_frequency(), + } + } + pub fn configure_cam_clock(self, clocks: &mut ClockTree, config: LcdCamCamClockConfig) { + let old_config = clocks.lcd_cam_cam_clock[self as usize].replace(config); + refresh_lcd_cam_cam_clock_downstream(clocks, self); + if clocks.lcd_cam_cam_clock_refcount[self as usize] > 0 { + match config.sclk { + LcdCamCamClockSclk::XtalClk => request_xtal_clk(clocks), + LcdCamCamClockSclk::PllF160m => request_pll_f160m(clocks), + } + self.configure_cam_clock_impl(clocks, old_config, config); + if let Some(old_config) = old_config { + match old_config.sclk { + LcdCamCamClockSclk::XtalClk => release_xtal_clk(clocks), + LcdCamCamClockSclk::PllF160m => release_pll_f160m(clocks), + } + } + } else { + self.configure_cam_clock_impl(clocks, old_config, config); + } + } + pub fn cam_clock_config(self, clocks: &mut ClockTree) -> Option { + clocks.lcd_cam_cam_clock[self as usize] + } + pub fn request_cam_clock(self, clocks: &mut ClockTree) { + trace!("Requesting {:?}::CAM_CLOCK", self); + if increment_reference_count(&mut clocks.lcd_cam_cam_clock_refcount[self as usize]) + { + trace!("Enabling {:?}::CAM_CLOCK", self); + crate::rtc_cntl::WakeLock::acquire(); + match unwrap!(clocks.lcd_cam_cam_clock[self as usize]).sclk { + LcdCamCamClockSclk::XtalClk => request_xtal_clk(clocks), + LcdCamCamClockSclk::PllF160m => request_pll_f160m(clocks), + } + self.enable_cam_clock_impl(clocks, true); + } + } + pub fn release_cam_clock(self, clocks: &mut ClockTree) { + trace!("Releasing {:?}::CAM_CLOCK", self); + if decrement_reference_count(&mut clocks.lcd_cam_cam_clock_refcount[self as usize]) + { + trace!("Disabling {:?}::CAM_CLOCK", self); + crate::rtc_cntl::WakeLock::release(); + self.enable_cam_clock_impl(clocks, false); + match unwrap!(clocks.lcd_cam_cam_clock[self as usize]).sclk { + LcdCamCamClockSclk::XtalClk => release_xtal_clk(clocks), + LcdCamCamClockSclk::PllF160m => release_pll_f160m(clocks), + } + } + } + #[allow(unused_variables)] + pub fn cam_clock_config_frequency( + clocks: &mut ClockTree, + config: LcdCamCamClockConfig, + ) -> u32 { + (((match config.sclk { + LcdCamCamClockSclk::XtalClk => xtal_clk_frequency(), + LcdCamCamClockSclk::PllF160m => pll_f160m_frequency(), + } as u64) + * (config.div_a() as u64)) + / (((config.div_num() * config.div_a()) + config.div_b()) as u64)) + as u32 + } + pub fn cam_clock_frequency(self) -> u32 { + LCD_CAM_CAM_CLOCK_FREQ_CACHE[self as usize] + .load(::core::sync::atomic::Ordering::Acquire) + } + pub fn cam_clock_source_frequency(sclk: LcdCamCamClockSclk) -> u32 { + match sclk { + LcdCamCamClockSclk::XtalClk => xtal_clk_frequency(), + LcdCamCamClockSclk::PllF160m => pll_f160m_frequency(), + } + } + } impl RmtInstance { pub fn configure_sclk(self, clocks: &mut ClockTree, new_selector: RmtSclkConfig) { let old_selector = clocks.rmt_sclk[self as usize].replace(new_selector); @@ -3705,6 +4095,22 @@ macro_rules! define_clock_tree_types { ); } } + fn refresh_lcd_cam_lcd_clock_downstream(clocks: &mut ClockTree, instance: LcdCamInstance) { + if let Some(config) = clocks.lcd_cam_lcd_clock[instance as usize] { + LCD_CAM_LCD_CLOCK_FREQ_CACHE[instance as usize].store( + LcdCamInstance::lcd_clock_config_frequency(clocks, config), + ::core::sync::atomic::Ordering::Release, + ); + } + } + fn refresh_lcd_cam_cam_clock_downstream(clocks: &mut ClockTree, instance: LcdCamInstance) { + if let Some(config) = clocks.lcd_cam_cam_clock[instance as usize] { + LCD_CAM_CAM_CLOCK_FREQ_CACHE[instance as usize].store( + LcdCamInstance::cam_clock_config_frequency(clocks, config), + ::core::sync::atomic::Ordering::Release, + ); + } + } fn refresh_rmt_sclk_downstream(clocks: &mut ClockTree, instance: RmtInstance) { if let Some(config) = clocks.rmt_sclk[instance as usize] { RMT_SCLK_FREQ_CACHE[instance as usize].store( @@ -3798,6 +4204,8 @@ macro_rules! implement_peripheral_clocks { I2c0, /// I2C1 peripheral clock signal I2c1, + /// LCD_CAM peripheral clock signal + LcdCam, /// RMT peripheral clock signal Rmt, /// RSA peripheral clock signal @@ -3841,6 +4249,7 @@ macro_rules! implement_peripheral_clocks { Self::GpioSd, Self::I2c0, Self::I2c1, + Self::LcdCam, Self::Rmt, Self::Rsa, Self::SdioHost, @@ -3900,6 +4309,11 @@ macro_rules! implement_peripheral_clocks { .i2c_ctrl0(1) .modify(|_, w| w.apb_clk_en().bit(enable).clk_en().bit(enable)); } + Peripheral::LcdCam => { + crate::peripherals::HP_SYS_CLKRST::regs() + .lcdcam_ctrl0() + .modify(|_, w| w.sys_clk_en().bit(enable).apb_clk_en().bit(enable)); + } Peripheral::Rmt => { crate::peripherals::HP_SYS_CLKRST::regs() .rmt_ctrl0() @@ -4017,6 +4431,11 @@ macro_rules! implement_peripheral_clocks { .i2c_ctrl0(1) .modify(|_, w| w.rst_en().bit(reset)); } + Peripheral::LcdCam => { + crate::peripherals::HP_SYS_CLKRST::regs() + .lcdcam_ctrl0() + .modify(|_, w| w.apb_rst_en().bit(reset).rst_en().bit(reset)); + } Peripheral::Rmt => { crate::peripherals::HP_SYS_CLKRST::regs() .rmt_ctrl0() @@ -4578,6 +4997,9 @@ macro_rules! for_each_peripheral { _for_each_inner_peripheral!((@ peri_type #[doc = "I2C1 peripheral singleton"] I2C1 <= I2C1(I2C1 : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc = + "LCD_CAM peripheral singleton"] LCD_CAM <= LCD_CAM(LCD_CAM : { + bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt }) + (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc = "INTERRUPT_CORE0 peripheral singleton"] INTERRUPT_CORE0 <= INTERRUPT_CORE0() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc = "INTERRUPT_CORE1 peripheral singleton"] INTERRUPT_CORE1 <= INTERRUPT_CORE1() @@ -4734,6 +5156,7 @@ macro_rules! for_each_peripheral { _for_each_inner_peripheral!((HP_ALIVE_SYS(unstable))); _for_each_inner_peripheral!((HP_SYS_CLKRST(unstable))); _for_each_inner_peripheral!((I2C0)); _for_each_inner_peripheral!((I2C1)); + _for_each_inner_peripheral!((LCD_CAM(unstable))); _for_each_inner_peripheral!((INTERRUPT_CORE0(unstable))); _for_each_inner_peripheral!((INTERRUPT_CORE1(unstable))); _for_each_inner_peripheral!((IO_MUX(unstable))); @@ -4783,6 +5206,7 @@ macro_rules! for_each_peripheral { _for_each_inner_peripheral!((FROM_CPU_INTR2(unstable))); _for_each_inner_peripheral!((FROM_CPU_INTR3(unstable))); _for_each_inner_peripheral!((UHCI0, Uhci0, 0, AhbGdmaChannel)); + _for_each_inner_peripheral!((LCD_CAM, LcdCam, 0, AxiGdmaChannel)); _for_each_inner_peripheral!((SPI2, Spi2, 1, AxiGdmaChannel)); _for_each_inner_peripheral!((SPI3, Spi3, 2, AxiGdmaChannel)); _for_each_inner_peripheral!((AES, Aes, 4, AxiGdmaChannel)); @@ -5020,8 +5444,10 @@ macro_rules! for_each_peripheral { : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (@ peri_type #[doc = "I2C1 peripheral singleton"] I2C1 <= I2C1(I2C1 : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (@ - peri_type #[doc = "INTERRUPT_CORE0 peripheral singleton"] INTERRUPT_CORE0 <= - INTERRUPT_CORE0() (unstable)), (@ peri_type #[doc = + peri_type #[doc = "LCD_CAM peripheral singleton"] LCD_CAM <= LCD_CAM(LCD_CAM : { + bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt }) + (unstable)), (@ peri_type #[doc = "INTERRUPT_CORE0 peripheral singleton"] + INTERRUPT_CORE0 <= INTERRUPT_CORE0() (unstable)), (@ peri_type #[doc = "INTERRUPT_CORE1 peripheral singleton"] INTERRUPT_CORE1 <= INTERRUPT_CORE1() (unstable)), (@ peri_type #[doc = "IO_MUX peripheral singleton"] IO_MUX <= IO_MUX() (unstable)), (@ peri_type #[doc = "IOMUX_MSPI_PIN peripheral singleton"] @@ -5111,10 +5537,10 @@ macro_rules! for_each_peripheral { (CLIC(unstable)), (ECC(unstable)), (GPIO(unstable)), (GPIO_SD(unstable)), (HP_APM(unstable)), (HP_MEM_APM(unstable)), (HP_SYS(unstable)), (HP_ALIVE_SYS(unstable)), (HP_SYS_CLKRST(unstable)), (I2C0), (I2C1), - (INTERRUPT_CORE0(unstable)), (INTERRUPT_CORE1(unstable)), (IO_MUX(unstable)), - (LP_AON_CLK_RST(unstable)), (LP_APM(unstable)), (LP_GPIO(unstable)), - (LP_IO_MUX(unstable)), (LP_PERI(unstable)), (LP_SYS(unstable)), - (LP_TEE(unstable)), (LP_WDT(unstable)), (LPWR(unstable)), + (LCD_CAM(unstable)), (INTERRUPT_CORE0(unstable)), (INTERRUPT_CORE1(unstable)), + (IO_MUX(unstable)), (LP_AON_CLK_RST(unstable)), (LP_APM(unstable)), + (LP_GPIO(unstable)), (LP_IO_MUX(unstable)), (LP_PERI(unstable)), + (LP_SYS(unstable)), (LP_TEE(unstable)), (LP_WDT(unstable)), (LPWR(unstable)), (MEM_MONITOR(unstable)), (MODEM_LPCON(unstable)), (MODEM_SYSCON(unstable)), (PAU(unstable)), (PMU(unstable)), (RTC_TIMER(unstable)), (RNG(unstable)), (RMT(unstable)), (RSA(unstable)), (SPI0(unstable)), (SPI1(unstable)), (SPI2), @@ -5126,8 +5552,9 @@ macro_rules! for_each_peripheral { (GPIO_DEDICATED(unstable)), (CPU_CTRL(unstable)), (FROM_CPU_INTR0(unstable)), (FROM_CPU_INTR1(unstable)), (FROM_CPU_INTR2(unstable)), (FROM_CPU_INTR3(unstable)))); _for_each_inner_peripheral!((dma_eligible(UHCI0, - Uhci0, 0, AhbGdmaChannel), (SPI2, Spi2, 1, AxiGdmaChannel), (SPI3, Spi3, 2, - AxiGdmaChannel), (AES, Aes, 4, AxiGdmaChannel), (SHA, Sha, 5, AxiGdmaChannel))); + Uhci0, 0, AhbGdmaChannel), (LCD_CAM, LcdCam, 0, AxiGdmaChannel), (SPI2, Spi2, 1, + AxiGdmaChannel), (SPI3, Spi3, 2, AxiGdmaChannel), (AES, Aes, 4, AxiGdmaChannel), + (SHA, Sha, 5, AxiGdmaChannel))); }; } /// This macro can be used to generate code for each `GPIOn` instance. @@ -5163,42 +5590,40 @@ macro_rules! for_each_gpio { macro_rules! _for_each_inner_gpio { $(($pattern) => $code;)* ($other : tt) => {} } _for_each_inner_gpio!((0, GPIO0() () ([Input] [Output]))); _for_each_inner_gpio!((1, GPIO1() () ([Input] [Output]))); - _for_each_inner_gpio!((2, GPIO2(_3 => LCD_DATA19) (_3 => LCD_DATA19) ([Input] - [Output]))); _for_each_inner_gpio!((3, GPIO3(_3 => LCD_DATA20) (_3 => LCD_DATA20) - ([Input] [Output]))); _for_each_inner_gpio!((4, GPIO4(_3 => LCD_DATA21) (_3 => - LCD_DATA21) ([Input] [Output]))); _for_each_inner_gpio!((5, GPIO5(_3 => - LCD_DATA22) (_3 => LCD_DATA22) ([Input] [Output]))); _for_each_inner_gpio!((6, - GPIO6() () ([Input] [Output]))); _for_each_inner_gpio!((7, GPIO7(_3 => - LCD_DATA23) (_3 => LCD_DATA23) ([Input] [Output]))); _for_each_inner_gpio!((8, - GPIO8(_2 => GMAC_PHY_TXD0 _3 => LCD_DATA0) (_2 => GMAC_PHY_TXD0 _3 => LCD_DATA0) - ([Input] [Output]))); _for_each_inner_gpio!((9, GPIO9(_0 => FSPIHD _2 => - GMAC_PHY_TXD1 _3 => LCD_DATA1 _4 => DBG_PSRAM_CK) (_0 => FSPIHD _2 => - GMAC_PHY_TXD1 _3 => LCD_DATA1 _4 => DBG_PSRAM_CK) ([Input] [Output]))); - _for_each_inner_gpio!((10, GPIO10(_0 => FSPICS0 _2 => GMAC_PHY_TXD2 _3 => - LCD_DATA2 _4 => DBG_PSRAM_CS) (_0 => FSPICS0 _2 => GMAC_PHY_TXD2 _3 => LCD_DATA2 - _4 => DBG_PSRAM_CS) ([Input] [Output]))); _for_each_inner_gpio!((11, GPIO11(_0 => - FSPID _2 => GMAC_PHY_TXD3 _3 => LCD_DATA3 _4 => DBG_PSRAM_D) (_0 => FSPID _2 => - GMAC_PHY_TXD3 _3 => LCD_DATA3 _4 => DBG_PSRAM_D) ([Input] [Output]))); - _for_each_inner_gpio!((12, GPIO12(_0 => FSPICLK _2 => GMAC_PHY_TXEN _3 => - LCD_DATA4 _4 => DBG_PSRAM_Q) (_0 => FSPICLK _2 => GMAC_PHY_TXEN _3 => LCD_DATA4 - _4 => DBG_PSRAM_Q) ([Input] [Output]))); _for_each_inner_gpio!((13, GPIO13(_0 => - FSPIQ _2 => GMAC_RMII_CLK _3 => LCD_DATA5 _4 => DBG_PSRAM_WP) (_0 => FSPIQ _2 => - GMAC_RMII_CLK _3 => LCD_DATA5 _4 => DBG_PSRAM_WP) ([Input] [Output]))); - _for_each_inner_gpio!((14, GPIO14(_0 => FSPIWP _2 => GMAC_RX_CLK _3 => LCD_DATA6 - _4 => DBG_PSRAM_HOLD) (_0 => FSPIWP _2 => GMAC_RX_CLK _3 => LCD_DATA6 _4 => + _for_each_inner_gpio!((2, GPIO2() (_3 => LCD_DATA_19) ([Input] [Output]))); + _for_each_inner_gpio!((3, GPIO3() (_3 => LCD_DATA_20) ([Input] [Output]))); + _for_each_inner_gpio!((4, GPIO4() (_3 => LCD_DATA_21) ([Input] [Output]))); + _for_each_inner_gpio!((5, GPIO5() (_3 => LCD_DATA_22) ([Input] [Output]))); + _for_each_inner_gpio!((6, GPIO6() () ([Input] [Output]))); + _for_each_inner_gpio!((7, GPIO7() (_3 => LCD_DATA_23) ([Input] [Output]))); + _for_each_inner_gpio!((8, GPIO8(_2 => GMAC_PHY_TXD0) (_2 => GMAC_PHY_TXD0 _3 => + LCD_DATA_0) ([Input] [Output]))); _for_each_inner_gpio!((9, GPIO9(_0 => FSPIHD _2 + => GMAC_PHY_TXD1 _4 => DBG_PSRAM_CK) (_0 => FSPIHD _2 => GMAC_PHY_TXD1 _3 => + LCD_DATA_1 _4 => DBG_PSRAM_CK) ([Input] [Output]))); _for_each_inner_gpio!((10, + GPIO10(_0 => FSPICS0 _2 => GMAC_PHY_TXD2 _4 => DBG_PSRAM_CS) (_0 => FSPICS0 _2 => + GMAC_PHY_TXD2 _3 => LCD_DATA_2 _4 => DBG_PSRAM_CS) ([Input] [Output]))); + _for_each_inner_gpio!((11, GPIO11(_0 => FSPID _2 => GMAC_PHY_TXD3 _4 => + DBG_PSRAM_D) (_0 => FSPID _2 => GMAC_PHY_TXD3 _3 => LCD_DATA_3 _4 => DBG_PSRAM_D) + ([Input] [Output]))); _for_each_inner_gpio!((12, GPIO12(_0 => FSPICLK _2 => + GMAC_PHY_TXEN _4 => DBG_PSRAM_Q) (_0 => FSPICLK _2 => GMAC_PHY_TXEN _3 => + LCD_DATA_4 _4 => DBG_PSRAM_Q) ([Input] [Output]))); _for_each_inner_gpio!((13, + GPIO13(_0 => FSPIQ _2 => GMAC_RMII_CLK _4 => DBG_PSRAM_WP) (_0 => FSPIQ _2 => + GMAC_RMII_CLK _3 => LCD_DATA_5 _4 => DBG_PSRAM_WP) ([Input] [Output]))); + _for_each_inner_gpio!((14, GPIO14(_0 => FSPIWP _2 => GMAC_RX_CLK _4 => + DBG_PSRAM_HOLD) (_0 => FSPIWP _2 => GMAC_RX_CLK _3 => LCD_DATA_6 _4 => DBG_PSRAM_HOLD) ([Input] [Output]))); _for_each_inner_gpio!((15, GPIO15(_0 => - FSPIIO4 _2 => GMAC_PHY_RXDV _3 => LCD_DATA7 _4 => DBG_PSRAM_DQ4) (_0 => FSPIIO4 - _2 => GMAC_PHY_RXDV _3 => LCD_DATA7 _4 => DBG_PSRAM_DQ4) ([Input] [Output]))); - _for_each_inner_gpio!((16, GPIO16(_0 => FSPIIO5 _2 => GMAC_PHY_RXD3 _3 => - LCD_DATA8 _4 => DBG_PSRAM_DQ5) (_0 => FSPIIO5 _2 => GMAC_PHY_RXD3 _3 => LCD_DATA8 - _4 => DBG_PSRAM_DQ5) ([Input] [Output]))); _for_each_inner_gpio!((17, GPIO17(_0 - => FSPIIO6 _2 => GMAC_PHY_RXD2 _3 => LCD_DATA9 _4 => DBG_PSRAM_DQ6) (_0 => - FSPIIO6 _2 => GMAC_PHY_RXD2 _3 => LCD_DATA9 _4 => DBG_PSRAM_DQ6) ([Input] - [Output]))); _for_each_inner_gpio!((18, GPIO18(_0 => FSPIIO7 _2 => GMAC_PHY_RXD1 - _3 => LCD_DATA10 _4 => DBG_PSRAM_DQ7) (_0 => FSPIIO7 _2 => GMAC_PHY_RXD1 _3 => - LCD_DATA10 _4 => DBG_PSRAM_DQ7) ([Input] [Output]))); _for_each_inner_gpio!((19, - GPIO19(_2 => GMAC_PHY_RXD0 _3 => LCD_DATA11 _4 => DBG_PSRAM_DQS_0) (_0 => FSPIDQS - _2 => GMAC_PHY_RXD0 _3 => LCD_DATA11 _4 => DBG_PSRAM_DQS_0) ([Input] [Output]))); + FSPIIO4 _2 => GMAC_PHY_RXDV _4 => DBG_PSRAM_DQ4) (_0 => FSPIIO4 _2 => + GMAC_PHY_RXDV _3 => LCD_DATA_7 _4 => DBG_PSRAM_DQ4) ([Input] [Output]))); + _for_each_inner_gpio!((16, GPIO16(_0 => FSPIIO5 _2 => GMAC_PHY_RXD3 _4 => + DBG_PSRAM_DQ5) (_0 => FSPIIO5 _2 => GMAC_PHY_RXD3 _3 => LCD_DATA_8 _4 => + DBG_PSRAM_DQ5) ([Input] [Output]))); _for_each_inner_gpio!((17, GPIO17(_0 => + FSPIIO6 _2 => GMAC_PHY_RXD2 _4 => DBG_PSRAM_DQ6) (_0 => FSPIIO6 _2 => + GMAC_PHY_RXD2 _3 => LCD_DATA_9 _4 => DBG_PSRAM_DQ6) ([Input] [Output]))); + _for_each_inner_gpio!((18, GPIO18(_0 => FSPIIO7 _2 => GMAC_PHY_RXD1 _4 => + DBG_PSRAM_DQ7) (_0 => FSPIIO7 _2 => GMAC_PHY_RXD1 _3 => LCD_DATA_10 _4 => + DBG_PSRAM_DQ7) ([Input] [Output]))); _for_each_inner_gpio!((19, GPIO19(_2 => + GMAC_PHY_RXD0 _4 => DBG_PSRAM_DQS_0) (_0 => FSPIDQS _2 => GMAC_PHY_RXD0 _3 => + LCD_DATA_11 _4 => DBG_PSRAM_DQS_0) ([Input] [Output]))); _for_each_inner_gpio!((20, GPIO20(_0 => SD1_DATA0 _2 => FSPICLK _4 => DBG_FLASH_CK) (_0 => SD1_DATA0 _2 => FSPICLK _4 => DBG_FLASH_CK) ([Input] [Output]))); _for_each_inner_gpio!((21, GPIO21(_0 => SD1_DATA1 _2 => FSPID _4 => @@ -5217,133 +5642,121 @@ macro_rules! for_each_gpio { SPIWP) ([Input] [Output]))); _for_each_inner_gpio!((30, GPIO30(_0 => SPIHD) (_0 => SPIHD) ([Input] [Output]))); _for_each_inner_gpio!((31, GPIO31(_0 => SPICLK) (_0 => SPICLK) ([Input] [Output]))); _for_each_inner_gpio!((32, GPIO32(_0 => - SPID) (_0 => SPID) ([Input] [Output]))); _for_each_inner_gpio!((33, GPIO33(_3 => - LCD_DATA12) (_3 => LCD_DATA12) ([Input] [Output]))); _for_each_inner_gpio!((34, - GPIO34(_3 => LCD_DATA13) (_3 => LCD_DATA13) ([Input] [Output]))); - _for_each_inner_gpio!((35, GPIO35(_2 => REF_GMAC_CLK _3 => LCD_DATA14 _4 => - SD2_CDATA0) (_2 => REF_GMAC_CLK _3 => LCD_DATA14 _4 => SD2_CDATA0) ([Input] - [Output]))); _for_each_inner_gpio!((36, GPIO36(_2 => GMAC_PHY_RXDV _3 => - LCD_DATA15 _4 => SD2_CDATA1) (_2 => GMAC_PHY_RXDV _3 => LCD_DATA15 _4 => + SPID) (_0 => SPID) ([Input] [Output]))); _for_each_inner_gpio!((33, GPIO33() (_3 + => LCD_DATA_12) ([Input] [Output]))); _for_each_inner_gpio!((34, GPIO34() (_3 => + LCD_DATA_13) ([Input] [Output]))); _for_each_inner_gpio!((35, GPIO35(_2 => + REF_GMAC_CLK _4 => SD2_CDATA0) (_2 => REF_GMAC_CLK _3 => LCD_DATA_14 _4 => + SD2_CDATA0) ([Input] [Output]))); _for_each_inner_gpio!((36, GPIO36(_2 => + GMAC_PHY_RXDV _4 => SD2_CDATA1) (_2 => GMAC_PHY_RXDV _3 => LCD_DATA_15 _4 => SD2_CDATA1) ([Input] [Output]))); _for_each_inner_gpio!((37, GPIO37(_2 => - GMAC_PHY_TXEN _3 => LCD_DATA16 _4 => SD2_CDATA2) (_2 => GMAC_PHY_TXEN _3 => - LCD_DATA16 _4 => SD2_CDATA2) ([Input] [Output]))); _for_each_inner_gpio!((38, - GPIO38(_2 => GMAC_PHY_RXD3 _3 => LCD_DATA17 _4 => SD2_CDATA3) (_2 => - GMAC_PHY_RXD3 _3 => LCD_DATA17 _4 => SD2_CDATA3) ([Input] [Output]))); - _for_each_inner_gpio!((39, GPIO39(_2 => GMAC_PHY_RXD2 _3 => LCD_DATA18 _4 => - SD2_CCLK) (_2 => GMAC_PHY_RXD2 _3 => LCD_DATA18 _4 => SD2_CCLK) ([Input] - [Output]))); _for_each_inner_gpio!((40, GPIO40(_2 => GMAC_PHY_RXD1 _3 => LCD_PCLK - _4 => SD2_CCMD) (_2 => GMAC_PHY_RXD1 _3 => LCD_PCLK _4 => SD2_CCMD) ([Input] - [Output]))); _for_each_inner_gpio!((42, GPIO42(_2 => GMAC_RX_CLK) (_2 => + GMAC_PHY_TXEN _4 => SD2_CDATA2) (_2 => GMAC_PHY_TXEN _3 => LCD_DATA_16 _4 => + SD2_CDATA2) ([Input] [Output]))); _for_each_inner_gpio!((38, GPIO38(_2 => + GMAC_PHY_RXD3 _4 => SD2_CDATA3) (_2 => GMAC_PHY_RXD3 _3 => LCD_DATA_17 _4 => + SD2_CDATA3) ([Input] [Output]))); _for_each_inner_gpio!((39, GPIO39(_2 => + GMAC_PHY_RXD2 _4 => SD2_CCLK) (_2 => GMAC_PHY_RXD2 _3 => LCD_DATA_18 _4 => + SD2_CCLK) ([Input] [Output]))); _for_each_inner_gpio!((40, GPIO40(_2 => + GMAC_PHY_RXD1 _4 => SD2_CCMD) (_2 => GMAC_PHY_RXD1 _3 => LCD_PCLK _4 => SD2_CCMD) + ([Input] [Output]))); _for_each_inner_gpio!((42, GPIO42(_2 => GMAC_RX_CLK) (_2 => GMAC_RX_CLK) ([Input] [Output]))); _for_each_inner_gpio!((43, GPIO43(_2 => - GMAC_RMII_CLK _3 => LCD_H_ENABLE) (_2 => GMAC_RMII_CLK _3 => LCD_H_ENABLE) - ([Input] [Output]))); _for_each_inner_gpio!((44, GPIO44(_2 => GMAC_PHY_TXD0 _3 => - LCD_H_SYNC) (_2 => GMAC_PHY_TXD0 _3 => LCD_H_SYNC) ([Input] [Output]))); - _for_each_inner_gpio!((45, GPIO45(_2 => GMAC_PHY_TXD1 _3 => LCD_V_SYNC) (_2 => - GMAC_PHY_TXD1 _3 => LCD_V_SYNC) ([Input] [Output]))); _for_each_inner_gpio!((46, - GPIO46(_2 => GMAC_PHY_TXD2 _3 => CAM_DATA0) (_2 => GMAC_PHY_TXD2 _3 => CAM_DATA0) - ([Input] [Output]))); _for_each_inner_gpio!((47, GPIO47(_2 => GMAC_PHY_TXD3 _3 => - CAM_DATA1) (_2 => GMAC_PHY_TXD3 _3 => CAM_DATA1) ([Input] [Output]))); - _for_each_inner_gpio!((48, GPIO48(_3 => CAM_DATA2) (_3 => CAM_DATA2) ([Input] - [Output]))); _for_each_inner_gpio!((49, GPIO49(_3 => CAM_DATA3) (_3 => CAM_DATA3) - ([Input] [Output]))); _for_each_inner_gpio!((50, GPIO50(_3 => CAM_DATA4) (_3 => - CAM_DATA4) ([Input] [Output]))); _for_each_inner_gpio!((51, GPIO51(_3 => - CAM_DATA5) (_3 => CAM_DATA5) ([Input] [Output]))); _for_each_inner_gpio!((52, - GPIO52(_2 => FSPICS0 _3 => CAM_DATA6) (_2 => FSPICS0 _3 => CAM_DATA6) ([Input] - [Output]))); _for_each_inner_gpio!((53, GPIO53(_2 => FSPICLK _3 => CAM_DATA7) (_2 - => FSPICLK _3 => CAM_DATA7) ([Input] [Output]))); _for_each_inner_gpio!((54, - GPIO54(_0 => MTDO _2 => FSPID _3 => CAM_PCLK) (_0 => MTDO _2 => FSPID _3 => - CAM_PCLK) ([Input] [Output]))); _for_each_inner_gpio!((55, GPIO55(_0 => MTCK _2 - => FSPIQ _3 => CAM_XCLK) (_0 => MTCK _2 => FSPIQ _3 => CAM_XCLK) ([Input] - [Output]))); _for_each_inner_gpio!((56, GPIO56(_0 => MTDI _2 => FSPIHD _3 => - CAM_V_SYNC) (_0 => MTDI _2 => FSPIHD _3 => CAM_V_SYNC) ([Input] [Output]))); - _for_each_inner_gpio!((57, GPIO57(_0 => MTMS _2 => FSPIWP _3 => CAM_H_SYNC) (_0 - => MTMS _2 => FSPIWP _3 => CAM_H_SYNC) ([Input] [Output]))); - _for_each_inner_gpio!((58, GPIO58() (_0 => U0TXD) ([Input] [Output]))); - _for_each_inner_gpio!((59, GPIO59(_0 => U0RXD) () ([Input] [Output]))); - _for_each_inner_gpio!((60, GPIO60() () ([Input] [Output]))); + GMAC_RMII_CLK) (_2 => GMAC_RMII_CLK _3 => LCD_H_ENABLE) ([Input] [Output]))); + _for_each_inner_gpio!((44, GPIO44(_2 => GMAC_PHY_TXD0) (_2 => GMAC_PHY_TXD0 _3 => + LCD_H_SYNC) ([Input] [Output]))); _for_each_inner_gpio!((45, GPIO45(_2 => + GMAC_PHY_TXD1) (_2 => GMAC_PHY_TXD1 _3 => LCD_V_SYNC) ([Input] [Output]))); + _for_each_inner_gpio!((46, GPIO46(_2 => GMAC_PHY_TXD2 _3 => CAM_DATA_0) (_2 => + GMAC_PHY_TXD2) ([Input] [Output]))); _for_each_inner_gpio!((47, GPIO47(_2 => + GMAC_PHY_TXD3 _3 => CAM_DATA_1) (_2 => GMAC_PHY_TXD3) ([Input] [Output]))); + _for_each_inner_gpio!((48, GPIO48(_3 => CAM_DATA_2) () ([Input] [Output]))); + _for_each_inner_gpio!((49, GPIO49(_3 => CAM_DATA_3) () ([Input] [Output]))); + _for_each_inner_gpio!((50, GPIO50(_3 => CAM_DATA_4) () ([Input] [Output]))); + _for_each_inner_gpio!((51, GPIO51(_3 => CAM_DATA_5) () ([Input] [Output]))); + _for_each_inner_gpio!((52, GPIO52(_2 => FSPICS0 _3 => CAM_DATA_6) (_2 => FSPICS0) + ([Input] [Output]))); _for_each_inner_gpio!((53, GPIO53(_2 => FSPICLK _3 => + CAM_DATA_7) (_2 => FSPICLK) ([Input] [Output]))); _for_each_inner_gpio!((54, + GPIO54(_0 => MTDO _2 => FSPID _3 => CAM_PCLK) (_0 => MTDO _2 => FSPID) ([Input] + [Output]))); _for_each_inner_gpio!((55, GPIO55(_0 => MTCK _2 => FSPIQ _3 => + CAM_XCLK) (_0 => MTCK _2 => FSPIQ _3 => CAM_XCLK) ([Input] [Output]))); + _for_each_inner_gpio!((56, GPIO56(_0 => MTDI _2 => FSPIHD _3 => CAM_V_SYNC) (_0 + => MTDI _2 => FSPIHD) ([Input] [Output]))); _for_each_inner_gpio!((57, GPIO57(_0 + => MTMS _2 => FSPIWP _3 => CAM_H_SYNC) (_0 => MTMS _2 => FSPIWP) ([Input] + [Output]))); _for_each_inner_gpio!((58, GPIO58() (_0 => U0TXD) ([Input] + [Output]))); _for_each_inner_gpio!((59, GPIO59(_0 => U0RXD) () ([Input] + [Output]))); _for_each_inner_gpio!((60, GPIO60() () ([Input] [Output]))); _for_each_inner_gpio!((61, GPIO61() () ([Input] [Output]))); _for_each_inner_gpio!((all(0, GPIO0() () ([Input] [Output])), (1, GPIO1() () - ([Input] [Output])), (2, GPIO2(_3 => LCD_DATA19) (_3 => LCD_DATA19) ([Input] - [Output])), (3, GPIO3(_3 => LCD_DATA20) (_3 => LCD_DATA20) ([Input] [Output])), - (4, GPIO4(_3 => LCD_DATA21) (_3 => LCD_DATA21) ([Input] [Output])), (5, GPIO5(_3 - => LCD_DATA22) (_3 => LCD_DATA22) ([Input] [Output])), (6, GPIO6() () ([Input] - [Output])), (7, GPIO7(_3 => LCD_DATA23) (_3 => LCD_DATA23) ([Input] [Output])), - (8, GPIO8(_2 => GMAC_PHY_TXD0 _3 => LCD_DATA0) (_2 => GMAC_PHY_TXD0 _3 => - LCD_DATA0) ([Input] [Output])), (9, GPIO9(_0 => FSPIHD _2 => GMAC_PHY_TXD1 _3 => - LCD_DATA1 _4 => DBG_PSRAM_CK) (_0 => FSPIHD _2 => GMAC_PHY_TXD1 _3 => LCD_DATA1 - _4 => DBG_PSRAM_CK) ([Input] [Output])), (10, GPIO10(_0 => FSPICS0 _2 => - GMAC_PHY_TXD2 _3 => LCD_DATA2 _4 => DBG_PSRAM_CS) (_0 => FSPICS0 _2 => - GMAC_PHY_TXD2 _3 => LCD_DATA2 _4 => DBG_PSRAM_CS) ([Input] [Output])), (11, - GPIO11(_0 => FSPID _2 => GMAC_PHY_TXD3 _3 => LCD_DATA3 _4 => DBG_PSRAM_D) (_0 => - FSPID _2 => GMAC_PHY_TXD3 _3 => LCD_DATA3 _4 => DBG_PSRAM_D) ([Input] [Output])), - (12, GPIO12(_0 => FSPICLK _2 => GMAC_PHY_TXEN _3 => LCD_DATA4 _4 => DBG_PSRAM_Q) - (_0 => FSPICLK _2 => GMAC_PHY_TXEN _3 => LCD_DATA4 _4 => DBG_PSRAM_Q) ([Input] - [Output])), (13, GPIO13(_0 => FSPIQ _2 => GMAC_RMII_CLK _3 => LCD_DATA5 _4 => - DBG_PSRAM_WP) (_0 => FSPIQ _2 => GMAC_RMII_CLK _3 => LCD_DATA5 _4 => - DBG_PSRAM_WP) ([Input] [Output])), (14, GPIO14(_0 => FSPIWP _2 => GMAC_RX_CLK _3 - => LCD_DATA6 _4 => DBG_PSRAM_HOLD) (_0 => FSPIWP _2 => GMAC_RX_CLK _3 => - LCD_DATA6 _4 => DBG_PSRAM_HOLD) ([Input] [Output])), (15, GPIO15(_0 => FSPIIO4 _2 - => GMAC_PHY_RXDV _3 => LCD_DATA7 _4 => DBG_PSRAM_DQ4) (_0 => FSPIIO4 _2 => - GMAC_PHY_RXDV _3 => LCD_DATA7 _4 => DBG_PSRAM_DQ4) ([Input] [Output])), (16, - GPIO16(_0 => FSPIIO5 _2 => GMAC_PHY_RXD3 _3 => LCD_DATA8 _4 => DBG_PSRAM_DQ5) (_0 - => FSPIIO5 _2 => GMAC_PHY_RXD3 _3 => LCD_DATA8 _4 => DBG_PSRAM_DQ5) ([Input] - [Output])), (17, GPIO17(_0 => FSPIIO6 _2 => GMAC_PHY_RXD2 _3 => LCD_DATA9 _4 => - DBG_PSRAM_DQ6) (_0 => FSPIIO6 _2 => GMAC_PHY_RXD2 _3 => LCD_DATA9 _4 => - DBG_PSRAM_DQ6) ([Input] [Output])), (18, GPIO18(_0 => FSPIIO7 _2 => GMAC_PHY_RXD1 - _3 => LCD_DATA10 _4 => DBG_PSRAM_DQ7) (_0 => FSPIIO7 _2 => GMAC_PHY_RXD1 _3 => - LCD_DATA10 _4 => DBG_PSRAM_DQ7) ([Input] [Output])), (19, GPIO19(_2 => - GMAC_PHY_RXD0 _3 => LCD_DATA11 _4 => DBG_PSRAM_DQS_0) (_0 => FSPIDQS _2 => - GMAC_PHY_RXD0 _3 => LCD_DATA11 _4 => DBG_PSRAM_DQS_0) ([Input] [Output])), (20, - GPIO20(_0 => SD1_DATA0 _2 => FSPICLK _4 => DBG_FLASH_CK) (_0 => SD1_DATA0 _2 => - FSPICLK _4 => DBG_FLASH_CK) ([Input] [Output])), (21, GPIO21(_0 => SD1_DATA1 _2 - => FSPID _4 => DBG_FLASH_D) (_0 => SD1_DATA1 _2 => FSPID _4 => DBG_FLASH_D) - ([Input] [Output])), (22, GPIO22(_0 => SD1_DATA2 _2 => FSPIQ _4 => DBG_FLASH_CS) - (_0 => SD1_DATA2 _2 => FSPIQ _4 => DBG_FLASH_CS) ([Input] [Output])), (23, - GPIO23(_0 => SD1_DATA3 _2 => FSPICS0 _4 => DBG_FLASH_Q) (_0 => SD1_DATA3 _2 => - FSPICS0 _4 => DBG_FLASH_Q) ([Input] [Output])), (24, GPIO24(_0 => SD1_CLK _2 => - FSPIHD _4 => DBG_FLASH_WP) (_0 => SD1_CLK _2 => FSPIHD _4 => DBG_FLASH_WP) - ([Input] [Output])), (25, GPIO25(_0 => SD1_CMD _2 => FSPIWP _4 => DBG_FLASH_HOLD) - (_0 => SD1_CMD _2 => FSPIWP _4 => DBG_FLASH_HOLD) ([Input] [Output])), (26, - GPIO26(_0 => SPICS0) (_0 => SPICS0) ([Input] [Output])), (27, GPIO27(_0 => SPIQ) - (_0 => SPIQ) ([Input] [Output])), (28, GPIO28(_0 => SPIWP) (_0 => SPIWP) ([Input] - [Output])), (30, GPIO30(_0 => SPIHD) (_0 => SPIHD) ([Input] [Output])), (31, - GPIO31(_0 => SPICLK) (_0 => SPICLK) ([Input] [Output])), (32, GPIO32(_0 => SPID) - (_0 => SPID) ([Input] [Output])), (33, GPIO33(_3 => LCD_DATA12) (_3 => - LCD_DATA12) ([Input] [Output])), (34, GPIO34(_3 => LCD_DATA13) (_3 => LCD_DATA13) - ([Input] [Output])), (35, GPIO35(_2 => REF_GMAC_CLK _3 => LCD_DATA14 _4 => - SD2_CDATA0) (_2 => REF_GMAC_CLK _3 => LCD_DATA14 _4 => SD2_CDATA0) ([Input] - [Output])), (36, GPIO36(_2 => GMAC_PHY_RXDV _3 => LCD_DATA15 _4 => SD2_CDATA1) - (_2 => GMAC_PHY_RXDV _3 => LCD_DATA15 _4 => SD2_CDATA1) ([Input] [Output])), (37, - GPIO37(_2 => GMAC_PHY_TXEN _3 => LCD_DATA16 _4 => SD2_CDATA2) (_2 => - GMAC_PHY_TXEN _3 => LCD_DATA16 _4 => SD2_CDATA2) ([Input] [Output])), (38, - GPIO38(_2 => GMAC_PHY_RXD3 _3 => LCD_DATA17 _4 => SD2_CDATA3) (_2 => - GMAC_PHY_RXD3 _3 => LCD_DATA17 _4 => SD2_CDATA3) ([Input] [Output])), (39, - GPIO39(_2 => GMAC_PHY_RXD2 _3 => LCD_DATA18 _4 => SD2_CCLK) (_2 => GMAC_PHY_RXD2 - _3 => LCD_DATA18 _4 => SD2_CCLK) ([Input] [Output])), (40, GPIO40(_2 => - GMAC_PHY_RXD1 _3 => LCD_PCLK _4 => SD2_CCMD) (_2 => GMAC_PHY_RXD1 _3 => LCD_PCLK - _4 => SD2_CCMD) ([Input] [Output])), (42, GPIO42(_2 => GMAC_RX_CLK) (_2 => - GMAC_RX_CLK) ([Input] [Output])), (43, GPIO43(_2 => GMAC_RMII_CLK _3 => - LCD_H_ENABLE) (_2 => GMAC_RMII_CLK _3 => LCD_H_ENABLE) ([Input] [Output])), (44, - GPIO44(_2 => GMAC_PHY_TXD0 _3 => LCD_H_SYNC) (_2 => GMAC_PHY_TXD0 _3 => - LCD_H_SYNC) ([Input] [Output])), (45, GPIO45(_2 => GMAC_PHY_TXD1 _3 => - LCD_V_SYNC) (_2 => GMAC_PHY_TXD1 _3 => LCD_V_SYNC) ([Input] [Output])), (46, - GPIO46(_2 => GMAC_PHY_TXD2 _3 => CAM_DATA0) (_2 => GMAC_PHY_TXD2 _3 => CAM_DATA0) - ([Input] [Output])), (47, GPIO47(_2 => GMAC_PHY_TXD3 _3 => CAM_DATA1) (_2 => - GMAC_PHY_TXD3 _3 => CAM_DATA1) ([Input] [Output])), (48, GPIO48(_3 => CAM_DATA2) - (_3 => CAM_DATA2) ([Input] [Output])), (49, GPIO49(_3 => CAM_DATA3) (_3 => - CAM_DATA3) ([Input] [Output])), (50, GPIO50(_3 => CAM_DATA4) (_3 => CAM_DATA4) - ([Input] [Output])), (51, GPIO51(_3 => CAM_DATA5) (_3 => CAM_DATA5) ([Input] - [Output])), (52, GPIO52(_2 => FSPICS0 _3 => CAM_DATA6) (_2 => FSPICS0 _3 => - CAM_DATA6) ([Input] [Output])), (53, GPIO53(_2 => FSPICLK _3 => CAM_DATA7) (_2 => - FSPICLK _3 => CAM_DATA7) ([Input] [Output])), (54, GPIO54(_0 => MTDO _2 => FSPID - _3 => CAM_PCLK) (_0 => MTDO _2 => FSPID _3 => CAM_PCLK) ([Input] [Output])), (55, + ([Input] [Output])), (2, GPIO2() (_3 => LCD_DATA_19) ([Input] [Output])), (3, + GPIO3() (_3 => LCD_DATA_20) ([Input] [Output])), (4, GPIO4() (_3 => LCD_DATA_21) + ([Input] [Output])), (5, GPIO5() (_3 => LCD_DATA_22) ([Input] [Output])), (6, + GPIO6() () ([Input] [Output])), (7, GPIO7() (_3 => LCD_DATA_23) ([Input] + [Output])), (8, GPIO8(_2 => GMAC_PHY_TXD0) (_2 => GMAC_PHY_TXD0 _3 => LCD_DATA_0) + ([Input] [Output])), (9, GPIO9(_0 => FSPIHD _2 => GMAC_PHY_TXD1 _4 => + DBG_PSRAM_CK) (_0 => FSPIHD _2 => GMAC_PHY_TXD1 _3 => LCD_DATA_1 _4 => + DBG_PSRAM_CK) ([Input] [Output])), (10, GPIO10(_0 => FSPICS0 _2 => GMAC_PHY_TXD2 + _4 => DBG_PSRAM_CS) (_0 => FSPICS0 _2 => GMAC_PHY_TXD2 _3 => LCD_DATA_2 _4 => + DBG_PSRAM_CS) ([Input] [Output])), (11, GPIO11(_0 => FSPID _2 => GMAC_PHY_TXD3 _4 + => DBG_PSRAM_D) (_0 => FSPID _2 => GMAC_PHY_TXD3 _3 => LCD_DATA_3 _4 => + DBG_PSRAM_D) ([Input] [Output])), (12, GPIO12(_0 => FSPICLK _2 => GMAC_PHY_TXEN + _4 => DBG_PSRAM_Q) (_0 => FSPICLK _2 => GMAC_PHY_TXEN _3 => LCD_DATA_4 _4 => + DBG_PSRAM_Q) ([Input] [Output])), (13, GPIO13(_0 => FSPIQ _2 => GMAC_RMII_CLK _4 + => DBG_PSRAM_WP) (_0 => FSPIQ _2 => GMAC_RMII_CLK _3 => LCD_DATA_5 _4 => + DBG_PSRAM_WP) ([Input] [Output])), (14, GPIO14(_0 => FSPIWP _2 => GMAC_RX_CLK _4 + => DBG_PSRAM_HOLD) (_0 => FSPIWP _2 => GMAC_RX_CLK _3 => LCD_DATA_6 _4 => + DBG_PSRAM_HOLD) ([Input] [Output])), (15, GPIO15(_0 => FSPIIO4 _2 => + GMAC_PHY_RXDV _4 => DBG_PSRAM_DQ4) (_0 => FSPIIO4 _2 => GMAC_PHY_RXDV _3 => + LCD_DATA_7 _4 => DBG_PSRAM_DQ4) ([Input] [Output])), (16, GPIO16(_0 => FSPIIO5 _2 + => GMAC_PHY_RXD3 _4 => DBG_PSRAM_DQ5) (_0 => FSPIIO5 _2 => GMAC_PHY_RXD3 _3 => + LCD_DATA_8 _4 => DBG_PSRAM_DQ5) ([Input] [Output])), (17, GPIO17(_0 => FSPIIO6 _2 + => GMAC_PHY_RXD2 _4 => DBG_PSRAM_DQ6) (_0 => FSPIIO6 _2 => GMAC_PHY_RXD2 _3 => + LCD_DATA_9 _4 => DBG_PSRAM_DQ6) ([Input] [Output])), (18, GPIO18(_0 => FSPIIO7 _2 + => GMAC_PHY_RXD1 _4 => DBG_PSRAM_DQ7) (_0 => FSPIIO7 _2 => GMAC_PHY_RXD1 _3 => + LCD_DATA_10 _4 => DBG_PSRAM_DQ7) ([Input] [Output])), (19, GPIO19(_2 => + GMAC_PHY_RXD0 _4 => DBG_PSRAM_DQS_0) (_0 => FSPIDQS _2 => GMAC_PHY_RXD0 _3 => + LCD_DATA_11 _4 => DBG_PSRAM_DQS_0) ([Input] [Output])), (20, GPIO20(_0 => + SD1_DATA0 _2 => FSPICLK _4 => DBG_FLASH_CK) (_0 => SD1_DATA0 _2 => FSPICLK _4 => + DBG_FLASH_CK) ([Input] [Output])), (21, GPIO21(_0 => SD1_DATA1 _2 => FSPID _4 => + DBG_FLASH_D) (_0 => SD1_DATA1 _2 => FSPID _4 => DBG_FLASH_D) ([Input] [Output])), + (22, GPIO22(_0 => SD1_DATA2 _2 => FSPIQ _4 => DBG_FLASH_CS) (_0 => SD1_DATA2 _2 + => FSPIQ _4 => DBG_FLASH_CS) ([Input] [Output])), (23, GPIO23(_0 => SD1_DATA3 _2 + => FSPICS0 _4 => DBG_FLASH_Q) (_0 => SD1_DATA3 _2 => FSPICS0 _4 => DBG_FLASH_Q) + ([Input] [Output])), (24, GPIO24(_0 => SD1_CLK _2 => FSPIHD _4 => DBG_FLASH_WP) + (_0 => SD1_CLK _2 => FSPIHD _4 => DBG_FLASH_WP) ([Input] [Output])), (25, + GPIO25(_0 => SD1_CMD _2 => FSPIWP _4 => DBG_FLASH_HOLD) (_0 => SD1_CMD _2 => + FSPIWP _4 => DBG_FLASH_HOLD) ([Input] [Output])), (26, GPIO26(_0 => SPICS0) (_0 + => SPICS0) ([Input] [Output])), (27, GPIO27(_0 => SPIQ) (_0 => SPIQ) ([Input] + [Output])), (28, GPIO28(_0 => SPIWP) (_0 => SPIWP) ([Input] [Output])), (30, + GPIO30(_0 => SPIHD) (_0 => SPIHD) ([Input] [Output])), (31, GPIO31(_0 => SPICLK) + (_0 => SPICLK) ([Input] [Output])), (32, GPIO32(_0 => SPID) (_0 => SPID) ([Input] + [Output])), (33, GPIO33() (_3 => LCD_DATA_12) ([Input] [Output])), (34, GPIO34() + (_3 => LCD_DATA_13) ([Input] [Output])), (35, GPIO35(_2 => REF_GMAC_CLK _4 => + SD2_CDATA0) (_2 => REF_GMAC_CLK _3 => LCD_DATA_14 _4 => SD2_CDATA0) ([Input] + [Output])), (36, GPIO36(_2 => GMAC_PHY_RXDV _4 => SD2_CDATA1) (_2 => + GMAC_PHY_RXDV _3 => LCD_DATA_15 _4 => SD2_CDATA1) ([Input] [Output])), (37, + GPIO37(_2 => GMAC_PHY_TXEN _4 => SD2_CDATA2) (_2 => GMAC_PHY_TXEN _3 => + LCD_DATA_16 _4 => SD2_CDATA2) ([Input] [Output])), (38, GPIO38(_2 => + GMAC_PHY_RXD3 _4 => SD2_CDATA3) (_2 => GMAC_PHY_RXD3 _3 => LCD_DATA_17 _4 => + SD2_CDATA3) ([Input] [Output])), (39, GPIO39(_2 => GMAC_PHY_RXD2 _4 => SD2_CCLK) + (_2 => GMAC_PHY_RXD2 _3 => LCD_DATA_18 _4 => SD2_CCLK) ([Input] [Output])), (40, + GPIO40(_2 => GMAC_PHY_RXD1 _4 => SD2_CCMD) (_2 => GMAC_PHY_RXD1 _3 => LCD_PCLK _4 + => SD2_CCMD) ([Input] [Output])), (42, GPIO42(_2 => GMAC_RX_CLK) (_2 => + GMAC_RX_CLK) ([Input] [Output])), (43, GPIO43(_2 => GMAC_RMII_CLK) (_2 => + GMAC_RMII_CLK _3 => LCD_H_ENABLE) ([Input] [Output])), (44, GPIO44(_2 => + GMAC_PHY_TXD0) (_2 => GMAC_PHY_TXD0 _3 => LCD_H_SYNC) ([Input] [Output])), (45, + GPIO45(_2 => GMAC_PHY_TXD1) (_2 => GMAC_PHY_TXD1 _3 => LCD_V_SYNC) ([Input] + [Output])), (46, GPIO46(_2 => GMAC_PHY_TXD2 _3 => CAM_DATA_0) (_2 => + GMAC_PHY_TXD2) ([Input] [Output])), (47, GPIO47(_2 => GMAC_PHY_TXD3 _3 => + CAM_DATA_1) (_2 => GMAC_PHY_TXD3) ([Input] [Output])), (48, GPIO48(_3 => + CAM_DATA_2) () ([Input] [Output])), (49, GPIO49(_3 => CAM_DATA_3) () ([Input] + [Output])), (50, GPIO50(_3 => CAM_DATA_4) () ([Input] [Output])), (51, GPIO51(_3 + => CAM_DATA_5) () ([Input] [Output])), (52, GPIO52(_2 => FSPICS0 _3 => + CAM_DATA_6) (_2 => FSPICS0) ([Input] [Output])), (53, GPIO53(_2 => FSPICLK _3 => + CAM_DATA_7) (_2 => FSPICLK) ([Input] [Output])), (54, GPIO54(_0 => MTDO _2 => + FSPID _3 => CAM_PCLK) (_0 => MTDO _2 => FSPID) ([Input] [Output])), (55, GPIO55(_0 => MTCK _2 => FSPIQ _3 => CAM_XCLK) (_0 => MTCK _2 => FSPIQ _3 => CAM_XCLK) ([Input] [Output])), (56, GPIO56(_0 => MTDI _2 => FSPIHD _3 => - CAM_V_SYNC) (_0 => MTDI _2 => FSPIHD _3 => CAM_V_SYNC) ([Input] [Output])), (57, - GPIO57(_0 => MTMS _2 => FSPIWP _3 => CAM_H_SYNC) (_0 => MTMS _2 => FSPIWP _3 => - CAM_H_SYNC) ([Input] [Output])), (58, GPIO58() (_0 => U0TXD) ([Input] [Output])), - (59, GPIO59(_0 => U0RXD) () ([Input] [Output])), (60, GPIO60() () ([Input] - [Output])), (61, GPIO61() () ([Input] [Output])))); + CAM_V_SYNC) (_0 => MTDI _2 => FSPIHD) ([Input] [Output])), (57, GPIO57(_0 => MTMS + _2 => FSPIWP _3 => CAM_H_SYNC) (_0 => MTMS _2 => FSPIWP) ([Input] [Output])), + (58, GPIO58() (_0 => U0TXD) ([Input] [Output])), (59, GPIO59(_0 => U0RXD) () + ([Input] [Output])), (60, GPIO60() () ([Input] [Output])), (61, GPIO61() () + ([Input] [Output])))); }; } /// This macro can be used to generate code for each analog function of each GPIO. @@ -5534,56 +5947,56 @@ macro_rules! for_each_lp_function { macro_rules! for_each_iomux_function { ($($pattern:tt => $code:tt;)*) => { macro_rules! _for_each_inner_iomux_function { $(($pattern) => $code;)* ($other : - tt) => {} } _for_each_inner_iomux_function!((LCD_DATA19, GPIO2, _3)); - _for_each_inner_iomux_function!((LCD_DATA20, GPIO3, _3)); - _for_each_inner_iomux_function!((LCD_DATA21, GPIO4, _3)); - _for_each_inner_iomux_function!((LCD_DATA22, GPIO5, _3)); - _for_each_inner_iomux_function!((LCD_DATA23, GPIO7, _3)); + tt) => {} } _for_each_inner_iomux_function!((LCD_DATA_19, GPIO2, _3)); + _for_each_inner_iomux_function!((LCD_DATA_20, GPIO3, _3)); + _for_each_inner_iomux_function!((LCD_DATA_21, GPIO4, _3)); + _for_each_inner_iomux_function!((LCD_DATA_22, GPIO5, _3)); + _for_each_inner_iomux_function!((LCD_DATA_23, GPIO7, _3)); _for_each_inner_iomux_function!((GMAC_PHY_TXD0, GPIO8, _2)); - _for_each_inner_iomux_function!((LCD_DATA0, GPIO8, _3)); + _for_each_inner_iomux_function!((LCD_DATA_0, GPIO8, _3)); _for_each_inner_iomux_function!((FSPIHD, GPIO9, _0)); _for_each_inner_iomux_function!((GMAC_PHY_TXD1, GPIO9, _2)); - _for_each_inner_iomux_function!((LCD_DATA1, GPIO9, _3)); + _for_each_inner_iomux_function!((LCD_DATA_1, GPIO9, _3)); _for_each_inner_iomux_function!((DBG_PSRAM_CK, GPIO9, _4)); _for_each_inner_iomux_function!((FSPICS0, GPIO10, _0)); _for_each_inner_iomux_function!((GMAC_PHY_TXD2, GPIO10, _2)); - _for_each_inner_iomux_function!((LCD_DATA2, GPIO10, _3)); + _for_each_inner_iomux_function!((LCD_DATA_2, GPIO10, _3)); _for_each_inner_iomux_function!((DBG_PSRAM_CS, GPIO10, _4)); _for_each_inner_iomux_function!((FSPID, GPIO11, _0)); _for_each_inner_iomux_function!((GMAC_PHY_TXD3, GPIO11, _2)); - _for_each_inner_iomux_function!((LCD_DATA3, GPIO11, _3)); + _for_each_inner_iomux_function!((LCD_DATA_3, GPIO11, _3)); _for_each_inner_iomux_function!((DBG_PSRAM_D, GPIO11, _4)); _for_each_inner_iomux_function!((FSPICLK, GPIO12, _0)); _for_each_inner_iomux_function!((GMAC_PHY_TXEN, GPIO12, _2)); - _for_each_inner_iomux_function!((LCD_DATA4, GPIO12, _3)); + _for_each_inner_iomux_function!((LCD_DATA_4, GPIO12, _3)); _for_each_inner_iomux_function!((DBG_PSRAM_Q, GPIO12, _4)); _for_each_inner_iomux_function!((FSPIQ, GPIO13, _0)); _for_each_inner_iomux_function!((GMAC_RMII_CLK, GPIO13, _2)); - _for_each_inner_iomux_function!((LCD_DATA5, GPIO13, _3)); + _for_each_inner_iomux_function!((LCD_DATA_5, GPIO13, _3)); _for_each_inner_iomux_function!((DBG_PSRAM_WP, GPIO13, _4)); _for_each_inner_iomux_function!((FSPIWP, GPIO14, _0)); _for_each_inner_iomux_function!((GMAC_RX_CLK, GPIO14, _2)); - _for_each_inner_iomux_function!((LCD_DATA6, GPIO14, _3)); + _for_each_inner_iomux_function!((LCD_DATA_6, GPIO14, _3)); _for_each_inner_iomux_function!((DBG_PSRAM_HOLD, GPIO14, _4)); _for_each_inner_iomux_function!((FSPIIO4, GPIO15, _0)); _for_each_inner_iomux_function!((GMAC_PHY_RXDV, GPIO15, _2)); - _for_each_inner_iomux_function!((LCD_DATA7, GPIO15, _3)); + _for_each_inner_iomux_function!((LCD_DATA_7, GPIO15, _3)); _for_each_inner_iomux_function!((DBG_PSRAM_DQ4, GPIO15, _4)); _for_each_inner_iomux_function!((FSPIIO5, GPIO16, _0)); _for_each_inner_iomux_function!((GMAC_PHY_RXD3, GPIO16, _2)); - _for_each_inner_iomux_function!((LCD_DATA8, GPIO16, _3)); + _for_each_inner_iomux_function!((LCD_DATA_8, GPIO16, _3)); _for_each_inner_iomux_function!((DBG_PSRAM_DQ5, GPIO16, _4)); _for_each_inner_iomux_function!((FSPIIO6, GPIO17, _0)); _for_each_inner_iomux_function!((GMAC_PHY_RXD2, GPIO17, _2)); - _for_each_inner_iomux_function!((LCD_DATA9, GPIO17, _3)); + _for_each_inner_iomux_function!((LCD_DATA_9, GPIO17, _3)); _for_each_inner_iomux_function!((DBG_PSRAM_DQ6, GPIO17, _4)); _for_each_inner_iomux_function!((FSPIIO7, GPIO18, _0)); _for_each_inner_iomux_function!((GMAC_PHY_RXD1, GPIO18, _2)); - _for_each_inner_iomux_function!((LCD_DATA10, GPIO18, _3)); + _for_each_inner_iomux_function!((LCD_DATA_10, GPIO18, _3)); _for_each_inner_iomux_function!((DBG_PSRAM_DQ7, GPIO18, _4)); _for_each_inner_iomux_function!((FSPIDQS, GPIO19, _0)); _for_each_inner_iomux_function!((GMAC_PHY_RXD0, GPIO19, _2)); - _for_each_inner_iomux_function!((LCD_DATA11, GPIO19, _3)); + _for_each_inner_iomux_function!((LCD_DATA_11, GPIO19, _3)); _for_each_inner_iomux_function!((DBG_PSRAM_DQS_0, GPIO19, _4)); _for_each_inner_iomux_function!((SD1_DATA0, GPIO20, _0)); _for_each_inner_iomux_function!((FSPICLK, GPIO20, _2)); @@ -5609,22 +6022,22 @@ macro_rules! for_each_iomux_function { _for_each_inner_iomux_function!((SPIHD, GPIO30, _0)); _for_each_inner_iomux_function!((SPICLK, GPIO31, _0)); _for_each_inner_iomux_function!((SPID, GPIO32, _0)); - _for_each_inner_iomux_function!((LCD_DATA12, GPIO33, _3)); - _for_each_inner_iomux_function!((LCD_DATA13, GPIO34, _3)); + _for_each_inner_iomux_function!((LCD_DATA_12, GPIO33, _3)); + _for_each_inner_iomux_function!((LCD_DATA_13, GPIO34, _3)); _for_each_inner_iomux_function!((REF_GMAC_CLK, GPIO35, _2)); - _for_each_inner_iomux_function!((LCD_DATA14, GPIO35, _3)); + _for_each_inner_iomux_function!((LCD_DATA_14, GPIO35, _3)); _for_each_inner_iomux_function!((SD2_CDATA0, GPIO35, _4)); _for_each_inner_iomux_function!((GMAC_PHY_RXDV, GPIO36, _2)); - _for_each_inner_iomux_function!((LCD_DATA15, GPIO36, _3)); + _for_each_inner_iomux_function!((LCD_DATA_15, GPIO36, _3)); _for_each_inner_iomux_function!((SD2_CDATA1, GPIO36, _4)); _for_each_inner_iomux_function!((GMAC_PHY_TXEN, GPIO37, _2)); - _for_each_inner_iomux_function!((LCD_DATA16, GPIO37, _3)); + _for_each_inner_iomux_function!((LCD_DATA_16, GPIO37, _3)); _for_each_inner_iomux_function!((SD2_CDATA2, GPIO37, _4)); _for_each_inner_iomux_function!((GMAC_PHY_RXD3, GPIO38, _2)); - _for_each_inner_iomux_function!((LCD_DATA17, GPIO38, _3)); + _for_each_inner_iomux_function!((LCD_DATA_17, GPIO38, _3)); _for_each_inner_iomux_function!((SD2_CDATA3, GPIO38, _4)); _for_each_inner_iomux_function!((GMAC_PHY_RXD2, GPIO39, _2)); - _for_each_inner_iomux_function!((LCD_DATA18, GPIO39, _3)); + _for_each_inner_iomux_function!((LCD_DATA_18, GPIO39, _3)); _for_each_inner_iomux_function!((SD2_CCLK, GPIO39, _4)); _for_each_inner_iomux_function!((GMAC_PHY_RXD1, GPIO40, _2)); _for_each_inner_iomux_function!((LCD_PCLK, GPIO40, _3)); @@ -5637,17 +6050,17 @@ macro_rules! for_each_iomux_function { _for_each_inner_iomux_function!((GMAC_PHY_TXD1, GPIO45, _2)); _for_each_inner_iomux_function!((LCD_V_SYNC, GPIO45, _3)); _for_each_inner_iomux_function!((GMAC_PHY_TXD2, GPIO46, _2)); - _for_each_inner_iomux_function!((CAM_DATA0, GPIO46, _3)); + _for_each_inner_iomux_function!((CAM_DATA_0, GPIO46, _3)); _for_each_inner_iomux_function!((GMAC_PHY_TXD3, GPIO47, _2)); - _for_each_inner_iomux_function!((CAM_DATA1, GPIO47, _3)); - _for_each_inner_iomux_function!((CAM_DATA2, GPIO48, _3)); - _for_each_inner_iomux_function!((CAM_DATA3, GPIO49, _3)); - _for_each_inner_iomux_function!((CAM_DATA4, GPIO50, _3)); - _for_each_inner_iomux_function!((CAM_DATA5, GPIO51, _3)); + _for_each_inner_iomux_function!((CAM_DATA_1, GPIO47, _3)); + _for_each_inner_iomux_function!((CAM_DATA_2, GPIO48, _3)); + _for_each_inner_iomux_function!((CAM_DATA_3, GPIO49, _3)); + _for_each_inner_iomux_function!((CAM_DATA_4, GPIO50, _3)); + _for_each_inner_iomux_function!((CAM_DATA_5, GPIO51, _3)); _for_each_inner_iomux_function!((FSPICS0, GPIO52, _2)); - _for_each_inner_iomux_function!((CAM_DATA6, GPIO52, _3)); + _for_each_inner_iomux_function!((CAM_DATA_6, GPIO52, _3)); _for_each_inner_iomux_function!((FSPICLK, GPIO53, _2)); - _for_each_inner_iomux_function!((CAM_DATA7, GPIO53, _3)); + _for_each_inner_iomux_function!((CAM_DATA_7, GPIO53, _3)); _for_each_inner_iomux_function!((MTDO, GPIO54, _0)); _for_each_inner_iomux_function!((FSPID, GPIO54, _2)); _for_each_inner_iomux_function!((CAM_PCLK, GPIO54, _3)); @@ -5662,30 +6075,30 @@ macro_rules! for_each_iomux_function { _for_each_inner_iomux_function!((CAM_H_SYNC, GPIO57, _3)); _for_each_inner_iomux_function!((U0TXD, GPIO58, _0)); _for_each_inner_iomux_function!((U0RXD, GPIO59, _0)); - _for_each_inner_iomux_function!(((LCD_DATA19, LCD_DATAn, 19), GPIO2, _3)); - _for_each_inner_iomux_function!(((LCD_DATA20, LCD_DATAn, 20), GPIO3, _3)); - _for_each_inner_iomux_function!(((LCD_DATA21, LCD_DATAn, 21), GPIO4, _3)); - _for_each_inner_iomux_function!(((LCD_DATA22, LCD_DATAn, 22), GPIO5, _3)); - _for_each_inner_iomux_function!(((LCD_DATA23, LCD_DATAn, 23), GPIO7, _3)); - _for_each_inner_iomux_function!(((LCD_DATA0, LCD_DATAn, 0), GPIO8, _3)); - _for_each_inner_iomux_function!(((LCD_DATA1, LCD_DATAn, 1), GPIO9, _3)); - _for_each_inner_iomux_function!(((LCD_DATA2, LCD_DATAn, 2), GPIO10, _3)); - _for_each_inner_iomux_function!(((LCD_DATA3, LCD_DATAn, 3), GPIO11, _3)); - _for_each_inner_iomux_function!(((LCD_DATA4, LCD_DATAn, 4), GPIO12, _3)); - _for_each_inner_iomux_function!(((LCD_DATA5, LCD_DATAn, 5), GPIO13, _3)); - _for_each_inner_iomux_function!(((LCD_DATA6, LCD_DATAn, 6), GPIO14, _3)); - _for_each_inner_iomux_function!(((LCD_DATA7, LCD_DATAn, 7), GPIO15, _3)); - _for_each_inner_iomux_function!(((LCD_DATA8, LCD_DATAn, 8), GPIO16, _3)); - _for_each_inner_iomux_function!(((LCD_DATA9, LCD_DATAn, 9), GPIO17, _3)); - _for_each_inner_iomux_function!(((LCD_DATA10, LCD_DATAn, 10), GPIO18, _3)); - _for_each_inner_iomux_function!(((LCD_DATA11, LCD_DATAn, 11), GPIO19, _3)); - _for_each_inner_iomux_function!(((LCD_DATA12, LCD_DATAn, 12), GPIO33, _3)); - _for_each_inner_iomux_function!(((LCD_DATA13, LCD_DATAn, 13), GPIO34, _3)); - _for_each_inner_iomux_function!(((LCD_DATA14, LCD_DATAn, 14), GPIO35, _3)); - _for_each_inner_iomux_function!(((LCD_DATA15, LCD_DATAn, 15), GPIO36, _3)); - _for_each_inner_iomux_function!(((LCD_DATA16, LCD_DATAn, 16), GPIO37, _3)); - _for_each_inner_iomux_function!(((LCD_DATA17, LCD_DATAn, 17), GPIO38, _3)); - _for_each_inner_iomux_function!(((LCD_DATA18, LCD_DATAn, 18), GPIO39, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_19, LCD_DATA_n, 19), GPIO2, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_20, LCD_DATA_n, 20), GPIO3, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_21, LCD_DATA_n, 21), GPIO4, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_22, LCD_DATA_n, 22), GPIO5, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_23, LCD_DATA_n, 23), GPIO7, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_0, LCD_DATA_n, 0), GPIO8, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_1, LCD_DATA_n, 1), GPIO9, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_2, LCD_DATA_n, 2), GPIO10, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_3, LCD_DATA_n, 3), GPIO11, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_4, LCD_DATA_n, 4), GPIO12, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_5, LCD_DATA_n, 5), GPIO13, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_6, LCD_DATA_n, 6), GPIO14, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_7, LCD_DATA_n, 7), GPIO15, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_8, LCD_DATA_n, 8), GPIO16, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_9, LCD_DATA_n, 9), GPIO17, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_10, LCD_DATA_n, 10), GPIO18, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_11, LCD_DATA_n, 11), GPIO19, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_12, LCD_DATA_n, 12), GPIO33, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_13, LCD_DATA_n, 13), GPIO34, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_14, LCD_DATA_n, 14), GPIO35, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_15, LCD_DATA_n, 15), GPIO36, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_16, LCD_DATA_n, 16), GPIO37, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_17, LCD_DATA_n, 17), GPIO38, _3)); + _for_each_inner_iomux_function!(((LCD_DATA_18, LCD_DATA_n, 18), GPIO39, _3)); _for_each_inner_iomux_function!(((GMAC_PHY_TXD0, GMAC_PHY_TXDn, 0), GPIO8, _2)); _for_each_inner_iomux_function!(((GMAC_PHY_TXD1, GMAC_PHY_TXDn, 1), GPIO9, _2)); _for_each_inner_iomux_function!(((GMAC_PHY_TXD2, GMAC_PHY_TXDn, 2), GPIO10, _2)); @@ -5726,70 +6139,71 @@ macro_rules! for_each_iomux_function { _for_each_inner_iomux_function!(((SD2_CDATA3, SDn_CDATAm, 2, 3), GPIO38, _4)); _for_each_inner_iomux_function!(((SD2_CCLK, SDn_CCLK, 2), GPIO39, _4)); _for_each_inner_iomux_function!(((SD2_CCMD, SDn_CCMD, 2), GPIO40, _4)); - _for_each_inner_iomux_function!(((CAM_DATA0, CAM_DATAn, 0), GPIO46, _3)); - _for_each_inner_iomux_function!(((CAM_DATA1, CAM_DATAn, 1), GPIO47, _3)); - _for_each_inner_iomux_function!(((CAM_DATA2, CAM_DATAn, 2), GPIO48, _3)); - _for_each_inner_iomux_function!(((CAM_DATA3, CAM_DATAn, 3), GPIO49, _3)); - _for_each_inner_iomux_function!(((CAM_DATA4, CAM_DATAn, 4), GPIO50, _3)); - _for_each_inner_iomux_function!(((CAM_DATA5, CAM_DATAn, 5), GPIO51, _3)); - _for_each_inner_iomux_function!(((CAM_DATA6, CAM_DATAn, 6), GPIO52, _3)); - _for_each_inner_iomux_function!(((CAM_DATA7, CAM_DATAn, 7), GPIO53, _3)); - _for_each_inner_iomux_function!((all(LCD_DATA19, GPIO2, _3), (LCD_DATA20, GPIO3, - _3), (LCD_DATA21, GPIO4, _3), (LCD_DATA22, GPIO5, _3), (LCD_DATA23, GPIO7, _3), - (GMAC_PHY_TXD0, GPIO8, _2), (LCD_DATA0, GPIO8, _3), (FSPIHD, GPIO9, _0), - (GMAC_PHY_TXD1, GPIO9, _2), (LCD_DATA1, GPIO9, _3), (DBG_PSRAM_CK, GPIO9, _4), - (FSPICS0, GPIO10, _0), (GMAC_PHY_TXD2, GPIO10, _2), (LCD_DATA2, GPIO10, _3), - (DBG_PSRAM_CS, GPIO10, _4), (FSPID, GPIO11, _0), (GMAC_PHY_TXD3, GPIO11, _2), - (LCD_DATA3, GPIO11, _3), (DBG_PSRAM_D, GPIO11, _4), (FSPICLK, GPIO12, _0), - (GMAC_PHY_TXEN, GPIO12, _2), (LCD_DATA4, GPIO12, _3), (DBG_PSRAM_Q, GPIO12, _4), - (FSPIQ, GPIO13, _0), (GMAC_RMII_CLK, GPIO13, _2), (LCD_DATA5, GPIO13, _3), + _for_each_inner_iomux_function!(((CAM_DATA_0, CAM_DATA_n, 0), GPIO46, _3)); + _for_each_inner_iomux_function!(((CAM_DATA_1, CAM_DATA_n, 1), GPIO47, _3)); + _for_each_inner_iomux_function!(((CAM_DATA_2, CAM_DATA_n, 2), GPIO48, _3)); + _for_each_inner_iomux_function!(((CAM_DATA_3, CAM_DATA_n, 3), GPIO49, _3)); + _for_each_inner_iomux_function!(((CAM_DATA_4, CAM_DATA_n, 4), GPIO50, _3)); + _for_each_inner_iomux_function!(((CAM_DATA_5, CAM_DATA_n, 5), GPIO51, _3)); + _for_each_inner_iomux_function!(((CAM_DATA_6, CAM_DATA_n, 6), GPIO52, _3)); + _for_each_inner_iomux_function!(((CAM_DATA_7, CAM_DATA_n, 7), GPIO53, _3)); + _for_each_inner_iomux_function!((all(LCD_DATA_19, GPIO2, _3), (LCD_DATA_20, + GPIO3, _3), (LCD_DATA_21, GPIO4, _3), (LCD_DATA_22, GPIO5, _3), (LCD_DATA_23, + GPIO7, _3), (GMAC_PHY_TXD0, GPIO8, _2), (LCD_DATA_0, GPIO8, _3), (FSPIHD, GPIO9, + _0), (GMAC_PHY_TXD1, GPIO9, _2), (LCD_DATA_1, GPIO9, _3), (DBG_PSRAM_CK, GPIO9, + _4), (FSPICS0, GPIO10, _0), (GMAC_PHY_TXD2, GPIO10, _2), (LCD_DATA_2, GPIO10, + _3), (DBG_PSRAM_CS, GPIO10, _4), (FSPID, GPIO11, _0), (GMAC_PHY_TXD3, GPIO11, + _2), (LCD_DATA_3, GPIO11, _3), (DBG_PSRAM_D, GPIO11, _4), (FSPICLK, GPIO12, _0), + (GMAC_PHY_TXEN, GPIO12, _2), (LCD_DATA_4, GPIO12, _3), (DBG_PSRAM_Q, GPIO12, _4), + (FSPIQ, GPIO13, _0), (GMAC_RMII_CLK, GPIO13, _2), (LCD_DATA_5, GPIO13, _3), (DBG_PSRAM_WP, GPIO13, _4), (FSPIWP, GPIO14, _0), (GMAC_RX_CLK, GPIO14, _2), - (LCD_DATA6, GPIO14, _3), (DBG_PSRAM_HOLD, GPIO14, _4), (FSPIIO4, GPIO15, _0), - (GMAC_PHY_RXDV, GPIO15, _2), (LCD_DATA7, GPIO15, _3), (DBG_PSRAM_DQ4, GPIO15, - _4), (FSPIIO5, GPIO16, _0), (GMAC_PHY_RXD3, GPIO16, _2), (LCD_DATA8, GPIO16, _3), - (DBG_PSRAM_DQ5, GPIO16, _4), (FSPIIO6, GPIO17, _0), (GMAC_PHY_RXD2, GPIO17, _2), - (LCD_DATA9, GPIO17, _3), (DBG_PSRAM_DQ6, GPIO17, _4), (FSPIIO7, GPIO18, _0), - (GMAC_PHY_RXD1, GPIO18, _2), (LCD_DATA10, GPIO18, _3), (DBG_PSRAM_DQ7, GPIO18, - _4), (FSPIDQS, GPIO19, _0), (GMAC_PHY_RXD0, GPIO19, _2), (LCD_DATA11, GPIO19, - _3), (DBG_PSRAM_DQS_0, GPIO19, _4), (SD1_DATA0, GPIO20, _0), (FSPICLK, GPIO20, - _2), (DBG_FLASH_CK, GPIO20, _4), (SD1_DATA1, GPIO21, _0), (FSPID, GPIO21, _2), - (DBG_FLASH_D, GPIO21, _4), (SD1_DATA2, GPIO22, _0), (FSPIQ, GPIO22, _2), + (LCD_DATA_6, GPIO14, _3), (DBG_PSRAM_HOLD, GPIO14, _4), (FSPIIO4, GPIO15, _0), + (GMAC_PHY_RXDV, GPIO15, _2), (LCD_DATA_7, GPIO15, _3), (DBG_PSRAM_DQ4, GPIO15, + _4), (FSPIIO5, GPIO16, _0), (GMAC_PHY_RXD3, GPIO16, _2), (LCD_DATA_8, GPIO16, + _3), (DBG_PSRAM_DQ5, GPIO16, _4), (FSPIIO6, GPIO17, _0), (GMAC_PHY_RXD2, GPIO17, + _2), (LCD_DATA_9, GPIO17, _3), (DBG_PSRAM_DQ6, GPIO17, _4), (FSPIIO7, GPIO18, + _0), (GMAC_PHY_RXD1, GPIO18, _2), (LCD_DATA_10, GPIO18, _3), (DBG_PSRAM_DQ7, + GPIO18, _4), (FSPIDQS, GPIO19, _0), (GMAC_PHY_RXD0, GPIO19, _2), (LCD_DATA_11, + GPIO19, _3), (DBG_PSRAM_DQS_0, GPIO19, _4), (SD1_DATA0, GPIO20, _0), (FSPICLK, + GPIO20, _2), (DBG_FLASH_CK, GPIO20, _4), (SD1_DATA1, GPIO21, _0), (FSPID, GPIO21, + _2), (DBG_FLASH_D, GPIO21, _4), (SD1_DATA2, GPIO22, _0), (FSPIQ, GPIO22, _2), (DBG_FLASH_CS, GPIO22, _4), (SD1_DATA3, GPIO23, _0), (FSPICS0, GPIO23, _2), (DBG_FLASH_Q, GPIO23, _4), (SD1_CLK, GPIO24, _0), (FSPIHD, GPIO24, _2), (DBG_FLASH_WP, GPIO24, _4), (SD1_CMD, GPIO25, _0), (FSPIWP, GPIO25, _2), (DBG_FLASH_HOLD, GPIO25, _4), (SPICS0, GPIO26, _0), (SPIQ, GPIO27, _0), (SPIWP, GPIO28, _0), (SPIHD, GPIO30, _0), (SPICLK, GPIO31, _0), (SPID, GPIO32, _0), - (LCD_DATA12, GPIO33, _3), (LCD_DATA13, GPIO34, _3), (REF_GMAC_CLK, GPIO35, _2), - (LCD_DATA14, GPIO35, _3), (SD2_CDATA0, GPIO35, _4), (GMAC_PHY_RXDV, GPIO36, _2), - (LCD_DATA15, GPIO36, _3), (SD2_CDATA1, GPIO36, _4), (GMAC_PHY_TXEN, GPIO37, _2), - (LCD_DATA16, GPIO37, _3), (SD2_CDATA2, GPIO37, _4), (GMAC_PHY_RXD3, GPIO38, _2), - (LCD_DATA17, GPIO38, _3), (SD2_CDATA3, GPIO38, _4), (GMAC_PHY_RXD2, GPIO39, _2), - (LCD_DATA18, GPIO39, _3), (SD2_CCLK, GPIO39, _4), (GMAC_PHY_RXD1, GPIO40, _2), + (LCD_DATA_12, GPIO33, _3), (LCD_DATA_13, GPIO34, _3), (REF_GMAC_CLK, GPIO35, _2), + (LCD_DATA_14, GPIO35, _3), (SD2_CDATA0, GPIO35, _4), (GMAC_PHY_RXDV, GPIO36, _2), + (LCD_DATA_15, GPIO36, _3), (SD2_CDATA1, GPIO36, _4), (GMAC_PHY_TXEN, GPIO37, _2), + (LCD_DATA_16, GPIO37, _3), (SD2_CDATA2, GPIO37, _4), (GMAC_PHY_RXD3, GPIO38, _2), + (LCD_DATA_17, GPIO38, _3), (SD2_CDATA3, GPIO38, _4), (GMAC_PHY_RXD2, GPIO39, _2), + (LCD_DATA_18, GPIO39, _3), (SD2_CCLK, GPIO39, _4), (GMAC_PHY_RXD1, GPIO40, _2), (LCD_PCLK, GPIO40, _3), (SD2_CCMD, GPIO40, _4), (GMAC_RX_CLK, GPIO42, _2), (GMAC_RMII_CLK, GPIO43, _2), (LCD_H_ENABLE, GPIO43, _3), (GMAC_PHY_TXD0, GPIO44, _2), (LCD_H_SYNC, GPIO44, _3), (GMAC_PHY_TXD1, GPIO45, _2), (LCD_V_SYNC, GPIO45, - _3), (GMAC_PHY_TXD2, GPIO46, _2), (CAM_DATA0, GPIO46, _3), (GMAC_PHY_TXD3, - GPIO47, _2), (CAM_DATA1, GPIO47, _3), (CAM_DATA2, GPIO48, _3), (CAM_DATA3, - GPIO49, _3), (CAM_DATA4, GPIO50, _3), (CAM_DATA5, GPIO51, _3), (FSPICS0, GPIO52, - _2), (CAM_DATA6, GPIO52, _3), (FSPICLK, GPIO53, _2), (CAM_DATA7, GPIO53, _3), - (MTDO, GPIO54, _0), (FSPID, GPIO54, _2), (CAM_PCLK, GPIO54, _3), (MTCK, GPIO55, - _0), (FSPIQ, GPIO55, _2), (CAM_XCLK, GPIO55, _3), (MTDI, GPIO56, _0), (FSPIHD, - GPIO56, _2), (CAM_V_SYNC, GPIO56, _3), (MTMS, GPIO57, _0), (FSPIWP, GPIO57, _2), - (CAM_H_SYNC, GPIO57, _3), (U0TXD, GPIO58, _0), (U0RXD, GPIO59, _0))); - _for_each_inner_iomux_function!((LCD_DATAn((LCD_DATA19, LCD_DATAn, 19), GPIO2, - _3), ((LCD_DATA20, LCD_DATAn, 20), GPIO3, _3), ((LCD_DATA21, LCD_DATAn, 21), - GPIO4, _3), ((LCD_DATA22, LCD_DATAn, 22), GPIO5, _3), ((LCD_DATA23, LCD_DATAn, - 23), GPIO7, _3), ((LCD_DATA0, LCD_DATAn, 0), GPIO8, _3), ((LCD_DATA1, LCD_DATAn, - 1), GPIO9, _3), ((LCD_DATA2, LCD_DATAn, 2), GPIO10, _3), ((LCD_DATA3, LCD_DATAn, - 3), GPIO11, _3), ((LCD_DATA4, LCD_DATAn, 4), GPIO12, _3), ((LCD_DATA5, LCD_DATAn, - 5), GPIO13, _3), ((LCD_DATA6, LCD_DATAn, 6), GPIO14, _3), ((LCD_DATA7, LCD_DATAn, - 7), GPIO15, _3), ((LCD_DATA8, LCD_DATAn, 8), GPIO16, _3), ((LCD_DATA9, LCD_DATAn, - 9), GPIO17, _3), ((LCD_DATA10, LCD_DATAn, 10), GPIO18, _3), ((LCD_DATA11, - LCD_DATAn, 11), GPIO19, _3), ((LCD_DATA12, LCD_DATAn, 12), GPIO33, _3), - ((LCD_DATA13, LCD_DATAn, 13), GPIO34, _3), ((LCD_DATA14, LCD_DATAn, 14), GPIO35, - _3), ((LCD_DATA15, LCD_DATAn, 15), GPIO36, _3), ((LCD_DATA16, LCD_DATAn, 16), - GPIO37, _3), ((LCD_DATA17, LCD_DATAn, 17), GPIO38, _3), ((LCD_DATA18, LCD_DATAn, - 18), GPIO39, _3))); + _3), (GMAC_PHY_TXD2, GPIO46, _2), (CAM_DATA_0, GPIO46, _3), (GMAC_PHY_TXD3, + GPIO47, _2), (CAM_DATA_1, GPIO47, _3), (CAM_DATA_2, GPIO48, _3), (CAM_DATA_3, + GPIO49, _3), (CAM_DATA_4, GPIO50, _3), (CAM_DATA_5, GPIO51, _3), (FSPICS0, + GPIO52, _2), (CAM_DATA_6, GPIO52, _3), (FSPICLK, GPIO53, _2), (CAM_DATA_7, + GPIO53, _3), (MTDO, GPIO54, _0), (FSPID, GPIO54, _2), (CAM_PCLK, GPIO54, _3), + (MTCK, GPIO55, _0), (FSPIQ, GPIO55, _2), (CAM_XCLK, GPIO55, _3), (MTDI, GPIO56, + _0), (FSPIHD, GPIO56, _2), (CAM_V_SYNC, GPIO56, _3), (MTMS, GPIO57, _0), (FSPIWP, + GPIO57, _2), (CAM_H_SYNC, GPIO57, _3), (U0TXD, GPIO58, _0), (U0RXD, GPIO59, + _0))); _for_each_inner_iomux_function!((LCD_DATA_n((LCD_DATA_19, LCD_DATA_n, 19), + GPIO2, _3), ((LCD_DATA_20, LCD_DATA_n, 20), GPIO3, _3), ((LCD_DATA_21, + LCD_DATA_n, 21), GPIO4, _3), ((LCD_DATA_22, LCD_DATA_n, 22), GPIO5, _3), + ((LCD_DATA_23, LCD_DATA_n, 23), GPIO7, _3), ((LCD_DATA_0, LCD_DATA_n, 0), GPIO8, + _3), ((LCD_DATA_1, LCD_DATA_n, 1), GPIO9, _3), ((LCD_DATA_2, LCD_DATA_n, 2), + GPIO10, _3), ((LCD_DATA_3, LCD_DATA_n, 3), GPIO11, _3), ((LCD_DATA_4, LCD_DATA_n, + 4), GPIO12, _3), ((LCD_DATA_5, LCD_DATA_n, 5), GPIO13, _3), ((LCD_DATA_6, + LCD_DATA_n, 6), GPIO14, _3), ((LCD_DATA_7, LCD_DATA_n, 7), GPIO15, _3), + ((LCD_DATA_8, LCD_DATA_n, 8), GPIO16, _3), ((LCD_DATA_9, LCD_DATA_n, 9), GPIO17, + _3), ((LCD_DATA_10, LCD_DATA_n, 10), GPIO18, _3), ((LCD_DATA_11, LCD_DATA_n, 11), + GPIO19, _3), ((LCD_DATA_12, LCD_DATA_n, 12), GPIO33, _3), ((LCD_DATA_13, + LCD_DATA_n, 13), GPIO34, _3), ((LCD_DATA_14, LCD_DATA_n, 14), GPIO35, _3), + ((LCD_DATA_15, LCD_DATA_n, 15), GPIO36, _3), ((LCD_DATA_16, LCD_DATA_n, 16), + GPIO37, _3), ((LCD_DATA_17, LCD_DATA_n, 17), GPIO38, _3), ((LCD_DATA_18, + LCD_DATA_n, 18), GPIO39, _3))); _for_each_inner_iomux_function!((GMAC_PHY_TXDn((GMAC_PHY_TXD0, GMAC_PHY_TXDn, 0), GPIO8, _2), ((GMAC_PHY_TXD1, GMAC_PHY_TXDn, 1), GPIO9, _2), ((GMAC_PHY_TXD2, GMAC_PHY_TXDn, 2), GPIO10, _2), ((GMAC_PHY_TXD3, GMAC_PHY_TXDn, 3), GPIO11, _2), @@ -5823,11 +6237,11 @@ macro_rules! for_each_iomux_function { SDn_CDATAm, 2, 2), GPIO37, _4), ((SD2_CDATA3, SDn_CDATAm, 2, 3), GPIO38, _4))); _for_each_inner_iomux_function!((SDn_CCLK((SD2_CCLK, SDn_CCLK, 2), GPIO39, _4))); _for_each_inner_iomux_function!((SDn_CCMD((SD2_CCMD, SDn_CCMD, 2), GPIO40, _4))); - _for_each_inner_iomux_function!((CAM_DATAn((CAM_DATA0, CAM_DATAn, 0), GPIO46, - _3), ((CAM_DATA1, CAM_DATAn, 1), GPIO47, _3), ((CAM_DATA2, CAM_DATAn, 2), GPIO48, - _3), ((CAM_DATA3, CAM_DATAn, 3), GPIO49, _3), ((CAM_DATA4, CAM_DATAn, 4), GPIO50, - _3), ((CAM_DATA5, CAM_DATAn, 5), GPIO51, _3), ((CAM_DATA6, CAM_DATAn, 6), GPIO52, - _3), ((CAM_DATA7, CAM_DATAn, 7), GPIO53, _3))); + _for_each_inner_iomux_function!((CAM_DATA_n((CAM_DATA_0, CAM_DATA_n, 0), GPIO46, + _3), ((CAM_DATA_1, CAM_DATA_n, 1), GPIO47, _3), ((CAM_DATA_2, CAM_DATA_n, 2), + GPIO48, _3), ((CAM_DATA_3, CAM_DATA_n, 3), GPIO49, _3), ((CAM_DATA_4, CAM_DATA_n, + 4), GPIO50, _3), ((CAM_DATA_5, CAM_DATA_n, 5), GPIO51, _3), ((CAM_DATA_6, + CAM_DATA_n, 6), GPIO52, _3), ((CAM_DATA_7, CAM_DATA_n, 7), GPIO53, _3))); }; } /// Returns the name of the GPIO that provides the given signal, as a string. @@ -5861,25 +6275,25 @@ macro_rules! gpio_for_signal { (LP_GPIO1 $(, $_fallback:literal)?) => { "GPIO1" }; - (LCD_DATA19 $(, $_fallback:literal)?) => { + (LCD_DATA_19 $(, $_fallback:literal)?) => { "GPIO2" }; (LP_GPIO2 $(, $_fallback:literal)?) => { "GPIO2" }; - (LCD_DATA20 $(, $_fallback:literal)?) => { + (LCD_DATA_20 $(, $_fallback:literal)?) => { "GPIO3" }; (LP_GPIO3 $(, $_fallback:literal)?) => { "GPIO3" }; - (LCD_DATA21 $(, $_fallback:literal)?) => { + (LCD_DATA_21 $(, $_fallback:literal)?) => { "GPIO4" }; (LP_GPIO4 $(, $_fallback:literal)?) => { "GPIO4" }; - (LCD_DATA22 $(, $_fallback:literal)?) => { + (LCD_DATA_22 $(, $_fallback:literal)?) => { "GPIO5" }; (LP_GPIO5 $(, $_fallback:literal)?) => { @@ -5888,7 +6302,7 @@ macro_rules! gpio_for_signal { (LP_GPIO6 $(, $_fallback:literal)?) => { "GPIO6" }; - (LCD_DATA23 $(, $_fallback:literal)?) => { + (LCD_DATA_23 $(, $_fallback:literal)?) => { "GPIO7" }; (LP_GPIO7 $(, $_fallback:literal)?) => { @@ -5897,7 +6311,7 @@ macro_rules! gpio_for_signal { (GMAC_PHY_TXD0 $(, $_fallback:literal)?) => { "GPIO8" }; - (LCD_DATA0 $(, $_fallback:literal)?) => { + (LCD_DATA_0 $(, $_fallback:literal)?) => { "GPIO8" }; (FSPIHD $(, $_fallback:literal)?) => { @@ -5906,7 +6320,7 @@ macro_rules! gpio_for_signal { (GMAC_PHY_TXD1 $(, $_fallback:literal)?) => { "GPIO9" }; - (LCD_DATA1 $(, $_fallback:literal)?) => { + (LCD_DATA_1 $(, $_fallback:literal)?) => { "GPIO9" }; (DBG_PSRAM_CK $(, $_fallback:literal)?) => { @@ -5918,7 +6332,7 @@ macro_rules! gpio_for_signal { (GMAC_PHY_TXD2 $(, $_fallback:literal)?) => { "GPIO10" }; - (LCD_DATA2 $(, $_fallback:literal)?) => { + (LCD_DATA_2 $(, $_fallback:literal)?) => { "GPIO10" }; (DBG_PSRAM_CS $(, $_fallback:literal)?) => { @@ -5930,7 +6344,7 @@ macro_rules! gpio_for_signal { (GMAC_PHY_TXD3 $(, $_fallback:literal)?) => { "GPIO11" }; - (LCD_DATA3 $(, $_fallback:literal)?) => { + (LCD_DATA_3 $(, $_fallback:literal)?) => { "GPIO11" }; (DBG_PSRAM_D $(, $_fallback:literal)?) => { @@ -5942,7 +6356,7 @@ macro_rules! gpio_for_signal { (GMAC_PHY_TXEN $(, $_fallback:literal)?) => { "GPIO12" }; - (LCD_DATA4 $(, $_fallback:literal)?) => { + (LCD_DATA_4 $(, $_fallback:literal)?) => { "GPIO12" }; (DBG_PSRAM_Q $(, $_fallback:literal)?) => { @@ -5954,7 +6368,7 @@ macro_rules! gpio_for_signal { (GMAC_RMII_CLK $(, $_fallback:literal)?) => { "GPIO13" }; - (LCD_DATA5 $(, $_fallback:literal)?) => { + (LCD_DATA_5 $(, $_fallback:literal)?) => { "GPIO13" }; (DBG_PSRAM_WP $(, $_fallback:literal)?) => { @@ -5966,7 +6380,7 @@ macro_rules! gpio_for_signal { (GMAC_RX_CLK $(, $_fallback:literal)?) => { "GPIO14" }; - (LCD_DATA6 $(, $_fallback:literal)?) => { + (LCD_DATA_6 $(, $_fallback:literal)?) => { "GPIO14" }; (DBG_PSRAM_HOLD $(, $_fallback:literal)?) => { @@ -5978,7 +6392,7 @@ macro_rules! gpio_for_signal { (GMAC_PHY_RXDV $(, $_fallback:literal)?) => { "GPIO15" }; - (LCD_DATA7 $(, $_fallback:literal)?) => { + (LCD_DATA_7 $(, $_fallback:literal)?) => { "GPIO15" }; (DBG_PSRAM_DQ4 $(, $_fallback:literal)?) => { @@ -5990,7 +6404,7 @@ macro_rules! gpio_for_signal { (GMAC_PHY_RXD3 $(, $_fallback:literal)?) => { "GPIO16" }; - (LCD_DATA8 $(, $_fallback:literal)?) => { + (LCD_DATA_8 $(, $_fallback:literal)?) => { "GPIO16" }; (DBG_PSRAM_DQ5 $(, $_fallback:literal)?) => { @@ -6002,7 +6416,7 @@ macro_rules! gpio_for_signal { (GMAC_PHY_RXD2 $(, $_fallback:literal)?) => { "GPIO17" }; - (LCD_DATA9 $(, $_fallback:literal)?) => { + (LCD_DATA_9 $(, $_fallback:literal)?) => { "GPIO17" }; (DBG_PSRAM_DQ6 $(, $_fallback:literal)?) => { @@ -6014,7 +6428,7 @@ macro_rules! gpio_for_signal { (GMAC_PHY_RXD1 $(, $_fallback:literal)?) => { "GPIO18" }; - (LCD_DATA10 $(, $_fallback:literal)?) => { + (LCD_DATA_10 $(, $_fallback:literal)?) => { "GPIO18" }; (DBG_PSRAM_DQ7 $(, $_fallback:literal)?) => { @@ -6026,7 +6440,7 @@ macro_rules! gpio_for_signal { (GMAC_PHY_RXD0 $(, $_fallback:literal)?) => { "GPIO19" }; - (LCD_DATA11 $(, $_fallback:literal)?) => { + (LCD_DATA_11 $(, $_fallback:literal)?) => { "GPIO19" }; (DBG_PSRAM_DQS_0 $(, $_fallback:literal)?) => { @@ -6086,13 +6500,13 @@ macro_rules! gpio_for_signal { (SPID $(, $_fallback:literal)?) => { "GPIO32" }; - (LCD_DATA12 $(, $_fallback:literal)?) => { + (LCD_DATA_12 $(, $_fallback:literal)?) => { "GPIO33" }; (USJ_DM $(, $_fallback:literal)?) => { "GPIO33" }; - (LCD_DATA13 $(, $_fallback:literal)?) => { + (LCD_DATA_13 $(, $_fallback:literal)?) => { "GPIO34" }; (USJ_DP $(, $_fallback:literal)?) => { @@ -6101,31 +6515,31 @@ macro_rules! gpio_for_signal { (REF_GMAC_CLK $(, $_fallback:literal)?) => { "GPIO35" }; - (LCD_DATA14 $(, $_fallback:literal)?) => { + (LCD_DATA_14 $(, $_fallback:literal)?) => { "GPIO35" }; (SD2_CDATA0 $(, $_fallback:literal)?) => { "GPIO35" }; - (LCD_DATA15 $(, $_fallback:literal)?) => { + (LCD_DATA_15 $(, $_fallback:literal)?) => { "GPIO36" }; (SD2_CDATA1 $(, $_fallback:literal)?) => { "GPIO36" }; - (LCD_DATA16 $(, $_fallback:literal)?) => { + (LCD_DATA_16 $(, $_fallback:literal)?) => { "GPIO37" }; (SD2_CDATA2 $(, $_fallback:literal)?) => { "GPIO37" }; - (LCD_DATA17 $(, $_fallback:literal)?) => { + (LCD_DATA_17 $(, $_fallback:literal)?) => { "GPIO38" }; (SD2_CDATA3 $(, $_fallback:literal)?) => { "GPIO38" }; - (LCD_DATA18 $(, $_fallback:literal)?) => { + (LCD_DATA_18 $(, $_fallback:literal)?) => { "GPIO39" }; (SD2_CCLK $(, $_fallback:literal)?) => { @@ -6158,49 +6572,49 @@ macro_rules! gpio_for_signal { (ADC1_CH3 $(, $_fallback:literal)?) => { "GPIO45" }; - (CAM_DATA0 $(, $_fallback:literal)?) => { + (CAM_DATA_0 $(, $_fallback:literal)?) => { "GPIO46" }; (ADC1_CH4 $(, $_fallback:literal)?) => { "GPIO46" }; - (CAM_DATA1 $(, $_fallback:literal)?) => { + (CAM_DATA_1 $(, $_fallback:literal)?) => { "GPIO47" }; (ADC1_CH5 $(, $_fallback:literal)?) => { "GPIO47" }; - (CAM_DATA2 $(, $_fallback:literal)?) => { + (CAM_DATA_2 $(, $_fallback:literal)?) => { "GPIO48" }; (ADC1_CH6 $(, $_fallback:literal)?) => { "GPIO48" }; - (CAM_DATA3 $(, $_fallback:literal)?) => { + (CAM_DATA_3 $(, $_fallback:literal)?) => { "GPIO49" }; (ADC1_CH7 $(, $_fallback:literal)?) => { "GPIO49" }; - (CAM_DATA4 $(, $_fallback:literal)?) => { + (CAM_DATA_4 $(, $_fallback:literal)?) => { "GPIO50" }; (ADC2_CH0 $(, $_fallback:literal)?) => { "GPIO50" }; - (CAM_DATA5 $(, $_fallback:literal)?) => { + (CAM_DATA_5 $(, $_fallback:literal)?) => { "GPIO51" }; (ADC2_CH1 $(, $_fallback:literal)?) => { "GPIO51" }; - (CAM_DATA6 $(, $_fallback:literal)?) => { + (CAM_DATA_6 $(, $_fallback:literal)?) => { "GPIO52" }; (ADC2_CH2 $(, $_fallback:literal)?) => { "GPIO52" }; - (CAM_DATA7 $(, $_fallback:literal)?) => { + (CAM_DATA_7 $(, $_fallback:literal)?) => { "GPIO53" }; (ADC2_CH3 $(, $_fallback:literal)?) => { @@ -6330,6 +6744,26 @@ macro_rules! define_io_mux_signals { RMT_SIG_1 = 247, RMT_SIG_2 = 248, RMT_SIG_3 = 249, + CAM_PCLK = 158, + CAM_H_ENABLE = 159, + CAM_H_SYNC = 160, + CAM_V_SYNC = 161, + CAM_DATA_0 = 162, + CAM_DATA_1 = 163, + CAM_DATA_2 = 164, + CAM_DATA_3 = 165, + CAM_DATA_4 = 166, + CAM_DATA_5 = 167, + CAM_DATA_6 = 168, + CAM_DATA_7 = 169, + CAM_DATA_8 = 170, + CAM_DATA_9 = 171, + CAM_DATA_10 = 172, + CAM_DATA_11 = 173, + CAM_DATA_12 = 174, + CAM_DATA_13 = 175, + CAM_DATA_14 = 176, + CAM_DATA_15 = 177, SDHOST_CDATA_IN_41 = 0, SDHOST_CDATA_IN_51 = 1, SDHOST_CDATA_IN_61 = 2, @@ -6380,46 +6814,7 @@ macro_rules! define_io_mux_signals { GMAC_PHY_RXD2, GMAC_PHY_RXD3, REF_GMAC_CLK, - LCD_DATA0, - LCD_DATA1, - LCD_DATA2, - LCD_DATA3, - LCD_DATA4, - LCD_DATA5, - LCD_DATA6, - LCD_DATA7, - LCD_DATA8, - LCD_DATA9, - LCD_DATA10, - LCD_DATA11, - LCD_DATA12, - LCD_DATA13, - LCD_DATA14, - LCD_DATA15, - LCD_DATA16, - LCD_DATA17, - LCD_DATA18, - LCD_DATA19, - LCD_DATA20, - LCD_DATA21, - LCD_DATA22, - LCD_DATA23, - LCD_PCLK, - LCD_H_ENABLE, - LCD_H_SYNC, - LCD_V_SYNC, - CAM_DATA0, - CAM_DATA1, - CAM_DATA2, - CAM_DATA3, - CAM_DATA4, - CAM_DATA5, - CAM_DATA6, - CAM_DATA7, - CAM_PCLK, CAM_XCLK, - CAM_V_SYNC, - CAM_H_SYNC, SD2_CDATA0, SD2_CDATA1, SD2_CDATA2, @@ -6534,6 +6929,37 @@ macro_rules! define_io_mux_signals { RMT_SIG_1 = 247, RMT_SIG_2 = 248, RMT_SIG_3 = 249, + LCD_CS = 144, + LCD_DC = 145, + LCD_PCLK = 149, + CAM_CLK = 150, + LCD_H_ENABLE = 151, + LCD_H_SYNC = 152, + LCD_V_SYNC = 153, + LCD_DATA_0 = 154, + LCD_DATA_1 = 155, + LCD_DATA_2 = 156, + LCD_DATA_3 = 157, + LCD_DATA_4 = 158, + LCD_DATA_5 = 159, + LCD_DATA_6 = 160, + LCD_DATA_7 = 161, + LCD_DATA_8 = 162, + LCD_DATA_9 = 163, + LCD_DATA_10 = 164, + LCD_DATA_11 = 165, + LCD_DATA_12 = 166, + LCD_DATA_13 = 167, + LCD_DATA_14 = 168, + LCD_DATA_15 = 169, + LCD_DATA_16 = 170, + LCD_DATA_17 = 171, + LCD_DATA_18 = 172, + LCD_DATA_19 = 173, + LCD_DATA_20 = 174, + LCD_DATA_21 = 175, + LCD_DATA_22 = 176, + LCD_DATA_23 = 177, GPIO = 256, MTDO, MTCK, @@ -6564,46 +6990,7 @@ macro_rules! define_io_mux_signals { GMAC_PHY_RXD2, GMAC_PHY_RXD3, REF_GMAC_CLK, - LCD_DATA0, - LCD_DATA1, - LCD_DATA2, - LCD_DATA3, - LCD_DATA4, - LCD_DATA5, - LCD_DATA6, - LCD_DATA7, - LCD_DATA8, - LCD_DATA9, - LCD_DATA10, - LCD_DATA11, - LCD_DATA12, - LCD_DATA13, - LCD_DATA14, - LCD_DATA15, - LCD_DATA16, - LCD_DATA17, - LCD_DATA18, - LCD_DATA19, - LCD_DATA20, - LCD_DATA21, - LCD_DATA22, - LCD_DATA23, - LCD_PCLK, - LCD_H_ENABLE, - LCD_H_SYNC, - LCD_V_SYNC, - CAM_DATA0, - CAM_DATA1, - CAM_DATA2, - CAM_DATA3, - CAM_DATA4, - CAM_DATA5, - CAM_DATA6, - CAM_DATA7, - CAM_PCLK, CAM_XCLK, - CAM_V_SYNC, - CAM_H_SYNC, SD2_CDATA0, SD2_CDATA1, SD2_CDATA2, diff --git a/esp-metadata/devices/esp32/soc.toml b/esp-metadata/devices/esp32/soc.toml index 814c4156c1b..8052a3a4314 100644 --- a/esp-metadata/devices/esp32/soc.toml +++ b/esp-metadata/devices/esp32/soc.toml @@ -279,6 +279,7 @@ support_status = "partial" support_status = "not_supported" [device.rgb_display] support_status = "partial" +output_lines = 24 [device.rng] support_status = { status = "partial", issue = 5979 } diff --git a/esp-metadata/devices/esp32p4/soc.toml b/esp-metadata/devices/esp32p4/soc.toml index f3e8724a759..d067cbd42d0 100644 --- a/esp-metadata/devices/esp32p4/soc.toml +++ b/esp-metadata/devices/esp32p4/soc.toml @@ -377,7 +377,8 @@ support_status = "not_supported" # 2 instances (MCPWM0/1) [device.pcnt] support_status = "not_supported" [device.rgb_display] -support_status = "not_supported" # LCD path of LCD_CAM block +support_status = "not_supported" +output_lines = 24 [device.rmt] support_status = "partial" diff --git a/esp-metadata/devices/esp32s2/soc.toml b/esp-metadata/devices/esp32s2/soc.toml index 4c20284329f..20820069006 100644 --- a/esp-metadata/devices/esp32s2/soc.toml +++ b/esp-metadata/devices/esp32s2/soc.toml @@ -303,6 +303,7 @@ support_status = "not_supported" [device.rgb_display] # via I2S support_status = "not_supported" +output_lines = 24 [device.spi_lcd] # the LCD mode of GP-SPI2 support_status = { status = "not_supported", issue = 5374 } diff --git a/esp-metadata/devices/esp32s3/soc.toml b/esp-metadata/devices/esp32s3/soc.toml index e57d23f708e..17a6f4d6861 100644 --- a/esp-metadata/devices/esp32s3/soc.toml +++ b/esp-metadata/devices/esp32s3/soc.toml @@ -404,6 +404,8 @@ instances = [ [device.camera] [device.rgb_display] +output_lines = 16 + [device.ledc] version = 2 channel_count = 8 diff --git a/esp-metadata/devices/esp32s31/clocks.toml b/esp-metadata/devices/esp32s31/clocks.toml index cd162c0840f..dc338679727 100644 --- a/esp-metadata/devices/esp32s31/clocks.toml +++ b/esp-metadata/devices/esp32s31/clocks.toml @@ -114,6 +114,17 @@ system_clocks = { clock_tree = [ { group = "SDM", clocks = [ { name = "FUNCTION_CLOCK", type = "generic", output = "IOMUX_FUNCTION_CLOCK" }, ] }, + # Function clocks live in HP_SYS_CLKRST. The divider register stores N - 1. + { group = "LCD_CAM", clocks = [ + { name = "LCD_CLOCK", type = "generic", wake_locking = true, output = "(sclk * div_a) / (div_num * div_a + div_b)", params = { sclk = [ + { name = "XTAL_CLK", outputs = "XTAL_CLK", default = true }, + { name = "PLL_F160M", outputs = "PLL_F160M" }, + ], div_num = "1 ..= 256", div_a = "1 ..= 255", div_b = "0 ..= 255" } }, + { name = "CAM_CLOCK", type = "generic", wake_locking = true, output = "(sclk * div_a) / (div_num * div_a + div_b)", params = { sclk = [ + { name = "XTAL_CLK", outputs = "XTAL_CLK", default = true }, + { name = "PLL_F160M", outputs = "PLL_F160M" }, + ], div_num = "1 ..= 256", div_a = "1 ..= 255", div_b = "0 ..= 255" } }, + ] }, ] } peripheral_clocks = { templates = [ @@ -171,5 +182,6 @@ peripheral_clocks = { templates = [ rst_template = "crate::peripherals::LP_PERI::regs().adc_ctrl().modify(|_, w| w.lp_adc_rst_en().bit(reset));" } }, { name = "Rmt", template_params = { clk_en = "{{sys_clk}}" } }, + { name = "LcdCam", template_params = { peripheral = "lcdcam", rst_en = ".apb_rst_en().bit(reset).rst_en().bit(reset)" } }, { name = "GpioSd", template_params = { clk_en_template = "crate::peripherals::GPIO_SD::regs().clock_gate().modify(|_, w| w.clk_en().bit(enable));", rst_template = "{{no_rst}}" } }, ] } diff --git a/esp-metadata/devices/esp32s31/gpio.toml b/esp-metadata/devices/esp32s31/gpio.toml index 58a221a4dca..9a95e166a61 100644 --- a/esp-metadata/devices/esp32s31/gpio.toml +++ b/esp-metadata/devices/esp32s31/gpio.toml @@ -7,58 +7,58 @@ constant_0_input = 0xc0 constant_1_input = 0x80 # GPIO29 and GPIO41 are not bonded. pins = [ - { pin = 0, lp = { 0 = "LP_GPIO0" }, analog = { 0 = "XTAL_32K_N" } }, - { pin = 1, lp = { 0 = "LP_GPIO1" }, analog = { 0 = "XTAL_32K_P" } }, - { pin = 2, functions = { 3 = "LCD_DATA19" }, lp = { 0 = "LP_GPIO2" } }, - { pin = 3, functions = { 3 = "LCD_DATA20" }, lp = { 0 = "LP_GPIO3" } }, - { pin = 4, functions = { 3 = "LCD_DATA21" }, lp = { 0 = "LP_GPIO4" } }, - { pin = 5, functions = { 3 = "LCD_DATA22" }, lp = { 0 = "LP_GPIO5" } }, - { pin = 6, lp = { 0 = "LP_GPIO6" } }, - { pin = 7, functions = { 3 = "LCD_DATA23" }, lp = { 0 = "LP_GPIO7" } }, - { pin = 8, functions = { 2 = "GMAC_PHY_TXD0", 3 = "LCD_DATA0" } }, - { pin = 9, functions = { 0 = "FSPIHD", 2 = "GMAC_PHY_TXD1", 3 = "LCD_DATA1", 4 = "DBG_PSRAM_CK" } }, - { pin = 10, functions = { 0 = "FSPICS0", 2 = "GMAC_PHY_TXD2", 3 = "LCD_DATA2", 4 = "DBG_PSRAM_CS" } }, - { pin = 11, functions = { 0 = "FSPID", 2 = "GMAC_PHY_TXD3", 3 = "LCD_DATA3", 4 = "DBG_PSRAM_D" } }, - { pin = 12, functions = { 0 = "FSPICLK", 2 = "GMAC_PHY_TXEN", 3 = "LCD_DATA4", 4 = "DBG_PSRAM_Q" } }, - { pin = 13, functions = { 0 = "FSPIQ", 2 = "GMAC_RMII_CLK", 3 = "LCD_DATA5", 4 = "DBG_PSRAM_WP" } }, - { pin = 14, functions = { 0 = "FSPIWP", 2 = "GMAC_RX_CLK", 3 = "LCD_DATA6", 4 = "DBG_PSRAM_HOLD" } }, - { pin = 15, functions = { 0 = "FSPIIO4", 2 = "GMAC_PHY_RXDV", 3 = "LCD_DATA7", 4 = "DBG_PSRAM_DQ4" } }, - { pin = 16, functions = { 0 = "FSPIIO5", 2 = "GMAC_PHY_RXD3", 3 = "LCD_DATA8", 4 = "DBG_PSRAM_DQ5" } }, - { pin = 17, functions = { 0 = "FSPIIO6", 2 = "GMAC_PHY_RXD2", 3 = "LCD_DATA9", 4 = "DBG_PSRAM_DQ6" } }, - { pin = 18, functions = { 0 = "FSPIIO7", 2 = "GMAC_PHY_RXD1", 3 = "LCD_DATA10", 4 = "DBG_PSRAM_DQ7" } }, - { pin = 19, functions = { 0 = "FSPIDQS", 2 = "GMAC_PHY_RXD0", 3 = "LCD_DATA11", 4 = "DBG_PSRAM_DQS_0" } }, - { pin = 20, functions = { 0 = "SD1_DATA0", 2 = "FSPICLK", 4 = "DBG_FLASH_CK" } }, # SDMMC is CNNT - { pin = 21, functions = { 0 = "SD1_DATA1", 2 = "FSPID", 4 = "DBG_FLASH_D" } }, # SDMMC is CNNT - { pin = 22, functions = { 0 = "SD1_DATA2", 2 = "FSPIQ", 4 = "DBG_FLASH_CS" } }, # SDMMC is CNNT - { pin = 23, functions = { 0 = "SD1_DATA3", 2 = "FSPICS0", 4 = "DBG_FLASH_Q" } }, # SDMMC is CNNT - { pin = 24, functions = { 0 = "SD1_CLK", 2 = "FSPIHD", 4 = "DBG_FLASH_WP" } }, # SDMMC is CNNT - { pin = 25, functions = { 0 = "SD1_CMD", 2 = "FSPIWP", 4 = "DBG_FLASH_HOLD" } }, # SDMMC is CNNT + { pin = 0, lp = { 0 = "LP_GPIO0" }, analog = { 0 = "XTAL_32K_N" } }, + { pin = 1, lp = { 0 = "LP_GPIO1" }, analog = { 0 = "XTAL_32K_P" } }, + { pin = 2, functions = { 3 = "LCD_DATA_19" }, lp = { 0 = "LP_GPIO2" } }, + { pin = 3, functions = { 3 = "LCD_DATA_20" }, lp = { 0 = "LP_GPIO3" } }, + { pin = 4, functions = { 3 = "LCD_DATA_21" }, lp = { 0 = "LP_GPIO4" } }, + { pin = 5, functions = { 3 = "LCD_DATA_22" }, lp = { 0 = "LP_GPIO5" } }, + { pin = 6, lp = { 0 = "LP_GPIO6" } }, + { pin = 7, functions = { 3 = "LCD_DATA_23" }, lp = { 0 = "LP_GPIO7" } }, + { pin = 8, functions = { 2 = "GMAC_PHY_TXD0", 3 = "LCD_DATA_0" } }, + { pin = 9, functions = { 0 = "FSPIHD", 2 = "GMAC_PHY_TXD1", 3 = "LCD_DATA_1", 4 = "DBG_PSRAM_CK" } }, + { pin = 10, functions = { 0 = "FSPICS0", 2 = "GMAC_PHY_TXD2", 3 = "LCD_DATA_2", 4 = "DBG_PSRAM_CS" } }, + { pin = 11, functions = { 0 = "FSPID", 2 = "GMAC_PHY_TXD3", 3 = "LCD_DATA_3", 4 = "DBG_PSRAM_D" } }, + { pin = 12, functions = { 0 = "FSPICLK", 2 = "GMAC_PHY_TXEN", 3 = "LCD_DATA_4", 4 = "DBG_PSRAM_Q" } }, + { pin = 13, functions = { 0 = "FSPIQ", 2 = "GMAC_RMII_CLK", 3 = "LCD_DATA_5", 4 = "DBG_PSRAM_WP" } }, + { pin = 14, functions = { 0 = "FSPIWP", 2 = "GMAC_RX_CLK", 3 = "LCD_DATA_6", 4 = "DBG_PSRAM_HOLD" } }, + { pin = 15, functions = { 0 = "FSPIIO4", 2 = "GMAC_PHY_RXDV", 3 = "LCD_DATA_7", 4 = "DBG_PSRAM_DQ4" } }, + { pin = 16, functions = { 0 = "FSPIIO5", 2 = "GMAC_PHY_RXD3", 3 = "LCD_DATA_8", 4 = "DBG_PSRAM_DQ5" } }, + { pin = 17, functions = { 0 = "FSPIIO6", 2 = "GMAC_PHY_RXD2", 3 = "LCD_DATA_9", 4 = "DBG_PSRAM_DQ6" } }, + { pin = 18, functions = { 0 = "FSPIIO7", 2 = "GMAC_PHY_RXD1", 3 = "LCD_DATA_10", 4 = "DBG_PSRAM_DQ7" } }, + { pin = 19, functions = { 0 = "FSPIDQS", 2 = "GMAC_PHY_RXD0", 3 = "LCD_DATA_11", 4 = "DBG_PSRAM_DQS_0" } }, + { pin = 20, functions = { 0 = "SD1_DATA0", 2 = "FSPICLK", 4 = "DBG_FLASH_CK" } }, # SDMMC is CNNT + { pin = 21, functions = { 0 = "SD1_DATA1", 2 = "FSPID", 4 = "DBG_FLASH_D" } }, # SDMMC is CNNT + { pin = 22, functions = { 0 = "SD1_DATA2", 2 = "FSPIQ", 4 = "DBG_FLASH_CS" } }, # SDMMC is CNNT + { pin = 23, functions = { 0 = "SD1_DATA3", 2 = "FSPICS0", 4 = "DBG_FLASH_Q" } }, # SDMMC is CNNT + { pin = 24, functions = { 0 = "SD1_CLK", 2 = "FSPIHD", 4 = "DBG_FLASH_WP" } }, # SDMMC is CNNT + { pin = 25, functions = { 0 = "SD1_CMD", 2 = "FSPIWP", 4 = "DBG_FLASH_HOLD" } }, # SDMMC is CNNT { pin = 26, functions = { 0 = "SPICS0" }, limitations = ["spi_flash"] }, { pin = 27, functions = { 0 = "SPIQ" }, limitations = ["spi_flash", "strapping"] }, { pin = 28, functions = { 0 = "SPIWP" }, limitations = ["spi_flash", "strapping"] }, { pin = 30, functions = { 0 = "SPIHD" }, limitations = ["spi_flash"] }, { pin = 31, functions = { 0 = "SPICLK" }, limitations = ["spi_flash"] }, { pin = 32, functions = { 0 = "SPID" }, limitations = ["spi_flash"] }, - { pin = 33, functions = { 3 = "LCD_DATA12" }, analog = { 0 = "USJ_DM" } }, - { pin = 34, functions = { 3 = "LCD_DATA13" }, analog = { 0 = "USJ_DP" } }, - { pin = 35, functions = { 2 = "REF_GMAC_CLK", 3 = "LCD_DATA14", 4 = "SD2_CDATA0" } }, - { pin = 36, functions = { 2 = "GMAC_PHY_RXDV", 3 = "LCD_DATA15", 4 = "SD2_CDATA1" }, limitations = ["strapping"] }, - { pin = 37, functions = { 2 = "GMAC_PHY_TXEN", 3 = "LCD_DATA16", 4 = "SD2_CDATA2" }, limitations = ["strapping"] }, - { pin = 38, functions = { 2 = "GMAC_PHY_RXD3", 3 = "LCD_DATA17", 4 = "SD2_CDATA3" }, limitations = ["strapping"] }, - { pin = 39, functions = { 2 = "GMAC_PHY_RXD2", 3 = "LCD_DATA18", 4 = "SD2_CCLK" }, limitations = ["strapping"] }, - { pin = 40, functions = { 2 = "GMAC_PHY_RXD1", 3 = "LCD_PCLK", 4 = "SD2_CCMD" }, limitations = ["strapping"] }, + { pin = 33, functions = { 3 = "LCD_DATA_12" }, analog = { 0 = "USJ_DM" } }, + { pin = 34, functions = { 3 = "LCD_DATA_13" }, analog = { 0 = "USJ_DP" } }, + { pin = 35, functions = { 2 = "REF_GMAC_CLK", 3 = "LCD_DATA_14", 4 = "SD2_CDATA0" } }, + { pin = 36, functions = { 2 = "GMAC_PHY_RXDV", 3 = "LCD_DATA_15", 4 = "SD2_CDATA1" }, limitations = ["strapping"] }, + { pin = 37, functions = { 2 = "GMAC_PHY_TXEN", 3 = "LCD_DATA_16", 4 = "SD2_CDATA2" }, limitations = ["strapping"] }, + { pin = 38, functions = { 2 = "GMAC_PHY_RXD3", 3 = "LCD_DATA_17", 4 = "SD2_CDATA3" }, limitations = ["strapping"] }, + { pin = 39, functions = { 2 = "GMAC_PHY_RXD2", 3 = "LCD_DATA_18", 4 = "SD2_CCLK" }, limitations = ["strapping"] }, + { pin = 40, functions = { 2 = "GMAC_PHY_RXD1", 3 = "LCD_PCLK", 4 = "SD2_CCMD" }, limitations = ["strapping"] }, { pin = 42, functions = { 2 = "GMAC_RX_CLK" }, analog = { 1 = "ADC1_CH0" } }, { pin = 43, functions = { 2 = "GMAC_RMII_CLK", 3 = "LCD_H_ENABLE" }, analog = { 1 = "ADC1_CH1" } }, { pin = 44, functions = { 2 = "GMAC_PHY_TXD0", 3 = "LCD_H_SYNC" }, analog = { 1 = "ADC1_CH2" } }, { pin = 45, functions = { 2 = "GMAC_PHY_TXD1", 3 = "LCD_V_SYNC" }, analog = { 1 = "ADC1_CH3" } }, - { pin = 46, functions = { 2 = "GMAC_PHY_TXD2", 3 = "CAM_DATA0" }, analog = { 1 = "ADC1_CH4" } }, - { pin = 47, functions = { 2 = "GMAC_PHY_TXD3", 3 = "CAM_DATA1" }, analog = { 1 = "ADC1_CH5" } }, - { pin = 48, functions = { 3 = "CAM_DATA2" }, analog = { 1 = "ADC1_CH6" } }, - { pin = 49, functions = { 3 = "CAM_DATA3" }, analog = { 1 = "ADC1_CH7" } }, - { pin = 50, functions = { 3 = "CAM_DATA4" }, analog = { 1 = "ADC2_CH0" } }, - { pin = 51, functions = { 3 = "CAM_DATA5" }, analog = { 1 = "ADC2_CH1" } }, - { pin = 52, functions = { 2 = "FSPICS0", 3 = "CAM_DATA6" }, analog = { 1 = "ADC2_CH2" } }, - { pin = 53, functions = { 2 = "FSPICLK", 3 = "CAM_DATA7" }, analog = { 1 = "ADC2_CH3" } }, + { pin = 46, functions = { 2 = "GMAC_PHY_TXD2", 3 = "CAM_DATA_0" }, analog = { 1 = "ADC1_CH4" } }, + { pin = 47, functions = { 2 = "GMAC_PHY_TXD3", 3 = "CAM_DATA_1" }, analog = { 1 = "ADC1_CH5" } }, + { pin = 48, functions = { 3 = "CAM_DATA_2" }, analog = { 1 = "ADC1_CH6" } }, + { pin = 49, functions = { 3 = "CAM_DATA_3" }, analog = { 1 = "ADC1_CH7" } }, + { pin = 50, functions = { 3 = "CAM_DATA_4" }, analog = { 1 = "ADC2_CH0" } }, + { pin = 51, functions = { 3 = "CAM_DATA_5" }, analog = { 1 = "ADC2_CH1" } }, + { pin = 52, functions = { 2 = "FSPICS0", 3 = "CAM_DATA_6" }, analog = { 1 = "ADC2_CH2" } }, + { pin = 53, functions = { 2 = "FSPICLK", 3 = "CAM_DATA_7" }, analog = { 1 = "ADC2_CH3" } }, { pin = 54, functions = { 0 = "MTDO", 2 = "FSPID", 3 = "CAM_PCLK" }, analog = { 1 = "ADC2_CH4" }, limitations = ["jtag"] }, { pin = 55, functions = { 0 = "MTCK", 2 = "FSPIQ", 3 = "CAM_XCLK" }, analog = { 1 = "ADC2_CH5" }, limitations = ["jtag"] }, { pin = 56, functions = { 0 = "MTDI", 2 = "FSPIHD", 3 = "CAM_V_SYNC" }, analog = { 1 = "ADC2_CH6" }, limitations = ["jtag"] }, @@ -143,6 +143,27 @@ input_signals = [ { name = "RMT_SIG_1", id = 247 }, { name = "RMT_SIG_2", id = 248 }, { name = "RMT_SIG_3", id = 249 }, + # LCD_CAM + { name = "CAM_PCLK", id = 158 }, + { name = "CAM_H_ENABLE", id = 159 }, + { name = "CAM_H_SYNC", id = 160 }, + { name = "CAM_V_SYNC", id = 161 }, + { name = "CAM_DATA_0", id = 162 }, + { name = "CAM_DATA_1", id = 163 }, + { name = "CAM_DATA_2", id = 164 }, + { name = "CAM_DATA_3", id = 165 }, + { name = "CAM_DATA_4", id = 166 }, + { name = "CAM_DATA_5", id = 167 }, + { name = "CAM_DATA_6", id = 168 }, + { name = "CAM_DATA_7", id = 169 }, + { name = "CAM_DATA_8", id = 170 }, + { name = "CAM_DATA_9", id = 171 }, + { name = "CAM_DATA_10", id = 172 }, + { name = "CAM_DATA_11", id = 173 }, + { name = "CAM_DATA_12", id = 174 }, + { name = "CAM_DATA_13", id = 175 }, + { name = "CAM_DATA_14", id = 176 }, + { name = "CAM_DATA_15", id = 177 }, # SDMMC { name = "SDHOST_CDATA_IN_41", id = 0 }, { name = "SDHOST_CDATA_IN_51", id = 1 }, @@ -198,46 +219,7 @@ input_signals = [ { name = "GMAC_PHY_RXD2" }, { name = "GMAC_PHY_RXD3" }, { name = "REF_GMAC_CLK" }, - { name = "LCD_DATA0" }, - { name = "LCD_DATA1" }, - { name = "LCD_DATA2" }, - { name = "LCD_DATA3" }, - { name = "LCD_DATA4" }, - { name = "LCD_DATA5" }, - { name = "LCD_DATA6" }, - { name = "LCD_DATA7" }, - { name = "LCD_DATA8" }, - { name = "LCD_DATA9" }, - { name = "LCD_DATA10" }, - { name = "LCD_DATA11" }, - { name = "LCD_DATA12" }, - { name = "LCD_DATA13" }, - { name = "LCD_DATA14" }, - { name = "LCD_DATA15" }, - { name = "LCD_DATA16" }, - { name = "LCD_DATA17" }, - { name = "LCD_DATA18" }, - { name = "LCD_DATA19" }, - { name = "LCD_DATA20" }, - { name = "LCD_DATA21" }, - { name = "LCD_DATA22" }, - { name = "LCD_DATA23" }, - { name = "LCD_PCLK" }, - { name = "LCD_H_ENABLE" }, - { name = "LCD_H_SYNC" }, - { name = "LCD_V_SYNC" }, - { name = "CAM_DATA0" }, - { name = "CAM_DATA1" }, - { name = "CAM_DATA2" }, - { name = "CAM_DATA3" }, - { name = "CAM_DATA4" }, - { name = "CAM_DATA5" }, - { name = "CAM_DATA6" }, - { name = "CAM_DATA7" }, - { name = "CAM_PCLK" }, { name = "CAM_XCLK" }, - { name = "CAM_V_SYNC" }, - { name = "CAM_H_SYNC" }, { name = "SD2_CDATA0" }, { name = "SD2_CDATA1" }, { name = "SD2_CDATA2" }, @@ -357,6 +339,38 @@ output_signals = [ { name = "RMT_SIG_1", id = 247 }, { name = "RMT_SIG_2", id = 248 }, { name = "RMT_SIG_3", id = 249 }, + # LCD_CAM + { name = "LCD_CS", id = 144 }, + { name = "LCD_DC", id = 145 }, + { name = "LCD_PCLK", id = 149 }, + { name = "CAM_CLK", id = 150 }, + { name = "LCD_H_ENABLE", id = 151 }, + { name = "LCD_H_SYNC", id = 152 }, + { name = "LCD_V_SYNC", id = 153 }, + { name = "LCD_DATA_0", id = 154 }, + { name = "LCD_DATA_1", id = 155 }, + { name = "LCD_DATA_2", id = 156 }, + { name = "LCD_DATA_3", id = 157 }, + { name = "LCD_DATA_4", id = 158 }, + { name = "LCD_DATA_5", id = 159 }, + { name = "LCD_DATA_6", id = 160 }, + { name = "LCD_DATA_7", id = 161 }, + { name = "LCD_DATA_8", id = 162 }, + { name = "LCD_DATA_9", id = 163 }, + { name = "LCD_DATA_10", id = 164 }, + { name = "LCD_DATA_11", id = 165 }, + { name = "LCD_DATA_12", id = 166 }, + { name = "LCD_DATA_13", id = 167 }, + { name = "LCD_DATA_14", id = 168 }, + { name = "LCD_DATA_15", id = 169 }, + { name = "LCD_DATA_16", id = 170 }, + { name = "LCD_DATA_17", id = 171 }, + { name = "LCD_DATA_18", id = 172 }, + { name = "LCD_DATA_19", id = 173 }, + { name = "LCD_DATA_20", id = 174 }, + { name = "LCD_DATA_21", id = 175 }, + { name = "LCD_DATA_22", id = 176 }, + { name = "LCD_DATA_23", id = 177 }, # GPIO passthrough { name = "GPIO", id = 256 }, @@ -390,46 +404,7 @@ output_signals = [ { name = "GMAC_PHY_RXD2" }, { name = "GMAC_PHY_RXD3" }, { name = "REF_GMAC_CLK" }, - { name = "LCD_DATA0" }, - { name = "LCD_DATA1" }, - { name = "LCD_DATA2" }, - { name = "LCD_DATA3" }, - { name = "LCD_DATA4" }, - { name = "LCD_DATA5" }, - { name = "LCD_DATA6" }, - { name = "LCD_DATA7" }, - { name = "LCD_DATA8" }, - { name = "LCD_DATA9" }, - { name = "LCD_DATA10" }, - { name = "LCD_DATA11" }, - { name = "LCD_DATA12" }, - { name = "LCD_DATA13" }, - { name = "LCD_DATA14" }, - { name = "LCD_DATA15" }, - { name = "LCD_DATA16" }, - { name = "LCD_DATA17" }, - { name = "LCD_DATA18" }, - { name = "LCD_DATA19" }, - { name = "LCD_DATA20" }, - { name = "LCD_DATA21" }, - { name = "LCD_DATA22" }, - { name = "LCD_DATA23" }, - { name = "LCD_PCLK" }, - { name = "LCD_H_ENABLE" }, - { name = "LCD_H_SYNC" }, - { name = "LCD_V_SYNC" }, - { name = "CAM_DATA0" }, - { name = "CAM_DATA1" }, - { name = "CAM_DATA2" }, - { name = "CAM_DATA3" }, - { name = "CAM_DATA4" }, - { name = "CAM_DATA5" }, - { name = "CAM_DATA6" }, - { name = "CAM_DATA7" }, - { name = "CAM_PCLK" }, { name = "CAM_XCLK" }, - { name = "CAM_V_SYNC" }, - { name = "CAM_H_SYNC" }, { name = "SD2_CDATA0" }, { name = "SD2_CDATA1" }, { name = "SD2_CDATA2" }, diff --git a/esp-metadata/devices/esp32s31/soc.toml b/esp-metadata/devices/esp32s31/soc.toml index 135a41cf2cd..4ffc22cac3f 100644 --- a/esp-metadata/devices/esp32s31/soc.toml +++ b/esp-metadata/devices/esp32s31/soc.toml @@ -61,6 +61,7 @@ peripherals = [ { name = "HP_SYS_CLKRST" }, { name = "I2C0", interrupts = { peri = "I2C0" }, clock_group = "I2C", stable = true }, { name = "I2C1", interrupts = { peri = "I2C1" }, clock_group = "I2C", stable = true }, + { name = "LCD_CAM", interrupts = { peri = "LCD_CAM" }, clock_group = "LCD_CAM" }, { name = "INTERRUPT_CORE0" }, { name = "INTERRUPT_CORE1" }, { name = "IO_MUX" }, @@ -277,9 +278,9 @@ engines = [ name = "AXI_GDMA", max_priority = 15, burst_sizes = [8, 16, 32, 64, 128], - drivers = ["spi_master", "aes"], + drivers = ["spi_master", "aes", "lcd_cam"], peripheral_instances = [ - # LCD_CAM + { name = "LCD_CAM", dma_id = 0 }, { name = "SPI2", dma_id = 1 }, { name = "SPI3", dma_id = 2 }, # PARL_IO @@ -349,13 +350,6 @@ algo = { # TODO: sm3 = 14 } -[device.hmac] -support_status = "not_supported" -[device.ds] -support_status = "not_supported" -[device.ecdsa] -support_status = "not_supported" - [device.adc] support_status = "partial" instances = [ @@ -363,51 +357,20 @@ instances = [ { name = "adc2" }, ] -# Peripherals the chip has, that no driver reaches yet. -[device.avc] -support_status = "not_supported" -[device.bit_scrambler] -support_status = "not_supported" [device.camera] -support_status = "not_supported" -[device.dac] -support_status = "not_supported" -[device.ethernet] -support_status = "not_supported" -[device.etm] -support_status = "not_supported" -[device.i2c_slave] -support_status = "not_supported" -[device.i2s] -support_status = "not_supported" -[device.ieee802154] -support_status = "not_supported" -[device.key_manager] -support_status = "not_supported" -[device.mcpwm] -support_status = "not_supported" -[device.pcnt] -support_status = "not_supported" +support_status = "partial" + [device.rgb_display] -support_status = "not_supported" +support_status = "partial" +output_lines = 24 [device.sdm] support_status = "partial" channel_count = 8 -[device.temp_sensor] -support_status = "not_supported" -[device.touch] -support_status = "not_supported" -[device.canfd] -support_status = "not_supported" [device.uhci] support_status = "partial" combined_uart_selector_field = true -[device.ulp_riscv] -support_status = "not_supported" -[device.usb_serial_jtag] -support_status = "not_supported" [device.rmt] support_status = "partial" @@ -422,10 +385,6 @@ has_tx_sync = true has_rx_wrap = true has_rx_demodulation = true -[device.parl_io] -support_status = "not_supported" -version = 1 # FIXME placeholder - [device.sdmmc] support_status = "partial" delay_phase_num = 8 # FIXME: placeholder @@ -452,6 +411,55 @@ slot_config = [ } ] +[device.psram] +support_status = "partial" +extmem_origin = 0x5000_0000 +octal_spi = true + +# Peripherals the chip has, that no driver reaches yet. +[device.hmac] +support_status = "not_supported" +[device.ds] +support_status = "not_supported" +[device.ecdsa] +support_status = "not_supported" +[device.parl_io] +support_status = "not_supported" +version = 1 # FIXME placeholder +[device.avc] +support_status = "not_supported" +[device.bit_scrambler] +support_status = "not_supported" +[device.dac] +support_status = "not_supported" +[device.ethernet] +support_status = "not_supported" +[device.etm] +support_status = "not_supported" +[device.i2c_slave] +support_status = "not_supported" +[device.i2s] +support_status = "not_supported" +[device.ieee802154] +support_status = "not_supported" +[device.key_manager] +support_status = "not_supported" +[device.mcpwm] +support_status = "not_supported" +[device.pcnt] +support_status = "not_supported" + +[device.temp_sensor] +support_status = "not_supported" +[device.touch] +support_status = "not_supported" +[device.canfd] +support_status = "not_supported" +[device.ulp_riscv] +support_status = "not_supported" +[device.usb_serial_jtag] +support_status = "not_supported" + ## Radio [device.wifi] support_status = "not_supported" @@ -474,10 +482,6 @@ channel_count = 8 support_status = "not_supported" ram_size = 20 # FIXME: placeholder -[device.psram] -extmem_origin = 0x5000_0000 -octal_spi = true - [device.pixel_accelerator] support_status = "not_supported" diff --git a/esp-metadata/src/cfg.rs b/esp-metadata/src/cfg.rs index 78af7402eed..c2c6f49103e 100644 --- a/esp-metadata/src/cfg.rs +++ b/esp-metadata/src/cfg.rs @@ -666,7 +666,9 @@ driver_configs![ RgbProperties { driver: rgb_display, name: "RGB display", // LCD_CAM, ESP32 I2S, S2 I2S - properties: {} + properties: { + output_lines: u32, + } }, SpiLcdProperties { driver: spi_lcd, diff --git a/hil-test/src/bin/lcd_cam.rs b/hil-test/src/bin/lcd_cam.rs index bd3ab8858f1..3071697022b 100644 --- a/hil-test/src/bin/lcd_cam.rs +++ b/hil-test/src/bin/lcd_cam.rs @@ -1,19 +1,26 @@ //! lcd_cam_i8080 and camera tests +//! +//! Camera/DPI loopback uses GPIO `split()` (no jumpers). +//! ESP32-S31 avoids USB Serial/JTAG (GPIO13/14), Ethernet RGMII (GPIO8-19), +//! and the CI GPIO2-GPIO3 tie. //% CHIP_FILTER: camera_driver_supported -//% FEATURES: unstable +//% FEATURES: unstable defmt #![no_std] #![no_main] +#[cfg(pcnt_driver_supported)] +use esp_hal::pcnt::{ + Pcnt, + channel::{CtrlMode, EdgeMode}, +}; use esp_hal::{ Async, - Blocking, dma::{DmaChannel, DmaRxBuf, DmaTxBuf}, dma_rx_buffer, dma_tx_buffer, gpio::Level, lcd_cam::{ - BitOrder, LcdCam, cam::{self, Camera, VhdeMode}, lcd::{ @@ -24,362 +31,362 @@ use esp_hal::{ i8080::{Command, Config, I8080}, }, }, - pcnt::{ - Pcnt, - channel::{CtrlMode, EdgeMode}, - }, - peripherals::{DMA_CH0, Peripherals}, + peripherals::Peripherals, time::Rate, }; use hil_test as _; const DATA_SIZE: usize = 1024 * 10; -#[allow(non_snake_case)] -struct Pins { - pub GPIO8: esp_hal::peripherals::GPIO8<'static>, - pub GPIO11: esp_hal::peripherals::GPIO11<'static>, - pub GPIO12: esp_hal::peripherals::GPIO12<'static>, - pub GPIO16: esp_hal::peripherals::GPIO16<'static>, - pub GPIO17: esp_hal::peripherals::GPIO17<'static>, -} - -struct AsyncContext<'d> { - lcd_cam: LcdCam<'d, Async>, - dma: DMA_CH0<'d>, - dma_buf: DmaTxBuf, -} - -struct BlockingContext<'d> { - lcd_cam: LcdCam<'d, Blocking>, - pcnt: Pcnt<'d>, - pins: Pins, - dma: DMA_CH0<'d>, - dma_buf: DmaTxBuf, -} +cfg_select! { + lcd_cam_dma_engine = "AHB_GDMA" => { + use esp_hal::peripherals::DMA_CH0 as DmaChannelInstance; + } -struct CameraContext { - peripherals: Peripherals, - dma_tx_buf: DmaTxBuf, - dma_rx_buf: DmaRxBuf, + lcd_cam_dma_engine = "AXI_GDMA" => { + use esp_hal::peripherals::DMA_AXI_CH0 as DmaChannelInstance; + } } // lcd_cam_i8080 tests +#[embedded_test::tests(default_timeout = 3, executor = hil_test::Executor::new())] mod async_tests { use super::*; - #[embedded_test::tests(default_timeout = 3, executor = hil_test::Executor::new())] - mod tests { - use super::*; - - #[init] - async fn init() -> AsyncContext<'static> { - let peripherals = esp_hal::init(esp_hal::Config::default()); - let lcd_cam = LcdCam::new(peripherals.LCD_CAM).into_async(); - let dma_buf = dma_tx_buffer!(DATA_SIZE).unwrap(); + struct Context<'d> { + lcd_cam: LcdCam<'d, Async>, + dma: DmaChannelInstance<'d>, + dma_buf: DmaTxBuf, + } - AsyncContext { - lcd_cam, - dma: peripherals.DMA_CH0, - dma_buf, - } + #[init] + async fn init() -> Context<'static> { + let peripherals = esp_hal::init(esp_hal::Config::default()); + let lcd_cam = LcdCam::new(peripherals.LCD_CAM).into_async(); + let dma_buf = dma_tx_buffer!(DATA_SIZE).unwrap(); + let dma_channel = cfg_select! { + lcd_cam_dma_engine = "AHB_GDMA" => peripherals.DMA_CH0, + lcd_cam_dma_engine = "AXI_GDMA" => peripherals.DMA_AXI_CH0, + }; + + Context { + lcd_cam, + dma: dma_channel, + dma_buf, } + } - #[test] - async fn test_i8080_8bit(ctx: AsyncContext<'static>) { - let i8080 = I8080::new( - ctx.lcd_cam.lcd, - ctx.dma, - Config::default().with_frequency(Rate::from_mhz(20)), - ) - .unwrap(); - - core::mem::drop(ctx.lcd_cam.cam); - let mut transfer = i8080.send(Command::::None, 0, ctx.dma_buf).unwrap(); - - transfer.wait_for_done().await; - transfer.wait_for_done().await; - transfer.wait().0.unwrap(); - } + #[test] + async fn test_i8080_8bit(ctx: Context<'static>) { + let i8080 = I8080::new( + ctx.lcd_cam.lcd, + ctx.dma, + Config::default().with_frequency(Rate::from_mhz(20)), + ) + .unwrap(); + + core::mem::drop(ctx.lcd_cam.cam); + let mut transfer = i8080.send(Command::::None, 0, ctx.dma_buf).unwrap(); + + transfer.wait_for_done().await; + transfer.wait_for_done().await; + transfer.wait().0.unwrap(); } } // lcd_cam_i8080 tests +#[cfg(pcnt_driver_supported)] +#[embedded_test::tests(default_timeout = 3)] mod blocking_tests { + use esp_hal::{Blocking, gpio::AnyPin, lcd_cam::BitOrder}; + use super::*; - #[embedded_test::tests(default_timeout = 3)] - mod tests { - use super::*; - - #[init] - fn init() -> BlockingContext<'static> { - let peripherals = esp_hal::init(esp_hal::Config::default()); - let lcd_cam = LcdCam::new(peripherals.LCD_CAM); - let pcnt = Pcnt::new(peripherals.PCNT); - let dma_buf = dma_tx_buffer!(DATA_SIZE).unwrap(); - - BlockingContext { - lcd_cam, - dma: peripherals.DMA_CH0, - pcnt, - pins: Pins { - GPIO8: peripherals.GPIO8, - GPIO11: peripherals.GPIO11, - GPIO12: peripherals.GPIO12, - GPIO16: peripherals.GPIO16, - GPIO17: peripherals.GPIO17, - }, - dma_buf, - } - } + struct Context<'d> { + lcd_cam: LcdCam<'d, Blocking>, + pcnt: Pcnt<'d>, + pins: [AnyPin<'d>; 5], + dma: DmaChannelInstance<'d>, + dma_buf: DmaTxBuf, + } - #[test] - fn test_i8080_8bit(ctx: BlockingContext<'static>) { - let i8080 = I8080::new( - ctx.lcd_cam.lcd, - ctx.dma, - Config::default().with_frequency(Rate::from_mhz(20)), - ) - .unwrap(); - - let xfer = i8080.send(Command::::None, 0, ctx.dma_buf).unwrap(); - xfer.wait().0.unwrap(); + #[init] + fn init() -> Context<'static> { + let peripherals = esp_hal::init(esp_hal::Config::default()); + let lcd_cam = LcdCam::new(peripherals.LCD_CAM); + let pcnt = Pcnt::new(peripherals.PCNT); + let dma_buf = dma_tx_buffer!(DATA_SIZE).unwrap(); + + Context { + lcd_cam, + dma: peripherals.DMA_CH0, + pcnt, + pins: [ + peripherals.GPIO8.into(), + peripherals.GPIO11.into(), + peripherals.GPIO12.into(), + peripherals.GPIO16.into(), + peripherals.GPIO17.into(), + ], + dma_buf, } + } - #[test] - fn test_i8080_8bit_is_seen_by_pcnt(ctx: BlockingContext<'static>) { - let (unit_ctrl, cs_signal) = unsafe { ctx.pins.GPIO8.split() }; - let (unit0_input, unit0_signal) = unsafe { ctx.pins.GPIO11.split() }; - let (unit1_input, unit1_signal) = unsafe { ctx.pins.GPIO12.split() }; - let (unit2_input, unit2_signal) = unsafe { ctx.pins.GPIO16.split() }; - let (unit3_input, unit3_signal) = unsafe { ctx.pins.GPIO17.split() }; - - let pcnt = ctx.pcnt; - pcnt.unit0 - .channel0 - .set_ctrl_mode(CtrlMode::Keep, CtrlMode::Disable); - pcnt.unit1 - .channel0 - .set_ctrl_mode(CtrlMode::Keep, CtrlMode::Disable); - pcnt.unit2 - .channel0 - .set_ctrl_mode(CtrlMode::Keep, CtrlMode::Disable); - pcnt.unit3 - .channel0 - .set_ctrl_mode(CtrlMode::Keep, CtrlMode::Disable); - - pcnt.unit0 - .channel0 - .set_input_mode(EdgeMode::Hold, EdgeMode::Increment); - pcnt.unit1 - .channel0 - .set_input_mode(EdgeMode::Hold, EdgeMode::Increment); - pcnt.unit2 - .channel0 - .set_input_mode(EdgeMode::Hold, EdgeMode::Increment); - pcnt.unit3 - .channel0 - .set_input_mode(EdgeMode::Hold, EdgeMode::Increment); - - let mut i8080 = I8080::new( - ctx.lcd_cam.lcd, - ctx.dma, - Config::default().with_frequency(Rate::from_mhz(20)), - ) - .unwrap() - .with_cs(cs_signal) - .with_data0(unit0_signal) - .with_data1(unit1_signal) - .with_data2(unit2_signal) - .with_data3(unit3_signal); - - core::mem::drop(ctx.lcd_cam.cam); - i8080.set_bit_order(BitOrder::Inverted); - - pcnt.unit0.channel0.set_edge_signal(unit0_input); - pcnt.unit1.channel0.set_edge_signal(unit1_input); - pcnt.unit2.channel0.set_edge_signal(unit2_input); - pcnt.unit3.channel0.set_edge_signal(unit3_input); - - pcnt.unit0.channel0.set_ctrl_signal(unit_ctrl.clone()); - pcnt.unit1.channel0.set_ctrl_signal(unit_ctrl.clone()); - pcnt.unit2.channel0.set_ctrl_signal(unit_ctrl.clone()); - pcnt.unit3.channel0.set_ctrl_signal(unit_ctrl.clone()); - - pcnt.unit0.resume(); - pcnt.unit1.resume(); - pcnt.unit2.resume(); - pcnt.unit3.resume(); - - let data_to_send = [ - 0b0000_0000, - 0b1010_0000, - 0b0110_0000, - 0b1110_0000, - 0b0000_0000, - 0b1000_0000, - 0b0100_0000, - 0b1010_0000, - 0b0101_0000, - 0b1000_0000, - ]; - - let mut dma_buf = ctx.dma_buf; - dma_buf.as_mut_slice().fill(0); - dma_buf.as_mut_slice()[..data_to_send.len()].copy_from_slice(&data_to_send); - - let xfer = i8080.send(Command::::None, 0, dma_buf).unwrap(); - xfer.wait().0.unwrap(); - - let actual = [ - pcnt.unit0.value(), - pcnt.unit1.value(), - pcnt.unit2.value(), - pcnt.unit3.value(), - ]; - assert_eq!([5, 3, 2, 1], actual); - } + #[test] + fn test_i8080_8bit(ctx: Context<'static>) { + let i8080 = I8080::new( + ctx.lcd_cam.lcd, + ctx.dma, + Config::default().with_frequency(Rate::from_mhz(20)), + ) + .unwrap(); + + let xfer = i8080.send(Command::::None, 0, ctx.dma_buf).unwrap(); + xfer.wait().0.unwrap(); + } - #[test] - fn test_i8080_16bit_is_seen_by_pcnt(ctx: BlockingContext<'static>) { - let (unit_ctrl, cs_signal) = unsafe { ctx.pins.GPIO8.split() }; - let (unit0_input, unit0_signal) = unsafe { ctx.pins.GPIO11.split() }; - let (unit1_input, unit1_signal) = unsafe { ctx.pins.GPIO12.split() }; - let (unit2_input, unit2_signal) = unsafe { ctx.pins.GPIO16.split() }; - let (unit3_input, unit3_signal) = unsafe { ctx.pins.GPIO17.split() }; - - let pcnt = ctx.pcnt; - pcnt.unit0 - .channel0 - .set_ctrl_mode(CtrlMode::Keep, CtrlMode::Disable); - pcnt.unit1 - .channel0 - .set_ctrl_mode(CtrlMode::Keep, CtrlMode::Disable); - pcnt.unit2 - .channel0 - .set_ctrl_mode(CtrlMode::Keep, CtrlMode::Disable); - pcnt.unit3 - .channel0 - .set_ctrl_mode(CtrlMode::Keep, CtrlMode::Disable); - - pcnt.unit0 - .channel0 - .set_input_mode(EdgeMode::Hold, EdgeMode::Increment); - pcnt.unit1 - .channel0 - .set_input_mode(EdgeMode::Hold, EdgeMode::Increment); - pcnt.unit2 - .channel0 - .set_input_mode(EdgeMode::Hold, EdgeMode::Increment); - pcnt.unit3 - .channel0 - .set_input_mode(EdgeMode::Hold, EdgeMode::Increment); - - let mut i8080 = I8080::new( - ctx.lcd_cam.lcd, - ctx.dma, - Config::default().with_frequency(Rate::from_mhz(20)), - ) - .unwrap() - .with_cs(cs_signal) - .with_data3(unit0_signal) - .with_data7(unit1_signal) - .with_data11(unit2_signal) - .with_data15(unit3_signal); - - i8080.set_bit_order(BitOrder::Inverted); - - pcnt.unit0.channel0.set_edge_signal(unit0_input); - pcnt.unit1.channel0.set_edge_signal(unit1_input); - pcnt.unit2.channel0.set_edge_signal(unit2_input); - pcnt.unit3.channel0.set_edge_signal(unit3_input); - - pcnt.unit0.channel0.set_ctrl_signal(unit_ctrl.clone()); - pcnt.unit1.channel0.set_ctrl_signal(unit_ctrl.clone()); - pcnt.unit2.channel0.set_ctrl_signal(unit_ctrl.clone()); - pcnt.unit3.channel0.set_ctrl_signal(unit_ctrl.clone()); - - pcnt.unit0.resume(); - pcnt.unit1.resume(); - pcnt.unit2.resume(); - pcnt.unit3.resume(); - - let data_to_send = [ - 0b0000_0000_0000_0000u16, - 0b0001_0000_0001_0000, - 0b0000_0001_0001_0000, - 0b0001_0001_0001_0000, - 0b0000_0000_0000_0000, - 0b0001_0000_0000_0000, - 0b0000_0001_0000_0000, - 0b0001_0000_0001_0000, - 0b0000_0001_0000_0001, - 0b0001_0000_0000_0000, - ]; - - let mut dma_buf = ctx.dma_buf; - dma_buf - .as_mut_slice() - .iter_mut() - .zip(data_to_send.iter().flat_map(|&d| d.to_ne_bytes())) - .for_each(|(d, s)| *d = s); - - let xfer = i8080.send(Command::::None, 0, dma_buf).unwrap(); - xfer.wait().0.unwrap(); - - let actual = [ - pcnt.unit0.value(), - pcnt.unit1.value(), - pcnt.unit2.value(), - pcnt.unit3.value(), - ]; - assert_eq!([5, 3, 2, 1], actual); - } + #[test] + fn test_i8080_8bit_is_seen_by_pcnt(ctx: Context<'static>) { + let [ctrl, u0, u1, u2, u3] = ctx.pins; + let (unit_ctrl, cs_signal) = unsafe { ctrl.split() }; + let (unit0_input, unit0_signal) = unsafe { u0.split() }; + let (unit1_input, unit1_signal) = unsafe { u1.split() }; + let (unit2_input, unit2_signal) = unsafe { u2.split() }; + let (unit3_input, unit3_signal) = unsafe { u3.split() }; + + let pcnt = ctx.pcnt; + pcnt.unit0 + .channel0 + .set_ctrl_mode(CtrlMode::Keep, CtrlMode::Disable); + pcnt.unit1 + .channel0 + .set_ctrl_mode(CtrlMode::Keep, CtrlMode::Disable); + pcnt.unit2 + .channel0 + .set_ctrl_mode(CtrlMode::Keep, CtrlMode::Disable); + pcnt.unit3 + .channel0 + .set_ctrl_mode(CtrlMode::Keep, CtrlMode::Disable); + + pcnt.unit0 + .channel0 + .set_input_mode(EdgeMode::Hold, EdgeMode::Increment); + pcnt.unit1 + .channel0 + .set_input_mode(EdgeMode::Hold, EdgeMode::Increment); + pcnt.unit2 + .channel0 + .set_input_mode(EdgeMode::Hold, EdgeMode::Increment); + pcnt.unit3 + .channel0 + .set_input_mode(EdgeMode::Hold, EdgeMode::Increment); + + let mut i8080 = I8080::new( + ctx.lcd_cam.lcd, + ctx.dma, + Config::default().with_frequency(Rate::from_mhz(20)), + ) + .unwrap() + .with_cs(cs_signal) + .with_data0(unit0_signal) + .with_data1(unit1_signal) + .with_data2(unit2_signal) + .with_data3(unit3_signal); + + core::mem::drop(ctx.lcd_cam.cam); + i8080.set_bit_order(BitOrder::Inverted); + + pcnt.unit0.channel0.set_edge_signal(unit0_input); + pcnt.unit1.channel0.set_edge_signal(unit1_input); + pcnt.unit2.channel0.set_edge_signal(unit2_input); + pcnt.unit3.channel0.set_edge_signal(unit3_input); + + pcnt.unit0.channel0.set_ctrl_signal(unit_ctrl.clone()); + pcnt.unit1.channel0.set_ctrl_signal(unit_ctrl.clone()); + pcnt.unit2.channel0.set_ctrl_signal(unit_ctrl.clone()); + pcnt.unit3.channel0.set_ctrl_signal(unit_ctrl.clone()); + + pcnt.unit0.resume(); + pcnt.unit1.resume(); + pcnt.unit2.resume(); + pcnt.unit3.resume(); + + let data_to_send = [ + 0b0000_0000, + 0b1010_0000, + 0b0110_0000, + 0b1110_0000, + 0b0000_0000, + 0b1000_0000, + 0b0100_0000, + 0b1010_0000, + 0b0101_0000, + 0b1000_0000, + ]; + + let mut dma_buf = ctx.dma_buf; + dma_buf.as_mut_slice().fill(0); + dma_buf.as_mut_slice()[..data_to_send.len()].copy_from_slice(&data_to_send); + + let xfer = i8080.send(Command::::None, 0, dma_buf).unwrap(); + xfer.wait().0.unwrap(); + + let actual = [ + pcnt.unit0.value(), + pcnt.unit1.value(), + pcnt.unit2.value(), + pcnt.unit3.value(), + ]; + assert_eq!([5, 3, 2, 1], actual); + } + + #[test] + fn test_i8080_16bit_is_seen_by_pcnt(ctx: Context<'static>) { + let [ctrl, u0, u1, u2, u3] = ctx.pins; + let (unit_ctrl, cs_signal) = unsafe { ctrl.split() }; + let (unit0_input, unit0_signal) = unsafe { u0.split() }; + let (unit1_input, unit1_signal) = unsafe { u1.split() }; + let (unit2_input, unit2_signal) = unsafe { u2.split() }; + let (unit3_input, unit3_signal) = unsafe { u3.split() }; + + let pcnt = ctx.pcnt; + pcnt.unit0 + .channel0 + .set_ctrl_mode(CtrlMode::Keep, CtrlMode::Disable); + pcnt.unit1 + .channel0 + .set_ctrl_mode(CtrlMode::Keep, CtrlMode::Disable); + pcnt.unit2 + .channel0 + .set_ctrl_mode(CtrlMode::Keep, CtrlMode::Disable); + pcnt.unit3 + .channel0 + .set_ctrl_mode(CtrlMode::Keep, CtrlMode::Disable); + + pcnt.unit0 + .channel0 + .set_input_mode(EdgeMode::Hold, EdgeMode::Increment); + pcnt.unit1 + .channel0 + .set_input_mode(EdgeMode::Hold, EdgeMode::Increment); + pcnt.unit2 + .channel0 + .set_input_mode(EdgeMode::Hold, EdgeMode::Increment); + pcnt.unit3 + .channel0 + .set_input_mode(EdgeMode::Hold, EdgeMode::Increment); + + let mut i8080 = I8080::new( + ctx.lcd_cam.lcd, + ctx.dma, + Config::default().with_frequency(Rate::from_mhz(20)), + ) + .unwrap() + .with_cs(cs_signal) + .with_data3(unit0_signal) + .with_data7(unit1_signal) + .with_data11(unit2_signal) + .with_data15(unit3_signal); + + i8080.set_bit_order(BitOrder::Inverted); + + pcnt.unit0.channel0.set_edge_signal(unit0_input); + pcnt.unit1.channel0.set_edge_signal(unit1_input); + pcnt.unit2.channel0.set_edge_signal(unit2_input); + pcnt.unit3.channel0.set_edge_signal(unit3_input); + + pcnt.unit0.channel0.set_ctrl_signal(unit_ctrl.clone()); + pcnt.unit1.channel0.set_ctrl_signal(unit_ctrl.clone()); + pcnt.unit2.channel0.set_ctrl_signal(unit_ctrl.clone()); + pcnt.unit3.channel0.set_ctrl_signal(unit_ctrl.clone()); + + pcnt.unit0.resume(); + pcnt.unit1.resume(); + pcnt.unit2.resume(); + pcnt.unit3.resume(); + + let data_to_send = [ + 0b0000_0000_0000_0000u16, + 0b0001_0000_0001_0000, + 0b0000_0001_0001_0000, + 0b0001_0001_0001_0000, + 0b0000_0000_0000_0000, + 0b0001_0000_0000_0000, + 0b0000_0001_0000_0000, + 0b0001_0000_0001_0000, + 0b0000_0001_0000_0001, + 0b0001_0000_0000_0000, + ]; + + let mut dma_buf = ctx.dma_buf; + dma_buf + .as_mut_slice() + .iter_mut() + .zip(data_to_send.iter().flat_map(|&d| d.to_ne_bytes())) + .for_each(|(d, s)| *d = s); + + let xfer = i8080.send(Command::::None, 0, dma_buf).unwrap(); + xfer.wait().0.unwrap(); + + let actual = [ + pcnt.unit0.value(), + pcnt.unit1.value(), + pcnt.unit2.value(), + pcnt.unit3.value(), + ]; + assert_eq!([5, 3, 2, 1], actual); } } // LCD_CAM Camera and DPI tests +#[embedded_test::tests(default_timeout = 3)] mod camera_tests { use super::*; - #[embedded_test::tests] - mod tests { - use super::*; + struct Context { + peripherals: Peripherals, + dma_tx_buf: DmaTxBuf, + dma_rx_buf: DmaRxBuf, + } - #[init] - fn init() -> CameraContext { - let peripherals = esp_hal::init(esp_hal::Config::default()); - let dma_rx_buf = dma_rx_buffer!(2500).unwrap(); - let dma_tx_buf = dma_tx_buffer!(2500).unwrap(); + #[init] + fn init() -> Context { + let peripherals = esp_hal::init(esp_hal::Config::default()); + let dma_rx_buf = dma_rx_buffer!(2500).unwrap(); + let dma_tx_buf = dma_tx_buffer!(2500).unwrap(); - CameraContext { - peripherals, - dma_tx_buf, - dma_rx_buf, - } + Context { + peripherals, + dma_tx_buf, + dma_rx_buf, } + } - #[test] - fn test_camera_can_receive_from_rgb(ctx: CameraContext) { - let peripherals = ctx.peripherals; - let lcd_cam = LcdCam::new(peripherals.LCD_CAM); - let (rx_channel, tx_channel) = peripherals.DMA_CH2.split(); - - let ( - (vsync_in, vsync_out), - (hsync_in, hsync_out), - (de_in, de_out), - (pclk_in, pclk_out), - (d0_in, d0_out), - (d1_in, d1_out), - (d2_in, d2_out), - (d3_in, d3_out), - (d4_in, d4_out), - (d5_in, d5_out), - (d6_in, d6_out), - (d7_in, d7_out), - ) = unsafe { + #[test] + fn test_camera_can_receive_from_rgb(ctx: Context) { + let peripherals = ctx.peripherals; + let lcd_cam = LcdCam::new(peripherals.LCD_CAM); + let dma_channel = cfg_select! { + lcd_cam_dma_engine = "AHB_GDMA" => peripherals.DMA_CH0, + lcd_cam_dma_engine = "AXI_GDMA" => peripherals.DMA_AXI_CH0, + }; + let (rx_channel, tx_channel) = dma_channel.split(); + + let ( + (vsync_in, vsync_out), + (hsync_in, hsync_out), + (de_in, de_out), + (pclk_in, pclk_out), + (d0_in, d0_out), + (d1_in, d1_out), + (d2_in, d2_out), + (d3_in, d3_out), + (d4_in, d4_out), + (d5_in, d5_out), + (d6_in, d6_out), + (d7_in, d7_out), + ) = cfg_select! { + esp32s3 => unsafe { ( peripherals.GPIO6.split(), peripherals.GPIO7.split(), @@ -394,84 +401,100 @@ mod camera_tests { peripherals.GPIO17.split(), peripherals.GPIO16.split(), ) - }; - - let config = dpi::Config::default() - .with_clock_mode(ClockMode { - polarity: Polarity::IdleHigh, - phase: Phase::ShiftLow, - }) - .with_frequency(Rate::from_khz(500)) - .with_format(Format { - enable_2byte_mode: false, - ..Default::default() - }) - .with_timing(FrameTiming { - horizontal_total_width: 65, - hsync_width: 5, - horizontal_blank_front_porch: 10, - horizontal_active_width: 50, - vertical_total_height: 65, - vsync_width: 5, - vertical_blank_front_porch: 10, - vertical_active_height: 50, - hsync_position: 0, - }) - .with_vsync_idle_level(Level::High) - .with_hsync_idle_level(Level::High) - .with_de_idle_level(Level::Low) - .with_disable_black_region(false); - - let dpi = Dpi::new(lcd_cam.lcd, tx_channel, config) - .unwrap() - .with_vsync(vsync_out) - .with_hsync(hsync_out) - .with_de(de_out) - .with_pclk(pclk_out) - .with_data0(d0_out) - .with_data1(d1_out) - .with_data2(d2_out) - .with_data3(d3_out) - .with_data4(d4_out) - .with_data5(d5_out) - .with_data6(d6_out) - .with_data7(d7_out); - - let camera = Camera::new( - lcd_cam.cam, - rx_channel, - cam::Config::default() - .with_frequency(Rate::from_mhz(1)) - .with_vh_de_mode(VhdeMode::VsyncHsync), - ) - .unwrap() - .with_vsync(vsync_in) - .with_hsync(hsync_in) - .with_h_enable(de_in) - .with_pixel_clock(pclk_in) - .with_data0(d0_in) - .with_data1(d1_in) - .with_data2(d2_in) - .with_data3(d3_in) - .with_data4(d4_in) - .with_data5(d5_in) - .with_data6(d6_in) - .with_data7(d7_in); - - let mut dma_tx_buf = ctx.dma_tx_buf; - let mut dma_rx_buf = ctx.dma_rx_buf; - - for (i, b) in dma_tx_buf.as_mut_slice().iter_mut().enumerate() { - *b = (i % 256) as u8; } + esp32s31 => unsafe { + ( + peripherals.GPIO20.split(), + peripherals.GPIO21.split(), + peripherals.GPIO22.split(), + peripherals.GPIO23.split(), + peripherals.GPIO24.split(), + peripherals.GPIO25.split(), + peripherals.GPIO35.split(), + peripherals.GPIO42.split(), + peripherals.GPIO43.split(), + peripherals.GPIO46.split(), + peripherals.GPIO47.split(), + peripherals.GPIO48.split(), + ) + } + }; + + let config = dpi::Config::default() + .with_clock_mode(ClockMode { + polarity: Polarity::IdleHigh, + phase: Phase::ShiftLow, + }) + .with_frequency(Rate::from_khz(500)) + .with_format(Format { + enable_2byte_mode: false, + ..Default::default() + }) + .with_timing(FrameTiming { + horizontal_total_width: 65, + hsync_width: 5, + horizontal_blank_front_porch: 10, + horizontal_active_width: 50, + vertical_total_height: 65, + vsync_width: 5, + vertical_blank_front_porch: 10, + vertical_active_height: 50, + hsync_position: 0, + }) + .with_vsync_idle_level(Level::High) + .with_hsync_idle_level(Level::High) + .with_de_idle_level(Level::Low) + .with_disable_black_region(false); + + let dpi = Dpi::new(lcd_cam.lcd, tx_channel, config) + .unwrap() + .with_vsync(vsync_out) + .with_hsync(hsync_out) + .with_de(de_out) + .with_pclk(pclk_out) + .with_data0(d0_out) + .with_data1(d1_out) + .with_data2(d2_out) + .with_data3(d3_out) + .with_data4(d4_out) + .with_data5(d5_out) + .with_data6(d6_out) + .with_data7(d7_out); + + let camera = Camera::new( + lcd_cam.cam, + rx_channel, + cam::Config::default() + .with_frequency(Rate::from_mhz(1)) + .with_vh_de_mode(VhdeMode::VsyncHsync), + ) + .unwrap() + .with_vsync(vsync_in) + .with_hsync(hsync_in) + .with_h_enable(de_in) + .with_pixel_clock(pclk_in) + .with_data0(d0_in) + .with_data1(d1_in) + .with_data2(d2_in) + .with_data3(d3_in) + .with_data4(d4_in) + .with_data5(d5_in) + .with_data6(d6_in) + .with_data7(d7_in); + + let mut dma_tx_buf = ctx.dma_tx_buf; + let mut dma_rx_buf = ctx.dma_rx_buf; + + for (i, b) in dma_tx_buf.as_mut_slice().iter_mut().enumerate() { + *b = (i % 256) as u8; + } - let camera_transfer = camera.receive(dma_rx_buf).map_err(|e| e.0).unwrap(); - let dpi_transfer = dpi.send(true, dma_tx_buf).map_err(|e| e.0).unwrap(); + let camera_transfer = camera.receive(dma_rx_buf).map_err(|e| e.0).unwrap(); + let dpi_transfer = dpi.send(true, dma_tx_buf).map_err(|e| e.0).unwrap(); - (_, _, dma_rx_buf) = camera_transfer.wait(); - (_, dma_tx_buf) = dpi_transfer.stop(); + (_, _, dma_rx_buf) = camera_transfer.wait(); + (_, dma_tx_buf) = dpi_transfer.stop(); - assert_eq!(dma_tx_buf.as_slice(), dma_rx_buf.as_slice()); - } + hil_test::assert_eq!(dma_tx_buf.as_slice(), dma_rx_buf.as_slice()); } } diff --git a/qa-test/src/bin/lcd_cam_ov2640.rs b/qa-test/src/bin/lcd_cam_ov2640.rs index bab0409003a..29689fc78d2 100644 --- a/qa-test/src/bin/lcd_cam_ov2640.rs +++ b/qa-test/src/bin/lcd_cam_ov2640.rs @@ -20,7 +20,7 @@ //! - D8 => GPIO17 //! - D9 => GPIO16 -//% CHIP_FILTER: camera_driver_supported +//% CHIP_FILTER: camera_driver_supported && lcd_cam_dma_engine == "AHB_GDMA" #![no_std] #![no_main] diff --git a/qa-test/src/bin/lcd_dpi.rs b/qa-test/src/bin/lcd_dpi.rs index ecb6fdbb292..bd0eb3c1bc0 100644 --- a/qa-test/src/bin/lcd_dpi.rs +++ b/qa-test/src/bin/lcd_dpi.rs @@ -1,43 +1,43 @@ -//! Drives the 16-bit parallel RGB display on ESP32-S3-LCD-EV-Board v1.5 +//! Drives a 16-bit parallel RGB display using the LCD_CAM peripheral. //! //! This example fills the screen with every color. //! -//! The following wiring is assumed: -//! - LCD_VSYNC => GPIO3 -//! - LCD_HSYNC => GPIO46 -//! - LCD_DE => GPIO17 -//! - LCD_PCLK => GPIO9 -//! - LCD_DATA0 => GPIO10 -//! - LCD_DATA1 => GPIO11 -//! - LCD_DATA2 => GPIO12 -//! - LCD_DATA3 => GPIO13 -//! - LCD_DATA4 => GPIO14 -//! - LCD_DATA5 => GPIO21 -//! - LCD_DATA6 => GPIO8 -//! - LCD_DATA7 => GPIO18 -//! - LCD_DATA8 => GPIO45 -//! - LCD_DATA9 => GPIO38 -//! - LCD_DATA10 => GPIO39 -//! - LCD_DATA11 => GPIO40 -//! - LCD_DATA12 => GPIO41 -//! - LCD_DATA13 => GPIO42 -//! - LCD_DATA14 => GPIO2 -//! - LCD_DATA15 => GPIO1 +//! Hardware setup: +//! +//! Signal | ESP32-S3-LCD-EV-Board v1.5 | ESP32-S31-Korvo-1-V1.1 +//! ---------- | -------------------------- | ---------------------- +//! LCD_VSYNC | GPIO3 | GPIO45 +//! LCD_HSYNC | GPIO46 | GPIO44 +//! LCD_DE | GPIO17 | GPIO43 +//! LCD_PCLK | GPIO9 | GPIO40 +//! LCD_DATA0 | GPIO10 | GPIO8 +//! LCD_DATA1 | GPIO11 | GPIO9 +//! LCD_DATA2 | GPIO12 | GPIO10 +//! LCD_DATA3 | GPIO13 | GPIO11 +//! LCD_DATA4 | GPIO14 | GPIO12 +//! LCD_DATA5 | GPIO21 | GPIO13 +//! LCD_DATA6 | GPIO8 | GPIO14 +//! LCD_DATA7 | GPIO18 | GPIO15 +//! LCD_DATA8 | GPIO45 | GPIO16 +//! LCD_DATA9 | GPIO38 | GPIO17 +//! LCD_DATA10 | GPIO39 | GPIO18 +//! LCD_DATA11 | GPIO40 | GPIO19 +//! LCD_DATA12 | GPIO41 | GPIO33 +//! LCD_DATA13 | GPIO42 | GPIO34 +//! LCD_DATA14 | GPIO2 | GPIO35 +//! LCD_DATA15 | GPIO1 | GPIO36 //% CHIP_FILTER: rgb_display_driver_supported && !esp32 #![no_std] #![no_main] -use core::iter::{empty, once}; +use core::iter::empty; use esp_backtrace as _; use esp_hal::{ - Blocking, - delay::Delay, dma_loop_buffer, - gpio::{Level, Output, OutputConfig}, - i2c::{self, master::I2c}, + gpio::Level, lcd_cam::{ LcdCam, lcd::{ @@ -53,6 +53,18 @@ use esp_hal::{ }; use esp_println::println; +cfg_select! { + esp32s3 => { + use core::iter::once; + use esp_hal::gpio::OutputConfig; + use esp_hal::gpio::Output; + use esp_hal::delay::Delay; + use esp_hal::i2c::{self, master::I2c}; + use esp_hal::Blocking; + } + _ => {} +} + esp_bootloader_esp_idf::esp_app_desc!(); #[main] @@ -61,136 +73,216 @@ fn main() -> ! { let peripherals: Peripherals = esp_hal::init(esp_hal::Config::default()); - let i2c = I2c::new( - peripherals.I2C0, - i2c::master::Config::default().with_frequency(Rate::from_khz(400)), - ) - .unwrap() - .with_sda(peripherals.GPIO47) - .with_scl(peripherals.GPIO48); - - let tx_channel = peripherals.DMA_CH2; + let tx_channel = cfg_select! { + lcd_cam_dma_engine = "AHB_GDMA" => peripherals.DMA_CH2, + lcd_cam_dma_engine = "AXI_GDMA" => peripherals.DMA_AXI_CH0, + }; let lcd_cam = LcdCam::new(peripherals.LCD_CAM); - let mut expander = Tca9554::new(i2c); - expander.write_output_reg(0b1111_0011).unwrap(); - expander.write_direction_reg(0b1111_0001).unwrap(); + cfg_select! { + esp32s3 => { + let i2c = I2c::new( + peripherals.I2C0, + i2c::master::Config::default().with_frequency(Rate::from_khz(400)), + ) + .unwrap() + .with_sda(peripherals.GPIO47) + .with_scl(peripherals.GPIO48); - let delay = Delay::new(); + let mut expander = Tca9554::new(i2c); + expander.write_output_reg(0b1111_0011).unwrap(); + expander.write_direction_reg(0b1111_0001).unwrap(); - println!("Initialising"); + let delay = Delay::new(); - let mut write_byte = |b: u8, is_cmd: bool| { - const SCS_BIT: u8 = 0b0000_0010; - const SCL_BIT: u8 = 0b0000_0100; - const SDA_BIT: u8 = 0b0000_1000; + println!("Initialising"); - let mut output = 0b1111_0001 & !SCS_BIT; - expander.write_output_reg(output).unwrap(); + let mut write_byte = |b: u8, is_cmd: bool| { + const SCS_BIT: u8 = 0b0000_0010; + const SCL_BIT: u8 = 0b0000_0100; + const SDA_BIT: u8 = 0b0000_1000; - for bit in once(!is_cmd).chain((0..8).map(|i| (b >> i) & 0b1 != 0).rev()) { - let prev = output; - if bit { - output |= SDA_BIT; - } else { - output &= !SDA_BIT; - } - if prev != output { + let mut output = 0b1111_0001 & !SCS_BIT; expander.write_output_reg(output).unwrap(); - } - - output &= !SCL_BIT; - expander.write_output_reg(output).unwrap(); - - output |= SCL_BIT; - expander.write_output_reg(output).unwrap(); - } - - output &= !SCL_BIT; - expander.write_output_reg(output).unwrap(); - output &= !SDA_BIT; - expander.write_output_reg(output).unwrap(); + for bit in once(!is_cmd).chain((0..8).map(|i| (b >> i) & 0b1 != 0).rev()) { + let prev = output; + if bit { + output |= SDA_BIT; + } else { + output &= !SDA_BIT; + } + if prev != output { + expander.write_output_reg(output).unwrap(); + } + + output &= !SCL_BIT; + expander.write_output_reg(output).unwrap(); + + output |= SCL_BIT; + expander.write_output_reg(output).unwrap(); + } - output |= SCS_BIT; - expander.write_output_reg(output).unwrap(); - }; + output &= !SCL_BIT; + expander.write_output_reg(output).unwrap(); - let mut vsync_pin = peripherals.GPIO3; + output &= !SDA_BIT; + expander.write_output_reg(output).unwrap(); - let vsync_must_be_high_during_setup = - Output::new(vsync_pin.reborrow(), Level::High, OutputConfig::default()); - for &init in INIT_CMDS.iter() { - match init { - InitCmd::Cmd(cmd, args) => { - write_byte(cmd, true); - for &arg in args { - write_byte(arg, false); + output |= SCS_BIT; + expander.write_output_reg(output).unwrap(); + }; + + let vsync_pin = peripherals.GPIO3; + let hsync_pin = peripherals.GPIO46; + let de_pin = peripherals.GPIO17; + let pclk_pin = peripherals.GPIO9; + let data0_pin = peripherals.GPIO10; + let data1_pin = peripherals.GPIO11; + let data2_pin = peripherals.GPIO12; + let data3_pin = peripherals.GPIO13; + let data4_pin = peripherals.GPIO14; + let data5_pin = peripherals.GPIO21; + let data6_pin = peripherals.GPIO8; + let data7_pin = peripherals.GPIO18; + let data8_pin = peripherals.GPIO45; + let data9_pin = peripherals.GPIO38; + let data10_pin = peripherals.GPIO39; + let data11_pin = peripherals.GPIO40; + let data12_pin = peripherals.GPIO41; + let data13_pin = peripherals.GPIO42; + let data14_pin = peripherals.GPIO2; + let data15_pin = peripherals.GPIO1; + + let mut vsync_pin = vsync_pin; + + let vsync_must_be_high_during_setup = + Output::new(vsync_pin.reborrow(), Level::High, OutputConfig::default()); + + for &init in INIT_CMDS.iter() { + match init { + InitCmd::Cmd(cmd, args) => { + write_byte(cmd, true); + for &arg in args { + write_byte(arg, false); + } + } + InitCmd::Delay(ms) => { + delay.delay_millis(ms as _); + } } } - InitCmd::Delay(ms) => { - delay.delay_millis(ms as _); - } + drop(vsync_must_be_high_during_setup); + + let config = Config::default() + .with_clock_mode(ClockMode { + polarity: Polarity::IdleLow, + phase: Phase::ShiftLow, + }) + .with_frequency(Rate::from_mhz(16)) + .with_format(Format { + enable_2byte_mode: true, + ..Default::default() + }) + .with_timing(FrameTiming { + horizontal_active_width: 480, + horizontal_total_width: 520, + horizontal_blank_front_porch: 10, + + vertical_active_height: 480, + vertical_total_height: 510, + vertical_blank_front_porch: 10, + + hsync_width: 10, + vsync_width: 10, + + hsync_position: 0, + }) + .with_vsync_idle_level(Level::High) + .with_hsync_idle_level(Level::High) + .with_de_idle_level(Level::Low) + .with_disable_black_region(false); + } + esp32s31 => { + let vsync_pin = peripherals.GPIO45; + let hsync_pin = peripherals.GPIO44; + let de_pin = peripherals.GPIO43; + let pclk_pin = peripherals.GPIO40; + let data0_pin = peripherals.GPIO8; + let data1_pin = peripherals.GPIO9; + let data2_pin = peripherals.GPIO10; + let data3_pin = peripherals.GPIO11; + let data4_pin = peripherals.GPIO12; + let data5_pin = peripherals.GPIO13; + let data6_pin = peripherals.GPIO14; + let data7_pin = peripherals.GPIO15; + let data8_pin = peripherals.GPIO16; + let data9_pin = peripherals.GPIO17; + let data10_pin = peripherals.GPIO18; + let data11_pin = peripherals.GPIO19; + let data12_pin = peripherals.GPIO33; + let data13_pin = peripherals.GPIO34; + let data14_pin = peripherals.GPIO35; + let data15_pin = peripherals.GPIO36; + + let config = Config::default() + .with_clock_mode(ClockMode { + polarity: Polarity::IdleLow, + phase: Phase::ShiftLow, + }) + .with_frequency(Rate::from_mhz(40)) + .with_format(Format { + enable_2byte_mode: true, + ..Default::default() + }) + .with_timing(FrameTiming { + horizontal_active_width: 800, + horizontal_total_width: 840, + horizontal_blank_front_porch: 10, + + vertical_active_height: 480, + vertical_total_height: 510, + vertical_blank_front_porch: 10, + + hsync_width: 10, + vsync_width: 10, + + hsync_position: 0, + }) + .with_vsync_idle_level(Level::High) + .with_hsync_idle_level(Level::High) + .with_de_idle_level(Level::Low) + .with_disable_black_region(false); } } - drop(vsync_must_be_high_during_setup); let mut dma_buf = dma_loop_buffer!(2 * 16); - let config = Config::default() - .with_clock_mode(ClockMode { - polarity: Polarity::IdleLow, - phase: Phase::ShiftLow, - }) - .with_frequency(Rate::from_mhz(16)) - .with_format(Format { - enable_2byte_mode: true, - ..Default::default() - }) - .with_timing(FrameTiming { - horizontal_active_width: 480, - horizontal_total_width: 520, - horizontal_blank_front_porch: 10, - - vertical_active_height: 480, - vertical_total_height: 510, - vertical_blank_front_porch: 10, - - hsync_width: 10, - vsync_width: 10, - - hsync_position: 0, - }) - .with_vsync_idle_level(Level::High) - .with_hsync_idle_level(Level::High) - .with_de_idle_level(Level::Low) - .with_disable_black_region(false); - let mut dpi = Dpi::new(lcd_cam.lcd, tx_channel, config) .unwrap() .with_vsync(vsync_pin) - .with_hsync(peripherals.GPIO46) - .with_de(peripherals.GPIO17) - .with_pclk(peripherals.GPIO9) + .with_hsync(hsync_pin) + .with_de(de_pin) + .with_pclk(pclk_pin) // Blue - .with_data0(peripherals.GPIO10) - .with_data1(peripherals.GPIO11) - .with_data2(peripherals.GPIO12) - .with_data3(peripherals.GPIO13) - .with_data4(peripherals.GPIO14) + .with_data0(data0_pin) + .with_data1(data1_pin) + .with_data2(data2_pin) + .with_data3(data3_pin) + .with_data4(data4_pin) // Green - .with_data5(peripherals.GPIO21) - .with_data6(peripherals.GPIO8) - .with_data7(peripherals.GPIO18) - .with_data8(peripherals.GPIO45) - .with_data9(peripherals.GPIO38) - .with_data10(peripherals.GPIO39) + .with_data5(data5_pin) + .with_data6(data6_pin) + .with_data7(data7_pin) + .with_data8(data8_pin) + .with_data9(data9_pin) + .with_data10(data10_pin) // Red - .with_data11(peripherals.GPIO40) - .with_data12(peripherals.GPIO41) - .with_data13(peripherals.GPIO42) - .with_data14(peripherals.GPIO2) - .with_data15(peripherals.GPIO1); + .with_data11(data11_pin) + .with_data12(data12_pin) + .with_data13(data13_pin) + .with_data14(data14_pin) + .with_data15(data15_pin); const MAX_RED: u16 = (1 << 5) - 1; const MAX_GREEN: u16 = (1 << 6) - 1; @@ -229,11 +321,13 @@ fn main() -> ! { } } +#[cfg(esp32s3)] struct Tca9554 { i2c: I2c<'static, Blocking>, address: u8, } +#[cfg(esp32s3)] impl Tca9554 { pub fn new(i2c: I2c<'static, Blocking>) -> Self { Self { i2c, address: 0x20 } @@ -248,12 +342,14 @@ impl Tca9554 { } } +#[cfg(esp32s3)] #[derive(Copy, Clone)] enum InitCmd { Cmd(u8, &'static [u8]), Delay(u8), } +#[cfg(esp32s3)] const INIT_CMDS: &[InitCmd] = &[ InitCmd::Cmd(0xf0, &[0x55, 0xaa, 0x52, 0x08, 0x00]), InitCmd::Cmd(0xf6, &[0x5a, 0x87]), diff --git a/qa-test/src/bin/lcd_i8080.rs b/qa-test/src/bin/lcd_i8080.rs index 1b9ac7fc198..bbaa82ed68b 100644 --- a/qa-test/src/bin/lcd_i8080.rs +++ b/qa-test/src/bin/lcd_i8080.rs @@ -17,7 +17,7 @@ //! - D6 => GPIO16 //! - D7 => GPIO15 -//% CHIP_FILTER: rgb_display_driver_supported && soc_has_lcd_cam +//% CHIP_FILTER: rgb_display_driver_supported && soc_has_lcd_cam && lcd_cam_dma_engine == "AHB_GDMA" #![no_std] #![no_main]