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nthainguyennthainguyen
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add arm
1 parent ce4c21b commit 3ebfc42

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Lines changed: 352 additions & 10 deletions

‎boards/arm/seeeduino_xiao_ble/Kconfig‎

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# Seeeduino XIAO BLE board configuration
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# Copyright (c) 2022 Peter Johanson
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_ENABLE_DCDC
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bool "Enable DCDC mode"
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select SOC_DCDC_NRF52X
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default y
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depends on BOARD_SEEEDUINO_XIAO_BLE

‎boards/arm/seeeduino_xiao_ble/Kconfig.board‎

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# Seeeduino XIAO BLE board configuration
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# Copyright (c) 2022 Peter Johanson
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_SEEEDUINO_XIAO_BLE
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bool "Seeeduino XIAO BLE"
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depends on SOC_NRF52840_QIAA
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‎boards/arm/seeeduino_xiao_ble/Kconfig.defconfig‎

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# Seeeduino XIAO BLE board configuration
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# Copyright (c) 2022 Peter Johanson
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# SPDX-License-Identifier: Apache-2.0
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config BOARD
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default "seeeduino_xiao_ble" if BOARD_SEEEDUINO_XIAO_BLE
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if BOARD_SEEEDUINO_XIAO_BLE
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config BT_CTLR
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default BT
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endif # BOARD_SEEEDUINO_XIAO_BLE

‎boards/arm/seeeduino_xiao_ble/board.cmake‎

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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(jlink "--device=nrf52" "--speed=4000")
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board_runner_args(pyocd "--target=nrf52" "--frequency=4000000")
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include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)

‎boards/arm/seeeduino_xiao_ble/seeed_xiao_connector.dtsi‎

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/*
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* Copyright (c) 2022 Peter Johanson
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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xiao_d: connector {
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compatible = "seeed,xiao-gpio";
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#gpio-cells = <2>;
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gpio-map-mask = <0xffffffff 0xffffffc0>;
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gpio-map-pass-thru = <0 0x3f>;
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gpio-map
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= <0 0 &gpio0 2 0> /* D0 */
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, <1 0 &gpio0 3 0> /* D1 */
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, <2 0 &gpio0 28 0> /* D2 */
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, <3 0 &gpio0 29 0> /* D3 */
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, <4 0 &gpio0 4 0> /* D4 */
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, <5 0 &gpio0 5 0> /* D5 */
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, <6 0 &gpio1 11 0> /* D6 */
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, <7 0 &gpio1 12 0> /* D7 */
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, <8 0 &gpio1 13 0> /* D8 */
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, <9 0 &gpio1 14 0> /* D9 */
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, <10 0 &gpio1 15 0> /* D10 */
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, <11 0 &gpio0 15 0> /* D10 */
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, <12 0 &gpio0 19 0> /* D10 */
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, <13 0 &gpio1 1 0> /* D10 */
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, <14 0 &gpio0 9 0> /* D10 */
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, <15 0 &gpio0 10 0> /* D10 */
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, <16 0 &gpio0 31 0> /* D10 */
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, <17 0 &gpio1 7 0> /* D10 */
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, <18 0 &gpio1 5 0> /* D10 */
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, <19 0 &gpio1 3 0> /* D10 */
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;
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};
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};
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xiao_spi: &spi2 {};
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xiao_i2c: &i2c0 {};
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xiao_serial: &uart0 {};

‎boards/arm/seeeduino_xiao_ble/seeeduino_xiao_ble-pinctrl.dtsi‎

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/*
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* Copyright (c) 2022 Pete Johanson
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* SPDX-License-Identifier: Apache-2.0
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*/
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&pinctrl {
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uart0_default: uart0_default {
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group1 {
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psels = <NRF_PSEL(UART_TX, 1, 11)>;
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};
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group2 {
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psels = <NRF_PSEL(UART_RX, 1, 12)>;
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bias-pull-up;
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};
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};
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uart0_sleep: uart0_sleep {
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group1 {
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psels = <NRF_PSEL(UART_TX, 1, 11)>,
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<NRF_PSEL(UART_RX, 1, 12)>;
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low-power-enable;
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};
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};
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i2c0_default: i2c0_default {
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group1 {
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psels = <NRF_PSEL(TWIM_SDA, 0, 4)>,
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<NRF_PSEL(TWIM_SCL, 0, 5)>;
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};
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};
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i2c0_sleep: i2c0_sleep {
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group1 {
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psels = <NRF_PSEL(TWIM_SDA, 0, 4)>,
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<NRF_PSEL(TWIM_SCL, 0, 5)>;
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low-power-enable;
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};
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};
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spi2_default: spi2_default {
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group1 {
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psels = <NRF_PSEL(SPIM_SCK, 1, 13)>,
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<NRF_PSEL(SPIM_MOSI, 1, 15)>,
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<NRF_PSEL(SPIM_MISO, 1, 14)>;
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};
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};
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spi2_sleep: spi2_sleep {
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group1 {
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psels = <NRF_PSEL(SPIM_SCK, 1, 13)>,
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<NRF_PSEL(SPIM_MOSI, 1, 15)>,
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<NRF_PSEL(SPIM_MISO, 1, 14)>;
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low-power-enable;
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};
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};
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qspi_default: qspi_default {
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group1 {
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psels = <NRF_PSEL(QSPI_SCK, 0, 21)>,
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<NRF_PSEL(QSPI_IO0, 0, 20)>,
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<NRF_PSEL(QSPI_IO1, 0, 24)>,
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<NRF_PSEL(QSPI_IO2, 0, 22)>,
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<NRF_PSEL(QSPI_IO3, 0, 23)>,
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<NRF_PSEL(QSPI_CSN, 0, 25)>;
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};
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};
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qspi_sleep: qspi_sleep {
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group1 {
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psels = <NRF_PSEL(QSPI_SCK, 0, 21)>,
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<NRF_PSEL(QSPI_IO0, 0, 20)>,
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<NRF_PSEL(QSPI_IO1, 0, 24)>,
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<NRF_PSEL(QSPI_IO2, 0, 22)>,
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<NRF_PSEL(QSPI_IO3, 0, 23)>;
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low-power-enable;
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};
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group2 {
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psels = <NRF_PSEL(QSPI_CSN, 0, 25)>;
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low-power-enable;
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bias-pull-up;
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};
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};
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};

‎boards/arm/seeeduino_xiao_ble/seeeduino_xiao_ble.dts‎

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/*
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* Copyright (c) 2022 Peter Johanson
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <nordic/nrf52840_qiaa.dtsi>
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#include "seeeduino_xiao_ble-pinctrl.dtsi"
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#include "seeed_xiao_connector.dtsi"
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/ {
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model = "Seeeduino XIAO BLE";
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compatible = "seeed,xiao_ble";
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,uart-mcumgr = &uart0;
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zephyr,bt-mon-uart = &uart0;
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zephyr,bt-c2h-uart = &uart0;
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,code-partition = &code_partition;
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};
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/* These aliases are provided for compatibility with samples */
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aliases {
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led0 = &led0;
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led1 = &led1;
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led2 = &led2;
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};
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leds {
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compatible = "gpio-leds";
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led0: led_0 {
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gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
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label = "Red LED";
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};
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led1: led_1 {
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gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
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label = "Blue LED";
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};
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led2: led_2 {
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gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
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label = "Green LED";
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};
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};
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};
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&gpiote {
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status = "okay";
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};
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&uart0 {
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status = "okay";
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compatible = "nordic,nrf-uart";
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current-speed = <115200>;
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pinctrl-0 = <&uart0_default>;
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pinctrl-1 = <&uart0_sleep>;
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pinctrl-names = "default", "sleep";
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};
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&i2c0 {
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compatible = "nordic,nrf-twi";
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pinctrl-0 = <&i2c0_default>;
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pinctrl-1 = <&i2c0_sleep>;
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pinctrl-names = "default", "sleep";
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};
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&spi2 {
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compatible = "nordic,nrf-spi";
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pinctrl-0 = <&spi2_default>;
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pinctrl-1 = <&spi2_sleep>;
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pinctrl-names = "default", "sleep";
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};
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zephyr_udc0: &usbd {
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compatible = "nordic,nrf-usbd";
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status = "okay";
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};
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&qspi {
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status = "okay";
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pinctrl-0 = <&qspi_default>;
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pinctrl-1 = <&qspi_sleep>;
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pinctrl-names = "default", "sleep";
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// TODO: VERIFY THESE!
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gd25q16: gd25q16@0 {
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/* NOTE: Quad mode not supported as driver does not handle
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* QE bit setting in SR2. Ref. GD25Q16C, Rev 3.0, p. 12.
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*/
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compatible = "nordic,qspi-nor";
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reg = <0>;
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writeoc = "pp2o";
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readoc = "read2io";
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sck-frequency = <16000000>;
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label = "GD25Q16";
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jedec-id = [c8 40 15];
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size = <2097152>;
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has-dpd;
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t-enter-dpd = <20000>;
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t-exit-dpd = <20000>;
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};
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};
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&flash0 {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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sd_partition: partition@0 {
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label = "softdevice";
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reg = <0x00000000 0x00026000>;
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};
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code_partition: partition@27000 {
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label = "code_partition";
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reg = <0x00027000 0x000c5000>;
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};
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/*
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* The flash starting at 0x000ec000 and ending at
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* 0x000f3fff is reserved for use by the application.
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*/
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/*
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* Storage partition will be used by FCB/LittleFS/NVS
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* if enabled.
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*/
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storage_partition: partition@ec000 {
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label = "storage";
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reg = <0x000ec000 0x00008000>;
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};
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boot_partition: partition@f4000 {
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label = "adafruit_boot";
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reg = <0x000f4000 0x0000c000>;
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};
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};
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};
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‎boards/arm/seeeduino_xiao_ble/seeeduino_xiao_ble.yaml‎

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identifier: seeeduino_xiao_ble_nrf52840
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name: Seeeduino Xiao BLE nRF52840
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type: mcu
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arch: arm
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toolchain:
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- zephyr
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- gnuarmemb
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- xtools
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ram: 256
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flash: 1024
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supported:
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- xiao_serial

‎boards/arm/seeeduino_xiao_ble/seeeduino_xiao_ble.zmk.yml‎

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This file was deleted.

‎boards/arm/seeeduino_xiao_ble/seeeduino_xiao_ble_defconfig‎

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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SOC_SERIES_NRF52X=y
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CONFIG_SOC_NRF52840_QIAA=y
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CONFIG_BOARD_SEEEDUINO_XIAO_BLE=y
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CONFIG_PINCTRL=y
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# Enable MPU
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CONFIG_ARM_MPU=y
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# enable GPIO
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CONFIG_GPIO=y
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# enable uart driver
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CONFIG_SERIAL=y
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# enable console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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CONFIG_USE_DT_CODE_PARTITION=y
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CONFIG_BUILD_OUTPUT_UF2=y

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