From d22ef6adc7c83bf4e770efba8b06141a0ad41afc Mon Sep 17 00:00:00 2001 From: Fazail Date: Wed, 13 Nov 2024 20:53:20 +0500 Subject: [PATCH 1/8] Store Buffer added with load-inst bypass --- rtl/defines/cache_defs.svh | 27 ++++ rtl/memory/mem_top.sv | 72 ++++++++- rtl/memory/store-buffer/lsu_stb_controller.sv | 153 ++++++++++++++++++ .../store-buffer/stb_cache_controller.sv | 136 ++++++++++++++++ .../store-buffer/store_buffer_datapath.sv | 115 +++++++++++++ rtl/memory/store-buffer/store_buffer_top.sv | 143 ++++++++++++++++ rtl/memory/wb_dcache/wb_dcache_top.sv | 8 +- 7 files changed, 649 insertions(+), 5 deletions(-) create mode 100644 rtl/memory/store-buffer/lsu_stb_controller.sv create mode 100644 rtl/memory/store-buffer/stb_cache_controller.sv create mode 100644 rtl/memory/store-buffer/store_buffer_datapath.sv create mode 100644 rtl/memory/store-buffer/store_buffer_top.sv diff --git a/rtl/defines/cache_defs.svh b/rtl/defines/cache_defs.svh index 145aa13a..69defae1 100644 --- a/rtl/defines/cache_defs.svh +++ b/rtl/defines/cache_defs.svh @@ -105,6 +105,33 @@ typedef struct packed { logic ack; } type_dcache2lsummu_s; +// Bus interface from STB to dcache +typedef struct packed { + logic [DCACHE_ADDR_WIDTH-1:0] addr; + logic [DCACHE_DATA_WIDTH-1:0] w_data; + logic [3:0] sel_byte; + logic w_en; + logic req; +} type_stb2dcache_s; + +typedef struct packed { + logic [DCACHE_DATA_WIDTH-1:0] r_data; + logic ack; +} type_dcache2stb_s; + +// Bus interface from LSU to STB +typedef struct packed { + logic [DCACHE_ADDR_WIDTH-1:0] addr; + logic [DCACHE_DATA_WIDTH-1:0] w_data; + logic [3:0] sel_byte; + logic w_en; + logic req; +} type_lsummu2stb_s; + +typedef struct packed { + logic ack; + logic stall; +} type_stb2lsummu_s; typedef struct packed { logic [DCACHE_ADDR_WIDTH-1:0] addr; diff --git a/rtl/memory/mem_top.sv b/rtl/memory/mem_top.sv index 63d346a9..3f14d7b7 100644 --- a/rtl/memory/mem_top.sv +++ b/rtl/memory/mem_top.sv @@ -65,8 +65,8 @@ type_dbus2peri_s dbus2peri; type_peri2dbus_s dcache2dbus; // Signals from data memory type_peri2dbus_s bmem2dbus; -type_lsummu2dcache_s lsummu2dcache; -type_dcache2lsummu_s dcache2lsummu; +type_lsummu2dcache_s lsummu2dcache,stb2dcache; +type_dcache2lsummu_s dcache2lsummu,dcache2stb; type_mem2dcache_s mem2dcache; type_dcache2mem_s dcache2mem; @@ -88,6 +88,15 @@ logic dcache2mem_kill; logic timeout_flag; logic [5:0] timeout_next, timeout_ff; +// Store Buffer related signals +//type_stb2dcache_s stb2dcache; +//type_dcache2stb_s dcache2stb; + +type_lsummu2stb_s lsummu2stb; +type_stb2lsummu_s stb2lsummu; +logic stb_dmem_sel_o; +logic stb2dcache_empty; + // Signal assignments assign mmu2dcache = mmu2dcache_i; assign dmem_sel = dmem_sel_i; @@ -156,6 +165,7 @@ dcache_kill_req = '0; lsummu2dcache.sel_byte = dbus2peri.sel_byte; lsummu2dcache.w_en = dbus2peri.w_en; lsummu2dcache.req = dbus2peri.req; + cache_arbiter_state_next = DCACHE_ARBITER_LSU; end else if (~dmem_sel & mmu2dcache.r_req & ~mmu2dcache.flush_req) begin lsummu2dcache.addr = mmu2dcache.paddr; @@ -206,11 +216,66 @@ dcache_kill_req = '0; end +//========================== Store Buffer top module ===========================// +store_buffer_top store_buffer_top_module ( + .clk (clk), + .rst_n (rst_n), + + // LSU --> store_buffer_top + .lsummu2stb_addr (lsummu2dcache.addr), + .lsummu2stb_wdata (lsummu2dcache.w_data), + .lsummu2stb_sel_byte (lsummu2dcache.sel_byte), + .lsummu2stb_w_en (lsummu2dcache.w_en), + .lsummu2stb_req (lsummu2dcache.req), + .dmem_sel_i (dmem_sel), + + // store_buffer_top --> LSU + .stb2lsummu_ack (dcache2lsummu.ack), + .stb2lsummu_rdata (dcache2lsummu.r_data), + + .stb2lsummu_stall (stb2lsummu.stall), + + + // store_buffer_top --> dcache + .stb2dcache_addr (stb2dcache.addr), + .stb2dcache_wdata (stb2dcache.w_data), + .stb2dcache_sel_byte (stb2dcache.sel_byte), + .stb2dcache_w_en (stb2dcache.w_en), + .stb2dcache_req (stb2dcache.req), + + .stb2dcache_empty (stb2dcache_empty), + .dmem_sel_o (stb_dmem_sel_o), + + .dcache2stb_ack (dcache2stb.ack), + .dcache2stb_rdata (dcache2stb.r_data) +); + //========================== Data cache top module ===========================// wb_dcache_top wb_dcache_top_module( .clk (clk), .rst_n (rst_n), + // LSU/MMU to data cache interface + .lsummu2dcache_i (stb2dcache), // lsummu2dmem + + .dcache2lsummu_o (dcache2stb), // dmem2lsummu + + .stb2dcache_empty (stb2dcache_empty), + + .dcache_kill_i (dcache_kill_req), + .dcache2mem_kill_o (dcache2mem_kill), + + // Data cache to main memory interface + .mem2dcache_i (mem2dcache), + .dcache2mem_o (dcache2mem), + + .dcache_flush_i (dcache_flush_i), + .dmem_sel_i (stb_dmem_sel_o | mmu2dcache.r_req) +); +/*wb_dcache_top wb_dcache_top_module( + .clk (clk), + .rst_n (rst_n), + // LSU/MMU to data cache interface .lsummu2dcache_i (lsummu2dcache), // lsummu2dmem .dcache2lsummu_o (dcache2lsummu), // dmem2lsummu @@ -222,7 +287,7 @@ wb_dcache_top wb_dcache_top_module( .dcache2mem_o (dcache2mem), .dcache_flush_i (dcache_flush_i), .dmem_sel_i (dmem_sel | mmu2dcache.r_req) -); +);*/ //============================= Main memory and its memory interface =============================// // Arbitration between data and instruction caches for main memory access @@ -362,3 +427,4 @@ assign dcache2dbus_o = dcache2dbus; assign dcache2mmu_o = dcache2mmu; endmodule : mem_top + diff --git a/rtl/memory/store-buffer/lsu_stb_controller.sv b/rtl/memory/store-buffer/lsu_stb_controller.sv new file mode 100644 index 00000000..c73c3aba --- /dev/null +++ b/rtl/memory/store-buffer/lsu_stb_controller.sv @@ -0,0 +1,153 @@ +module lsu_stb_controller ( + input logic clk, + input logic rst_n, + + // LSU --> lsu_stb_controller + input logic lsummu2stb_w_en, // Write enable from LSU + input logic lsummu2stb_req, // Store request from LSU + input logic dmem_sel_i, // Input from LSU (data memory select) + + // store_buffer_datapath --> lsu_stb_controller + input logic stb_full, // Store buffer stb_full flag + input logic stb_empty, // store buffer stb_empty flag + + input logic stb_bypass, + input logic dcache2stb_ack, + + // lsu_stb_controller --> LSU + output logic stb2lsummu_ack, // stb_acknowledgement signal + output logic stb2lsummu_stall, // Stall signal if buffer is stb_full + + // lsu_stb_controller --> store_buffer_datapath + output logic stb_wr_en // Store buffer write enable +); + logic ack, d_ack; + + typedef enum logic [1:0] { + SB_IDLE = 2'b00, + SB_WRITE = 2'b01, + SB_FULL = 2'b10 + } state_t; + + state_t current_state, next_state; + + // State transition logic (sequential) + always_ff @(posedge clk or negedge rst_n) begin + if (!rst_n) + current_state <= SB_IDLE; + else + current_state <= next_state; + end + + always_ff @(posedge clk or negedge rst_n) begin + if (!rst_n) + d_ack <= 0; + else if (stb_bypass) + d_ack <= 1; + else + d_ack <= '0; + end + + always_comb begin + case (stb_bypass) + 1'b1: begin + stb2lsummu_ack = dcache2stb_ack; + end + 1'b0: begin + if (d_ack) stb2lsummu_ack = dcache2stb_ack; + else stb2lsummu_ack = ack; + end + default: begin + stb2lsummu_ack = ack; + end + endcase + end + + // Next state logic (combinational) + always_comb begin + // Default values + stb_wr_en = 1'b0; + stb2lsummu_stall = 1'b0; + ack = 1'b0; + + case (current_state) + SB_IDLE: begin + if (dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req && !stb_full) begin + stb_wr_en = 1'b1; // Enable write to buffer + stb2lsummu_stall = 1'b0; + ack = 1'b0; + next_state = SB_WRITE; + end + else if (dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req && stb_full) begin + stb2lsummu_stall = 1'b1; + stb_wr_en = 1'b0; + ack = 1'b0; + next_state = SB_FULL; + end else begin + stb2lsummu_stall = 1'b0; + stb_wr_en = 1'b0; + ack = 1'b0; + next_state = SB_IDLE; + end + end + + SB_WRITE: begin + ack = 1'b1; + if (dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req && !stb_full)begin + stb_wr_en = 1'b1; // Enable write to buffer + stb2lsummu_stall = 1'b0; + //ack = 1'b1; + next_state = SB_WRITE; + end + else if (dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req && stb_full)begin + stb_wr_en = 1'b0; + stb2lsummu_stall = 1'b1; + //ack = 1'b0; + next_state = SB_FULL; + end + else if (!stb_empty) begin + if (dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req) begin + stb_wr_en = 1'b1; + //ack = 1'b1; + next_state = SB_WRITE; // Transition to stb_full state if buffer is stb_full + end + else begin + stb_wr_en = 1'b0; + //ack = 1'b0; + next_state = SB_IDLE; + end + end + end + + SB_FULL: begin + stb2lsummu_stall = 1'b1; // Stall signal if buffer is stb_full + if (dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req && !stb_full) begin + stb_wr_en = 1'b1; + stb2lsummu_stall = 1'b0; + ack = 1'b0; + next_state = SB_WRITE; // Go to idle once buffer is not stb_full + end + else if(dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req && stb_full) begin + stb_wr_en = 1'b0; + ack = 1'b0; + next_state = SB_FULL; + end + /*else if (!(dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req)) begin + stb_wr_en = 1'b0; + stb2lsummu_stall = 1'b0; + ack = 1'b0; + next_state = SB_IDLE; + end*/ + else begin + stb_wr_en = 1'b0; + stb2lsummu_stall = 1'b0; + ack = 1'b0; + next_state = SB_IDLE; + end + end + + default: next_state = SB_IDLE; + endcase + end + +endmodule diff --git a/rtl/memory/store-buffer/stb_cache_controller.sv b/rtl/memory/store-buffer/stb_cache_controller.sv new file mode 100644 index 00000000..2f90778b --- /dev/null +++ b/rtl/memory/store-buffer/stb_cache_controller.sv @@ -0,0 +1,136 @@ +module stb_cache_controller ( + input logic clk, + input logic rst_n, + + // store_buffer_datapath --> stb_cache_controller + input logic stb_full, // Store buffer full flag + input logic stb_empty, // Store buffer empty flag + + input logic stb_bypass, + + // dcache --> stb_cache_controller + input logic dcache2stb_ack, // Acknowledgement from cache + + // LSU --> lsu_stb_controller + input logic lsummu2stb_w_en, // Write enable from LSU + input logic lsummu2stb_req, // Store request from LSU + input logic dmem_sel_i, // Input from LSU (data memory select) + + // stb_cache_controller --> store_buffer_datapath + output logic stb_rd_en, // enable for read counter + output logic rd_sel, // Store buffer mux read selection + + // stb_cache_controller --> dcache + output logic stb2dcache_req, // Store buffer request signal + output logic stb2dcache_w_en, // Last word enable (for last write to cache) + output logic dmem_sel_o +); + +logic req, w_en, dm_sel; + + typedef enum logic [1:0] { + IDLE = 2'b00, + SB_CACHE_WRITE = 2'b01 + } state_t; + + state_t current_state, next_state; + + // State transition logic (sequential) + always_ff @(posedge clk or negedge rst_n) begin + if (!rst_n) + current_state <= IDLE; + else + current_state <= next_state; + end + + always_comb begin + case (stb_bypass) + 1'b1: begin + stb2dcache_req = lsummu2stb_req; + stb2dcache_w_en = lsummu2stb_w_en; + dmem_sel_o = dmem_sel_i; + end + 1'b0: begin + stb2dcache_req = req; + stb2dcache_w_en = w_en; + dmem_sel_o = dm_sel; + end + default: begin + stb2dcache_req = req; + stb2dcache_w_en = w_en; + dmem_sel_o = dm_sel; + end + endcase + end + + // Next state logic (combinational) + always_comb + begin + // Default values + rd_sel = 1'b0; + req = 1'b0; + w_en = 1'b0; + stb_rd_en = 1'b0; + dm_sel = 1'b0; + next_state = current_state; + + case (current_state) + IDLE: begin + if (!stb_empty || stb_full) begin + req = 1'b1; // Request cache write + rd_sel = 1'b1; // Read selection for store buffer + w_en = 1'b1; + dm_sel = 1'b1; + stb_rd_en = 1'b0; + next_state = SB_CACHE_WRITE; + end + else if(stb_empty) begin + rd_sel = 1'b0; + req = 1'b0; + w_en = 1'b0; + stb_rd_en = 1'b0; + dm_sel = 1'b0; + next_state = IDLE; + end + end + + SB_CACHE_WRITE: begin + if (!dcache2stb_ack && !stb_empty) begin + req = 1'b1; + rd_sel = 1'b1; + w_en = 1'b1; + dm_sel = 1'b1; + stb_rd_en = 1'b0; + next_state = SB_CACHE_WRITE; // Stay SB_CACHE_WRITE state till store buffer contain data + + end + else if (dcache2stb_ack && !stb_empty) begin + req = 1'b0; + rd_sel = 1'b1; + w_en = 1'b0; + dm_sel = 1'b1; + stb_rd_en = 1'b1; + next_state = SB_CACHE_WRITE; // Stay SB_CACHE_WRITE state till all data written to cache then cache acknowledges set + end + else if (dcache2stb_ack && stb_empty) begin + req = 1'b0; + rd_sel = 1'b1; + w_en = 1'b0; + dm_sel = 1'b1; + stb_rd_en = 1'b1; + next_state = IDLE; + end + else if (stb_empty) begin + req = 1'b0; + rd_sel = 1'b0; + w_en = 1'b0; + dm_sel = 1'b0; + stb_rd_en = 1'b0; + next_state = IDLE; + end + end + + default: next_state = IDLE; + endcase + end +endmodule diff --git a/rtl/memory/store-buffer/store_buffer_datapath.sv b/rtl/memory/store-buffer/store_buffer_datapath.sv new file mode 100644 index 00000000..2105a56d --- /dev/null +++ b/rtl/memory/store-buffer/store_buffer_datapath.sv @@ -0,0 +1,115 @@ +module store_buffer_datapath #( + parameter BLEN = 4, // Buffer Length + parameter ADDR_WIDTH = 32, + parameter DATA_WIDTH = 32, + parameter BYTE_SEL_WIDTH = 4 +)( + input logic clk, + input logic rst_n, + + // LSU --> store_buffer_datapath + input logic [ADDR_WIDTH-1:0] lsummu2stb_addr, // Address input from LSU/MMU + input logic [DATA_WIDTH-1:0] lsummu2stb_wdata, // Data input from LSU/MMU + input logic [BYTE_SEL_WIDTH-1:0] lsummu2stb_sel_byte, // Byte selection input from LSU/MMU + + // lsu_stb_controller --> store_buffer_datapath + input logic stb_wr_en, // Write enable signal + + // stb_cache_controller --> store_buffer_datapath + input logic stb_rd_en, // Read enable signal + input logic rd_sel, // Read Selection signal + + // store_buffer_datapath --> dcache + output logic [ADDR_WIDTH-1:0] stb2dcache_addr, // Address output to Cache + output logic [DATA_WIDTH-1:0] stb2dcache_wdata, // Data output to Cache + output logic [BYTE_SEL_WIDTH-1:0] stb2dcache_sel_byte, // Byte selection output to Cache + + // store_buffer_datapath --> store buffer controllers + output logic stb_full, // Full signal + output logic stb_empty, // Empty signal + + input logic stb_bypass +); + + // Buffer Registers (arrays to hold multiple entries) + logic [ADDR_WIDTH-1:0] addr_buf [BLEN-1:0]; + logic [DATA_WIDTH-1:0] data_buf [BLEN-1:0]; + logic [BYTE_SEL_WIDTH-1:0] sel_byte_buf [BLEN-1:0]; + logic [BLEN-1:0] valid_buf; // Valid entries in buffer + + // Buffer Counter (to track read and write index) + logic [$clog2(BLEN)-1:0] rd_index, rd_index_add; + logic [$clog2(BLEN)-1:0] wr_index, wr_index_comp, wr_index_add; + + // counter for write operaitons + assign wr_index_add = (wr_index == BLEN-1) ? '0: (wr_index + 1); + always_ff @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + wr_index <= 0; + end + else if (stb_wr_en) begin + wr_index <= wr_index_add; + end + else begin + wr_index <= wr_index; + end + end + + // counter for read operaitons + assign rd_index_add = (rd_index == BLEN-1) ? '0: (rd_index + 1); + always_ff @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + rd_index <= 0; + end + else if (stb_rd_en) begin + rd_index <= rd_index_add; + end + else begin + rd_index <= rd_index; + end + end + + // Write/Read logic + always_ff @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + addr_buf <= addr_buf ; + data_buf <= data_buf ; + sel_byte_buf <= sel_byte_buf; + end + else if (stb_wr_en) begin + // Write new values to buffer at wr_index + addr_buf [wr_index] <= lsummu2stb_addr; + data_buf [wr_index] <= lsummu2stb_wdata; + sel_byte_buf [wr_index] <= lsummu2stb_sel_byte; + end + else begin + addr_buf [rd_index] <= addr_buf [rd_index]; + data_buf [rd_index] <= data_buf [rd_index]; + sel_byte_buf [rd_index] <= sel_byte_buf [rd_index]; + end + end + + always_comb begin + if (stb_bypass) begin + stb2dcache_addr = lsummu2stb_addr; + stb2dcache_wdata = lsummu2stb_wdata; + stb2dcache_sel_byte = lsummu2stb_sel_byte; + end + else if (rd_sel) begin + stb2dcache_addr = addr_buf [rd_index]; + stb2dcache_wdata = data_buf [rd_index]; + stb2dcache_sel_byte = sel_byte_buf [rd_index]; + end + else begin + stb2dcache_addr = '0; + stb2dcache_wdata = '0; + stb2dcache_sel_byte = '0; + end + end + + assign wr_index_comp = (wr_index == BLEN-1) ? '0: wr_index + 1; + + assign stb_full = (rd_index == (wr_index_comp)) ? 1'b1 : 1'b0; + assign stb_empty = (rd_index == wr_index) ? 1'b1 : 1'b0; + +endmodule diff --git a/rtl/memory/store-buffer/store_buffer_top.sv b/rtl/memory/store-buffer/store_buffer_top.sv new file mode 100644 index 00000000..f3cd83c0 --- /dev/null +++ b/rtl/memory/store-buffer/store_buffer_top.sv @@ -0,0 +1,143 @@ +module store_buffer_top #( + parameter BLEN = 4, // Buffer Length + parameter ADDR_WIDTH = 32, // Address width + parameter DATA_WIDTH = 32, // Data width + parameter BYTE_SEL_WIDTH = 4 // Byte selection width +)( + input logic clk, // Clock + input logic rst_n, // Reset, active low + + // LSU --> store_buffer_top + input logic [ADDR_WIDTH-1:0] lsummu2stb_addr, // Address input from LSU + input logic [DATA_WIDTH-1:0] lsummu2stb_wdata, // Data input from LSU + input logic [BYTE_SEL_WIDTH-1:0] lsummu2stb_sel_byte, // Byte selection from LSU + input logic lsummu2stb_w_en, // Write enable from LSU + input logic lsummu2stb_req, // Store request from LSU + input logic dmem_sel_i, // Data memory select from LSU + + // store_buffer_top --> LSU + output logic stb2lsummu_stall, // Stall signal (from LSU controller) + output logic stb2lsummu_ack, // Store Buffer acknowledges the write + + output logic [DATA_WIDTH-1:0] stb2lsummu_rdata, // Cache to LSU + + // store_buffer_top --> dcache + output logic [ADDR_WIDTH-1:0] stb2dcache_addr, // Address to Cache + output logic [DATA_WIDTH-1:0] stb2dcache_wdata, // Data to Cache + output logic [BYTE_SEL_WIDTH-1:0] stb2dcache_sel_byte, // Byte select to Cache + output logic stb2dcache_w_en, // Write enable from Store Buffer + output logic stb2dcache_req, // Store request from Store Buffer + output logic stb2dcache_empty, // store buffer empty signal to dcache + output logic dmem_sel_o, // Data memory select from Store Buffer + + // dCache --> store_buffer_top + input logic [DATA_WIDTH-1:0] dcache2stb_rdata, + input logic dcache2stb_ack // Cache acknowledges the write +); + + // Internal Signals + logic stb_wr_en; // Store Buffer Write Enable (from LSU controller) + logic stb_rd_en; // Store Buffer Read Enable (from Cache controller) + logic stb_full; // Store Buffer full signal + logic stb_empty; // Store Buffer empty signal + logic rd_sel; // selection for read mux + logic stb_bypass; + + assign stb2lsummu_rdata = dcache2stb_rdata; // bypassing rdata signal + assign stb_bypass = ((lsummu2stb_req & !lsummu2stb_w_en) | (!lsummu2stb_req & !lsummu2stb_w_en)) & dmem_sel_i & stb_empty; + + // Instantiate the Store Buffer Datapath + store_buffer_datapath #( + .BLEN(BLEN), + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .BYTE_SEL_WIDTH(BYTE_SEL_WIDTH) + ) u_store_buffer ( + .clk (clk), + .rst_n (rst_n), + + // LSU --> store_buffer_datapath + .lsummu2stb_addr (lsummu2stb_addr), + .lsummu2stb_wdata (lsummu2stb_wdata), + .lsummu2stb_sel_byte (lsummu2stb_sel_byte), + + // lsu_stb_controller --> store_buffer_datapath + .stb_wr_en (stb_wr_en), + + // stb_cache_controller --> store_buffer_datapath + .stb_rd_en (stb_rd_en), + .rd_sel (rd_sel), + + // store_buffer_datapath --> dcache + .stb2dcache_addr (stb2dcache_addr), + .stb2dcache_wdata (stb2dcache_wdata), + .stb2dcache_sel_byte (stb2dcache_sel_byte), + + // store_buffer --> store_buffer_controllers + .stb_full (stb_full), + .stb_empty (stb_empty), + + .stb_bypass (stb_bypass) + ); + + // Instantiate the LSU to Store Buffer Controller + lsu_stb_controller u_lsu_stb_controller ( + .clk (clk), + .rst_n (rst_n), + + // LSU --> lsu_stb_controller + .lsummu2stb_w_en (lsummu2stb_w_en), + .lsummu2stb_req (lsummu2stb_req), + .dmem_sel_i (dmem_sel_i), + + // store_buffer_datapath --> lsu_stb_controller + .stb_full (stb_full), + .stb_empty (stb_empty), + + .stb_bypass (stb_bypass), + + // dcache --> stb_cache_controller + .dcache2stb_ack (dcache2stb_ack), + + // lsu_stb_controller --> LSU + .stb2lsummu_ack (stb2lsummu_ack), + + // lsu_stb_controller --> store_buffer_datapath + .stb_wr_en (stb_wr_en), + + // lsu_stb_controller --> LSU + .stb2lsummu_stall (stb2lsummu_stall) + ); + + // Instantiate the Store Buffer to Cache Controller + stb_cache_controller u_stb_cache_controller ( + .clk (clk), + .rst_n (rst_n), + + // store_buffer_datapath --> stb_cache_controller + .stb_full (stb_full), + .stb_empty (stb_empty), + + .stb_bypass (stb_bypass), + + // LSU --> lsu_stb_controller + .lsummu2stb_w_en (lsummu2stb_w_en), + .lsummu2stb_req (lsummu2stb_req), + .dmem_sel_i (dmem_sel_i), + + // dcache --> stb_cache_controller + .dcache2stb_ack (dcache2stb_ack), + + // stb_cache_controller --> store_buffer_datapath + .stb_rd_en (stb_rd_en), + .rd_sel (rd_sel), + + // stb_cache_controller --> dcache + .stb2dcache_req (stb2dcache_req), + .stb2dcache_w_en (stb2dcache_w_en), + .dmem_sel_o (dmem_sel_o) + ); + +assign stb2dcache_empty = stb_empty; + +endmodule diff --git a/rtl/memory/wb_dcache/wb_dcache_top.sv b/rtl/memory/wb_dcache/wb_dcache_top.sv index 54693e05..6f6e9eac 100644 --- a/rtl/memory/wb_dcache/wb_dcache_top.sv +++ b/rtl/memory/wb_dcache/wb_dcache_top.sv @@ -21,6 +21,7 @@ module wb_dcache_top ( input wire dmem_sel_i, input wire dcache_flush_i, input wire dcache_kill_i, + input wire stb2dcache_empty, // LSU/MMU to data cache interface input wire type_lsummu2dcache_s lsummu2dcache_i, @@ -46,9 +47,12 @@ type_dcache2lsummu_s dcache2lsummu; type_mem2dcache_s mem2dcache; type_dcache2mem_s dcache2mem; +logic top_dcache_flush; + assign lsummu2dcache = lsummu2dcache_i; assign mem2dcache = mem2dcache_i; +assign top_dcache_flush = stb2dcache_empty && dcache_flush_i; wb_dcache_controller wb_dcache_controller_module( .clk (clk), @@ -67,7 +71,7 @@ wb_dcache_controller wb_dcache_controller_module( .lsummu2dcache_req_i (lsummu2dcache.req), .lsummu2dcache_wr_i (lsummu2dcache.w_en), .dcache2lsummu_ack_o (dcache2lsummu.ack), - .dcache_flush_i (dcache_flush_i), + .dcache_flush_i (top_dcache_flush), .dcache_kill_i (dcache_kill_i), // .dcache_flush_ack_o (dcache2lsummu.flush_ack), @@ -93,7 +97,7 @@ wb_dcache_datapath wb_dcache_datapath_module( .cache_evict_req_o (cache_evict_req), // LSU/MMU <---> data cache signals - .dcache_flush_i (dcache_flush_i), + .dcache_flush_i (top_dcache_flush), .lsummu2dcache_req_i (lsummu2dcache.req), .lsummu2dcache_addr_i (lsummu2dcache.addr), .lsummu2dcache_wdata_i (lsummu2dcache.w_data), From ecf46a388d1e3c465efa6644b790091f9c79fd3e Mon Sep 17 00:00:00 2001 From: Fazail Date: Fri, 15 Nov 2024 11:56:38 +0500 Subject: [PATCH 2/8] Store buffer integrated --- rtl/memory/store-buffer/stb_cache_controller.sv | 4 ++-- rtl/memory/store-buffer/store_buffer_top.sv | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/rtl/memory/store-buffer/stb_cache_controller.sv b/rtl/memory/store-buffer/stb_cache_controller.sv index 2f90778b..d007ce7d 100644 --- a/rtl/memory/store-buffer/stb_cache_controller.sv +++ b/rtl/memory/store-buffer/stb_cache_controller.sv @@ -106,7 +106,7 @@ logic req, w_en, dm_sel; end else if (dcache2stb_ack && !stb_empty) begin req = 1'b0; - rd_sel = 1'b1; + rd_sel = 1'b0; w_en = 1'b0; dm_sel = 1'b1; stb_rd_en = 1'b1; @@ -114,7 +114,7 @@ logic req, w_en, dm_sel; end else if (dcache2stb_ack && stb_empty) begin req = 1'b0; - rd_sel = 1'b1; + rd_sel = 1'b0; w_en = 1'b0; dm_sel = 1'b1; stb_rd_en = 1'b1; diff --git a/rtl/memory/store-buffer/store_buffer_top.sv b/rtl/memory/store-buffer/store_buffer_top.sv index f3cd83c0..795ee8e9 100644 --- a/rtl/memory/store-buffer/store_buffer_top.sv +++ b/rtl/memory/store-buffer/store_buffer_top.sv @@ -44,7 +44,7 @@ module store_buffer_top #( logic stb_bypass; assign stb2lsummu_rdata = dcache2stb_rdata; // bypassing rdata signal - assign stb_bypass = ((lsummu2stb_req & !lsummu2stb_w_en) | (!lsummu2stb_req & !lsummu2stb_w_en)) & dmem_sel_i & stb_empty; + assign stb_bypass = ((lsummu2stb_req & !lsummu2stb_w_en) | (!lsummu2stb_req & !lsummu2stb_w_en)) & stb_empty; // Instantiate the Store Buffer Datapath store_buffer_datapath #( From cb0baa4049f97b59281c776c31628034865e0f54 Mon Sep 17 00:00:00 2001 From: Fazail Date: Sat, 16 Nov 2024 14:33:48 +0500 Subject: [PATCH 3/8] Update Store Buffer Signals --- rtl/defines/cache_defs.svh | 4 +- rtl/memory/mem_top.sv | 104 ++++++--------- rtl/memory/store-buffer/lsu_stb_controller.sv | 9 ++ .../store-buffer/stb_cache_controller.sv | 9 ++ .../store-buffer/store_buffer_datapath.sv | 60 +++++---- rtl/memory/store-buffer/store_buffer_top.sv | 121 ++++++++++++------ 6 files changed, 182 insertions(+), 125 deletions(-) diff --git a/rtl/defines/cache_defs.svh b/rtl/defines/cache_defs.svh index 69defae1..96baef5f 100644 --- a/rtl/defines/cache_defs.svh +++ b/rtl/defines/cache_defs.svh @@ -129,8 +129,8 @@ typedef struct packed { } type_lsummu2stb_s; typedef struct packed { - logic ack; - logic stall; + logic ack; + logic [DCACHE_DATA_WIDTH-1:0] r_data; } type_stb2lsummu_s; typedef struct packed { diff --git a/rtl/memory/mem_top.sv b/rtl/memory/mem_top.sv index 3f14d7b7..aba8e361 100644 --- a/rtl/memory/mem_top.sv +++ b/rtl/memory/mem_top.sv @@ -65,8 +65,8 @@ type_dbus2peri_s dbus2peri; type_peri2dbus_s dcache2dbus; // Signals from data memory type_peri2dbus_s bmem2dbus; -type_lsummu2dcache_s lsummu2dcache,stb2dcache; -type_dcache2lsummu_s dcache2lsummu,dcache2stb; +//type_lsummu2dcache_s lsummu2dcache; +//type_dcache2lsummu_s dcache2lsummu; type_mem2dcache_s mem2dcache; type_dcache2mem_s dcache2mem; @@ -89,12 +89,13 @@ logic timeout_flag; logic [5:0] timeout_next, timeout_ff; // Store Buffer related signals -//type_stb2dcache_s stb2dcache; -//type_dcache2stb_s dcache2stb; +type_stb2dcache_s stb2dcache; +type_dcache2stb_s dcache2stb; type_lsummu2stb_s lsummu2stb; type_stb2lsummu_s stb2lsummu; logic stb_dmem_sel_o; +//logic stb2lsummu_stall; logic stb2dcache_empty; // Signal assignments @@ -150,7 +151,7 @@ always_ff @(posedge clk) begin end always_comb begin -lsummu2dcache = '0; +lsummu2stb = '0; dcache2dbus = '0; dcache2mmu = '0; cache_arbiter_state_next = cache_arbiter_state_ff; @@ -160,35 +161,35 @@ dcache_kill_req = '0; DCACHE_ARBITER_IDLE: begin if (dmem_sel) begin - lsummu2dcache.addr = dbus2peri.addr; - lsummu2dcache.w_data = dbus2peri.w_data; - lsummu2dcache.sel_byte = dbus2peri.sel_byte; - lsummu2dcache.w_en = dbus2peri.w_en; - lsummu2dcache.req = dbus2peri.req; + lsummu2stb.addr = dbus2peri.addr; + lsummu2stb.w_data = dbus2peri.w_data; + lsummu2stb.sel_byte = dbus2peri.sel_byte; + lsummu2stb.w_en = dbus2peri.w_en; + lsummu2stb.req = dbus2peri.req; cache_arbiter_state_next = DCACHE_ARBITER_LSU; end else if (~dmem_sel & mmu2dcache.r_req & ~mmu2dcache.flush_req) begin - lsummu2dcache.addr = mmu2dcache.paddr; - lsummu2dcache.w_data = '0; - lsummu2dcache.sel_byte = '0; - lsummu2dcache.w_en = '0; - lsummu2dcache.req = 1'b1; + lsummu2stb.addr = mmu2dcache.paddr; + lsummu2stb.w_data = '0; + lsummu2stb.sel_byte = '0; + lsummu2stb.w_en = '0; + lsummu2stb.req = 1'b1; cache_arbiter_state_next = DCACHE_ARBITER_MMU; end end DCACHE_ARBITER_LSU: begin - if (dcache2lsummu.ack) begin - dcache2dbus.r_data = dcache2lsummu.r_data; + if (stb2lsummu.ack) begin + dcache2dbus.r_data = stb2lsummu.r_data; dcache2dbus.ack = 1'b1; cache_arbiter_state_next = DCACHE_ARBITER_IDLE; end else begin cache_arbiter_state_next = DCACHE_ARBITER_LSU; - lsummu2dcache.addr = dbus2peri.addr; - lsummu2dcache.w_data = dbus2peri.w_data; - lsummu2dcache.sel_byte = dbus2peri.sel_byte; - lsummu2dcache.w_en = dbus2peri.w_en; - lsummu2dcache.req = dbus2peri.req; + lsummu2stb.addr = dbus2peri.addr; + lsummu2stb.w_data = dbus2peri.w_data; + lsummu2stb.sel_byte = dbus2peri.sel_byte; + lsummu2stb.w_en = dbus2peri.w_en; + lsummu2stb.req = dbus2peri.req; end end @@ -197,17 +198,17 @@ dcache_kill_req = '0; if (mmu2dcache.flush_req) begin cache_arbiter_state_next = DCACHE_ARBITER_IDLE; dcache_kill_req = 1'b1; - end else if (dcache2lsummu.ack) begin - dcache2mmu.r_data = dcache2lsummu.r_data; + end else if (stb2lsummu.ack) begin + dcache2mmu.r_data = stb2lsummu.r_data; dcache2mmu.r_valid = 1'b1; cache_arbiter_state_next = DCACHE_ARBITER_IDLE; end else begin cache_arbiter_state_next = DCACHE_ARBITER_MMU; - lsummu2dcache.addr = mmu2dcache.paddr; - lsummu2dcache.w_data = '0; - lsummu2dcache.sel_byte = '0; - lsummu2dcache.w_en = '0; - lsummu2dcache.req = 1'b1; + lsummu2stb.addr = mmu2dcache.paddr; + lsummu2stb.w_data = '0; + lsummu2stb.sel_byte = '0; + lsummu2stb.w_en = '0; + lsummu2stb.req = 1'b1; end end @@ -221,33 +222,22 @@ store_buffer_top store_buffer_top_module ( .clk (clk), .rst_n (rst_n), - // LSU --> store_buffer_top - .lsummu2stb_addr (lsummu2dcache.addr), - .lsummu2stb_wdata (lsummu2dcache.w_data), - .lsummu2stb_sel_byte (lsummu2dcache.sel_byte), - .lsummu2stb_w_en (lsummu2dcache.w_en), - .lsummu2stb_req (lsummu2dcache.req), +// LSU --> store_buffer_top + .lsummu2stb_i (lsummu2stb), .dmem_sel_i (dmem_sel), - // store_buffer_top --> LSU - .stb2lsummu_ack (dcache2lsummu.ack), - .stb2lsummu_rdata (dcache2lsummu.r_data), - - .stb2lsummu_stall (stb2lsummu.stall), +// store_buffer_top --> LSU + .stb2lsummu_o (stb2lsummu), + //.stb2lsummu_stall (stb2lsummu_stall), - // store_buffer_top --> dcache - .stb2dcache_addr (stb2dcache.addr), - .stb2dcache_wdata (stb2dcache.w_data), - .stb2dcache_sel_byte (stb2dcache.sel_byte), - .stb2dcache_w_en (stb2dcache.w_en), - .stb2dcache_req (stb2dcache.req), - +// store_buffer_top --> dcache + .stb2dcache_o (stb2dcache), .stb2dcache_empty (stb2dcache_empty), .dmem_sel_o (stb_dmem_sel_o), - .dcache2stb_ack (dcache2stb.ack), - .dcache2stb_rdata (dcache2stb.r_data) +// dcache --> store_buffer_top + .dcache2stb_i (dcache2stb) ); //========================== Data cache top module ===========================// @@ -272,22 +262,6 @@ wb_dcache_top wb_dcache_top_module( .dcache_flush_i (dcache_flush_i), .dmem_sel_i (stb_dmem_sel_o | mmu2dcache.r_req) ); -/*wb_dcache_top wb_dcache_top_module( - .clk (clk), - .rst_n (rst_n), - - // LSU/MMU to data cache interface - .lsummu2dcache_i (lsummu2dcache), // lsummu2dmem - .dcache2lsummu_o (dcache2lsummu), // dmem2lsummu - .dcache_kill_i (dcache_kill_req), - .dcache2mem_kill_o (dcache2mem_kill), - - // Data cache to main memory interface - .mem2dcache_i (mem2dcache), - .dcache2mem_o (dcache2mem), - .dcache_flush_i (dcache_flush_i), - .dmem_sel_i (dmem_sel | mmu2dcache.r_req) -);*/ //============================= Main memory and its memory interface =============================// // Arbitration between data and instruction caches for main memory access diff --git a/rtl/memory/store-buffer/lsu_stb_controller.sv b/rtl/memory/store-buffer/lsu_stb_controller.sv index c73c3aba..ff266580 100644 --- a/rtl/memory/store-buffer/lsu_stb_controller.sv +++ b/rtl/memory/store-buffer/lsu_stb_controller.sv @@ -1,3 +1,12 @@ +// Copyright 2023 University of Engineering and Technology Lahore. +// Licensed under the Apache License, Version 2.0, see LICENSE file for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Description: The Store Buffer module. +// +// Author: Fazail Ali Butt, UET Lahore +// Date: 15.11.2024 + module lsu_stb_controller ( input logic clk, input logic rst_n, diff --git a/rtl/memory/store-buffer/stb_cache_controller.sv b/rtl/memory/store-buffer/stb_cache_controller.sv index d007ce7d..51dcb98c 100644 --- a/rtl/memory/store-buffer/stb_cache_controller.sv +++ b/rtl/memory/store-buffer/stb_cache_controller.sv @@ -1,3 +1,12 @@ +// Copyright 2023 University of Engineering and Technology Lahore. +// Licensed under the Apache License, Version 2.0, see LICENSE file for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Description: The Store Buffer module. +// +// Author: Fazail Ali Butt, UET Lahore +// Date: 15.11.2024 + module stb_cache_controller ( input logic clk, input logic rst_n, diff --git a/rtl/memory/store-buffer/store_buffer_datapath.sv b/rtl/memory/store-buffer/store_buffer_datapath.sv index 2105a56d..307159f1 100644 --- a/rtl/memory/store-buffer/store_buffer_datapath.sv +++ b/rtl/memory/store-buffer/store_buffer_datapath.sv @@ -1,30 +1,46 @@ +// Copyright 2023 University of Engineering and Technology Lahore. +// Licensed under the Apache License, Version 2.0, see LICENSE file for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Description: The Store Buffer module. +// +// Author: Fazail Ali Butt, UET Lahore +// Date: 15.11.2024 + +`ifndef VERILATOR +`include "../defines/mmu_defs.svh" +`include "../defines/cache_defs.svh" +`include "../defines/ddr_defs.svh" +`else +`include "mmu_defs.svh" +`include "cache_defs.svh" +`include "ddr_defs.svh" +`endif + module store_buffer_datapath #( - parameter BLEN = 4, // Buffer Length - parameter ADDR_WIDTH = 32, - parameter DATA_WIDTH = 32, - parameter BYTE_SEL_WIDTH = 4 + parameter BLEN = 4 // Buffer Length )( input logic clk, input logic rst_n, - // LSU --> store_buffer_datapath - input logic [ADDR_WIDTH-1:0] lsummu2stb_addr, // Address input from LSU/MMU - input logic [DATA_WIDTH-1:0] lsummu2stb_wdata, // Data input from LSU/MMU - input logic [BYTE_SEL_WIDTH-1:0] lsummu2stb_sel_byte, // Byte selection input from LSU/MMU +// LSU --> store_buffer_datapath + input logic [DCACHE_ADDR_WIDTH-1:0] lsummu2stb_addr, // Address input from LSU/MMU + input logic [DCACHE_DATA_WIDTH-1:0] lsummu2stb_wdata, // Data input from LSU/MMU + input logic [3:0] lsummu2stb_sel_byte, // Byte selection input from LSU/MMU - // lsu_stb_controller --> store_buffer_datapath - input logic stb_wr_en, // Write enable signal +// lsu_stb_controller --> store_buffer_datapath + input logic stb_wr_en, // Write enable signal - // stb_cache_controller --> store_buffer_datapath - input logic stb_rd_en, // Read enable signal - input logic rd_sel, // Read Selection signal +// stb_cache_controller --> store_buffer_datapath + input logic stb_rd_en, // Read enable signal + input logic rd_sel, // Read Selection signal - // store_buffer_datapath --> dcache - output logic [ADDR_WIDTH-1:0] stb2dcache_addr, // Address output to Cache - output logic [DATA_WIDTH-1:0] stb2dcache_wdata, // Data output to Cache - output logic [BYTE_SEL_WIDTH-1:0] stb2dcache_sel_byte, // Byte selection output to Cache +// store_buffer_datapath --> dcache + output logic [DCACHE_ADDR_WIDTH-1:0] stb2dcache_addr, // Address output to Cache + output logic [DCACHE_DATA_WIDTH-1:0] stb2dcache_wdata, // Data output to Cache + output logic [3:0] stb2dcache_sel_byte, // Byte selection output to Cache - // store_buffer_datapath --> store buffer controllers +// store_buffer_datapath --> store buffer controllers output logic stb_full, // Full signal output logic stb_empty, // Empty signal @@ -32,10 +48,10 @@ module store_buffer_datapath #( ); // Buffer Registers (arrays to hold multiple entries) - logic [ADDR_WIDTH-1:0] addr_buf [BLEN-1:0]; - logic [DATA_WIDTH-1:0] data_buf [BLEN-1:0]; - logic [BYTE_SEL_WIDTH-1:0] sel_byte_buf [BLEN-1:0]; - logic [BLEN-1:0] valid_buf; // Valid entries in buffer + logic [DCACHE_ADDR_WIDTH-1:0] addr_buf [BLEN-1:0]; + logic [DCACHE_DATA_WIDTH-1:0] data_buf [BLEN-1:0]; + logic [3:0] sel_byte_buf [BLEN-1:0]; + // logic [BLEN-1:0] valid_buf; // Valid entries in buffer // Buffer Counter (to track read and write index) logic [$clog2(BLEN)-1:0] rd_index, rd_index_add; diff --git a/rtl/memory/store-buffer/store_buffer_top.sv b/rtl/memory/store-buffer/store_buffer_top.sv index 795ee8e9..93bdb89f 100644 --- a/rtl/memory/store-buffer/store_buffer_top.sv +++ b/rtl/memory/store-buffer/store_buffer_top.sv @@ -1,57 +1,94 @@ +// Copyright 2023 University of Engineering and Technology Lahore. +// Licensed under the Apache License, Version 2.0, see LICENSE file for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Description: The Store Buffer module. +// +// Author: Fazail Ali Butt, UET Lahore +// Date: 15.11.2024 + +`ifndef VERILATOR +`include "../defines/mmu_defs.svh" +`include "../defines/cache_defs.svh" +`include "../defines/ddr_defs.svh" +`else +`include "mmu_defs.svh" +`include "cache_defs.svh" +`include "ddr_defs.svh" +`endif + module store_buffer_top #( - parameter BLEN = 4, // Buffer Length - parameter ADDR_WIDTH = 32, // Address width - parameter DATA_WIDTH = 32, // Data width - parameter BYTE_SEL_WIDTH = 4 // Byte selection width + parameter BLEN = 4 // Buffer Length )( input logic clk, // Clock input logic rst_n, // Reset, active low // LSU --> store_buffer_top - input logic [ADDR_WIDTH-1:0] lsummu2stb_addr, // Address input from LSU - input logic [DATA_WIDTH-1:0] lsummu2stb_wdata, // Data input from LSU - input logic [BYTE_SEL_WIDTH-1:0] lsummu2stb_sel_byte, // Byte selection from LSU - input logic lsummu2stb_w_en, // Write enable from LSU - input logic lsummu2stb_req, // Store request from LSU + input wire type_lsummu2stb_s lsummu2stb_i, input logic dmem_sel_i, // Data memory select from LSU // store_buffer_top --> LSU - output logic stb2lsummu_stall, // Stall signal (from LSU controller) - output logic stb2lsummu_ack, // Store Buffer acknowledges the write - - output logic [DATA_WIDTH-1:0] stb2lsummu_rdata, // Cache to LSU + output type_stb2lsummu_s stb2lsummu_o, + //output logic stb2lsummu_stall, // Stall signal // store_buffer_top --> dcache - output logic [ADDR_WIDTH-1:0] stb2dcache_addr, // Address to Cache - output logic [DATA_WIDTH-1:0] stb2dcache_wdata, // Data to Cache - output logic [BYTE_SEL_WIDTH-1:0] stb2dcache_sel_byte, // Byte select to Cache - output logic stb2dcache_w_en, // Write enable from Store Buffer - output logic stb2dcache_req, // Store request from Store Buffer + output type_stb2dcache_s stb2dcache_o, + output logic stb2dcache_empty, // store buffer empty signal to dcache output logic dmem_sel_o, // Data memory select from Store Buffer // dCache --> store_buffer_top - input logic [DATA_WIDTH-1:0] dcache2stb_rdata, - input logic dcache2stb_ack // Cache acknowledges the write + input wire type_dcache2stb_s dcache2stb_i ); - // Internal Signals - logic stb_wr_en; // Store Buffer Write Enable (from LSU controller) - logic stb_rd_en; // Store Buffer Read Enable (from Cache controller) - logic stb_full; // Store Buffer full signal - logic stb_empty; // Store Buffer empty signal - logic rd_sel; // selection for read mux - logic stb_bypass; +// store_buffer_top --> dcache + logic [DCACHE_ADDR_WIDTH-1:0] stb2dcache_addr; + logic [DCACHE_DATA_WIDTH-1:0] stb2dcache_wdata; + logic [3:0] stb2dcache_sel_byte; + logic stb2dcache_w_en; + logic stb2dcache_req; + +// dcache --> store buffer top + logic [DCACHE_DATA_WIDTH-1:0] dcache2stb_rdata; + logic dcache2stb_ack; + +// lsummu --> stb (store buffer) + logic [DCACHE_ADDR_WIDTH-1:0] lsummu2stb_addr; + logic [DCACHE_DATA_WIDTH-1:0] lsummu2stb_wdata; + logic [3:0] lsummu2stb_sel_byte; + logic lsummu2stb_w_en; + logic lsummu2stb_req; + +// stb (store buffer) --> lsummu + logic stb2lsummu_ack; + logic [DCACHE_DATA_WIDTH-1:0] stb2lsummu_rdata; + +// Local Signals + logic stb_wr_en; // Store Buffer Write Enable (from LSU controller) + logic stb_rd_en; // Store Buffer Read Enable (from Cache controller) + logic stb_full; // Store Buffer full signal + logic stb_empty; // Store Buffer empty signal + logic rd_sel; // selection for read mux + logic stb_bypass; // Buffer Bypass signal + logic stb_stall; // Buffer Stall signal + +// lsummu --> stb (store buffer) + assign lsummu2stb_addr = lsummu2stb_i.addr; + assign lsummu2stb_wdata = lsummu2stb_i.w_data; + assign lsummu2stb_sel_byte = lsummu2stb_i.sel_byte; + assign lsummu2stb_w_en = lsummu2stb_i.w_en; + assign lsummu2stb_req = lsummu2stb_i.req; + +// dcache --> store_buffer_top + assign dcache2stb_ack = dcache2stb_i.ack; + assign dcache2stb_rdata = dcache2stb_i.r_data; assign stb2lsummu_rdata = dcache2stb_rdata; // bypassing rdata signal assign stb_bypass = ((lsummu2stb_req & !lsummu2stb_w_en) | (!lsummu2stb_req & !lsummu2stb_w_en)) & stb_empty; - // Instantiate the Store Buffer Datapath +/* =========================================== Store Buffer Datapath ============================================= */ store_buffer_datapath #( - .BLEN(BLEN), - .ADDR_WIDTH(ADDR_WIDTH), - .DATA_WIDTH(DATA_WIDTH), - .BYTE_SEL_WIDTH(BYTE_SEL_WIDTH) + .BLEN(BLEN) ) u_store_buffer ( .clk (clk), .rst_n (rst_n), @@ -80,7 +117,7 @@ module store_buffer_top #( .stb_bypass (stb_bypass) ); - // Instantiate the LSU to Store Buffer Controller +/* =========================================== LSU to Store Buffer Controller ==================================== */ lsu_stb_controller u_lsu_stb_controller ( .clk (clk), .rst_n (rst_n), @@ -106,10 +143,10 @@ module store_buffer_top #( .stb_wr_en (stb_wr_en), // lsu_stb_controller --> LSU - .stb2lsummu_stall (stb2lsummu_stall) + .stb2lsummu_stall (stb_stall) ); - // Instantiate the Store Buffer to Cache Controller +/* =========================================== Store Buffer to Cache Controller ================================== */ stb_cache_controller u_stb_cache_controller ( .clk (clk), .rst_n (rst_n), @@ -138,6 +175,18 @@ module store_buffer_top #( .dmem_sel_o (dmem_sel_o) ); -assign stb2dcache_empty = stb_empty; +/* =========================================== Output signals ==================================================== */ + assign stb2dcache_empty = stb_empty; + + // stb (store buffer) --> lsummu + assign stb2lsummu_o.ack = stb2lsummu_ack; + assign stb2lsummu_o.r_data = stb2lsummu_rdata; + + // store_buffer_top --> dcache + assign stb2dcache_o.addr = stb2dcache_addr; + assign stb2dcache_o.w_data = stb2dcache_wdata; + assign stb2dcache_o.sel_byte = stb2dcache_sel_byte; + assign stb2dcache_o.w_en = stb2dcache_w_en; + assign stb2dcache_o.req = stb2dcache_req; endmodule From d9b2d7dbf5824a32b2fc2199949bbd79b422388a Mon Sep 17 00:00:00 2001 From: Fazail Date: Mon, 18 Nov 2024 18:05:15 +0500 Subject: [PATCH 4/8] Added Bypassing in the store buffer top module and Update cache signals type from lsummu to stb --- rtl/defines/cache_defs.svh | 7 +- rtl/memory/mem_top.sv | 11 +- rtl/memory/store-buffer/lsu_stb_controller.sv | 122 +++++---------- .../store-buffer/stb_cache_controller.sv | 79 +++------- .../store-buffer/store_buffer_datapath.sv | 57 +++---- rtl/memory/store-buffer/store_buffer_top.sv | 143 +++++++++++------- rtl/memory/wb_dcache/wb_dcache_controller.sv | 42 ++--- rtl/memory/wb_dcache/wb_dcache_datapath.sv | 50 +++--- rtl/memory/wb_dcache/wb_dcache_top.sv | 30 ++-- 9 files changed, 243 insertions(+), 298 deletions(-) diff --git a/rtl/defines/cache_defs.svh b/rtl/defines/cache_defs.svh index 96baef5f..8bc619fb 100644 --- a/rtl/defines/cache_defs.svh +++ b/rtl/defines/cache_defs.svh @@ -79,6 +79,9 @@ parameter DCACHE_TAG_LSB = DCACHE_ADDR_WIDTH - DCACHE_TAG_BITS; parameter DCACHE_MAX_IDX = DCACHE_IDX_BITS'(DCACHE_NO_OF_SETS - 1); +parameter STORE_BUFFER_WIDTH = 4; +parameter BLEN = STORE_BUFFER_WIDTH; + typedef enum logic [2:0] { DCACHE_IDLE, DCACHE_PROCESS_REQ, @@ -91,7 +94,7 @@ typedef enum logic [2:0] { } type_dcache_states_e; // Bus interface from LSU to dcache -typedef struct packed { +/*typedef struct packed { logic [DCACHE_ADDR_WIDTH-1:0] addr; logic [DCACHE_DATA_WIDTH-1:0] w_data; logic [3:0] sel_byte; @@ -103,7 +106,7 @@ typedef struct packed { typedef struct packed { logic [DCACHE_DATA_WIDTH-1:0] r_data; logic ack; -} type_dcache2lsummu_s; +} type_dcache2lsummu_s;*/ // Bus interface from STB to dcache typedef struct packed { diff --git a/rtl/memory/mem_top.sv b/rtl/memory/mem_top.sv index aba8e361..2c25dc1c 100644 --- a/rtl/memory/mem_top.sv +++ b/rtl/memory/mem_top.sv @@ -95,7 +95,6 @@ type_dcache2stb_s dcache2stb; type_lsummu2stb_s lsummu2stb; type_stb2lsummu_s stb2lsummu; logic stb_dmem_sel_o; -//logic stb2lsummu_stall; logic stb2dcache_empty; // Signal assignments @@ -222,14 +221,12 @@ store_buffer_top store_buffer_top_module ( .clk (clk), .rst_n (rst_n), -// LSU --> store_buffer_top +// LSU/MMU --> store_buffer_top .lsummu2stb_i (lsummu2stb), .dmem_sel_i (dmem_sel), -// store_buffer_top --> LSU +// store_buffer_top --> LSU/MMU .stb2lsummu_o (stb2lsummu), - //.stb2lsummu_stall (stb2lsummu_stall), - // store_buffer_top --> dcache .stb2dcache_o (stb2dcache), @@ -246,9 +243,9 @@ wb_dcache_top wb_dcache_top_module( .rst_n (rst_n), // LSU/MMU to data cache interface - .lsummu2dcache_i (stb2dcache), // lsummu2dmem + .stb2dcache_i (stb2dcache), // stb2dcache - .dcache2lsummu_o (dcache2stb), // dmem2lsummu + .dcache2stb_o (dcache2stb), // dcache2stb .stb2dcache_empty (stb2dcache_empty), diff --git a/rtl/memory/store-buffer/lsu_stb_controller.sv b/rtl/memory/store-buffer/lsu_stb_controller.sv index ff266580..ac9ec414 100644 --- a/rtl/memory/store-buffer/lsu_stb_controller.sv +++ b/rtl/memory/store-buffer/lsu_stb_controller.sv @@ -20,17 +20,13 @@ module lsu_stb_controller ( input logic stb_full, // Store buffer stb_full flag input logic stb_empty, // store buffer stb_empty flag - input logic stb_bypass, - input logic dcache2stb_ack, - // lsu_stb_controller --> LSU - output logic stb2lsummu_ack, // stb_acknowledgement signal - output logic stb2lsummu_stall, // Stall signal if buffer is stb_full + output logic stb_ack, // stb_acknowledgement signal + output logic stb_stall, // Stall signal if buffer is stb_full // lsu_stb_controller --> store_buffer_datapath - output logic stb_wr_en // Store buffer write enable + output logic wr_en // Store buffer write enable ); - logic ack, d_ack; typedef enum logic [1:0] { SB_IDLE = 2'b00, @@ -48,114 +44,80 @@ module lsu_stb_controller ( current_state <= next_state; end - always_ff @(posedge clk or negedge rst_n) begin - if (!rst_n) - d_ack <= 0; - else if (stb_bypass) - d_ack <= 1; - else - d_ack <= '0; - end - - always_comb begin - case (stb_bypass) - 1'b1: begin - stb2lsummu_ack = dcache2stb_ack; - end - 1'b0: begin - if (d_ack) stb2lsummu_ack = dcache2stb_ack; - else stb2lsummu_ack = ack; - end - default: begin - stb2lsummu_ack = ack; - end - endcase - end - // Next state logic (combinational) always_comb begin // Default values - stb_wr_en = 1'b0; - stb2lsummu_stall = 1'b0; - ack = 1'b0; + wr_en = 1'b0; + stb_stall = 1'b0; + stb_ack = 1'b0; case (current_state) SB_IDLE: begin if (dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req && !stb_full) begin - stb_wr_en = 1'b1; // Enable write to buffer - stb2lsummu_stall = 1'b0; - ack = 1'b0; - next_state = SB_WRITE; + wr_en = 1'b1; // Enable write to buffer + stb_stall = 1'b0; + stb_ack = 1'b0; + next_state = SB_WRITE; end else if (dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req && stb_full) begin - stb2lsummu_stall = 1'b1; - stb_wr_en = 1'b0; - ack = 1'b0; - next_state = SB_FULL; + stb_stall = 1'b1; + wr_en = 1'b0; + stb_ack = 1'b0; + next_state = SB_FULL; end else begin - stb2lsummu_stall = 1'b0; - stb_wr_en = 1'b0; - ack = 1'b0; - next_state = SB_IDLE; + stb_stall = 1'b0; + wr_en = 1'b0; + stb_ack = 1'b0; + next_state = SB_IDLE; end end SB_WRITE: begin - ack = 1'b1; + stb_ack = 1'b1; if (dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req && !stb_full)begin - stb_wr_en = 1'b1; // Enable write to buffer - stb2lsummu_stall = 1'b0; - //ack = 1'b1; - next_state = SB_WRITE; + wr_en = 1'b1; // Enable write to buffer + stb_stall = 1'b0; + next_state = SB_WRITE; end else if (dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req && stb_full)begin - stb_wr_en = 1'b0; - stb2lsummu_stall = 1'b1; - //ack = 1'b0; - next_state = SB_FULL; + wr_en = 1'b0; + stb_stall = 1'b1; + next_state = SB_FULL; end else if (!stb_empty) begin if (dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req) begin - stb_wr_en = 1'b1; - //ack = 1'b1; - next_state = SB_WRITE; // Transition to stb_full state if buffer is stb_full + wr_en = 1'b1; + next_state = SB_WRITE; // Transition to stb_full state if buffer is stb_full end else begin - stb_wr_en = 1'b0; - //ack = 1'b0; - next_state = SB_IDLE; + wr_en = 1'b0; + next_state = SB_IDLE; end end end SB_FULL: begin - stb2lsummu_stall = 1'b1; // Stall signal if buffer is stb_full + stb_stall = 1'b1; // Stall signal if buffer is stb_full if (dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req && !stb_full) begin - stb_wr_en = 1'b1; - stb2lsummu_stall = 1'b0; - ack = 1'b0; - next_state = SB_WRITE; // Go to idle once buffer is not stb_full + wr_en = 1'b1; + stb_stall = 1'b0; + stb_ack = 1'b0; + next_state = SB_WRITE; // Go to idle once buffer is not stb_full end else if(dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req && stb_full) begin - stb_wr_en = 1'b0; - ack = 1'b0; - next_state = SB_FULL; + wr_en = 1'b0; + stb_ack = 1'b0; + next_state = SB_FULL; end - /*else if (!(dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req)) begin - stb_wr_en = 1'b0; - stb2lsummu_stall = 1'b0; - ack = 1'b0; - next_state = SB_IDLE; - end*/ else begin - stb_wr_en = 1'b0; - stb2lsummu_stall = 1'b0; - ack = 1'b0; - next_state = SB_IDLE; + wr_en = 1'b0; + stb_stall = 1'b0; + stb_ack = 1'b0; + next_state = SB_IDLE; end end - default: next_state = SB_IDLE; + default: next_state = SB_IDLE; endcase end diff --git a/rtl/memory/store-buffer/stb_cache_controller.sv b/rtl/memory/store-buffer/stb_cache_controller.sv index 51dcb98c..dc11d047 100644 --- a/rtl/memory/store-buffer/stb_cache_controller.sv +++ b/rtl/memory/store-buffer/stb_cache_controller.sv @@ -14,29 +14,20 @@ module stb_cache_controller ( // store_buffer_datapath --> stb_cache_controller input logic stb_full, // Store buffer full flag input logic stb_empty, // Store buffer empty flag - - input logic stb_bypass, // dcache --> stb_cache_controller input logic dcache2stb_ack, // Acknowledgement from cache - // LSU --> lsu_stb_controller - input logic lsummu2stb_w_en, // Write enable from LSU - input logic lsummu2stb_req, // Store request from LSU - input logic dmem_sel_i, // Input from LSU (data memory select) - // stb_cache_controller --> store_buffer_datapath - output logic stb_rd_en, // enable for read counter + output logic rd_en, // enable for read counter output logic rd_sel, // Store buffer mux read selection // stb_cache_controller --> dcache - output logic stb2dcache_req, // Store buffer request signal - output logic stb2dcache_w_en, // Last word enable (for last write to cache) - output logic dmem_sel_o + output logic stb_req, // Store buffer request signal + output logic stb_w_en, // Last word enable (for last write to cache) + output logic dm_sel ); -logic req, w_en, dm_sel; - typedef enum logic [1:0] { IDLE = 2'b00, SB_CACHE_WRITE = 2'b01 @@ -52,52 +43,32 @@ logic req, w_en, dm_sel; current_state <= next_state; end - always_comb begin - case (stb_bypass) - 1'b1: begin - stb2dcache_req = lsummu2stb_req; - stb2dcache_w_en = lsummu2stb_w_en; - dmem_sel_o = dmem_sel_i; - end - 1'b0: begin - stb2dcache_req = req; - stb2dcache_w_en = w_en; - dmem_sel_o = dm_sel; - end - default: begin - stb2dcache_req = req; - stb2dcache_w_en = w_en; - dmem_sel_o = dm_sel; - end - endcase - end - // Next state logic (combinational) always_comb begin // Default values rd_sel = 1'b0; - req = 1'b0; - w_en = 1'b0; - stb_rd_en = 1'b0; + stb_req = 1'b0; + stb_w_en = 1'b0; + rd_en = 1'b0; dm_sel = 1'b0; next_state = current_state; case (current_state) IDLE: begin if (!stb_empty || stb_full) begin - req = 1'b1; // Request cache write + stb_req = 1'b1; // Request cache write rd_sel = 1'b1; // Read selection for store buffer - w_en = 1'b1; + stb_w_en = 1'b1; dm_sel = 1'b1; - stb_rd_en = 1'b0; + rd_en = 1'b0; next_state = SB_CACHE_WRITE; end else if(stb_empty) begin rd_sel = 1'b0; - req = 1'b0; - w_en = 1'b0; - stb_rd_en = 1'b0; + stb_req = 1'b0; + stb_w_en = 1'b0; + rd_en = 1'b0; dm_sel = 1'b0; next_state = IDLE; end @@ -105,36 +76,36 @@ logic req, w_en, dm_sel; SB_CACHE_WRITE: begin if (!dcache2stb_ack && !stb_empty) begin - req = 1'b1; + stb_req = 1'b1; rd_sel = 1'b1; - w_en = 1'b1; + stb_w_en = 1'b1; dm_sel = 1'b1; - stb_rd_en = 1'b0; + rd_en = 1'b0; next_state = SB_CACHE_WRITE; // Stay SB_CACHE_WRITE state till store buffer contain data end else if (dcache2stb_ack && !stb_empty) begin - req = 1'b0; + stb_req = 1'b0; rd_sel = 1'b0; - w_en = 1'b0; + stb_w_en = 1'b0; dm_sel = 1'b1; - stb_rd_en = 1'b1; + rd_en = 1'b1; next_state = SB_CACHE_WRITE; // Stay SB_CACHE_WRITE state till all data written to cache then cache acknowledges set end else if (dcache2stb_ack && stb_empty) begin - req = 1'b0; + stb_req = 1'b0; rd_sel = 1'b0; - w_en = 1'b0; + stb_w_en = 1'b0; dm_sel = 1'b1; - stb_rd_en = 1'b1; + rd_en = 1'b1; next_state = IDLE; end else if (stb_empty) begin - req = 1'b0; + stb_req = 1'b0; rd_sel = 1'b0; - w_en = 1'b0; + stb_w_en = 1'b0; dm_sel = 1'b0; - stb_rd_en = 1'b0; + rd_en = 1'b0; next_state = IDLE; end end diff --git a/rtl/memory/store-buffer/store_buffer_datapath.sv b/rtl/memory/store-buffer/store_buffer_datapath.sv index 307159f1..f4544600 100644 --- a/rtl/memory/store-buffer/store_buffer_datapath.sv +++ b/rtl/memory/store-buffer/store_buffer_datapath.sv @@ -8,20 +8,14 @@ // Date: 15.11.2024 `ifndef VERILATOR -`include "../defines/mmu_defs.svh" `include "../defines/cache_defs.svh" -`include "../defines/ddr_defs.svh" `else -`include "mmu_defs.svh" `include "cache_defs.svh" -`include "ddr_defs.svh" `endif -module store_buffer_datapath #( - parameter BLEN = 4 // Buffer Length -)( - input logic clk, - input logic rst_n, +module store_buffer_datapath ( + input logic clk, + input logic rst_n, // LSU --> store_buffer_datapath input logic [DCACHE_ADDR_WIDTH-1:0] lsummu2stb_addr, // Address input from LSU/MMU @@ -29,29 +23,26 @@ module store_buffer_datapath #( input logic [3:0] lsummu2stb_sel_byte, // Byte selection input from LSU/MMU // lsu_stb_controller --> store_buffer_datapath - input logic stb_wr_en, // Write enable signal + input logic wr_en, // Write enable signal // stb_cache_controller --> store_buffer_datapath - input logic stb_rd_en, // Read enable signal + input logic rd_en, // Read enable signal input logic rd_sel, // Read Selection signal // store_buffer_datapath --> dcache - output logic [DCACHE_ADDR_WIDTH-1:0] stb2dcache_addr, // Address output to Cache - output logic [DCACHE_DATA_WIDTH-1:0] stb2dcache_wdata, // Data output to Cache - output logic [3:0] stb2dcache_sel_byte, // Byte selection output to Cache + output logic [DCACHE_ADDR_WIDTH-1:0] stb_addr, // Address output to Cache + output logic [DCACHE_DATA_WIDTH-1:0] stb_wdata, // Data output to Cache + output logic [3:0] stb_sel_byte, // Byte selection output to Cache // store_buffer_datapath --> store buffer controllers - output logic stb_full, // Full signal - output logic stb_empty, // Empty signal - - input logic stb_bypass + output logic stb_full, // Full signal + output logic stb_empty // Empty signal ); // Buffer Registers (arrays to hold multiple entries) logic [DCACHE_ADDR_WIDTH-1:0] addr_buf [BLEN-1:0]; logic [DCACHE_DATA_WIDTH-1:0] data_buf [BLEN-1:0]; logic [3:0] sel_byte_buf [BLEN-1:0]; - // logic [BLEN-1:0] valid_buf; // Valid entries in buffer // Buffer Counter (to track read and write index) logic [$clog2(BLEN)-1:0] rd_index, rd_index_add; @@ -63,7 +54,7 @@ module store_buffer_datapath #( if (!rst_n) begin wr_index <= 0; end - else if (stb_wr_en) begin + else if (wr_en) begin wr_index <= wr_index_add; end else begin @@ -77,7 +68,7 @@ module store_buffer_datapath #( if (!rst_n) begin rd_index <= 0; end - else if (stb_rd_en) begin + else if (rd_en) begin rd_index <= rd_index_add; end else begin @@ -92,7 +83,7 @@ module store_buffer_datapath #( data_buf <= data_buf ; sel_byte_buf <= sel_byte_buf; end - else if (stb_wr_en) begin + else if (wr_en) begin // Write new values to buffer at wr_index addr_buf [wr_index] <= lsummu2stb_addr; data_buf [wr_index] <= lsummu2stb_wdata; @@ -106,20 +97,14 @@ module store_buffer_datapath #( end always_comb begin - if (stb_bypass) begin - stb2dcache_addr = lsummu2stb_addr; - stb2dcache_wdata = lsummu2stb_wdata; - stb2dcache_sel_byte = lsummu2stb_sel_byte; - end - else if (rd_sel) begin - stb2dcache_addr = addr_buf [rd_index]; - stb2dcache_wdata = data_buf [rd_index]; - stb2dcache_sel_byte = sel_byte_buf [rd_index]; - end - else begin - stb2dcache_addr = '0; - stb2dcache_wdata = '0; - stb2dcache_sel_byte = '0; + if (rd_sel) begin + stb_addr = addr_buf [rd_index]; + stb_wdata = data_buf [rd_index]; + stb_sel_byte = sel_byte_buf [rd_index]; + end else begin + stb_addr = '0; + stb_wdata = '0; + stb_sel_byte = '0; end end diff --git a/rtl/memory/store-buffer/store_buffer_top.sv b/rtl/memory/store-buffer/store_buffer_top.sv index 93bdb89f..1fd1f0bd 100644 --- a/rtl/memory/store-buffer/store_buffer_top.sv +++ b/rtl/memory/store-buffer/store_buffer_top.sv @@ -8,18 +8,12 @@ // Date: 15.11.2024 `ifndef VERILATOR -`include "../defines/mmu_defs.svh" `include "../defines/cache_defs.svh" -`include "../defines/ddr_defs.svh" `else -`include "mmu_defs.svh" `include "cache_defs.svh" -`include "ddr_defs.svh" `endif -module store_buffer_top #( - parameter BLEN = 4 // Buffer Length -)( +module store_buffer_top ( input logic clk, // Clock input logic rst_n, // Reset, active low @@ -29,7 +23,6 @@ module store_buffer_top #( // store_buffer_top --> LSU output type_stb2lsummu_s stb2lsummu_o, - //output logic stb2lsummu_stall, // Stall signal // store_buffer_top --> dcache output type_stb2dcache_s stb2dcache_o, @@ -41,55 +34,105 @@ module store_buffer_top #( input wire type_dcache2stb_s dcache2stb_i ); -// store_buffer_top --> dcache +// store_buffer_top --> dcache Signals logic [DCACHE_ADDR_WIDTH-1:0] stb2dcache_addr; logic [DCACHE_DATA_WIDTH-1:0] stb2dcache_wdata; logic [3:0] stb2dcache_sel_byte; logic stb2dcache_w_en; logic stb2dcache_req; -// dcache --> store buffer top +// dcache --> store buffer top Signals logic [DCACHE_DATA_WIDTH-1:0] dcache2stb_rdata; logic dcache2stb_ack; -// lsummu --> stb (store buffer) +// lsummu --> stb (store buffer) Signals logic [DCACHE_ADDR_WIDTH-1:0] lsummu2stb_addr; logic [DCACHE_DATA_WIDTH-1:0] lsummu2stb_wdata; logic [3:0] lsummu2stb_sel_byte; logic lsummu2stb_w_en; logic lsummu2stb_req; -// stb (store buffer) --> lsummu +// stb (store buffer) --> lsummu Signals logic stb2lsummu_ack; logic [DCACHE_DATA_WIDTH-1:0] stb2lsummu_rdata; // Local Signals - logic stb_wr_en; // Store Buffer Write Enable (from LSU controller) - logic stb_rd_en; // Store Buffer Read Enable (from Cache controller) + logic wr_en; // Store Buffer Write Enable (from LSU controller) + logic rd_en; // Store Buffer Read Enable (from Cache controller) logic stb_full; // Store Buffer full signal logic stb_empty; // Store Buffer empty signal logic rd_sel; // selection for read mux logic stb_bypass; // Buffer Bypass signal logic stb_stall; // Buffer Stall signal -// lsummu --> stb (store buffer) + logic stb_ack; + + logic [DCACHE_ADDR_WIDTH-1:0] stb_addr; + logic [DCACHE_DATA_WIDTH-1:0] stb_wdata; + logic [3:0] stb_sel_byte; + logic stb_req; + logic stb_w_en; + logic dm_sel; + +/* =========================================== Input signals ===================================================== */ + // lsummu --> stb (store buffer) assign lsummu2stb_addr = lsummu2stb_i.addr; assign lsummu2stb_wdata = lsummu2stb_i.w_data; assign lsummu2stb_sel_byte = lsummu2stb_i.sel_byte; assign lsummu2stb_w_en = lsummu2stb_i.w_en; assign lsummu2stb_req = lsummu2stb_i.req; -// dcache --> store_buffer_top + // dcache --> store_buffer_top assign dcache2stb_ack = dcache2stb_i.ack; assign dcache2stb_rdata = dcache2stb_i.r_data; - assign stb2lsummu_rdata = dcache2stb_rdata; // bypassing rdata signal +/* =========================================== Bypassing Store buffer for Load Instructions ====================== */ + // Store Buffer bypass for load instructions assign stb_bypass = ((lsummu2stb_req & !lsummu2stb_w_en) | (!lsummu2stb_req & !lsummu2stb_w_en)) & stb_empty; + always_comb begin + case (stb_bypass) + 1'b1: begin + stb2lsummu_ack = dcache2stb_ack; + stb2lsummu_rdata = dcache2stb_rdata; + + stb2dcache_addr = lsummu2stb_addr; + stb2dcache_wdata = lsummu2stb_wdata; + stb2dcache_sel_byte = lsummu2stb_sel_byte; + stb2dcache_req = lsummu2stb_req; + stb2dcache_w_en = lsummu2stb_w_en; + + dmem_sel_o = dmem_sel_i; + end + 1'b0: begin + stb2lsummu_ack = stb_ack; + stb2lsummu_rdata = '0; + + stb2dcache_addr = stb_addr; + stb2dcache_wdata = stb_wdata; + stb2dcache_sel_byte = stb_sel_byte; + stb2dcache_req = stb_req; + stb2dcache_w_en = stb_w_en; + + dmem_sel_o = dm_sel; + end + default: begin + stb2lsummu_ack = stb_ack; + stb2lsummu_rdata = '0; + + stb2dcache_addr = stb_addr; + stb2dcache_wdata = stb_wdata; + stb2dcache_sel_byte = stb_sel_byte; + stb2dcache_req = stb_req; + stb2dcache_w_en = stb_w_en; + + dmem_sel_o = dm_sel; + end + endcase + end + /* =========================================== Store Buffer Datapath ============================================= */ - store_buffer_datapath #( - .BLEN(BLEN) - ) u_store_buffer ( + store_buffer_datapath u_store_buffer ( .clk (clk), .rst_n (rst_n), @@ -99,22 +142,20 @@ module store_buffer_top #( .lsummu2stb_sel_byte (lsummu2stb_sel_byte), // lsu_stb_controller --> store_buffer_datapath - .stb_wr_en (stb_wr_en), + .wr_en (wr_en), // stb_cache_controller --> store_buffer_datapath - .stb_rd_en (stb_rd_en), + .rd_en (rd_en), .rd_sel (rd_sel), // store_buffer_datapath --> dcache - .stb2dcache_addr (stb2dcache_addr), - .stb2dcache_wdata (stb2dcache_wdata), - .stb2dcache_sel_byte (stb2dcache_sel_byte), + .stb_addr (stb_addr), + .stb_wdata (stb_wdata), + .stb_sel_byte (stb_sel_byte), // store_buffer --> store_buffer_controllers .stb_full (stb_full), - .stb_empty (stb_empty), - - .stb_bypass (stb_bypass) + .stb_empty (stb_empty) ); /* =========================================== LSU to Store Buffer Controller ==================================== */ @@ -129,21 +170,14 @@ module store_buffer_top #( // store_buffer_datapath --> lsu_stb_controller .stb_full (stb_full), - .stb_empty (stb_empty), - - .stb_bypass (stb_bypass), - - // dcache --> stb_cache_controller - .dcache2stb_ack (dcache2stb_ack), + .stb_empty (stb_empty), // lsu_stb_controller --> LSU - .stb2lsummu_ack (stb2lsummu_ack), + .stb_ack (stb_ack), + .stb_stall (stb_stall), // lsu_stb_controller --> store_buffer_datapath - .stb_wr_en (stb_wr_en), - - // lsu_stb_controller --> LSU - .stb2lsummu_stall (stb_stall) + .wr_en (wr_en) ); /* =========================================== Store Buffer to Cache Controller ================================== */ @@ -155,38 +189,31 @@ module store_buffer_top #( .stb_full (stb_full), .stb_empty (stb_empty), - .stb_bypass (stb_bypass), - - // LSU --> lsu_stb_controller - .lsummu2stb_w_en (lsummu2stb_w_en), - .lsummu2stb_req (lsummu2stb_req), - .dmem_sel_i (dmem_sel_i), - // dcache --> stb_cache_controller .dcache2stb_ack (dcache2stb_ack), // stb_cache_controller --> store_buffer_datapath - .stb_rd_en (stb_rd_en), + .rd_en (rd_en), .rd_sel (rd_sel), // stb_cache_controller --> dcache - .stb2dcache_req (stb2dcache_req), - .stb2dcache_w_en (stb2dcache_w_en), - .dmem_sel_o (dmem_sel_o) + .stb_req (stb_req), + .stb_w_en (stb_w_en), + .dm_sel (dm_sel) ); /* =========================================== Output signals ==================================================== */ - assign stb2dcache_empty = stb_empty; + assign stb2dcache_empty = stb_empty; // stb (store buffer) --> lsummu - assign stb2lsummu_o.ack = stb2lsummu_ack; - assign stb2lsummu_o.r_data = stb2lsummu_rdata; + assign stb2lsummu_o.ack = stb2lsummu_ack; + assign stb2lsummu_o.r_data = stb2lsummu_rdata; // store_buffer_top --> dcache - assign stb2dcache_o.addr = stb2dcache_addr; - assign stb2dcache_o.w_data = stb2dcache_wdata; - assign stb2dcache_o.sel_byte = stb2dcache_sel_byte; - assign stb2dcache_o.w_en = stb2dcache_w_en; - assign stb2dcache_o.req = stb2dcache_req; + assign stb2dcache_o.addr = stb2dcache_addr; + assign stb2dcache_o.w_data = stb2dcache_wdata; + assign stb2dcache_o.sel_byte = stb2dcache_sel_byte; + assign stb2dcache_o.w_en = stb2dcache_w_en; + assign stb2dcache_o.req = stb2dcache_req; endmodule diff --git a/rtl/memory/wb_dcache/wb_dcache_controller.sv b/rtl/memory/wb_dcache/wb_dcache_controller.sv index 9dcd24d1..d775a42e 100644 --- a/rtl/memory/wb_dcache/wb_dcache_controller.sv +++ b/rtl/memory/wb_dcache/wb_dcache_controller.sv @@ -30,9 +30,9 @@ module wb_dcache_controller ( output logic [DCACHE_IDX_BITS-1:0] evict_index_o, // LSU/MMU to data cache interface - input wire lsummu2dcache_req_i, - input wire lsummu2dcache_wr_i, - output logic dcache2lsummu_ack_o, + input wire stb2dcache_req_i, + input wire stb2dcache_wr_i, + output logic dcache2stb_ack_o, input wire dcache_kill_i, // Data memory to data cache interface @@ -47,8 +47,8 @@ module wb_dcache_controller ( type_dcache_states_e dcache_state_ff, dcache_state_next; logic [DCACHE_IDX_BITS-1:0] evict_index_next, evict_index_ff; -logic lsummu2dcache_wr_ff; -logic dcache2lsummu_ack; +logic stb2dcache_wr_ff; +logic dcache2stb_ack; logic dcache_hit; logic dcache_miss; logic dcache_evict; @@ -60,22 +60,22 @@ logic cache_wr; logic cache_line_wr; logic cache_line_clean; logic dcache2mem_kill; -logic lsummu2dcache_req_ff, dmem_sel_ff; +logic stb2dcache_req_ff, dmem_sel_ff; -assign dcache_hit = lsummu2dcache_req_ff & dmem_sel_ff & cache_hit_i; -assign dcache_miss = lsummu2dcache_req_ff & dmem_sel_ff & ~cache_hit_i ; +assign dcache_hit = stb2dcache_req_ff & dmem_sel_ff & cache_hit_i; +assign dcache_miss = stb2dcache_req_ff & dmem_sel_ff & ~cache_hit_i ; assign dcache_evict = cache_evict_req_i; always_ff@(posedge clk) begin if(!rst_n) begin - lsummu2dcache_req_ff <= '0; + stb2dcache_req_ff <= '0; dmem_sel_ff <= '0; - lsummu2dcache_wr_ff <= '0; + stb2dcache_wr_ff <= '0; end else begin - lsummu2dcache_req_ff <= lsummu2dcache_req_i; + stb2dcache_req_ff <= stb2dcache_req_i; dmem_sel_ff <= dmem_sel_i; - lsummu2dcache_wr_ff <= lsummu2dcache_wr_i; + stb2dcache_wr_ff <= stb2dcache_wr_i; end end @@ -94,7 +94,7 @@ end always_comb begin dcache_state_next = dcache_state_ff; evict_index_next = evict_index_ff; - dcache2lsummu_ack = 1'b0; + dcache2stb_ack = 1'b0; dcache2mem_req = 1'b0; dcache2mem_wr = 1'b0; cache_wrb_req = 1'b0; @@ -108,7 +108,7 @@ always_comb begin // In case of flush, go to FLUSH State if (dcache_flush_i) begin dcache_state_next = DCACHE_FLUSH; - end else if (lsummu2dcache_req_i) begin + end else if (stb2dcache_req_i) begin dcache_state_next = DCACHE_PROCESS_REQ; end else begin dcache_state_next = DCACHE_IDLE; @@ -121,12 +121,12 @@ always_comb begin if (dcache_hit) begin // In case of hit, perform the cache read/write operation - if (lsummu2dcache_wr_ff) begin + if (stb2dcache_wr_ff) begin cache_wr = 1'b1; dcache_state_next = DCACHE_IDLE; - dcache2lsummu_ack = 1'b1; + dcache2stb_ack = 1'b1; end else begin - dcache2lsummu_ack = 1'b1; + dcache2stb_ack = 1'b1; dcache_state_next = DCACHE_IDLE; end @@ -144,7 +144,7 @@ always_comb begin end DCACHE_WRITE: begin dcache_state_next = DCACHE_IDLE; - dcache2lsummu_ack = 1'b1; + dcache2stb_ack = 1'b1; end DCACHE_ALLOCATE: begin @@ -192,7 +192,7 @@ always_comb begin end else begin if (&evict_index_ff) begin // evict_index_ff == DCACHE_MAX_IDX dcache_state_next = DCACHE_FLUSH_DONE; - // dcache2lsummu_ack = 1'b1; + // dcache2stb_ack = 1'b1; evict_index_next = '0; end else begin evict_index_next = evict_index_ff + 1; @@ -202,7 +202,7 @@ always_comb begin end DCACHE_FLUSH_DONE: begin - dcache2lsummu_ack = 1'b1; + dcache2stb_ack = 1'b1; dcache_state_next = DCACHE_IDLE; end default: begin @@ -232,6 +232,6 @@ assign dcache2mem_wr_o = dcache2mem_wr; assign dcache2mem_req_o = dcache2mem_req; assign dcache2mem_kill_o = dcache2mem_kill; -assign dcache2lsummu_ack_o = dcache2lsummu_ack; +assign dcache2stb_ack_o = dcache2stb_ack; endmodule diff --git a/rtl/memory/wb_dcache/wb_dcache_datapath.sv b/rtl/memory/wb_dcache/wb_dcache_datapath.sv index d9209a29..394fccf1 100644 --- a/rtl/memory/wb_dcache/wb_dcache_datapath.sv +++ b/rtl/memory/wb_dcache/wb_dcache_datapath.sv @@ -29,11 +29,11 @@ module wb_dcache_datapath( // LSU/MMU to data cache interface input wire dcache_flush_i, - input wire lsummu2dcache_req_i, - input wire [DCACHE_ADDR_WIDTH-1:0] lsummu2dcache_addr_i, - input wire [DCACHE_DATA_WIDTH-1:0] lsummu2dcache_wdata_i, + input wire stb2dcache_req_i, + input wire [DCACHE_ADDR_WIDTH-1:0] stb2dcache_addr_i, + input wire [DCACHE_DATA_WIDTH-1:0] stb2dcache_wdata_i, input wire [3:0] sel_byte_i, - output logic [DCACHE_DATA_WIDTH-1:0] dcache2lsummu_data_o, + output logic [DCACHE_DATA_WIDTH-1:0] dcache2stb_data_o, // Data cache to data memory interface input wire [DCACHE_LINE_WIDTH-1:0] mem2dcache_data_i, @@ -47,13 +47,13 @@ type_dcache_data_s cache_line_read, cache_line_write, cache_wd type_dcache_tag_s cache_tag_read, cache_tag_write; logic [DCACHE_DATA_WIDTH-1:0] cache_word_read, cache_word_write; -logic [DCACHE_DATA_WIDTH-1:0] lsummu2dcache_wdata; +logic [DCACHE_DATA_WIDTH-1:0] stb2dcache_wdata; logic [DCACHE_ADDR_WIDTH-1:0] dcache2mem_addr; logic [15:0] cache_line_sel_byte, cache_data_wr_sel; logic [3:0] sel_byte; logic [3:0] cache_tag_wr_sel; -logic [DCACHE_DATA_WIDTH-1:0] dcache2lsummu_data_ff, dcache2lsummu_data_next; +logic [DCACHE_DATA_WIDTH-1:0] dcache2stb_data_ff, dcache2stb_data_next; logic [DCACHE_TAG_BITS-1:0] addr_tag, addr_tag_ff; logic [1:0] addr_offset, addr_offset_ff; logic [DCACHE_IDX_BITS-1:0] addr_index, addr_index_ff; @@ -63,20 +63,20 @@ logic dcache_flush; assign dcache_flush = dcache_flush_i; assign evict_index = evict_index_i; //assign sel_byte = sel_byte_i; -//assign lsummu2dcache_wdata = lsummu2dcache_wdata_i; +//assign stb2dcache_wdata = stb2dcache_wdata_i; -assign addr_tag = lsummu2dcache_addr_i[DCACHE_ADDR_WIDTH-1:DCACHE_TAG_LSB]; -assign addr_offset = lsummu2dcache_addr_i[DCACHE_OFFSET_BITS-1:2]; +assign addr_tag = stb2dcache_addr_i[DCACHE_ADDR_WIDTH-1:DCACHE_TAG_LSB]; +assign addr_offset = stb2dcache_addr_i[DCACHE_OFFSET_BITS-1:2]; assign addr_index = dcache_flush ? evict_index : cache_wr_i ? addr_index_ff : - lsummu2dcache_addr_i[DCACHE_TAG_LSB-1:DCACHE_OFFSET_BITS]; + stb2dcache_addr_i[DCACHE_TAG_LSB-1:DCACHE_OFFSET_BITS]; always_ff@(posedge clk) begin if(!rst_n) begin - lsummu2dcache_wdata <= '0; + stb2dcache_wdata <= '0; sel_byte <= '0; end else begin - lsummu2dcache_wdata <= lsummu2dcache_wdata_i; // MT + stb2dcache_wdata <= stb2dcache_wdata_i; // MT sel_byte <= sel_byte_i; end end @@ -103,10 +103,10 @@ end always_comb begin cache_word_write = '0; // MT cache_word_read - if (sel_byte[0]) cache_word_write[7:0] = lsummu2dcache_wdata[7:0]; - if (sel_byte[1]) cache_word_write[15:8] = lsummu2dcache_wdata[15:8]; - if (sel_byte[2]) cache_word_write[23:16] = lsummu2dcache_wdata[23:16]; - if (sel_byte[3]) cache_word_write[31:24] = lsummu2dcache_wdata[31:24]; + if (sel_byte[0]) cache_word_write[7:0] = stb2dcache_wdata[7:0]; + if (sel_byte[1]) cache_word_write[15:8] = stb2dcache_wdata[15:8]; + if (sel_byte[2]) cache_word_write[23:16] = stb2dcache_wdata[23:16]; + if (sel_byte[3]) cache_word_write[31:24] = stb2dcache_wdata[31:24]; end always_comb begin @@ -130,7 +130,7 @@ always_comb begin cache_line_write[127:96] = cache_word_write; cache_line_sel_byte[15:12] = sel_byte; end - // default: dcache2lsummu_data_next = '0; + // default: dcache2stb_data_next = '0; endcase end @@ -157,7 +157,7 @@ always_comb begin if (cache_wrb_req_i) begin dcache2mem_addr = {cache_tag_read.tag[DCACHE_TAG_BITS-1:0], addr_index, {{DCACHE_OFFSET_BITS}{1'b0}}}; end else begin - dcache2mem_addr = lsummu2dcache_addr_i; + dcache2mem_addr = stb2dcache_addr_i; end end @@ -167,9 +167,9 @@ assign cache_data_wr_sel = cache_line_wr_i ? 16'hFFFF : cache_wr_i ? cache_line_ always_ff@(posedge clk) begin if(!rst_n) begin - dcache2lsummu_data_ff <= '0; + dcache2stb_data_ff <= '0; end else begin - dcache2lsummu_data_ff <= dcache2lsummu_data_next; + dcache2stb_data_ff <= dcache2stb_data_next; end end @@ -179,7 +179,7 @@ always_ff@(posedge clk) begin addr_index_ff <= '0; end else begin addr_tag_ff <= addr_tag; - addr_index_ff <= lsummu2dcache_addr_i[DCACHE_TAG_LSB-1:DCACHE_OFFSET_BITS]; + addr_index_ff <= stb2dcache_addr_i[DCACHE_TAG_LSB-1:DCACHE_OFFSET_BITS]; end end @@ -187,7 +187,7 @@ dcache_data_ram dcache_data_ram_module ( .clk (clk), .rst_n (rst_n), - .req (lsummu2dcache_req_i), + .req (stb2dcache_req_i), .wr_en (cache_data_wr_sel), .addr (addr_index), .wdata (cache_wdata), @@ -199,7 +199,7 @@ dcache_tag_ram dcache_tag_ram_module ( .clk (clk), .rst_n (rst_n), - .req (lsummu2dcache_req_i), + .req (stb2dcache_req_i), .wr_en (cache_tag_wr_sel), .addr (addr_index), .wdata (cache_tag_write), @@ -208,12 +208,12 @@ dcache_tag_ram dcache_tag_ram_module ( // Output signals update -assign dcache2lsummu_data_next = cache_word_read; // Read data from cache to LSU/MMU +assign dcache2stb_data_next = cache_word_read; // Read data from cache to LSU/MMU assign cache_hit_o = (addr_tag_ff == cache_tag_read.tag[DCACHE_TAG_BITS-1:0]) && cache_tag_read.valid; assign cache_evict_req_o = cache_tag_read.dirty[0]; // & cache_tag_read.valid; assign dcache2mem_addr_o = dcache2mem_addr; assign dcache2mem_data_o = cache_line_read; -assign dcache2lsummu_data_o = dcache2lsummu_data_next; +assign dcache2stb_data_o = dcache2stb_data_next; endmodule diff --git a/rtl/memory/wb_dcache/wb_dcache_top.sv b/rtl/memory/wb_dcache/wb_dcache_top.sv index 6f6e9eac..53d93f99 100644 --- a/rtl/memory/wb_dcache/wb_dcache_top.sv +++ b/rtl/memory/wb_dcache/wb_dcache_top.sv @@ -24,8 +24,8 @@ module wb_dcache_top ( input wire stb2dcache_empty, // LSU/MMU to data cache interface - input wire type_lsummu2dcache_s lsummu2dcache_i, - output type_dcache2lsummu_s dcache2lsummu_o, + input wire type_stb2dcache_s stb2dcache_i, + output type_dcache2stb_s dcache2stb_o, // Data cache to data memory interface input wire type_mem2dcache_s mem2dcache_i, @@ -41,15 +41,15 @@ logic cache_line_clean; logic cache_wrb_req; logic [DCACHE_IDX_BITS-1:0] evict_index; -type_lsummu2dcache_s lsummu2dcache; -type_dcache2lsummu_s dcache2lsummu; +type_stb2dcache_s stb2dcache; +type_dcache2stb_s dcache2stb; type_mem2dcache_s mem2dcache; type_dcache2mem_s dcache2mem; logic top_dcache_flush; -assign lsummu2dcache = lsummu2dcache_i; +assign stb2dcache = stb2dcache_i; assign mem2dcache = mem2dcache_i; assign top_dcache_flush = stb2dcache_empty && dcache_flush_i; @@ -68,12 +68,12 @@ wb_dcache_controller wb_dcache_controller_module( .cache_wrb_req_o (cache_wrb_req), // LSU/MMU <---> data cache signals - .lsummu2dcache_req_i (lsummu2dcache.req), - .lsummu2dcache_wr_i (lsummu2dcache.w_en), - .dcache2lsummu_ack_o (dcache2lsummu.ack), + .stb2dcache_req_i (stb2dcache.req), + .stb2dcache_wr_i (stb2dcache.w_en), + .dcache2stb_ack_o (dcache2stb.ack), .dcache_flush_i (top_dcache_flush), .dcache_kill_i (dcache_kill_i), -// .dcache_flush_ack_o (dcache2lsummu.flush_ack), +// .dcache_flush_ack_o (dcache2stb.flush_ack), // Data memory <---> data cache signals .mem2dcache_ack_i (mem2dcache.ack), @@ -98,11 +98,11 @@ wb_dcache_datapath wb_dcache_datapath_module( // LSU/MMU <---> data cache signals .dcache_flush_i (top_dcache_flush), - .lsummu2dcache_req_i (lsummu2dcache.req), - .lsummu2dcache_addr_i (lsummu2dcache.addr), - .lsummu2dcache_wdata_i (lsummu2dcache.w_data), - .sel_byte_i (lsummu2dcache.sel_byte), - .dcache2lsummu_data_o (dcache2lsummu.r_data), + .stb2dcache_req_i (stb2dcache.req), + .stb2dcache_addr_i (stb2dcache.addr), + .stb2dcache_wdata_i (stb2dcache.w_data), + .sel_byte_i (stb2dcache.sel_byte), + .dcache2stb_data_o (dcache2stb.r_data), // Data memory <---> data cache signals .mem2dcache_data_i (mem2dcache.r_data), @@ -111,7 +111,7 @@ wb_dcache_datapath wb_dcache_datapath_module( ); -assign dcache2lsummu_o = dcache2lsummu; +assign dcache2stb_o = dcache2stb; assign dcache2mem_o = dcache2mem; From 6b91b8caa1190c7f1f7f0790b842eeb5871da875 Mon Sep 17 00:00:00 2001 From: Fazail Date: Wed, 27 Nov 2024 08:38:01 +0500 Subject: [PATCH 5/8] updates for vsim simulation --- rtl/core/pipeline/fetch.sv | 10 +++++----- rtl/memory/store-buffer/store_buffer_datapath.sv | 12 ++++++------ rtl/memory/store-buffer/store_buffer_top.sv | 8 ++++---- 3 files changed, 15 insertions(+), 15 deletions(-) diff --git a/rtl/core/pipeline/fetch.sv b/rtl/core/pipeline/fetch.sv index 9e95768d..743a82a1 100644 --- a/rtl/core/pipeline/fetch.sv +++ b/rtl/core/pipeline/fetch.sv @@ -71,6 +71,11 @@ logic [`XLEN-1:0] instr_word; logic if_stall; logic pc_misaligned; +//////////////////////////////////////////////////////////////// +logic [`XLEN-1:0] pc_new_jal; +logic [`XLEN-1:0] jal_imm; +logic is_jal; + assign icache2if = icache2if_i; assign mmu2if = mmu2if_i; @@ -119,11 +124,6 @@ always_comb begin endcase end -//////////////////////////////////////////////////////////////// -logic [`XLEN-1:0] pc_new_jal; -logic [`XLEN-1:0] jal_imm; -logic is_jal; - assign jal_imm = {{12{instr_word[31]}}, instr_word[19:12], instr_word[20], instr_word[30:21], 1'b0}; //assign pc_new_jal = pc_ff + jal_imm; diff --git a/rtl/memory/store-buffer/store_buffer_datapath.sv b/rtl/memory/store-buffer/store_buffer_datapath.sv index f4544600..4248b260 100644 --- a/rtl/memory/store-buffer/store_buffer_datapath.sv +++ b/rtl/memory/store-buffer/store_buffer_datapath.sv @@ -8,7 +8,7 @@ // Date: 15.11.2024 `ifndef VERILATOR -`include "../defines/cache_defs.svh" +`include "../../defines/cache_defs.svh" `else `include "cache_defs.svh" `endif @@ -49,13 +49,13 @@ module store_buffer_datapath ( logic [$clog2(BLEN)-1:0] wr_index, wr_index_comp, wr_index_add; // counter for write operaitons - assign wr_index_add = (wr_index == BLEN-1) ? '0: (wr_index + 1); + //assign wr_index_add = (wr_index == BLEN-1) ? '0: (wr_index + 1); always_ff @(posedge clk or negedge rst_n) begin if (!rst_n) begin wr_index <= 0; end else if (wr_en) begin - wr_index <= wr_index_add; + wr_index <= (wr_index + 1); end else begin wr_index <= wr_index; @@ -63,13 +63,13 @@ module store_buffer_datapath ( end // counter for read operaitons - assign rd_index_add = (rd_index == BLEN-1) ? '0: (rd_index + 1); + //assign rd_index_add = (rd_index == BLEN-1) ? '0: (rd_index + 1); always_ff @(posedge clk or negedge rst_n) begin if (!rst_n) begin rd_index <= 0; end else if (rd_en) begin - rd_index <= rd_index_add; + rd_index <= (rd_index + 1); end else begin rd_index <= rd_index; @@ -110,7 +110,7 @@ module store_buffer_datapath ( assign wr_index_comp = (wr_index == BLEN-1) ? '0: wr_index + 1; - assign stb_full = (rd_index == (wr_index_comp)) ? 1'b1 : 1'b0; + assign stb_full = (rd_index == wr_index_comp) ? 1'b1 : 1'b0; assign stb_empty = (rd_index == wr_index) ? 1'b1 : 1'b0; endmodule diff --git a/rtl/memory/store-buffer/store_buffer_top.sv b/rtl/memory/store-buffer/store_buffer_top.sv index 1fd1f0bd..8a7b0d6b 100644 --- a/rtl/memory/store-buffer/store_buffer_top.sv +++ b/rtl/memory/store-buffer/store_buffer_top.sv @@ -8,7 +8,7 @@ // Date: 15.11.2024 `ifndef VERILATOR -`include "../defines/cache_defs.svh" +`include "../../defines/cache_defs.svh" `else `include "cache_defs.svh" `endif @@ -106,7 +106,7 @@ module store_buffer_top ( end 1'b0: begin stb2lsummu_ack = stb_ack; - stb2lsummu_rdata = '0; + stb2lsummu_rdata = '0; stb2dcache_addr = stb_addr; stb2dcache_wdata = stb_wdata; @@ -118,7 +118,7 @@ module store_buffer_top ( end default: begin stb2lsummu_ack = stb_ack; - stb2lsummu_rdata = '0; + stb2lsummu_rdata = '0; stb2dcache_addr = stb_addr; stb2dcache_wdata = stb_wdata; @@ -130,7 +130,7 @@ module store_buffer_top ( end endcase end - + /* =========================================== Store Buffer Datapath ============================================= */ store_buffer_datapath u_store_buffer ( .clk (clk), From 68ba3eefb8bd9c3b44b8b0a17d14b75ea77035c7 Mon Sep 17 00:00:00 2001 From: Fazail Date: Thu, 28 Nov 2024 14:34:45 +0500 Subject: [PATCH 6/8] update for simulation --- rtl/defines/pcore_config_defs.svh | 4 ++-- rtl/memory/main_mem.sv | 3 ++- rtl/memory/store-buffer/lsu_stb_controller.sv | 15 +++++++++------ 3 files changed, 13 insertions(+), 9 deletions(-) diff --git a/rtl/defines/pcore_config_defs.svh b/rtl/defines/pcore_config_defs.svh index c4c7e73d..bc9eced4 100644 --- a/rtl/defines/pcore_config_defs.svh +++ b/rtl/defines/pcore_config_defs.svh @@ -13,7 +13,7 @@ `ifndef COMPLIANCE //`define DRAM 1 -//`define RTL_SIMULATION 1 +`define RTL_SIMULATION 1 `endif `define ICACHE_SETS 512 @@ -42,7 +42,7 @@ `define BMEM_ADDR_MATCH 20'h00001 // Boot mode selection -`define LINUX_BOOT 1 +//`define LINUX_BOOT 1 `ifndef COMPLIANCE `ifdef LINUX_BOOT diff --git a/rtl/memory/main_mem.sv b/rtl/memory/main_mem.sv index f94c1d4b..5482c12c 100644 --- a/rtl/memory/main_mem.sv +++ b/rtl/memory/main_mem.sv @@ -56,7 +56,8 @@ end initial begin // Reading the contents of example imem.txt file to memory variable - $readmemh("imem.txt", dualport_memory); + // $readmemh("imem.txt", dualport_memory); + $readmemh("sdk/example-uart/build/pcore.hex", dualport_memory); end //`endif `else diff --git a/rtl/memory/store-buffer/lsu_stb_controller.sv b/rtl/memory/store-buffer/lsu_stb_controller.sv index ac9ec414..14763710 100644 --- a/rtl/memory/store-buffer/lsu_stb_controller.sv +++ b/rtl/memory/store-buffer/lsu_stb_controller.sv @@ -35,6 +35,9 @@ module lsu_stb_controller ( } state_t; state_t current_state, next_state; + logic st_req; + + assign st_req = dmem_sel_i & lsummu2stb_w_en & lsummu2stb_req; // State transition logic (sequential) always_ff @(posedge clk or negedge rst_n) begin @@ -53,13 +56,13 @@ module lsu_stb_controller ( case (current_state) SB_IDLE: begin - if (dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req && !stb_full) begin + if (st_req & !stb_full) begin wr_en = 1'b1; // Enable write to buffer stb_stall = 1'b0; stb_ack = 1'b0; next_state = SB_WRITE; end - else if (dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req && stb_full) begin + else if (st_req & stb_full) begin stb_stall = 1'b1; wr_en = 1'b0; stb_ack = 1'b0; @@ -74,12 +77,12 @@ module lsu_stb_controller ( SB_WRITE: begin stb_ack = 1'b1; - if (dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req && !stb_full)begin + if (st_req & !stb_full)begin wr_en = 1'b1; // Enable write to buffer stb_stall = 1'b0; next_state = SB_WRITE; end - else if (dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req && stb_full)begin + else if (st_req & stb_full)begin wr_en = 1'b0; stb_stall = 1'b1; next_state = SB_FULL; @@ -98,13 +101,13 @@ module lsu_stb_controller ( SB_FULL: begin stb_stall = 1'b1; // Stall signal if buffer is stb_full - if (dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req && !stb_full) begin + if (st_req & !stb_full) begin wr_en = 1'b1; stb_stall = 1'b0; stb_ack = 1'b0; next_state = SB_WRITE; // Go to idle once buffer is not stb_full end - else if(dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req && stb_full) begin + else if(st_req & stb_full) begin wr_en = 1'b0; stb_ack = 1'b0; next_state = SB_FULL; From e09ca5d8f9ef05ccd568e7d92718a829e019f025 Mon Sep 17 00:00:00 2001 From: Fazail Date: Thu, 16 Jan 2025 20:24:33 +0500 Subject: [PATCH 7/8] Update-store-buffer --- rtl/defines/cache_defs.svh | 46 ------ rtl/defines/pcore_config_defs.svh | 4 +- rtl/defines/store_buffer_defs.svh | 48 ++++++ rtl/memory/main_mem.sv | 4 +- rtl/memory/mem_top.sv | 104 +++++++++++- rtl/memory/store-buffer/lsu_stb_controller.sv | 129 +++++++-------- .../store-buffer/stb_cache_controller.sv | 21 +-- .../store-buffer/store_buffer_datapath.sv | 50 +++--- rtl/memory/store-buffer/store_buffer_top.sv | 153 ++++++------------ 9 files changed, 303 insertions(+), 256 deletions(-) create mode 100644 rtl/defines/store_buffer_defs.svh diff --git a/rtl/defines/cache_defs.svh b/rtl/defines/cache_defs.svh index 8bc619fb..be37afc7 100644 --- a/rtl/defines/cache_defs.svh +++ b/rtl/defines/cache_defs.svh @@ -79,9 +79,6 @@ parameter DCACHE_TAG_LSB = DCACHE_ADDR_WIDTH - DCACHE_TAG_BITS; parameter DCACHE_MAX_IDX = DCACHE_IDX_BITS'(DCACHE_NO_OF_SETS - 1); -parameter STORE_BUFFER_WIDTH = 4; -parameter BLEN = STORE_BUFFER_WIDTH; - typedef enum logic [2:0] { DCACHE_IDLE, DCACHE_PROCESS_REQ, @@ -93,49 +90,6 @@ typedef enum logic [2:0] { DCACHE_FLUSH_DONE } type_dcache_states_e; -// Bus interface from LSU to dcache -/*typedef struct packed { - logic [DCACHE_ADDR_WIDTH-1:0] addr; - logic [DCACHE_DATA_WIDTH-1:0] w_data; - logic [3:0] sel_byte; - logic w_en; - logic req; -} type_lsummu2dcache_s; - -// Bus interface from Icache to IF -typedef struct packed { - logic [DCACHE_DATA_WIDTH-1:0] r_data; - logic ack; -} type_dcache2lsummu_s;*/ - -// Bus interface from STB to dcache -typedef struct packed { - logic [DCACHE_ADDR_WIDTH-1:0] addr; - logic [DCACHE_DATA_WIDTH-1:0] w_data; - logic [3:0] sel_byte; - logic w_en; - logic req; -} type_stb2dcache_s; - -typedef struct packed { - logic [DCACHE_DATA_WIDTH-1:0] r_data; - logic ack; -} type_dcache2stb_s; - -// Bus interface from LSU to STB -typedef struct packed { - logic [DCACHE_ADDR_WIDTH-1:0] addr; - logic [DCACHE_DATA_WIDTH-1:0] w_data; - logic [3:0] sel_byte; - logic w_en; - logic req; -} type_lsummu2stb_s; - -typedef struct packed { - logic ack; - logic [DCACHE_DATA_WIDTH-1:0] r_data; -} type_stb2lsummu_s; - typedef struct packed { logic [DCACHE_ADDR_WIDTH-1:0] addr; logic [DCACHE_LINE_WIDTH-1:0] w_data; diff --git a/rtl/defines/pcore_config_defs.svh b/rtl/defines/pcore_config_defs.svh index bc9eced4..c4c7e73d 100644 --- a/rtl/defines/pcore_config_defs.svh +++ b/rtl/defines/pcore_config_defs.svh @@ -13,7 +13,7 @@ `ifndef COMPLIANCE //`define DRAM 1 -`define RTL_SIMULATION 1 +//`define RTL_SIMULATION 1 `endif `define ICACHE_SETS 512 @@ -42,7 +42,7 @@ `define BMEM_ADDR_MATCH 20'h00001 // Boot mode selection -//`define LINUX_BOOT 1 +`define LINUX_BOOT 1 `ifndef COMPLIANCE `ifdef LINUX_BOOT diff --git a/rtl/defines/store_buffer_defs.svh b/rtl/defines/store_buffer_defs.svh new file mode 100644 index 00000000..9373ef92 --- /dev/null +++ b/rtl/defines/store_buffer_defs.svh @@ -0,0 +1,48 @@ +// Copyright 2023 University of Engineering and Technology Lahore. +// Licensed under the Apache License, Version 2.0, see LICENSE file for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Description: +// +// Author: Fazail Ali Butt, UET Lahore +// Date: 30.11.2024 + +`ifndef STORE_BUFFER_DEFS +`define STORE_BUFFER_DEFS + +`include "pcore_interface_defs.svh" +`include "mmu_defs.svh" +`include "cache_defs.svh" + +//=========================== Store Buffer related definitions ===========================// +parameter STORE_BUFFER_WIDTH = 4; +parameter BLEN = STORE_BUFFER_WIDTH; + +typedef struct packed { + logic [DCACHE_ADDR_WIDTH-1:0] addr; + logic [DCACHE_DATA_WIDTH-1:0] w_data; + logic [3:0] sel_byte; + logic w_en; + logic req; +} type_stb2dcache_s; + +typedef struct packed { + logic [DCACHE_DATA_WIDTH-1:0] r_data; + logic ack; +} type_dcache2stb_s; + +// Bus interface from LSU to STB +typedef struct packed { + logic [DCACHE_ADDR_WIDTH-1:0] addr; + logic [DCACHE_DATA_WIDTH-1:0] w_data; + logic [3:0] sel_byte; + logic w_en; + logic req; +} type_lsummu2stb_s; + +typedef struct packed { + logic ack; + logic [DCACHE_DATA_WIDTH-1:0] r_data; +} type_stb2lsummu_s; + +`endif diff --git a/rtl/memory/main_mem.sv b/rtl/memory/main_mem.sv index 5482c12c..1dbdfbfe 100644 --- a/rtl/memory/main_mem.sv +++ b/rtl/memory/main_mem.sv @@ -56,8 +56,8 @@ end initial begin // Reading the contents of example imem.txt file to memory variable - // $readmemh("imem.txt", dualport_memory); - $readmemh("sdk/example-uart/build/pcore.hex", dualport_memory); + $readmemh("imem.txt", dualport_memory); + //$readmemh("sdk/example-uart/build/pcore.hex", dualport_memory); end //`endif `else diff --git a/rtl/memory/mem_top.sv b/rtl/memory/mem_top.sv index 2c25dc1c..add00c97 100644 --- a/rtl/memory/mem_top.sv +++ b/rtl/memory/mem_top.sv @@ -13,10 +13,12 @@ `include "../defines/mmu_defs.svh" `include "../defines/cache_defs.svh" `include "../defines/ddr_defs.svh" +`include "../defines/store_buffer_defs.svh" `else `include "mmu_defs.svh" `include "cache_defs.svh" `include "ddr_defs.svh" +`include "store_buffer_defs.svh" `endif module mem_top ( @@ -89,13 +91,20 @@ logic timeout_flag; logic [5:0] timeout_next, timeout_ff; // Store Buffer related signals -type_stb2dcache_s stb2dcache; -type_dcache2stb_s dcache2stb; +type_stb2dcache_s stb2dcache, lsustb2dcache_mux; +type_dcache2stb_s dcache2stb, dcache2lsustb_mux; type_lsummu2stb_s lsummu2stb; type_stb2lsummu_s stb2lsummu; logic stb_dmem_sel_o; logic stb2dcache_empty; +logic stb_bypass; + +logic mmu2stb_sel, dbus2stb_sel, dbus_sel; +logic stb2dbus_sel, stb2mmu_sel; +logic mmu_sel; + +assign mmu_sel = ~dmem_sel & mmu2dcache.r_req & ~mmu2dcache.flush_req; // Signal assignments assign mmu2dcache = mmu2dcache_i; @@ -149,7 +158,7 @@ always_ff @(posedge clk) begin end end -always_comb begin +/*always_comb begin lsummu2stb = '0; dcache2dbus = '0; dcache2mmu = '0; @@ -214,8 +223,95 @@ dcache_kill_req = '0; default: begin end endcase +end*/ + +always_comb begin +mmu2stb_sel = '0; +dbus2stb_sel = '0; +dbus_sel = '0; +stb2dbus_sel = '0; +stb2mmu_sel = '0; + case (cache_arbiter_state_ff) + + DCACHE_ARBITER_IDLE: begin + if (dmem_sel) begin + dbus2stb_sel = 1'b1; + dbus_sel = 1'b1; + cache_arbiter_state_next = DCACHE_ARBITER_LSU; + end else if (mmu_sel) begin + mmu2stb_sel = 1'b1; + cache_arbiter_state_next = DCACHE_ARBITER_MMU; + end + end + + DCACHE_ARBITER_LSU: begin + if (stb2lsummu.ack) begin + stb2dbus_sel = 1'b1; + cache_arbiter_state_next = DCACHE_ARBITER_IDLE; + end else begin + cache_arbiter_state_next = DCACHE_ARBITER_LSU; + dbus2stb_sel = 1'b1; + dbus_sel = 1'b1; + end + + end + + DCACHE_ARBITER_MMU: begin + if (mmu2dcache.flush_req) begin + cache_arbiter_state_next = DCACHE_ARBITER_IDLE; + dcache_kill_req = 1'b1; + end else if (stb2lsummu.ack) begin + stb2mmu_sel = 1'b1; + cache_arbiter_state_next = DCACHE_ARBITER_IDLE; + end else begin + cache_arbiter_state_next = DCACHE_ARBITER_MMU; + mmu2stb_sel = 1'b1; + end + end + + default: begin + cache_arbiter_state_next = DCACHE_ARBITER_IDLE; + end + endcase end +always_comb begin // lsummu2stb + lsummu2stb = '0; + if (dbus_sel & dbus2stb_sel) begin + lsummu2stb.addr = dbus2peri.addr; + lsummu2stb.w_data = dbus2peri.w_data; + lsummu2stb.sel_byte = dbus2peri.sel_byte; + lsummu2stb.w_en = dbus2peri.w_en; + lsummu2stb.req = dbus2peri.req; + end else if (mmu2stb_sel) begin + lsummu2stb.addr = mmu2dcache.paddr; + lsummu2stb.w_data = '0; + lsummu2stb.sel_byte = '0; + lsummu2stb.w_en = '0; + lsummu2stb.req = 1'b1; + end +end // lsummu2stb + +always_comb begin // stb2dbus + dcache2dbus.ack = '0; + if (stb2dbus_sel) begin + dcache2dbus.r_data = stb2lsummu.r_data; + dcache2dbus.ack = 1'b1; + end +end // stb2dbus + +always_comb begin // stb2mmu + dcache2mmu = '0; + if (stb2mmu_sel) begin + dcache2mmu.r_data = stb2lsummu.r_data; + dcache2mmu.r_valid = 1'b1; + end +end // stb2mmu + +//assign stb_bypass = ((lsummu2stb.req & !lsummu2stb.w_en) | (!lsummu2stb.req & !lsummu2stb.w_en)) & stb2dcache_empty ; + +//assign dcache2lsustb_mux = (stb_bypass)? stb2lsummu : dcache2stb; + //========================== Store Buffer top module ===========================// store_buffer_top store_buffer_top_module ( .clk (clk), @@ -237,6 +333,8 @@ store_buffer_top store_buffer_top_module ( .dcache2stb_i (dcache2stb) ); +//assign lsustb2dcache_mux = (stb_bypass)? stb2dcache : lsummu2stb; + //========================== Data cache top module ===========================// wb_dcache_top wb_dcache_top_module( .clk (clk), diff --git a/rtl/memory/store-buffer/lsu_stb_controller.sv b/rtl/memory/store-buffer/lsu_stb_controller.sv index 14763710..fcf9db23 100644 --- a/rtl/memory/store-buffer/lsu_stb_controller.sv +++ b/rtl/memory/store-buffer/lsu_stb_controller.sv @@ -18,110 +18,113 @@ module lsu_stb_controller ( // store_buffer_datapath --> lsu_stb_controller input logic stb_full, // Store buffer stb_full flag - input logic stb_empty, // store buffer stb_empty flag // lsu_stb_controller --> LSU - output logic stb_ack, // stb_acknowledgement signal - output logic stb_stall, // Stall signal if buffer is stb_full + output logic stb_ack, // stb_acknowledgement signal // lsu_stb_controller --> store_buffer_datapath - output logic wr_en // Store buffer write enable + output logic wr_en // Store buffer write enable ); typedef enum logic [1:0] { SB_IDLE = 2'b00, SB_WRITE = 2'b01, - SB_FULL = 2'b10 + SB_FULL = 2'b10, + SB_BYPASS = 2'b11 } state_t; state_t current_state, next_state; - logic st_req; + logic full_ff; - assign st_req = dmem_sel_i & lsummu2stb_w_en & lsummu2stb_req; - - // State transition logic (sequential) + //State transition logic (sequential) always_ff @(posedge clk or negedge rst_n) begin - if (!rst_n) + if (!rst_n) begin current_state <= SB_IDLE; - else + full_ff <= '0; + end else begin current_state <= next_state; + full_ff <= stb_full; + end end // Next state logic (combinational) always_comb begin // Default values - wr_en = 1'b0; - stb_stall = 1'b0; + wr_en = 1'b0; stb_ack = 1'b0; - + case (current_state) SB_IDLE: begin - if (st_req & !stb_full) begin - wr_en = 1'b1; // Enable write to buffer - stb_stall = 1'b0; - stb_ack = 1'b0; - next_state = SB_WRITE; - end - else if (st_req & stb_full) begin - stb_stall = 1'b1; - wr_en = 1'b0; - stb_ack = 1'b0; - next_state = SB_FULL; + stb_ack = 1'b0; + if (lsummu2stb_req ) begin + if (lsummu2stb_w_en) begin + if (full_ff) begin + wr_en = 1'b0; + next_state = SB_FULL; + end else begin + wr_en = 1'b1; + next_state = SB_WRITE; + end + end else begin + wr_en = 1'b0; + next_state = SB_IDLE; + end end else begin - stb_stall = 1'b0; wr_en = 1'b0; - stb_ack = 1'b0; next_state = SB_IDLE; end end SB_WRITE: begin stb_ack = 1'b1; - if (st_req & !stb_full)begin - wr_en = 1'b1; // Enable write to buffer - stb_stall = 1'b0; - next_state = SB_WRITE; - end - else if (st_req & stb_full)begin - wr_en = 1'b0; - stb_stall = 1'b1; - next_state = SB_FULL; - end - else if (!stb_empty) begin - if (dmem_sel_i && lsummu2stb_w_en && lsummu2stb_req) begin - wr_en = 1'b1; - next_state = SB_WRITE; // Transition to stb_full state if buffer is stb_full - end - else begin - wr_en = 1'b0; - next_state = SB_IDLE; + if (lsummu2stb_req) begin + if (lsummu2stb_w_en) begin + if (full_ff) begin + wr_en = 1'b0; + next_state = SB_FULL; + end else begin + wr_en = 1'b1; + next_state = SB_WRITE; + end + end else begin + wr_en = 1'b0; + next_state = SB_IDLE; end - end + end else begin + wr_en = 1'b0; + next_state = SB_IDLE; + end end SB_FULL: begin - stb_stall = 1'b1; // Stall signal if buffer is stb_full - if (st_req & !stb_full) begin - wr_en = 1'b1; - stb_stall = 1'b0; - stb_ack = 1'b0; - next_state = SB_WRITE; // Go to idle once buffer is not stb_full - end - else if(st_req & stb_full) begin - wr_en = 1'b0; - stb_ack = 1'b0; - next_state = SB_FULL; - end - else begin + stb_ack = 1'b0; + if (lsummu2stb_req) begin + if (lsummu2stb_w_en) begin + if (full_ff) begin + wr_en = 1'b0; + next_state = SB_FULL; // Go to idle once buffer is not stb_full + end else begin + wr_en = 1'b1; + next_state = SB_WRITE; + end + end else begin + wr_en = 1'b0; + next_state = SB_IDLE; + end + end else begin wr_en = 1'b0; - stb_stall = 1'b0; - stb_ack = 1'b0; next_state = SB_IDLE; end end - - default: next_state = SB_IDLE; + default: begin + next_state = SB_IDLE; + end endcase + + if (~dmem_sel_i) begin + next_state = SB_IDLE; + end + end endmodule diff --git a/rtl/memory/store-buffer/stb_cache_controller.sv b/rtl/memory/store-buffer/stb_cache_controller.sv index dc11d047..a690dcde 100644 --- a/rtl/memory/store-buffer/stb_cache_controller.sv +++ b/rtl/memory/store-buffer/stb_cache_controller.sv @@ -12,7 +12,6 @@ module stb_cache_controller ( input logic rst_n, // store_buffer_datapath --> stb_cache_controller - input logic stb_full, // Store buffer full flag input logic stb_empty, // Store buffer empty flag // dcache --> stb_cache_controller @@ -28,19 +27,24 @@ module stb_cache_controller ( output logic dm_sel ); - typedef enum logic [1:0] { - IDLE = 2'b00, - SB_CACHE_WRITE = 2'b01 + typedef enum logic [1:0]{ + IDLE = '0, + SB_CACHE_WRITE = 1, + SB_READ = 2 } state_t; state_t current_state, next_state; + logic empty_ff; // State transition logic (sequential) always_ff @(posedge clk or negedge rst_n) begin - if (!rst_n) + if (!rst_n) begin current_state <= IDLE; - else + empty_ff <= '0; + end else begin current_state <= next_state; + empty_ff <= stb_empty; + end end // Next state logic (combinational) @@ -52,11 +56,10 @@ module stb_cache_controller ( stb_w_en = 1'b0; rd_en = 1'b0; dm_sel = 1'b0; - next_state = current_state; case (current_state) IDLE: begin - if (!stb_empty || stb_full) begin + if (!stb_empty) begin stb_req = 1'b1; // Request cache write rd_sel = 1'b1; // Read selection for store buffer stb_w_en = 1'b1; @@ -64,7 +67,7 @@ module stb_cache_controller ( rd_en = 1'b0; next_state = SB_CACHE_WRITE; end - else if(stb_empty) begin + else begin rd_sel = 1'b0; stb_req = 1'b0; stb_w_en = 1'b0; diff --git a/rtl/memory/store-buffer/store_buffer_datapath.sv b/rtl/memory/store-buffer/store_buffer_datapath.sv index 4248b260..7a195df6 100644 --- a/rtl/memory/store-buffer/store_buffer_datapath.sv +++ b/rtl/memory/store-buffer/store_buffer_datapath.sv @@ -8,9 +8,9 @@ // Date: 15.11.2024 `ifndef VERILATOR -`include "../../defines/cache_defs.svh" +`include "../../defines/store_buffer_defs.svh" `else -`include "cache_defs.svh" +`include "store_buffer_defs.svh" `endif module store_buffer_datapath ( @@ -21,7 +21,9 @@ module store_buffer_datapath ( input logic [DCACHE_ADDR_WIDTH-1:0] lsummu2stb_addr, // Address input from LSU/MMU input logic [DCACHE_DATA_WIDTH-1:0] lsummu2stb_wdata, // Data input from LSU/MMU input logic [3:0] lsummu2stb_sel_byte, // Byte selection input from LSU/MMU - + //input logic stb_write, + //input logic stb_request, + // lsu_stb_controller --> store_buffer_datapath input logic wr_en, // Write enable signal @@ -33,7 +35,6 @@ module store_buffer_datapath ( output logic [DCACHE_ADDR_WIDTH-1:0] stb_addr, // Address output to Cache output logic [DCACHE_DATA_WIDTH-1:0] stb_wdata, // Data output to Cache output logic [3:0] stb_sel_byte, // Byte selection output to Cache - // store_buffer_datapath --> store buffer controllers output logic stb_full, // Full signal output logic stb_empty // Empty signal @@ -43,27 +44,24 @@ module store_buffer_datapath ( logic [DCACHE_ADDR_WIDTH-1:0] addr_buf [BLEN-1:0]; logic [DCACHE_DATA_WIDTH-1:0] data_buf [BLEN-1:0]; logic [3:0] sel_byte_buf [BLEN-1:0]; - + // Buffer Counter (to track read and write index) - logic [$clog2(BLEN)-1:0] rd_index, rd_index_add; - logic [$clog2(BLEN)-1:0] wr_index, wr_index_comp, wr_index_add; + logic [$clog2(BLEN)-1:0] rd_index; + logic [$clog2(BLEN)-1:0] wr_index, wr_index_comp; // counter for write operaitons - //assign wr_index_add = (wr_index == BLEN-1) ? '0: (wr_index + 1); always_ff @(posedge clk or negedge rst_n) begin if (!rst_n) begin wr_index <= 0; end else if (wr_en) begin wr_index <= (wr_index + 1); - end - else begin + end else begin wr_index <= wr_index; end end // counter for read operaitons - //assign rd_index_add = (rd_index == BLEN-1) ? '0: (rd_index + 1); always_ff @(posedge clk or negedge rst_n) begin if (!rst_n) begin rd_index <= 0; @@ -79,20 +77,16 @@ module store_buffer_datapath ( // Write/Read logic always_ff @(posedge clk or negedge rst_n) begin if (!rst_n) begin - addr_buf <= addr_buf ; - data_buf <= data_buf ; - sel_byte_buf <= sel_byte_buf; - end - else if (wr_en) begin - // Write new values to buffer at wr_index - addr_buf [wr_index] <= lsummu2stb_addr; - data_buf [wr_index] <= lsummu2stb_wdata; - sel_byte_buf [wr_index] <= lsummu2stb_sel_byte; - end - else begin - addr_buf [rd_index] <= addr_buf [rd_index]; - data_buf [rd_index] <= data_buf [rd_index]; - sel_byte_buf [rd_index] <= sel_byte_buf [rd_index]; + addr_buf [wr_index] <= addr_buf [wr_index]; + data_buf [wr_index] <= data_buf [wr_index]; + sel_byte_buf [wr_index] <= sel_byte_buf [wr_index]; + end else begin + if (wr_en) begin + // Write new values to buffer at wr_index + addr_buf [wr_index] <= lsummu2stb_addr; //addr_ff; + data_buf [wr_index] <= lsummu2stb_wdata; //data_ff; + sel_byte_buf [wr_index] <= lsummu2stb_sel_byte; //sel_byte_ff; + end end end @@ -110,7 +104,9 @@ module store_buffer_datapath ( assign wr_index_comp = (wr_index == BLEN-1) ? '0: wr_index + 1; - assign stb_full = (rd_index == wr_index_comp) ? 1'b1 : 1'b0; - assign stb_empty = (rd_index == wr_index) ? 1'b1 : 1'b0; + assign stb_full = (wr_index_comp == rd_index) ? 1'b1 : 1'b0; + assign stb_empty = (wr_index == rd_index) ? 1'b1 : 1'b0; + //assign stb_empty = 1; endmodule + diff --git a/rtl/memory/store-buffer/store_buffer_top.sv b/rtl/memory/store-buffer/store_buffer_top.sv index 8a7b0d6b..e45f54b7 100644 --- a/rtl/memory/store-buffer/store_buffer_top.sv +++ b/rtl/memory/store-buffer/store_buffer_top.sv @@ -8,9 +8,9 @@ // Date: 15.11.2024 `ifndef VERILATOR -`include "../../defines/cache_defs.svh" +`include "../../defines/store_buffer_defs.svh" `else -`include "cache_defs.svh" +`include "store_buffer_defs.svh" `endif module store_buffer_top ( @@ -20,7 +20,7 @@ module store_buffer_top ( // LSU --> store_buffer_top input wire type_lsummu2stb_s lsummu2stb_i, input logic dmem_sel_i, // Data memory select from LSU - + // store_buffer_top --> LSU output type_stb2lsummu_s stb2lsummu_o, @@ -34,38 +34,15 @@ module store_buffer_top ( input wire type_dcache2stb_s dcache2stb_i ); -// store_buffer_top --> dcache Signals - logic [DCACHE_ADDR_WIDTH-1:0] stb2dcache_addr; - logic [DCACHE_DATA_WIDTH-1:0] stb2dcache_wdata; - logic [3:0] stb2dcache_sel_byte; - logic stb2dcache_w_en; - logic stb2dcache_req; - -// dcache --> store buffer top Signals - logic [DCACHE_DATA_WIDTH-1:0] dcache2stb_rdata; - logic dcache2stb_ack; - -// lsummu --> stb (store buffer) Signals - logic [DCACHE_ADDR_WIDTH-1:0] lsummu2stb_addr; - logic [DCACHE_DATA_WIDTH-1:0] lsummu2stb_wdata; - logic [3:0] lsummu2stb_sel_byte; - logic lsummu2stb_w_en; - logic lsummu2stb_req; - -// stb (store buffer) --> lsummu Signals - logic stb2lsummu_ack; - logic [DCACHE_DATA_WIDTH-1:0] stb2lsummu_rdata; - // Local Signals - logic wr_en; // Store Buffer Write Enable (from LSU controller) + logic wr_en, wr_ff; // Store Buffer Write Enable (from LSU controller) logic rd_en; // Store Buffer Read Enable (from Cache controller) logic stb_full; // Store Buffer full signal - logic stb_empty; // Store Buffer empty signal + logic stb_empty, empty_ff; // Store Buffer empty signal logic rd_sel; // selection for read mux logic stb_bypass; // Buffer Bypass signal - logic stb_stall; // Buffer Stall signal - logic stb_ack; + logic stb_ack, stb_acknowledge; logic [DCACHE_ADDR_WIDTH-1:0] stb_addr; logic [DCACHE_DATA_WIDTH-1:0] stb_wdata; @@ -74,72 +51,29 @@ module store_buffer_top ( logic stb_w_en; logic dm_sel; -/* =========================================== Input signals ===================================================== */ - // lsummu --> stb (store buffer) - assign lsummu2stb_addr = lsummu2stb_i.addr; - assign lsummu2stb_wdata = lsummu2stb_i.w_data; - assign lsummu2stb_sel_byte = lsummu2stb_i.sel_byte; - assign lsummu2stb_w_en = lsummu2stb_i.w_en; - assign lsummu2stb_req = lsummu2stb_i.req; - - // dcache --> store_buffer_top - assign dcache2stb_ack = dcache2stb_i.ack; - assign dcache2stb_rdata = dcache2stb_i.r_data; - /* =========================================== Bypassing Store buffer for Load Instructions ====================== */ // Store Buffer bypass for load instructions - assign stb_bypass = ((lsummu2stb_req & !lsummu2stb_w_en) | (!lsummu2stb_req & !lsummu2stb_w_en)) & stb_empty; - - always_comb begin - case (stb_bypass) - 1'b1: begin - stb2lsummu_ack = dcache2stb_ack; - stb2lsummu_rdata = dcache2stb_rdata; - - stb2dcache_addr = lsummu2stb_addr; - stb2dcache_wdata = lsummu2stb_wdata; - stb2dcache_sel_byte = lsummu2stb_sel_byte; - stb2dcache_req = lsummu2stb_req; - stb2dcache_w_en = lsummu2stb_w_en; - - dmem_sel_o = dmem_sel_i; - end - 1'b0: begin - stb2lsummu_ack = stb_ack; - stb2lsummu_rdata = '0; - - stb2dcache_addr = stb_addr; - stb2dcache_wdata = stb_wdata; - stb2dcache_sel_byte = stb_sel_byte; - stb2dcache_req = stb_req; - stb2dcache_w_en = stb_w_en; - - dmem_sel_o = dm_sel; - end - default: begin - stb2lsummu_ack = stb_ack; - stb2lsummu_rdata = '0; - - stb2dcache_addr = stb_addr; - stb2dcache_wdata = stb_wdata; - stb2dcache_sel_byte = stb_sel_byte; - stb2dcache_req = stb_req; - stb2dcache_w_en = stb_w_en; - - dmem_sel_o = dm_sel; - end - endcase + always_ff @(posedge clk or negedge rst_n ) begin : blockName + if (!rst_n)begin + empty_ff <= '0; + wr_ff <= '0; + end else begin + empty_ff <= stb_empty; + wr_ff <= lsummu2stb_i.w_en; + end end + assign stb_bypass = ((lsummu2stb_i.req & !wr_ff) | (!lsummu2stb_i.req & !wr_ff)) & empty_ff; + /* =========================================== Store Buffer Datapath ============================================= */ store_buffer_datapath u_store_buffer ( .clk (clk), .rst_n (rst_n), // LSU --> store_buffer_datapath - .lsummu2stb_addr (lsummu2stb_addr), - .lsummu2stb_wdata (lsummu2stb_wdata), - .lsummu2stb_sel_byte (lsummu2stb_sel_byte), + .lsummu2stb_addr (lsummu2stb_i.addr), + .lsummu2stb_wdata (lsummu2stb_i.w_data), + .lsummu2stb_sel_byte (lsummu2stb_i.sel_byte), // lsu_stb_controller --> store_buffer_datapath .wr_en (wr_en), @@ -164,17 +98,15 @@ module store_buffer_top ( .rst_n (rst_n), // LSU --> lsu_stb_controller - .lsummu2stb_w_en (lsummu2stb_w_en), - .lsummu2stb_req (lsummu2stb_req), + .lsummu2stb_w_en (lsummu2stb_i.w_en), + .lsummu2stb_req (lsummu2stb_i.req), .dmem_sel_i (dmem_sel_i), // store_buffer_datapath --> lsu_stb_controller - .stb_full (stb_full), - .stb_empty (stb_empty), + .stb_full (stb_full), // lsu_stb_controller --> LSU .stb_ack (stb_ack), - .stb_stall (stb_stall), // lsu_stb_controller --> store_buffer_datapath .wr_en (wr_en) @@ -186,11 +118,10 @@ module store_buffer_top ( .rst_n (rst_n), // store_buffer_datapath --> stb_cache_controller - .stb_full (stb_full), .stb_empty (stb_empty), // dcache --> stb_cache_controller - .dcache2stb_ack (dcache2stb_ack), + .dcache2stb_ack (dcache2stb_i.ack), // stb_cache_controller --> store_buffer_datapath .rd_en (rd_en), @@ -203,17 +134,31 @@ module store_buffer_top ( ); /* =========================================== Output signals ==================================================== */ - assign stb2dcache_empty = stb_empty; - - // stb (store buffer) --> lsummu - assign stb2lsummu_o.ack = stb2lsummu_ack; - assign stb2lsummu_o.r_data = stb2lsummu_rdata; - - // store_buffer_top --> dcache - assign stb2dcache_o.addr = stb2dcache_addr; - assign stb2dcache_o.w_data = stb2dcache_wdata; - assign stb2dcache_o.sel_byte = stb2dcache_sel_byte; - assign stb2dcache_o.w_en = stb2dcache_w_en; - assign stb2dcache_o.req = stb2dcache_req; + assign stb2dcache_empty = empty_ff; + + always_comb begin + stb2lsummu_o.ack = stb_ack; + stb2lsummu_o.r_data = '0; + + stb2dcache_o.addr = stb_addr; + stb2dcache_o.w_data = stb_wdata; + stb2dcache_o.sel_byte = stb_sel_byte; + stb2dcache_o.req = stb_req; + stb2dcache_o.w_en = stb_w_en; + + dmem_sel_o = dm_sel; + if (stb_bypass) begin + stb2lsummu_o.ack = dcache2stb_i.ack; + stb2lsummu_o.r_data = dcache2stb_i.r_data; + + stb2dcache_o.addr = lsummu2stb_i.addr; + stb2dcache_o.w_data = lsummu2stb_i.w_data; + stb2dcache_o.sel_byte = lsummu2stb_i.sel_byte; + stb2dcache_o.req = lsummu2stb_i.req; + stb2dcache_o.w_en = lsummu2stb_i.w_en; + + dmem_sel_o = dmem_sel_i; + end + end endmodule From 72664d6161246eb2784ca2091a8c992f5c98f59a Mon Sep 17 00:00:00 2001 From: Fazail Date: Fri, 17 Jan 2025 12:30:35 +0500 Subject: [PATCH 8/8] update store buffer --- rtl/memory/mem_top.sv | 11 +-- rtl/memory/store-buffer/lsu_stb_controller.sv | 68 +++++++------------ .../store-buffer/stb_cache_controller.sv | 16 ++--- .../store-buffer/store_buffer_datapath.sv | 20 +++--- rtl/memory/store-buffer/store_buffer_top.sv | 38 ++++++----- 5 files changed, 63 insertions(+), 90 deletions(-) diff --git a/rtl/memory/mem_top.sv b/rtl/memory/mem_top.sv index add00c97..52316d72 100644 --- a/rtl/memory/mem_top.sv +++ b/rtl/memory/mem_top.sv @@ -91,14 +91,13 @@ logic timeout_flag; logic [5:0] timeout_next, timeout_ff; // Store Buffer related signals -type_stb2dcache_s stb2dcache, lsustb2dcache_mux; -type_dcache2stb_s dcache2stb, dcache2lsustb_mux; +type_stb2dcache_s stb2dcache; +type_dcache2stb_s dcache2stb; type_lsummu2stb_s lsummu2stb; type_stb2lsummu_s stb2lsummu; logic stb_dmem_sel_o; logic stb2dcache_empty; -logic stb_bypass; logic mmu2stb_sel, dbus2stb_sel, dbus_sel; logic stb2dbus_sel, stb2mmu_sel; @@ -308,10 +307,6 @@ always_comb begin // stb2mmu end end // stb2mmu -//assign stb_bypass = ((lsummu2stb.req & !lsummu2stb.w_en) | (!lsummu2stb.req & !lsummu2stb.w_en)) & stb2dcache_empty ; - -//assign dcache2lsustb_mux = (stb_bypass)? stb2lsummu : dcache2stb; - //========================== Store Buffer top module ===========================// store_buffer_top store_buffer_top_module ( .clk (clk), @@ -333,8 +328,6 @@ store_buffer_top store_buffer_top_module ( .dcache2stb_i (dcache2stb) ); -//assign lsustb2dcache_mux = (stb_bypass)? stb2dcache : lsummu2stb; - //========================== Data cache top module ===========================// wb_dcache_top wb_dcache_top_module( .clk (clk), diff --git a/rtl/memory/store-buffer/lsu_stb_controller.sv b/rtl/memory/store-buffer/lsu_stb_controller.sv index fcf9db23..9b83e71f 100644 --- a/rtl/memory/store-buffer/lsu_stb_controller.sv +++ b/rtl/memory/store-buffer/lsu_stb_controller.sv @@ -12,8 +12,7 @@ module lsu_stb_controller ( input logic rst_n, // LSU --> lsu_stb_controller - input logic lsummu2stb_w_en, // Write enable from LSU - input logic lsummu2stb_req, // Store request from LSU + input logic st_req, // store request from lsu input logic dmem_sel_i, // Input from LSU (data memory select) // store_buffer_datapath --> lsu_stb_controller @@ -29,21 +28,17 @@ module lsu_stb_controller ( typedef enum logic [1:0] { SB_IDLE = 2'b00, SB_WRITE = 2'b01, - SB_FULL = 2'b10, - SB_BYPASS = 2'b11 + SB_FULL = 2'b10 } state_t; state_t current_state, next_state; - logic full_ff; //State transition logic (sequential) always_ff @(posedge clk or negedge rst_n) begin if (!rst_n) begin current_state <= SB_IDLE; - full_ff <= '0; end else begin current_state <= next_state; - full_ff <= stb_full; end end @@ -56,65 +51,50 @@ module lsu_stb_controller ( case (current_state) SB_IDLE: begin stb_ack = 1'b0; - if (lsummu2stb_req ) begin - if (lsummu2stb_w_en) begin - if (full_ff) begin - wr_en = 1'b0; - next_state = SB_FULL; - end else begin - wr_en = 1'b1; - next_state = SB_WRITE; - end - end else begin + if (st_req) begin + if (stb_full) begin wr_en = 1'b0; - next_state = SB_IDLE; + next_state = SB_FULL; + end else begin + wr_en = 1'b1; + next_state = SB_WRITE; end end else begin wr_en = 1'b0; - next_state = SB_IDLE; + next_state = SB_IDLE; end end SB_WRITE: begin stb_ack = 1'b1; - if (lsummu2stb_req) begin - if (lsummu2stb_w_en) begin - if (full_ff) begin - wr_en = 1'b0; - next_state = SB_FULL; - end else begin - wr_en = 1'b1; - next_state = SB_WRITE; - end + if (st_req) begin + if (stb_full) begin + wr_en = 1'b0; + next_state = SB_FULL; end else begin - wr_en = 1'b0; - next_state = SB_IDLE; + wr_en = 1'b1; + next_state = SB_WRITE; end end else begin - wr_en = 1'b0; - next_state = SB_IDLE; + wr_en = 1'b0; + next_state = SB_IDLE; end end SB_FULL: begin stb_ack = 1'b0; - if (lsummu2stb_req) begin - if (lsummu2stb_w_en) begin - if (full_ff) begin - wr_en = 1'b0; - next_state = SB_FULL; // Go to idle once buffer is not stb_full - end else begin - wr_en = 1'b1; - next_state = SB_WRITE; - end - end else begin + if (st_req) begin + if (stb_full) begin wr_en = 1'b0; - next_state = SB_IDLE; + next_state = SB_FULL; + end else begin + wr_en = 1'b1; + next_state = SB_WRITE; end end else begin wr_en = 1'b0; next_state = SB_IDLE; - end + end end default: begin next_state = SB_IDLE; diff --git a/rtl/memory/store-buffer/stb_cache_controller.sv b/rtl/memory/store-buffer/stb_cache_controller.sv index a690dcde..fd840903 100644 --- a/rtl/memory/store-buffer/stb_cache_controller.sv +++ b/rtl/memory/store-buffer/stb_cache_controller.sv @@ -18,7 +18,7 @@ module stb_cache_controller ( input logic dcache2stb_ack, // Acknowledgement from cache // stb_cache_controller --> store_buffer_datapath - output logic rd_en, // enable for read counter + output logic rd_en, // enable for read counter output logic rd_sel, // Store buffer mux read selection // stb_cache_controller --> dcache @@ -27,23 +27,19 @@ module stb_cache_controller ( output logic dm_sel ); - typedef enum logic [1:0]{ - IDLE = '0, - SB_CACHE_WRITE = 1, - SB_READ = 2 + typedef enum logic { + IDLE = 1'b0, + SB_CACHE_WRITE = 1'b1 } state_t; state_t current_state, next_state; - logic empty_ff; // State transition logic (sequential) always_ff @(posedge clk or negedge rst_n) begin if (!rst_n) begin current_state <= IDLE; - empty_ff <= '0; end else begin current_state <= next_state; - empty_ff <= stb_empty; end end @@ -60,8 +56,8 @@ module stb_cache_controller ( case (current_state) IDLE: begin if (!stb_empty) begin - stb_req = 1'b1; // Request cache write - rd_sel = 1'b1; // Read selection for store buffer + stb_req = 1'b1; + rd_sel = 1'b1; stb_w_en = 1'b1; dm_sel = 1'b1; rd_en = 1'b0; diff --git a/rtl/memory/store-buffer/store_buffer_datapath.sv b/rtl/memory/store-buffer/store_buffer_datapath.sv index 7a195df6..1607feb0 100644 --- a/rtl/memory/store-buffer/store_buffer_datapath.sv +++ b/rtl/memory/store-buffer/store_buffer_datapath.sv @@ -21,20 +21,19 @@ module store_buffer_datapath ( input logic [DCACHE_ADDR_WIDTH-1:0] lsummu2stb_addr, // Address input from LSU/MMU input logic [DCACHE_DATA_WIDTH-1:0] lsummu2stb_wdata, // Data input from LSU/MMU input logic [3:0] lsummu2stb_sel_byte, // Byte selection input from LSU/MMU - //input logic stb_write, - //input logic stb_request, // lsu_stb_controller --> store_buffer_datapath - input logic wr_en, // Write enable signal + input logic wr_en, // Write enable signal // stb_cache_controller --> store_buffer_datapath - input logic rd_en, // Read enable signal + input logic rd_en, // Read enable signal input logic rd_sel, // Read Selection signal // store_buffer_datapath --> dcache - output logic [DCACHE_ADDR_WIDTH-1:0] stb_addr, // Address output to Cache - output logic [DCACHE_DATA_WIDTH-1:0] stb_wdata, // Data output to Cache - output logic [3:0] stb_sel_byte, // Byte selection output to Cache + output logic [DCACHE_ADDR_WIDTH-1:0] stb_addr, // Address output to Cache + output logic [DCACHE_DATA_WIDTH-1:0] stb_wdata, // Data output to Cache + output logic [3:0] stb_sel_byte, // Byte selection output to Cache + // store_buffer_datapath --> store buffer controllers output logic stb_full, // Full signal output logic stb_empty // Empty signal @@ -83,9 +82,9 @@ module store_buffer_datapath ( end else begin if (wr_en) begin // Write new values to buffer at wr_index - addr_buf [wr_index] <= lsummu2stb_addr; //addr_ff; - data_buf [wr_index] <= lsummu2stb_wdata; //data_ff; - sel_byte_buf [wr_index] <= lsummu2stb_sel_byte; //sel_byte_ff; + addr_buf [wr_index] <= lsummu2stb_addr; + data_buf [wr_index] <= lsummu2stb_wdata; + sel_byte_buf [wr_index] <= lsummu2stb_sel_byte; end end end @@ -106,7 +105,6 @@ module store_buffer_datapath ( assign stb_full = (wr_index_comp == rd_index) ? 1'b1 : 1'b0; assign stb_empty = (wr_index == rd_index) ? 1'b1 : 1'b0; - //assign stb_empty = 1; endmodule diff --git a/rtl/memory/store-buffer/store_buffer_top.sv b/rtl/memory/store-buffer/store_buffer_top.sv index e45f54b7..01449a4a 100644 --- a/rtl/memory/store-buffer/store_buffer_top.sv +++ b/rtl/memory/store-buffer/store_buffer_top.sv @@ -35,25 +35,30 @@ module store_buffer_top ( ); // Local Signals - logic wr_en, wr_ff; // Store Buffer Write Enable (from LSU controller) - logic rd_en; // Store Buffer Read Enable (from Cache controller) - logic stb_full; // Store Buffer full signal + logic wr_en; // Store Buffer Write Enable (from LSU controller) + logic rd_en; // Store Buffer Read Enable (from Cache controller) + logic stb_full; // Store Buffer full signal logic stb_empty, empty_ff; // Store Buffer empty signal - logic rd_sel; // selection for read mux - logic stb_bypass; // Buffer Bypass signal + logic rd_sel; // selection for read mux + logic stb_bypass; // Buffer Bypass signal - logic stb_ack, stb_acknowledge; + logic stb_ack; // store buffer acknowledgement signal for lsu - logic [DCACHE_ADDR_WIDTH-1:0] stb_addr; - logic [DCACHE_DATA_WIDTH-1:0] stb_wdata; - logic [3:0] stb_sel_byte; - logic stb_req; - logic stb_w_en; - logic dm_sel; + logic [DCACHE_ADDR_WIDTH-1:0] stb_addr; // store buffer addr to dcache + logic [DCACHE_DATA_WIDTH-1:0] stb_wdata; // store buffer wdata to dcache + logic [3:0] stb_sel_byte; // store buffer sel_byte to dcache + logic stb_req; // store buffer request to dcache + logic stb_w_en; // store buffer write enable to dcache + logic dm_sel; // store buffer dmem selection to dcache + + logic st_req; // store request + + assign st_req = lsummu2stb_i.req & lsummu2stb_i.w_en; /* =========================================== Bypassing Store buffer for Load Instructions ====================== */ // Store Buffer bypass for load instructions - always_ff @(posedge clk or negedge rst_n ) begin : blockName + logic wr_ff; + always_ff @(posedge clk or negedge rst_n ) begin if (!rst_n)begin empty_ff <= '0; wr_ff <= '0; @@ -98,10 +103,11 @@ module store_buffer_top ( .rst_n (rst_n), // LSU --> lsu_stb_controller - .lsummu2stb_w_en (lsummu2stb_i.w_en), - .lsummu2stb_req (lsummu2stb_i.req), .dmem_sel_i (dmem_sel_i), + // store buffer top --> lsu_stb_controller + .st_req (st_req), + // store_buffer_datapath --> lsu_stb_controller .stb_full (stb_full), @@ -134,7 +140,7 @@ module store_buffer_top ( ); /* =========================================== Output signals ==================================================== */ - assign stb2dcache_empty = empty_ff; + assign stb2dcache_empty = stb_empty; always_comb begin stb2lsummu_o.ack = stb_ack;