Hello!
I want make via shiedling across the edge of the board
I select the edge lines, check "include drawing lines" , select layer

and get error

details:
18:43:29: exception on via fence generation: Execution of clipper did not succeed!
18:43:29: Traceback (most recent call last):
File "C:\Users\imya-familiev\Documents\KiCad\9.0\3rdparty\plugins\com_github_easyw_kicad-rf-tools\via_fence_generator\viafence_action.py", line 596, in Run
viaPoints = generateViaFence(self.pathList, self.viaOffset, self.viaPitch)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "C:\Users\imya-familiev\Documents\KiCad\9.0\3rdparty\plugins\com_github_easyw_kicad-rf-tools\via_fence_generator\viafence.py", line 263, in generateViaFence
offsetPoly = trimFlushPolygonAtVertices(offsetPoly, leafVertexList, leafVertexAngles, 1.1*viaOffset)[0]
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "C:\Users\imya-familiev\Documents\KiCad\9.0\3rdparty\plugins\com_github_easyw_kicad-rf-tools\via_fence_generator\viafence.py", line 234, in trimFlushPolygonAtVertices
trimPolys = unionPolygons(trimPolys)
^^^^^^^^^^^^^^^^^^^^^^^^
File "C:\Users\imya-familiev\Documents\KiCad\9.0\3rdparty\plugins\com_github_easyw_kicad-rf-tools\via_fence_generator\viafence.py", line 170, in unionPolygons
return pc.Execute(pyclipper.CT_UNION, pyclipper.PFT_NONZERO)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "src\\pyclipper\\_pyclipper.pyx", line 697, in pyclipper._pyclipper.Pyclipper.Execute
pyclipper._pyclipper.ClipperException: Execution of clipper did not succeed!
If i select any object inside pcb edge al work as expected (vias surround drawing line)
But in this case i expect that only vias inside edge rectangle will be generated, but it not.
i think it will be very usefull option to make shielding in this way. thanks
Hello!
I want make via shiedling across the edge of the board
I select the edge lines, check "include drawing lines" , select layer
and get error
details:
If i select any object inside pcb edge al work as expected (vias surround drawing line)
But in this case i expect that only vias inside edge rectangle will be generated, but it not.
i think it will be very usefull option to make shielding in this way. thanks