The SV Testbench in charge of dCache verification is limited by:
- a driver issuing AW & W synchronously
- dCache accepting only AW & W channels synchronous, not fully independent.
It wasn't a problem till now because memfy module supports correctly AXI channel independency requirement, it's just a driver issue. However, the new bypass circuit in dCache revealed again the problem because in this situation channels are independent. It's been patched with a AXI pipeline stage absorbing the outstanding requests and ensuring the driver is not lost in his transaction flow but this is a temporary solution.
Ultimately:
- dCache should be designed better and accept AW and W separately
- pusher stage
- memory controller
- tb driver should also support this required independence and generate random back pressure for both AW and W channels
The SV Testbench in charge of dCache verification is limited by:
It wasn't a problem till now because memfy module supports correctly AXI channel independency requirement, it's just a driver issue. However, the new bypass circuit in dCache revealed again the problem because in this situation channels are independent. It's been patched with a AXI pipeline stage absorbing the outstanding requests and ensuring the driver is not lost in his transaction flow but this is a temporary solution.
Ultimately: