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Hi. |
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@nooberfsh Thanks for your dump. Unfortunately I'm finding no hint in this register. Can you show me how your 9950X memory controller is decoded with: |
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@cyring Sure |
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Hello, # UMC::BaseAddr
## Channel 0
./zencli smu 0x50000
./zencli smu 0x50004
./zencli smu 0x50008
./zencli smu 0x5000c
## Channel 1
./zencli smu 0x150000
./zencli smu 0x150004
./zencli smu 0x150008
./zencli smu 0x15000c
# UMC::BaseAddrSec
## Channel 0
./zencli smu 0x50010
./zencli smu 0x50014
./zencli smu 0x50018
./zencli smu 0x5001c
## Channel 1
./zencli smu 0x150010
./zencli smu 0x150014
./zencli smu 0x150018
./zencli smu 0x15001c
# UMC::AddrMask
## Channel 0
./zencli smu 0x50020
./zencli smu 0x50024
./zencli smu 0x50028
./zencli smu 0x5002c
## Channel 1
./zencli smu 0x150020
./zencli smu 0x150024
./zencli smu 0x150028
./zencli smu 0x15002c
# UMC::AddrMaskSec
## Channel 0
./zencli smu 0x50030
./zencli smu 0x50034
./zencli smu 0x50038
./zencli smu 0x5003c
## Channel 1
./zencli smu 0x150030
./zencli smu 0x150034
./zencli smu 0x150038
./zencli smu 0x15003cAnd also # UMC::AddrCfg
## Channel 0
./zencli smu 0x50040
./zencli smu 0x50044
./zencli smu 0x50048
./zencli smu 0x5004c
## Channel 1
./zencli smu 0x150040
./zencli smu 0x150044
./zencli smu 0x150048
./zencli smu 0x15004c
# UMC::DimmCfg
## Channel 0
./zencli smu 0x50090
./zencli smu 0x50094
## Channel 1
./zencli smu 0x150090
./zencli smu 0x150094 |
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Sure, but I can't access my PC until this weekend, I'll post the result as soon as possible. |
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Will you also please have a try to the branch develop_amd_ext_apic_id and post the output of |
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It seems the branch doesn't exist |
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Everything has been merged, you can now pull latest commits from master. |
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@nooberfsh Thank you for your answers.
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Sure |
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Thank you. Can you switch to the Make sure to unload previous version. I would like to see the output of: |
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@nooberfsh Thanks.
Fyi, your output is stored in Wiki/CPU support/Ryzen 9 9950X/MPG X670E CARBON WIFI |
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Thanks for making a such great project. |
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Although register is accessible and (Edit) As a fix, I'm reserving to Zen-2 the aggregation in new commit 09a1d36 which should print as |
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This is so subtil ! 16 GB Binary case shows echo "ibase=16;obase=2;DFE" | bc
110111111110
echo "ibase=16;obase=2;BFE" | bc
101111111110A flip happens in bits 9 and 10 and specs say The difference between Presume a new decoder where Also Now if we're adding the two (dual channels) matrices we are getting Thus two DIMMs of |
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If you still have your Source code at https://github.com/cyring/Tips/blob/master/C/zencli.c
cc zencli.c -o zencli -D HSMP_CMD_REG=0x3b10934
./zencli umcThank you for your help As a example, here it's the result for a binary DIMM size ./zencli umc
Data Fabric: scanning UMC @ BAR[0x00050000] : 0 1 2 3 4 5 6 7 8 9 10 11
for 2 detected channels without a shared mask
CHA[0] CHIP[0:0] @ 0x00050000[0x00000001] Enable, 1 DPC
CHA[0] MASK[0:0] @ 0x00050020[0x0ffff3fe] ChipSize[33554432]
CHA[0] CHIP[0:1] @ 0x00050010[0x00000000] Disable, 1 DPC
CHA[0] MASK[0:1] @ 0x00050030[0x00000000]
CHA[0] CHIP[1:0] @ 0x00050004[0x00000401] Enable, 2 DPC
CHA[0] MASK[1:0] @ 0x00050024[0x0ffff3fe] ChipSize[33554432]
CHA[0] CHIP[1:1] @ 0x00050014[0x00000000] Disable, 2 DPC
CHA[0] MASK[1:1] @ 0x00050034[0x00000000]
CHA[0] CHIP[2:0] @ 0x00050008[0x00000801] Enable, 1 DPC
CHA[0] MASK[2:0] @ 0x00050028[0x0ffff3fe] ChipSize[33554432]
CHA[0] CHIP[2:1] @ 0x00050018[0x00000000] Disable, 1 DPC
CHA[0] MASK[2:1] @ 0x00050038[0x00000000]
CHA[0] CHIP[3:0] @ 0x0005000c[0x00000c01] Enable, 2 DPC
CHA[0] MASK[3:0] @ 0x0005002c[0x0ffff3fe] ChipSize[33554432]
CHA[0] CHIP[3:1] @ 0x0005001c[0x00000000] Disable, 2 DPC
CHA[0] MASK[3:1] @ 0x0005003c[0x00000000]
DIMM Size[33554432 KB] [32768 MB]
CHA[1] CHIP[0:0] @ 0x00150000[0x00000001] Enable, 1 DPC
CHA[1] MASK[0:0] @ 0x00150020[0x0ffff3fe] ChipSize[33554432]
CHA[1] CHIP[0:1] @ 0x00150010[0x00000000] Disable, 1 DPC
CHA[1] MASK[0:1] @ 0x00150030[0x00000000]
CHA[1] CHIP[1:0] @ 0x00150004[0x00000401] Enable, 2 DPC
CHA[1] MASK[1:0] @ 0x00150024[0x0ffff3fe] ChipSize[33554432]
CHA[1] CHIP[1:1] @ 0x00150014[0x00000000] Disable, 2 DPC
CHA[1] MASK[1:1] @ 0x00150034[0x00000000]
CHA[1] CHIP[2:0] @ 0x00150008[0x00000801] Enable, 1 DPC
CHA[1] MASK[2:0] @ 0x00150028[0x0ffff3fe] ChipSize[33554432]
CHA[1] CHIP[2:1] @ 0x00150018[0x00000000] Disable, 1 DPC
CHA[1] MASK[2:1] @ 0x00150038[0x00000000]
CHA[1] CHIP[3:0] @ 0x0015000c[0x00000c01] Enable, 2 DPC
CHA[1] MASK[3:0] @ 0x0015002c[0x0ffff3fe] ChipSize[33554432]
CHA[1] CHIP[3:1] @ 0x0015001c[0x00000000] Disable, 2 DPC
CHA[1] MASK[3:1] @ 0x0015003c[0x00000000]
DIMM Size[33554432 KB] [32768 MB] |
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This is the great news of my morning. Thank you. I will impact this algorithm into CoreFreq for AMD Zen architectures |
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Here is my design of the future model for AMD Zen which removes |
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@nooberfsh Hello, Could you try the CoreFreq branch |
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Sure. |
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Hi, I have some questions:
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I have programmed PMU events to monitor some Fabric Clocks but those are not compiled by default. You will have to employ a directive during the build. Then in the UI, you switch to the package view, pressing
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DDR5 Query
What is “non-binary” memory?
To decode the 24GB or 48GB DIMM geometry, can anyone dump some registers ?
[AMD] Zen 4 or 5
# Compile the tool cc zencli.c -o zencliDdrTypebits-field I expect to find some new DDR5 type values or something in theReservedpart[Intel]
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