Zen4 voltages #439

cyring · 2023-05-12T15:01:16Z

cyring
May 12, 2023
Maintainer

Specifications

Known addresses

/*		--- SMU SVI [ 0x5a00c ; 0x5a010 ; 0x5a014 ; 0x6f038] ---
 *				[ CPU addr]	[ SoC addr]
 * ZEN	[8F_01h]		[ 0x5a00c ]	[ 0x5a010 ]
 * ZEN(+) [8F_08h]		[ 0x5a00c ]	[ 0x5a010 ]
 * ZEN(+) [8F_11h ; 8F_18h]	[ 0x5a00c ]	[ 0x5a010 ]
 * ZEN2 [8F_71h]		[ 0x5a010 ]	[ 0x5a00c ]
 * ZEN2 [8F_60h]		[ 0x6f038 ]	[ 0x6f03c ]
 * ZEN2 [8F_31h]		[ 0x5a014 ]	[ 0x5a010 ]
 * ZEN3 [9F_21h]		[ 0x5a010 ]	[ 0x5a00c ]
 */

/*				--- SMU SVI [ Rembrandt ] ---
 *				[ CPU addr]	[ SoC addr]
 * ZEN3(+) [AF_44]		[ 0x6f010 ]	[ 0x6f014 ]
 */

/*
 * where addr = { 0x5a04c ... 0x5a04f || 0x5a050 ... 0x5a053 }
 * and '_mod' register offset could be equaled to:
 * 0x0		: Zen & Zen+		[UNTESTED]
 * 0x1		: Zen2/Matisse		[VERIFIED]
 * 0x2		: Zen2/CastlePeak	[UNTESTED]
 * 0x5404	: Renoir		[UNTESTED]
*/

Dump

Prerequisite

Compile zencli source code
zencli

Scan actions

## Zen{1,2,3} Desktop, Server
for addr in 0x5a00c 0x5a010 0x5a014 ; do ./zencli smu ${addr}; done

## Ryzen Mobile
for addr in 0x6f038 0x6f03c ; do ./zencli smu ${addr}; done

## Some Core VID
for addr in 0x5a04c 0x5a050 ; do ./zencli smu ${addr}; done

Remark:
A register output value of 0xffffffff means "does not exist".

amfern · 2023-05-13T10:31:55Z

amfern
May 13, 2023

Hi, here is the output of the commands

## Zen{1,2,3} Desktop, Server
[root@ilya C]# for addr in 0x5a00c 0x5a010 0x5a014 ; do ./zencli smu ${addr}; done
[0x0005a00c] READ(smu) = 0x00000000 (0)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
[0x0005a010] READ(smu) = 0x00000000 (0)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
[0x0005a014] READ(smu) = 0x00000000 (0)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000


## Ryzen Mobile
[root@ilya C]# for addr in 0x6f038 0x6f03c ; do ./zencli smu ${addr}; done
[0x0006f038] READ(smu) = 0xffffffff (4294967295)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111
[0x0006f03c] READ(smu) = 0xffffffff (4294967295)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111


## Some Core VID
[root@ilya C]# for addr in 0x5a04c 0x5a050 ; do ./zencli smu ${addr}; done
[0x0005a04c] READ(smu) = 0x00000000 (0)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
[0x0005a050] READ(smu) = 0x00000000 (0)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

2 replies

amfern May 13, 2023

The numbers, what do they mean?

cyring May 13, 2023
Maintainer Author

Those zero would mean the SMU has nothing at the requested address.

0xffffffff which is the hexadecimal of decimal -1 can mean there is no register behind the address or the privilege level or reader is not sufficient

cyring · 2023-05-13T12:55:38Z

cyring
May 13, 2023
Maintainer Author

Unfortunately, in above dump, no meaningful values are showing up.

Can you now try to read MSR 0xC0010071
defined as COFVID

rdmsr -ax 0xC0010071

Bits of interest could be CurNbVid; presuming that Northbridge Voltage ID is somehow the SoC.

2 replies

amfern May 13, 2023

[root@ilya C]# rdmsr -ax 0xC0010071
rdmsr: CPU 0 cannot read MSR 0xc0010071

cyring May 13, 2023
Maintainer Author

This MSR from legacy architectures doesn't work for Zen

cyring · 2023-05-13T14:00:26Z

cyring
May 13, 2023
Maintainer Author

In Wiki > Documentation > AMD Developer Guides you will find link to AMD Tech Docs where you can download the PPR specifications of Zen4. You have to select document of Raphael family and model numbers.
Document will list Registers of MSR or SMU

2 replies

cyring May 14, 2023
Maintainer Author

Processor Programming Reference (PPR) for AMD Family 19h Model 61h, Revision B1 Processors

amfern May 14, 2023

Thank you, i kinda guessed the same that the 7950x CPU is from 19h family and of the 61h model because the /proc/cpuinfo lists

cpu family  : 25
model       : 97
model name  : AMD Ryzen 9 7950X 16-Core Processor

model 97 is 0x61 in hex.
But it took me quite a while to read through the PPR, i am quite new to the terminology and PPR documentations

cyring · 2023-05-14T07:44:06Z

cyring
May 14, 2023
Maintainer Author

Can you read those from Rembrandt ?

for addr in 0x0006f010 0x0006f014 0x0006f018 0x0006f01c ; do ./zencli smu ${addr}; done

1 reply

amfern May 14, 2023

root@ilya C]# for addr in 0x0006f010 0x0006f014 0x0006f018 0x0006f01c ; do ./zencli smu ${addr}; done
[0x0006f010] READ(smu) = 0xffffffff (4294967295)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111
[0x0006f014] READ(smu) = 0xffffffff (4294967295)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111
[0x0006f018] READ(smu) = 0xffffffff (4294967295)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111
[0x0006f01c] READ(smu) = 0xffffffff (4294967295)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111

amfern · 2023-05-14T10:32:59Z

amfern
May 14, 2023

Is it possible that the SoC voltage is reported by the Motherboard and not part of the CPU registers?

5 replies

cyring May 14, 2023
Maintainer Author

Usually when reported by motherboard, it goes through a Super I/O chip.
Mine is for instance a NCT

When part of Processor, at least up to the Zen3+, SoC Voltage VID goes through the SMU, retrieved either from a SMM address, either from PM table, and/or HSMP reserved to server EPYC and some HEDT

amfern May 14, 2023

The motherboard is a Biostar racing GTQ b650e and i can see the super I/O chips but i am not sure how to probe them.

[root@ilya C]# superiotool
superiotool r4.19-1624-gd1c61a8e704
Found Aspeed AST2400 (id=0x00) at 0x2e
Found Aspeed AST2400 (id=0x00) at 0x4e
Found ITE IT8625E (id=0x8625, rev=0xc) at 0x2e

cyring May 14, 2023
Maintainer Author

Are you already getting voltage values using the semsors command; especially SoC voltage ?

amfern May 14, 2023

No, i don't see any voltage.

[root@ilya C]# sensors
drivetemp-scsi-3-0
Adapter: SCSI adapter
temp1:        +44.0°C
                                                                                                                                                                                                                                                                                                                
drivetemp-scsi-1-0
Adapter: SCSI adapter
temp1:        +46.0°C  (low  =  +0.0°C, high = +70.0°C)
                       (crit low =  +0.0°C, crit = +70.0°C)
                       (lowest = +30.0°C, highest = +50.0°C)
                                                                                                                                                                                                                                                                                                                
amdgpu-pci-0300
Adapter: PCI adapter
vddgfx:      538.00 mV
fan1:         675 RPM  (min =    0 RPM, max = 3300 RPM)
edge:         +43.0°C  (crit = +100.0°C, hyst = -273.1°C)
                       (emerg = +105.0°C)
junction:     +48.0°C  (crit = +110.0°C, hyst = -273.1°C)
                       (emerg = +115.0°C)
mem:          +62.0°C  (crit = +108.0°C, hyst = -273.1°C)
                       (emerg = +113.0°C)
PPT:          32.00 W  (cap = 290.00 W)
                                                                                                                                                                                                                                                                                                                
acpitz-acpi-0
Adapter: ACPI interface
temp1:        +64.0°C  (crit = +127.0°C)
                                                                                                                                                                                                                                                                                                                
k10temp-pci-00c3
Adapter: PCI adapter
Tctl:         +64.0°C
Tccd1:        +51.0°C
Tccd2:        +46.4°C
                                                                                                                                                                                                                                                                                                                
drivetemp-scsi-2-0
Adapter: SCSI adapter
temp1:        +50.0°C
                                                                                                                                                                                                                                                                                                                
drivetemp-scsi-0-0
Adapter: SCSI adapter
temp1:         +0.0°C  (low  =  +0.0°C, high = +70.0°C)
                       (crit low =  -5.0°C, crit = +75.0°C)
                       (lowest =  +0.0°C, highest =  +0.0°C)
                                                                                                                                                                                                                                                                                                                
nvme-pci-0c00
Adapter: PCI adapter
Composite:    +45.9°C  (low  = -273.1°C, high = +84.8°C)
                       (crit = +84.8°C)
Sensor 1:     +45.9°C  (low  = -273.1°C, high = +65261.8°C)
Sensor 2:     +47.9°C  (low  = -273.1°C, high = +65261.8°C)

amfern May 15, 2023

Does CoreFreq currently able to display the SOC voltage for zen3 cpus?

amfern · 2023-05-15T00:52:57Z

amfern
May 15, 2023

It seems like k10temp driver used to support zen3 SoC voltage, but this support for was dropped here torvalds/linux@0a4e668
and it was added here torvalds/linux@55163a1

It seems like zen3 and zen4 are both from 19h fameliy so i guess they will have similar way of reading SoC voltage.

3 replies

cyring May 15, 2023
Maintainer Author

Socket, Core and SoC voltages I have achieved on Zen3+ Rembrandt Mobile
Ryzen 5 6600H

Those SMU addresses which however belong to the Mobile segment have not worked in our previous zencli tests.

This is where we are stopped with Zen4

cyring May 15, 2023
Maintainer Author

And you will also read in kernel at

#define ZEN_SVI_BASE 0x0005A000

which is the same specified base address, for Desktop and Server segment, used in corefreqk.ko module.

This is where we are stopped with Zen4

If we are lucky, the manufacturer has just shifted the whole voltage BAR offset.
This is how I have, by chance, found it on Rembrandt on testing, idle, next stressed, next idle, one by one, each address, per increment of 4, because SMU is still 32-bits, at least up to Zen3+

When a SMU address has a moving value depending on system load, then you know you are facing some kind of indicator: voltage or temp or power or clock

cyring May 15, 2023
Maintainer Author

And there's also a bad chance Phoenix voltages are not available either.
But I have not received some screenshot evidences of CoreFreq PHX support.

amfern · 2023-05-16T10:54:50Z

amfern
May 16, 2023

I have scanned the Range of addresses and I found two values that change relative to system performance. 0x000730d8 and 0x00073010

I am able to see package power via turbostat command, so I wonder if it's possible to find SoC VID in msr registers, also what is the relationship between MSR registers and PCI (what is zencli is reading)?
Screencast from 2023-05-16 16-59-54.webm
Screencast from 2023-05-16 18-24-53.webm

9 replies

cyring Jun 1, 2025
Maintainer Author

@cyring I had to fix the aur https://aur.archlinux.org/pkgbase/corefreq-git package to make it work. Can you give me permission to edit it, or maybe it's better to remove it because it's not maintained.

You will have to reach the package owner mentioned in PKGBUILD : Leonidas @Artafinde for an update or to get the ownership.

cyring Jun 1, 2025
Maintainer Author

@cyring Thank you! It seems to work, i tired to stress the memory controller with stress-ng --vm 32 --vm-bytes 1G --timeout 60s command.

Idle @ 1.1250V

Stressed @ 1.438V

Can 1.438V be a SoC voltage ?

I'm not yet familiar with Zen4 but I have read some issues that SoC could have crazy voltage values which leads to Raphael damage. BIOS upgrades had followed to limit problem.
Is your platform BIOS was fixed ?

amfern Jun 1, 2025

I’m not sure if my BIOS is patched. I haven’t had issues running this system for over a year, but I’m worried about high SoC voltage potentially damaging the CPU, which is why I want to monitor SoC voltage in CoreFreq a year ago.

amfern Jun 1, 2025

Can 1.438V be a SoC voltage ?

Sorry i fixed my original post, it's 1.1438v.

cyring Jun 1, 2025
Maintainer Author

Can 1.438V be a SoC voltage ?

Sorry i fixed my original post, it's 1.1438v.

Great!
I'm confident we have a good register address

I'm now looking in the addresses around for the IDD in Amps then I can convert SoC voltage to SoC power in Watt

cyring · 2023-05-16T16:31:44Z

cyring
May 16, 2023
Maintainer Author

In none MSR I've found SoC voltage.
Only CPU Core VID is found within P-states and Boosted P-state MSR
SoC VID can be retrieved from undocumented SMU registers.

VID is usually an 8-bits you will supply to a voltage formula:

Families 17h, 19h
https://github.com/cyring/CoreFreq/blob/a28ea7bea3cab13493c1011d28fa2d564722cd3a/coretypes.h#LL726C15-L726C15
Rembrandt

CoreFreq/coretypes.h

Line 729 in a28ea7b

#define COMPUTE_VOLTAGE_AMD_RMB(Vcore, VID) \

The register values you found in SMU addresses 0x00073010 and 0x000730d8 you mask the 8-bits at non zero. Can be at position 0, 8, 16, or 24 then right shifted to bit position 0

Then compute Voltage using formulas (which are solving Vcore but also SoC voltage, if we're lucky)

MSR may cache PCI registers or other IP registers, can be IP microcode.
But, contrary to Intel, I have not found (many) AMD Zen overlapping features between MSR and PCI.

7 replies

cyring May 17, 2023
Maintainer Author

Idle

0x3bc10000

$$3B: 1.55−(0.00625×59)=1.18V$$

$$C1: 1.55−(0.00625×193)=0.34V$$

0x0000ba81

$$BA: 1.55−(0.00625×186)=0.39V$$

$$81: 1.55−(0.00625×129)=0.74V$$

Under stress

0x34010000

$$34: 1.55−(0.00625×52)=1.22V$$

$$01: 1.55−(0.00625×01)=1.54V$$

0x0000b401

$$B4: 1.55−(0.00625×180)=0.42V$$

cyring May 17, 2023
Maintainer Author

Do they look like voltages of your Processor Elements ?

amfern May 17, 2023

[0x000730d8] looks kinda like the voltage while the SoC VID is configured to 1.200v in bios
1.550 - (0.00625 * 0x3bc10000 >> 24) = 1.18125 (idle)
1.550 - (0.00625 * 0x34010000 >> 24) = 1.225 (load)

But if I set the SoC VID to 1.020v in bios, it doesn't really change by much.
1.550 - (0.00625 * 0x3c810000 >> 24) = 1.175 (idle)
1.550 - (0.00625 * 0x34410000 >> 24) = 1.225 (load)

cyring May 17, 2023
Maintainer Author

What I can tell about my 3950X + X570 board is that Voltage SoC just fluctuates about 0.01V

If registers you found are indeed voltages then it could be other components: Fabric, I/O die ?
Can you post screenshots of the BIOS all voltages to search for a match ?

amfern May 18, 2023

What I can tell about my 3950X + X570 board is that Voltage SoC just fluctuates about 0.01V

Thank you, i was wondering what it i should be looking for.
I noticed in my bios that SOC Voltage will fluctuate by about 0.01 too.

I can really pinpoint the voltage reported by [0x000730d8] register though.

cyring · 2023-05-18T06:38:53Z

cyring
May 18, 2023
Maintainer Author

Fyi, Registers you found in Zen4 don't seem to work on Zen2. These are results on my 3950X:

# ./zencli smu 0x00073010
[0x00073010] READ(smu) = 0xffffffff (4294967295)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111

# ./zencli smu 0x000730d8
[0x000730d8] READ(smu) = 0xffffffff (4294967295)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111

0 replies

cyring · 2023-05-18T07:10:26Z

cyring
May 18, 2023
Maintainer Author

We can try other ports for the HSMP protocol:

Please change at lines:

CoreFreq/amd_reg.h

Line 164 in a28ea7b

#define SMU_AMD_INDEX_PORT_F17H 0x60

and replace with:

#define SMU_AMD_INDEX_PORT_F17H 	0xc4
#define SMU_AMD_DATA_PORT_F17H		0xc8

rebuild all and load driver

make clean all
insmod ./corefreqk.ko

next check into your kernel log (dmesg) if you encounter a HSMP timeout or error ?

1 reply

amfern May 20, 2023

I see timeout message

[ 3400.073129] CoreFreq: PCI_HSMP_Mailbox(1) Timeout
[ 3400.203246] CoreFreq(8:24:-1): Processor [ AF_61] Architecture [Zen4/Raphael] SMT [32/32]

cyring · 2023-05-18T11:30:02Z

cyring
May 18, 2023
Maintainer Author

In the article of igorslab.de you'll find the link to the "Renesas Electronics Corporation. 2020. ISL62776 Multiphase PWM Regulator for AMD CPUs Using SVI2"

Once PDF downloaded, you will go to Table 5. Serial VID Codes

This match the 0x0000b401 and could confirmed the found Register 0x00073010 as a SVI2

Concerning SVI3 on Zen4, I have not found much info on renesas.com

2 replies

amfern May 20, 2023

Interesting, it does fit the voltage.

cyring May 20, 2023
Maintainer Author

I gave a quick look to the Renesas datasheets: SVI3 can be the answer; it requires an I2C dialog, I believe some userspace tools can help to query VID.

cyring · 2023-06-13T07:04:50Z

cyring
Jun 13, 2023
Maintainer Author

@amfern Hello,

I'm still not giving up with this subject.

Can you try the AMD HSMP driver ?
CoreFreq is apparently doing the same protocol but just in case I forgot something.

Based on latest Linux kernel, make sure CONFIG_AMD_HSMP is set. Mine is m for module.

zgrep CONFIG_AMD_HSMP /proc/config.gz 
CONFIG_AMD_HSMP=m

If unset, build your own kernel: in make menuconfig go to AMD HSMP Driver to enable that driver.

Next, load the module and post the result from the kernel log.

modprobe amd_hsmp

If you reach the point where driver is correctly inserted, we will submit commands in subsequent post.

Thank you
CyrIng

5 replies

amfern Jun 15, 2023

Sorry been busy with personal life and had some weird issue of random freezes, and disabling c-states seems to fix it.

Thank you for not giving up, I will try your suggestion abit later.

amfern Jun 15, 2023

I get the error message

[ 1401.421165] amd_hsmp: HSMP is not supported on Fam:19 model:61
[ 1401.421168] amd_hsmp: Or Is HSMP disabled in BIOS ?

cyring Jun 15, 2023
Maintainer Author

Does this mean that AMD has definitely fuse HSMP off, with the exception of EPYC processors ?

amfern Jun 15, 2023

I don't see the option to enable HSMP in the bios either.

cyring Jun 15, 2023
Maintainer Author

I've been answered that the functional HSMP mailbox protocol in 3950X was a design mistake. Oops.

cyring · 2024-03-18T07:33:31Z

cyring
Mar 18, 2024
Maintainer Author

Meanwhile in this EPYC/Genoa output, we have confirmation that HSMP has worked for Version and some PL fields:

Processor                                     [AMD EPYC 9274F 24-Core Processor]
|- Firmware                                                        [ 71.121.0-5]
...
|- Thermal Design Power                                      Package   < Enable>
   |- Power Limit                                                PL1   <  400 W>
   |- Time Window                                                TW1   <   0 ns>
   |- Power Limit                                                PL2   <  400 W>

1 reply

cyring Mar 27, 2024
Maintainer Author

But the boosted frequency ratio from SMU on Genoa is inconsistent.
See this issue
Bit fields and/or addresses of Zen4 seem to be now undocumented.

mikealanni · 2024-06-20T05:13:56Z

mikealanni
Jun 20, 2024

Any news about Zen4 voltages. Thanks

3 replies

cyring Jun 20, 2024
Maintainer Author

We stopped at getting successfully the Voltage P-State
See these examples:

https://gist.github.com/cyring/b48da82e6ccbce83d88f8e127beac743?permalink_comment_id=4449915#gistcomment-4449915

https://gist.github.com/cyring/36b8fab0f6f5e61d52aa9abe07c532a0

mikealanni Jun 20, 2024

I have AMD 7945HX, and here are some screenshots. Do they showing the right numbers?

cyring Jun 20, 2024
Maintainer Author

In the last screenshot, from the Min to the Max, the amplitude of the Core Voltage appears not very large.

Can you show the Voltages view when CPU are idling; no stress ?

According to the processor specs the Cores Power measured is closed to 55W TDP and max temperature below the 100C TjMax

mikealanni · 2024-06-20T14:43:49Z

mikealanni
Jun 20, 2024

Here you go

And this with full stress

7 replies

mikealanni Jun 20, 2024

No my bios not showing core voltage my MB is BD790i, here is single core pic

Also my MB has it87 and here is sensors results (when stressed) if that's helpful to you. aldo another information may important I'm using 6.10 kernel
`sensors
it8620-isa-0a30
Adapter: ISA adapter
in0: 936.00 mV (min = +0.00 V, max = +3.06 V)
in1: 1.20 V (min = +0.00 V, max = +3.06 V)
in2: 2.18 V (min = +0.00 V, max = +3.06 V)
+5V: 4.37 V (min = +0.00 V, max = +6.12 V)
in4: 2.20 V (min = +0.00 V, max = +3.06 V)
in5: 1.93 V (min = +0.00 V, max = +3.06 V)
in6: 1.85 V (min = +0.00 V, max = +3.06 V)
3VSB: 3.58 V (min = +0.00 V, max = +6.12 V)
Vbat: 3.55 V
fan2: 0 RPM (min = 0 RPM)
fan3: 1569 RPM (min = 0 RPM)
fan4: 0 RPM (min = 0 RPM)
fan5: 1923 RPM (min = 0 RPM)
temp1: +57.0°C (low = -128.0°C, high = +127.0°C) sensor = thermistor
temp2: +65.0°C (low = -128.0°C, high = +127.0°C) sensor = thermistor
temp3: +85.0°C (low = -128.0°C, high = +127.0°C)
temp4: +0.0°C
temp6: +57.0°C
intrusion0: ALARM

nvme-pci-0200
Adapter: PCI adapter
Composite: +49.9°C (low = -5.2°C, high = +89.8°C)
(crit = +93.8°C)

iwlwifi_1-virtual-0
Adapter: Virtual device
temp1: N/A

amdgpu-pci-0600
Adapter: PCI adapter
vddgfx: 854.00 mV
vddnb: 1.10 V
edge: +73.0°C
PPT: 29.24 W`

mikealanni Jun 20, 2024

Also this the p-state if they help and correct sudo ./zenstates.py -l P0 - Enabled - FID = 7D - DID = A - VID = C9 - Ratio = 25.00 - vCore = 0.29375 P1 - Enabled - FID = 78 - DID = 10 - VID = 79 - Ratio = 15.00 - vCore = 0.79375 P2 - Disabled P3 - Disabled P4 - Disabled P5 - Disabled P6 - Disabled P7 - Disabled C6 State - Package - Enabled C6 State - Core - Enabled

cyring Jun 20, 2024
Maintainer Author

Putting back the Core Performance Boost in the array

Case	`VID`	`f1`	`f2`
Idle `9:40`	`231`	`1.443`	`0.107`
Full `9:40`	`182`	`1.137`	`0.412`
Full `7:19`	`122`	`0.762`	`0.788`
CPB `11:06`	`211`	`1.318`	`0.231`

Meanwhile in the Renesas ISL62776 datasheet, I'm reading among the Features

0.5V to 1.55V in 6.25mV steps

What about raising the lowest bound by 0.5V ?

$$f3(): VID = 2.05 - (0.00625 * VID)$$

Case	`VID`	`f1`	`f3`
Idle `9:40`	`231`	`1.443`	`0.606`
Full `9:40`	`182`	`1.137`	`0.912`
Full `7:19`	`122`	`0.762`	`1.287`
CPB `11:06`	`211`	`1.318`	`0.731`

f3 pleases most cases but CPB

cyring Jun 20, 2024
Maintainer Author

zenstates.py

It's the same formula. So it does not solve the issue.

cyring Jun 21, 2024
Maintainer Author

Things found about 7945HX Vcore

Does your BIOS show Core voltage ?

https://www.guru3d.com/review/amd-ryzen-9-7945hx-processor-review/page-5/

cyring · 2024-06-20T16:54:29Z

cyring
Jun 20, 2024
Maintainer Author

In the Sensors command line in0 is "Vcore"

it8620-isa-0a30
Adapter: ISA adapter
in0: 936.00 mV (min = +0.00 V, max = +3.06 V)

To find a formula, it will be useful if you can report in0 in these 3 cases.

You can employ employ the CoreFreq Tool to stress CPU

Conic Compute > Hyperboloid of two sheets to fully stressed all Cores
Turbo < Select CPU > to trigger Core Performance Boost on your best Core

Please report values in such array:

Case	`VID`	`in0`
Idle	`?`	`?`
Full	`?`	`?`
CPB	`?`	`?`

Btw thanks I did not know MINIS FORUM

8 replies

cyring Jun 20, 2024
Maintainer Author

Do you have unload the old driver corefreqk.ko ?

Because there is a version check inside the 3 binaries: driver, daemon and client.
This control is made to avoid a mix of incompatible API.

Make sure old binaries are not within PATH
Uninstall first if CoreFreq came from a distro package
No resident driver listed by lsmod then build and load the latest with change applied

mikealanni Jun 20, 2024

Yes forget to unload them...

Here is the new screenshots

cyring Jun 20, 2024
Maintainer Author

Great.
Are you finding Vcore more accurate in various cases ?

mikealanni Jun 21, 2024

This other cases, Idle, Hyperboloid of two sheets and one CPU turbo

cyring Jun 21, 2024
Maintainer Author

Thank you for your returns.

I will go to sleep thinking about Maths in this issue.
In any case:

VID is correct
Voltage may be linear to VID
A constant has to be added or subtracted
Probably an additional 0.5v

cyring · 2024-06-22T01:10:42Z

cyring
Jun 22, 2024
Maintainer Author

@mikealanni Hi

If you have the msr-tools, can you please read, in the 3 cases, that register

CoreFreq/x86_64/amd_reg.h

Line 80 in 7c8d354

#define MSR_AMD_F17H_HW_PSTATE_STATUS 0xc0010293

Like:

rdmsr -a -x 0xc0010293

14 replies

cyring Jun 23, 2024
Maintainer Author

I still have no clue.
There are 2 working formulas: f2 is common among all Zen; f1 is in use in 1 or 2 cases.
But Dragon Range does not work with any, despite this architecture shares the same CPUID family as Raphael.
I wonder if we can reverse the formula of in0 and apply it to the VID of a P-State ?

cyring Jun 23, 2024
Maintainer Author

The original source code, same as current is to me the most appropriate function which is f1

$$Vcore = VID×0.00625$$

The fact that we don't see a Vcore coherent with the load: is it explained by a screenshot slightly in late with the real monitoring ?

mikealanni Jun 23, 2024

I'm not that expert but I have 3 AMDs if you need help collecting data, 7945HX, EPYC 7763 and 7940HS. I really want to manage power or CPU frequency for 7945HX and 7763 on Linux command line to to manage the heat a little bit

cyring Jun 23, 2024
Maintainer Author

Sure it will be very helpful if you can show your other Zen.
In particular those which are not listed in the Wiki CPU Support list.
I suggest you create a discussion issue per model in which you can let screenshots and CLI outputs in Markdown format
Like the output of the following:

corefreq-cli -s -n -m -n -B -n -M -n -k -n -C 1 -n -i 1 -n -V 1 -n -W 1

cyring Jun 23, 2024
Maintainer Author

PS: I suggest you pull latest commit from the branch master

tofurky · 2024-06-25T17:11:48Z

tofurky
Jun 25, 2024

As requested, here is output from 7950x. CPU load was generated with stress-ng --cpu-method fft on 1 (single) or 32 (multi) cores.

corefreq-cli -s -n -m -n -M -n -B -n -k: corefreq_info.txt
corefreq-cli -V 2 : corefreq_idle.txt
corefreq-cli -V 2: corefreq_single.txt
corefreq-cli -V 2: corefreq_multi.txt

14 replies

tofurky Jun 26, 2024

I didn't see a way to dump registers from HWiNFO. If you give the address and width I can use rdmsr.

Here are dumps from HWiNFO:
7950x_hwinfo_fft_core0.CSV
7950x_hwinfo_fft_even_cores.CSV
7950x_hwinfo_fft_idle.CSV

mikealanni Jun 26, 2024

Thanks a lot.

EPYC 7763 which is a Milan shows coherent voltages

7945 is reproducing the same voltage oddness than the other previous Zen4

Can you post detail of 7945 which is listed under different brands in source code
corefreq-cli -s -n -m -n -k -n -M -n -k -n -C 2

Here you go
info.txt

cyring Jun 26, 2024
Maintainer Author

Thank you, it is added in Wiki CPU support AMD Desktops

The DIMM computed size is wrong. It's an opened issue

I make the mistake to ask you twice the kernel output. Can you post SMBIOS as below?

corefreq-cli -B

mikealanni Jun 26, 2024

Thank you, it is added in Wiki CPU support AMD Desktops

The DIMM computed size is wrong. It's an opened issue

I make the mistake to ask you twice the kernel output. Can you post SMBIOS as below?
corefreq-cli -B

Here you go
smbios.txt

cyring Jun 26, 2024
Maintainer Author

Thanks!

cyring · 2024-06-26T10:49:19Z

cyring
Jun 26, 2024
Maintainer Author

@tofurky @mikealanni

Reading SKATTERBENCHER I wonder if among your ASUS boards some Custom Algorithms are in action ?

If true, please deactivate all tweaks and report about the VID

1 reply

cyring Aug 7, 2024
Maintainer Author

Very strange that I found this reddit employing 1 year a go the original Vcore formula showing correct results on Ryzen 9 7900

Now I'm wondering if we did not make all these efforts to cover a hardware/firmware setup issue

Who among Zen4 Desktop and Mobile can confirm good Vcore or accuracy regression ?

cyring · 2024-06-27T06:16:12Z

cyring
Jun 27, 2024
Maintainer Author

@tofurky @mikealanni

From the top of this discussion, @amfern has scanned two noticeable addresses: 0x000730d8 and 0x00073010

Can you please scan those addresses, in the 3 cases (Idle, Full, Single), using the zencli on your 7950X 7945HX ?

Second CCD could be read by placing one in front of the addresses 0x001730d8 and 0x00173010

2 replies

tofurky Jun 27, 2024

idle:

Thu Jun 27 01:39:13 PM EDT 2024
[0x00073010] READ(smu) = 0x0000bbc1 (48065)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1011 1011 1100 0001
[0x000730d8] READ(smu) = 0x3bc10000 (1002504192)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0011 1011 1100 0001 0000 0000 0000 0000

Thu Jun 27 01:39:18 PM EDT 2024
[0x00073010] READ(smu) = 0x0000bb81 (48001)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1011 1011 1000 0001
[0x000730d8] READ(smu) = 0x3b810000 (998309888)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0011 1011 1000 0001 0000 0000 0000 0000

Thu Jun 27 01:39:23 PM EDT 2024
[0x00073010] READ(smu) = 0x0000bbc1 (48065)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1011 1011 1100 0001
[0x000730d8] READ(smu) = 0x3bc10000 (1002504192)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0011 1011 1100 0001 0000 0000 0000 0000

1 core (pinned to core 0 via taskset -cp 0):

Thu Jun 27 01:42:20 PM EDT 2024
[0x00073010] READ(smu) = 0x0000b941 (47425)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1011 1001 0100 0001
[0x000730d8] READ(smu) = 0x39410000 (960561152)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0011 1001 0100 0001 0000 0000 0000 0000

Thu Jun 27 01:42:25 PM EDT 2024
[0x00073010] READ(smu) = 0x0000b9c1 (47553)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1011 1001 1100 0001
[0x000730d8] READ(smu) = 0x39810000 (964755456)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0011 1001 1000 0001 0000 0000 0000 0000

Thu Jun 27 01:42:30 PM EDT 2024
[0x00073010] READ(smu) = 0x0000b981 (47489)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1011 1001 1000 0001
[0x000730d8] READ(smu) = 0x39810000 (964755456)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0011 1001 1000 0001 0000 0000 0000 0000

16 core:

Thu Jun 27 01:43:14 PM EDT 2024
[0x00073010] READ(smu) = 0x0000b1c1 (45505)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1011 0001 1100 0001
[0x000730d8] READ(smu) = 0x31c10000 (834732032)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0011 0001 1100 0001 0000 0000 0000 0000

Thu Jun 27 01:43:19 PM EDT 2024
[0x00073010] READ(smu) = 0x0000b241 (45633)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1011 0010 0100 0001
[0x000730d8] READ(smu) = 0x32410000 (843120640)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0011 0010 0100 0001 0000 0000 0000 0000

Thu Jun 27 01:43:24 PM EDT 2024
[0x00073010] READ(smu) = 0x0000b1c1 (45505)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1011 0001 1100 0001
[0x000730d8] READ(smu) = 0x31c10000 (834732032)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0011 0001 1100 0001 0000 0000 0000 0000

adding 1 to the beginning didn't return data:

[0x00173010] READ(smu) = 0xffffffff (4294967295)
  60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111
[0x001730d8] READ(smu) = 0xffffffff (4294967295)
  60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111

cyring Jun 27, 2024
Maintainer Author

Thanks
Here's the adapted spreadsheet but no significant voltage found
Zen4_VID.ods.gz

cyring · 2024-06-30T03:29:54Z

cyring
Jun 30, 2024
Maintainer Author

SVI3 issues

Do you have a BIOS|firmware which might limit the high voltage ?

Like when turbo is engaged, my Zen2 claims 1.5V but an all Cores stress remains around 1.24V

1 reply

tofurky Jun 30, 2024

there definitely was an issue with zen4 frying with high voltages, especially x3d series, but there's been bios with soc voltage limit for about a year now from what i understand. i don't know how it worked under the hood. apparently vendors were ignoring amd recommendations,

cyring · 2024-06-30T04:38:58Z

cyring
Jun 30, 2024
Maintainer Author

The RT3678BE is designed to meet AMD SVI3 compatible CPUs specification

This datasheet shows the SVI3 Type 1 Target VID Table in page 44

...

...

...

It explains the VID[8] added in Zen4 specifications

The step is this time 0.005V

A formula is calibrated based on the various samples and an expected minimum of 0.635V:

$$Vcore = 2.09 - ((VID * 0.005) + 0.245)$$

@tofurky @mikealanni

Based on the master branch, can you please change the formula at this line:

CoreFreq/x86_64/coretypes.h

Line 776 in 43b96ae

#define COMPUTE_VOLTAGE_AMD_RMB(Vcore, VID) \

Replace with:

#define COMPUTE_VOLTAGE_AMD_RMB(Vcore, VID)				\
		( Vcore = 2.09 - ((0.005 * (double) (VID)) + 0.245) )

Rebuild and make sure to reload driver corefreqk.ko

make -j clean
make -j

Proceed to testings and let me know if voltage is accurate or not ?

0 replies

mikealanni · 2024-06-30T05:13:43Z

mikealanni
Jun 30, 2024

Here you go

6 replies

cyring Jun 30, 2024
Maintainer Author

Since commit 2ded4e4, still in branch develop, a new formula is now applied.

Voltage formula can be calibrated at will until we met accuracy.

Remark: voltage SoC is deactivated.

CoreFreq/x86_64/coretypes.h

Line 781 in 2ded4e4

#define COMPUTE_VOLTAGE_AMD_19_61h(Vcore, VID) \

tofurky Jun 30, 2024

Since commit 2ded4e4, still in branch develop, a new formula is now applied.

here's develop branch idle, core0, 16core fft

cyring Jun 30, 2024
Maintainer Author

Thanks for these outputs

To fully stress all Cores, you can use the integrated Tools in corefreq-cli
Run one of the Conics stress loops, the VID should reach its max

tofurky Jul 1, 2024

conics ellipsoid:

cyring Jul 1, 2024
Maintainer Author

Thank you for this stress test.

The max Vcore has been recorded to ~~1.255~~1.61 (edit: which means a VID of 47) but only showing 0.915
edit: lowering the interval to 100ms may give us a chance to display Voltage at the time it switches

It's odd when comparing 7950X with 3950X voltage curve.

Btw, are they some BIOS tweaks in effect which impact high voltage ?

As said above, you can calibrate the formula (in source code) against the expected voltages traced with Windows tools or Linux sensors.
Please let me know if you find more appropriated equation paramaters ?

cyring · 2024-08-07T14:08:06Z

cyring
Aug 7, 2024
Maintainer Author

This is a follow up to my question

0 replies

cyring · 2024-08-25T11:46:34Z

cyring
Aug 25, 2024
Maintainer Author

Please go to Voltage Curve Optimizer #506 issue

0 replies

cyring · 2025-04-27T07:36:29Z

cyring
Apr 27, 2025
Maintainer Author

I'm testing by myself this Mobile Zen4 and the voltage Vcore taken from the Boosted P-State MSR appears to work as expected

Idle `@ 0.61 V`

Single Core `@ 1.48 V`

All Cores `@ 0.93 V`

Algorithm for this Hawk Point is the same as the formula used for Zen4, especially Desktop/Raphael

Because I don't find any tweak in BIOS for Mobile to alter voltage "curve", I tend to believe the inaccurate voltage reading I'm getting from Desktop Ryzen and perhaps new EPYC are due to their various Voltage Curve BIOS options.

The only way to check is that if Owners of such boards could set Voltage to the most standards; disabling all tweaks as possible. Further than that, disabling Idle States and letting board running at full P0 P-state while reading the Hardware P-State MSR

## MSR_AMD_F17H_HW_PSTATE_STATUS
rdmsr -aX 0xc0010293

0 replies

cyring · 2025-06-01T17:47:36Z

cyring
Jun 1, 2025
Maintainer Author

#439 (reply in thread)

0 replies

cyring · 2026-05-07T08:56:37Z

cyring
May 7, 2026
Maintainer Author

Zen5 of Family 1Ah , I don't have the SMU address for Voltage SoC and Processor : any idea ?

0 replies

Zen4 voltages #439

Uh oh!

cyring May 12, 2023 Maintainer

Specifications

Known addresses

Dump

Prerequisite

Scan actions

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