V4-4 Phase A2: Ryzen AI NUC measurer + mapper support (CPU + Radeon iGPU + XDNA NPU)

[Ravenwater]

Context

The V4 validation harness currently supports CPU (i7-12700K via RAPL), desktop NVIDIA (H100 via NVML), and Jetson NVIDIA (Orin via INA3221). To extend coverage to AMD Ryzen AI NUCs (Hawk Point / Strix Point / Strix Halo), three new measurer backends + corresponding hardware mappers + plumbing entries need to land.

The capture-on-target runbook (bin/v4-capture-ryzen-ai-nuc.sh) is already in place but only Step 1 ("identify which NUC you have") works without this issue resolved. Steps 2-13 require the code below.

Hardware mappers (registry)

src/graphs/hardware/mappers/cpu.py

• create_ryzen_ai_9_hx_370_mapper -- Strix Point, Zen 5, NPU 50 TOPS
• create_ryzen_7_8840hs_mapper -- Hawk Point, Zen 4, NPU 16 TOPS
• create_ryzen_ai_max_plus_395_mapper -- Strix Halo, Zen 5, NPU 50 TOPS

Each captures: P-core / E-core counts, AVX2/AVX-512 SIMD width, L1/L2/L3 hierarchy with on-chip BW peaks per #61, DDR5 / LPDDR5X DRAM BW, integrated graphics block reference for partition routing.

src/graphs/hardware/mappers/gpu.py

• create_radeon_780m_mapper -- RDNA 3, 12 CUs, Hawk Point
• create_radeon_890m_mapper -- RDNA 3.5, 16 CUs, Strix Point
• create_radeon_8060s_mapper -- RDNA 3.5, 40 CUs, Strix Halo

Each captures: CU count, peak FP32/FP16/BF16, shared L1/L2 hierarchy + ROCm precision profiles.

src/graphs/hardware/mappers/accelerators/xdna.py (new file)

• create_xdna1_npu_mapper -- Phoenix / Hawk Point, ~16 TOPS INT8
• create_xdna2_npu_mapper -- Strix Point / Halo, ~50 TOPS INT8

Heterogeneous tile architecture (AIE-ML tiles); shape-similar to KPU but with different scratchpad / dataflow semantics. Per the v4 plan Principle 2, the NPU may need to be consistency-only validated (the V4-5 KPU pattern) until simulator output is available.

Ground-truth measurers (validation/model_v4/ground_truth/)

pytorch_amd_cpu.py

PyTorchAMDCPUMeasurer: wall-clock + amd_energy sysfs (/sys/devices/platform/amd_energy.0/hwmon/hwmonN/energy*_input). Some Zen 4+ kernels also expose Intel-style RAPL at /sys/class/powercap/intel-rapl:0/; the probe should try both and report which succeeded. Shape-mirrors pytorch_cpu.py.

pytorch_rocm.py

PyTorchROCmMeasurer: hipEvent timing + amdgpu sysfs power (/sys/class/drm/cardN/device/hwmon/hwmonM/power1_average in uW). Note: ROCm support on consumer Radeon (RDNA 3+) is fragile; the measurer must surface "ROCm not available" cleanly when torch.cuda.is_available() returns False on a non-NVIDIA system. Shape-mirrors pytorch_cuda.py.

onnx_xdna.py

OnnxXdnaMeasurer: ONNX Runtime with Vitis AI / Ryzen AI execution provider + xrt-smi telemetry. Different shape from the PyTorch-based measurers; takes an exported ONNX model rather than nn.Module. The harness will need a thin adapter so it can drive ONNX-EP measurers via the same ground_truth.base.Measurer Protocol.

XDNA power telemetry is driver-version-dependent. As of late-2025 drivers, rails appear under /sys/bus/pci/drivers/amdxdna/*/hwmon/hwmonN/ or /sys/class/amdxdna/*/power. If both paths are missing, the measurer should fall through to xrt-smi parsed-output as a fallback, or emit energy_j=None with a note.

Plumbing

• validation/model_v4/sweeps/_augment.py KNOWN_TARGETS: 8 new entries (3 CPU + 3 GPU + 2 NPU)
• validation/model_v4/harness/runner.py SWEEP_HW_TO_MAPPER: same 8 keys
• validation/model_v4/cli/capture_ground_truth.py _MEASURER_FACTORY: dispatch tags pytorch_amd_cpu, pytorch_rocm, onnx_xdna
• tests/validation_model_v4/test_sweeps.py hw fixture: 8 new mapper instances
• After plumbing: run python -m validation.model_v4.sweeps._augment --all to additively classify the new keys against existing committed sweep entries.

Tests

Each new measurer needs a mock-based test in tests/validation_model_v4/ (matching the test_ground_truth_pytorch_cuda.py and test_ground_truth_pytorch_jetson.py pattern). The augmented sweep tests in test_sweeps.py will then auto-cover the new keys.

Phase B follow-up (separate PR)

Once Phase A2 lands, run bin/v4-capture-ryzen-ai-nuc.sh on a real NUC; commit the resulting CSVs under validation/model_v4/results/baselines/; add test_<hw>_pass_*_floor cases pinning the post-capture pass rates.

Provenance

Filed alongside the Ryzen AI NUC capture runbook. The runbook references this issue in its "Phase A prerequisites" section.