Just a question, I am trying to understand the code

[edwin-oetelaar]

Thanks for sharing your code and video's I am learning from it and will also be using some of it to assist some students by pointing them to your project.

https://github.com/bikerglen/beagle/blame/master/projects/led-pixels/fpga/rtl/dmx_tx.v#L108

You repeat the logic block that already exists in the IDLE state. (checking available data etc)
Would it not have been simpler to move to the IDLE state after sending the byte out.
I am trying to make sense of the verilog code and reconstruct the state diagram / state transitions diagram (so I can explain them to other people too)

As a general question : Do you have a structured way to approach FSM design? I have not been able to find a good tutorial yet. Pointers welcome. As a general remark, your code and design looks very clean ;-) compared to other stuff I found.
Greetings from the Netherlands

[bikerglen]

Hi! It's been a while since I wrote the code but I do still use it in projects frequently. If I jumped back to the IDLE state, I would have had a one clock pause between words of transmit data. By duplicating the code rather than jumping back to the IDLE state, I don't have the one clock pause. As a result, all my bits are spaced and timed perfectly.

Thanks. I try to keep my code readable and simple. I also try to a better job at commenting now than when I wrote that code. There's likely some way to code this so that the code isn't duplicated but I felt this was a bit clearer to understand.

I learned the FSM stuff in college over two decades ago then learned Verilog and FPGA/ASIC design on the job so unfortunately, I don't have any good references. Feel free to ask more questions about the code and I'll do my best to answer them.